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append a table with offsets for the no-ack and slot timing code to wl.o
[openwrt/svn-archive/archive.git] / openwrt / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
2 --- linux.old/arch/mips/Makefile 2006-04-27 18:04:37.000000000 +0200
3 +++ linux.dev/arch/mips/Makefile 2006-04-27 19:24:19.000000000 +0200
4 @@ -726,6 +726,19 @@
5 endif
6
7 #
8 +# Broadcom BCM947XX variants
9 +#
10 +ifdef CONFIG_BCM947XX
11 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
12 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
13 +LOADADDR := 0x80001000
14 +
15 +zImage: vmlinux
16 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
17 +export LOADADDR
18 +endif
19 +
20 +#
21 # Choosing incompatible machines durings configuration will result in
22 # error messages during linking. Select a default linkscript if
23 # none has been choosen above.
24 @@ -778,6 +791,7 @@
25 $(MAKE) -C arch/$(ARCH)/tools clean
26 $(MAKE) -C arch/mips/baget clean
27 $(MAKE) -C arch/mips/lasat clean
28 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
29
30 archmrproper:
31 @$(MAKEBOOT) mrproper
32 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
33 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
34 +++ linux.dev/arch/mips/bcm947xx/Makefile 2006-05-02 17:46:22.000000000 +0200
35 @@ -0,0 +1,17 @@
36 +#
37 +# Makefile for the BCM947xx specific kernel interface routines
38 +# under Linux.
39 +#
40 +
41 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
42 +
43 +O_TARGET := bcm947xx.o
44 +
45 +export-objs := export.o
46 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
47 +obj-y += nvram.o nvram_linux.o sflash.o cfe_env.o
48 +obj-y += sbutils.o bcmutils.o bcmsrom.o hndchipc.o
49 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
50 +obj-y += export.o
51 +
52 +include $(TOPDIR)/Rules.make
53 diff -urN linux.old/arch/mips/bcm947xx/bcmsrom.c linux.dev/arch/mips/bcm947xx/bcmsrom.c
54 --- linux.old/arch/mips/bcm947xx/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
55 +++ linux.dev/arch/mips/bcm947xx/bcmsrom.c 2006-04-27 20:32:48.000000000 +0200
56 @@ -0,0 +1,1212 @@
57 +/*
58 + * Misc useful routines to access NIC SROM/OTP .
59 + *
60 + * Copyright 2006, Broadcom Corporation
61 + * All Rights Reserved.
62 + *
63 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
64 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
65 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
66 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
67 + * $Id: bcmsrom.c,v 1.1.1.14 2006/04/15 01:28:25 michael Exp $
68 + */
69 +
70 +#include <typedefs.h>
71 +#include <bcmdefs.h>
72 +#include <osl.h>
73 +#include <bcmutils.h>
74 +#include <bcmsrom.h>
75 +#include <bcmdevs.h>
76 +#include <bcmendian.h>
77 +#include <sbpcmcia.h>
78 +#include <pcicfg.h>
79 +#include <sbutils.h>
80 +#include <bcmnvram.h>
81 +
82 +/* debug/trace */
83 +#if defined(WLTEST)
84 +#define BS_ERROR(args) printf args
85 +#else
86 +#define BS_ERROR(args)
87 +#endif /* BCMDBG_ERR || WLTEST */
88 +
89 +#define VARS_MAX 4096 /* should be reduced */
90 +
91 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
92 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
93 +
94 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count);
95 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count);
96 +static int initvars_flash_sb(void *sbh, char **vars, uint *count);
97 +static int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count);
98 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
99 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
100 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
101 +static int sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords,
102 + bool check_crc);
103 +
104 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
105 +static int initvars_flash(osl_t *osh, char **vp, uint len, char *devpath);
106 +
107 +/*
108 + * Initialize local vars from the right source for this platform.
109 + * Return 0 on success, nonzero on error.
110 + */
111 +int
112 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, uint *count)
113 +{
114 + ASSERT(bustype == BUSTYPE(bustype));
115 + if (vars == NULL || count == NULL)
116 + return (0);
117 +
118 + switch (BUSTYPE(bustype)) {
119 + case SB_BUS:
120 + case JTAG_BUS:
121 + return initvars_flash_sb(sbh, vars, count);
122 +
123 + case PCI_BUS:
124 + ASSERT(curmap); /* can not be NULL */
125 + return initvars_srom_pci(sbh, curmap, vars, count);
126 +
127 + case PCMCIA_BUS:
128 + return initvars_cis_pcmcia(sbh, osh, vars, count);
129 +
130 +
131 + default:
132 + ASSERT(0);
133 + }
134 + return (-1);
135 +}
136 +
137 +/* support only 16-bit word read from srom */
138 +int
139 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
140 +{
141 + void *srom;
142 + uint i, off, nw;
143 +
144 + ASSERT(bustype == BUSTYPE(bustype));
145 +
146 + /* check input - 16-bit access only */
147 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
148 + return 1;
149 +
150 + off = byteoff / 2;
151 + nw = nbytes / 2;
152 +
153 + if (BUSTYPE(bustype) == PCI_BUS) {
154 + if (!curmap)
155 + return 1;
156 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
157 + if (sprom_read_pci(osh, srom, off, buf, nw, FALSE))
158 + return 1;
159 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
160 + for (i = 0; i < nw; i++) {
161 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
162 + return 1;
163 + }
164 + } else {
165 + return 1;
166 + }
167 +
168 + return 0;
169 +}
170 +
171 +/* support only 16-bit word write into srom */
172 +int
173 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
174 +{
175 + uint16 *srom;
176 + uint i, nw, crc_range;
177 + uint16 image[SPROM_SIZE];
178 + uint8 crc;
179 + volatile uint32 val32;
180 +
181 + ASSERT(bustype == BUSTYPE(bustype));
182 +
183 + /* check input - 16-bit access only */
184 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
185 + return 1;
186 +
187 + /* Are we writing the whole thing at once? */
188 + if ((byteoff == 0) &&
189 + ((nbytes == SPROM_SIZE) ||
190 + (nbytes == (SPROM_CRC_RANGE * 2)) ||
191 + (nbytes == (SROM4_WORDS * 2)))) {
192 + crc_range = nbytes;
193 + bcopy((void*)buf, (void*)image, nbytes);
194 + nw = nbytes / 2;
195 + } else {
196 + if ((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS))
197 + crc_range = SPROM_SIZE;
198 + else
199 + crc_range = SPROM_CRC_RANGE * 2; /* Tentative */
200 +
201 + nw = crc_range / 2;
202 + /* read first 64 words from srom */
203 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
204 + return 1;
205 + if (image[SROM4_SIGN] == SROM4_SIGNATURE) {
206 + crc_range = SROM4_WORDS;
207 + nw = crc_range / 2;
208 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
209 + return 1;
210 + }
211 + /* make changes */
212 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
213 + }
214 +
215 + /* calculate crc */
216 + htol16_buf(image, crc_range);
217 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
218 + ltoh16_buf(image, crc_range);
219 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
220 +
221 + if (BUSTYPE(bustype) == PCI_BUS) {
222 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
223 + /* enable writes to the SPROM */
224 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
225 + val32 |= SPROM_WRITEEN;
226 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
227 + bcm_mdelay(WRITE_ENABLE_DELAY);
228 + /* write srom */
229 + for (i = 0; i < nw; i++) {
230 + W_REG(osh, &srom[i], image[i]);
231 + bcm_mdelay(WRITE_WORD_DELAY);
232 + }
233 + /* disable writes to the SPROM */
234 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 &
235 + ~SPROM_WRITEEN);
236 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
237 + /* enable writes to the SPROM */
238 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
239 + return 1;
240 + bcm_mdelay(WRITE_ENABLE_DELAY);
241 + /* write srom */
242 + for (i = 0; i < nw; i++) {
243 + sprom_write_pcmcia(osh, (uint16)(i), image[i]);
244 + bcm_mdelay(WRITE_WORD_DELAY);
245 + }
246 + /* disable writes to the SPROM */
247 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
248 + return 1;
249 + } else {
250 + return 1;
251 + }
252 +
253 + bcm_mdelay(WRITE_ENABLE_DELAY);
254 + return 0;
255 +}
256 +
257 +
258 +static int
259 +srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count)
260 +{
261 + char eabuf[32];
262 + char *vp, *base;
263 + uint8 *cis, tup, tlen, sromrev = 1;
264 + int i, j;
265 + uint varsize;
266 + bool ag_init = FALSE;
267 + uint32 w32;
268 +
269 + ASSERT(vars);
270 + ASSERT(count);
271 +
272 + base = vp = MALLOC(osh, VARS_MAX);
273 + ASSERT(vp);
274 + if (!vp)
275 + return -2;
276 +
277 + while (ciscnt--) {
278 + cis = *pcis++;
279 + i = 0;
280 + do {
281 + tup = cis[i++];
282 + tlen = cis[i++];
283 + if ((i + tlen) >= CIS_SIZE)
284 + break;
285 +
286 + switch (tup) {
287 + case CISTPL_MANFID:
288 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
289 + vp++;
290 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
291 + vp++;
292 + break;
293 +
294 + case CISTPL_FUNCE:
295 + switch (cis[i]) {
296 + case LAN_NID:
297 + ASSERT(cis[i + 1] == 6);
298 + bcm_ether_ntoa((struct ether_addr *)&cis[i + 2], eabuf);
299 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
300 + vp++;
301 + break;
302 + case 1: /* SDIO Extended Data */
303 + vp += sprintf(vp, "sdmaxblk=%d",
304 + (cis[i + 13] << 8) | cis[i + 12]);
305 + vp++;
306 + break;
307 + }
308 + break;
309 +
310 + case CISTPL_CFTABLE:
311 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
312 + vp++;
313 + break;
314 +
315 + case CISTPL_BRCM_HNBU:
316 + switch (cis[i]) {
317 + case HNBU_SROMREV:
318 + sromrev = cis[i + 1];
319 + break;
320 +
321 + case HNBU_CHIPID:
322 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) +
323 + cis[i + 1]);
324 + vp++;
325 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) +
326 + cis[i + 3]);
327 + vp++;
328 + if (tlen == 7) {
329 + vp += sprintf(vp, "chiprev=%d",
330 + (cis[i + 6] << 8) + cis[i + 5]);
331 + vp++;
332 + }
333 + break;
334 +
335 + case HNBU_BOARDREV:
336 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
337 + vp++;
338 + break;
339 +
340 + case HNBU_AA:
341 + vp += sprintf(vp, "aa2g=%d", cis[i + 1]);
342 + vp++;
343 + break;
344 +
345 + case HNBU_AG:
346 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
347 + vp++;
348 + ag_init = TRUE;
349 + break;
350 +
351 + case HNBU_CC:
352 + ASSERT(sromrev == 1);
353 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
354 + vp++;
355 + break;
356 +
357 + case HNBU_PAPARMS:
358 + if (tlen == 2) {
359 + ASSERT(sromrev == 1);
360 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
361 + vp++;
362 + } else if (tlen >= 9) {
363 + if (tlen == 10) {
364 + ASSERT(sromrev == 2);
365 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
366 + vp++;
367 + } else
368 + ASSERT(tlen == 9);
369 +
370 + for (j = 0; j < 3; j++) {
371 + vp += sprintf(vp, "pa0b%d=%d", j,
372 + (cis[i + (j * 2) + 2] << 8) +
373 + cis[i + (j * 2) + 1]);
374 + vp++;
375 + }
376 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
377 + vp++;
378 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
379 + vp++;
380 + } else
381 + ASSERT(tlen >= 9);
382 + break;
383 +
384 + case HNBU_OEM:
385 + ASSERT(sromrev == 1);
386 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
387 + cis[i + 1], cis[i + 2],
388 + cis[i + 3], cis[i + 4],
389 + cis[i + 5], cis[i + 6],
390 + cis[i + 7], cis[i + 8]);
391 + vp++;
392 + break;
393 +
394 + case HNBU_BOARDFLAGS:
395 + w32 = (cis[i + 2] << 8) + cis[i + 1];
396 + if (tlen == 5)
397 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
398 + vp += sprintf(vp, "boardflags=0x%x", w32);
399 + vp++;
400 + break;
401 +
402 + case HNBU_LEDS:
403 + if (cis[i + 1] != 0xff) {
404 + vp += sprintf(vp, "ledbh0=%d", cis[i + 1]);
405 + vp++;
406 + }
407 + if (cis[i + 2] != 0xff) {
408 + vp += sprintf(vp, "ledbh1=%d", cis[i + 2]);
409 + vp++;
410 + }
411 + if (cis[i + 3] != 0xff) {
412 + vp += sprintf(vp, "ledbh2=%d", cis[i + 3]);
413 + vp++;
414 + }
415 + if (cis[i + 4] != 0xff) {
416 + vp += sprintf(vp, "ledbh3=%d", cis[i + 4]);
417 + vp++;
418 + }
419 + break;
420 +
421 + case HNBU_CCODE:
422 + {
423 + char str[3];
424 + ASSERT(sromrev > 1);
425 + str[0] = cis[i + 1];
426 + str[1] = cis[i + 2];
427 + str[2] = 0;
428 + vp += sprintf(vp, "ccode=%s", str);
429 + vp++;
430 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
431 + vp++;
432 + break;
433 + }
434 +
435 + case HNBU_CCKPO:
436 + ASSERT(sromrev > 2);
437 + vp += sprintf(vp, "cckpo=0x%x",
438 + (cis[i + 2] << 8) | cis[i + 1]);
439 + vp++;
440 + break;
441 +
442 + case HNBU_OFDMPO:
443 + ASSERT(sromrev > 2);
444 + vp += sprintf(vp, "ofdmpo=0x%x",
445 + (cis[i + 4] << 24) |
446 + (cis[i + 3] << 16) |
447 + (cis[i + 2] << 8) |
448 + cis[i + 1]);
449 + vp++;
450 + break;
451 + }
452 + break;
453 +
454 + }
455 + i += tlen;
456 + } while (tup != 0xff);
457 + }
458 +
459 + /* Set the srom version */
460 + vp += sprintf(vp, "sromrev=%d", sromrev);
461 + vp++;
462 +
463 + /* if there is no antenna gain field, set default */
464 + if (ag_init == FALSE) {
465 + ASSERT(sromrev == 1);
466 + vp += sprintf(vp, "ag0=%d", 0xff);
467 + vp++;
468 + }
469 +
470 + /* final nullbyte terminator */
471 + *vp++ = '\0';
472 + varsize = (uint)(vp - base);
473 +
474 + ASSERT((vp - base) < VARS_MAX);
475 +
476 + if (varsize == VARS_MAX) {
477 + *vars = base;
478 + } else {
479 + vp = MALLOC(osh, varsize);
480 + ASSERT(vp);
481 + if (vp)
482 + bcopy(base, vp, varsize);
483 + MFREE(osh, base, VARS_MAX);
484 + *vars = vp;
485 + if (!vp) {
486 + *count = 0;
487 + return -2;
488 + }
489 + }
490 + *count = varsize;
491 +
492 + return (0);
493 +}
494 +
495 +
496 +/* set PCMCIA sprom command register */
497 +static int
498 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
499 +{
500 + uint8 status = 0;
501 + uint wait_cnt = 1000;
502 +
503 + /* write sprom command register */
504 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
505 +
506 + /* wait status */
507 + while (wait_cnt--) {
508 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
509 + if (status & SROM_DONE)
510 + return 0;
511 + }
512 +
513 + return 1;
514 +}
515 +
516 +/* read a word from the PCMCIA srom */
517 +static int
518 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
519 +{
520 + uint8 addr_l, addr_h, data_l, data_h;
521 +
522 + addr_l = (uint8)((addr * 2) & 0xff);
523 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
524 +
525 + /* set address */
526 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
527 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
528 +
529 + /* do read */
530 + if (sprom_cmd_pcmcia(osh, SROM_READ))
531 + return 1;
532 +
533 + /* read data */
534 + data_h = data_l = 0;
535 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
536 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
537 +
538 + *data = (data_h << 8) | data_l;
539 + return 0;
540 +}
541 +
542 +/* write a word to the PCMCIA srom */
543 +static int
544 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
545 +{
546 + uint8 addr_l, addr_h, data_l, data_h;
547 +
548 + addr_l = (uint8)((addr * 2) & 0xff);
549 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
550 + data_l = (uint8)(data & 0xff);
551 + data_h = (uint8)((data >> 8) & 0xff);
552 +
553 + /* set address */
554 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
555 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
556 +
557 + /* write data */
558 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
559 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
560 +
561 + /* do write */
562 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
563 +}
564 +
565 +/*
566 + * Read in and validate sprom.
567 + * Return 0 on success, nonzero on error.
568 + */
569 +static int
570 +sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
571 +{
572 + int err = 0;
573 + uint i;
574 +
575 + /* read the sprom */
576 + for (i = 0; i < nwords; i++)
577 + buf[i] = R_REG(osh, &sprom[wordoff + i]);
578 +
579 + if (check_crc) {
580 + /* fixup the endianness so crc8 will pass */
581 + htol16_buf(buf, nwords * 2);
582 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
583 + err = 1;
584 + /* now correct the endianness of the byte array */
585 + ltoh16_buf(buf, nwords * 2);
586 + }
587 +
588 + return err;
589 +}
590 +
591 +/*
592 +* Create variable table from memory.
593 +* Return 0 on success, nonzero on error.
594 +*/
595 +static int
596 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
597 +{
598 + int c = (int)(end - start);
599 +
600 + /* do it only when there is more than just the null string */
601 + if (c > 1) {
602 + char *vp = MALLOC(osh, c);
603 + ASSERT(vp);
604 + if (!vp)
605 + return BCME_NOMEM;
606 + bcopy(start, vp, c);
607 + *vars = vp;
608 + *count = c;
609 + }
610 + else {
611 + *vars = NULL;
612 + *count = 0;
613 + }
614 +
615 + return 0;
616 +}
617 +
618 +/*
619 + * Find variables with <devpath> from flash. 'base' points to the beginning
620 + * of the table upon enter and to the end of the table upon exit when success.
621 + * Return 0 on success, nonzero on error.
622 + */
623 +static int
624 +initvars_flash(osl_t *osh, char **base, uint len, char *devpath)
625 +{
626 + char *vp = *base;
627 + char *flash;
628 + int err;
629 + char *s;
630 + uint l, dl, copy_len;
631 +
632 + /* allocate memory and read in flash */
633 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
634 + return BCME_NOMEM;
635 + if ((err = nvram_getall(flash, NVRAM_SPACE)))
636 + goto exit;
637 +
638 + /* grab vars with the <devpath> prefix in name */
639 + dl = strlen(devpath);
640 + for (s = flash; s && *s; s += l + 1) {
641 + l = strlen(s);
642 +
643 + /* skip non-matching variable */
644 + if (strncmp(s, devpath, dl))
645 + continue;
646 +
647 + /* is there enough room to copy? */
648 + copy_len = l - dl + 1;
649 + if (len < copy_len) {
650 + err = BCME_BUFTOOSHORT;
651 + goto exit;
652 + }
653 +
654 + /* no prefix, just the name=value */
655 + strcpy(vp, &s[dl]);
656 + vp += copy_len;
657 + len -= copy_len;
658 + }
659 +
660 + /* add null string as terminator */
661 + if (len < 1) {
662 + err = BCME_BUFTOOSHORT;
663 + goto exit;
664 + }
665 + *vp++ = '\0';
666 +
667 + *base = vp;
668 +
669 +exit: MFREE(osh, flash, NVRAM_SPACE);
670 + return err;
671 +}
672 +
673 +/*
674 + * Initialize nonvolatile variable table from flash.
675 + * Return 0 on success, nonzero on error.
676 + */
677 +static int
678 +initvars_flash_sb(void *sbh, char **vars, uint *count)
679 +{
680 + osl_t *osh = sb_osh(sbh);
681 + char devpath[SB_DEVPATH_BUFSZ];
682 + char *vp, *base;
683 + int err;
684 +
685 + ASSERT(vars);
686 + ASSERT(count);
687 +
688 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
689 + return err;
690 +
691 + base = vp = MALLOC(osh, VARS_MAX);
692 + ASSERT(vp);
693 + if (!vp)
694 + return BCME_NOMEM;
695 +
696 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
697 + goto err;
698 +
699 + err = initvars_table(osh, base, vp, vars, count);
700 +
701 +err: MFREE(osh, base, VARS_MAX);
702 + return err;
703 +}
704 +
705 +#ifdef WLTEST
706 +char mfgsromvars[256];
707 +char *defaultsromvars = "il0macaddr=00:11:22:33:44:51\0"
708 + "et0macaddr=00:11:22:33:44:52\0"
709 + "et1macaddr=00:11:22:33:44:53\0"
710 + "boardtype=0xffff\0"
711 + "boardrev=0x10\0"
712 + "boardflags=8\0"
713 + "sromrev=2\0"
714 + "aa2g=3";
715 +#define MFGSROM_DEFVARSLEN 147 /* default srom len */
716 +#endif /* WL_TEST */
717 +
718 +/*
719 + * Initialize nonvolatile variable table from sprom.
720 + * Return 0 on success, nonzero on error.
721 + */
722 +static int
723 +initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count)
724 +{
725 + uint16 w, *b;
726 + uint8 sromrev = 0;
727 + struct ether_addr ea;
728 + char eabuf[32];
729 + uint32 w32;
730 + int woff, i;
731 + char *vp, *base;
732 + osl_t *osh = sb_osh(sbh);
733 + bool flash = FALSE;
734 + char name[SB_DEVPATH_BUFSZ+16], *value;
735 + char devpath[SB_DEVPATH_BUFSZ];
736 + int err;
737 +
738 + /*
739 + * Apply CRC over SROM content regardless SROM is present or not,
740 + * and use variable <devpath>sromrev's existance in flash to decide
741 + * if we should return an error when CRC fails or read SROM variables
742 + * from flash.
743 + */
744 + b = MALLOC(osh, SROM_MAX);
745 + ASSERT(b);
746 + if (!b)
747 + return -2;
748 +
749 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
750 + 64, TRUE);
751 + if (err == 0) {
752 + /* srom is good and is rev < 4 */
753 + /* top word of sprom contains version and crc8 */
754 + sromrev = b[63] & 0xff;
755 + /* bcm4401 sroms misprogrammed */
756 + if (sromrev == 0x10)
757 + sromrev = 1;
758 + } else if (b[SROM4_SIGN] == SROM4_SIGNATURE) {
759 + /* If sromrev >= 4, read more */
760 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
761 + SROM4_WORDS, TRUE);
762 + sromrev = b[SROM4_WORDS - 1] & 0xff;
763 + }
764 +
765 + if (err) {
766 +#ifdef WLTEST
767 + BS_ERROR(("SROM Crc Error, so see if we could use a default\n"));
768 + w32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
769 + if (w32 & SPROM_OTPIN_USE) {
770 + BS_ERROR(("srom crc failed with OTP, use default vars....\n"));
771 + vp = base = mfgsromvars;
772 + if (sb_chip(sbh) == BCM4311_CHIP_ID) {
773 + BS_ERROR(("setting the devid to be 4311\n"));
774 + vp += sprintf(vp, "devid=0x4311");
775 + vp++;
776 + }
777 + bcopy(defaultsromvars, vp, MFGSROM_DEFVARSLEN);
778 + vp += MFGSROM_DEFVARSLEN;
779 + goto varsdone;
780 + } else {
781 + BS_ERROR(("srom crc failed with SPROM....\n"));
782 +#endif /* WLTEST */
783 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
784 + return err;
785 + sprintf(name, "%ssromrev", devpath);
786 + if (!(value = getvar(NULL, name)))
787 + return (-1);
788 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
789 + flash = TRUE;
790 +#ifdef WLTEST
791 + }
792 +#endif /* WLTEST */
793 + }
794 +
795 + /* srom version check */
796 + if (sromrev > 4)
797 + return (-2);
798 +
799 + ASSERT(vars);
800 + ASSERT(count);
801 +
802 + base = vp = MALLOC(osh, VARS_MAX);
803 + ASSERT(vp);
804 + if (!vp)
805 + return -2;
806 +
807 + /* read variables from flash */
808 + if (flash) {
809 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
810 + goto err;
811 + goto varsdone;
812 + }
813 +
814 + vp += sprintf(vp, "sromrev=%d", sromrev);
815 + vp++;
816 +
817 + if (sromrev >= 4) {
818 + uint path, pathbase;
819 + const uint pathbases[MAX_PATH] = {SROM4_PATH0, SROM4_PATH1,
820 + SROM4_PATH2, SROM4_PATH3};
821 +
822 + vp += sprintf(vp, "boardrev=%d", b[SROM4_BREV]);
823 + vp++;
824 +
825 + vp += sprintf(vp, "boardflags=%d", (b[SROM4_BFL1] << 16) | b[SROM4_BFL0]);
826 + vp++;
827 +
828 + vp += sprintf(vp, "boardflags2=%d", (b[SROM4_BFL3] << 16) | b[SROM4_BFL2]);
829 + vp++;
830 +
831 + /* The macaddr */
832 + ea.octet[0] = (b[SROM4_MACHI] >> 8) & 0xff;
833 + ea.octet[1] = b[SROM4_MACHI] & 0xff;
834 + ea.octet[2] = (b[SROM4_MACMID] >> 8) & 0xff;
835 + ea.octet[3] = b[SROM4_MACMID] & 0xff;
836 + ea.octet[4] = (b[SROM4_MACLO] >> 8) & 0xff;
837 + ea.octet[5] = b[SROM4_MACLO] & 0xff;
838 + bcm_ether_ntoa(&ea, eabuf);
839 + vp += sprintf(vp, "macaddr=%s", eabuf);
840 + vp++;
841 +
842 + w = b[SROM4_CCODE];
843 + if (w == 0)
844 + vp += sprintf(vp, "ccode=");
845 + else
846 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
847 + vp++;
848 + vp += sprintf(vp, "regrev=%d", b[SROM4_REGREV]);
849 + vp++;
850 +
851 + w = b[SROM4_LEDBH10];
852 + if ((w != 0) && (w != 0xffff)) {
853 + /* ledbh0 */
854 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
855 + vp++;
856 +
857 + /* ledbh1 */
858 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
859 + vp++;
860 + }
861 + w = b[SROM4_LEDBH32];
862 + if ((w != 0) && (w != 0xffff)) {
863 + /* ledbh2 */
864 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
865 + vp++;
866 +
867 + /* ledbh3 */
868 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
869 + vp++;
870 + }
871 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
872 + w = b[SROM4_LEDDC];
873 + w32 = ((uint32)((unsigned char)(w >> 8) & 0xff) << 24) | /* oncount */
874 + ((uint32)((unsigned char)(w & 0xff)) << 8); /* offcount */
875 + vp += sprintf(vp, "leddc=%d", w32);
876 + vp++;
877 +
878 + w = b[SROM4_AA];
879 + vp += sprintf(vp, "aa2g=%d", w & SROM4_AA2G_MASK);
880 + vp++;
881 + vp += sprintf(vp, "aa5g=%d", w >> SROM4_AA5G_SHIFT);
882 + vp++;
883 +
884 + w = b[SROM4_AG10];
885 + vp += sprintf(vp, "ag0=%d", w & 0xff);
886 + vp++;
887 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
888 + vp++;
889 + w = b[SROM4_AG32];
890 + vp += sprintf(vp, "ag2=%d", w & 0xff);
891 + vp++;
892 + vp += sprintf(vp, "ag3=%d", (w >> 8) & 0xff);
893 + vp++;
894 +
895 + /* Fixed power indices when power control is disabled */
896 + for (i = 0; i < 2; i++) {
897 + w = b[SROM4_TXPID2G + i];
898 + vp += sprintf(vp, "txpid2ga%d=%d", 2 * i, w & 0xff);
899 + vp++;
900 + vp += sprintf(vp, "txpid2ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
901 + vp++;
902 + w = b[SROM4_TXPID5G + i];
903 + vp += sprintf(vp, "txpid5ga%d=%d", 2 * i, w & 0xff);
904 + vp++;
905 + vp += sprintf(vp, "txpid5ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
906 + vp++;
907 + w = b[SROM4_TXPID5GL + i];
908 + vp += sprintf(vp, "txpid5gla%d=%d", 2 * i, w & 0xff);
909 + vp++;
910 + vp += sprintf(vp, "txpid5gla%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
911 + vp++;
912 + w = b[SROM4_TXPID5GH + i];
913 + vp += sprintf(vp, "txpid5gha%d=%d", 2 * i, w & 0xff);
914 + vp++;
915 + vp += sprintf(vp, "txpid5gha%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
916 + vp++;
917 + }
918 +
919 + /* Per path variables */
920 + for (path = 0; path < MAX_PATH; path++) {
921 + pathbase = pathbases[path];
922 + w = b[pathbase + SROM4_2G_ITT_MAXP];
923 + vp += sprintf(vp, "itt2ga%d=%d", path, w >> B2G_ITT_SHIFT);
924 + vp++;
925 + vp += sprintf(vp, "maxp2ga%d=%d", path, w & B2G_MAXP_MASK);
926 + vp++;
927 +
928 + for (i = 0; i < 4; i++) {
929 + vp += sprintf(vp, "pa2gw%da%d=%d", i, path,
930 + b[pathbase + SROM4_2G_PA + i]);
931 + vp++;
932 + }
933 +
934 + w = b[pathbase + SROM4_5G_ITT_MAXP];
935 + vp += sprintf(vp, "itt5ga%d=%d", path, w >> B5G_ITT_SHIFT);
936 + vp++;
937 + vp += sprintf(vp, "maxp5ga%d=%d", path, w & B5G_MAXP_MASK);
938 + vp++;
939 +
940 + w = b[pathbase + SROM4_5GLH_MAXP];
941 + vp += sprintf(vp, "maxp5lga%d=%d", path, w >> B5GL_MAXP_SHIFT);
942 + vp++;
943 + vp += sprintf(vp, "maxp5gha%d=%d", path, w & B5GH_MAXP_MASK);
944 + vp++;
945 +
946 + for (i = 0; i < 4; i++) {
947 + vp += sprintf(vp, "pa5gw%da%d=%d", i, path,
948 + b[pathbase + SROM4_5G_PA + i]);
949 + vp++;
950 + vp += sprintf(vp, "pa5glw%da%d=%d", i, path,
951 + b[pathbase + SROM4_5GL_PA + i]);
952 + vp++;
953 + vp += sprintf(vp, "pa5hgw%da%d=%d", i, path,
954 + b[pathbase + SROM4_5GH_PA + i]);
955 + vp++;
956 + }
957 + }
958 +
959 + vp += sprintf(vp, "cck2gpo=%d", b[SROM4_2G_CCKPO]);
960 + vp++;
961 +
962 + w32 = ((uint32)b[SROM4_2G_OFDMPO + 1] << 16) | b[SROM4_2G_OFDMPO];
963 + vp += sprintf(vp, "ofdm2gpo=%d", w32);
964 + vp++;
965 +
966 + w32 = ((uint32)b[SROM4_5G_OFDMPO + 1] << 16) | b[SROM4_5G_OFDMPO];
967 + vp += sprintf(vp, "ofdm5gpo=%d", w32);
968 + vp++;
969 +
970 + w32 = ((uint32)b[SROM4_5GL_OFDMPO + 1] << 16) | b[SROM4_5GL_OFDMPO];
971 + vp += sprintf(vp, "ofdm5glpo=%d", w32);
972 + vp++;
973 +
974 + w32 = ((uint32)b[SROM4_5GH_OFDMPO + 1] << 16) | b[SROM4_5GH_OFDMPO];
975 + vp += sprintf(vp, "ofdm5ghpo=%d", w32);
976 + vp++;
977 +
978 + for (i = 0; i < 8; i++) {
979 + vp += sprintf(vp, "mcs2gpo%d=%d", i, b[SROM4_2G_MCSPO]);
980 + vp++;
981 + vp += sprintf(vp, "mcs5gpo%d=%d", i, b[SROM4_5G_MCSPO]);
982 + vp++;
983 + vp += sprintf(vp, "mcs5glpo%d=%d", i, b[SROM4_5GL_MCSPO]);
984 + vp++;
985 + vp += sprintf(vp, "mcs5ghpo%d=%d", i, b[SROM4_5GH_MCSPO]);
986 + vp++;
987 + }
988 +
989 + vp += sprintf(vp, "ccdpo%d=%d", i, b[SROM4_CCDPO]);
990 + vp++;
991 + vp += sprintf(vp, "stbcpo%d=%d", i, b[SROM4_STBCPO]);
992 + vp++;
993 + vp += sprintf(vp, "bw40po%d=%d", i, b[SROM4_BW40PO]);
994 + vp++;
995 + vp += sprintf(vp, "bwduppo%d=%d", i, b[SROM4_BWDUPPO]);
996 + vp++;
997 +
998 + goto done;
999 + }
1000 + if (sromrev >= 3) {
1001 + /* New section takes over the 3th hardware function space */
1002 +
1003 + /* Words 22+23 are 11a (mid) ofdm power offsets */
1004 + w32 = ((uint32)b[23] << 16) | b[22];
1005 + vp += sprintf(vp, "ofdmapo=%d", w32);
1006 + vp++;
1007 +
1008 + /* Words 24+25 are 11a (low) ofdm power offsets */
1009 + w32 = ((uint32)b[25] << 16) | b[24];
1010 + vp += sprintf(vp, "ofdmalpo=%d", w32);
1011 + vp++;
1012 +
1013 + /* Words 26+27 are 11a (high) ofdm power offsets */
1014 + w32 = ((uint32)b[27] << 16) | b[26];
1015 + vp += sprintf(vp, "ofdmahpo=%d", w32);
1016 + vp++;
1017 +
1018 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
1019 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xff) << 24) | /* oncount */
1020 + ((uint32)((unsigned char)(b[21] & 0xff)) << 8); /* offcount */
1021 + vp += sprintf(vp, "leddc=%d", w32);
1022 +
1023 + vp++;
1024 + }
1025 +
1026 + if (sromrev >= 2) {
1027 + /* New section takes over the 4th hardware function space */
1028 +
1029 + /* Word 29 is max power 11a high/low */
1030 + w = b[29];
1031 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
1032 + vp++;
1033 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
1034 + vp++;
1035 +
1036 + /* Words 30-32 set the 11alow pa settings,
1037 + * 33-35 are the 11ahigh ones.
1038 + */
1039 + for (i = 0; i < 3; i++) {
1040 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
1041 + vp++;
1042 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
1043 + vp++;
1044 + }
1045 + w = b[59];
1046 + if (w == 0)
1047 + vp += sprintf(vp, "ccode=");
1048 + else
1049 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
1050 + vp++;
1051 +
1052 + }
1053 +
1054 + /* parameter section of sprom starts at byte offset 72 */
1055 + woff = 72/2;
1056 +
1057 + /* first 6 bytes are il0macaddr */
1058 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1059 + ea.octet[1] = b[woff] & 0xff;
1060 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1061 + ea.octet[3] = b[woff+1] & 0xff;
1062 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1063 + ea.octet[5] = b[woff+2] & 0xff;
1064 + woff += 3;
1065 + bcm_ether_ntoa(&ea, eabuf);
1066 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
1067 + vp++;
1068 +
1069 + /* next 6 bytes are et0macaddr */
1070 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1071 + ea.octet[1] = b[woff] & 0xff;
1072 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1073 + ea.octet[3] = b[woff+1] & 0xff;
1074 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1075 + ea.octet[5] = b[woff+2] & 0xff;
1076 + woff += 3;
1077 + bcm_ether_ntoa(&ea, eabuf);
1078 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
1079 + vp++;
1080 +
1081 + /* next 6 bytes are et1macaddr */
1082 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1083 + ea.octet[1] = b[woff] & 0xff;
1084 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1085 + ea.octet[3] = b[woff+1] & 0xff;
1086 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1087 + ea.octet[5] = b[woff+2] & 0xff;
1088 + woff += 3;
1089 + bcm_ether_ntoa(&ea, eabuf);
1090 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
1091 + vp++;
1092 +
1093 + /*
1094 + * Enet phy settings one or two singles or a dual
1095 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
1096 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
1097 + * Bit 14 : Mdio for enet0
1098 + * Bit 15 : Mdio for enet1
1099 + */
1100 + w = b[woff];
1101 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
1102 + vp++;
1103 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
1104 + vp++;
1105 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
1106 + vp++;
1107 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
1108 + vp++;
1109 +
1110 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
1111 + w = b[46];
1112 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
1113 + vp++;
1114 +
1115 + if (sromrev > 1)
1116 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
1117 + else
1118 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
1119 + vp++;
1120 +
1121 + vp += sprintf(vp, "aa2g=%d", (w >> 12) & 0x3);
1122 + vp++;
1123 +
1124 + vp += sprintf(vp, "aa5g=%d", (w >> 14) & 0x3);
1125 + vp++;
1126 +
1127 + /* Words 47-49 set the (wl) pa settings */
1128 + woff = 47;
1129 +
1130 + for (i = 0; i < 3; i++) {
1131 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
1132 + vp++;
1133 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
1134 + vp++;
1135 + }
1136 +
1137 + /*
1138 + * Words 50-51 set the customer-configured wl led behavior.
1139 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
1140 + * LED behavior values defined in wlioctl.h .
1141 + */
1142 + w = b[50];
1143 + if ((w != 0) && (w != 0xffff)) {
1144 + /* ledbh0 */
1145 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
1146 + vp++;
1147 +
1148 + /* ledbh1 */
1149 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
1150 + vp++;
1151 + }
1152 + w = b[51];
1153 + if ((w != 0) && (w != 0xffff)) {
1154 + /* ledbh2 */
1155 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
1156 + vp++;
1157 +
1158 + /* ledbh */
1159 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
1160 + vp++;
1161 + }
1162 +
1163 + /* Word 52 is max power 0/1 */
1164 + w = b[52];
1165 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
1166 + vp++;
1167 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
1168 + vp++;
1169 +
1170 + /* Word 56 is idle tssi target 0/1 */
1171 + w = b[56];
1172 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
1173 + vp++;
1174 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
1175 + vp++;
1176 +
1177 + /* Word 57 is boardflags, if not programmed make it zero */
1178 + w32 = (uint32)b[57];
1179 + if (w32 == 0xffff) w32 = 0;
1180 + if (sromrev > 1) {
1181 + /* Word 28 is the high bits of boardflags */
1182 + w32 |= (uint32)b[28] << 16;
1183 + }
1184 + vp += sprintf(vp, "boardflags=%d", w32);
1185 + vp++;
1186 +
1187 + /* Word 58 is antenna gain 0/1 */
1188 + w = b[58];
1189 + vp += sprintf(vp, "ag0=%d", w & 0xff);
1190 + vp++;
1191 +
1192 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
1193 + vp++;
1194 +
1195 + if (sromrev == 1) {
1196 + /* set the oem string */
1197 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
1198 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
1199 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
1200 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
1201 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
1202 + vp++;
1203 + } else if (sromrev == 2) {
1204 + /* Word 60 OFDM tx power offset from CCK level */
1205 + /* OFDM Power Offset - opo */
1206 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
1207 + vp++;
1208 + } else {
1209 + /* Word 60: cck power offsets */
1210 + vp += sprintf(vp, "cckpo=%d", b[60]);
1211 + vp++;
1212 +
1213 + /* Words 61+62: 11g ofdm power offsets */
1214 + w32 = ((uint32)b[62] << 16) | b[61];
1215 + vp += sprintf(vp, "ofdmgpo=%d", w32);
1216 + vp++;
1217 + }
1218 +
1219 + /* final nullbyte terminator */
1220 +done: *vp++ = '\0';
1221 +
1222 + ASSERT((vp - base) <= VARS_MAX);
1223 +
1224 +varsdone:
1225 + err = initvars_table(osh, base, vp, vars, count);
1226 +
1227 +err:
1228 +#ifdef WLTEST
1229 + if (base != mfgsromvars)
1230 +#endif
1231 + MFREE(osh, base, VARS_MAX);
1232 + MFREE(osh, b, SROM_MAX);
1233 + return err;
1234 +}
1235 +
1236 +/*
1237 + * Read the cis and call parsecis to initialize the vars.
1238 + * Return 0 on success, nonzero on error.
1239 + */
1240 +static int
1241 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count)
1242 +{
1243 + uint8 *cis = NULL;
1244 + int rc;
1245 + uint data_sz;
1246 +
1247 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
1248 +
1249 + if ((cis = MALLOC(osh, data_sz)) == NULL)
1250 + return (-2);
1251 +
1252 + if (sb_pcmciarev(sbh) == 1) {
1253 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
1254 + MFREE(osh, cis, data_sz);
1255 + return (-1);
1256 + }
1257 + /* fix up endianess for 16-bit data vs 8-bit parsing */
1258 + ltoh16_buf((uint16 *)cis, data_sz);
1259 + } else
1260 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
1261 +
1262 + rc = srom_parsecis(osh, &cis, 1, vars, count);
1263 +
1264 + MFREE(osh, cis, data_sz);
1265 +
1266 + return (rc);
1267 +}
1268 +
1269 diff -urN linux.old/arch/mips/bcm947xx/bcmutils.c linux.dev/arch/mips/bcm947xx/bcmutils.c
1270 --- linux.old/arch/mips/bcm947xx/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
1271 +++ linux.dev/arch/mips/bcm947xx/bcmutils.c 2006-04-28 00:34:02.000000000 +0200
1272 @@ -0,0 +1,247 @@
1273 +/*
1274 + * Misc useful OS-independent routines.
1275 + *
1276 + * Copyright 2006, Broadcom Corporation
1277 + * All Rights Reserved.
1278 + *
1279 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1280 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1281 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1282 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1283 + * $Id: bcmutils.c,v 1.1.1.12 2006/02/27 03:43:16 honor Exp $
1284 + */
1285 +
1286 +#include <typedefs.h>
1287 +#include <bcmdefs.h>
1288 +#include <stdarg.h>
1289 +#include <bcmutils.h>
1290 +#include <osl.h>
1291 +#include <sbutils.h>
1292 +#include <bcmnvram.h>
1293 +#include <bcmendian.h>
1294 +#include <bcmdevs.h>
1295 +
1296 +unsigned char bcm_ctype[] = {
1297 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
1298 + _BCM_C, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C,
1299 + _BCM_C, /* 8-15 */
1300 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
1301 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
1302 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
1303 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
1304 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
1305 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
1306 + _BCM_P, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X,
1307 + _BCM_U|_BCM_X, _BCM_U, /* 64-71 */
1308 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
1309 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
1310 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
1311 + _BCM_P, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X,
1312 + _BCM_L|_BCM_X, _BCM_L, /* 96-103 */
1313 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
1314 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
1315 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
1316 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 128-143 */
1317 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 144-159 */
1318 + _BCM_S|_BCM_SP, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1319 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 160-175 */
1320 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1321 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 176-191 */
1322 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,
1323 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, /* 192-207 */
1324 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_P, _BCM_U, _BCM_U, _BCM_U,
1325 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_L, /* 208-223 */
1326 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,
1327 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, /* 224-239 */
1328 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_P, _BCM_L, _BCM_L, _BCM_L,
1329 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L /* 240-255 */
1330 +};
1331 +
1332 +
1333 +ulong
1334 +bcm_strtoul(char *cp, char **endp, uint base)
1335 +{
1336 + ulong result, value;
1337 + bool minus;
1338 +
1339 + minus = FALSE;
1340 +
1341 + while (bcm_isspace(*cp))
1342 + cp++;
1343 +
1344 + if (cp[0] == '+')
1345 + cp++;
1346 + else if (cp[0] == '-') {
1347 + minus = TRUE;
1348 + cp++;
1349 + }
1350 +
1351 + if (base == 0) {
1352 + if (cp[0] == '0') {
1353 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
1354 + base = 16;
1355 + cp = &cp[2];
1356 + } else {
1357 + base = 8;
1358 + cp = &cp[1];
1359 + }
1360 + } else
1361 + base = 10;
1362 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
1363 + cp = &cp[2];
1364 + }
1365 +
1366 + result = 0;
1367 +
1368 + while (bcm_isxdigit(*cp) &&
1369 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
1370 + result = result*base + value;
1371 + cp++;
1372 + }
1373 +
1374 + if (minus)
1375 + result = (ulong)(result * -1);
1376 +
1377 + if (endp)
1378 + *endp = (char *)cp;
1379 +
1380 + return (result);
1381 +}
1382 +
1383 +uchar
1384 +bcm_toupper(uchar c)
1385 +{
1386 + if (bcm_islower(c))
1387 + c -= 'a'-'A';
1388 + return (c);
1389 +}
1390 +
1391 +char*
1392 +bcm_ether_ntoa(struct ether_addr *ea, char *buf)
1393 +{
1394 + sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
1395 + ea->octet[0]&0xff, ea->octet[1]&0xff, ea->octet[2]&0xff,
1396 + ea->octet[3]&0xff, ea->octet[4]&0xff, ea->octet[5]&0xff);
1397 + return (buf);
1398 +}
1399 +
1400 +
1401 +/*
1402 + * Search the name=value vars for a specific one and return its value.
1403 + * Returns NULL if not found.
1404 + */
1405 +char*
1406 +getvar(char *vars, char *name)
1407 +{
1408 + char *s;
1409 + int len;
1410 +
1411 + len = strlen(name);
1412 +
1413 + /* first look in vars[] */
1414 + for (s = vars; s && *s;) {
1415 + /* CSTYLED */
1416 + if ((memcmp(s, name, len) == 0) && (s[len] == '='))
1417 + return (&s[len+1]);
1418 +
1419 + while (*s++)
1420 + ;
1421 + }
1422 +
1423 + /* then query nvram */
1424 + return (nvram_get(name));
1425 +}
1426 +
1427 +/*
1428 + * Search the vars for a specific one and return its value as
1429 + * an integer. Returns 0 if not found.
1430 + */
1431 +int
1432 +getintvar(char *vars, char *name)
1433 +{
1434 + char *val;
1435 +
1436 + if ((val = getvar(vars, name)) == NULL)
1437 + return (0);
1438 +
1439 + return (bcm_strtoul(val, NULL, 0));
1440 +}
1441 +
1442 +
1443 +/*******************************************************************************
1444 + * crc8
1445 + *
1446 + * Computes a crc8 over the input data using the polynomial:
1447 + *
1448 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
1449 + *
1450 + * The caller provides the initial value (either CRC8_INIT_VALUE
1451 + * or the previous returned value) to allow for processing of
1452 + * discontiguous blocks of data. When generating the CRC the
1453 + * caller is responsible for complementing the final return value
1454 + * and inserting it into the byte stream. When checking, a final
1455 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
1456 + *
1457 + * Reference: Dallas Semiconductor Application Note 27
1458 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1459 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1460 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1461 + *
1462 + * ****************************************************************************
1463 + */
1464 +
1465 +static uint8 crc8_table[256] = {
1466 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
1467 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
1468 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
1469 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
1470 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
1471 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
1472 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
1473 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
1474 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
1475 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
1476 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
1477 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
1478 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
1479 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
1480 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
1481 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
1482 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
1483 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
1484 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
1485 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
1486 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
1487 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
1488 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
1489 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
1490 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
1491 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
1492 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
1493 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
1494 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
1495 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
1496 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
1497 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
1498 +};
1499 +
1500 +#define CRC_INNER_LOOP(n, c, x) \
1501 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
1502 +
1503 +uint8
1504 +hndcrc8(
1505 + uint8 *pdata, /* pointer to array of data to process */
1506 + uint nbytes, /* number of input data bytes to process */
1507 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
1508 +)
1509 +{
1510 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
1511 + * to avoid the undefined and unnecessary (uint8 >> 8) operation.
1512 + */
1513 + while (nbytes-- > 0)
1514 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
1515 +
1516 + return crc;
1517 +}
1518 +
1519 +
1520 diff -urN linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
1521 --- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
1522 +++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2006-04-27 19:24:19.000000000 +0200
1523 @@ -0,0 +1,234 @@
1524 +/*
1525 + * NVRAM variable manipulation (Linux kernel half)
1526 + *
1527 + * Copyright 2001-2003, Broadcom Corporation
1528 + * All Rights Reserved.
1529 + *
1530 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1531 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1532 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1533 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1534 + *
1535 + * $Id$
1536 + */
1537 +
1538 +#include <linux/config.h>
1539 +#include <linux/init.h>
1540 +#include <linux/module.h>
1541 +#include <linux/kernel.h>
1542 +#include <linux/string.h>
1543 +#include <asm/io.h>
1544 +#include <asm/uaccess.h>
1545 +
1546 +#include <typedefs.h>
1547 +#include <osl.h>
1548 +#include <bcmendian.h>
1549 +#include <bcmutils.h>
1550 +
1551 +#define NVRAM_SIZE (0x1ff0)
1552 +static char _nvdata[NVRAM_SIZE] __initdata;
1553 +static char _valuestr[256] __initdata;
1554 +
1555 +/*
1556 + * TLV types. These codes are used in the "type-length-value"
1557 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
1558 + *
1559 + * The layout of the flash/nvram is as follows:
1560 + *
1561 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
1562 + *
1563 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
1564 + * The "length" field marks the length of the data section, not
1565 + * including the type and length fields.
1566 + *
1567 + * Environment variables are stored as follows:
1568 + *
1569 + * <type_env> <length> <flags> <name> = <value>
1570 + *
1571 + * If bit 0 (low bit) is set, the length is an 8-bit value.
1572 + * If bit 0 (low bit) is clear, the length is a 16-bit value
1573 + *
1574 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
1575 + * indicates the size of the length field.
1576 + *
1577 + * Flags are from the constants below:
1578 + *
1579 + */
1580 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
1581 +#define ENV_LENGTH_8BITS 0x01
1582 +
1583 +#define ENV_TYPE_USER 0x80
1584 +
1585 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
1586 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
1587 +
1588 +/*
1589 + * The actual TLV types we support
1590 + */
1591 +
1592 +#define ENV_TLV_TYPE_END 0x00
1593 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
1594 +
1595 +/*
1596 + * Environment variable flags
1597 + */
1598 +
1599 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
1600 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
1601 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
1602 +
1603 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
1604 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
1605 +
1606 +
1607 +/* *********************************************************************
1608 + * _nvram_read(buffer,offset,length)
1609 + *
1610 + * Read data from the NVRAM device
1611 + *
1612 + * Input parameters:
1613 + * buffer - destination buffer
1614 + * offset - offset of data to read
1615 + * length - number of bytes to read
1616 + *
1617 + * Return value:
1618 + * number of bytes read, or <0 if error occured
1619 + ********************************************************************* */
1620 +static int
1621 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
1622 +{
1623 + int i;
1624 + if (offset > NVRAM_SIZE)
1625 + return -1;
1626 +
1627 + for ( i = 0; i < length; i++) {
1628 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
1629 + }
1630 + return length;
1631 +}
1632 +
1633 +
1634 +static char*
1635 +_strnchr(const char *dest,int c,size_t cnt)
1636 +{
1637 + while (*dest && (cnt > 0)) {
1638 + if (*dest == c) return (char *) dest;
1639 + dest++;
1640 + cnt--;
1641 + }
1642 + return NULL;
1643 +}
1644 +
1645 +
1646 +
1647 +/*
1648 + * Core support API: Externally visible.
1649 + */
1650 +
1651 +/*
1652 + * Get the value of an NVRAM variable
1653 + * @param name name of variable to get
1654 + * @return value of variable or NULL if undefined
1655 + */
1656 +
1657 +char*
1658 +cfe_env_get(unsigned char *nv_buf, char* name)
1659 +{
1660 + int size;
1661 + unsigned char *buffer;
1662 + unsigned char *ptr;
1663 + unsigned char *envval;
1664 + unsigned int reclen;
1665 + unsigned int rectype;
1666 + int offset;
1667 + int flg;
1668 +
1669 + size = NVRAM_SIZE;
1670 + buffer = &_nvdata[0];
1671 +
1672 + ptr = buffer;
1673 + offset = 0;
1674 +
1675 + /* Read the record type and length */
1676 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1677 + goto error;
1678 + }
1679 +
1680 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1681 +
1682 + /* Adjust pointer for TLV type */
1683 + rectype = *(ptr);
1684 + offset++;
1685 + size--;
1686 +
1687 + /*
1688 + * Read the length. It can be either 1 or 2 bytes
1689 + * depending on the code
1690 + */
1691 + if (rectype & ENV_LENGTH_8BITS) {
1692 + /* Read the record type and length - 8 bits */
1693 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1694 + goto error;
1695 + }
1696 + reclen = *(ptr);
1697 + size--;
1698 + offset++;
1699 + }
1700 + else {
1701 + /* Read the record type and length - 16 bits, MSB first */
1702 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1703 + goto error;
1704 + }
1705 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1706 + size -= 2;
1707 + offset += 2;
1708 + }
1709 +
1710 + if (reclen > size)
1711 + break; /* should not happen, bad NVRAM */
1712 +
1713 + switch (rectype) {
1714 + case ENV_TLV_TYPE_ENV:
1715 + /* Read the TLV data */
1716 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1717 + goto error;
1718 + flg = *ptr++;
1719 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1720 + if (envval) {
1721 + *envval++ = '\0';
1722 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1723 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1724 +#if 0
1725 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1726 +#endif
1727 + if(!strcmp(ptr, name)){
1728 + return _valuestr;
1729 + }
1730 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1731 + return _valuestr;
1732 + }
1733 + break;
1734 +
1735 + default:
1736 + /* Unknown TLV type, skip it. */
1737 + break;
1738 + }
1739 +
1740 + /*
1741 + * Advance to next TLV
1742 + */
1743 +
1744 + size -= (int)reclen;
1745 + offset += reclen;
1746 +
1747 + /* Read the next record type */
1748 + ptr = buffer;
1749 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1750 + goto error;
1751 + }
1752 +
1753 +error:
1754 + return NULL;
1755 +
1756 +}
1757 +
1758 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
1759 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
1760 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2006-04-27 19:24:19.000000000 +0200
1761 @@ -0,0 +1,33 @@
1762 +#
1763 +# Makefile for Broadcom BCM947XX boards
1764 +#
1765 +# Copyright 2001-2003, Broadcom Corporation
1766 +# All Rights Reserved.
1767 +#
1768 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1769 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1770 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1771 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1772 +#
1773 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
1774 +#
1775 +
1776 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
1777 +SYSTEM ?= $(TOPDIR)/vmlinux
1778 +
1779 +all: vmlinuz
1780 +
1781 +# Don't build dependencies, this may die if $(CC) isn't gcc
1782 +dep:
1783 +
1784 +# Create a gzipped version named vmlinuz for compatibility
1785 +vmlinuz: piggy
1786 + gzip -c9 $< > $@
1787 +
1788 +piggy: $(SYSTEM)
1789 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
1790 +
1791 +mrproper: clean
1792 +
1793 +clean:
1794 + rm -f vmlinuz piggy
1795 diff -urN linux.old/arch/mips/bcm947xx/export.c linux.dev/arch/mips/bcm947xx/export.c
1796 --- linux.old/arch/mips/bcm947xx/export.c 1970-01-01 01:00:00.000000000 +0100
1797 +++ linux.dev/arch/mips/bcm947xx/export.c 2006-04-28 02:57:34.000000000 +0200
1798 @@ -0,0 +1,62 @@
1799 +#include <linux/module.h>
1800 +
1801 +#define _export(n) \
1802 + void n(void); \
1803 + EXPORT_SYMBOL(n);
1804 +
1805 +_export(bcm947xx_sbh)
1806 +
1807 +_export(sb_attach)
1808 +_export(sb_boardtype)
1809 +_export(sb_boardvendor)
1810 +_export(sb_btcgpiowar)
1811 +_export(sb_bus)
1812 +_export(sb_chip)
1813 +_export(sb_chiprev)
1814 +_export(sb_chipcrev)
1815 +_export(sb_chippkg)
1816 +_export(sb_clkctl_clk)
1817 +_export(sb_clkctl_fast_pwrup_delay)
1818 +_export(sb_clkctl_init)
1819 +_export(sb_clkctl_xtal)
1820 +_export(sb_core_disable)
1821 +_export(sb_core_reset)
1822 +_export(sb_core_tofixup)
1823 +_export(sb_coreflags)
1824 +_export(sb_coreflagshi)
1825 +_export(sb_coreidx)
1826 +_export(sb_corerev)
1827 +_export(sb_coreunit)
1828 +_export(sb_detach)
1829 +_export(sb_deviceremoved)
1830 +_export(sb_gpiocontrol)
1831 +_export(sb_gpioled)
1832 +_export(sb_gpioin)
1833 +_export(sb_gpioout)
1834 +_export(sb_gpioouten)
1835 +_export(sb_gpiotimerval)
1836 +_export(sb_iscoreup)
1837 +_export(sb_pci_setup)
1838 +_export(sb_pcirev)
1839 +_export(sb_pcmcia_init)
1840 +_export(sb_pcmciarev)
1841 +_export(sb_register_intr_callback)
1842 +_export(sb_setcore)
1843 +_export(sb_war16165)
1844 +_export(sb_osh)
1845 +
1846 +_export(getvar)
1847 +_export(getintvar)
1848 +_export(bcm_strtoul)
1849 +_export(bcm_ctype)
1850 +_export(bcm_toupper)
1851 +_export(bcm_ether_ntoa)
1852 +
1853 +_export(nvram_get)
1854 +_export(nvram_getall)
1855 +_export(nvram_set)
1856 +_export(nvram_unset)
1857 +_export(nvram_commit)
1858 +
1859 +_export(srom_read)
1860 +_export(srom_write)
1861 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
1862 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
1863 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2006-04-27 19:24:19.000000000 +0200
1864 @@ -0,0 +1,15 @@
1865 +#
1866 +# Makefile for the BCM947xx specific kernel interface routines
1867 +# under Linux.
1868 +#
1869 +
1870 +.S.s:
1871 + $(CPP) $(AFLAGS) $< -o $*.s
1872 +.S.o:
1873 + $(CC) $(AFLAGS) -c $< -o $*.o
1874 +
1875 +O_TARGET := brcm.o
1876 +
1877 +obj-y := int-handler.o irq.o
1878 +
1879 +include $(TOPDIR)/Rules.make
1880 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
1881 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
1882 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2006-04-27 19:24:19.000000000 +0200
1883 @@ -0,0 +1,51 @@
1884 +/*
1885 + * Generic interrupt handler for Broadcom MIPS boards
1886 + *
1887 + * Copyright 2004, Broadcom Corporation
1888 + * All Rights Reserved.
1889 + *
1890 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1891 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1892 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1893 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1894 + *
1895 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
1896 + */
1897 +
1898 +#include <linux/config.h>
1899 +
1900 +#include <asm/asm.h>
1901 +#include <asm/mipsregs.h>
1902 +#include <asm/regdef.h>
1903 +#include <asm/stackframe.h>
1904 +
1905 +/*
1906 + * MIPS IRQ Source
1907 + * -------- ------
1908 + * 0 Software (ignored)
1909 + * 1 Software (ignored)
1910 + * 2 Combined hardware interrupt (hw0)
1911 + * 3 Hardware
1912 + * 4 Hardware
1913 + * 5 Hardware
1914 + * 6 Hardware
1915 + * 7 R4k timer
1916 + */
1917 +
1918 + .text
1919 + .set noreorder
1920 + .set noat
1921 + .align 5
1922 + NESTED(brcmIRQ, PT_SIZE, sp)
1923 + SAVE_ALL
1924 + CLI
1925 + .set at
1926 + .set noreorder
1927 +
1928 + jal brcm_irq_dispatch
1929 + move a0, sp
1930 +
1931 + j ret_from_irq
1932 + nop
1933 +
1934 + END(brcmIRQ)
1935 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
1936 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
1937 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2006-04-27 19:24:19.000000000 +0200
1938 @@ -0,0 +1,130 @@
1939 +/*
1940 + * Generic interrupt control functions for Broadcom MIPS boards
1941 + *
1942 + * Copyright 2004, Broadcom Corporation
1943 + * All Rights Reserved.
1944 + *
1945 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1946 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1947 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1948 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1949 + *
1950 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
1951 + */
1952 +
1953 +#include <linux/config.h>
1954 +#include <linux/init.h>
1955 +#include <linux/kernel.h>
1956 +#include <linux/types.h>
1957 +#include <linux/interrupt.h>
1958 +#include <linux/irq.h>
1959 +
1960 +#include <asm/irq.h>
1961 +#include <asm/mipsregs.h>
1962 +#include <asm/gdb-stub.h>
1963 +
1964 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1965 +
1966 +extern asmlinkage void brcmIRQ(void);
1967 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
1968 +
1969 +void
1970 +brcm_irq_dispatch(struct pt_regs *regs)
1971 +{
1972 + u32 cause;
1973 +
1974 + cause = read_c0_cause() &
1975 + read_c0_status() &
1976 + CAUSEF_IP;
1977 +
1978 +#ifdef CONFIG_KERNPROF
1979 + change_c0_status(cause | 1, 1);
1980 +#else
1981 + clear_c0_status(cause);
1982 +#endif
1983 +
1984 + if (cause & CAUSEF_IP7)
1985 + do_IRQ(7, regs);
1986 + if (cause & CAUSEF_IP2)
1987 + do_IRQ(2, regs);
1988 + if (cause & CAUSEF_IP3)
1989 + do_IRQ(3, regs);
1990 + if (cause & CAUSEF_IP4)
1991 + do_IRQ(4, regs);
1992 + if (cause & CAUSEF_IP5)
1993 + do_IRQ(5, regs);
1994 + if (cause & CAUSEF_IP6)
1995 + do_IRQ(6, regs);
1996 +}
1997 +
1998 +static void
1999 +enable_brcm_irq(unsigned int irq)
2000 +{
2001 + if (irq < 8)
2002 + set_c0_status(1 << (irq + 8));
2003 + else
2004 + set_c0_status(IE_IRQ0);
2005 +}
2006 +
2007 +static void
2008 +disable_brcm_irq(unsigned int irq)
2009 +{
2010 + if (irq < 8)
2011 + clear_c0_status(1 << (irq + 8));
2012 + else
2013 + clear_c0_status(IE_IRQ0);
2014 +}
2015 +
2016 +static void
2017 +ack_brcm_irq(unsigned int irq)
2018 +{
2019 + /* Already done in brcm_irq_dispatch */
2020 +}
2021 +
2022 +static unsigned int
2023 +startup_brcm_irq(unsigned int irq)
2024 +{
2025 + enable_brcm_irq(irq);
2026 +
2027 + return 0; /* never anything pending */
2028 +}
2029 +
2030 +static void
2031 +end_brcm_irq(unsigned int irq)
2032 +{
2033 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
2034 + enable_brcm_irq(irq);
2035 +}
2036 +
2037 +static struct hw_interrupt_type brcm_irq_type = {
2038 + typename: "MIPS",
2039 + startup: startup_brcm_irq,
2040 + shutdown: disable_brcm_irq,
2041 + enable: enable_brcm_irq,
2042 + disable: disable_brcm_irq,
2043 + ack: ack_brcm_irq,
2044 + end: end_brcm_irq,
2045 + NULL
2046 +};
2047 +
2048 +void __init
2049 +init_IRQ(void)
2050 +{
2051 + int i;
2052 +
2053 + for (i = 0; i < NR_IRQS; i++) {
2054 + irq_desc[i].status = IRQ_DISABLED;
2055 + irq_desc[i].action = 0;
2056 + irq_desc[i].depth = 1;
2057 + irq_desc[i].handler = &brcm_irq_type;
2058 + }
2059 +
2060 + set_except_vector(0, brcmIRQ);
2061 + change_c0_status(ST0_IM, ALLINTS);
2062 +
2063 +#ifdef CONFIG_REMOTE_DEBUG
2064 + printk("Breaking into debugger...\n");
2065 + set_debug_traps();
2066 + breakpoint();
2067 +#endif
2068 +}
2069 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
2070 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
2071 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2006-04-27 23:09:33.000000000 +0200
2072 @@ -0,0 +1,159 @@
2073 +/*
2074 + * GPIO char driver
2075 + *
2076 + * Copyright 2005, Broadcom Corporation
2077 + * All Rights Reserved.
2078 + *
2079 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2080 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2081 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2082 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2083 + *
2084 + * $Id$
2085 + */
2086 +
2087 +#include <linux/module.h>
2088 +#include <linux/init.h>
2089 +#include <linux/fs.h>
2090 +#include <linux/miscdevice.h>
2091 +#include <asm/uaccess.h>
2092 +
2093 +#include <typedefs.h>
2094 +#include <osl.h>
2095 +#include <bcmutils.h>
2096 +#include <sbutils.h>
2097 +#include <bcmdevs.h>
2098 +
2099 +static sb_t *gpio_sbh;
2100 +static int gpio_major;
2101 +static devfs_handle_t gpio_dir;
2102 +static struct {
2103 + char *name;
2104 + devfs_handle_t handle;
2105 +} gpio_file[] = {
2106 + { "in", NULL },
2107 + { "out", NULL },
2108 + { "outen", NULL },
2109 + { "control", NULL }
2110 +};
2111 +
2112 +static int
2113 +gpio_open(struct inode *inode, struct file * file)
2114 +{
2115 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
2116 + return -ENODEV;
2117 +
2118 + MOD_INC_USE_COUNT;
2119 + return 0;
2120 +}
2121 +
2122 +static int
2123 +gpio_release(struct inode *inode, struct file * file)
2124 +{
2125 + MOD_DEC_USE_COUNT;
2126 + return 0;
2127 +}
2128 +
2129 +static ssize_t
2130 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
2131 +{
2132 + u32 val;
2133 +
2134 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2135 + case 0:
2136 + val = sb_gpioin(gpio_sbh);
2137 + break;
2138 + case 1:
2139 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2140 + break;
2141 + case 2:
2142 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2143 + break;
2144 + case 3:
2145 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2146 + break;
2147 + default:
2148 + return -ENODEV;
2149 + }
2150 +
2151 + if (put_user(val, (u32 *) buf))
2152 + return -EFAULT;
2153 +
2154 + return sizeof(val);
2155 +}
2156 +
2157 +static ssize_t
2158 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
2159 +{
2160 + u32 val;
2161 +
2162 + if (get_user(val, (u32 *) buf))
2163 + return -EFAULT;
2164 +
2165 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2166 + case 0:
2167 + return -EACCES;
2168 + case 1:
2169 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2170 + break;
2171 + case 2:
2172 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2173 + break;
2174 + case 3:
2175 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2176 + break;
2177 + default:
2178 + return -ENODEV;
2179 + }
2180 +
2181 + return sizeof(val);
2182 +}
2183 +
2184 +static struct file_operations gpio_fops = {
2185 + owner: THIS_MODULE,
2186 + open: gpio_open,
2187 + release: gpio_release,
2188 + read: gpio_read,
2189 + write: gpio_write,
2190 +};
2191 +
2192 +static int __init
2193 +gpio_init(void)
2194 +{
2195 + int i;
2196 +
2197 + if (!(gpio_sbh = sb_kattach()))
2198 + return -ENODEV;
2199 +
2200 + sb_gpiosetcore(gpio_sbh);
2201 +
2202 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
2203 + return gpio_major;
2204 +
2205 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
2206 +
2207 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
2208 + gpio_file[i].handle = devfs_register(gpio_dir,
2209 + gpio_file[i].name,
2210 + DEVFS_FL_DEFAULT, gpio_major, i,
2211 + S_IFCHR | S_IRUGO | S_IWUGO,
2212 + &gpio_fops, NULL);
2213 + }
2214 +
2215 + return 0;
2216 +}
2217 +
2218 +static void __exit
2219 +gpio_exit(void)
2220 +{
2221 + int i;
2222 +
2223 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
2224 + devfs_unregister(gpio_file[i].handle);
2225 + devfs_unregister(gpio_dir);
2226 + devfs_unregister_chrdev(gpio_major, "gpio");
2227 + sb_detach(gpio_sbh);
2228 +}
2229 +
2230 +module_init(gpio_init);
2231 +module_exit(gpio_exit);
2232 diff -urN linux.old/arch/mips/bcm947xx/hndchipc.c linux.dev/arch/mips/bcm947xx/hndchipc.c
2233 --- linux.old/arch/mips/bcm947xx/hndchipc.c 1970-01-01 01:00:00.000000000 +0100
2234 +++ linux.dev/arch/mips/bcm947xx/hndchipc.c 2006-04-28 00:33:05.000000000 +0200
2235 @@ -0,0 +1,158 @@
2236 +/*
2237 + * BCM47XX support code for some chipcommon (old extif) facilities (uart)
2238 + *
2239 + * Copyright 2006, Broadcom Corporation
2240 + * All Rights Reserved.
2241 + *
2242 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2243 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2244 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2245 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2246 + *
2247 + * $Id: hndchipc.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
2248 + */
2249 +
2250 +#include <typedefs.h>
2251 +#include <bcmdefs.h>
2252 +#include <osl.h>
2253 +#include <bcmutils.h>
2254 +#include <sbutils.h>
2255 +#include <bcmdevs.h>
2256 +#include <bcmnvram.h>
2257 +#include <sbconfig.h>
2258 +#include <sbextif.h>
2259 +#include <sbchipc.h>
2260 +#include <hndcpu.h>
2261 +
2262 +/*
2263 + * Returns TRUE if an external UART exists at the given base
2264 + * register.
2265 + */
2266 +static bool
2267 +BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
2268 +{
2269 + uint8 save_mcr, status1;
2270 +
2271 + save_mcr = R_REG(osh, &regs[UART_MCR]);
2272 + W_REG(osh, &regs[UART_MCR], UART_MCR_LOOP | 0x0a);
2273 + status1 = R_REG(osh, &regs[UART_MSR]) & 0xf0;
2274 + W_REG(osh, &regs[UART_MCR], save_mcr);
2275 +
2276 + return (status1 == 0x90);
2277 +}
2278 +
2279 +/*
2280 + * Initializes UART access. The callback function will be called once
2281 + * per found UART.
2282 + */
2283 +void
2284 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base,
2285 + uint reg_shift))
2286 +{
2287 + osl_t *osh;
2288 + void *regs;
2289 + ulong base;
2290 + uint irq;
2291 + int i, n;
2292 +
2293 + osh = sb_osh(sbh);
2294 +
2295 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
2296 + extifregs_t *eir = (extifregs_t *) regs;
2297 + sbconfig_t *sb;
2298 +
2299 + /* Determine external UART register base */
2300 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
2301 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
2302 +
2303 + /* Determine IRQ */
2304 + irq = sb_irq(sbh);
2305 +
2306 + /* Disable GPIO interrupt initially */
2307 + W_REG(osh, &eir->gpiointpolarity, 0);
2308 + W_REG(osh, &eir->gpiointmask, 0);
2309 +
2310 + /* Search for external UARTs */
2311 + n = 2;
2312 + for (i = 0; i < 2; i++) {
2313 + regs = (void *) REG_MAP(base + (i * 8), 8);
2314 + if (serial_exists(osh, regs)) {
2315 + /* Set GPIO 1 to be the external UART IRQ */
2316 + W_REG(osh, &eir->gpiointmask, 2);
2317 + /* XXXDetermine external UART clock */
2318 + if (add)
2319 + add(regs, irq, 13500000, 0);
2320 + }
2321 + }
2322 +
2323 + /* Add internal UART if enabled */
2324 + if (R_REG(osh, &eir->corecontrol) & CC_UE)
2325 + if (add)
2326 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
2327 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
2328 + chipcregs_t *cc = (chipcregs_t *) regs;
2329 + uint32 rev, cap, pll, baud_base, div;
2330 +
2331 + /* Determine core revision and capabilities */
2332 + rev = sb_corerev(sbh);
2333 + cap = R_REG(osh, &cc->capabilities);
2334 + pll = cap & CAP_PLL_MASK;
2335 +
2336 + /* Determine IRQ */
2337 + irq = sb_irq(sbh);
2338 +
2339 + if (pll == PLL_TYPE1) {
2340 + /* PLL clock */
2341 + baud_base = sb_clock_rate(pll,
2342 + R_REG(osh, &cc->clockcontrol_n),
2343 + R_REG(osh, &cc->clockcontrol_m2));
2344 + div = 1;
2345 + } else {
2346 + /* Fixed ALP clock */
2347 + if (rev >= 11 && rev != 15) {
2348 + baud_base = 20000000;
2349 + div = 1;
2350 + /* Set the override bit so we don't divide it */
2351 + W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
2352 + }
2353 + /* Internal backplane clock */
2354 + else if (rev >= 3) {
2355 + baud_base = sb_clock(sbh);
2356 + div = 2; /* Minimum divisor */
2357 + W_REG(osh, &cc->clkdiv,
2358 + ((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
2359 + }
2360 + /* Fixed internal backplane clock */
2361 + else {
2362 + baud_base = 88000000;
2363 + div = 48;
2364 + }
2365 +
2366 + /* Clock source depends on strapping if UartClkOverride is unset */
2367 + if ((rev > 0) &&
2368 + ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
2369 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
2370 + /* Internal divided backplane clock */
2371 + baud_base /= div;
2372 + } else {
2373 + /* Assume external clock of 1.8432 MHz */
2374 + baud_base = 1843200;
2375 + }
2376 + }
2377 + }
2378 +
2379 + /* Add internal UARTs */
2380 + n = cap & CAP_UARTS_MASK;
2381 + for (i = 0; i < n; i++) {
2382 + /* Register offset changed after revision 0 */
2383 + if (rev)
2384 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
2385 + else
2386 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
2387 +
2388 + if (add)
2389 + add(regs, irq, baud_base, 0);
2390 + }
2391 + }
2392 +}
2393 +
2394 diff -urN linux.old/arch/mips/bcm947xx/include/bcm4710.h linux.dev/arch/mips/bcm947xx/include/bcm4710.h
2395 --- linux.old/arch/mips/bcm947xx/include/bcm4710.h 1970-01-01 01:00:00.000000000 +0100
2396 +++ linux.dev/arch/mips/bcm947xx/include/bcm4710.h 2006-04-27 22:30:01.000000000 +0200
2397 @@ -0,0 +1,91 @@
2398 +/*
2399 + * BCM4710 address space map and definitions
2400 + * Think twice before adding to this file, this is not the kitchen sink
2401 + * These definitions are not guaranteed for all 47xx chips, only the 4710
2402 + *
2403 + * Copyright 2004, Broadcom Corporation
2404 + * All Rights Reserved.
2405 + *
2406 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2407 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2408 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2409 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2410 + *
2411 + * $Id: bcm4710.h,v 1.3 2004/09/27 07:23:30 tallest Exp $
2412 + */
2413 +
2414 +#ifndef _bcm4710_h_
2415 +#define _bcm4710_h_
2416 +
2417 +/* Address map */
2418 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2419 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2420 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2421 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2422 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2423 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2424 +
2425 +/* Core register space */
2426 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2427 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2428 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2429 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2430 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2431 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2432 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2433 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2434 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2435 +
2436 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2437 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2438 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2439 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2440 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2441 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2442 +
2443 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2444 +
2445 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2446 +
2447 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2448 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2449 +
2450 +#define SBFLAG_PCI 0
2451 +#define SBFLAG_ENET0 1
2452 +#define SBFLAG_ILINE20 2
2453 +#define SBFLAG_CODEC 3
2454 +#define SBFLAG_USB 4
2455 +#define SBFLAG_EXTIF 5
2456 +#define SBFLAG_ENET1 6
2457 +
2458 +#ifdef CONFIG_HWSIM
2459 +#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
2460 +#else
2461 +#define BCM4710_TRACE(trval)
2462 +#endif
2463 +
2464 +
2465 +/* BCM94702 CPCI -ExtIF used for LocalBus devs */
2466 +
2467 +#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
2468 +#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
2469 +#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
2470 +#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
2471 +#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
2472 +#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
2473 +#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
2474 +#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
2475 +
2476 +#define LED_REG(x) \
2477 + (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
2478 +
2479 +/*
2480 + * Reset function implemented in PLD. Read or write should trigger hard reset
2481 + */
2482 +#define SYS_HARD_RESET() \
2483 + { for (;;) \
2484 + *( (volatile unsigned char *)\
2485 + KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
2486 + }
2487 +
2488 +#endif /* _bcm4710_h_ */
2489 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdefs.h linux.dev/arch/mips/bcm947xx/include/bcmdefs.h
2490 --- linux.old/arch/mips/bcm947xx/include/bcmdefs.h 1970-01-01 01:00:00.000000000 +0100
2491 +++ linux.dev/arch/mips/bcm947xx/include/bcmdefs.h 2006-04-27 20:12:21.000000000 +0200
2492 @@ -0,0 +1,106 @@
2493 +/*
2494 + * Misc system wide definitions
2495 + *
2496 + * Copyright 2006, Broadcom Corporation
2497 + * All Rights Reserved.
2498 + *
2499 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2500 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2501 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2502 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2503 + * $Id: bcmdefs.h,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
2504 + */
2505 +
2506 +#ifndef _bcmdefs_h_
2507 +#define _bcmdefs_h_
2508 +
2509 +/*
2510 + * One doesn't need to include this file explicitly, gets included automatically if
2511 + * typedefs.h is included.
2512 + */
2513 +
2514 +/* Reclaiming text and data :
2515 + * The following macros specify special linker sections that can be reclaimed
2516 + * after a system is considered 'up'.
2517 + */
2518 +#if defined(__GNUC__) && defined(BCMRECLAIM)
2519 +extern bool bcmreclaimed;
2520 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data
2521 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn
2522 +#else /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2523 +#define BCMINITDATA(_data) _data
2524 +#define BCMINITFN(_fn) _fn
2525 +#define bcmreclaimed 0
2526 +#endif /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2527 +
2528 +/* Reclaim uninit functions if BCMNODOWN is defined */
2529 +/* and if they are not already removed by -gc-sections */
2530 +#ifdef BCMNODOWN
2531 +#define BCMUNINITFN(_fn) BCMINITFN(_fn)
2532 +#else
2533 +#define BCMUNINITFN(_fn) _fn
2534 +#endif
2535 +
2536 +#ifdef BCMRECLAIM
2537 +#define CONST
2538 +#else
2539 +#define CONST const
2540 +#endif /* BCMRECLAIM */
2541 +
2542 +/* Compatibility with old-style BCMRECLAIM */
2543 +#define BCMINIT(_id) _id
2544 +
2545 +
2546 +/* Put some library data/code into ROM to reduce RAM requirements */
2547 +#if defined(__GNUC__) && defined(BCMROMOFFLOAD)
2548 +#define BCMROMDATA(_data) __attribute__ ((__section__ (".datarom." #_data))) _data
2549 +#define BCMROMFN(_fn) __attribute__ ((__section__ (".textrom." #_fn))) _fn
2550 +#else
2551 +#define BCMROMDATA(_data) _data
2552 +#define BCMROMFN(_fn) _fn
2553 +#endif
2554 +
2555 +/* Bus types */
2556 +#define SB_BUS 0 /* Silicon Backplane */
2557 +#define PCI_BUS 1 /* PCI target */
2558 +#define PCMCIA_BUS 2 /* PCMCIA target */
2559 +#define SDIO_BUS 3 /* SDIO target */
2560 +#define JTAG_BUS 4 /* JTAG */
2561 +#define NO_BUS 0xFF /* Bus that does not support R/W REG */
2562 +
2563 +/* Allows optimization for single-bus support */
2564 +#ifdef BCMBUSTYPE
2565 +#define BUSTYPE(bus) (BCMBUSTYPE)
2566 +#else
2567 +#define BUSTYPE(bus) (bus)
2568 +#endif
2569 +
2570 +/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
2571 +#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
2572 +#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
2573 +#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
2574 +
2575 +#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
2576 +#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
2577 +#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
2578 +#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
2579 +
2580 +/* packet headroom necessary to accomodate the largest header in the system, (i.e TXOFF).
2581 + * By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
2582 + * There is a compile time check in wlc.c which ensure that this value is at least as big
2583 + * as TXOFF. This value is used in dma_rxfill (hnddma.c).
2584 + */
2585 +#define BCMEXTRAHDROOM 160
2586 +
2587 +/* Headroom required for dongle-to-host communication. Packets allocated
2588 + * locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
2589 + * leave this much room in front for low-level message headers which may
2590 + * be needed to get across the dongle bus to the host. (These messages
2591 + * don't go over the network, so room for the full WL header above would
2592 + * be a waste.)
2593 + */
2594 +#define BCMDONGLEHDRSZ 8
2595 +
2596 +
2597 +
2598 +#endif /* _bcmdefs_h_ */
2599 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
2600 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
2601 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-04-27 22:30:25.000000000 +0200
2602 @@ -0,0 +1,369 @@
2603 +/*
2604 + * Broadcom device-specific manifest constants.
2605 + *
2606 + * Copyright 2006, Broadcom Corporation
2607 + * All Rights Reserved.
2608 + *
2609 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2610 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2611 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2612 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2613 + * $Id: bcmdevs.h,v 1.1.1.17 2006/04/15 01:29:08 michael Exp $
2614 + */
2615 +
2616 +#ifndef _BCMDEVS_H
2617 +#define _BCMDEVS_H
2618 +
2619 +#include "bcm4710.h"
2620 +
2621 +/* Known PCI vendor Id's */
2622 +#define VENDOR_EPIGRAM 0xfeda
2623 +#define VENDOR_BROADCOM 0x14e4
2624 +#define VENDOR_3COM 0x10b7
2625 +#define VENDOR_NETGEAR 0x1385
2626 +#define VENDOR_DIAMOND 0x1092
2627 +#define VENDOR_DELL 0x1028
2628 +#define VENDOR_HP 0x0e11
2629 +#define VENDOR_APPLE 0x106b
2630 +
2631 +/* PCI Device Id's */
2632 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2633 +#define BCM4211_DEVICE_ID 0x4211
2634 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2635 +#define BCM4231_DEVICE_ID 0x4231
2636 +
2637 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2638 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2639 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2640 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2641 +
2642 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2643 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2644 +
2645 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2646 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2647 +
2648 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2649 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
2650 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
2651 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
2652 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
2653 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
2654 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
2655 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
2656 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
2657 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
2658 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
2659 +#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
2660 +#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
2661 +#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
2662 +
2663 +#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
2664 +#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
2665 +
2666 +#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */
2667 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
2668 +
2669 +#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
2670 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
2671 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
2672 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
2673 +
2674 +#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
2675 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
2676 +#define BCM4306_D11G_ID2 0x4325
2677 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
2678 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
2679 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
2680 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
2681 +
2682 +#define BCM4309_PKG_ID 1 /* 4309 package id */
2683 +
2684 +#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
2685 +#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
2686 +#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
2687 +#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
2688 +
2689 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
2690 +#define BCM4303_PKG_ID 2 /* 4303 package id */
2691 +
2692 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
2693 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
2694 +
2695 +#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
2696 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
2697 +
2698 +#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */
2699 +#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
2700 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
2701 +#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
2702 +
2703 +#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */
2704 +#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
2705 +#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Hgz band id */
2706 +#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
2707 +
2708 +#define BCM4331_CHIP_ID 0x4331 /* 4331 chip common chipid */
2709 +#define BCM4331_D11N2G_ID 0x4330 /* 4331 802.11n 2.4Ghz band id */
2710 +#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
2711 +#define BCM4331_D11N5G_ID 0x4332 /* 4331 802.11n 5Ghz band id */
2712 +
2713 +#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
2714 +#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
2715 +#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
2716 +
2717 +#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
2718 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
2719 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
2720 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
2721 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
2722 +
2723 +#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
2724 +#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
2725 +#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
2726 +
2727 +#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
2728 +
2729 +#define BCM4328_CHIP_ID 0x4328 /* bcm4328 chipcommon chipid */
2730 +
2731 +#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
2732 +#define BCM43XX_JTAGM_ID 0x43f1 /* 43xx jtagm device id */
2733 +#define BCM43XXOLD_JTAGM_ID 0x4331 /* 43xx old jtagm device id */
2734 +
2735 +#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
2736 +#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
2737 +
2738 +#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
2739 +
2740 +#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
2741 +
2742 +/* PCMCIA vendor Id's */
2743 +
2744 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
2745 +
2746 +/* SDIO vendor Id's */
2747 +#define VENDOR_BROADCOM_SDIO 0x00BF
2748 +
2749 +
2750 +/* boardflags */
2751 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
2752 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
2753 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
2754 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
2755 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
2756 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
2757 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
2758 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
2759 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
2760 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
2761 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
2762 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
2763 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
2764 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
2765 +
2766 +/* boardflags2 */
2767 +#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */
2768 +#define BFL2_SSWITCH_AVAIL 0x00000002 /* This board has a superswitch for > 2 antennas */
2769 +#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits TX Power Control to be enabled */
2770 +
2771 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
2772 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
2773 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
2774 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
2775 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
2776 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
2777 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
2778 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
2779 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
2780 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
2781 +
2782 +/* power control defines */
2783 +#define PLL_DELAY 150 /* us pll on delay */
2784 +#define FREF_DELAY 200 /* us fref change delay */
2785 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
2786 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
2787 +
2788 +/* Reference Board Types */
2789 +
2790 +#define BU4710_BOARD 0x0400
2791 +#define VSIM4710_BOARD 0x0401
2792 +#define QT4710_BOARD 0x0402
2793 +
2794 +#define BU4309_BOARD 0x040a
2795 +#define BCM94309CB_BOARD 0x040b
2796 +#define BCM94309MP_BOARD 0x040c
2797 +#define BCM4309AP_BOARD 0x040d
2798 +
2799 +#define BCM94302MP_BOARD 0x040e
2800 +
2801 +#define BU4306_BOARD 0x0416
2802 +#define BCM94306CB_BOARD 0x0417
2803 +#define BCM94306MP_BOARD 0x0418
2804 +
2805 +#define BCM94710D_BOARD 0x041a
2806 +#define BCM94710R1_BOARD 0x041b
2807 +#define BCM94710R4_BOARD 0x041c
2808 +#define BCM94710AP_BOARD 0x041d
2809 +
2810 +#define BU2050_BOARD 0x041f
2811 +
2812 +
2813 +#define BCM94309G_BOARD 0x0421
2814 +
2815 +#define BU4704_BOARD 0x0423
2816 +#define BU4702_BOARD 0x0424
2817 +
2818 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
2819 +
2820 +
2821 +#define BCM94702MN_BOARD 0x0428
2822 +
2823 +/* BCM4702 1U CompactPCI Board */
2824 +#define BCM94702CPCI_BOARD 0x0429
2825 +
2826 +/* BCM4702 with BCM95380 VLAN Router */
2827 +#define BCM95380RR_BOARD 0x042a
2828 +
2829 +/* cb4306 with SiGe PA */
2830 +#define BCM94306CBSG_BOARD 0x042b
2831 +
2832 +/* cb4306 with SiGe PA */
2833 +#define PCSG94306_BOARD 0x042d
2834 +
2835 +/* bu4704 with sdram */
2836 +#define BU4704SD_BOARD 0x042e
2837 +
2838 +/* Dual 11a/11g Router */
2839 +#define BCM94704AGR_BOARD 0x042f
2840 +
2841 +/* 11a-only minipci */
2842 +#define BCM94308MP_BOARD 0x0430
2843 +
2844 +
2845 +
2846 +#define BU4712_BOARD 0x0444
2847 +#define BU4712SD_BOARD 0x045d
2848 +#define BU4712L_BOARD 0x045f
2849 +
2850 +/* BCM4712 boards */
2851 +#define BCM94712AP_BOARD 0x0445
2852 +#define BCM94712P_BOARD 0x0446
2853 +
2854 +/* BCM4318 boards */
2855 +#define BU4318_BOARD 0x0447
2856 +#define CB4318_BOARD 0x0448
2857 +#define MPG4318_BOARD 0x0449
2858 +#define MP4318_BOARD 0x044a
2859 +#define SD4318_BOARD 0x044b
2860 +
2861 +/* BCM63XX boards */
2862 +#define BCM96338_BOARD 0x6338
2863 +#define BCM96348_BOARD 0x6348
2864 +
2865 +/* Another mp4306 with SiGe */
2866 +#define BCM94306P_BOARD 0x044c
2867 +
2868 +/* mp4303 */
2869 +#define BCM94303MP_BOARD 0x044e
2870 +
2871 +/* mpsgh4306 */
2872 +#define BCM94306MPSGH_BOARD 0x044f
2873 +
2874 +/* BRCM 4306 w/ Front End Modules */
2875 +#define BCM94306MPM 0x0450
2876 +#define BCM94306MPL 0x0453
2877 +
2878 +/* 4712agr */
2879 +#define BCM94712AGR_BOARD 0x0451
2880 +
2881 +/* pcmcia 4303 */
2882 +#define PC4303_BOARD 0x0454
2883 +
2884 +/* 5350K */
2885 +#define BCM95350K_BOARD 0x0455
2886 +
2887 +/* 5350R */
2888 +#define BCM95350R_BOARD 0x0456
2889 +
2890 +/* 4306mplna */
2891 +#define BCM94306MPLNA_BOARD 0x0457
2892 +
2893 +/* 4320 boards */
2894 +#define BU4320_BOARD 0x0458
2895 +#define BU4320S_BOARD 0x0459
2896 +#define BCM94320PH_BOARD 0x045a
2897 +
2898 +/* 4306mph */
2899 +#define BCM94306MPH_BOARD 0x045b
2900 +
2901 +/* 4306pciv */
2902 +#define BCM94306PCIV_BOARD 0x045c
2903 +
2904 +#define BU4712SD_BOARD 0x045d
2905 +
2906 +#define BCM94320PFLSH_BOARD 0x045e
2907 +
2908 +#define BU4712L_BOARD 0x045f
2909 +#define BCM94712LGR_BOARD 0x0460
2910 +#define BCM94320R_BOARD 0x0461
2911 +
2912 +#define BU5352_BOARD 0x0462
2913 +
2914 +#define BCM94318MPGH_BOARD 0x0463
2915 +
2916 +#define BU4311_BOARD 0x0464
2917 +#define BCM94311MC_BOARD 0x0465
2918 +#define BCM94311MCAG_BOARD 0x0466
2919 +
2920 +#define BCM95352GR_BOARD 0x0467
2921 +
2922 +/* bcm95351agr */
2923 +#define BCM95351AGR_BOARD 0x0470
2924 +
2925 +/* bcm94704mpcb */
2926 +#define BCM94704MPCB_BOARD 0x0472
2927 +
2928 +/* 4785 boards */
2929 +#define BU4785_BOARD 0x0478
2930 +
2931 +/* 4321 boards */
2932 +#define BU4321_BOARD 0x046b
2933 +#define BU4321E_BOARD 0x047c
2934 +#define MP4321_BOARD 0x046c
2935 +#define CB2_4321_BOARD 0x046d
2936 +#define MC4321_BOARD 0x046e
2937 +
2938 +/* # of GPIO pins */
2939 +#define GPIO_NUMPINS 16
2940 +
2941 +/* radio ID codes */
2942 +#define NORADIO_ID 0xe4f5
2943 +#define NORADIO_IDCODE 0x4e4f5246
2944 +
2945 +#define BCM2050_ID 0x2050
2946 +#define BCM2050_IDCODE 0x02050000
2947 +#define BCM2050A0_IDCODE 0x1205017f
2948 +#define BCM2050A1_IDCODE 0x2205017f
2949 +#define BCM2050R8_IDCODE 0x8205017f
2950 +
2951 +#define BCM2055_ID 0x2055
2952 +#define BCM2055_IDCODE 0x02055000
2953 +#define BCM2055A0_IDCODE 0x1205517f
2954 +
2955 +#define BCM2060_ID 0x2060
2956 +#define BCM2060_IDCODE 0x02060000
2957 +#define BCM2060WW_IDCODE 0x1206017f
2958 +
2959 +#define BCM2062_ID 0x2062
2960 +#define BCM2062_IDCODE 0x02062000
2961 +#define BCM2062A0_IDCODE 0x0206217f
2962 +
2963 +/* parts of an idcode: */
2964 +#define IDCODE_MFG_MASK 0x00000fff
2965 +#define IDCODE_MFG_SHIFT 0
2966 +#define IDCODE_ID_MASK 0x0ffff000
2967 +#define IDCODE_ID_SHIFT 12
2968 +#define IDCODE_REV_MASK 0xf0000000
2969 +#define IDCODE_REV_SHIFT 28
2970 +
2971 +#endif /* _BCMDEVS_H */
2972 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs1.h linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h
2973 --- linux.old/arch/mips/bcm947xx/include/bcmdevs1.h 1970-01-01 01:00:00.000000000 +0100
2974 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h 2006-05-02 04:32:03.000000000 +0200
2975 @@ -0,0 +1,391 @@
2976 +/*
2977 + * Broadcom device-specific manifest constants.
2978 + *
2979 + * Copyright 2005, Broadcom Corporation
2980 + * All Rights Reserved.
2981 + *
2982 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2983 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2984 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2985 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2986 + * $Id$
2987 + */
2988 +
2989 +#ifndef _BCMDEVS_H
2990 +#define _BCMDEVS_H
2991 +
2992 +
2993 +/* Known PCI vendor Id's */
2994 +#define VENDOR_EPIGRAM 0xfeda
2995 +#define VENDOR_BROADCOM 0x14e4
2996 +#define VENDOR_3COM 0x10b7
2997 +#define VENDOR_NETGEAR 0x1385
2998 +#define VENDOR_DIAMOND 0x1092
2999 +#define VENDOR_DELL 0x1028
3000 +#define VENDOR_HP 0x0e11
3001 +#define VENDOR_APPLE 0x106b
3002 +
3003 +/* PCI Device Id's */
3004 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
3005 +#define BCM4211_DEVICE_ID 0x4211
3006 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
3007 +#define BCM4231_DEVICE_ID 0x4231
3008 +
3009 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
3010 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
3011 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
3012 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
3013 +
3014 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
3015 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
3016 +
3017 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
3018 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
3019 +
3020 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
3021 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
3022 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
3023 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
3024 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
3025 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
3026 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
3027 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
3028 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
3029 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
3030 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
3031 +
3032 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
3033 +
3034 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
3035 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
3036 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
3037 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
3038 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
3039 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
3040 +
3041 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
3042 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
3043 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
3044 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
3045 +
3046 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
3047 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
3048 +
3049 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
3050 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
3051 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
3052 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
3053 +
3054 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
3055 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
3056 +#define BCM4306_D11G_ID2 0x4325
3057 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
3058 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
3059 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
3060 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
3061 +
3062 +#define BCM4309_PKG_ID 1 /* 4309 package id */
3063 +
3064 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
3065 +#define BCM4303_PKG_ID 2 /* 4303 package id */
3066 +
3067 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
3068 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
3069 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
3070 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
3071 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
3072 +
3073 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
3074 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
3075 +
3076 +
3077 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
3078 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
3079 +
3080 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
3081 +
3082 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
3083 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
3084 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
3085 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
3086 +
3087 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
3088 +
3089 +/* Address map */
3090 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
3091 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
3092 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
3093 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
3094 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
3095 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
3096 +
3097 +/* Core register space */
3098 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
3099 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
3100 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
3101 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
3102 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
3103 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
3104 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
3105 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
3106 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
3107 +
3108 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
3109 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
3110 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
3111 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
3112 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
3113 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
3114 +
3115 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
3116 +
3117 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
3118 +
3119 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
3120 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
3121 +
3122 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
3123 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
3124 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
3125 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
3126 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
3127 +
3128 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
3129 +
3130 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
3131 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
3132 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
3133 +
3134 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
3135 +
3136 +/* PCMCIA vendor Id's */
3137 +
3138 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
3139 +
3140 +/* SDIO vendor Id's */
3141 +#define VENDOR_BROADCOM_SDIO 0x00BF
3142 +
3143 +
3144 +/* boardflags */
3145 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
3146 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
3147 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
3148 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
3149 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
3150 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
3151 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
3152 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
3153 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
3154 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
3155 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
3156 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
3157 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
3158 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
3159 +
3160 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
3161 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
3162 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
3163 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
3164 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
3165 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
3166 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
3167 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
3168 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
3169 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
3170 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
3171 +
3172 +/* Bus types */
3173 +#define SB_BUS 0 /* Silicon Backplane */
3174 +#define PCI_BUS 1 /* PCI target */
3175 +#define PCMCIA_BUS 2 /* PCMCIA target */
3176 +#define SDIO_BUS 3 /* SDIO target */
3177 +#define JTAG_BUS 4 /* JTAG */
3178 +
3179 +/* Allows optimization for single-bus support */
3180 +#ifdef BCMBUSTYPE
3181 +#define BUSTYPE(bus) (BCMBUSTYPE)
3182 +#else
3183 +#define BUSTYPE(bus) (bus)
3184 +#endif
3185 +
3186 +/* power control defines */
3187 +#define PLL_DELAY 150 /* us pll on delay */
3188 +#define FREF_DELAY 200 /* us fref change delay */
3189 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
3190 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
3191 +
3192 +/* Reference Board Types */
3193 +
3194 +#define BU4710_BOARD 0x0400
3195 +#define VSIM4710_BOARD 0x0401
3196 +#define QT4710_BOARD 0x0402
3197 +
3198 +#define BU4610_BOARD 0x0403
3199 +#define VSIM4610_BOARD 0x0404
3200 +
3201 +#define BU4307_BOARD 0x0405
3202 +#define BCM94301CB_BOARD 0x0406
3203 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
3204 +#define BCM94301MP_BOARD 0x0407
3205 +#define BCM94307MP_BOARD 0x0408
3206 +#define BCMAP4307_BOARD 0x0409
3207 +
3208 +#define BU4309_BOARD 0x040a
3209 +#define BCM94309CB_BOARD 0x040b
3210 +#define BCM94309MP_BOARD 0x040c
3211 +#define BCM4309AP_BOARD 0x040d
3212 +
3213 +#define BCM94302MP_BOARD 0x040e
3214 +
3215 +#define VSIM4310_BOARD 0x040f
3216 +#define BU4711_BOARD 0x0410
3217 +#define BCM94310U_BOARD 0x0411
3218 +#define BCM94310AP_BOARD 0x0412
3219 +#define BCM94310MP_BOARD 0x0414
3220 +
3221 +#define BU4306_BOARD 0x0416
3222 +#define BCM94306CB_BOARD 0x0417
3223 +#define BCM94306MP_BOARD 0x0418
3224 +
3225 +#define BCM94710D_BOARD 0x041a
3226 +#define BCM94710R1_BOARD 0x041b
3227 +#define BCM94710R4_BOARD 0x041c
3228 +#define BCM94710AP_BOARD 0x041d
3229 +
3230 +
3231 +#define BU2050_BOARD 0x041f
3232 +
3233 +
3234 +#define BCM94309G_BOARD 0x0421
3235 +
3236 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
3237 +
3238 +#define BU4704_BOARD 0x0423
3239 +#define BU4702_BOARD 0x0424
3240 +
3241 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
3242 +
3243 +#define BU4317_BOARD 0x0426
3244 +
3245 +
3246 +#define BCM94702MN_BOARD 0x0428
3247 +
3248 +/* BCM4702 1U CompactPCI Board */
3249 +#define BCM94702CPCI_BOARD 0x0429
3250 +
3251 +/* BCM4702 with BCM95380 VLAN Router */
3252 +#define BCM95380RR_BOARD 0x042a
3253 +
3254 +/* cb4306 with SiGe PA */
3255 +#define BCM94306CBSG_BOARD 0x042b
3256 +
3257 +/* mp4301 with 2050 radio */
3258 +#define BCM94301MPL_BOARD 0x042c
3259 +
3260 +/* cb4306 with SiGe PA */
3261 +#define PCSG94306_BOARD 0x042d
3262 +
3263 +/* bu4704 with sdram */
3264 +#define BU4704SD_BOARD 0x042e
3265 +
3266 +/* Dual 11a/11g Router */
3267 +#define BCM94704AGR_BOARD 0x042f
3268 +
3269 +/* 11a-only minipci */
3270 +#define BCM94308MP_BOARD 0x0430
3271 +
3272 +
3273 +
3274 +/* BCM94317 boards */
3275 +#define BCM94317CB_BOARD 0x0440
3276 +#define BCM94317MP_BOARD 0x0441
3277 +#define BCM94317PCMCIA_BOARD 0x0442
3278 +#define BCM94317SDIO_BOARD 0x0443
3279 +
3280 +#define BU4712_BOARD 0x0444
3281 +#define BU4712SD_BOARD 0x045d
3282 +#define BU4712L_BOARD 0x045f
3283 +
3284 +/* BCM4712 boards */
3285 +#define BCM94712AP_BOARD 0x0445
3286 +#define BCM94712P_BOARD 0x0446
3287 +
3288 +/* BCM4318 boards */
3289 +#define BU4318_BOARD 0x0447
3290 +#define CB4318_BOARD 0x0448
3291 +#define MPG4318_BOARD 0x0449
3292 +#define MP4318_BOARD 0x044a
3293 +#define SD4318_BOARD 0x044b
3294 +
3295 +/* BCM63XX boards */
3296 +#define BCM96338_BOARD 0x6338
3297 +#define BCM96345_BOARD 0x6345
3298 +#define BCM96348_BOARD 0x6348
3299 +
3300 +/* Another mp4306 with SiGe */
3301 +#define BCM94306P_BOARD 0x044c
3302 +
3303 +/* CF-like 4317 modules */
3304 +#define BCM94317CF_BOARD 0x044d
3305 +
3306 +/* mp4303 */
3307 +#define BCM94303MP_BOARD 0x044e
3308 +
3309 +/* mpsgh4306 */
3310 +#define BCM94306MPSGH_BOARD 0x044f
3311 +
3312 +/* BRCM 4306 w/ Front End Modules */
3313 +#define BCM94306MPM 0x0450
3314 +#define BCM94306MPL 0x0453
3315 +
3316 +/* 4712agr */
3317 +#define BCM94712AGR_BOARD 0x0451
3318 +
3319 +/* The real CF 4317 board */
3320 +#define CFI4317_BOARD 0x0452
3321 +
3322 +/* pcmcia 4303 */
3323 +#define PC4303_BOARD 0x0454
3324 +
3325 +/* 5350K */
3326 +#define BCM95350K_BOARD 0x0455
3327 +
3328 +/* 5350R */
3329 +#define BCM95350R_BOARD 0x0456
3330 +
3331 +/* 4306mplna */
3332 +#define BCM94306MPLNA_BOARD 0x0457
3333 +
3334 +/* 4320 boards */
3335 +#define BU4320_BOARD 0x0458
3336 +#define BU4320S_BOARD 0x0459
3337 +#define BCM94320PH_BOARD 0x045a
3338 +
3339 +/* 4306mph */
3340 +#define BCM94306MPH_BOARD 0x045b
3341 +
3342 +/* 4306pciv */
3343 +#define BCM94306PCIV_BOARD 0x045c
3344 +
3345 +#define BU4712SD_BOARD 0x045d
3346 +
3347 +#define BCM94320PFLSH_BOARD 0x045e
3348 +
3349 +#define BU4712L_BOARD 0x045f
3350 +#define BCM94712LGR_BOARD 0x0460
3351 +#define BCM94320R_BOARD 0x0461
3352 +
3353 +#define BU5352_BOARD 0x0462
3354 +
3355 +#define BCM94318MPGH_BOARD 0x0463
3356 +
3357 +
3358 +#define BCM95352GR_BOARD 0x0467
3359 +
3360 +/* bcm95351agr */
3361 +#define BCM95351AGR_BOARD 0x0470
3362 +
3363 +/* # of GPIO pins */
3364 +#define GPIO_NUMPINS 16
3365 +
3366 +#endif /* _BCMDEVS_H */
3367 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
3368 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
3369 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-04-27 20:08:35.000000000 +0200
3370 @@ -0,0 +1,198 @@
3371 +/*
3372 + * local version of endian.h - byte order defines
3373 + *
3374 + * Copyright 2006, Broadcom Corporation
3375 + * All Rights Reserved.
3376 + *
3377 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3378 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3379 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3380 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3381 + *
3382 + * $Id: bcmendian.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
3383 +*/
3384 +
3385 +#ifndef _BCMENDIAN_H_
3386 +#define _BCMENDIAN_H_
3387 +
3388 +#include <typedefs.h>
3389 +
3390 +/* Byte swap a 16 bit value */
3391 +#define BCMSWAP16(val) \
3392 + ((uint16)(\
3393 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
3394 + (((uint16)(val) & (uint16)0xff00U) >> 8)))
3395 +
3396 +/* Byte swap a 32 bit value */
3397 +#define BCMSWAP32(val) \
3398 + ((uint32)(\
3399 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
3400 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
3401 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
3402 + (((uint32)(val) & (uint32)0xff000000UL) >> 24)))
3403 +
3404 +/* 2 Byte swap a 32 bit value */
3405 +#define BCMSWAP32BY16(val) \
3406 + ((uint32)(\
3407 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
3408 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16)))
3409 +
3410 +
3411 +static INLINE uint16
3412 +bcmswap16(uint16 val)
3413 +{
3414 + return BCMSWAP16(val);
3415 +}
3416 +
3417 +static INLINE uint32
3418 +bcmswap32(uint32 val)
3419 +{
3420 + return BCMSWAP32(val);
3421 +}
3422 +
3423 +static INLINE uint32
3424 +bcmswap32by16(uint32 val)
3425 +{
3426 + return BCMSWAP32BY16(val);
3427 +}
3428 +
3429 +/* buf - start of buffer of shorts to swap */
3430 +/* len - byte length of buffer */
3431 +static INLINE void
3432 +bcmswap16_buf(uint16 *buf, uint len)
3433 +{
3434 + len = len/2;
3435 +
3436 + while (len--) {
3437 + *buf = bcmswap16(*buf);
3438 + buf++;
3439 + }
3440 +}
3441 +
3442 +#ifndef hton16
3443 +#ifndef IL_BIGENDIAN
3444 +#define HTON16(i) BCMSWAP16(i)
3445 +#define hton16(i) bcmswap16(i)
3446 +#define hton32(i) bcmswap32(i)
3447 +#define ntoh16(i) bcmswap16(i)
3448 +#define ntoh32(i) bcmswap32(i)
3449 +#define ltoh16(i) (i)
3450 +#define ltoh32(i) (i)
3451 +#define htol16(i) (i)
3452 +#define htol32(i) (i)
3453 +#else
3454 +#define HTON16(i) (i)
3455 +#define hton16(i) (i)
3456 +#define hton32(i) (i)
3457 +#define ntoh16(i) (i)
3458 +#define ntoh32(i) (i)
3459 +#define ltoh16(i) bcmswap16(i)
3460 +#define ltoh32(i) bcmswap32(i)
3461 +#define htol16(i) bcmswap16(i)
3462 +#define htol32(i) bcmswap32(i)
3463 +#endif /* IL_BIGENDIAN */
3464 +#endif /* hton16 */
3465 +
3466 +#ifndef IL_BIGENDIAN
3467 +#define ltoh16_buf(buf, i)
3468 +#define htol16_buf(buf, i)
3469 +#else
3470 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3471 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3472 +#endif /* IL_BIGENDIAN */
3473 +
3474 +/*
3475 +* store 16-bit value to unaligned little endian byte array.
3476 +*/
3477 +static INLINE void
3478 +htol16_ua_store(uint16 val, uint8 *bytes)
3479 +{
3480 + bytes[0] = val&0xff;
3481 + bytes[1] = val>>8;
3482 +}
3483 +
3484 +/*
3485 +* store 32-bit value to unaligned little endian byte array.
3486 +*/
3487 +static INLINE void
3488 +htol32_ua_store(uint32 val, uint8 *bytes)
3489 +{
3490 + bytes[0] = val&0xff;
3491 + bytes[1] = (val>>8)&0xff;
3492 + bytes[2] = (val>>16)&0xff;