openwrt/target/linux/linux-2.4/patches/007-bcm94710_mmu.patch

   1 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
   2 --- linux.old/arch/mips/mm/c-r4k.c      2005-05-28 17:42:06.000000000 +0200
   3 +++ linux.dev/arch/mips/mm/c-r4k.c      2005-05-29 18:26:34.000000000 +0200
   4 @@ -14,6 +14,12 @@
   5  #include <linux/mm.h>
   6  #include <linux/bitops.h>
   7
   8 +#ifdef CONFIG_BCM4710
   9 +#include "../bcm947xx/include/typedefs.h"
  10 +#include "../bcm947xx/include/sbconfig.h"
  11 +#include <asm/paccess.h>
  12 +#endif
  13 +
  14  #include <asm/bcache.h>
  15  #include <asm/bootinfo.h>
  16  #include <asm/cacheops.h>
  17 @@ -390,6 +396,11 @@
  18                         addr = start & ~(dc_lsize - 1);
  19                         aend = (end - 1) & ~(dc_lsize - 1);
  20
  21 +#ifdef CONFIG_BCM4710
  22 +                       BCM4710_FILL_TLB(addr);
  23 +                       BCM4710_FILL_TLB(aend);
  24 +#endif
  25 +
  26                         while (1) {
  27                                 /* Hit_Writeback_Inv_D */
  28                                 protected_writeback_dcache_line(addr);
  29 @@ -509,6 +520,10 @@
  30                 R4600_HIT_CACHEOP_WAR_IMPL;
  31                 a = addr & ~(dc_lsize - 1);
  32                 end = (addr + size - 1) & ~(dc_lsize - 1);
  33 +#ifdef CONFIG_BCM4710
  34 +               BCM4710_FILL_TLB(a);
  35 +               BCM4710_FILL_TLB(end);
  36 +#endif
  37                 while (1) {
  38                         flush_dcache_line(a);   /* Hit_Writeback_Inv_D */
  39                         if (a == end)
  40 @@ -576,6 +591,10 @@
  41         unsigned long ic_lsize = current_cpu_data.icache.linesz;
  42         unsigned long dc_lsize = current_cpu_data.dcache.linesz;
  43
  44 +#ifdef CONFIG_BCM4710
  45 +       BCM4710_PROTECTED_FILL_TLB(addr);
  46 +       BCM4710_PROTECTED_FILL_TLB(addr + 4);
  47 +#endif
  48         R4600_HIT_CACHEOP_WAR_IMPL;
  49         protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
  50         protected_flush_icache_line(addr & ~(ic_lsize - 1));
  51 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
  52 --- linux.old/include/asm-mips/r4kcache.h       2005-05-28 17:42:06.000000000 +0200
  53 +++ linux.dev/include/asm-mips/r4kcache.h       2005-05-29 18:34:46.000000000 +0200
  54 @@ -15,6 +15,25 @@
  55  #include <asm/asm.h>
  56  #include <asm/cacheops.h>
  57
  58 +#ifdef CONFIG_BCM4710
  59 +#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
  60 +
  61 +#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
  62 +#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
  63 +
  64 +#define cache_op(op,addr)                                              \
  65 +       BCM4710_DUMMY_RREG();                                           \
  66 +       __asm__ __volatile__(                                           \
  67 +       "       .set    noreorder                               \n"     \
  68 +       "       .set    mips3\n\t                               \n"     \
  69 +       "       cache   %0, %1                                  \n"     \
  70 +       "       .set    mips0                                   \n"     \
  71 +       "       .set    reorder"                                        \
  72 +       :                                                               \
  73 +       : "i" (op), "m" (*(unsigned char *)(addr)))
  74 +
  75 +#else
  76 +
  77  #define cache_op(op,addr)                                              \
  78         __asm__ __volatile__(                                           \
  79         "       .set    noreorder                               \n"     \
  80 @@ -24,6 +43,8 @@
  81         "       .set    reorder"                                        \
  82         :                                                               \
  83         : "i" (op), "m" (*(unsigned char *)(addr)))
  84 +#endif
  85 +
  86
  87  static inline void flush_icache_line_indexed(unsigned long addr)
  88  {
  89 @@ -47,6 +68,10 @@
  90
  91  static inline void flush_dcache_line(unsigned long addr)
  92  {
  93 +
  94 +#ifdef CONFIG_BCM4710
  95 +       BCM4710_DUMMY_RREG();
  96 +#endif
  97         cache_op(Hit_Writeback_Inv_D, addr);
  98  }
  99
 100 @@ -196,7 +221,13 @@
 101         unsigned long start = page;
 102         unsigned long end = start + PAGE_SIZE;
 103
 104 +#ifdef CONFIG_BCM4710
 105 +       BCM4710_FILL_TLB(start);
 106 +#endif
 107         do {
 108 +#ifdef CONFIG_BCM4710
 109 +               BCM4710_DUMMY_RREG();
 110 +#endif
 111                 cache16_unroll32(start,Hit_Invalidate_I);
 112                 start += 0x200;
 113         } while (start < end);
 114 @@ -291,8 +322,12 @@
 115         unsigned long ws, addr;
 116
 117         for (ws = 0; ws < ws_end; ws += ws_inc)
 118 -               for (addr = start; addr < end; addr += 0x400)
 119 +               for (addr = start; addr < end; addr += 0x400) {
 120 +#ifdef CONFIG_BCM4710
 121 +                       BCM4710_DUMMY_RREG();
 122 +#endif
 123                         cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
 124 +               }
 125  }
 126
 127  static inline void blast_dcache32_page(unsigned long page)
 128 @@ -300,6 +335,9 @@
 129         unsigned long start = page;
 130         unsigned long end = start + PAGE_SIZE;
 131
 132 +#ifdef CONFIG_BCM4710
 133 +       __asm__ __volatile__("nop;nop;nop;nop");
 134 +#endif
 135         do {
 136                 cache32_unroll32(start,Hit_Writeback_Inv_D);
 137                 start += 0x400;
 138 @@ -339,6 +377,9 @@
 139         unsigned long start = page;
 140         unsigned long end = start + PAGE_SIZE;
 141
 142 +#ifdef CONFIG_BCM4710
 143 +       BCM4710_FILL_TLB(start);
 144 +#endif
 145         do {
 146                 cache32_unroll32(start,Hit_Invalidate_I);
 147                 start += 0x400;