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[openwrt/svn-archive/archive.git] / package / ath9k / src / drivers / net / wireless / ath9k / core.h
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef CORE_H
18 #define CORE_H
19
20 #include <linux/version.h>
21 #include <linux/autoconf.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/skbuff.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ip.h>
30 #include <linux/tcp.h>
31 #include <linux/in.h>
32 #include <linux/delay.h>
33 #include <linux/wait.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/sched.h>
37 #include <linux/list.h>
38 #include <asm/byteorder.h>
39 #include <linux/scatterlist.h>
40 #include <asm/page.h>
41 #include <net/mac80211.h>
42
43 #include "ath9k.h"
44 #include "rc.h"
45
46 struct ath_node;
47
48 /******************/
49 /* Utility macros */
50 /******************/
51
52 /* An attempt will be made to merge these link list helpers upstream
53 * instead */
54
55 static inline void __list_splice_tail(const struct list_head *list,
56 struct list_head *head)
57 {
58 struct list_head *first = list->next;
59 struct list_head *last = list->prev;
60 struct list_head *current_tail = head->prev;
61
62 current_tail->next = first;
63 last->next = head;
64 head->prev = last;
65 first->prev = current_tail;
66 }
67
68 static inline void __list_cut_position(struct list_head *list,
69 struct list_head *head, struct list_head *entry)
70 {
71 struct list_head *new_first =
72 (entry->next != head) ? entry->next : head;
73 list->next = head->next;
74 list->next->prev = list;
75 list->prev = entry;
76 entry->next = list;
77 head->next = new_first;
78 new_first->prev = head;
79 }
80
81 /**
82 * list_splice_tail - join two lists, each list being a queue
83 * @list: the new list to add.
84 * @head: the place to add it in the first list.
85 */
86 static inline void list_splice_tail(const struct list_head *list,
87 struct list_head *head)
88 {
89 if (!list_empty(list))
90 __list_splice_tail(list, head);
91 }
92
93 /**
94 * list_splice_tail_init - join two lists, each list being a queue, and
95 * reinitialise the emptied list.
96 * @list: the new list to add.
97 * @head: the place to add it in the first list.
98 *
99 * The list at @list is reinitialised
100 */
101 static inline void list_splice_tail_init(struct list_head *list,
102 struct list_head *head)
103 {
104 if (!list_empty(list)) {
105 __list_splice_tail(list, head);
106 INIT_LIST_HEAD(list);
107 }
108 }
109
110 /**
111 * list_cut_position - cut a list into two
112 * @list: a new list to add all removed entries
113 * @head: a list with entries
114 * @entry: an entry within head, could be the head itself
115 * and if so we won't won't cut the list
116 */
117 static inline void list_cut_position(struct list_head *list,
118 struct list_head *head, struct list_head *entry)
119 {
120 BUG_ON(list_empty(head));
121 if (list_is_singular(head))
122 BUG_ON(head->next != entry && head != entry);
123 if (entry == head)
124 INIT_LIST_HEAD(list);
125 else
126 __list_cut_position(list, head, entry);
127 }
128
129 /* Macro to expand scalars to 64-bit objects */
130
131 #define ito64(x) (sizeof(x) == 8) ? \
132 (((unsigned long long int)(x)) & (0xff)) : \
133 (sizeof(x) == 16) ? \
134 (((unsigned long long int)(x)) & 0xffff) : \
135 ((sizeof(x) == 32) ? \
136 (((unsigned long long int)(x)) & 0xffffffff) : \
137 (unsigned long long int)(x))
138
139 /* increment with wrap-around */
140 #define INCR(_l, _sz) do { \
141 (_l)++; \
142 (_l) &= ((_sz) - 1); \
143 } while (0)
144
145 /* decrement with wrap-around */
146 #define DECR(_l, _sz) do { \
147 (_l)--; \
148 (_l) &= ((_sz) - 1); \
149 } while (0)
150
151 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
152
153 #define ASSERT(exp) do { \
154 if (unlikely(!(exp))) { \
155 BUG(); \
156 } \
157 } while (0)
158
159 #define KASSERT(exp, msg) do { \
160 if (unlikely(!(exp))) { \
161 printk msg; \
162 BUG(); \
163 } \
164 } while (0)
165
166 /* XXX: remove */
167 #define memzero(_buf, _len) memset(_buf, 0, _len)
168
169 #define get_dma_mem_context(var, field) (&((var)->field))
170 #define copy_dma_mem_context(dst, src) (*dst = *src)
171
172 #define ATH9K_BH_STATUS_INTACT 0
173 #define ATH9K_BH_STATUS_CHANGE 1
174
175 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
176
177 static inline unsigned long get_timestamp(void)
178 {
179 return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
180 }
181
182 /*************/
183 /* Debugging */
184 /*************/
185
186 enum ATH_DEBUG {
187 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
188 ATH_DEBUG_RECV = 0x00000002, /* basic recv operation */
189 ATH_DEBUG_BEACON = 0x00000004, /* beacon handling */
190 ATH_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */
191 ATH_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */
192 ATH_DEBUG_BEACON_PROC = 0x00000020, /* beacon ISR proc */
193 ATH_DEBUG_RATE = 0x00000040, /* rate control */
194 ATH_DEBUG_CONFIG = 0x00000080, /* configuration */
195 ATH_DEBUG_KEYCACHE = 0x00000100, /* key cache management */
196 ATH_DEBUG_NODE = 0x00000200, /* node management */
197 ATH_DEBUG_AGGR = 0x00000400, /* Aggregation */
198 ATH_DEBUG_CWM = 0x00000800, /* Channel Width Management */
199 ATH_DEBUG_FATAL = 0x00001000, /* fatal errors */
200 ATH_DEBUG_ANY = 0xffffffff
201 };
202
203 #define DBG_DEFAULT (ATH_DEBUG_FATAL)
204
205 #define DPRINTF(sc, _m, _fmt, ...) do { \
206 if (sc->sc_debug & (_m)) \
207 printk(_fmt , ##__VA_ARGS__); \
208 } while (0)
209
210 /***************************/
211 /* Load-time Configuration */
212 /***************************/
213
214 /* Per-instance load-time (note: NOT run-time) configurations
215 * for Atheros Device */
216 struct ath_config {
217 u_int8_t chainmask_sel; /* enable automatic tx chainmask selection */
218 u_int32_t ath_aggr_prot;
219 u_int16_t txpowlimit;
220 u_int16_t txpowlimit_override;
221 u_int8_t cabqReadytime; /* Cabq Readytime % */
222 u_int8_t swBeaconProcess; /* Process received beacons
223 in SW (vs HW) */
224 };
225
226 /***********************/
227 /* Chainmask Selection */
228 /***********************/
229
230 #define ATH_CHAINMASK_SEL_TIMEOUT 6000
231 /* Default - Number of last RSSI values that is used for
232 * chainmask selection */
233 #define ATH_CHAINMASK_SEL_RSSI_CNT 10
234 /* Means use 3x3 chainmask instead of configured chainmask */
235 #define ATH_CHAINMASK_SEL_3X3 7
236 /* Default - Rssi threshold below which we have to switch to 3x3 */
237 #define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
238 /* Default - Rssi threshold above which we have to switch to
239 * user configured values */
240 #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
241 /* Struct to store the chainmask select related info */
242 struct ath_chainmask_sel {
243 struct timer_list timer;
244 int cur_tx_mask; /* user configured or 3x3 */
245 int cur_rx_mask; /* user configured or 3x3 */
246 int tx_avgrssi;
247 u8 switch_allowed:1, /* timer will set this */
248 cm_sel_enabled:1;
249 };
250
251 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
252
253 /*************************/
254 /* Descriptor Management */
255 /*************************/
256
257 /* Number of descriptors per buffer. The only case where we see skbuff
258 chains is due to FF aggregation in the driver. */
259 #define ATH_TXDESC 1
260 /* if there's more fragment for this MSDU */
261 #define ATH_BF_MORE_MPDU 1
262 #define ATH_TXBUF_RESET(_bf) do { \
263 (_bf)->bf_status = 0; \
264 (_bf)->bf_lastbf = NULL; \
265 (_bf)->bf_lastfrm = NULL; \
266 (_bf)->bf_next = NULL; \
267 memzero(&((_bf)->bf_state), \
268 sizeof(struct ath_buf_state)); \
269 } while (0)
270
271 struct ath_buf_state {
272 int bfs_nframes; /* # frames in aggregate */
273 u_int16_t bfs_al; /* length of aggregate */
274 u_int16_t bfs_frmlen; /* length of frame */
275 int bfs_seqno; /* sequence number */
276 int bfs_tidno; /* tid of this frame */
277 int bfs_retries; /* current retries */
278 struct ath_rc_series bfs_rcs[4]; /* rate series */
279 u8 bfs_isdata:1; /* is a data frame/aggregate */
280 u8 bfs_isaggr:1; /* is an aggregate */
281 u8 bfs_isampdu:1; /* is an a-mpdu, aggregate or not */
282 u8 bfs_ht:1; /* is an HT frame */
283 u8 bfs_isretried:1; /* is retried */
284 u8 bfs_isxretried:1; /* is excessive retried */
285 u8 bfs_shpreamble:1; /* is short preamble */
286 u8 bfs_isbar:1; /* is a BAR */
287 u8 bfs_ispspoll:1; /* is a PS-Poll */
288 u8 bfs_aggrburst:1; /* is a aggr burst */
289 u8 bfs_calcairtime:1; /* requests airtime be calculated
290 when set for tx frame */
291 int bfs_rifsburst_elem; /* RIFS burst/bar */
292 int bfs_nrifsubframes; /* # of elements in burst */
293 enum hal_key_type bfs_keytype; /* key type use to encrypt this frame */
294 };
295
296 #define bf_nframes bf_state.bfs_nframes
297 #define bf_al bf_state.bfs_al
298 #define bf_frmlen bf_state.bfs_frmlen
299 #define bf_retries bf_state.bfs_retries
300 #define bf_seqno bf_state.bfs_seqno
301 #define bf_tidno bf_state.bfs_tidno
302 #define bf_rcs bf_state.bfs_rcs
303 #define bf_isdata bf_state.bfs_isdata
304 #define bf_isaggr bf_state.bfs_isaggr
305 #define bf_isampdu bf_state.bfs_isampdu
306 #define bf_ht bf_state.bfs_ht
307 #define bf_isretried bf_state.bfs_isretried
308 #define bf_isxretried bf_state.bfs_isxretried
309 #define bf_shpreamble bf_state.bfs_shpreamble
310 #define bf_rifsburst_elem bf_state.bfs_rifsburst_elem
311 #define bf_nrifsubframes bf_state.bfs_nrifsubframes
312 #define bf_keytype bf_state.bfs_keytype
313 #define bf_isbar bf_state.bfs_isbar
314 #define bf_ispspoll bf_state.bfs_ispspoll
315 #define bf_aggrburst bf_state.bfs_aggrburst
316 #define bf_calcairtime bf_state.bfs_calcairtime
317
318 /*
319 * Abstraction of a contiguous buffer to transmit/receive. There is only
320 * a single hw descriptor encapsulated here.
321 */
322
323 struct ath_buf {
324 struct list_head list;
325 struct list_head *last;
326 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
327 an aggregate) */
328 struct ath_buf *bf_lastfrm; /* last buf of this frame */
329 struct ath_buf *bf_next; /* next subframe in the aggregate */
330 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */
331 void *bf_mpdu; /* enclosing frame structure */
332 void *bf_node; /* pointer to the node */
333 struct ath_desc *bf_desc; /* virtual addr of desc */
334 dma_addr_t bf_daddr; /* physical addr of desc */
335 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
336 u_int32_t bf_status;
337 u_int16_t bf_flags; /* tx descriptor flags */
338 struct ath_buf_state bf_state; /* buffer state */
339 dma_addr_t bf_dmacontext;
340 };
341
342 /*
343 * reset the rx buffer.
344 * any new fields added to the athbuf and require
345 * reset need to be added to this macro.
346 * currently bf_status is the only one requires that
347 * requires reset.
348 */
349 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
350
351 /* hw processing complete, desc processed by hal */
352 #define ATH_BUFSTATUS_DONE 0x00000001
353 /* hw processing complete, desc hold for hw */
354 #define ATH_BUFSTATUS_STALE 0x00000002
355 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
356 #define ATH_BUFSTATUS_FREE 0x00000004
357
358 /* DMA state for tx/rx descriptors */
359
360 struct ath_descdma {
361 const char *dd_name;
362 struct ath_desc *dd_desc; /* descriptors */
363 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
364 u_int32_t dd_desc_len; /* size of dd_desc */
365 struct ath_buf *dd_bufptr; /* associated buffers */
366 dma_addr_t dd_dmacontext;
367 };
368
369 /* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
370
371 struct ath_rx_context {
372 struct ath_buf *ctx_rxbuf; /* associated ath_buf for rx */
373 };
374 #define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
375
376 int ath_descdma_setup(struct ath_softc *sc,
377 struct ath_descdma *dd,
378 struct list_head *head,
379 const char *name,
380 int nbuf,
381 int ndesc);
382 int ath_desc_alloc(struct ath_softc *sc);
383 void ath_desc_free(struct ath_softc *sc);
384 void ath_descdma_cleanup(struct ath_softc *sc,
385 struct ath_descdma *dd,
386 struct list_head *head);
387
388 /******/
389 /* RX */
390 /******/
391
392 #define ATH_MAX_ANTENNA 3
393 #define ATH_RXBUF 512
394 #define ATH_RX_TIMEOUT 40 /* 40 milliseconds */
395 #define WME_NUM_TID 16
396 #define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */
397 #define IEEE80211_BAR_CTL_TID_S 2 /* tid shift */
398
399 enum ATH_RX_TYPE {
400 ATH_RX_NON_CONSUMED = 0,
401 ATH_RX_CONSUMED
402 };
403
404 /* per frame rx status block */
405 struct ath_recv_status {
406 u_int64_t tsf; /* mac tsf */
407 int8_t rssi; /* RSSI (noise floor ajusted) */
408 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
409 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
410 int8_t abs_rssi; /* absolute RSSI */
411 u_int8_t rateieee; /* data rate received (IEEE rate code) */
412 u_int8_t ratecode; /* phy rate code */
413 int rateKbps; /* data rate received (Kbps) */
414 int antenna; /* rx antenna */
415 int flags; /* status of associated skb */
416 #define ATH_RX_FCS_ERROR 0x01
417 #define ATH_RX_MIC_ERROR 0x02
418 #define ATH_RX_DECRYPT_ERROR 0x04
419 #define ATH_RX_RSSI_VALID 0x08
420 /* if any of ctl,extn chainrssis are valid */
421 #define ATH_RX_CHAIN_RSSI_VALID 0x10
422 /* if extn chain rssis are valid */
423 #define ATH_RX_RSSI_EXTN_VALID 0x20
424 /* set if 40Mhz, clear if 20Mhz */
425 #define ATH_RX_40MHZ 0x40
426 /* set if short GI, clear if full GI */
427 #define ATH_RX_SHORT_GI 0x80
428 };
429
430 struct ath_rxbuf {
431 struct sk_buff *rx_wbuf; /* buffer */
432 unsigned long rx_time; /* system time when received */
433 struct ath_recv_status rx_status; /* cached rx status */
434 };
435
436 /* Per-TID aggregate receiver state for a node */
437 struct ath_arx_tid {
438 struct ath_node *an; /* parent ath node */
439 struct ath_rxbuf *rxbuf; /* re-ordering buffer */
440 struct timer_list timer;
441 spinlock_t tidlock; /* lock to protect this TID structure */
442 int baw_head; /* seq_next at head */
443 int baw_tail; /* tail of block-ack window */
444 int seq_reset; /* need to reset start sequence */
445 int addba_exchangecomplete;
446 u_int16_t seq_next; /* next expected sequence */
447 u_int16_t baw_size; /* block-ack window size */
448 };
449
450 /* Per-node receiver aggregate state */
451 struct ath_arx {
452 struct ath_arx_tid tid[WME_NUM_TID];
453 };
454
455 void ath_setrxfilter(struct ath_softc *sc);
456 int ath_startrecv(struct ath_softc *sc);
457 enum hal_bool ath_stoprecv(struct ath_softc *sc);
458 void ath_flushrecv(struct ath_softc *sc);
459 u_int32_t ath_calcrxfilter(struct ath_softc *sc);
460 void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
461 void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an);
462 void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
463 void ath_handle_rx_intr(struct ath_softc *sc);
464 int ath_rx_init(struct ath_softc *sc, int nbufs);
465 void ath_rx_cleanup(struct ath_softc *sc);
466 int ath_rx_tasklet(struct ath_softc *sc, int flush);
467 int ath_rx_input(struct ath_softc *sc,
468 struct ath_node *node,
469 int is_ampdu,
470 struct sk_buff *skb,
471 struct ath_recv_status *rx_status,
472 enum ATH_RX_TYPE *status);
473 int ath__rx_indicate(struct ath_softc *sc,
474 struct sk_buff *skb,
475 struct ath_recv_status *status,
476 u_int16_t keyix);
477 int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
478 struct ath_recv_status *status);
479
480 /******/
481 /* TX */
482 /******/
483
484 #define ATH_FRAG_PER_MSDU 1
485 #define ATH_TXBUF (512/ATH_FRAG_PER_MSDU)
486 /* max number of transmit attempts (tries) */
487 #define ATH_TXMAXTRY 13
488 /* max number of 11n transmit attempts (tries) */
489 #define ATH_11N_TXMAXTRY 10
490 /* max number of tries for management and control frames */
491 #define ATH_MGT_TXMAXTRY 4
492 #define WME_BA_BMP_SIZE 64
493 #define WME_MAX_BA WME_BA_BMP_SIZE
494 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
495 #define TID_TO_WME_AC(_tid) \
496 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
497 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
498 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
499 WME_AC_VO)
500
501
502 /* Wireless Multimedia Extension Defines */
503 #define WME_AC_BE 0 /* best effort */
504 #define WME_AC_BK 1 /* background */
505 #define WME_AC_VI 2 /* video */
506 #define WME_AC_VO 3 /* voice */
507 #define WME_NUM_AC 4
508
509 enum ATH_SM_PWRSAV{
510 ATH_SM_ENABLE,
511 ATH_SM_PWRSAV_STATIC,
512 ATH_SM_PWRSAV_DYNAMIC,
513 };
514
515 /*
516 * Data transmit queue state. One of these exists for each
517 * hardware transmit queue. Packets sent to us from above
518 * are assigned to queues based on their priority. Not all
519 * devices support a complete set of hardware transmit queues.
520 * For those devices the array sc_ac2q will map multiple
521 * priorities to fewer hardware queues (typically all to one
522 * hardware queue).
523 */
524 struct ath_txq {
525 u_int axq_qnum; /* hardware q number */
526 u_int32_t *axq_link; /* link ptr in last TX desc */
527 struct list_head axq_q; /* transmit queue */
528 spinlock_t axq_lock; /* lock on q and link */
529 unsigned long axq_lockflags; /* intr state when must cli */
530 u_int axq_depth; /* queue depth */
531 u_int8_t axq_aggr_depth; /* aggregates queued */
532 u_int32_t axq_totalqueued;/* total ever queued */
533 u_int axq_intrcnt; /* count to determine
534 if descriptor should generate
535 int on this txq. */
536 bool stopped; /* Is mac80211 queue
537 stopped ? */
538 /* State for patching up CTS when bursting */
539 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
540 struct ath_desc *axq_lastdsWithCTS; /* first desc of the
541 last descriptor that contains CTS */
542 struct ath_desc *axq_gatingds; /* final desc of the gating desc
543 * that determines whether lastdsWithCTS has
544 * been DMA'ed or not */
545 struct list_head axq_acq;
546 };
547
548 /* per TID aggregate tx state for a destination */
549 struct ath_atx_tid {
550 struct list_head list; /* round-robin tid entry */
551 struct list_head buf_q; /* pending buffers */
552 struct ath_node *an; /* parent node structure */
553 struct ath_atx_ac *ac; /* parent access category */
554 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];/* active tx frames */
555 u_int16_t seq_start; /* starting seq of BA window */
556 u_int16_t seq_next; /* next seq to be used */
557 u_int16_t baw_size; /* BA window size */
558 int tidno; /* TID number */
559 int baw_head; /* first un-acked tx buffer */
560 int baw_tail; /* next unused tx buffer slot */
561 int sched; /* TID is scheduled */
562 int paused; /* TID is paused */
563 int cleanup_inprogress; /* aggr of this TID is
564 being teared down */
565 u_int32_t addba_exchangecomplete:1; /* ADDBA state */
566 int32_t addba_exchangeinprogress;
567 int addba_exchangeattempts;
568 };
569
570 /* per access-category aggregate tx state for a destination */
571 struct ath_atx_ac {
572 int sched; /* dest-ac is scheduled */
573 int qnum; /* H/W queue number associated
574 with this AC */
575 struct list_head list; /* round-robin txq entry */
576 struct list_head tid_q; /* queue of TIDs with buffers */
577 };
578
579 /* per dest tx state */
580 struct ath_atx {
581 struct ath_atx_tid tid[WME_NUM_TID];
582 struct ath_atx_ac ac[WME_NUM_AC];
583 };
584
585 /* per-frame tx control block */
586 struct ath_tx_control {
587 struct ath_node *an; /* destination to sent to */
588 int if_id; /* only valid for cab traffic */
589 int qnum; /* h/w queue number */
590 u_int ht:1; /* if it can be transmitted using HT */
591 u_int ps:1; /* if one or more stations are in PS mode */
592 u_int use_minrate:1; /* if this frame should transmitted using
593 minimum rate */
594 enum hal_pkt_type atype; /* Atheros packet type */
595 enum hal_key_type keytype; /* key type */
596 u_int flags; /* HAL flags */
597 u_int16_t seqno; /* sequence number */
598 u_int16_t tidno; /* tid number */
599 u_int16_t txpower; /* transmit power */
600 u_int16_t frmlen; /* frame length */
601 u_int32_t keyix; /* key index */
602 int min_rate; /* minimum rate */
603 int mcast_rate; /* multicast rate */
604 u_int16_t nextfraglen; /* next fragment length */
605 /* below is set only by ath_dev */
606 struct ath_softc *dev; /* device handle */
607 dma_addr_t dmacontext;
608 };
609
610 /* per frame tx status block */
611 struct ath_xmit_status {
612 int retries; /* number of retries to successufully
613 transmit this frame */
614 int flags; /* status of transmit */
615 #define ATH_TX_ERROR 0x01
616 #define ATH_TX_XRETRY 0x02
617 #define ATH_TX_BAR 0x04
618 };
619
620 struct ath_tx_stat {
621 int rssi; /* RSSI (noise floor ajusted) */
622 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
623 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
624 int rateieee; /* data rate xmitted (IEEE rate code) */
625 int rateKbps; /* data rate xmitted (Kbps) */
626 int ratecode; /* phy rate code */
627 int flags; /* validity flags */
628 /* if any of ctl,extn chain rssis are valid */
629 #define ATH_TX_CHAIN_RSSI_VALID 0x01
630 /* if extn chain rssis are valid */
631 #define ATH_TX_RSSI_EXTN_VALID 0x02
632 u_int32_t airtime; /* time on air per final tx rate */
633 };
634
635 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
636 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
637 int ath_tx_setup(struct ath_softc *sc, int haltype);
638 void ath_draintxq(struct ath_softc *sc, enum hal_bool retry_tx);
639 void ath_tx_draintxq(struct ath_softc *sc,
640 struct ath_txq *txq, enum hal_bool retry_tx);
641 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
642 void ath_tx_node_cleanup(struct ath_softc *sc,
643 struct ath_node *an, bool bh_flag);
644 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
645 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
646 int ath_tx_init(struct ath_softc *sc, int nbufs);
647 int ath_tx_cleanup(struct ath_softc *sc);
648 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
649 int ath_txq_update(struct ath_softc *sc, int qnum, struct hal_txq_info *q);
650 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
651 void ath_tx_tasklet(struct ath_softc *sc);
652 u_int32_t ath_txq_depth(struct ath_softc *sc, int qnum);
653 u_int32_t ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
654 void ath_notify_txq_status(struct ath_softc *sc, u_int16_t queue_depth);
655 void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
656 struct ath_xmit_status *tx_status, struct ath_node *an);
657
658 /**********************/
659 /* Node / Aggregation */
660 /**********************/
661
662 /* indicates the node is clened up */
663 #define ATH_NODE_CLEAN 0x1
664 /* indicates the node is 80211 power save */
665 #define ATH_NODE_PWRSAVE 0x2
666
667 #define ADDBA_TIMEOUT 200 /* 200 milliseconds */
668 #define ADDBA_EXCHANGE_ATTEMPTS 10
669 #define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
670 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
671 /* number of delimiters for encryption padding */
672 #define ATH_AGGR_ENCRYPTDELIM 10
673 /* minimum h/w qdepth to be sustained to maximize aggregation */
674 #define ATH_AGGR_MIN_QDEPTH 2
675 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
676 #define IEEE80211_SEQ_SEQ_SHIFT 4
677 #define IEEE80211_SEQ_MAX 4096
678 #define IEEE80211_MIN_AMPDU_BUF 0x8
679
680 /* return whether a bit at index _n in bitmap _bm is set
681 * _sz is the size of the bitmap */
682 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
683 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
684
685 /* return block-ack bitmap index given sequence and starting sequence */
686 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
687
688 /* returns delimiter padding required given the packet length */
689 #define ATH_AGGR_GET_NDELIM(_len) \
690 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
691 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
692
693 #define BAW_WITHIN(_start, _bawsz, _seqno) \
694 ((((_seqno) - (_start)) & 4095) < (_bawsz))
695
696 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
697 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
698 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & HAL_TX_BA)
699 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
700
701 enum ATH_AGGR_STATUS {
702 ATH_AGGR_DONE,
703 ATH_AGGR_BAW_CLOSED,
704 ATH_AGGR_LIMITED,
705 ATH_AGGR_SHORTPKT,
706 ATH_AGGR_8K_LIMITED,
707 };
708
709 enum ATH_AGGR_CHECK {
710 AGGR_NOT_REQUIRED,
711 AGGR_REQUIRED,
712 AGGR_CLEANUP_PROGRESS,
713 AGGR_EXCHANGE_PROGRESS,
714 AGGR_EXCHANGE_DONE
715 };
716
717 struct aggr_rifs_param {
718 int param_max_frames;
719 int param_max_len;
720 int param_rl;
721 int param_al;
722 struct ath_rc_series *param_rcs;
723 };
724
725 /* Per-node aggregation state */
726 struct ath_node_aggr {
727 struct ath_atx tx; /* node transmit state */
728 struct ath_arx rx; /* node receive state */
729 };
730
731 /* driver-specific node state */
732 struct ath_node {
733 struct list_head list;
734 struct ath_softc *an_sc; /* back pointer */
735 atomic_t an_refcnt;
736 struct ath_chainmask_sel an_chainmask_sel;
737 struct ath_node_aggr an_aggr; /* A-MPDU aggregation state */
738 u_int8_t an_smmode; /* SM Power save mode */
739 u_int8_t an_flags;
740 u8 an_addr[ETH_ALEN];
741 };
742
743 void ath_tx_resume_tid(struct ath_softc *sc,
744 struct ath_atx_tid *tid);
745 enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
746 struct ath_node *an, u8 tidno);
747 void ath_tx_aggr_teardown(struct ath_softc *sc,
748 struct ath_node *an, u_int8_t tidno);
749 void ath_rx_aggr_teardown(struct ath_softc *sc,
750 struct ath_node *an, u_int8_t tidno);
751 int ath_rx_aggr_start(struct ath_softc *sc,
752 const u8 *addr,
753 u16 tid,
754 u16 *ssn);
755 int ath_rx_aggr_stop(struct ath_softc *sc,
756 const u8 *addr,
757 u16 tid);
758 int ath_tx_aggr_start(struct ath_softc *sc,
759 const u8 *addr,
760 u16 tid,
761 u16 *ssn);
762 int ath_tx_aggr_stop(struct ath_softc *sc,
763 const u8 *addr,
764 u16 tid);
765 void ath_newassoc(struct ath_softc *sc,
766 struct ath_node *node, int isnew, int isuapsd);
767 struct ath_node *ath_node_attach(struct ath_softc *sc,
768 u_int8_t addr[ETH_ALEN], int if_id);
769 void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
770 struct ath_node *ath_node_get(struct ath_softc *sc, u_int8_t addr[ETH_ALEN]);
771 void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
772 struct ath_node *ath_node_find(struct ath_softc *sc, u_int8_t *addr);
773
774 /*******************/
775 /* Beacon Handling */
776 /*******************/
777
778 /*
779 * Regardless of the number of beacons we stagger, (i.e. regardless of the
780 * number of BSSIDs) if a given beacon does not go out even after waiting this
781 * number of beacon intervals, the game's up.
782 */
783 #define BSTUCK_THRESH (9 * ATH_BCBUF)
784 #define ATH_BCBUF 4 /* number of beacon buffers */
785 #define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
786 #define ATH_DEFAULT_BMISS_LIMIT 10
787 #define ATH_BEACON_AIFS_DEFAULT 0 /* Default aifs for ap beacon q */
788 #define ATH_BEACON_CWMIN_DEFAULT 0 /* Default cwmin for ap beacon q */
789 #define ATH_BEACON_CWMAX_DEFAULT 0 /* Default cwmax for ap beacon q */
790 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
791
792 /* beacon configuration */
793 struct ath_beacon_config {
794 u_int16_t beacon_interval;
795 u_int16_t listen_interval;
796 u_int16_t dtim_period;
797 u_int16_t bmiss_timeout;
798 u_int8_t dtim_count;
799 u_int8_t tim_offset;
800 union {
801 u_int64_t last_tsf;
802 u_int8_t last_tstamp[8];
803 } u; /* last received beacon/probe response timestamp of this BSS. */
804 };
805
806 /* offsets in a beacon frame for
807 * quick acess of beacon content by low-level driver */
808 struct ath_beacon_offset {
809 u_int8_t *bo_tim; /* start of atim/dtim */
810 };
811
812 void ath9k_beacon_tasklet(unsigned long data);
813 void ath_beacon_config(struct ath_softc *sc, int if_id);
814 int ath_beaconq_setup(struct ath_hal *ah);
815 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
816 void ath_bstuck_process(struct ath_softc *sc);
817 void ath_beacon_tasklet(struct ath_softc *sc, int *needmark);
818 void ath_beacon_free(struct ath_softc *sc);
819 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
820 void ath_beacon_sync(struct ath_softc *sc, int if_id);
821 void ath_update_beacon_info(struct ath_softc *sc, int avgbrssi);
822 void ath_get_beaconconfig(struct ath_softc *sc,
823 int if_id,
824 struct ath_beacon_config *conf);
825 struct sk_buff *ath_get_beacon(struct ath_softc *sc,
826 int if_id,
827 struct ath_beacon_offset *bo,
828 struct ath_tx_control *txctl);
829 int ath_update_beacon(struct ath_softc *sc,
830 int if_id,
831 struct ath_beacon_offset *bo,
832 struct sk_buff *skb,
833 int mcast);
834 /********/
835 /* VAPs */
836 /********/
837
838 #define ATH_IF_HW_OFF 0x0001 /* hardware state needs to turn off */
839 #define ATH_IF_HW_ON 0x0002 /* hardware state needs to turn on */
840 /* STA only: the associated AP is HT capable */
841 #define ATH_IF_HT 0x0004
842 /* AP/IBSS only: current BSS has privacy on */
843 #define ATH_IF_PRIVACY 0x0008
844 #define ATH_IF_BEACON_ENABLE 0x0010 /* AP/IBSS only: enable beacon */
845 #define ATH_IF_BEACON_SYNC 0x0020 /* IBSS only: need to sync beacon */
846
847 /*
848 * Define the scheme that we select MAC address for multiple
849 * BSS on the same radio. The very first VAP will just use the MAC
850 * address from the EEPROM. For the next 3 VAPs, we set the
851 * U/L bit (bit 1) in MAC address, and use the next two bits as the
852 * index of the VAP.
853 */
854
855 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
856 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
857
858 /* VAP configuration (from protocol layer) */
859 struct ath_vap_config {
860 u_int32_t av_fixed_rateset;
861 u_int32_t av_fixed_retryset;
862 };
863
864 /* driver-specific vap state */
865 struct ath_vap {
866 struct ieee80211_vif *av_if_data; /* interface(vap)
867 instance from 802.11 protocal layer */
868 enum hal_opmode av_opmode; /* VAP operational mode */
869 struct ath_buf *av_bcbuf; /* beacon buffer */
870 struct ath_beacon_offset av_boff; /* dynamic update state */
871 struct ath_tx_control av_btxctl; /* tx control information
872 for beacon */
873 int av_bslot; /* beacon slot index */
874 struct ath_txq av_mcastq; /* multicast
875 transmit queue */
876 struct ath_vap_config av_config; /* vap configuration
877 parameters from 802.11 protocol layer*/
878 };
879
880 int ath_vap_attach(struct ath_softc *sc,
881 int if_id,
882 struct ieee80211_vif *if_data,
883 enum hal_opmode opmode,
884 enum hal_opmode iv_opmode,
885 int nostabeacons);
886 int ath_vap_detach(struct ath_softc *sc, int if_id);
887 int ath_vap_config(struct ath_softc *sc,
888 int if_id, struct ath_vap_config *if_config);
889 int ath_vap_down(struct ath_softc *sc, int if_id, u_int flags);
890 int ath_vap_listen(struct ath_softc *sc, int if_id);
891 int ath_vap_join(struct ath_softc *sc,
892 int if_id,
893 const u_int8_t bssid[ETH_ALEN],
894 u_int flags);
895 int ath_vap_up(struct ath_softc *sc,
896 int if_id,
897 const u_int8_t bssid[ETH_ALEN],
898 u_int8_t aid,
899 u_int flags);
900
901 /*********************/
902 /* Antenna diversity */
903 /*********************/
904
905 #define ATH_ANT_DIV_MAX_CFG 2
906 #define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
907 #define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
908
909 enum ATH_ANT_DIV_STATE{
910 ATH_ANT_DIV_IDLE,
911 ATH_ANT_DIV_SCAN, /* evaluating antenna */
912 };
913
914 struct ath_antdiv {
915 struct ath_softc *antdiv_sc;
916 u_int8_t antdiv_start;
917 enum ATH_ANT_DIV_STATE antdiv_state;
918 u_int8_t antdiv_num_antcfg;
919 u_int8_t antdiv_curcfg;
920 u_int8_t antdiv_bestcfg;
921 int32_t antdivf_rssitrig;
922 int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
923 u_int64_t antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
924 u_int64_t antdiv_laststatetsf;
925 u_int8_t antdiv_bssid[ETH_ALEN];
926 };
927
928 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
929 struct ath_softc *sc, int32_t rssitrig);
930 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
931 u_int8_t num_antcfg,
932 const u_int8_t *bssid);
933 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
934 void ath_slow_ant_div(struct ath_antdiv *antdiv,
935 struct ieee80211_hdr *wh,
936 struct ath_rx_status *rx_stats);
937 void ath_setdefantenna(void *sc, u_int antenna);
938
939 /********************/
940 /* Main driver core */
941 /********************/
942
943 /*
944 * Default cache line size, in bytes.
945 * Used when PCI device not fully initialized by bootrom/BIOS
946 */
947 #define DEFAULT_CACHELINE 32
948 #define ATH_DEFAULT_NOISE_FLOOR -95
949 #define ATH_REGCLASSIDS_MAX 10
950 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
951 #define ATH_PREAMBLE_SHORT (1<<0)
952 #define ATH_PROTECT_ENABLE (1<<1)
953 #define ATH_MAX_SW_RETRIES 10
954 /* Num farmes difference in tx to flip default recv */
955 #define ATH_ANTENNA_DIFF 2
956 #define ATH_CHAN_MAX 255
957 #define IEEE80211_WEP_NKID 4 /* number of key ids */
958 #define IEEE80211_RATE_VAL 0x7f
959 /*
960 * The key cache is used for h/w cipher state and also for
961 * tracking station state such as the current tx antenna.
962 * We also setup a mapping table between key cache slot indices
963 * and station state to short-circuit node lookups on rx.
964 * Different parts have different size key caches. We handle
965 * up to ATH_KEYMAX entries (could dynamically allocate state).
966 */
967 #define ATH_KEYMAX 128 /* max key cache size we handle */
968 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */
969
970 #define RESET_RETRY_TXQ 0x00000001
971 #define ATH_IF_ID_ANY 0xff
972
973 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
974
975 #define ATH_ISR_NOSCHED 0x0000 /* Do not schedule bottom half */
976 /* Schedule the bottom half for execution */
977 #define ATH_ISR_SCHED 0x0001
978 /* This was not my interrupt, for shared IRQ's */
979 #define ATH_ISR_NOTMINE 0x0002
980
981 #define RSSI_LPF_THRESHOLD -20
982 #define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
983 #define ATH_RATE_DUMMY_MARKER 0
984 #define ATH_RSSI_LPF_LEN 10
985 #define ATH_RSSI_DUMMY_MARKER 0x127
986
987 #define ATH_EP_MUL(x, mul) ((x) * (mul))
988 #define ATH_EP_RND(x, mul) \
989 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
990 #define ATH_RSSI_OUT(x) \
991 (((x) != ATH_RSSI_DUMMY_MARKER) ? \
992 (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
993 #define ATH_RSSI_IN(x) \
994 (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
995 #define ATH_LPF_RSSI(x, y, len) \
996 ((x != ATH_RSSI_DUMMY_MARKER) ? \
997 (((x) * ((len) - 1) + (y)) / (len)) : (y))
998 #define ATH_RSSI_LPF(x, y) do { \
999 if ((y) >= RSSI_LPF_THRESHOLD) \
1000 x = ATH_LPF_RSSI((x), \
1001 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
1002 } while (0)
1003
1004
1005 enum PROT_MODE {
1006 PROT_M_NONE = 0,
1007 PROT_M_RTSCTS,
1008 PROT_M_CTSONLY
1009 };
1010
1011 enum ieee80211_clist_cmd {
1012 CLIST_UPDATE,
1013 CLIST_DFS_UPDATE,
1014 CLIST_NEW_COUNTRY
1015 };
1016
1017 enum RATE_TYPE {
1018 NORMAL_RATE = 0,
1019 HALF_RATE,
1020 QUARTER_RATE
1021 };
1022
1023 struct ath_ht_info {
1024 enum hal_ht_macmode tx_chan_width;
1025 u_int16_t maxampdu;
1026 u_int8_t mpdudensity;
1027 u_int8_t ext_chan_offset;
1028 };
1029
1030 struct ath_softc {
1031 struct ieee80211_hw *hw; /* mac80211 instance */
1032 struct pci_dev *pdev; /* Bus handle */
1033 void __iomem *mem; /* address of the device */
1034 struct tasklet_struct intr_tq; /* General tasklet */
1035 struct tasklet_struct bcon_tasklet; /* Beacon tasklet */
1036 struct ath_config sc_config; /* per-instance load-time
1037 parameters */
1038 int sc_debug; /* Debug masks */
1039 struct ath_hal *sc_ah; /* HAL Instance */
1040 struct ath_rate_softc *sc_rc; /* tx rate control support */
1041 u_int32_t sc_intrstatus; /* HAL_STATUS */
1042 enum hal_opmode sc_opmode; /* current operating mode */
1043
1044 /* Properties, Config */
1045 unsigned int
1046 sc_invalid : 1, /* being detached */
1047 sc_mrretry : 1, /* multi-rate retry support */
1048 sc_needmib : 1, /* enable MIB stats intr */
1049 sc_hasdiversity : 1, /* rx diversity available */
1050 sc_diversity : 1, /* enable rx diversity */
1051 sc_hasveol : 1, /* tx VEOL support */
1052 sc_beacons : 1, /* beacons running */
1053 sc_hasbmask : 1, /* bssid mask support */
1054 sc_hastsfadd : 1, /* tsf adjust support */
1055 sc_scanning : 1, /* scanning active */
1056 sc_nostabeacons : 1, /* no beacons for station */
1057 sc_hasclrkey : 1, /* CLR key supported */
1058 sc_stagbeacons : 1, /* use staggered beacons */
1059 sc_txaggr : 1, /* enable 11n tx aggregation */
1060 sc_rxaggr : 1, /* enable 11n rx aggregation */
1061 sc_hasautosleep : 1, /* automatic sleep after TIM */
1062 sc_waitbeacon : 1, /* waiting for first beacon
1063 after waking up */
1064 sc_no_tx_3_chains : 1, /* user, hardware, regulatory
1065 or country may disallow transmit on
1066 three chains. */
1067 sc_update_chainmask : 1, /* change chain mask */
1068 sc_rx_chainmask_detect : 1, /* enable rx chain mask detection */
1069 sc_rx_chainmask_start : 1, /* start rx chain mask detection */
1070 sc_hashtsupport : 1, /* supports 11n */
1071 sc_full_reset : 1, /* force full reset */
1072 sc_slowAntDiv : 1; /* enable slow antenna diversity */
1073 enum wireless_mode sc_curmode; /* current phy mode */
1074 u_int16_t sc_curtxpow; /* current tx power limit */
1075 u_int16_t sc_curaid; /* current association id */
1076 u_int8_t sc_curbssid[ETH_ALEN];
1077 u_int8_t sc_myaddr[ETH_ALEN];
1078 enum PROT_MODE sc_protmode; /* protection mode */
1079 u_int8_t sc_mcastantenna;/* Multicast antenna number */
1080 u_int8_t sc_txantenna; /* data tx antenna
1081 (fixed or auto) */
1082 u_int8_t sc_nbcnvaps; /* # of vaps sending beacons */
1083 u_int16_t sc_nvaps; /* # of active virtual ap's */
1084 struct ath_vap *sc_vaps[ATH_BCBUF]; /* interface id
1085 to avp map */
1086 enum hal_int sc_imask; /* interrupt mask copy */
1087 u_int8_t sc_bssidmask[ETH_ALEN];
1088 u_int8_t sc_defant; /* current default antenna */
1089 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
1090 u_int16_t sc_cachelsz; /* cache line size */
1091 int sc_slotupdate; /* slot to next advance fsm */
1092 int sc_slottime; /* slot time */
1093 u_int8_t sc_noreset;
1094 int sc_bslot[ATH_BCBUF];/* beacon xmit slots */
1095 struct hal_node_stats sc_halstats; /* station-mode rssi stats */
1096 struct list_head node_list;
1097 struct ath_ht_info sc_ht_info;
1098 int16_t sc_noise_floor; /* signal noise floor in dBm */
1099 enum hal_ht_extprotspacing sc_ht_extprotspacing;
1100 u_int8_t sc_tx_chainmask;
1101 u_int8_t sc_rx_chainmask;
1102 u_int8_t sc_rxchaindetect_ref;
1103 u_int8_t sc_rxchaindetect_thresh5GHz;
1104 u_int8_t sc_rxchaindetect_thresh2GHz;
1105 u_int8_t sc_rxchaindetect_delta5GHz;
1106 u_int8_t sc_rxchaindetect_delta2GHz;
1107 u_int32_t sc_rtsaggrlimit; /* Chipset specific
1108 aggr limit */
1109 u32 sc_flags;
1110 #ifdef CONFIG_SLOW_ANT_DIV
1111 /* Slow antenna diversity */
1112 struct ath_antdiv sc_antdiv;
1113 #endif
1114 enum {
1115 OK, /* no change needed */
1116 UPDATE, /* update pending */
1117 COMMIT /* beacon sent, commit change */
1118 } sc_updateslot; /* slot time update fsm */
1119
1120 /* Crypto */
1121 u_int sc_keymax; /* size of key cache */
1122 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */
1123 u_int8_t sc_splitmic; /* split TKIP MIC keys */
1124 int sc_keytype; /* type of the key being used */
1125
1126 /* RX */
1127 struct list_head sc_rxbuf; /* receive buffer */
1128 struct ath_descdma sc_rxdma; /* RX descriptors */
1129 int sc_rxbufsize; /* rx size based on mtu */
1130 u_int32_t *sc_rxlink; /* link ptr in last RX desc */
1131 u_int32_t sc_rxflush; /* rx flush in progress */
1132 u_int64_t sc_lastrx; /* tsf of last rx'd frame */
1133
1134 /* TX */
1135 struct list_head sc_txbuf; /* transmit buffer */
1136 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
1137 struct ath_descdma sc_txdma; /* TX descriptors */
1138 u_int sc_txqsetup; /* h/w queues setup */
1139 u_int sc_txintrperiod;/* tx interrupt batching */
1140 int sc_haltype2q[HAL_WME_AC_VO+1]; /* HAL WME
1141 AC -> h/w qnum */
1142 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
1143
1144 /* Beacon */
1145 struct hal_txq_info sc_beacon_qi; /* adhoc only: beacon
1146 queue parameters */
1147 struct ath_descdma sc_bdma; /* beacon descriptors */
1148 struct ath_txq *sc_cabq; /* tx q for cab frames */
1149 struct list_head sc_bbuf; /* beacon buffers */
1150 u_int sc_bhalq; /* HAL q for outgoing beacons */
1151 u_int sc_bmisscount; /* missed beacon transmits */
1152 u_int32_t ast_be_xmit; /* beacons transmitted */
1153
1154 /* Rate */
1155 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
1156 const struct hal_rate_table *sc_rates[WIRELESS_MODE_MAX];
1157 const struct hal_rate_table *sc_currates; /* current rate table */
1158 u_int8_t sc_rixmap[256]; /* IEEE to h/w
1159 rate table ix */
1160 u_int8_t sc_minrateix; /* min h/w rate index */
1161 u_int8_t sc_protrix; /* protection rate index */
1162 struct {
1163 u_int32_t rateKbps; /* transfer rate in kbs */
1164 u_int8_t ieeerate; /* IEEE rate */
1165 } sc_hwmap[256]; /* h/w rate ix mappings */
1166
1167 /* Channel, Band */
1168 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
1169 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
1170 struct hal_channel sc_curchan; /* current h/w channel */
1171
1172 /* Locks */
1173 spinlock_t sc_rxflushlock; /* lock of RX flush */
1174 spinlock_t sc_rxbuflock; /* rxbuf lock */
1175 spinlock_t sc_txbuflock; /* txbuf lock */
1176 spinlock_t sc_resetlock;
1177 spinlock_t node_lock;
1178 };
1179
1180 int ath_init(u_int16_t devid, struct ath_softc *sc);
1181 void ath_deinit(struct ath_softc *sc);
1182 int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan);
1183 int ath_suspend(struct ath_softc *sc);
1184 int ath_intr(struct ath_softc *sc);
1185 int ath_reset(struct ath_softc *sc);
1186 void ath_scan_start(struct ath_softc *sc);
1187 void ath_scan_end(struct ath_softc *sc);
1188 int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan);
1189 void ath_setup_channel_list(struct ath_softc *sc,
1190 enum ieee80211_clist_cmd cmd,
1191 const struct hal_channel *chans,
1192 int nchan,
1193 const u_int8_t *regclassids,
1194 u_int nregclass,
1195 int countrycode);
1196 void ath_setup_rate(struct ath_softc *sc,
1197 enum wireless_mode wMode,
1198 enum RATE_TYPE type,
1199 const struct hal_rate_table *rt);
1200
1201 /*********************/
1202 /* Utility Functions */
1203 /*********************/
1204
1205 void ath_set_macmode(struct ath_softc *sc, enum hal_ht_macmode macmode);
1206 void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot);
1207 int ath_keyset(struct ath_softc *sc,
1208 u_int16_t keyix,
1209 struct hal_keyval *hk,
1210 const u_int8_t mac[ETH_ALEN]);
1211 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
1212 int ath_get_mac80211_qnum(u_int queue, struct ath_softc *sc);
1213 void ath_setslottime(struct ath_softc *sc);
1214 void ath_update_txpow(struct ath_softc *sc);
1215 int ath_cabq_update(struct ath_softc *);
1216 void ath_get_currentCountry(struct ath_softc *sc,
1217 struct hal_country_entry *ctry);
1218 u_int64_t ath_extend_tsf(struct ath_softc *sc, u_int32_t rstamp);
1219 void ath_internal_reset(struct ath_softc *sc);
1220 u_int32_t ath_chan2flags(struct ieee80211_channel *chan, struct ath_softc *sc);
1221 dma_addr_t ath_skb_map_single(struct ath_softc *sc,
1222 struct sk_buff *skb,
1223 int direction,
1224 dma_addr_t *pa);
1225 void ath_skb_unmap_single(struct ath_softc *sc,
1226 struct sk_buff *skb,
1227 int direction,
1228 dma_addr_t *pa);
1229 void ath_mcast_merge(struct ath_softc *sc, u_int32_t mfilt[2]);
1230 enum hal_ht_macmode ath_cwm_macmode(struct ath_softc *sc);
1231
1232 #endif /* CORE_H */
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