package/ifxmips-atm/src/common.h

   1 #include <linux/atmdev.h>
   2 #include <asm/ifxmips/ifxmips_irq.h>
   3 #include <linux/irq.h>
   4 #include <linux/sem.h>
   5 #include <linux/coda.h>
   6
   7 #define RX_DMA_CH_CBR                   0
   8 #define RX_DMA_CH_VBR_RT                1
   9 #define RX_DMA_CH_VBR_NRT               2
  10 #define RX_DMA_CH_AVR                   3
  11 #define RX_DMA_CH_UBR                   4
  12 #define RX_DMA_CH_OAM                   5
  13 #define RX_DMA_CH_TOTAL                 6
  14
  15 #define WRX_DMA_CHANNEL_INTERRUPT_MODE  0x00
  16 #define WRX_DMA_CHANNEL_POLLING_MODE    0x01
  17 //#define WRX_DMA_CHANNEL_COUNTER_MODE    0x02
  18 #define WRX_DMA_CHANNEL_COUNTER_MODE    WRX_DMA_CHANNEL_INTERRUPT_MODE
  19 #define WRX_DMA_BUF_LEN_PER_DESCRIPTOR  0x00
  20 #define WRX_DMA_BUF_LEN_PER_CHANNEL     0x01
  21
  22 #define ATM_VBR_RT     6
  23 #define ATM_VBR_NRT    ATM_VBR
  24 #define ATM_UBR_PLUS   7
  25
  26 #define SET_BITS(x, msb, lsb, value)    (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
  27
  28 #define GET_ATM_PRIV(dev)       ((Atm_Priv *)dev->priv)
  29
  30 #define CDM_CFG                         PPE_REG_ADDR(0x0100)
  31
  32 #define CDM_CFG_RAM1                    GET_BITS(*CDM_CFG, 3, 2)
  33 #define CDM_CFG_RAM0                    (*CDM_CFG & (1 << 1))
  34
  35 #define CDM_CFG_RAM1_SET(value)         SET_BITS(0, 3, 2, value)
  36 #define CDM_CFG_RAM0_SET(value)         ((value) ? (1 << 1) : 0)
  37
  38 /*
  39  *  EMA Registers
  40  */
  41 #define EMA_CMDCFG                      PPE_REG_ADDR(0x0A00)
  42 #define EMA_DATACFG                     PPE_REG_ADDR(0x0A01)
  43 #define EMA_CMDCNT                      PPE_REG_ADDR(0x0A02)
  44 #define EMA_DATACNT                     PPE_REG_ADDR(0x0A03)
  45 #define EMA_ISR                         PPE_REG_ADDR(0x0A04)
  46 #define EMA_IER                         PPE_REG_ADDR(0x0A05)
  47 #define EMA_CFG                         PPE_REG_ADDR(0x0A06)
  48 #define EMA_SUBID                       PPE_REG_ADDR(0x0A07)
  49
  50
  51 /*
  52  *  QSB RAM Access Register
  53  */
  54 #define QSB_RAMAC                       QSB_CONF_REG(0x000D)
  55
  56 #define QSB_RAMAC_RW                    (*QSB_RAMAC & (1 << 31))
  57 #define QSB_RAMAC_TSEL                  GET_BITS(*QSB_RAMAC, 27, 24)
  58 #define QSB_RAMAC_LH                    (*QSB_RAMAC & (1 << 16))
  59 #define QSB_RAMAC_TESEL                 GET_BITS(*QSB_RAMAC, 9, 0)
  60
  61 #define QSB_RAMAC_RW_SET(value)         ((value) ? (1 << 31) : 0)
  62 #define QSB_RAMAC_TSEL_SET(value)       SET_BITS(0, 27, 24, value)
  63 #define QSB_RAMAC_LH_SET(value)         ((value) ? (1 << 16) : 0)
  64 #define QSB_RAMAC_TESEL_SET(value)      SET_BITS(0, 9, 0, value)
  65
  66 /*  QSB */
  67 #define QSB_RAMAC_RW_READ               0
  68 #define QSB_RAMAC_RW_WRITE              1
  69
  70 #define QSB_RAMAC_TSEL_QPT              0x01
  71 #define QSB_RAMAC_TSEL_SCT              0x02
  72 #define QSB_RAMAC_TSEL_SPT              0x03
  73 #define QSB_RAMAC_TSEL_VBR              0x08
  74
  75 #define QSB_RAMAC_LH_LOW                0
  76 #define QSB_RAMAC_LH_HIGH               1
  77
  78 #define QSB_QPT_SET_MASK                0x0
  79 #define QSB_QVPT_SET_MASK               0x0
  80 #define QSB_SET_SCT_MASK                0x0
  81 #define QSB_SET_SPT_MASK                0x0
  82 #define QSB_SET_SPT_SBVALID_MASK        0x7FFFFFFF
  83
  84 #define QSB_SPT_SBV_VALID               (1 << 31)
  85 #define QSB_SPT_PN_SET(value)           (((value) & 0x01) ? (1 << 16) : 0)
  86 #define QSB_SPT_INTRATE_SET(value)      SET_BITS(0, 13, 0, value)
  87
  88 /*
  89  *  QSB Internal Cell Delay Variation Register
  90  */
  91 #define QSB_ICDV                        QSB_CONF_REG(0x0007)
  92
  93 #define QSB_ICDV_TAU                    GET_BITS(*QSB_ICDV, 5, 0)
  94
  95 #define QSB_ICDV_TAU_SET(value)         SET_BITS(0, 5, 0, value)
  96
  97 /*
  98  *  QSB Scheduler Burst Limit Register
  99  */
 100 #define QSB_SBL                         QSB_CONF_REG(0x0009)
 101
 102 #define QSB_SBL_SBL                     GET_BITS(*QSB_SBL, 3, 0)
 103
 104 #define QSB_SBL_SBL_SET(value)          SET_BITS(0, 3, 0, value)
 105
 106 /*
 107  *  QSB Configuration Register
 108  */
 109 #define QSB_CFG                         QSB_CONF_REG(0x000A)
 110
 111 #define QSB_CFG_TSTEPC                  GET_BITS(*QSB_CFG, 1, 0)
 112
 113 #define QSB_CFG_TSTEPC_SET(value)       SET_BITS(0, 1, 0, value)
 114
 115 /*
 116  *  QSB RAM Transfer Table Register
 117  */
 118 #define QSB_RTM                         QSB_CONF_REG(0x000B)
 119
 120 #define QSB_RTM_DM                      (*QSB_RTM)
 121
 122 #define QSB_RTM_DM_SET(value)           ((value) & 0xFFFFFFFF)
 123
 124 /*
 125  *  QSB RAM Transfer Data Register
 126  */
 127 #define QSB_RTD                         QSB_CONF_REG(0x000C)
 128
 129 #define QSB_RTD_TTV                     (*QSB_RTD)
 130
 131 #define QSB_RTD_TTV_SET(value)          ((value) & 0xFFFFFFFF)
 132
 133 /*
 134  *  PP32 Debug Control Register
 135  */
 136 #define PP32_DBG_CTRL                   PP32_DEBUG_REG_ADDR(0x0000)
 137
 138 #define DBG_CTRL_START_SET(value)       ((value) ? (1 << 0) : 0)
 139 #define DBG_CTRL_STOP_SET(value)        ((value) ? (1 << 1) : 0)
 140 #define DBG_CTRL_STEP_SET(value)        ((value) ? (1 << 2) : 0)
 141
 142 #define SB_RAM0_ADDR(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0x8000) << 2)))
 143 #define UPDATE_VCC_STAT(conn, item, num)    do { ppe_dev.connection[conn].item += num; } while (0)
 144 /*
 145  *  EMA Settings
 146  */
 147 #define EMA_CMD_BUF_LEN      0x0040
 148 #define EMA_CMD_BASE_ADDR    (0x00001580 << 2)
 149 #define EMA_DATA_BUF_LEN     0x0100
 150 #define EMA_DATA_BASE_ADDR   (0x00001900 << 2)
 151 #define EMA_WRITE_BURST      0x2
 152 #define EMA_READ_BURST       0x2
 153
 154
 155 #define CELL_SIZE                       ATM_AAL0_SDU
 156 #define IDLE_CYCLE_NUMBER               30000
 157
 158 #define MBOX_IGU1_ISR                   PPE_REG_ADDR(0x0206)
 159 #define MBOX_IGU3_ISRS                  PPE_REG_ADDR(0x0214)
 160 #define MBOX_IGU1_ISRC                  PPE_REG_ADDR(0x0205)
 161 #define MBOX_IGU3_ISR                   PPE_REG_ADDR(0x0216)
 162 #define MBOX_IGU3_ISRS_SET(n)           (1 << (n))
 163 #define MBOX_IGU3_ISR_ISR(n)            (*MBOX_IGU3_ISR & (1 << (n)))
 164 /*
 165  *  *  Mailbox IGU1 Registers
 166  *   */
 167 #define MBOX_IGU1_ISRS                  PPE_REG_ADDR(0x0204)
 168 #define MBOX_IGU1_IER                   PPE_REG_ADDR(0x0207)
 169
 170 #define MBOX_IGU1_ISRS_SET(n)           (1 << (n))
 171 #define MBOX_IGU1_ISRC_CLEAR(n)         (1 << (n))
 172 #define MBOX_IGU1_ISR_ISR(n)            (*MBOX_IGU1_ISR & (1 << (n)))
 173 #define MBOX_IGU1_IER_EN(n)             (*MBOX_IGU1_IER & (1 << (n)))
 174 #define MBOX_IGU1_IER_EN_SET(n)         (1 << (n))
 175
 176 /*
 177  *  *  Mailbox IGU3 Registers
 178  *   */
 179 #define MBOX_IGU3_ISRC                  PPE_REG_ADDR(0x0215)
 180 #define MBOX_IGU3_IER                   PPE_REG_ADDR(0x0217)
 181
 182 #define MBOX_IGU3_ISRS_SET(n)           (1 << (n))
 183 #define MBOX_IGU3_ISRC_CLEAR(n)         (1 << (n))
 184 #define MBOX_IGU3_ISR_ISR(n)            (*MBOX_IGU3_ISR & (1 << (n)))
 185 #define MBOX_IGU3_IER_EN(n)             (*MBOX_IGU3_IER & (1 << (n)))
 186 #define MBOX_IGU3_IER_EN_SET(n)         (1 << (n))
 187
 188
 189 // RX Frame Definitions
 190 #define MAX_RX_PACKET_ALIGN_BYTES       3
 191 #define MAX_RX_PACKET_PADDING_BYTES     3
 192 #define RX_INBAND_TRAILER_LENGTH        8
 193 #define MAX_RX_FRAME_EXTRA_BYTES        (RX_INBAND_TRAILER_LENGTH + MAX_RX_PACKET_ALIGN_BYTES + MAX_RX_PACKET_PADDING_BYTES)
 194
 195 // TX Frame Definitions
 196 #define MAX_TX_HEADER_ALIGN_BYTES       12
 197 #define MAX_TX_PACKET_ALIGN_BYTES       3
 198 #define MAX_TX_PACKET_PADDING_BYTES     3
 199 #define TX_INBAND_HEADER_LENGTH         8
 200 #define MAX_TX_FRAME_EXTRA_BYTES        (TX_INBAND_HEADER_LENGTH + MAX_TX_HEADER_ALIGN_BYTES + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES)
 201
 202
 203 // DWORD-Length of Memory Blocks
 204 #define PP32_DEBUG_REG_DWLEN            0x0030
 205 #define PPM_INT_REG_DWLEN               0x0010
 206 #define PP32_INTERNAL_RES_DWLEN         0x00C0
 207 #define PPE_CLOCK_CONTROL_DWLEN         0x0F00
 208 #define CDM_CODE_MEMORY_RAM0_DWLEN      0x1000
 209 #define CDM_CODE_MEMORY_RAM1_DWLEN      0x0800
 210 #define PPE_REG_DWLEN                   0x1000
 211 #define PP32_DATA_MEMORY_RAM1_DWLEN     0x0800
 212 #define PPM_INT_UNIT_DWLEN              0x0100
 213 #define PPM_TIMER0_DWLEN                0x0100
 214 #define PPM_TASK_IND_REG_DWLEN          0x0100
 215 #define PPS_BRK_DWLEN                   0x0100
 216 #define PPM_TIMER1_DWLEN                0x0100
 217 #define SB_RAM0_DWLEN                   0x0400
 218 #define SB_RAM1_DWLEN                   0x0800
 219 #define SB_RAM2_DWLEN                   0x0A00
 220 #define SB_RAM3_DWLEN                   0x0400
 221 #define QSB_CONF_REG_DWLEN              0x0100
 222 /*
 223  *  QSB Queue Scheduling and Shaping Definitions
 224  */
 225 #define QSB_WFQ_NONUBR_MAX              0x3f00
 226 #define QSB_WFQ_UBR_BYPASS              0x3fff
 227 #define QSB_TP_TS_MAX                   65472
 228 #define QSB_TAUS_MAX                    64512
 229 #define QSB_GCR_MIN                     18
 230
 231
 232
 233 // OAM Definitions
 234 #define OAM_RX_QUEUE_NUMBER             1
 235 #define OAM_TX_QUEUE_NUMBER_PER_PORT    0
 236 #define OAM_RX_DMA_CHANNEL_NUMBER       OAM_RX_QUEUE_NUMBER
 237 #define OAM_HTU_ENTRY_NUMBER            3
 238 #define OAM_F4_SEG_HTU_ENTRY            0
 239 #define OAM_F4_TOT_HTU_ENTRY            1
 240 #define OAM_F5_HTU_ENTRY                2
 241 #define OAM_F4_CELL_ID                  0
 242 #define OAM_F5_CELL_ID                  15
 243
 244 // ATM Port, QSB Queue, DMA RX/TX Channel Parameters
 245 #define ATM_PORT_NUMBER                 2
 246 #define MAX_QUEUE_NUMBER                16
 247 #define QSB_QUEUE_NUMBER_BASE           1
 248 #define MAX_QUEUE_NUMBER_PER_PORT       (MAX_QUEUE_NUMBER - QSB_QUEUE_NUMBER_BASE)
 249 #define MAX_CONNECTION_NUMBER           MAX_QUEUE_NUMBER
 250 #define MAX_RX_DMA_CHANNEL_NUMBER       8
 251 #define MAX_TX_DMA_CHANNEL_NUMBER       16
 252 #define DMA_ALIGNMENT                   4
 253
 254 #define DEFAULT_RX_HUNT_BITTH           4
 255
 256 /*
 257  *  FPI Configuration Bus Register and Memory Address Mapping
 258  */
 259 #define DANUBE_PPE                      (KSEG1 + 0x1E180000)
 260 #define PP32_DEBUG_REG_ADDR(x)          ((volatile u32*)(DANUBE_PPE + (((x) + 0x0000) << 2)))
 261 #define PPM_INT_REG_ADDR(x)             ((volatile u32*)(DANUBE_PPE + (((x) + 0x0030) << 2)))
 262 #define PP32_INTERNAL_RES_ADDR(x)       ((volatile u32*)(DANUBE_PPE + (((x) + 0x0040) << 2)))
 263 #define PPE_CLOCK_CONTROL_ADDR(x)       ((volatile u32*)(DANUBE_PPE + (((x) + 0x0100) << 2)))
 264 #define CDM_CODE_MEMORY_RAM0_ADDR(x)    ((volatile u32*)(DANUBE_PPE + (((x) + 0x1000) << 2)))
 265 #define CDM_CODE_MEMORY_RAM1_ADDR(x)    ((volatile u32*)(DANUBE_PPE + (((x) + 0x2000) << 2)))
 266 #define PPE_REG_ADDR(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0x4000) << 2)))
 267 #define PP32_DATA_MEMORY_RAM1_ADDR(x)   ((volatile u32*)(DANUBE_PPE + (((x) + 0x5000) << 2)))
 268 #define PPM_INT_UNIT_ADDR(x)            ((volatile u32*)(DANUBE_PPE + (((x) + 0x6000) << 2)))
 269 #define PPM_TIMER0_ADDR(x)              ((volatile u32*)(DANUBE_PPE + (((x) + 0x6100) << 2)))
 270 #define PPM_TASK_IND_REG_ADDR(x)        ((volatile u32*)(DANUBE_PPE + (((x) + 0x6200) << 2)))
 271 #define PPS_BRK_ADDR(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0x6300) << 2)))
 272 #define PPM_TIMER1_ADDR(x)              ((volatile u32*)(DANUBE_PPE + (((x) + 0x6400) << 2)))
 273 #define SB_RAM0_ADDR(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0x8000) << 2)))
 274 #define SB_RAM1_ADDR(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0x8400) << 2)))
 275 #define SB_RAM2_ADDR(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0x8C00) << 2)))
 276 #define SB_RAM3_ADDR(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0x9600) << 2)))
 277 #define QSB_CONF_REG(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0xC000) << 2)))
 278
 279 /*
 280  *  Host-PPE Communication Data Address Mapping
 281  */
 282 #define CFG_WRX_HTUTS                   PPM_INT_UNIT_ADDR(0x2400)   /*  WAN RX HTU Table Size, must be configured before enable PPE firmware.   */
 283 #define CFG_WRX_QNUM                    PPM_INT_UNIT_ADDR(0x2401)   /*  WAN RX Queue Number */
 284 #define CFG_WRX_DCHNUM                  PPM_INT_UNIT_ADDR(0x2402)   /*  WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware.   */
 285 #define CFG_WTX_DCHNUM                  PPM_INT_UNIT_ADDR(0x2403)   /*  WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware.  */
 286 #define CFG_WRDES_DELAY                 PPM_INT_UNIT_ADDR(0x2404)   /*  WAN Descriptor Write Delay, must be configured before enable PPE firmware.  */
 287 #define WRX_DMACH_ON                    PPM_INT_UNIT_ADDR(0x2405)   /*  WAN RX DMA Channel Enable, must be configured before enable PPE firmware.   */
 288 #define WTX_DMACH_ON                    PPM_INT_UNIT_ADDR(0x2406)   /*  WAN TX DMA Channel Enable, must be configured before enable PPE firmware.   */
 289 #define WRX_HUNT_BITTH                  PPM_INT_UNIT_ADDR(0x2407)   /*  WAN RX HUNT Threshold, must be between 2 to 8.  */
 290 #define WRX_QUEUE_CONFIG(i)             ((struct wrx_queue_config*)PPM_INT_UNIT_ADDR(0x2500 + (i) * 20))
 291 #define WRX_DMA_CHANNEL_CONFIG(i)       ((struct wrx_dma_channel_config*)PPM_INT_UNIT_ADDR(0x2640 + (i) * 7))
 292 #define WTX_PORT_CONFIG(i)              ((struct wtx_port_config*)PPM_INT_UNIT_ADDR(0x2440 + (i)))
 293 #define WTX_QUEUE_CONFIG(i)             ((struct wtx_queue_config*)PPM_INT_UNIT_ADDR(0x2710 + (i) * 27))
 294 #define WTX_DMA_CHANNEL_CONFIG(i)       ((struct wtx_dma_channel_config*)PPM_INT_UNIT_ADDR(0x2711 + (i) * 27))
 295 #define WAN_MIB_TABLE                   ((struct wan_mib_table*)PPM_INT_UNIT_ADDR(0x2410))
 296 #define HTU_ENTRY(i)                    ((struct htu_entry*)PPM_INT_UNIT_ADDR(0x2000 + (i)))
 297 #define HTU_MASK(i)                     ((struct htu_mask*)PPM_INT_UNIT_ADDR(0x2020 + (i)))
 298 #define HTU_RESULT(i)                   ((struct htu_result*)PPM_INT_UNIT_ADDR(0x2040 + (i)))
 299
 300 // DREG Idle Counters
 301 #define DREG_AT_CELL0                   PPE_REG_ADDR(0x0D24)
 302 #define DREG_AT_CELL1                   PPE_REG_ADDR(0x0D25)
 303 #define DREG_AT_IDLE_CNT0               PPE_REG_ADDR(0x0D26)
 304 #define DREG_AT_IDLE_CNT1               PPE_REG_ADDR(0x0D27)
 305 #define DREG_AR_CELL0                   PPE_REG_ADDR(0x0D68)
 306 #define DREG_AR_CELL1                   PPE_REG_ADDR(0x0D69)
 307 #define DREG_AR_IDLE_CNT0               PPE_REG_ADDR(0x0D6A)
 308 #define DREG_AR_IDLE_CNT1               PPE_REG_ADDR(0x0D6B)
 309 #define DREG_AR_AIIDLE_CNT0             PPE_REG_ADDR(0x0D6C)
 310 #define DREG_AR_AIIDLE_CNT1             PPE_REG_ADDR(0x0D6D)
 311 #define DREG_AR_BE_CNT0                 PPE_REG_ADDR(0x0D6E)
 312 #define DREG_AR_BE_CNT1                 PPE_REG_ADDR(0x0D6F)
 313
 314
 315 /*
 316  *  64-bit Data Type
 317  */
 318 typedef struct {
 319     unsigned int    h: 32;
 320     unsigned int    l: 32;
 321 } ppe_u64_t;
 322
 323 /*
 324  *  PPE ATM Cell Header
 325  */
 326 #if defined(__BIG_ENDIAN)
 327     struct uni_cell_header {
 328         unsigned int        gfc     :4;
 329         unsigned int        vpi     :8;
 330         unsigned int        vci     :16;
 331         unsigned int        pti     :3;
 332         unsigned int        clp     :1;
 333     };
 334 #else
 335     struct uni_cell_header {
 336         unsigned int        clp     :1;
 337         unsigned int        pti     :3;
 338         unsigned int        vci     :16;
 339         unsigned int        vpi     :8;
 340         unsigned int        gfc     :4;
 341     };
 342 #endif  //  defined(__BIG_ENDIAN)
 343
 344 /*
 345  *  Inband Header and Trailer
 346  */
 347 #if defined(__BIG_ENDIAN)
 348     struct rx_inband_trailer {
 349         /*  0 - 3h  */
 350         unsigned int        uu      :8;
 351         unsigned int        cpi     :8;
 352         unsigned int        stw_res1:4;
 353         unsigned int        stw_clp :1;
 354         unsigned int        stw_ec  :1;
 355         unsigned int        stw_uu  :1;
 356         unsigned int        stw_cpi :1;
 357         unsigned int        stw_ovz :1;
 358         unsigned int        stw_mfl :1;
 359         unsigned int        stw_usz :1;
 360         unsigned int        stw_crc :1;
 361         unsigned int        stw_il  :1;
 362         unsigned int        stw_ra  :1;
 363         unsigned int        stw_res2:2;
 364         /*  4 - 7h  */
 365         unsigned int        gfc     :4;
 366         unsigned int        vpi     :8;
 367         unsigned int        vci     :16;
 368         unsigned int        pti     :3;
 369         unsigned int        clp     :1;
 370     };
 371
 372     struct tx_inband_header {
 373         /*  0 - 3h  */
 374         unsigned int        gfc     :4;
 375         unsigned int        vpi     :8;
 376         unsigned int        vci     :16;
 377         unsigned int        pti     :3;
 378         unsigned int        clp     :1;
 379         /*  4 - 7h  */
 380         unsigned int        uu      :8;
 381         unsigned int        cpi     :8;
 382         unsigned int        pad     :8;
 383         unsigned int        res1    :8;
 384     };
 385 #else
 386     struct rx_inband_trailer {
 387         /*  0 - 3h  */
 388         unsigned int        stw_res2:2;
 389         unsigned int        stw_ra  :1;
 390         unsigned int        stw_il  :1;
 391         unsigned int        stw_crc :1;
 392         unsigned int        stw_usz :1;
 393         unsigned int        stw_mfl :1;
 394         unsigned int        stw_ovz :1;
 395         unsigned int        stw_cpi :1;
 396         unsigned int        stw_uu  :1;
 397         unsigned int        stw_ec  :1;
 398         unsigned int        stw_clp :1;
 399         unsigned int        stw_res1:4;
 400         unsigned int        cpi     :8;
 401         unsigned int        uu      :8;
 402         /*  4 - 7h  */
 403         unsigned int        clp     :1;
 404         unsigned int        pti     :3;
 405         unsigned int        vci     :16;
 406         unsigned int        vpi     :8;
 407         unsigned int        gfc     :4;
 408     };
 409
 410     struct tx_inband_header {
 411         /*  0 - 3h  */
 412         unsigned int        clp     :1;
 413         unsigned int        pti     :3;
 414         unsigned int        vci     :16;
 415         unsigned int        vpi     :8;
 416         unsigned int        gfc     :4;
 417         /*  4 - 7h  */
 418         unsigned int        res1    :8;
 419         unsigned int        pad     :8;
 420         unsigned int        cpi     :8;
 421         unsigned int        uu      :8;
 422     };
 423 #endif  //  defined(__BIG_ENDIAN)
 424
 425 struct wan_mib_table {
 426     unsigned int                     res1;
 427     unsigned int                     wrx_drophtu_cell;
 428     unsigned int                     wrx_dropdes_pdu;
 429     unsigned int                     wrx_correct_pdu;
 430     unsigned int                     wrx_err_pdu;
 431     unsigned int                     wrx_dropdes_cell;
 432     unsigned int                     wrx_correct_cell;
 433     unsigned int                     wrx_err_cell;
 434     unsigned int                     wrx_total_byte;
 435     unsigned int                     wtx_total_pdu;
 436     unsigned int                     wtx_total_cell;
 437     unsigned int                     wtx_total_byte;
 438 };
 439
 440 /*
 441  *  Internal Structure of Device
 442  */
 443 struct port {
 444     int                     connection_base;        /*  first connection ID (RX/TX queue ID)    */
 445     unsigned int                     max_connections;        /*  maximum connection number               */
 446     unsigned int                     connection_table;       /*  connection opened status, every bit     */
 447     unsigned int                     tx_max_cell_rate;       /*  maximum cell rate                       */
 448     unsigned int                     tx_current_cell_rate;   /*  currently used cell rate                */
 449 #if !defined(ENABLE_RX_QOS) || !ENABLE_RX_QOS
 450     int                     rx_dma_channel_base;    /*  first RX DMA channel ID                 */
 451     unsigned int                     rx_dma_channel_assigned;/*  totally RX DMA channels used            */
 452 #endif  //  !defined(ENABLE_RX_QOS) || !ENABLE_RX_QOS
 453     int                     oam_tx_queue;           /*  first TX queue ID of OAM cell           */
 454     struct atm_dev          *dev;
 455
 456 };
 457
 458 struct connection {
 459     struct atm_vcc          *vcc;                   /*  opened VCC                              */
 460     struct timespec         access_time;            /*  time when last F4/F5 user cell arrives  */
 461     unsigned int                     aal5_vcc_crc_err;       /*  number of packets with CRC error        */
 462     unsigned int                     aal5_vcc_oversize_sdu;  /*  number of packets with oversize error   */
 463     int                     rx_dma_channel;         /*  RX DMA channel ID assigned              */
 464     int                     port;                   /*  to which port the connection belongs    */
 465     unsigned int                     rx_pdu;
 466     unsigned int                     rx_err_pdu;
 467     unsigned int                     rx_sw_drop_pdu;
 468     unsigned int                     tx_pdu;
 469     unsigned int                     tx_err_pdu;
 470     unsigned int                     tx_hw_drop_pdu;
 471     unsigned int                     tx_sw_drop_pdu;
 472 };
 473
 474 struct ppe_dev {
 475     struct connection       connection[MAX_CONNECTION_NUMBER];
 476     struct port             port[ATM_PORT_NUMBER];
 477
 478     struct aal5 {
 479         unsigned char              padding_byte;               /*  padding byte pattern of AAL5 packet     */
 480         unsigned int             rx_max_packet_size;         /*  max AAL5 packet length                  */
 481         unsigned int             rx_min_packet_size;         /*  min AAL5 packet length                  */
 482         unsigned int             rx_buffer_size;             /*  max memory allocated for a AAL5 packet  */
 483         unsigned int             tx_max_packet_size;         /*  max AAL5 packet length                  */
 484         unsigned int             tx_min_packet_size;         /*  min AAL5 packet length                  */
 485         unsigned int             tx_buffer_size;             /*  max memory allocated for a AAL5 packet  */
 486         unsigned int    rx_drop_error_packet;       /*  1: drop error packet, 0: ignore errors  */
 487     }                       aal5;
 488
 489     struct qsb {
 490         unsigned int             tau;                        /*  cell delay variation due to concurrency */
 491         unsigned int             tstepc;                     /*  shceduler burst length                  */
 492         unsigned int             sbl;                        /*  time step                               */
 493     }                       qsb;
 494
 495     struct dma {
 496         unsigned int             rx_descriptor_number;       /*  number of RX descriptors                */
 497         unsigned int             tx_descriptor_number;       /*  number of TX descriptors                */
 498         unsigned int             rx_clp1_desc_threshold;     /*  threshold to drop cells with CLP1       */
 499         unsigned int             write_descriptor_delay;     /*  delay on descriptor write path          */
 500         unsigned int             rx_total_channel_used;      /*  total RX channel used                   */
 501         void            *rx_descriptor_addr;        /*  base address of memory allocated for    */
 502         struct rx_descriptor
 503                         *rx_descriptor_base;        /*  base address of RX descriptors          */
 504         int             rx_desc_read_pos[MAX_RX_DMA_CHANNEL_NUMBER];    /*  first RX descriptor */
 505                                                                         /*  to be read          */
 506 //        struct sk_buff  **rx_skb_pointers;          /*  base address of RX sk_buff pointers     */
 507
 508 #if defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
 509         long            rx_weight[MAX_RX_DMA_CHANNEL_NUMBER];           /*  RX schedule weight  */
 510         long            rx_default_weight[MAX_RX_DMA_CHANNEL_NUMBER];   /*  default weight      */
 511 #endif
 512
 513         unsigned int             tx_total_channel_used;      /*  total TX channel used                   */
 514         void            *tx_descriptor_addr;        /*  base address of memory allocated for    */
 515                                                     /*  TX descriptors                          */
 516         struct tx_descriptor
 517                         *tx_descriptor_base;        /*  base address of TX descriptors          */
 518         int             tx_desc_alloc_pos[MAX_TX_DMA_CHANNEL_NUMBER];   /*  first TX descriptor */
 519                                                                         /*  could be allocated  */
 520 //        int             tx_desc_alloc_num[MAX_TX_DMA_CHANNEL_NUMBER];   /*  number of allocated */
 521 //                                                                        /*  TX descriptors      */
 522         int             tx_desc_alloc_flag[MAX_TX_DMA_CHANNEL_NUMBER];  /*  at least one TX     */
 523                                                                         /*  descriptor is alloc */
 524 //        int             tx_desc_send_pos[MAX_TX_DMA_CHANNEL_NUMBER];    /*  first TX descriptor */
 525 //                                                                        /*  to be send          */
 526         int             tx_desc_release_pos[MAX_TX_DMA_CHANNEL_NUMBER]; /*  first TX descriptor */
 527                                                                         /*  to be released      */
 528         struct sk_buff  **tx_skb_pointers;          /*  base address of TX sk_buff pointers     */
 529     }                       dma;
 530
 531     struct mib {
 532         ppe_u64_t       wrx_total_byte;             /*  bit-64 extention of MIB table member    */
 533         ppe_u64_t       wtx_total_byte;             /*  bit-64 extention of MIB talbe member    */
 534
 535         unsigned int             wrx_pdu;                    /*  successfully received AAL5 packet       */
 536         unsigned int             wrx_drop_pdu;               /*  AAL5 packet dropped by driver on RX     */
 537         unsigned int             wtx_err_pdu;                /*  error AAL5 packet                       */
 538         unsigned int             wtx_drop_pdu;               /*  AAL5 packet dropped by driver on TX     */
 539     }                       mib;
 540     struct wan_mib_table    prev_mib;
 541
 542     int                     oam_rx_queue;           /*  RX queue ID of OAM cell                 */
 543     int                     oam_rx_dma_channel;     /*  RX DMA channel ID of OAM cell           */
 544     int                     max_connections;        /*  total connections available             */
 545
 546     struct semaphore        sem;                    /*  lock used by open/close function        */
 547 };
 548
 549 /*
 550  *  Host-PPE Communication Data Structure
 551  */
 552 #if defined(__BIG_ENDIAN)
 553     struct wrx_queue_config {
 554         /*  0h  */
 555         unsigned int    res2        :27;
 556         unsigned int    dmach       :4;
 557         unsigned int    errdp       :1;
 558         /*  1h  */
 559         unsigned int    oversize    :16;
 560         unsigned int    undersize   :16;
 561         /*  2h  */
 562         unsigned int    res1        :16;
 563         unsigned int    mfs         :16;
 564         /*  3h  */
 565         unsigned int    uumask      :8;
 566         unsigned int    cpimask     :8;
 567         unsigned int    uuexp       :8;
 568         unsigned int    cpiexp      :8;
 569     };
 570
 571     struct wtx_port_config {
 572         unsigned int    res1        :27;
 573         unsigned int    qid         :4;
 574         unsigned int    qsben       :1;
 575     };
 576
 577     struct wtx_queue_config {
 578         unsigned int    res1        :25;
 579         unsigned int    sbid        :1;
 580         unsigned int    res2        :3;
 581         unsigned int    type        :2;
 582         unsigned int    qsben       :1;
 583     };
 584
 585     struct wrx_dma_channel_config {
 586         /*  0h  */
 587         unsigned int    res1        :1;
 588         unsigned int    mode        :2;
 589         unsigned int    rlcfg       :1;
 590         unsigned int    desba       :28;
 591         /*  1h  */
 592         unsigned int    chrl        :16;
 593         unsigned int    clp1th      :16;
 594         /*  2h  */
 595         unsigned int    deslen      :16;
 596         unsigned int    vlddes      :16;
 597     };
 598
 599     struct wtx_dma_channel_config {
 600         /*  0h  */
 601         unsigned int    res2        :1;
 602         unsigned int    mode        :2;
 603         unsigned int    res3        :1;
 604         unsigned int    desba       :28;
 605         /*  1h  */
 606         unsigned int    res1        :32;
 607         /*  2h  */
 608         unsigned int    deslen      :16;
 609         unsigned int    vlddes      :16;
 610     };
 611
 612     struct htu_entry {
 613         unsigned int    res1        :2;
 614         unsigned int    pid         :2;
 615         unsigned int    vpi         :8;
 616         unsigned int    vci         :16;
 617         unsigned int    pti         :3;
 618         unsigned int    vld         :1;
 619     };
 620
 621     struct htu_mask {
 622         unsigned int    set         :2;
 623         unsigned int    pid_mask    :2;
 624         unsigned int    vpi_mask    :8;
 625         unsigned int    vci_mask    :16;
 626         unsigned int    pti_mask    :3;
 627         unsigned int    clear       :1;
 628     };
 629
 630    struct htu_result {
 631         unsigned int    res1        :12;
 632         unsigned int    cellid      :4;
 633         unsigned int    res2        :5;
 634         unsigned int    type        :1;
 635         unsigned int    ven         :1;
 636         unsigned int    res3        :5;
 637         unsigned int    qid         :4;
 638     };
 639
 640     struct rx_descriptor {
 641         /*  0 - 3h  */
 642         unsigned int    own         :1;
 643         unsigned int    c           :1;
 644         unsigned int    sop         :1;
 645         unsigned int    eop         :1;
 646         unsigned int    res1        :3;
 647         unsigned int    byteoff     :2;
 648         unsigned int    res2        :2;
 649         unsigned int    id          :4;
 650         unsigned int    err         :1;
 651         unsigned int    datalen     :16;
 652         /*  4 - 7h  */
 653         unsigned int    res3        :4;
 654         unsigned int    dataptr     :28;
 655     };
 656
 657     struct tx_descriptor {
 658         /*  0 - 3h  */
 659         unsigned int    own         :1;
 660         unsigned int    c           :1;
 661         unsigned int    sop         :1;
 662         unsigned int    eop         :1;
 663         unsigned int    byteoff     :5;
 664         unsigned int    res1        :5;
 665         unsigned int    iscell      :1;
 666         unsigned int    clp         :1;
 667         unsigned int    datalen     :16;
 668         /*  4 - 7h  */
 669         unsigned int    res2        :4;
 670         unsigned int    dataptr     :28;
 671     };
 672 #else
 673     struct wrx_queue_config {
 674         /*  0h  */
 675         unsigned int    errdp       :1;
 676         unsigned int    dmach       :4;
 677         unsigned int    res2        :27;
 678         /*  1h  */
 679         unsigned int    undersize   :16;
 680         unsigned int    oversize    :16;
 681         /*  2h  */
 682         unsigned int    mfs         :16;
 683         unsigned int    res1        :16;
 684         /*  3h  */
 685         unsigned int    cpiexp      :8;
 686         unsigned int    uuexp       :8;
 687         unsigned int    cpimask     :8;
 688         unsigned int    uumask      :8;
 689     };
 690
 691     struct wtx_port_config {
 692         unsigned int    qsben       :1;
 693         unsigned int    qid         :4;
 694         unsigned int    res1        :27;
 695     };
 696
 697     struct wtx_queue_config {
 698         unsigned int    qsben       :1;
 699         unsigned int    type        :2;
 700         unsigned int    res2        :3;
 701         unsigned int    sbid        :1;
 702         unsigned int    res1        :25;
 703     };
 704
 705     struct wrx_dma_channel_config
 706     {
 707         /*  0h  */
 708         unsigned int    desba       :28;
 709         unsigned int    rlcfg       :1;
 710         unsigned int    mode        :2;
 711         unsigned int    res1        :1;
 712         /*  1h  */
 713         unsigned int    clp1th      :16;
 714         unsigned int    chrl        :16;
 715         /*  2h  */
 716         unsigned int    vlddes      :16;
 717         unsigned int    deslen      :16;
 718     };
 719
 720     struct wtx_dma_channel_config {
 721         /*  0h  */
 722         unsigned int    desba       :28;
 723         unsigned int    res3        :1;
 724         unsigned int    mode        :2;
 725         unsigned int    res2        :1;
 726         /*  1h  */
 727         unsigned int    res1        :32;
 728         /*  2h  */
 729         unsigned int    vlddes      :16;
 730         unsigned int    deslen      :16;
 731     };
 732
 733     struct rx_descriptor {
 734         /*  4 - 7h  */
 735         unsigned int    dataptr     :28;
 736         unsigned int    res3        :4;
 737         /*  0 - 3h  */
 738         unsigned int    datalen     :16;
 739         unsigned int    err         :1;
 740         unsigned int    id          :4;
 741         unsigned int    res2        :2;
 742         unsigned int    byteoff     :2;
 743         unsigned int    res1        :3;
 744         unsigned int    eop         :1;
 745         unsigned int    sop         :1;
 746         unsigned int    c           :1;
 747         unsigned int    own         :1;
 748     };
 749
 750     struct tx_descriptor {
 751         /*  4 - 7h  */
 752         unsigned int    dataptr     :28;
 753         unsigned int    res2        :4;
 754         /*  0 - 3h  */
 755         unsigned int    datalen     :16;
 756         unsigned int    clp         :1;
 757         unsigned int    iscell      :1;
 758         unsigned int    res1        :5;
 759         unsigned int    byteoff     :5;
 760         unsigned int    eop         :1;
 761         unsigned int    sop         :1;
 762         unsigned int    c           :1;
 763         unsigned int    own         :1;
 764     };
 765 #endif  //  defined(__BIG_ENDIAN)
 766
 767 /*
 768  *  QSB Queue Parameter Table Entry and Queue VBR Parameter Table Entry
 769  */
 770 #if defined(__BIG_ENDIAN)
 771     union qsb_queue_parameter_table {
 772         struct {
 773             unsigned int    res1    :1;
 774             unsigned int    vbr     :1;
 775             unsigned int    wfqf    :14;
 776             unsigned int    tp      :16;
 777         }               bit;
 778         unsigned int             dword;
 779     };
 780
 781     union qsb_queue_vbr_parameter_table {
 782         struct {
 783             unsigned int    taus    :16;
 784             unsigned int    ts      :16;
 785         }               bit;
 786         unsigned int             dword;
 787     };
 788 #else
 789     union qsb_queue_parameter_table {
 790         struct {
 791             unsigned int    tp      :16;
 792             unsigned int    wfqf    :14;
 793             unsigned int    vbr     :1;
 794             unsigned int    res1    :1;
 795         }               bit;
 796         unsigned int             dword;
 797     };
 798
 799     union qsb_queue_vbr_parameter_table {
 800         struct {
 801             unsigned int    ts      :16;
 802             unsigned int    taus    :16;
 803         }               bit;
 804         unsigned int             dword;
 805     };
 806 #endif  //  defined(__BIG_ENDIAN)
 807
 808
 809 typedef enum
 810 {
 811     IAD_ATM_CBR     = 6,                                                /* IAD_ATM_PRI_HIGH,                                                    */
 812     IAD_ATM_VBR_RT  = 4,                                                /* IAD_ATM_PRI_MED_HIGH,        VBR, Real-Time          */
 813     IAD_ATM_VBR_NRT = 2,                                                /* IAD_ATM_PRI_MED_LOW,     VBR, Non-Real-Time  */
 814     IAD_ATM_UBR     = 0,                                                /* IAD_ATM_PRI_LOW                                                              */
 815 } iad_atmServiceCategory;
 816
 817 typedef unsigned int iad_atmDiffServCategory;
 818
 819 typedef struct
 820 {
 821    int cellRate;
 822    int round;   /* IAD_ATM_RATE_CEILING, IAD_ATM_RATE_FLOOR */
 823 } iad_atmCellRateDesc;
 824
 825 typedef struct
 826 {
 827     unsigned int               phyID;          /* IAD_ATM_PHY0, IAD_ATM_PHY1 */
 828     unsigned int               txQHnd;         /* Tx HW Q */
 829     union _pri
 830     {
 831         int                     priority;       /* TS Q:    4 priorities: IAD_ATM_PRI_HIGH, IAD_ATM_PRI_MED_HIGH, IAD_ATM_PRI_MED_LOW, IAD_ATM_PRI_LOW
 832                                                   non-TS Q: 8 priorities: IAD_ATM_PRI_LEVEL_7, IAD_ATM_PRI_LEVEL_6,..., IAD_ATM_PRI_LEVEL_0 */
 833         iad_atmServiceCategory  qosClass;       /* IAD_ATM_CBR, IAD_ATM_VBR_RT, IAD_ATM_VBR_NRT, IAD_ATM_UBR */
 834         iad_atmDiffServCategory diffServClass;  /* IP_QOS */
 835     } srvCat; /* service category */
 836     iad_atmCellRateDesc         pcr;            /* Peak Cell Rate */
 837     iad_atmCellRateDesc         scr;            /* Sustained Cell Rate. */
 838     iad_atmCellRateDesc         mcr;            /* Minimum Cell Rate, not used */
 839     int                         mbs;            /* maximum bursting size in cells */
 840     int                         isPrioritize;   /* TRUE: This flow is of the higher priority than the flows of the same QOS category.(Use MCR to boost priority) */
 841 } iad_atmTrfPar; /* Tx Traffic Parameters */
 842
 843 typedef struct
 844 {
 845     unsigned int    txGrpId;
 846     unsigned int    flowId;
 847     iad_atmTrfPar   trfPar;
 848 } Atm_Ictl_Flow_Set;
 849
 850 typedef struct
 851 {
 852     unsigned int    txGrpId;
 853     unsigned int    vpi;
 854     unsigned int    vci;
 855
 856     unsigned int    encaps;
 857     unsigned int    proto;
 858
 859 } Atm_Ictl_Open_Vcc;
 860
 861 typedef struct
 862 {
 863     struct atm_vcc                      vcc;
 864         unsigned int                    valid;
 865         unsigned int                    on;
 866     unsigned int                        vccIndex; /* 0~7 */
 867         unsigned int                    itf;
 868     struct net_device_stats     stats;
 869 } Atm_Priv;
 870
 871
 872 extern struct ppe_dev ppe_dev;
 873
 874
 875 int pp32_start(void);
 876 void pp32_stop(void);
 877 void init_rx_tables(void);
 878 void init_tx_tables(void);
 879 struct sk_buff* alloc_skb_rx(void);
 880 struct sk_buff* alloc_skb_tx(unsigned int);
 881 void resize_skb_rx(struct sk_buff *, unsigned int, int);
 882 struct sk_buff* atm_alloc_tx(struct atm_vcc *, unsigned int);
 883 void atm_free_tx_skb_vcc(struct sk_buff *);
 884 int alloc_tx_connection(int);
 885 int ppe_open(struct atm_vcc *vcc);
 886 void ppe_close(struct atm_vcc *vcc);
 887 int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg);
 888 int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb);
 889 int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags);
 890 int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags);
 891 irqreturn_t mailbox_irq_handler(int, void *);
 892 int find_vcc(struct atm_vcc *vcc);
 893 int find_vpi(unsigned int vpi);
 894 int find_vpivci(unsigned int vpi, unsigned int vci);
 895 void mailbox_signal(unsigned int channel, int is_tx);
 896