package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vr9.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_ptm_vr9.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : PTM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : PTM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24
  25
  26 /*
  27  * ####################################
  28  *              Head File
  29  * ####################################
  30  */
  31
  32 /*
  33  *  Common Head File
  34  */
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/version.h>
  38 #include <linux/types.h>
  39 #include <linux/errno.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/init.h>
  42 #include <linux/ioctl.h>
  43 #include <asm/delay.h>
  44
  45 /*
  46  *  Chip Specific Head File
  47  */
  48 #include "ifxmips_ptm_vdsl.h"
  49 #include "ifxmips_ptm_fw_vr9.h"
  50
  51 #include <lantiq_soc.h>
  52
  53 static inline void init_pmu(void);
  54 static inline void uninit_pmu(void);
  55 static inline void reset_ppe(void);
  56 static inline void init_pdma(void);
  57 static inline void init_mailbox(void);
  58 static inline void init_atm_tc(void);
  59 static inline void clear_share_buffer(void);
  60
  61 #define IFX_PMU_MODULE_PPE_SLL01  BIT(19)
  62 #define IFX_PMU_MODULE_PPE_TC     BIT(21)
  63 #define IFX_PMU_MODULE_PPE_EMA    BIT(22)
  64 #define IFX_PMU_MODULE_PPE_QSB    BIT(18)
  65 #define IFX_PMU_MODULE_AHBS       BIT(13)
  66 #define IFX_PMU_MODULE_DSL_DFE    BIT(9)
  67
  68
  69 static inline void init_pmu(void)
  70 {
  71         ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
  72                 IFX_PMU_MODULE_PPE_TC |
  73                 IFX_PMU_MODULE_PPE_EMA |
  74                 IFX_PMU_MODULE_AHBS |
  75                 IFX_PMU_MODULE_DSL_DFE);
  76
  77 }
  78
  79 static inline void uninit_pmu(void)
  80 {
  81 }
  82
  83 static inline void reset_ppe(void)
  84 {
  85 /*#ifdef MODULE
  86     //  reset PPE
  87     ifx_rcu_rst(IFX_RCU_DOMAIN_DSLDFE, IFX_RCU_MODULE_PTM);
  88     udelay(1000);
  89     ifx_rcu_rst(IFX_RCU_DOMAIN_DSLTC, IFX_RCU_MODULE_PTM);
  90     udelay(1000);
  91     ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_PTM);
  92     udelay(1000);
  93     *PP32_SRST &= ~0x000303CF;
  94     udelay(1000);
  95     *PP32_SRST |= 0x000303CF;
  96     udelay(1000);
  97 #endif*/
  98 }
  99
 100 static inline void init_pdma(void)
 101 {
 102     IFX_REG_W32(0x00000001, PDMA_CFG);
 103     IFX_REG_W32(0x00082C00, PDMA_RX_CTX_CFG);
 104     IFX_REG_W32(0x00081B00, PDMA_TX_CTX_CFG);
 105     IFX_REG_W32(0x02040604, PDMA_RX_MAX_LEN_REG);
 106     IFX_REG_W32(0x000F003F, PDMA_RX_DELAY_CFG);
 107
 108     IFX_REG_W32(0x00000011, SAR_MODE_CFG);
 109     IFX_REG_W32(0x00082A00, SAR_RX_CTX_CFG);
 110     IFX_REG_W32(0x00082E00, SAR_TX_CTX_CFG);
 111     IFX_REG_W32(0x00001021, SAR_POLY_CFG_SET0);
 112     IFX_REG_W32(0x1EDC6F41, SAR_POLY_CFG_SET1);
 113     IFX_REG_W32(0x04C11DB7, SAR_POLY_CFG_SET2);
 114     IFX_REG_W32(0x00000F3E, SAR_CRC_SIZE_CFG);
 115
 116     IFX_REG_W32(0x01001900, SAR_PDMA_RX_CMDBUF_CFG);
 117     IFX_REG_W32(0x01001A00, SAR_PDMA_TX_CMDBUF_CFG);
 118 }
 119
 120 static inline void init_mailbox(void)
 121 {
 122     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
 123     IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
 124     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
 125     IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
 126 }
 127
 128 static inline void init_atm_tc(void)
 129 {
 130     IFX_REG_W32(0x00010040, SFSM_CFG0);
 131     IFX_REG_W32(0x00010040, SFSM_CFG1);
 132     IFX_REG_W32(0x00020000, SFSM_PGCNT0);
 133     IFX_REG_W32(0x00020000, SFSM_PGCNT1);
 134     IFX_REG_W32(0x00000000, DREG_AT_IDLE0);
 135     IFX_REG_W32(0x00000000, DREG_AT_IDLE1);
 136     IFX_REG_W32(0x00000000, DREG_AR_IDLE0);
 137     IFX_REG_W32(0x00000000, DREG_AR_IDLE1);
 138     IFX_REG_W32(0x0000080C, DREG_B0_LADR);
 139     IFX_REG_W32(0x0000080C, DREG_B1_LADR);
 140
 141     IFX_REG_W32(0x000001F0, DREG_AR_CFG0);
 142     IFX_REG_W32(0x000001F0, DREG_AR_CFG1);
 143     IFX_REG_W32(0x000001E0, DREG_AT_CFG0);
 144     IFX_REG_W32(0x000001E0, DREG_AT_CFG1);
 145
 146     /*  clear sync state    */
 147     //IFX_REG_W32(0, SFSM_STATE0);
 148     //IFX_REG_W32(0, SFSM_STATE1);
 149
 150     IFX_REG_W32_MASK(0, 1 << 14, SFSM_CFG0);    //  enable SFSM storing
 151     IFX_REG_W32_MASK(0, 1 << 14, SFSM_CFG1);
 152
 153     IFX_REG_W32_MASK(0, 1 << 15, SFSM_CFG0);    //  HW keep the IDLE cells in RTHA buffer
 154     IFX_REG_W32_MASK(0, 1 << 15, SFSM_CFG1);
 155
 156     IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);
 157     IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);
 158     IFX_REG_W32(0x00030028, FFSM_CFG0);         //  Force_idle
 159     IFX_REG_W32(0x00030028, FFSM_CFG1);
 160 }
 161
 162 static inline void clear_share_buffer(void)
 163 {
 164     volatile u32 *p;
 165     unsigned int i;
 166
 167     p = SB_RAM0_ADDR(0);
 168     for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
 169         IFX_REG_W32(0, p++);
 170
 171     p = SB_RAM6_ADDR(0);
 172     for ( i = 0; i < SB_RAM6_DWLEN; i++ )
 173         IFX_REG_W32(0, p++);
 174 }
 175
 176 /*
 177  *  Description:
 178  *    Download PPE firmware binary code.
 179  *  Input:
 180  *    pp32      --- int, which pp32 core
 181  *    src       --- u32 *, binary code buffer
 182  *    dword_len --- unsigned int, binary code length in DWORD (32-bit)
 183  *  Output:
 184  *    int       --- 0:    Success
 185  *                  else:           Error Code
 186  */
 187 static inline int pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
 188 {
 189     unsigned int clr, set;
 190     volatile u32 *dest;
 191
 192     if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
 193         || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
 194         return -1;
 195
 196     clr = pp32 ? 0xF0 : 0x0F;
 197     if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
 198         set = pp32 ? (3 << 6): (2 << 2);
 199     else
 200         set = 0x00;
 201     IFX_REG_W32_MASK(clr, set, CDM_CFG);
 202
 203     /*  copy code   */
 204     dest = CDM_CODE_MEMORY(pp32, 0);
 205     while ( code_dword_len-- > 0 )
 206         IFX_REG_W32(*code_src++, dest++);
 207
 208     /*  copy data   */
 209     dest = CDM_DATA_MEMORY(pp32, 0);
 210     while ( data_dword_len-- > 0 )
 211         IFX_REG_W32(*data_src++, dest++);
 212
 213     return 0;
 214 }
 215
 216
 217
 218 /*
 219  * ####################################
 220  *           Global Function
 221  * ####################################
 222  */
 223
 224 extern void ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *minor)
 225 {
 226     ASSERT(major != NULL, "pointer is NULL");
 227     ASSERT(minor != NULL, "pointer is NULL");
 228
 229     *major = FW_VER_ID->major;
 230     *minor = FW_VER_ID->minor;
 231 }
 232
 233 void ifx_ptm_init_chip(void)
 234 {
 235     init_pmu();
 236
 237     reset_ppe();
 238
 239     init_pdma();
 240
 241     init_mailbox();
 242
 243     init_atm_tc();
 244
 245     clear_share_buffer();
 246 }
 247
 248 void ifx_ptm_uninit_chip(void)
 249 {
 250     uninit_pmu();
 251 }
 252
 253 /*
 254  *  Description:
 255  *    Initialize and start up PP32.
 256  *  Input:
 257  *    none
 258  *  Output:
 259  *    int  --- 0: Success
 260  *             else:        Error Code
 261  */
 262 int ifx_pp32_start(int pp32)
 263 {
 264     unsigned int mask = 1 << (pp32 << 4);
 265     int ret;
 266
 267     /*  download firmware   */
 268     ret = pp32_download_code(pp32, firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
 269     if ( ret != 0 )
 270         return ret;
 271
 272     /*  run PP32    */
 273     IFX_REG_W32_MASK(mask, 0, PP32_FREEZE);
 274
 275     /*  idle for a while to let PP32 init itself    */
 276     udelay(10);
 277
 278     return 0;
 279 }
 280
 281 /*
 282  *  Description:
 283  *    Halt PP32.
 284  *  Input:
 285  *    none
 286  *  Output:
 287  *    none
 288  */
 289 void ifx_pp32_stop(int pp32)
 290 {
 291     unsigned int mask = 1 << (pp32 << 4);
 292
 293     /*  halt PP32   */
 294     IFX_REG_W32_MASK(0, mask, PP32_FREEZE);
 295 }