package/kernel/lantiq/ltq-vmmc/patches/500-ar9_vr9.patch

   1 --- drv_vmmc-1.9.0_orig/src/mps/drv_mps_vmmc_ar9.c      2010-03-08 14:08:30.000000000 +0100
   2 +++ drv_vmmc-1.9.0/src/mps/drv_mps_vmmc_ar9.c   2014-10-14 21:49:20.000000000 +0200
   3 @@ -30,15 +30,24 @@
   4  #include "ifxos_interrupt.h"
   5
   6  /* board specific headers */
   7 +#if !defined CONFIG_LANTIQ
   8  #include <asm/ifx/ifx_regs.h>
   9  #include <asm/ifx_vpe.h>
  10  #include <asm/ifx/ifx_gpio.h>
  11 +#endif
  12 +
  13 +#include <lantiq_soc.h>
  14 +#include <vpe.h>
  15
  16  /* device specific headers */
  17  #include "drv_mps_vmmc.h"
  18  #include "drv_mps_vmmc_dbg.h"
  19  #include "drv_mps_vmmc_device.h"
  20
  21 +const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n) = NULL;
  22 +
  23 +#define IFX_MPS_SRAM IFXMIPS_MPS_SRAM
  24 +
  25  /* ============================= */
  26  /* Local Macros & Definitions    */
  27  /* ============================= */
  28 @@ -108,6 +108,7 @@
  29   */
  30  IFX_int32_t ifx_mps_fw_wdog_start_ar9()
  31  {
  32 +   return IFX_SUCCESS; /* FIXME - Disable start wdog... */
  33     /* vpe1_wdog_ctr should be set up in u-boot as
  34        "vpe1_wdog_ctr_addr=0xBF2001B0"; protection from incorrect or missing
  35        setting */
  36 @@ -292,7 +302,19 @@
  37           decryption. Subtract sizeof(u32) from length to avoid decryption
  38           of data beyond the FW image code */
  39        pFWDwnld->length -= sizeof(IFX_uint32_t);
  40 +      switch(ltq_soc_type()) {
  41 +          case SOC_TYPE_AR9:
  42 +                  ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf0017c4;
  43 +                  break;
  44 +          case SOC_TYPE_VR9:
  45 +                  ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf001ea4;
  46 +                  break;
  47 +          case SOC_TYPE_VR9_2:
  48 +                  ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf001f38;
  49 +                  break;
  50 +      }
  51 +      if (ifx_bsp_basic_mps_decrypt)
  52        ifx_bsp_basic_mps_decrypt((IFX_uint32_t)cpu1_base_addr, pFWDwnld->length);
  53     }
  54
  55     /* calculate CRC32 checksum over downloaded image */
  56 @@ -306,7 +320,7 @@
  57           TRACE (MPS, DBG_LEVEL_HIGH,
  58                  ("MPS: FW checksum error: img=0x%08x calc=0x%08x\r\n",
  59                  pFW_img_data->crc32, cksum));
  60 -         return IFX_ERROR;
  61 +         /* return IFX_ERROR; -- FIXME */
  62        }
  63     }
  64     else
  65 @@ -454,62 +473,62 @@
  66  #endif /* DEBUG */
  67
  68     /* reset SmartSLIC */
  69 -   IFXOS_LOCKINT (flags);
  70 -   if (ifx_gpio_pin_reserve
  71 -       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
  72 -   {
  73 -      TRACE (MPS, DBG_LEVEL_HIGH,
  74 -             (KERN_ERR "[%s %s %d]: GPIO port/pin reservation error.\r\n",
  75 -              __FILE__, __func__, __LINE__));
  76 -   }
  77 +//   IFXOS_LOCKINT (flags);
  78 +//   if (ifx_gpio_pin_reserve
  79 +//       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
  80 +//   {
  81 +//      TRACE (MPS, DBG_LEVEL_HIGH,
  82 +//             (KERN_ERR "[%s %s %d]: GPIO port/pin reservation error.\r\n",
  83 +//              __FILE__, __func__, __LINE__));
  84 +//   }
  85     /* P1_ALTSEL0.15 = 0 */
  86 -   if (ifx_gpio_altsel0_clear
  87 -       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
  88 -   {
  89 -      TRACE (MPS, DBG_LEVEL_HIGH,
  90 -             (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL0.\r\n", __FILE__,
  91 -              __func__, __LINE__));
  92 -   }
  93 +//   if (ifx_gpio_altsel0_clear
  94 +//       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
  95 +//   {
  96 +//      TRACE (MPS, DBG_LEVEL_HIGH,
  97 +//             (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL0.\r\n", __FILE__,
  98 +//              __func__, __LINE__));
  99 +//   }
 100     /* P1_ALTSEL1.15 = 0 */
 101 -   if (ifx_gpio_altsel1_clear
 102 -       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
 103 -   {
 104 -      TRACE (MPS, DBG_LEVEL_HIGH,
 105 -             (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL1.\r\n", __FILE__,
 106 -              __func__, __LINE__));
 107 -   }
 108 +//   if (ifx_gpio_altsel1_clear
 109 +//       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
 110 +//   {
 111 +//      TRACE (MPS, DBG_LEVEL_HIGH,
 112 +//             (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL1.\r\n", __FILE__,
 113 +//              __func__, __LINE__));
 114 +//   }
 115     /* P1_DIR.15 = 1 */
 116 -   if (ifx_gpio_dir_out_set
 117 -       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
 118 -   {
 119 -      TRACE (MPS, DBG_LEVEL_HIGH,
 120 -             (KERN_ERR "[%s %s %d]: GPIO error setting DIR.\r\n", __FILE__,
 121 -              __func__, __LINE__));
 122 -   }
 123 +//   if (ifx_gpio_dir_out_set
 124 +//       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
 125 +//   {
 126 +//      TRACE (MPS, DBG_LEVEL_HIGH,
 127 +//             (KERN_ERR "[%s %s %d]: GPIO error setting DIR.\r\n", __FILE__,
 128 +//              __func__, __LINE__));
 129 +//   }
 130     /* P1_OD.15 = 1 */
 131 -   if (ifx_gpio_open_drain_set
 132 -       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
 133 -   {
 134 -      TRACE (MPS, DBG_LEVEL_HIGH,
 135 -             (KERN_ERR "[%s %s %d]: GPIO error setting OD.\r\n", __FILE__,
 136 -              __func__, __LINE__));
 137 -   }
 138 +//   if (ifx_gpio_open_drain_set
 139 +//       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
 140 +//   {
 141 +//      TRACE (MPS, DBG_LEVEL_HIGH,
 142 +//             (KERN_ERR "[%s %s %d]: GPIO error setting OD.\r\n", __FILE__,
 143 +//              __func__, __LINE__));
 144 +//   }
 145     /* P1_OUT.15 = 0 */
 146 -   if (ifx_gpio_output_clear
 147 -       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
 148 -   {
 149 -      TRACE (MPS, DBG_LEVEL_HIGH,
 150 -             (KERN_ERR "[%s %s %d]: GPIO error clearing OUT.\r\n", __FILE__,
 151 -              __func__, __LINE__));
 152 -   }
 153 -   if (ifx_gpio_pin_free
 154 -       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
 155 -   {
 156 -      TRACE (MPS, DBG_LEVEL_HIGH,
 157 -             (KERN_ERR "[%s %s %d]: GPIO port/pin freeing error.\r\n", __FILE__,
 158 -              __func__, __LINE__));
 159 -   }
 160 -   IFXOS_UNLOCKINT (flags);
 161 +//   if (ifx_gpio_output_clear
 162 +//       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
 163 +//   {
 164 +//      TRACE (MPS, DBG_LEVEL_HIGH,
 165 +//             (KERN_ERR "[%s %s %d]: GPIO error clearing OUT.\r\n", __FILE__,
 166 +//              __func__, __LINE__));
 167 +//   }
 168 +//   if (ifx_gpio_pin_free
 169 +//       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
 170 +//   {
 171 +//      TRACE (MPS, DBG_LEVEL_HIGH,
 172 +//             (KERN_ERR "[%s %s %d]: GPIO port/pin freeing error.\r\n", __FILE__,
 173 +//              __func__, __LINE__));
 174 +//   }
 175 +//   IFXOS_UNLOCKINT (flags);
 176
 177     /* recalculate and compare the firmware checksum */
 178     ifx_mps_fw_crc_compare(cpu1_base_addr, pFW_img_data);
 179 --- drv_vmmc-1.9.0_orig/src/drv_vmmc_amazon_s.h 2009-12-03 17:20:34.000000000 +0100
 180 +++ drv_vmmc-1.9.0/src/drv_vmmc_amazon_s.h      2014-10-16 10:30:48.000000000 +0200
 181 @@ -16,7 +16,7 @@
 182
 183
 184  #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 185 -#include <asm/ifx/ifx_gpio.h>
 186 +//#include <asm/ifx/ifx_gpio.h>
 187  #else
 188  #error no system selected
 189  #endif
 190 @@ -27,45 +27,6 @@
 191  */
 192  #define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \
 193  do { \
 194 -   ret = VMMC_statusOk; \
 195 -   /* Reserve P0.0 as TDM/FSC */ \
 196 -   if (!GPIOreserved) \
 197 -      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
 198 -   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
 199 -   ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
 200 -   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\
 201 -   \
 202 -   /* Reserve P1.9 as TDM/DO */ \
 203 -   if (!GPIOreserved) \
 204 -      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
 205 -   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
 206 -   ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
 207 -   ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
 208 -   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
 209 -   \
 210 -   /* Reserve P2.9 as TDM/DI */ \
 211 -   if (!GPIOreserved) \
 212 -      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
 213 -   ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
 214 -   ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID);\
 215 -   ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
 216 -   \
 217 -   /* Reserve P2.8 as TDM/DCL */ \
 218 -   if (!GPIOreserved) \
 219 -      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
 220 -   ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
 221 -   ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
 222 -   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
 223 -   \
 224 -   if (mode == 2) { \
 225 -      /* TDM/FSC+DCL Master */ \
 226 -      ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
 227 -      ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
 228 -   } else { \
 229 -      /* TDM/FSC+DCL Slave */ \
 230 -      ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
 231 -      ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
 232 -   } \
 233  } while(0);
 234
 235  /**
 236 @@ -73,11 +34,6 @@
 237  */
 238  #define VMMC_DRIVER_UNLOAD_HOOK(ret) \
 239  do { \
 240 -   ret = VMMC_statusOk; \
 241 -   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
 242 -   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
 243 -   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
 244 -   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
 245  } while (0)
 246
 247  #endif /* _DRV_VMMC_AMAZON_S_H */