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3545935f5153dce705bd603456a6686d673bcc89
[openwrt/svn-archive/archive.git] / package / mac80211 / patches / 300-ar9300_support.patch
1 diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
2 index 97133be..dd112be 100644
3 --- a/drivers/net/wireless/ath/ath9k/Makefile
4 +++ b/drivers/net/wireless/ath/ath9k/Makefile
5 @@ -13,16 +13,26 @@ ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
6
7 obj-$(CONFIG_ATH9K) += ath9k.o
8
9 -ath9k_hw-y:= hw.o \
10 +ath9k_hw-y:= \
11 + ar9002_hw.o \
12 + ar9003_hw.o \
13 + hw.o \
14 + ar9003_phy.o \
15 + ar9002_phy.o \
16 + ar5008_phy.o \
17 + ar9002_calib.o \
18 + ar9003_calib.o \
19 + calib.o \
20 eeprom.o \
21 eeprom_def.o \
22 eeprom_4k.o \
23 eeprom_9287.o \
24 - calib.o \
25 ani.o \
26 - phy.o \
27 btcoex.o \
28 mac.o \
29 + ar9002_mac.o \
30 + ar9003_mac.o \
31 + ar9003_eeprom.o
32
33 obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o
34
35 diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
36 index 2a0cd64..5a2d867 100644
37 --- a/drivers/net/wireless/ath/ath9k/ani.c
38 +++ b/drivers/net/wireless/ath/ath9k/ani.c
39 @@ -15,6 +15,7 @@
40 */
41
42 #include "hw.h"
43 +#include "hw-ops.h"
44
45 static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
46 struct ath9k_channel *chan)
47 @@ -37,190 +38,6 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
48 return 0;
49 }
50
51 -static bool ath9k_hw_ani_control(struct ath_hw *ah,
52 - enum ath9k_ani_cmd cmd, int param)
53 -{
54 - struct ar5416AniState *aniState = ah->curani;
55 - struct ath_common *common = ath9k_hw_common(ah);
56 -
57 - switch (cmd & ah->ani_function) {
58 - case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
59 - u32 level = param;
60 -
61 - if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
62 - ath_print(common, ATH_DBG_ANI,
63 - "level out of range (%u > %u)\n",
64 - level,
65 - (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
66 - return false;
67 - }
68 -
69 - REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
70 - AR_PHY_DESIRED_SZ_TOT_DES,
71 - ah->totalSizeDesired[level]);
72 - REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
73 - AR_PHY_AGC_CTL1_COARSE_LOW,
74 - ah->coarse_low[level]);
75 - REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
76 - AR_PHY_AGC_CTL1_COARSE_HIGH,
77 - ah->coarse_high[level]);
78 - REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
79 - AR_PHY_FIND_SIG_FIRPWR,
80 - ah->firpwr[level]);
81 -
82 - if (level > aniState->noiseImmunityLevel)
83 - ah->stats.ast_ani_niup++;
84 - else if (level < aniState->noiseImmunityLevel)
85 - ah->stats.ast_ani_nidown++;
86 - aniState->noiseImmunityLevel = level;
87 - break;
88 - }
89 - case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
90 - const int m1ThreshLow[] = { 127, 50 };
91 - const int m2ThreshLow[] = { 127, 40 };
92 - const int m1Thresh[] = { 127, 0x4d };
93 - const int m2Thresh[] = { 127, 0x40 };
94 - const int m2CountThr[] = { 31, 16 };
95 - const int m2CountThrLow[] = { 63, 48 };
96 - u32 on = param ? 1 : 0;
97 -
98 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
99 - AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
100 - m1ThreshLow[on]);
101 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
102 - AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
103 - m2ThreshLow[on]);
104 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
105 - AR_PHY_SFCORR_M1_THRESH,
106 - m1Thresh[on]);
107 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
108 - AR_PHY_SFCORR_M2_THRESH,
109 - m2Thresh[on]);
110 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
111 - AR_PHY_SFCORR_M2COUNT_THR,
112 - m2CountThr[on]);
113 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
114 - AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
115 - m2CountThrLow[on]);
116 -
117 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
118 - AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
119 - m1ThreshLow[on]);
120 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
121 - AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
122 - m2ThreshLow[on]);
123 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
124 - AR_PHY_SFCORR_EXT_M1_THRESH,
125 - m1Thresh[on]);
126 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
127 - AR_PHY_SFCORR_EXT_M2_THRESH,
128 - m2Thresh[on]);
129 -
130 - if (on)
131 - REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
132 - AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
133 - else
134 - REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
135 - AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
136 -
137 - if (!on != aniState->ofdmWeakSigDetectOff) {
138 - if (on)
139 - ah->stats.ast_ani_ofdmon++;
140 - else
141 - ah->stats.ast_ani_ofdmoff++;
142 - aniState->ofdmWeakSigDetectOff = !on;
143 - }
144 - break;
145 - }
146 - case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
147 - const int weakSigThrCck[] = { 8, 6 };
148 - u32 high = param ? 1 : 0;
149 -
150 - REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
151 - AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
152 - weakSigThrCck[high]);
153 - if (high != aniState->cckWeakSigThreshold) {
154 - if (high)
155 - ah->stats.ast_ani_cckhigh++;
156 - else
157 - ah->stats.ast_ani_ccklow++;
158 - aniState->cckWeakSigThreshold = high;
159 - }
160 - break;
161 - }
162 - case ATH9K_ANI_FIRSTEP_LEVEL:{
163 - const int firstep[] = { 0, 4, 8 };
164 - u32 level = param;
165 -
166 - if (level >= ARRAY_SIZE(firstep)) {
167 - ath_print(common, ATH_DBG_ANI,
168 - "level out of range (%u > %u)\n",
169 - level,
170 - (unsigned) ARRAY_SIZE(firstep));
171 - return false;
172 - }
173 - REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
174 - AR_PHY_FIND_SIG_FIRSTEP,
175 - firstep[level]);
176 - if (level > aniState->firstepLevel)
177 - ah->stats.ast_ani_stepup++;
178 - else if (level < aniState->firstepLevel)
179 - ah->stats.ast_ani_stepdown++;
180 - aniState->firstepLevel = level;
181 - break;
182 - }
183 - case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
184 - const int cycpwrThr1[] =
185 - { 2, 4, 6, 8, 10, 12, 14, 16 };
186 - u32 level = param;
187 -
188 - if (level >= ARRAY_SIZE(cycpwrThr1)) {
189 - ath_print(common, ATH_DBG_ANI,
190 - "level out of range (%u > %u)\n",
191 - level,
192 - (unsigned) ARRAY_SIZE(cycpwrThr1));
193 - return false;
194 - }
195 - REG_RMW_FIELD(ah, AR_PHY_TIMING5,
196 - AR_PHY_TIMING5_CYCPWR_THR1,
197 - cycpwrThr1[level]);
198 - if (level > aniState->spurImmunityLevel)
199 - ah->stats.ast_ani_spurup++;
200 - else if (level < aniState->spurImmunityLevel)
201 - ah->stats.ast_ani_spurdown++;
202 - aniState->spurImmunityLevel = level;
203 - break;
204 - }
205 - case ATH9K_ANI_PRESENT:
206 - break;
207 - default:
208 - ath_print(common, ATH_DBG_ANI,
209 - "invalid cmd %u\n", cmd);
210 - return false;
211 - }
212 -
213 - ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
214 - ath_print(common, ATH_DBG_ANI,
215 - "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
216 - "ofdmWeakSigDetectOff=%d\n",
217 - aniState->noiseImmunityLevel,
218 - aniState->spurImmunityLevel,
219 - !aniState->ofdmWeakSigDetectOff);
220 - ath_print(common, ATH_DBG_ANI,
221 - "cckWeakSigThreshold=%d, "
222 - "firstepLevel=%d, listenTime=%d\n",
223 - aniState->cckWeakSigThreshold,
224 - aniState->firstepLevel,
225 - aniState->listenTime);
226 - ath_print(common, ATH_DBG_ANI,
227 - "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
228 - aniState->cycleCount,
229 - aniState->ofdmPhyErrCount,
230 - aniState->cckPhyErrCount);
231 -
232 - return true;
233 -}
234 -
235 static void ath9k_hw_update_mibstats(struct ath_hw *ah,
236 struct ath9k_mib_stats *stats)
237 {
238 diff --git a/drivers/net/wireless/ath/ath9k/ar5008_initvals.h b/drivers/net/wireless/ath/ath9k/ar5008_initvals.h
239 new file mode 100644
240 index 0000000..ba899f9
241 --- /dev/null
242 +++ b/drivers/net/wireless/ath/ath9k/ar5008_initvals.h
243 @@ -0,0 +1,873 @@
244 +/*
245 + * Copyright (c) 2008-2009 Atheros Communications Inc.
246 + *
247 + * Permission to use, copy, modify, and/or distribute this software for any
248 + * purpose with or without fee is hereby granted, provided that the above
249 + * copyright notice and this permission notice appear in all copies.
250 + *
251 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
252 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
253 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
254 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
255 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
256 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
257 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
258 + */
259 +
260 +#ifndef INITVALS_AR5008_H
261 +#define INITVALS_AR5008_H
262 +
263 +static const u32 ar5416Modes[][6] = {
264 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
265 + 0x000001e0},
266 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
267 + 0x000001e0},
268 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
269 + 0x00001180},
270 + {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000,
271 + 0x00014008},
272 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00,
273 + 0x06e006e0},
274 + {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab,
275 + 0x098813cf},
276 + {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810,
277 + 0x08f04810},
278 + {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a,
279 + 0x0000320a},
280 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
281 + 0x00000303},
282 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
283 + 0x02020200},
284 + {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
285 + 0x00000e0e},
286 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
287 + 0x0a020001},
288 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
289 + 0x00000e0e},
290 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
291 + 0x00000007},
292 + {0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0,
293 + 0x137216a0},
294 + {0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
295 + 0x00197a68},
296 + {0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
297 + 0x00197a68},
298 + {0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
299 + 0x00197a68},
300 + {0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de,
301 + 0x6c48b0de},
302 + {0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e,
303 + 0x7ec82d2e},
304 + {0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e,
305 + 0x31395d5e},
306 + {0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18,
307 + 0x00049d18},
308 + {0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00,
309 + 0x0001ce00},
310 + {0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190,
311 + 0x409a4190},
312 + {0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081,
313 + 0x050cb081},
314 + {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898,
315 + 0x000007d0},
316 + {0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134,
317 + 0x00000134},
318 + {0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b,
319 + 0xd0058a0b},
320 + {0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020,
321 + 0xffb81020},
322 + {0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80,
323 + 0x00012d80},
324 + {0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80,
325 + 0x00012d80},
326 + {0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80,
327 + 0x00012d80},
328 + {0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120,
329 + 0x00001120},
330 + {0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00,
331 + 0x001a0a00},
332 + {0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be,
333 + 0x038919be},
334 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
335 + 0x06336f77},
336 + {0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c,
337 + 0x6af6532c},
338 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
339 + 0x08f186c8},
340 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
341 + 0x00046384},
342 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
343 + 0x00000000},
344 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
345 + 0x00000000},
346 + {0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880,
347 + 0x00000880},
348 + {0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788,
349 + 0xd03e4788},
350 + {0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120,
351 + 0x002ac120},
352 + {0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120,
353 + 0x002ac120},
354 + {0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120,
355 + 0x002ac120},
356 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
357 + 0x1883800a},
358 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
359 + 0x00000000},
360 + {0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa,
361 + 0x0a1a7caa},
362 + {0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000,
363 + 0x18010000},
364 + {0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402,
365 + 0x2e032402},
366 + {0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06,
367 + 0x4a0a3c06},
368 + {0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b,
369 + 0x621a540b},
370 + {0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b,
371 + 0x764f6c1b},
372 + {0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a,
373 + 0x845b7a5a},
374 + {0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf,
375 + 0x950f8ccf},
376 + {0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f,
377 + 0xa5cf9b4f},
378 + {0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f,
379 + 0xbddfaf1f},
380 + {0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f,
381 + 0xd1ffc93f},
382 + {0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000,
383 + 0x00000000},
384 + {0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
385 + 0x00000000},
386 + {0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
387 + 0x00000000},
388 + {0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
389 + 0x00000000},
390 +};
391 +
392 +static const u32 ar5416Common[][2] = {
393 + {0x0000000c, 0x00000000},
394 + {0x00000030, 0x00020015},
395 + {0x00000034, 0x00000005},
396 + {0x00000040, 0x00000000},
397 + {0x00000044, 0x00000008},
398 + {0x00000048, 0x00000008},
399 + {0x0000004c, 0x00000010},
400 + {0x00000050, 0x00000000},
401 + {0x00000054, 0x0000001f},
402 + {0x00000800, 0x00000000},
403 + {0x00000804, 0x00000000},
404 + {0x00000808, 0x00000000},
405 + {0x0000080c, 0x00000000},
406 + {0x00000810, 0x00000000},
407 + {0x00000814, 0x00000000},
408 + {0x00000818, 0x00000000},
409 + {0x0000081c, 0x00000000},
410 + {0x00000820, 0x00000000},
411 + {0x00000824, 0x00000000},
412 + {0x00001040, 0x002ffc0f},
413 + {0x00001044, 0x002ffc0f},
414 + {0x00001048, 0x002ffc0f},
415 + {0x0000104c, 0x002ffc0f},
416 + {0x00001050, 0x002ffc0f},
417 + {0x00001054, 0x002ffc0f},
418 + {0x00001058, 0x002ffc0f},
419 + {0x0000105c, 0x002ffc0f},
420 + {0x00001060, 0x002ffc0f},
421 + {0x00001064, 0x002ffc0f},
422 + {0x00001230, 0x00000000},
423 + {0x00001270, 0x00000000},
424 + {0x00001038, 0x00000000},
425 + {0x00001078, 0x00000000},
426 + {0x000010b8, 0x00000000},
427 + {0x000010f8, 0x00000000},
428 + {0x00001138, 0x00000000},
429 + {0x00001178, 0x00000000},
430 + {0x000011b8, 0x00000000},
431 + {0x000011f8, 0x00000000},
432 + {0x00001238, 0x00000000},
433 + {0x00001278, 0x00000000},
434 + {0x000012b8, 0x00000000},
435 + {0x000012f8, 0x00000000},
436 + {0x00001338, 0x00000000},
437 + {0x00001378, 0x00000000},
438 + {0x000013b8, 0x00000000},
439 + {0x000013f8, 0x00000000},
440 + {0x00001438, 0x00000000},
441 + {0x00001478, 0x00000000},
442 + {0x000014b8, 0x00000000},
443 + {0x000014f8, 0x00000000},
444 + {0x00001538, 0x00000000},
445 + {0x00001578, 0x00000000},
446 + {0x000015b8, 0x00000000},
447 + {0x000015f8, 0x00000000},
448 + {0x00001638, 0x00000000},
449 + {0x00001678, 0x00000000},
450 + {0x000016b8, 0x00000000},
451 + {0x000016f8, 0x00000000},
452 + {0x00001738, 0x00000000},
453 + {0x00001778, 0x00000000},
454 + {0x000017b8, 0x00000000},
455 + {0x000017f8, 0x00000000},
456 + {0x0000103c, 0x00000000},
457 + {0x0000107c, 0x00000000},
458 + {0x000010bc, 0x00000000},
459 + {0x000010fc, 0x00000000},
460 + {0x0000113c, 0x00000000},
461 + {0x0000117c, 0x00000000},
462 + {0x000011bc, 0x00000000},
463 + {0x000011fc, 0x00000000},
464 + {0x0000123c, 0x00000000},
465 + {0x0000127c, 0x00000000},
466 + {0x000012bc, 0x00000000},
467 + {0x000012fc, 0x00000000},
468 + {0x0000133c, 0x00000000},
469 + {0x0000137c, 0x00000000},
470 + {0x000013bc, 0x00000000},
471 + {0x000013fc, 0x00000000},
472 + {0x0000143c, 0x00000000},
473 + {0x0000147c, 0x00000000},
474 + {0x00004030, 0x00000002},
475 + {0x0000403c, 0x00000002},
476 + {0x00007010, 0x00000000},
477 + {0x00007038, 0x000004c2},
478 + {0x00008004, 0x00000000},
479 + {0x00008008, 0x00000000},
480 + {0x0000800c, 0x00000000},
481 + {0x00008018, 0x00000700},
482 + {0x00008020, 0x00000000},
483 + {0x00008038, 0x00000000},
484 + {0x0000803c, 0x00000000},
485 + {0x00008048, 0x40000000},
486 + {0x00008054, 0x00000000},
487 + {0x00008058, 0x00000000},
488 + {0x0000805c, 0x000fc78f},
489 + {0x00008060, 0x0000000f},
490 + {0x00008064, 0x00000000},
491 + {0x000080c0, 0x2a82301a},
492 + {0x000080c4, 0x05dc01e0},
493 + {0x000080c8, 0x1f402710},
494 + {0x000080cc, 0x01f40000},
495 + {0x000080d0, 0x00001e00},
496 + {0x000080d4, 0x00000000},
497 + {0x000080d8, 0x00400000},
498 + {0x000080e0, 0xffffffff},
499 + {0x000080e4, 0x0000ffff},
500 + {0x000080e8, 0x003f3f3f},
501 + {0x000080ec, 0x00000000},
502 + {0x000080f0, 0x00000000},
503 + {0x000080f4, 0x00000000},
504 + {0x000080f8, 0x00000000},
505 + {0x000080fc, 0x00020000},
506 + {0x00008100, 0x00020000},
507 + {0x00008104, 0x00000001},
508 + {0x00008108, 0x00000052},
509 + {0x0000810c, 0x00000000},
510 + {0x00008110, 0x00000168},
511 + {0x00008118, 0x000100aa},
512 + {0x0000811c, 0x00003210},
513 + {0x00008124, 0x00000000},
514 + {0x00008128, 0x00000000},
515 + {0x0000812c, 0x00000000},
516 + {0x00008130, 0x00000000},
517 + {0x00008134, 0x00000000},
518 + {0x00008138, 0x00000000},
519 + {0x0000813c, 0x00000000},
520 + {0x00008144, 0xffffffff},
521 + {0x00008168, 0x00000000},
522 + {0x0000816c, 0x00000000},
523 + {0x00008170, 0x32143320},
524 + {0x00008174, 0xfaa4fa50},
525 + {0x00008178, 0x00000100},
526 + {0x0000817c, 0x00000000},
527 + {0x000081c4, 0x00000000},
528 + {0x000081ec, 0x00000000},
529 + {0x000081f0, 0x00000000},
530 + {0x000081f4, 0x00000000},
531 + {0x000081f8, 0x00000000},
532 + {0x000081fc, 0x00000000},
533 + {0x00008200, 0x00000000},
534 + {0x00008204, 0x00000000},
535 + {0x00008208, 0x00000000},
536 + {0x0000820c, 0x00000000},
537 + {0x00008210, 0x00000000},
538 + {0x00008214, 0x00000000},
539 + {0x00008218, 0x00000000},
540 + {0x0000821c, 0x00000000},
541 + {0x00008220, 0x00000000},
542 + {0x00008224, 0x00000000},
543 + {0x00008228, 0x00000000},
544 + {0x0000822c, 0x00000000},
545 + {0x00008230, 0x00000000},
546 + {0x00008234, 0x00000000},
547 + {0x00008238, 0x00000000},
548 + {0x0000823c, 0x00000000},
549 + {0x00008240, 0x00100000},
550 + {0x00008244, 0x0010f400},
551 + {0x00008248, 0x00000100},
552 + {0x0000824c, 0x0001e800},
553 + {0x00008250, 0x00000000},
554 + {0x00008254, 0x00000000},
555 + {0x00008258, 0x00000000},
556 + {0x0000825c, 0x400000ff},
557 + {0x00008260, 0x00080922},
558 + {0x00008264, 0xa8000010},
559 + {0x00008270, 0x00000000},
560 + {0x00008274, 0x40000000},
561 + {0x00008278, 0x003e4180},
562 + {0x0000827c, 0x00000000},
563 + {0x00008284, 0x0000002c},
564 + {0x00008288, 0x0000002c},
565 + {0x0000828c, 0x00000000},
566 + {0x00008294, 0x00000000},
567 + {0x00008298, 0x00000000},
568 + {0x00008300, 0x00000000},
569 + {0x00008304, 0x00000000},
570 + {0x00008308, 0x00000000},
571 + {0x0000830c, 0x00000000},
572 + {0x00008310, 0x00000000},
573 + {0x00008314, 0x00000000},
574 + {0x00008318, 0x00000000},
575 + {0x00008328, 0x00000000},
576 + {0x0000832c, 0x00000007},
577 + {0x00008330, 0x00000302},
578 + {0x00008334, 0x00000e00},
579 + {0x00008338, 0x00070000},
580 + {0x0000833c, 0x00000000},
581 + {0x00008340, 0x000107ff},
582 + {0x00009808, 0x00000000},
583 + {0x0000980c, 0xad848e19},
584 + {0x00009810, 0x7d14e000},
585 + {0x00009814, 0x9c0a9f6b},
586 + {0x0000981c, 0x00000000},
587 + {0x0000982c, 0x0000a000},
588 + {0x00009830, 0x00000000},
589 + {0x0000983c, 0x00200400},
590 + {0x00009840, 0x206a002e},
591 + {0x0000984c, 0x1284233c},
592 + {0x00009854, 0x00000859},
593 + {0x00009900, 0x00000000},
594 + {0x00009904, 0x00000000},
595 + {0x00009908, 0x00000000},
596 + {0x0000990c, 0x00000000},
597 + {0x0000991c, 0x10000fff},
598 + {0x00009920, 0x05100000},
599 + {0x0000a920, 0x05100000},
600 + {0x0000b920, 0x05100000},
601 + {0x00009928, 0x00000001},
602 + {0x0000992c, 0x00000004},
603 + {0x00009934, 0x1e1f2022},
604 + {0x00009938, 0x0a0b0c0d},
605 + {0x0000993c, 0x00000000},
606 + {0x00009948, 0x9280b212},
607 + {0x0000994c, 0x00020028},
608 + {0x00009954, 0x5d50e188},
609 + {0x00009958, 0x00081fff},
610 + {0x0000c95c, 0x004b6a8e},
611 + {0x0000c968, 0x000003ce},
612 + {0x00009970, 0x190fb515},
613 + {0x00009974, 0x00000000},
614 + {0x00009978, 0x00000001},
615 + {0x0000997c, 0x00000000},
616 + {0x00009980, 0x00000000},
617 + {0x00009984, 0x00000000},
618 + {0x00009988, 0x00000000},
619 + {0x0000998c, 0x00000000},
620 + {0x00009990, 0x00000000},
621 + {0x00009994, 0x00000000},
622 + {0x00009998, 0x00000000},
623 + {0x0000999c, 0x00000000},
624 + {0x000099a0, 0x00000000},
625 + {0x000099a4, 0x00000001},
626 + {0x000099a8, 0x001fff00},
627 + {0x000099ac, 0x00000000},
628 + {0x000099b0, 0x03051000},
629 + {0x000099dc, 0x00000000},
630 + {0x000099e0, 0x00000200},
631 + {0x000099e4, 0xaaaaaaaa},
632 + {0x000099e8, 0x3c466478},
633 + {0x000099ec, 0x000000aa},
634 + {0x000099fc, 0x00001042},
635 + {0x00009b00, 0x00000000},
636 + {0x00009b04, 0x00000001},
637 + {0x00009b08, 0x00000002},
638 + {0x00009b0c, 0x00000003},
639 + {0x00009b10, 0x00000004},
640 + {0x00009b14, 0x00000005},
641 + {0x00009b18, 0x00000008},
642 + {0x00009b1c, 0x00000009},
643 + {0x00009b20, 0x0000000a},
644 + {0x00009b24, 0x0000000b},
645 + {0x00009b28, 0x0000000c},
646 + {0x00009b2c, 0x0000000d},
647 + {0x00009b30, 0x00000010},
648 + {0x00009b34, 0x00000011},
649 + {0x00009b38, 0x00000012},
650 + {0x00009b3c, 0x00000013},
651 + {0x00009b40, 0x00000014},
652 + {0x00009b44, 0x00000015},
653 + {0x00009b48, 0x00000018},
654 + {0x00009b4c, 0x00000019},
655 + {0x00009b50, 0x0000001a},
656 + {0x00009b54, 0x0000001b},
657 + {0x00009b58, 0x0000001c},
658 + {0x00009b5c, 0x0000001d},
659 + {0x00009b60, 0x00000020},
660 + {0x00009b64, 0x00000021},
661 + {0x00009b68, 0x00000022},
662 + {0x00009b6c, 0x00000023},
663 + {0x00009b70, 0x00000024},
664 + {0x00009b74, 0x00000025},
665 + {0x00009b78, 0x00000028},
666 + {0x00009b7c, 0x00000029},
667 + {0x00009b80, 0x0000002a},
668 + {0x00009b84, 0x0000002b},
669 + {0x00009b88, 0x0000002c},
670 + {0x00009b8c, 0x0000002d},
671 + {0x00009b90, 0x00000030},
672 + {0x00009b94, 0x00000031},
673 + {0x00009b98, 0x00000032},
674 + {0x00009b9c, 0x00000033},
675 + {0x00009ba0, 0x00000034},
676 + {0x00009ba4, 0x00000035},
677 + {0x00009ba8, 0x00000035},
678 + {0x00009bac, 0x00000035},
679 + {0x00009bb0, 0x00000035},
680 + {0x00009bb4, 0x00000035},
681 + {0x00009bb8, 0x00000035},
682 + {0x00009bbc, 0x00000035},
683 + {0x00009bc0, 0x00000035},
684 + {0x00009bc4, 0x00000035},
685 + {0x00009bc8, 0x00000035},
686 + {0x00009bcc, 0x00000035},
687 + {0x00009bd0, 0x00000035},
688 + {0x00009bd4, 0x00000035},
689 + {0x00009bd8, 0x00000035},
690 + {0x00009bdc, 0x00000035},
691 + {0x00009be0, 0x00000035},
692 + {0x00009be4, 0x00000035},
693 + {0x00009be8, 0x00000035},
694 + {0x00009bec, 0x00000035},
695 + {0x00009bf0, 0x00000035},
696 + {0x00009bf4, 0x00000035},
697 + {0x00009bf8, 0x00000010},
698 + {0x00009bfc, 0x0000001a},
699 + {0x0000a210, 0x40806333},
700 + {0x0000a214, 0x00106c10},
701 + {0x0000a218, 0x009c4060},
702 + {0x0000a220, 0x018830c6},
703 + {0x0000a224, 0x00000400},
704 + {0x0000a228, 0x00000bb5},
705 + {0x0000a22c, 0x00000011},
706 + {0x0000a234, 0x20202020},
707 + {0x0000a238, 0x20202020},
708 + {0x0000a23c, 0x13c889af},
709 + {0x0000a240, 0x38490a20},
710 + {0x0000a244, 0x00007bb6},
711 + {0x0000a248, 0x0fff3ffc},
712 + {0x0000a24c, 0x00000001},
713 + {0x0000a250, 0x0000a000},
714 + {0x0000a254, 0x00000000},
715 + {0x0000a258, 0x0cc75380},
716 + {0x0000a25c, 0x0f0f0f01},
717 + {0x0000a260, 0xdfa91f01},
718 + {0x0000a268, 0x00000000},
719 + {0x0000a26c, 0x0e79e5c6},
720 + {0x0000b26c, 0x0e79e5c6},
721 + {0x0000c26c, 0x0e79e5c6},
722 + {0x0000d270, 0x00820820},
723 + {0x0000a278, 0x1ce739ce},
724 + {0x0000a27c, 0x051701ce},
725 + {0x0000a338, 0x00000000},
726 + {0x0000a33c, 0x00000000},
727 + {0x0000a340, 0x00000000},
728 + {0x0000a344, 0x00000000},
729 + {0x0000a348, 0x3fffffff},
730 + {0x0000a34c, 0x3fffffff},
731 + {0x0000a350, 0x3fffffff},
732 + {0x0000a354, 0x0003ffff},
733 + {0x0000a358, 0x79a8aa1f},
734 + {0x0000d35c, 0x07ffffef},
735 + {0x0000d360, 0x0fffffe7},
736 + {0x0000d364, 0x17ffffe5},
737 + {0x0000d368, 0x1fffffe4},
738 + {0x0000d36c, 0x37ffffe3},
739 + {0x0000d370, 0x3fffffe3},
740 + {0x0000d374, 0x57ffffe3},
741 + {0x0000d378, 0x5fffffe2},
742 + {0x0000d37c, 0x7fffffe2},
743 + {0x0000d380, 0x7f3c7bba},
744 + {0x0000d384, 0xf3307ff0},
745 + {0x0000a388, 0x08000000},
746 + {0x0000a38c, 0x20202020},
747 + {0x0000a390, 0x20202020},
748 + {0x0000a394, 0x1ce739ce},
749 + {0x0000a398, 0x000001ce},
750 + {0x0000a39c, 0x00000001},
751 + {0x0000a3a0, 0x00000000},
752 + {0x0000a3a4, 0x00000000},
753 + {0x0000a3a8, 0x00000000},
754 + {0x0000a3ac, 0x00000000},
755 + {0x0000a3b0, 0x00000000},
756 + {0x0000a3b4, 0x00000000},
757 + {0x0000a3b8, 0x00000000},
758 + {0x0000a3bc, 0x00000000},
759 + {0x0000a3c0, 0x00000000},
760 + {0x0000a3c4, 0x00000000},
761 + {0x0000a3c8, 0x00000246},
762 + {0x0000a3cc, 0x20202020},
763 + {0x0000a3d0, 0x20202020},
764 + {0x0000a3d4, 0x20202020},
765 + {0x0000a3dc, 0x1ce739ce},
766 + {0x0000a3e0, 0x000001ce},
767 +};
768 +
769 +static const u32 ar5416Bank0[][2] = {
770 + {0x000098b0, 0x1e5795e5},
771 + {0x000098e0, 0x02008020},
772 +};
773 +
774 +static const u32 ar5416BB_RfGain[][3] = {
775 + {0x00009a00, 0x00000000, 0x00000000},
776 + {0x00009a04, 0x00000040, 0x00000040},
777 + {0x00009a08, 0x00000080, 0x00000080},
778 + {0x00009a0c, 0x000001a1, 0x00000141},
779 + {0x00009a10, 0x000001e1, 0x00000181},
780 + {0x00009a14, 0x00000021, 0x000001c1},
781 + {0x00009a18, 0x00000061, 0x00000001},
782 + {0x00009a1c, 0x00000168, 0x00000041},
783 + {0x00009a20, 0x000001a8, 0x000001a8},
784 + {0x00009a24, 0x000001e8, 0x000001e8},
785 + {0x00009a28, 0x00000028, 0x00000028},
786 + {0x00009a2c, 0x00000068, 0x00000068},
787 + {0x00009a30, 0x00000189, 0x000000a8},
788 + {0x00009a34, 0x000001c9, 0x00000169},
789 + {0x00009a38, 0x00000009, 0x000001a9},
790 + {0x00009a3c, 0x00000049, 0x000001e9},
791 + {0x00009a40, 0x00000089, 0x00000029},
792 + {0x00009a44, 0x00000170, 0x00000069},
793 + {0x00009a48, 0x000001b0, 0x00000190},
794 + {0x00009a4c, 0x000001f0, 0x000001d0},
795 + {0x00009a50, 0x00000030, 0x00000010},
796 + {0x00009a54, 0x00000070, 0x00000050},
797 + {0x00009a58, 0x00000191, 0x00000090},
798 + {0x00009a5c, 0x000001d1, 0x00000151},
799 + {0x00009a60, 0x00000011, 0x00000191},
800 + {0x00009a64, 0x00000051, 0x000001d1},
801 + {0x00009a68, 0x00000091, 0x00000011},
802 + {0x00009a6c, 0x000001b8, 0x00000051},
803 + {0x00009a70, 0x000001f8, 0x00000198},
804 + {0x00009a74, 0x00000038, 0x000001d8},
805 + {0x00009a78, 0x00000078, 0x00000018},
806 + {0x00009a7c, 0x00000199, 0x00000058},
807 + {0x00009a80, 0x000001d9, 0x00000098},
808 + {0x00009a84, 0x00000019, 0x00000159},
809 + {0x00009a88, 0x00000059, 0x00000199},
810 + {0x00009a8c, 0x00000099, 0x000001d9},
811 + {0x00009a90, 0x000000d9, 0x00000019},
812 + {0x00009a94, 0x000000f9, 0x00000059},
813 + {0x00009a98, 0x000000f9, 0x00000099},
814 + {0x00009a9c, 0x000000f9, 0x000000d9},
815 + {0x00009aa0, 0x000000f9, 0x000000f9},
816 + {0x00009aa4, 0x000000f9, 0x000000f9},
817 + {0x00009aa8, 0x000000f9, 0x000000f9},
818 + {0x00009aac, 0x000000f9, 0x000000f9},
819 + {0x00009ab0, 0x000000f9, 0x000000f9},
820 + {0x00009ab4, 0x000000f9, 0x000000f9},
821 + {0x00009ab8, 0x000000f9, 0x000000f9},
822 + {0x00009abc, 0x000000f9, 0x000000f9},
823 + {0x00009ac0, 0x000000f9, 0x000000f9},
824 + {0x00009ac4, 0x000000f9, 0x000000f9},
825 + {0x00009ac8, 0x000000f9, 0x000000f9},
826 + {0x00009acc, 0x000000f9, 0x000000f9},
827 + {0x00009ad0, 0x000000f9, 0x000000f9},
828 + {0x00009ad4, 0x000000f9, 0x000000f9},
829 + {0x00009ad8, 0x000000f9, 0x000000f9},
830 + {0x00009adc, 0x000000f9, 0x000000f9},
831 + {0x00009ae0, 0x000000f9, 0x000000f9},
832 + {0x00009ae4, 0x000000f9, 0x000000f9},
833 + {0x00009ae8, 0x000000f9, 0x000000f9},
834 + {0x00009aec, 0x000000f9, 0x000000f9},
835 + {0x00009af0, 0x000000f9, 0x000000f9},
836 + {0x00009af4, 0x000000f9, 0x000000f9},
837 + {0x00009af8, 0x000000f9, 0x000000f9},
838 + {0x00009afc, 0x000000f9, 0x000000f9},
839 +};
840 +
841 +static const u32 ar5416Bank1[][2] = {
842 + {0x000098b0, 0x02108421},
843 + {0x000098ec, 0x00000008},
844 +};
845 +
846 +static const u32 ar5416Bank2[][2] = {
847 + {0x000098b0, 0x0e73ff17},
848 + {0x000098e0, 0x00000420},
849 +};
850 +
851 +static const u32 ar5416Bank3[][3] = {
852 + {0x000098f0, 0x01400018, 0x01c00018},
853 +};
854 +
855 +static const u32 ar5416Bank6[][3] = {
856 +
857 + {0x0000989c, 0x00000000, 0x00000000},
858 + {0x0000989c, 0x00000000, 0x00000000},
859 + {0x0000989c, 0x00000000, 0x00000000},
860 + {0x0000989c, 0x00e00000, 0x00e00000},
861 + {0x0000989c, 0x005e0000, 0x005e0000},
862 + {0x0000989c, 0x00120000, 0x00120000},
863 + {0x0000989c, 0x00620000, 0x00620000},
864 + {0x0000989c, 0x00020000, 0x00020000},
865 + {0x0000989c, 0x00ff0000, 0x00ff0000},
866 + {0x0000989c, 0x00ff0000, 0x00ff0000},
867 + {0x0000989c, 0x00ff0000, 0x00ff0000},
868 + {0x0000989c, 0x40ff0000, 0x40ff0000},
869 + {0x0000989c, 0x005f0000, 0x005f0000},
870 + {0x0000989c, 0x00870000, 0x00870000},
871 + {0x0000989c, 0x00f90000, 0x00f90000},
872 + {0x0000989c, 0x007b0000, 0x007b0000},
873 + {0x0000989c, 0x00ff0000, 0x00ff0000},
874 + {0x0000989c, 0x00f50000, 0x00f50000},
875 + {0x0000989c, 0x00dc0000, 0x00dc0000},
876 + {0x0000989c, 0x00110000, 0x00110000},
877 + {0x0000989c, 0x006100a8, 0x006100a8},
878 + {0x0000989c, 0x004210a2, 0x004210a2},
879 + {0x0000989c, 0x0014008f, 0x0014008f},
880 + {0x0000989c, 0x00c40003, 0x00c40003},
881 + {0x0000989c, 0x003000f2, 0x003000f2},
882 + {0x0000989c, 0x00440016, 0x00440016},
883 + {0x0000989c, 0x00410040, 0x00410040},
884 + {0x0000989c, 0x0001805e, 0x0001805e},
885 + {0x0000989c, 0x0000c0ab, 0x0000c0ab},
886 + {0x0000989c, 0x000000f1, 0x000000f1},
887 + {0x0000989c, 0x00002081, 0x00002081},
888 + {0x0000989c, 0x000000d4, 0x000000d4},
889 + {0x000098d0, 0x0000000f, 0x0010000f},
890 +};
891 +
892 +static const u32 ar5416Bank6TPC[][3] = {
893 + {0x0000989c, 0x00000000, 0x00000000},
894 + {0x0000989c, 0x00000000, 0x00000000},
895 + {0x0000989c, 0x00000000, 0x00000000},
896 + {0x0000989c, 0x00e00000, 0x00e00000},
897 + {0x0000989c, 0x005e0000, 0x005e0000},
898 + {0x0000989c, 0x00120000, 0x00120000},
899 + {0x0000989c, 0x00620000, 0x00620000},
900 + {0x0000989c, 0x00020000, 0x00020000},
901 + {0x0000989c, 0x00ff0000, 0x00ff0000},
902 + {0x0000989c, 0x00ff0000, 0x00ff0000},
903 + {0x0000989c, 0x00ff0000, 0x00ff0000},
904 + {0x0000989c, 0x40ff0000, 0x40ff0000},
905 + {0x0000989c, 0x005f0000, 0x005f0000},
906 + {0x0000989c, 0x00870000, 0x00870000},
907 + {0x0000989c, 0x00f90000, 0x00f90000},
908 + {0x0000989c, 0x007b0000, 0x007b0000},
909 + {0x0000989c, 0x00ff0000, 0x00ff0000},
910 + {0x0000989c, 0x00f50000, 0x00f50000},
911 + {0x0000989c, 0x00dc0000, 0x00dc0000},
912 + {0x0000989c, 0x00110000, 0x00110000},
913 + {0x0000989c, 0x006100a8, 0x006100a8},
914 + {0x0000989c, 0x00423022, 0x00423022},
915 + {0x0000989c, 0x201400df, 0x201400df},
916 + {0x0000989c, 0x00c40002, 0x00c40002},
917 + {0x0000989c, 0x003000f2, 0x003000f2},
918 + {0x0000989c, 0x00440016, 0x00440016},
919 + {0x0000989c, 0x00410040, 0x00410040},
920 + {0x0000989c, 0x0001805e, 0x0001805e},
921 + {0x0000989c, 0x0000c0ab, 0x0000c0ab},
922 + {0x0000989c, 0x000000e1, 0x000000e1},
923 + {0x0000989c, 0x00007081, 0x00007081},
924 + {0x0000989c, 0x000000d4, 0x000000d4},
925 + {0x000098d0, 0x0000000f, 0x0010000f},
926 +};
927 +
928 +static const u32 ar5416Bank7[][2] = {
929 + {0x0000989c, 0x00000500},
930 + {0x0000989c, 0x00000800},
931 + {0x000098cc, 0x0000000e},
932 +};
933 +
934 +static const u32 ar5416Addac[][2] = {
935 + {0x0000989c, 0x00000000},
936 + {0x0000989c, 0x00000003},
937 + {0x0000989c, 0x00000000},
938 + {0x0000989c, 0x0000000c},
939 + {0x0000989c, 0x00000000},
940 + {0x0000989c, 0x00000030},
941 + {0x0000989c, 0x00000000},
942 + {0x0000989c, 0x00000000},
943 + {0x0000989c, 0x00000000},
944 + {0x0000989c, 0x00000000},
945 + {0x0000989c, 0x00000000},
946 + {0x0000989c, 0x00000000},
947 + {0x0000989c, 0x00000000},
948 + {0x0000989c, 0x00000000},
949 + {0x0000989c, 0x00000000},
950 + {0x0000989c, 0x00000000},
951 + {0x0000989c, 0x00000000},
952 + {0x0000989c, 0x00000000},
953 + {0x0000989c, 0x00000060},
954 + {0x0000989c, 0x00000000},
955 + {0x0000989c, 0x00000000},
956 + {0x0000989c, 0x00000000},
957 + {0x0000989c, 0x00000000},
958 + {0x0000989c, 0x00000000},
959 + {0x0000989c, 0x00000000},
960 + {0x0000989c, 0x00000000},
961 + {0x0000989c, 0x00000000},
962 + {0x0000989c, 0x00000000},
963 + {0x0000989c, 0x00000000},
964 + {0x0000989c, 0x00000000},
965 + {0x0000989c, 0x00000000},
966 + {0x0000989c, 0x00000058},
967 + {0x0000989c, 0x00000000},
968 + {0x0000989c, 0x00000000},
969 + {0x0000989c, 0x00000000},
970 + {0x0000989c, 0x00000000},
971 + {0x000098cc, 0x00000000},
972 +};
973 +
974 +static const u32 ar5416Modes_9100[][6] = {
975 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
976 + 0x000001e0},
977 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
978 + 0x000001e0},
979 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
980 + 0x00001180},
981 + {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000,
982 + 0x00014008},
983 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00,
984 + 0x06e006e0},
985 + {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab,
986 + 0x098813cf},
987 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
988 + 0x00000303},
989 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
990 + 0x02020200},
991 + {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
992 + 0x00000e0e},
993 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
994 + 0x0a020001},
995 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
996 + 0x00000e0e},
997 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
998 + 0x00000007},
999 + {0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0,
1000 + 0x037216a0},
1001 + {0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
1002 + 0x00197a68},
1003 + {0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
1004 + 0x00197a68},
1005 + {0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
1006 + 0x00197a68},
1007 + {0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2,
1008 + 0x6d48b0e2},
1009 + {0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec86d2e, 0x7ec84d2e,
1010 + 0x7ec82d2e},
1011 + {0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e,
1012 + 0x3139605e},
1013 + {0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20,
1014 + 0x00048d18},
1015 + {0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00,
1016 + 0x0001ce00},
1017 + {0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0,
1018 + 0x409a40d0},
1019 + {0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081,
1020 + 0x050cb081},
1021 + {0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898,
1022 + 0x000007d0},
1023 + {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b,
1024 + 0x00000016},
1025 + {0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a11, 0xd00a8a0d,
1026 + 0xd00a8a0d},
1027 + {0x00009940, 0x00754604, 0x00754604, 0xfff81204, 0xfff81204,
1028 + 0xfff81204},
1029 + {0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020,
1030 + 0xdfb81020},
1031 + {0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e,
1032 + 0xe250a51e},
1033 + {0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff,
1034 + 0x3388ffff},
1035 +#ifdef TB243
1036 + {0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40,
1037 + 0x00012d80},
1038 + {0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40,
1039 + 0x00012d80},
1040 + {0x0000b960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40,
1041 + 0x00012d80},
1042 + {0x00009964, 0x00000000, 0x00000000, 0x00002210, 0x00002210,
1043 + 0x00001120},
1044 +#else
1045 + {0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0,
1046 + 0x0001bfc0},
1047 + {0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0,
1048 + 0x0001bfc0},
1049 + {0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0,
1050 + 0x0001bfc0},
1051 + {0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120,
1052 + 0x00001120},
1053 +#endif
1054 + {0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00,
1055 + 0x001a0c00},
1056 + {0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be,
1057 + 0x038919be},
1058 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
1059 + 0x06336f77},
1060 + {0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329,
1061 + 0x60f65329},
1062 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
1063 + 0x08f186c8},
1064 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
1065 + 0x00046384},
1066 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1067 + 0x00000000},
1068 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1069 + 0x00000000},
1070 + {0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880,
1071 + 0x00000880},
1072 + {0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788,
1073 + 0xd03e4788},
1074 + {0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120,
1075 + 0x002ac120},
1076 + {0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120,
1077 + 0x002ac120},
1078 + {0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120,
1079 + 0x002ac120},
1080 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
1081 + 0x1883800a},
1082 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
1083 + 0x00000000},
1084 + {0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa,
1085 + 0x0a1a7caa},
1086 + {0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000,
1087 + 0x18010000},
1088 + {0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402,
1089 + 0x2e032402},
1090 + {0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06,
1091 + 0x4a0a3c06},
1092 + {0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b,
1093 + 0x621a540b},
1094 + {0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b,
1095 + 0x764f6c1b},
1096 + {0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a,
1097 + 0x845b7a5a},
1098 + {0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf,
1099 + 0x950f8ccf},
1100 + {0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f,
1101 + 0xa5cf9b4f},
1102 + {0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f,
1103 + 0xbddfaf1f},
1104 + {0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f,
1105 + 0xd1ffc93f},
1106 + {0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000,
1107 + 0x00000000},
1108 + {0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1109 + 0x00000000},
1110 + {0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1111 + 0x00000000},
1112 + {0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1113 + 0x00000000},
1114 +};
1115 +
1116 +#endif /* INITVALS_AR5008_H */
1117 diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
1118 new file mode 100644
1119 index 0000000..60fe5bb
1120 --- /dev/null
1121 +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
1122 @@ -0,0 +1,1278 @@
1123 +/*
1124 + * Copyright (c) 2008-2010 Atheros Communications Inc.
1125 + *
1126 + * Permission to use, copy, modify, and/or distribute this software for any
1127 + * purpose with or without fee is hereby granted, provided that the above
1128 + * copyright notice and this permission notice appear in all copies.
1129 + *
1130 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
1131 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
1132 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
1133 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
1134 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
1135 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
1136 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
1137 + */
1138 +
1139 +#include "hw.h"
1140 +#include "hw-ops.h"
1141 +#include "../regd.h"
1142 +#include "ar9002_phy.h"
1143 +
1144 +/* All code below is for non single-chip solutions */
1145 +
1146 +/**
1147 + * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
1148 + * @rfbuf:
1149 + * @reg32:
1150 + * @numBits:
1151 + * @firstBit:
1152 + * @column:
1153 + *
1154 + * Performs analog "swizzling" of parameters into their location.
1155 + * Used on external AR2133/AR5133 radios.
1156 + */
1157 +static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
1158 + u32 numBits, u32 firstBit,
1159 + u32 column)
1160 +{
1161 + u32 tmp32, mask, arrayEntry, lastBit;
1162 + int32_t bitPosition, bitsLeft;
1163 +
1164 + tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
1165 + arrayEntry = (firstBit - 1) / 8;
1166 + bitPosition = (firstBit - 1) % 8;
1167 + bitsLeft = numBits;
1168 + while (bitsLeft > 0) {
1169 + lastBit = (bitPosition + bitsLeft > 8) ?
1170 + 8 : bitPosition + bitsLeft;
1171 + mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
1172 + (column * 8);
1173 + rfBuf[arrayEntry] &= ~mask;
1174 + rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
1175 + (column * 8)) & mask;
1176 + bitsLeft -= 8 - bitPosition;
1177 + tmp32 = tmp32 >> (8 - bitPosition);
1178 + bitPosition = 0;
1179 + arrayEntry++;
1180 + }
1181 +}
1182 +
1183 +/*
1184 + * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
1185 + * rf_pwd_icsyndiv.
1186 + *
1187 + * Theoretical Rules:
1188 + * if 2 GHz band
1189 + * if forceBiasAuto
1190 + * if synth_freq < 2412
1191 + * bias = 0
1192 + * else if 2412 <= synth_freq <= 2422
1193 + * bias = 1
1194 + * else // synth_freq > 2422
1195 + * bias = 2
1196 + * else if forceBias > 0
1197 + * bias = forceBias & 7
1198 + * else
1199 + * no change, use value from ini file
1200 + * else
1201 + * no change, invalid band
1202 + *
1203 + * 1st Mod:
1204 + * 2422 also uses value of 2
1205 + * <approved>
1206 + *
1207 + * 2nd Mod:
1208 + * Less than 2412 uses value of 0, 2412 and above uses value of 2
1209 + */
1210 +static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
1211 +{
1212 + struct ath_common *common = ath9k_hw_common(ah);
1213 + u32 tmp_reg;
1214 + int reg_writes = 0;
1215 + u32 new_bias = 0;
1216 +
1217 + if (!AR_SREV_5416(ah) || synth_freq >= 3000) {
1218 + return;
1219 + }
1220 +
1221 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1222 +
1223 + if (synth_freq < 2412)
1224 + new_bias = 0;
1225 + else if (synth_freq < 2422)
1226 + new_bias = 1;
1227 + else
1228 + new_bias = 2;
1229 +
1230 + /* pre-reverse this field */
1231 + tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
1232 +
1233 + ath_print(common, ATH_DBG_CONFIG,
1234 + "Force rf_pwd_icsyndiv to %1d on %4d\n",
1235 + new_bias, synth_freq);
1236 +
1237 + /* swizzle rf_pwd_icsyndiv */
1238 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
1239 +
1240 + /* write Bank 6 with new params */
1241 + REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
1242 +}
1243 +
1244 +/**
1245 + * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
1246 + * @ah: atheros hardware stucture
1247 + * @chan:
1248 + *
1249 + * For the external AR2133/AR5133 radios, takes the MHz channel value and set
1250 + * the channel value. Assumes writes enabled to analog bus and bank6 register
1251 + * cache in ah->analogBank6Data.
1252 + */
1253 +static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
1254 +{
1255 + struct ath_common *common = ath9k_hw_common(ah);
1256 + u32 channelSel = 0;
1257 + u32 bModeSynth = 0;
1258 + u32 aModeRefSel = 0;
1259 + u32 reg32 = 0;
1260 + u16 freq;
1261 + struct chan_centers centers;
1262 +
1263 + ath9k_hw_get_channel_centers(ah, chan, &centers);
1264 + freq = centers.synth_center;
1265 +
1266 + if (freq < 4800) {
1267 + u32 txctl;
1268 +
1269 + if (((freq - 2192) % 5) == 0) {
1270 + channelSel = ((freq - 672) * 2 - 3040) / 10;
1271 + bModeSynth = 0;
1272 + } else if (((freq - 2224) % 5) == 0) {
1273 + channelSel = ((freq - 704) * 2 - 3040) / 10;
1274 + bModeSynth = 1;
1275 + } else {
1276 + ath_print(common, ATH_DBG_FATAL,
1277 + "Invalid channel %u MHz\n", freq);
1278 + return -EINVAL;
1279 + }
1280 +
1281 + channelSel = (channelSel << 2) & 0xff;
1282 + channelSel = ath9k_hw_reverse_bits(channelSel, 8);
1283 +
1284 + txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
1285 + if (freq == 2484) {
1286 +
1287 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
1288 + txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
1289 + } else {
1290 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
1291 + txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
1292 + }
1293 +
1294 + } else if ((freq % 20) == 0 && freq >= 5120) {
1295 + channelSel =
1296 + ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
1297 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1298 + } else if ((freq % 10) == 0) {
1299 + channelSel =
1300 + ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
1301 + if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
1302 + aModeRefSel = ath9k_hw_reverse_bits(2, 2);
1303 + else
1304 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1305 + } else if ((freq % 5) == 0) {
1306 + channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
1307 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1308 + } else {
1309 + ath_print(common, ATH_DBG_FATAL,
1310 + "Invalid channel %u MHz\n", freq);
1311 + return -EINVAL;
1312 + }
1313 +
1314 + ar5008_hw_force_bias(ah, freq);
1315 +
1316 + reg32 =
1317 + (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
1318 + (1 << 5) | 0x1;
1319 +
1320 + REG_WRITE(ah, AR_PHY(0x37), reg32);
1321 +
1322 + ah->curchan = chan;
1323 + ah->curchan_rad_index = -1;
1324 +
1325 + return 0;
1326 +}
1327 +
1328 +/**
1329 + * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
1330 + * @ah: atheros hardware structure
1331 + * @chan:
1332 + *
1333 + * For non single-chip solutions. Converts to baseband spur frequency given the
1334 + * input channel frequency and compute register settings below.
1335 + */
1336 +static void ar5008_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1337 +{
1338 + int bb_spur = AR_NO_SPUR;
1339 + int bin, cur_bin;
1340 + int spur_freq_sd;
1341 + int spur_delta_phase;
1342 + int denominator;
1343 + int upper, lower, cur_vit_mask;
1344 + int tmp, new;
1345 + int i;
1346 + int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1347 + AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1348 + };
1349 + int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1350 + AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1351 + };
1352 + int inc[4] = { 0, 100, 0, 0 };
1353 +
1354 + int8_t mask_m[123];
1355 + int8_t mask_p[123];
1356 + int8_t mask_amt;
1357 + int tmp_mask;
1358 + int cur_bb_spur;
1359 + bool is2GHz = IS_CHAN_2GHZ(chan);
1360 +
1361 + memset(&mask_m, 0, sizeof(int8_t) * 123);
1362 + memset(&mask_p, 0, sizeof(int8_t) * 123);
1363 +
1364 + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1365 + cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1366 + if (AR_NO_SPUR == cur_bb_spur)
1367 + break;
1368 + cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1369 + if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1370 + bb_spur = cur_bb_spur;
1371 + break;
1372 + }
1373 + }
1374 +
1375 + if (AR_NO_SPUR == bb_spur)
1376 + return;
1377 +
1378 + bin = bb_spur * 32;
1379 +
1380 + tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1381 + new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1382 + AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1383 + AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1384 + AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1385 +
1386 + REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
1387 +
1388 + new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1389 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1390 + AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1391 + AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1392 + SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1393 + REG_WRITE(ah, AR_PHY_SPUR_REG, new);
1394 +
1395 + spur_delta_phase = ((bb_spur * 524288) / 100) &
1396 + AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1397 +
1398 + denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
1399 + spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
1400 +
1401 + new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1402 + SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1403 + SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1404 + REG_WRITE(ah, AR_PHY_TIMING11, new);
1405 +
1406 + cur_bin = -6000;
1407 + upper = bin + 100;
1408 + lower = bin - 100;
1409 +
1410 + for (i = 0; i < 4; i++) {
1411 + int pilot_mask = 0;
1412 + int chan_mask = 0;
1413 + int bp = 0;
1414 + for (bp = 0; bp < 30; bp++) {
1415 + if ((cur_bin > lower) && (cur_bin < upper)) {
1416 + pilot_mask = pilot_mask | 0x1 << bp;
1417 + chan_mask = chan_mask | 0x1 << bp;
1418 + }
1419 + cur_bin += 100;
1420 + }
1421 + cur_bin += inc[i];
1422 + REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1423 + REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1424 + }
1425 +
1426 + cur_vit_mask = 6100;
1427 + upper = bin + 120;
1428 + lower = bin - 120;
1429 +
1430 + for (i = 0; i < 123; i++) {
1431 + if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1432 +
1433 + /* workaround for gcc bug #37014 */
1434 + volatile int tmp_v = abs(cur_vit_mask - bin);
1435 +
1436 + if (tmp_v < 75)
1437 + mask_amt = 1;
1438 + else
1439 + mask_amt = 0;
1440 + if (cur_vit_mask < 0)
1441 + mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1442 + else
1443 + mask_p[cur_vit_mask / 100] = mask_amt;
1444 + }
1445 + cur_vit_mask -= 100;
1446 + }
1447 +
1448 + tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1449 + | (mask_m[48] << 26) | (mask_m[49] << 24)
1450 + | (mask_m[50] << 22) | (mask_m[51] << 20)
1451 + | (mask_m[52] << 18) | (mask_m[53] << 16)
1452 + | (mask_m[54] << 14) | (mask_m[55] << 12)
1453 + | (mask_m[56] << 10) | (mask_m[57] << 8)
1454 + | (mask_m[58] << 6) | (mask_m[59] << 4)
1455 + | (mask_m[60] << 2) | (mask_m[61] << 0);
1456 + REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1457 + REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1458 +
1459 + tmp_mask = (mask_m[31] << 28)
1460 + | (mask_m[32] << 26) | (mask_m[33] << 24)
1461 + | (mask_m[34] << 22) | (mask_m[35] << 20)
1462 + | (mask_m[36] << 18) | (mask_m[37] << 16)
1463 + | (mask_m[48] << 14) | (mask_m[39] << 12)
1464 + | (mask_m[40] << 10) | (mask_m[41] << 8)
1465 + | (mask_m[42] << 6) | (mask_m[43] << 4)
1466 + | (mask_m[44] << 2) | (mask_m[45] << 0);
1467 + REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1468 + REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1469 +
1470 + tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1471 + | (mask_m[18] << 26) | (mask_m[18] << 24)
1472 + | (mask_m[20] << 22) | (mask_m[20] << 20)
1473 + | (mask_m[22] << 18) | (mask_m[22] << 16)
1474 + | (mask_m[24] << 14) | (mask_m[24] << 12)
1475 + | (mask_m[25] << 10) | (mask_m[26] << 8)
1476 + | (mask_m[27] << 6) | (mask_m[28] << 4)
1477 + | (mask_m[29] << 2) | (mask_m[30] << 0);
1478 + REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1479 + REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1480 +
1481 + tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1482 + | (mask_m[2] << 26) | (mask_m[3] << 24)
1483 + | (mask_m[4] << 22) | (mask_m[5] << 20)
1484 + | (mask_m[6] << 18) | (mask_m[7] << 16)
1485 + | (mask_m[8] << 14) | (mask_m[9] << 12)
1486 + | (mask_m[10] << 10) | (mask_m[11] << 8)
1487 + | (mask_m[12] << 6) | (mask_m[13] << 4)
1488 + | (mask_m[14] << 2) | (mask_m[15] << 0);
1489 + REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1490 + REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1491 +
1492 + tmp_mask = (mask_p[15] << 28)
1493 + | (mask_p[14] << 26) | (mask_p[13] << 24)
1494 + | (mask_p[12] << 22) | (mask_p[11] << 20)
1495 + | (mask_p[10] << 18) | (mask_p[9] << 16)
1496 + | (mask_p[8] << 14) | (mask_p[7] << 12)
1497 + | (mask_p[6] << 10) | (mask_p[5] << 8)
1498 + | (mask_p[4] << 6) | (mask_p[3] << 4)
1499 + | (mask_p[2] << 2) | (mask_p[1] << 0);
1500 + REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1501 + REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1502 +
1503 + tmp_mask = (mask_p[30] << 28)
1504 + | (mask_p[29] << 26) | (mask_p[28] << 24)
1505 + | (mask_p[27] << 22) | (mask_p[26] << 20)
1506 + | (mask_p[25] << 18) | (mask_p[24] << 16)
1507 + | (mask_p[23] << 14) | (mask_p[22] << 12)
1508 + | (mask_p[21] << 10) | (mask_p[20] << 8)
1509 + | (mask_p[19] << 6) | (mask_p[18] << 4)
1510 + | (mask_p[17] << 2) | (mask_p[16] << 0);
1511 + REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1512 + REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1513 +
1514 + tmp_mask = (mask_p[45] << 28)
1515 + | (mask_p[44] << 26) | (mask_p[43] << 24)
1516 + | (mask_p[42] << 22) | (mask_p[41] << 20)
1517 + | (mask_p[40] << 18) | (mask_p[39] << 16)
1518 + | (mask_p[38] << 14) | (mask_p[37] << 12)
1519 + | (mask_p[36] << 10) | (mask_p[35] << 8)
1520 + | (mask_p[34] << 6) | (mask_p[33] << 4)
1521 + | (mask_p[32] << 2) | (mask_p[31] << 0);
1522 + REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1523 + REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1524 +
1525 + tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1526 + | (mask_p[59] << 26) | (mask_p[58] << 24)
1527 + | (mask_p[57] << 22) | (mask_p[56] << 20)
1528 + | (mask_p[55] << 18) | (mask_p[54] << 16)
1529 + | (mask_p[53] << 14) | (mask_p[52] << 12)
1530 + | (mask_p[51] << 10) | (mask_p[50] << 8)
1531 + | (mask_p[49] << 6) | (mask_p[48] << 4)
1532 + | (mask_p[47] << 2) | (mask_p[46] << 0);
1533 + REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1534 + REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1535 +}
1536 +
1537 +/**
1538 + * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
1539 + * @ah: atheros hardware structure
1540 + *
1541 + * Only required for older devices with external AR2133/AR5133 radios.
1542 + */
1543 +static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
1544 +{
1545 +#define ATH_ALLOC_BANK(bank, size) do { \
1546 + bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
1547 + if (!bank) { \
1548 + ath_print(common, ATH_DBG_FATAL, \
1549 + "Cannot allocate RF banks\n"); \
1550 + return -ENOMEM; \
1551 + } \
1552 + } while (0);
1553 +
1554 + struct ath_common *common = ath9k_hw_common(ah);
1555 +
1556 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1557 +
1558 + ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
1559 + ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
1560 + ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
1561 + ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
1562 + ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
1563 + ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
1564 + ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
1565 + ATH_ALLOC_BANK(ah->addac5416_21,
1566 + ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
1567 + ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
1568 +
1569 + return 0;
1570 +#undef ATH_ALLOC_BANK
1571 +}
1572 +
1573 +
1574 +/**
1575 + * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
1576 + * @ah: atheros hardware struture
1577 + * For the external AR2133/AR5133 radios banks.
1578 + */
1579 +static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
1580 +{
1581 +#define ATH_FREE_BANK(bank) do { \
1582 + kfree(bank); \
1583 + bank = NULL; \
1584 + } while (0);
1585 +
1586 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1587 +
1588 + ATH_FREE_BANK(ah->analogBank0Data);
1589 + ATH_FREE_BANK(ah->analogBank1Data);
1590 + ATH_FREE_BANK(ah->analogBank2Data);
1591 + ATH_FREE_BANK(ah->analogBank3Data);
1592 + ATH_FREE_BANK(ah->analogBank6Data);
1593 + ATH_FREE_BANK(ah->analogBank6TPCData);
1594 + ATH_FREE_BANK(ah->analogBank7Data);
1595 + ATH_FREE_BANK(ah->addac5416_21);
1596 + ATH_FREE_BANK(ah->bank6Temp);
1597 +
1598 +#undef ATH_FREE_BANK
1599 +}
1600 +
1601 +/* *
1602 + * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
1603 + * @ah: atheros hardware structure
1604 + * @chan:
1605 + * @modesIndex:
1606 + *
1607 + * Used for the external AR2133/AR5133 radios.
1608 + *
1609 + * Reads the EEPROM header info from the device structure and programs
1610 + * all rf registers. This routine requires access to the analog
1611 + * rf device. This is not required for single-chip devices.
1612 + */
1613 +static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
1614 + struct ath9k_channel *chan,
1615 + u16 modesIndex)
1616 +{
1617 + u32 eepMinorRev;
1618 + u32 ob5GHz = 0, db5GHz = 0;
1619 + u32 ob2GHz = 0, db2GHz = 0;
1620 + int regWrites = 0;
1621 +
1622 + /*
1623 + * Software does not need to program bank data
1624 + * for single chip devices, that is AR9280 or anything
1625 + * after that.
1626 + */
1627 + if (AR_SREV_9280_10_OR_LATER(ah))
1628 + return true;
1629 +
1630 + /* Setup rf parameters */
1631 + eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
1632 +
1633 + /* Setup Bank 0 Write */
1634 + RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
1635 +
1636 + /* Setup Bank 1 Write */
1637 + RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
1638 +
1639 + /* Setup Bank 2 Write */
1640 + RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
1641 +
1642 + /* Setup Bank 6 Write */
1643 + RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
1644 + modesIndex);
1645 + {
1646 + int i;
1647 + for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
1648 + ah->analogBank6Data[i] =
1649 + INI_RA(&ah->iniBank6TPC, i, modesIndex);
1650 + }
1651 + }
1652 +
1653 + /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
1654 + if (eepMinorRev >= 2) {
1655 + if (IS_CHAN_2GHZ(chan)) {
1656 + ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
1657 + db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
1658 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1659 + ob2GHz, 3, 197, 0);
1660 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1661 + db2GHz, 3, 194, 0);
1662 + } else {
1663 + ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
1664 + db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
1665 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1666 + ob5GHz, 3, 203, 0);
1667 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1668 + db5GHz, 3, 200, 0);
1669 + }
1670 + }
1671 +
1672 + /* Setup Bank 7 Setup */
1673 + RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
1674 +
1675 + /* Write Analog registers */
1676 + REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
1677 + regWrites);
1678 + REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
1679 + regWrites);
1680 + REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
1681 + regWrites);
1682 + REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
1683 + regWrites);
1684 + REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
1685 + regWrites);
1686 + REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
1687 + regWrites);
1688 +
1689 + return true;
1690 +}
1691 +
1692 +static void ar5008_hw_init_bb(struct ath_hw *ah,
1693 + struct ath9k_channel *chan)
1694 +{
1695 + u32 synthDelay;
1696 +
1697 + synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1698 + if (IS_CHAN_B(chan))
1699 + synthDelay = (4 * synthDelay) / 22;
1700 + else
1701 + synthDelay /= 10;
1702 +
1703 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1704 +
1705 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
1706 +}
1707 +
1708 +static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
1709 +{
1710 + int rx_chainmask, tx_chainmask;
1711 +
1712 + rx_chainmask = ah->rxchainmask;
1713 + tx_chainmask = ah->txchainmask;
1714 +
1715 + switch (rx_chainmask) {
1716 + case 0x5:
1717 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1718 + AR_PHY_SWAP_ALT_CHAIN);
1719 + case 0x3:
1720 + if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1721 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1722 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1723 + break;
1724 + }
1725 + case 0x1:
1726 + case 0x2:
1727 + case 0x7:
1728 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1729 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1730 + break;
1731 + default:
1732 + break;
1733 + }
1734 +
1735 + REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1736 + if (tx_chainmask == 0x5) {
1737 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1738 + AR_PHY_SWAP_ALT_CHAIN);
1739 + }
1740 + if (AR_SREV_9100(ah))
1741 + REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1742 + REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1743 +}
1744 +
1745 +static void ar5008_hw_override_ini(struct ath_hw *ah,
1746 + struct ath9k_channel *chan)
1747 +{
1748 + u32 val;
1749 +
1750 + /*
1751 + * Set the RX_ABORT and RX_DIS and clear if off only after
1752 + * RXE is set for MAC. This prevents frames with corrupted
1753 + * descriptor status.
1754 + */
1755 + REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1756 +
1757 + if (AR_SREV_9280_10_OR_LATER(ah)) {
1758 + val = REG_READ(ah, AR_PCU_MISC_MODE2);
1759 +
1760 + if (!AR_SREV_9271(ah))
1761 + val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1762 +
1763 + if (AR_SREV_9287_10_OR_LATER(ah))
1764 + val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1765 +
1766 + REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1767 + }
1768 +
1769 + if (!AR_SREV_5416_20_OR_LATER(ah) ||
1770 + AR_SREV_9280_10_OR_LATER(ah))
1771 + return;
1772 + /*
1773 + * Disable BB clock gating
1774 + * Necessary to avoid issues on AR5416 2.0
1775 + */
1776 + REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1777 +
1778 + /*
1779 + * Disable RIFS search on some chips to avoid baseband
1780 + * hang issues.
1781 + */
1782 + if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1783 + val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1784 + val &= ~AR_PHY_RIFS_INIT_DELAY;
1785 + REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1786 + }
1787 +}
1788 +
1789 +static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
1790 + struct ath9k_channel *chan)
1791 +{
1792 + u32 phymode;
1793 + u32 enableDacFifo = 0;
1794 +
1795 + if (AR_SREV_9285_10_OR_LATER(ah))
1796 + enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1797 + AR_PHY_FC_ENABLE_DAC_FIFO);
1798 +
1799 + phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1800 + | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1801 +
1802 + if (IS_CHAN_HT40(chan)) {
1803 + phymode |= AR_PHY_FC_DYN2040_EN;
1804 +
1805 + if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1806 + (chan->chanmode == CHANNEL_G_HT40PLUS))
1807 + phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1808 +
1809 + }
1810 + REG_WRITE(ah, AR_PHY_TURBO, phymode);
1811 +
1812 + ath9k_hw_set11nmac2040(ah);
1813 +
1814 + REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1815 + REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1816 +}
1817 +
1818 +
1819 +static int ar5008_hw_process_ini(struct ath_hw *ah,
1820 + struct ath9k_channel *chan)
1821 +{
1822 + struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1823 + int i, regWrites = 0;
1824 + struct ieee80211_channel *channel = chan->chan;
1825 + u32 modesIndex, freqIndex;
1826 +
1827 + switch (chan->chanmode) {
1828 + case CHANNEL_A:
1829 + case CHANNEL_A_HT20:
1830 + modesIndex = 1;
1831 + freqIndex = 1;
1832 + break;
1833 + case CHANNEL_A_HT40PLUS:
1834 + case CHANNEL_A_HT40MINUS:
1835 + modesIndex = 2;
1836 + freqIndex = 1;
1837 + break;
1838 + case CHANNEL_G:
1839 + case CHANNEL_G_HT20:
1840 + case CHANNEL_B:
1841 + modesIndex = 4;
1842 + freqIndex = 2;
1843 + break;
1844 + case CHANNEL_G_HT40PLUS:
1845 + case CHANNEL_G_HT40MINUS:
1846 + modesIndex = 3;
1847 + freqIndex = 2;
1848 + break;
1849 +
1850 + default:
1851 + return -EINVAL;
1852 + }
1853 +
1854 + if (AR_SREV_9287_12_OR_LATER(ah)) {
1855 + /* Enable ASYNC FIFO */
1856 + REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1857 + AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1858 + REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1859 + REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1860 + AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1861 + REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1862 + AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1863 + }
1864 +
1865 + /* Set correct baseband to analog shift setting to access analog chips */
1866 + REG_WRITE(ah, AR_PHY(0), 0x00000007);
1867 +
1868 + /* Write ADDAC shifts */
1869 + REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1870 + ah->eep_ops->set_addac(ah, chan);
1871 +
1872 + if (AR_SREV_5416_22_OR_LATER(ah)) {
1873 + REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1874 + } else {
1875 + struct ar5416IniArray temp;
1876 + u32 addacSize =
1877 + sizeof(u32) * ah->iniAddac.ia_rows *
1878 + ah->iniAddac.ia_columns;
1879 +
1880 + /* For AR5416 2.0/2.1 */
1881 + memcpy(ah->addac5416_21,
1882 + ah->iniAddac.ia_array, addacSize);
1883 +
1884 + /* override CLKDRV value at [row, column] = [31, 1] */
1885 + (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1886 +
1887 + temp.ia_array = ah->addac5416_21;
1888 + temp.ia_columns = ah->iniAddac.ia_columns;
1889 + temp.ia_rows = ah->iniAddac.ia_rows;
1890 + REG_WRITE_ARRAY(&temp, 1, regWrites);
1891 + }
1892 +
1893 + REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1894 +
1895 + for (i = 0; i < ah->iniModes.ia_rows; i++) {
1896 + u32 reg = INI_RA(&ah->iniModes, i, 0);
1897 + u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1898 +
1899 + if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
1900 + val &= ~AR_AN_TOP2_PWDCLKIND;
1901 +
1902 + REG_WRITE(ah, reg, val);
1903 +
1904 + if (reg >= 0x7800 && reg < 0x78a0
1905 + && ah->config.analog_shiftreg) {
1906 + udelay(100);
1907 + }
1908 +
1909 + DO_DELAY(regWrites);
1910 + }
1911 +
1912 + if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1913 + REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1914 +
1915 + if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1916 + AR_SREV_9287_10_OR_LATER(ah))
1917 + REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1918 +
1919 + if (AR_SREV_9271_10(ah))
1920 + REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1921 + modesIndex, regWrites);
1922 +
1923 + /* Write common array parameters */
1924 + for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1925 + u32 reg = INI_RA(&ah->iniCommon, i, 0);
1926 + u32 val = INI_RA(&ah->iniCommon, i, 1);
1927 +
1928 + REG_WRITE(ah, reg, val);
1929 +
1930 + if (reg >= 0x7800 && reg < 0x78a0
1931 + && ah->config.analog_shiftreg) {
1932 + udelay(100);
1933 + }
1934 +
1935 + DO_DELAY(regWrites);
1936 + }
1937 +
1938 + if (AR_SREV_9271(ah)) {
1939 + if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1940 + REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1941 + modesIndex, regWrites);
1942 + else
1943 + REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1944 + modesIndex, regWrites);
1945 + }
1946 +
1947 + REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
1948 +
1949 + if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1950 + REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1951 + regWrites);
1952 + }
1953 +
1954 + ar5008_hw_override_ini(ah, chan);
1955 + ar5008_hw_set_channel_regs(ah, chan);
1956 + ar5008_hw_init_chain_masks(ah);
1957 + ath9k_olc_init(ah);
1958 +
1959 + /* Set TX power */
1960 + ah->eep_ops->set_txpower(ah, chan,
1961 + ath9k_regd_get_ctl(regulatory, chan),
1962 + channel->max_antenna_gain * 2,
1963 + channel->max_power * 2,
1964 + min((u32) MAX_RATE_POWER,
1965 + (u32) regulatory->power_limit));
1966 +
1967 + /* Write analog registers */
1968 + if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1969 + ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1970 + "ar5416SetRfRegs failed\n");
1971 + return -EIO;
1972 + }
1973 +
1974 + return 0;
1975 +}
1976 +
1977 +static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1978 +{
1979 + u32 rfMode = 0;
1980 +
1981 + if (chan == NULL)
1982 + return;
1983 +
1984 + rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1985 + ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1986 +
1987 + if (!AR_SREV_9280_10_OR_LATER(ah))
1988 + rfMode |= (IS_CHAN_5GHZ(chan)) ?
1989 + AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1990 +
1991 + if ((AR_SREV_9280_20(ah) || AR_SREV_9300_20_OR_LATER(ah))
1992 + && IS_CHAN_A_5MHZ_SPACED(chan))
1993 + rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1994 +
1995 + REG_WRITE(ah, AR_PHY_MODE, rfMode);
1996 +}
1997 +
1998 +static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
1999 +{
2000 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
2001 +}
2002 +
2003 +static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
2004 + struct ath9k_channel *chan)
2005 +{
2006 + u32 coef_scaled, ds_coef_exp, ds_coef_man;
2007 + u32 clockMhzScaled = 0x64000000;
2008 + struct chan_centers centers;
2009 +
2010 + if (IS_CHAN_HALF_RATE(chan))
2011 + clockMhzScaled = clockMhzScaled >> 1;
2012 + else if (IS_CHAN_QUARTER_RATE(chan))
2013 + clockMhzScaled = clockMhzScaled >> 2;
2014 +
2015 + ath9k_hw_get_channel_centers(ah, chan, &centers);
2016 + coef_scaled = clockMhzScaled / centers.synth_center;
2017 +
2018 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
2019 + &ds_coef_exp);
2020 +
2021 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
2022 + AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
2023 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
2024 + AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
2025 +
2026 + coef_scaled = (9 * coef_scaled) / 10;
2027 +
2028 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
2029 + &ds_coef_exp);
2030 +
2031 + REG_RMW_FIELD(ah, AR_PHY_HALFGI,
2032 + AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
2033 + REG_RMW_FIELD(ah, AR_PHY_HALFGI,
2034 + AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
2035 +}
2036 +
2037 +static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
2038 +{
2039 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
2040 + return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
2041 + AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
2042 +}
2043 +
2044 +static void ar5008_hw_rfbus_done(struct ath_hw *ah)
2045 +{
2046 + u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
2047 + if (IS_CHAN_B(ah->curchan))
2048 + synthDelay = (4 * synthDelay) / 22;
2049 + else
2050 + synthDelay /= 10;
2051 +
2052 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
2053 +
2054 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
2055 +}
2056 +
2057 +static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
2058 +{
2059 + REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2060 + AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2061 +
2062 + REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2063 + AR_GPIO_INPUT_MUX2_RFSILENT);
2064 +
2065 + ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2066 + REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2067 +}
2068 +
2069 +static void ar5008_restore_chainmask(struct ath_hw *ah)
2070 +{
2071 + int rx_chainmask = ah->rxchainmask;
2072 +
2073 + if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2074 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2075 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2076 + }
2077 +}
2078 +
2079 +static void ar5008_set_diversity(struct ath_hw *ah, bool value)
2080 +{
2081 + u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
2082 + if (value)
2083 + v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
2084 + else
2085 + v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
2086 + REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
2087 +}
2088 +
2089 +static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
2090 + struct ath9k_channel *chan)
2091 +{
2092 + if (chan && IS_CHAN_5GHZ(chan))
2093 + return 0x1450;
2094 + return 0x1458;
2095 +}
2096 +
2097 +static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
2098 + struct ath9k_channel *chan)
2099 +{
2100 + u32 pll;
2101 +
2102 + pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
2103 +
2104 + if (chan && IS_CHAN_HALF_RATE(chan))
2105 + pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
2106 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
2107 + pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
2108 +
2109 + if (chan && IS_CHAN_5GHZ(chan))
2110 + pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
2111 + else
2112 + pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
2113 +
2114 + return pll;
2115 +}
2116 +
2117 +static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
2118 + struct ath9k_channel *chan)
2119 +{
2120 + u32 pll;
2121 +
2122 + pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
2123 +
2124 + if (chan && IS_CHAN_HALF_RATE(chan))
2125 + pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
2126 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
2127 + pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
2128 +
2129 + if (chan && IS_CHAN_5GHZ(chan))
2130 + pll |= SM(0xa, AR_RTC_PLL_DIV);
2131 + else
2132 + pll |= SM(0xb, AR_RTC_PLL_DIV);
2133 +
2134 + return pll;
2135 +}
2136 +
2137 +static bool ar5008_hw_ani_control(struct ath_hw *ah,
2138 + enum ath9k_ani_cmd cmd, int param)
2139 +{
2140 + struct ar5416AniState *aniState = ah->curani;
2141 + struct ath_common *common = ath9k_hw_common(ah);
2142 +
2143 + switch (cmd & ah->ani_function) {
2144 + case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
2145 + u32 level = param;
2146 +
2147 + if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
2148 + ath_print(common, ATH_DBG_ANI,
2149 + "level out of range (%u > %u)\n",
2150 + level,
2151 + (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
2152 + return false;
2153 + }
2154 +
2155 + REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2156 + AR_PHY_DESIRED_SZ_TOT_DES,
2157 + ah->totalSizeDesired[level]);
2158 + REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2159 + AR_PHY_AGC_CTL1_COARSE_LOW,
2160 + ah->coarse_low[level]);
2161 + REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2162 + AR_PHY_AGC_CTL1_COARSE_HIGH,
2163 + ah->coarse_high[level]);
2164 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2165 + AR_PHY_FIND_SIG_FIRPWR,
2166 + ah->firpwr[level]);
2167 +
2168 + if (level > aniState->noiseImmunityLevel)
2169 + ah->stats.ast_ani_niup++;
2170 + else if (level < aniState->noiseImmunityLevel)
2171 + ah->stats.ast_ani_nidown++;
2172 + aniState->noiseImmunityLevel = level;
2173 + break;
2174 + }
2175 + case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2176 + const int m1ThreshLow[] = { 127, 50 };
2177 + const int m2ThreshLow[] = { 127, 40 };
2178 + const int m1Thresh[] = { 127, 0x4d };
2179 + const int m2Thresh[] = { 127, 0x40 };
2180 + const int m2CountThr[] = { 31, 16 };
2181 + const int m2CountThrLow[] = { 63, 48 };
2182 + u32 on = param ? 1 : 0;
2183 +
2184 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2185 + AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2186 + m1ThreshLow[on]);
2187 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2188 + AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2189 + m2ThreshLow[on]);
2190 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2191 + AR_PHY_SFCORR_M1_THRESH,
2192 + m1Thresh[on]);
2193 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2194 + AR_PHY_SFCORR_M2_THRESH,
2195 + m2Thresh[on]);
2196 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2197 + AR_PHY_SFCORR_M2COUNT_THR,
2198 + m2CountThr[on]);
2199 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2200 + AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2201 + m2CountThrLow[on]);
2202 +
2203 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2204 + AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2205 + m1ThreshLow[on]);
2206 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2207 + AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2208 + m2ThreshLow[on]);
2209 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2210 + AR_PHY_SFCORR_EXT_M1_THRESH,
2211 + m1Thresh[on]);
2212 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2213 + AR_PHY_SFCORR_EXT_M2_THRESH,
2214 + m2Thresh[on]);
2215 +
2216 + if (on)
2217 + REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2218 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2219 + else
2220 + REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
2221 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2222 +
2223 + if (!on != aniState->ofdmWeakSigDetectOff) {
2224 + if (on)
2225 + ah->stats.ast_ani_ofdmon++;
2226 + else
2227 + ah->stats.ast_ani_ofdmoff++;
2228 + aniState->ofdmWeakSigDetectOff = !on;
2229 + }
2230 + break;
2231 + }
2232 + case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
2233 + const int weakSigThrCck[] = { 8, 6 };
2234 + u32 high = param ? 1 : 0;
2235 +
2236 + REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2237 + AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2238 + weakSigThrCck[high]);
2239 + if (high != aniState->cckWeakSigThreshold) {
2240 + if (high)
2241 + ah->stats.ast_ani_cckhigh++;
2242 + else
2243 + ah->stats.ast_ani_ccklow++;
2244 + aniState->cckWeakSigThreshold = high;
2245 + }
2246 + break;
2247 + }
2248 + case ATH9K_ANI_FIRSTEP_LEVEL:{
2249 + const int firstep[] = { 0, 4, 8 };
2250 + u32 level = param;
2251 +
2252 + if (level >= ARRAY_SIZE(firstep)) {
2253 + ath_print(common, ATH_DBG_ANI,
2254 + "level out of range (%u > %u)\n",
2255 + level,
2256 + (unsigned) ARRAY_SIZE(firstep));
2257 + return false;
2258 + }
2259 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2260 + AR_PHY_FIND_SIG_FIRSTEP,
2261 + firstep[level]);
2262 + if (level > aniState->firstepLevel)
2263 + ah->stats.ast_ani_stepup++;
2264 + else if (level < aniState->firstepLevel)
2265 + ah->stats.ast_ani_stepdown++;
2266 + aniState->firstepLevel = level;
2267 + break;
2268 + }
2269 + case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
2270 + const int cycpwrThr1[] =
2271 + { 2, 4, 6, 8, 10, 12, 14, 16 };
2272 + u32 level = param;
2273 +
2274 + if (level >= ARRAY_SIZE(cycpwrThr1)) {
2275 + ath_print(common, ATH_DBG_ANI,
2276 + "level out of range (%u > %u)\n",
2277 + level,
2278 + (unsigned) ARRAY_SIZE(cycpwrThr1));
2279 + return false;
2280 + }
2281 + REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2282 + AR_PHY_TIMING5_CYCPWR_THR1,
2283 + cycpwrThr1[level]);
2284 + if (level > aniState->spurImmunityLevel)
2285 + ah->stats.ast_ani_spurup++;
2286 + else if (level < aniState->spurImmunityLevel)
2287 + ah->stats.ast_ani_spurdown++;
2288 + aniState->spurImmunityLevel = level;
2289 + break;
2290 + }
2291 + case ATH9K_ANI_PRESENT:
2292 + break;
2293 + default:
2294 + ath_print(common, ATH_DBG_ANI,
2295 + "invalid cmd %u\n", cmd);
2296 + return false;
2297 + }
2298 +
2299 + ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
2300 + ath_print(common, ATH_DBG_ANI,
2301 + "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2302 + "ofdmWeakSigDetectOff=%d\n",
2303 + aniState->noiseImmunityLevel,
2304 + aniState->spurImmunityLevel,
2305 + !aniState->ofdmWeakSigDetectOff);
2306 + ath_print(common, ATH_DBG_ANI,
2307 + "cckWeakSigThreshold=%d, "
2308 + "firstepLevel=%d, listenTime=%d\n",
2309 + aniState->cckWeakSigThreshold,
2310 + aniState->firstepLevel,
2311 + aniState->listenTime);
2312 + ath_print(common, ATH_DBG_ANI,
2313 + "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2314 + aniState->cycleCount,
2315 + aniState->ofdmPhyErrCount,
2316 + aniState->cckPhyErrCount);
2317 +
2318 + return true;
2319 +}
2320 +
2321 +static void ar5008_hw_do_getnf(struct ath_hw *ah,
2322 + int16_t nfarray[NUM_NF_READINGS])
2323 +{
2324 + struct ath_common *common = ath9k_hw_common(ah);
2325 + int16_t nf;
2326 +
2327 + nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
2328 + if (nf & 0x100)
2329 + nf = 0 - ((nf ^ 0x1ff) + 1);
2330 + ath_print(common, ATH_DBG_CALIBRATE,
2331 + "NF calibrated [ctl] [chain 0] is %d\n", nf);
2332 + nfarray[0] = nf;
2333 +
2334 + nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
2335 + if (nf & 0x100)
2336 + nf = 0 - ((nf ^ 0x1ff) + 1);
2337 + ath_print(common, ATH_DBG_CALIBRATE,
2338 + "NF calibrated [ctl] [chain 1] is %d\n", nf);
2339 + nfarray[1] = nf;
2340 +
2341 + nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
2342 + if (nf & 0x100)
2343 + nf = 0 - ((nf ^ 0x1ff) + 1);
2344 + ath_print(common, ATH_DBG_CALIBRATE,
2345 + "NF calibrated [ctl] [chain 2] is %d\n", nf);
2346 + nfarray[2] = nf;
2347 +
2348 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
2349 + if (nf & 0x100)
2350 + nf = 0 - ((nf ^ 0x1ff) + 1);
2351 + ath_print(common, ATH_DBG_CALIBRATE,
2352 + "NF calibrated [ext] [chain 0] is %d\n", nf);
2353 + nfarray[3] = nf;
2354 +
2355 + nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
2356 + if (nf & 0x100)
2357 + nf = 0 - ((nf ^ 0x1ff) + 1);
2358 + ath_print(common, ATH_DBG_CALIBRATE,
2359 + "NF calibrated [ext] [chain 1] is %d\n", nf);
2360 + nfarray[4] = nf;
2361 +
2362 + nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
2363 + if (nf & 0x100)
2364 + nf = 0 - ((nf ^ 0x1ff) + 1);
2365 + ath_print(common, ATH_DBG_CALIBRATE,
2366 + "NF calibrated [ext] [chain 2] is %d\n", nf);
2367 + nfarray[5] = nf;
2368 +}
2369 +
2370 +void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
2371 +{
2372 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
2373 +
2374 + priv_ops->rf_set_freq = ar5008_hw_set_channel;
2375 + priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
2376 +
2377 + priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
2378 + priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
2379 + priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
2380 + priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
2381 + priv_ops->init_bb = ar5008_hw_init_bb;
2382 + priv_ops->process_ini = ar5008_hw_process_ini;
2383 + priv_ops->set_rfmode = ar5008_hw_set_rfmode;
2384 + priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
2385 + priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
2386 + priv_ops->rfbus_req = ar5008_hw_rfbus_req;
2387 + priv_ops->rfbus_done = ar5008_hw_rfbus_done;
2388 + priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
2389 + priv_ops->restore_chainmask = ar5008_restore_chainmask;
2390 + priv_ops->set_diversity = ar5008_set_diversity;
2391 + priv_ops->ani_control = ar5008_hw_ani_control;
2392 + priv_ops->do_getnf = ar5008_hw_do_getnf;
2393 +
2394 + if (AR_SREV_9100(ah))
2395 + priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
2396 + else if (AR_SREV_9160_10_OR_LATER(ah))
2397 + priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
2398 + else
2399 + priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
2400 +}
2401 diff --git a/drivers/net/wireless/ath/ath9k/ar9001_initvals.h b/drivers/net/wireless/ath/ath9k/ar9001_initvals.h
2402 new file mode 100644
2403 index 0000000..3e34dc9
2404 --- /dev/null
2405 +++ b/drivers/net/wireless/ath/ath9k/ar9001_initvals.h
2406 @@ -0,0 +1,1314 @@
2407 +
2408 +static const u32 ar5416Common_9100[][2] = {
2409 + {0x0000000c, 0x00000000},
2410 + {0x00000030, 0x00020015},
2411 + {0x00000034, 0x00000005},
2412 + {0x00000040, 0x00000000},
2413 + {0x00000044, 0x00000008},
2414 + {0x00000048, 0x00000008},
2415 + {0x0000004c, 0x00000010},
2416 + {0x00000050, 0x00000000},
2417 + {0x00000054, 0x0000001f},
2418 + {0x00000800, 0x00000000},
2419 + {0x00000804, 0x00000000},
2420 + {0x00000808, 0x00000000},
2421 + {0x0000080c, 0x00000000},
2422 + {0x00000810, 0x00000000},
2423 + {0x00000814, 0x00000000},
2424 + {0x00000818, 0x00000000},
2425 + {0x0000081c, 0x00000000},
2426 + {0x00000820, 0x00000000},
2427 + {0x00000824, 0x00000000},
2428 + {0x00001040, 0x002ffc0f},
2429 + {0x00001044, 0x002ffc0f},
2430 + {0x00001048, 0x002ffc0f},
2431 + {0x0000104c, 0x002ffc0f},
2432 + {0x00001050, 0x002ffc0f},
2433 + {0x00001054, 0x002ffc0f},
2434 + {0x00001058, 0x002ffc0f},
2435 + {0x0000105c, 0x002ffc0f},
2436 + {0x00001060, 0x002ffc0f},
2437 + {0x00001064, 0x002ffc0f},
2438 + {0x00001230, 0x00000000},
2439 + {0x00001270, 0x00000000},
2440 + {0x00001038, 0x00000000},
2441 + {0x00001078, 0x00000000},
2442 + {0x000010b8, 0x00000000},
2443 + {0x000010f8, 0x00000000},
2444 + {0x00001138, 0x00000000},
2445 + {0x00001178, 0x00000000},
2446 + {0x000011b8, 0x00000000},
2447 + {0x000011f8, 0x00000000},
2448 + {0x00001238, 0x00000000},
2449 + {0x00001278, 0x00000000},
2450 + {0x000012b8, 0x00000000},
2451 + {0x000012f8, 0x00000000},
2452 + {0x00001338, 0x00000000},
2453 + {0x00001378, 0x00000000},
2454 + {0x000013b8, 0x00000000},
2455 + {0x000013f8, 0x00000000},
2456 + {0x00001438, 0x00000000},
2457 + {0x00001478, 0x00000000},
2458 + {0x000014b8, 0x00000000},
2459 + {0x000014f8, 0x00000000},
2460 + {0x00001538, 0x00000000},
2461 + {0x00001578, 0x00000000},
2462 + {0x000015b8, 0x00000000},
2463 + {0x000015f8, 0x00000000},
2464 + {0x00001638, 0x00000000},
2465 + {0x00001678, 0x00000000},
2466 + {0x000016b8, 0x00000000},
2467 + {0x000016f8, 0x00000000},
2468 + {0x00001738, 0x00000000},
2469 + {0x00001778, 0x00000000},
2470 + {0x000017b8, 0x00000000},
2471 + {0x000017f8, 0x00000000},
2472 + {0x0000103c, 0x00000000},
2473 + {0x0000107c, 0x00000000},
2474 + {0x000010bc, 0x00000000},
2475 + {0x000010fc, 0x00000000},
2476 + {0x0000113c, 0x00000000},
2477 + {0x0000117c, 0x00000000},
2478 + {0x000011bc, 0x00000000},
2479 + {0x000011fc, 0x00000000},
2480 + {0x0000123c, 0x00000000},
2481 + {0x0000127c, 0x00000000},
2482 + {0x000012bc, 0x00000000},
2483 + {0x000012fc, 0x00000000},
2484 + {0x0000133c, 0x00000000},
2485 + {0x0000137c, 0x00000000},
2486 + {0x000013bc, 0x00000000},
2487 + {0x000013fc, 0x00000000},
2488 + {0x0000143c, 0x00000000},
2489 + {0x0000147c, 0x00000000},
2490 + {0x00020010, 0x00000003},
2491 + {0x00020038, 0x000004c2},
2492 + {0x00008004, 0x00000000},
2493 + {0x00008008, 0x00000000},
2494 + {0x0000800c, 0x00000000},
2495 + {0x00008018, 0x00000700},
2496 + {0x00008020, 0x00000000},
2497 + {0x00008038, 0x00000000},
2498 + {0x0000803c, 0x00000000},
2499 + {0x00008048, 0x40000000},
2500 + {0x00008054, 0x00004000},
2501 + {0x00008058, 0x00000000},
2502 + {0x0000805c, 0x000fc78f},
2503 + {0x00008060, 0x0000000f},
2504 + {0x00008064, 0x00000000},
2505 + {0x000080c0, 0x2a82301a},
2506 + {0x000080c4, 0x05dc01e0},
2507 + {0x000080c8, 0x1f402710},
2508 + {0x000080cc, 0x01f40000},
2509 + {0x000080d0, 0x00001e00},
2510 + {0x000080d4, 0x00000000},
2511 + {0x000080d8, 0x00400000},
2512 + {0x000080e0, 0xffffffff},
2513 + {0x000080e4, 0x0000ffff},
2514 + {0x000080e8, 0x003f3f3f},
2515 + {0x000080ec, 0x00000000},
2516 + {0x000080f0, 0x00000000},
2517 + {0x000080f4, 0x00000000},
2518 + {0x000080f8, 0x00000000},
2519 + {0x000080fc, 0x00020000},
2520 + {0x00008100, 0x00020000},
2521 + {0x00008104, 0x00000001},
2522 + {0x00008108, 0x00000052},
2523 + {0x0000810c, 0x00000000},
2524 + {0x00008110, 0x00000168},
2525 + {0x00008118, 0x000100aa},
2526 + {0x0000811c, 0x00003210},
2527 + {0x00008120, 0x08f04800},
2528 + {0x00008124, 0x00000000},
2529 + {0x00008128, 0x00000000},
2530 + {0x0000812c, 0x00000000},
2531 + {0x00008130, 0x00000000},
2532 + {0x00008134, 0x00000000},
2533 + {0x00008138, 0x00000000},
2534 + {0x0000813c, 0x00000000},
2535 + {0x00008144, 0x00000000},
2536 + {0x00008168, 0x00000000},
2537 + {0x0000816c, 0x00000000},
2538 + {0x00008170, 0x32143320},
2539 + {0x00008174, 0xfaa4fa50},
2540 + {0x00008178, 0x00000100},
2541 + {0x0000817c, 0x00000000},
2542 + {0x000081c4, 0x00000000},
2543 + {0x000081d0, 0x00003210},
2544 + {0x000081ec, 0x00000000},
2545 + {0x000081f0, 0x00000000},
2546 + {0x000081f4, 0x00000000},
2547 + {0x000081f8, 0x00000000},
2548 + {0x000081fc, 0x00000000},
2549 + {0x00008200, 0x00000000},
2550 + {0x00008204, 0x00000000},
2551 + {0x00008208, 0x00000000},
2552 + {0x0000820c, 0x00000000},
2553 + {0x00008210, 0x00000000},
2554 + {0x00008214, 0x00000000},
2555 + {0x00008218, 0x00000000},
2556 + {0x0000821c, 0x00000000},
2557 + {0x00008220, 0x00000000},
2558 + {0x00008224, 0x00000000},
2559 + {0x00008228, 0x00000000},
2560 + {0x0000822c, 0x00000000},
2561 + {0x00008230, 0x00000000},
2562 + {0x00008234, 0x00000000},
2563 + {0x00008238, 0x00000000},
2564 + {0x0000823c, 0x00000000},
2565 + {0x00008240, 0x00100000},
2566 + {0x00008244, 0x0010f400},
2567 + {0x00008248, 0x00000100},
2568 + {0x0000824c, 0x0001e800},
2569 + {0x00008250, 0x00000000},
2570 + {0x00008254, 0x00000000},
2571 + {0x00008258, 0x00000000},
2572 + {0x0000825c, 0x400000ff},
2573 + {0x00008260, 0x00080922},
2574 + {0x00008270, 0x00000000},
2575 + {0x00008274, 0x40000000},
2576 + {0x00008278, 0x003e4180},
2577 + {0x0000827c, 0x00000000},
2578 + {0x00008284, 0x0000002c},
2579 + {0x00008288, 0x0000002c},
2580 + {0x0000828c, 0x00000000},
2581 + {0x00008294, 0x00000000},
2582 + {0x00008298, 0x00000000},
2583 + {0x00008300, 0x00000000},
2584 + {0x00008304, 0x00000000},
2585 + {0x00008308, 0x00000000},
2586 + {0x0000830c, 0x00000000},
2587 + {0x00008310, 0x00000000},
2588 + {0x00008314, 0x00000000},
2589 + {0x00008318, 0x00000000},
2590 + {0x00008328, 0x00000000},
2591 + {0x0000832c, 0x00000007},
2592 + {0x00008330, 0x00000302},
2593 + {0x00008334, 0x00000e00},
2594 + {0x00008338, 0x00000000},
2595 + {0x0000833c, 0x00000000},
2596 + {0x00008340, 0x000107ff},
2597 + {0x00009808, 0x00000000},
2598 + {0x0000980c, 0xad848e19},
2599 + {0x00009810, 0x7d14e000},
2600 + {0x00009814, 0x9c0a9f6b},
2601 + {0x0000981c, 0x00000000},
2602 + {0x0000982c, 0x0000a000},
2603 + {0x00009830, 0x00000000},
2604 + {0x0000983c, 0x00200400},
2605 + {0x00009840, 0x206a01ae},
2606 + {0x0000984c, 0x1284233c},
2607 + {0x00009854, 0x00000859},
2608 + {0x00009900, 0x00000000},
2609 + {0x00009904, 0x00000000},
2610 + {0x00009908, 0x00000000},
2611 + {0x0000990c, 0x00000000},
2612 + {0x0000991c, 0x10000fff},
2613 + {0x00009920, 0x05100000},
2614 + {0x0000a920, 0x05100000},
2615 + {0x0000b920, 0x05100000},
2616 + {0x00009928, 0x00000001},
2617 + {0x0000992c, 0x00000004},
2618 + {0x00009934, 0x1e1f2022},
2619 + {0x00009938, 0x0a0b0c0d},
2620 + {0x0000993c, 0x00000000},
2621 + {0x00009948, 0x9280b212},
2622 + {0x0000994c, 0x00020028},
2623 + {0x0000c95c, 0x004b6a8e},
2624 + {0x0000c968, 0x000003ce},
2625 + {0x00009970, 0x190fb515},
2626 + {0x00009974, 0x00000000},
2627 + {0x00009978, 0x00000001},
2628 + {0x0000997c, 0x00000000},
2629 + {0x00009980, 0x00000000},
2630 + {0x00009984, 0x00000000},
2631 + {0x00009988, 0x00000000},
2632 + {0x0000998c, 0x00000000},
2633 + {0x00009990, 0x00000000},
2634 + {0x00009994, 0x00000000},
2635 + {0x00009998, 0x00000000},
2636 + {0x0000999c, 0x00000000},
2637 + {0x000099a0, 0x00000000},
2638 + {0x000099a4, 0x00000001},
2639 + {0x000099a8, 0x201fff00},
2640 + {0x000099ac, 0x006f0000},
2641 + {0x000099b0, 0x03051000},
2642 + {0x000099dc, 0x00000000},
2643 + {0x000099e0, 0x00000200},
2644 + {0x000099e4, 0xaaaaaaaa},
2645 + {0x000099e8, 0x3c466478},
2646 + {0x000099ec, 0x0cc80caa},
2647 + {0x000099fc, 0x00001042},
2648 + {0x00009b00, 0x00000000},
2649 + {0x00009b04, 0x00000001},
2650 + {0x00009b08, 0x00000002},
2651 + {0x00009b0c, 0x00000003},
2652 + {0x00009b10, 0x00000004},
2653 + {0x00009b14, 0x00000005},
2654 + {0x00009b18, 0x00000008},
2655 + {0x00009b1c, 0x00000009},
2656 + {0x00009b20, 0x0000000a},
2657 + {0x00009b24, 0x0000000b},
2658 + {0x00009b28, 0x0000000c},
2659 + {0x00009b2c, 0x0000000d},
2660 + {0x00009b30, 0x00000010},
2661 + {0x00009b34, 0x00000011},
2662 + {0x00009b38, 0x00000012},
2663 + {0x00009b3c, 0x00000013},
2664 + {0x00009b40, 0x00000014},
2665 + {0x00009b44, 0x00000015},
2666 + {0x00009b48, 0x00000018},
2667 + {0x00009b4c, 0x00000019},
2668 + {0x00009b50, 0x0000001a},
2669 + {0x00009b54, 0x0000001b},
2670 + {0x00009b58, 0x0000001c},
2671 + {0x00009b5c, 0x0000001d},
2672 + {0x00009b60, 0x00000020},
2673 + {0x00009b64, 0x00000021},
2674 + {0x00009b68, 0x00000022},
2675 + {0x00009b6c, 0x00000023},
2676 + {0x00009b70, 0x00000024},
2677 + {0x00009b74, 0x00000025},
2678 + {0x00009b78, 0x00000028},
2679 + {0x00009b7c, 0x00000029},
2680 + {0x00009b80, 0x0000002a},
2681 + {0x00009b84, 0x0000002b},
2682 + {0x00009b88, 0x0000002c},
2683 + {0x00009b8c, 0x0000002d},
2684 + {0x00009b90, 0x00000030},
2685 + {0x00009b94, 0x00000031},
2686 + {0x00009b98, 0x00000032},
2687 + {0x00009b9c, 0x00000033},
2688 + {0x00009ba0, 0x00000034},
2689 + {0x00009ba4, 0x00000035},
2690 + {0x00009ba8, 0x00000035},
2691 + {0x00009bac, 0x00000035},
2692 + {0x00009bb0, 0x00000035},
2693 + {0x00009bb4, 0x00000035},
2694 + {0x00009bb8, 0x00000035},
2695 + {0x00009bbc, 0x00000035},
2696 + {0x00009bc0, 0x00000035},
2697 + {0x00009bc4, 0x00000035},
2698 + {0x00009bc8, 0x00000035},
2699 + {0x00009bcc, 0x00000035},
2700 + {0x00009bd0, 0x00000035},
2701 + {0x00009bd4, 0x00000035},
2702 + {0x00009bd8, 0x00000035},
2703 + {0x00009bdc, 0x00000035},
2704 + {0x00009be0, 0x00000035},
2705 + {0x00009be4, 0x00000035},
2706 + {0x00009be8, 0x00000035},
2707 + {0x00009bec, 0x00000035},
2708 + {0x00009bf0, 0x00000035},
2709 + {0x00009bf4, 0x00000035},
2710 + {0x00009bf8, 0x00000010},
2711 + {0x00009bfc, 0x0000001a},
2712 + {0x0000a210, 0x40806333},
2713 + {0x0000a214, 0x00106c10},
2714 + {0x0000a218, 0x009c4060},
2715 + {0x0000a220, 0x018830c6},
2716 + {0x0000a224, 0x00000400},
2717 + {0x0000a228, 0x001a0bb5},
2718 + {0x0000a22c, 0x00000000},
2719 + {0x0000a234, 0x20202020},
2720 + {0x0000a238, 0x20202020},
2721 + {0x0000a23c, 0x13c889ae},
2722 + {0x0000a240, 0x38490a20},
2723 + {0x0000a244, 0x00007bb6},
2724 + {0x0000a248, 0x0fff3ffc},
2725 + {0x0000a24c, 0x00000001},
2726 + {0x0000a250, 0x0000a000},
2727 + {0x0000a254, 0x00000000},
2728 + {0x0000a258, 0x0cc75380},
2729 + {0x0000a25c, 0x0f0f0f01},
2730 + {0x0000a260, 0xdfa91f01},
2731 + {0x0000a268, 0x00000001},
2732 + {0x0000a26c, 0x0ebae9c6},
2733 + {0x0000b26c, 0x0ebae9c6},
2734 + {0x0000c26c, 0x0ebae9c6},
2735 + {0x0000d270, 0x00820820},
2736 + {0x0000a278, 0x1ce739ce},
2737 + {0x0000a27c, 0x050701ce},
2738 + {0x0000a338, 0x00000000},
2739 + {0x0000a33c, 0x00000000},
2740 + {0x0000a340, 0x00000000},
2741 + {0x0000a344, 0x00000000},
2742 + {0x0000a348, 0x3fffffff},
2743 + {0x0000a34c, 0x3fffffff},
2744 + {0x0000a350, 0x3fffffff},
2745 + {0x0000a354, 0x0003ffff},
2746 + {0x0000a358, 0x79a8aa33},
2747 + {0x0000d35c, 0x07ffffef},
2748 + {0x0000d360, 0x0fffffe7},
2749 + {0x0000d364, 0x17ffffe5},
2750 + {0x0000d368, 0x1fffffe4},
2751 + {0x0000d36c, 0x37ffffe3},
2752 + {0x0000d370, 0x3fffffe3},
2753 + {0x0000d374, 0x57ffffe3},
2754 + {0x0000d378, 0x5fffffe2},
2755 + {0x0000d37c, 0x7fffffe2},
2756 + {0x0000d380, 0x7f3c7bba},
2757 + {0x0000d384, 0xf3307ff0},
2758 + {0x0000a388, 0x0c000000},
2759 + {0x0000a38c, 0x20202020},
2760 + {0x0000a390, 0x20202020},
2761 + {0x0000a394, 0x1ce739ce},
2762 + {0x0000a398, 0x000001ce},
2763 + {0x0000a39c, 0x00000001},
2764 + {0x0000a3a0, 0x00000000},
2765 + {0x0000a3a4, 0x00000000},
2766 + {0x0000a3a8, 0x00000000},
2767 + {0x0000a3ac, 0x00000000},
2768 + {0x0000a3b0, 0x00000000},
2769 + {0x0000a3b4, 0x00000000},
2770 + {0x0000a3b8, 0x00000000},
2771 + {0x0000a3bc, 0x00000000},
2772 + {0x0000a3c0, 0x00000000},
2773 + {0x0000a3c4, 0x00000000},
2774 + {0x0000a3c8, 0x00000246},
2775 + {0x0000a3cc, 0x20202020},
2776 + {0x0000a3d0, 0x20202020},
2777 + {0x0000a3d4, 0x20202020},
2778 + {0x0000a3dc, 0x1ce739ce},
2779 + {0x0000a3e0, 0x000001ce},
2780 +};
2781 +
2782 +static const u32 ar5416Bank0_9100[][2] = {
2783 + {0x000098b0, 0x1e5795e5},
2784 + {0x000098e0, 0x02008020},
2785 +};
2786 +
2787 +static const u32 ar5416BB_RfGain_9100[][3] = {
2788 + {0x00009a00, 0x00000000, 0x00000000},
2789 + {0x00009a04, 0x00000040, 0x00000040},
2790 + {0x00009a08, 0x00000080, 0x00000080},
2791 + {0x00009a0c, 0x000001a1, 0x00000141},
2792 + {0x00009a10, 0x000001e1, 0x00000181},
2793 + {0x00009a14, 0x00000021, 0x000001c1},
2794 + {0x00009a18, 0x00000061, 0x00000001},
2795 + {0x00009a1c, 0x00000168, 0x00000041},
2796 + {0x00009a20, 0x000001a8, 0x000001a8},
2797 + {0x00009a24, 0x000001e8, 0x000001e8},
2798 + {0x00009a28, 0x00000028, 0x00000028},
2799 + {0x00009a2c, 0x00000068, 0x00000068},
2800 + {0x00009a30, 0x00000189, 0x000000a8},
2801 + {0x00009a34, 0x000001c9, 0x00000169},
2802 + {0x00009a38, 0x00000009, 0x000001a9},
2803 + {0x00009a3c, 0x00000049, 0x000001e9},
2804 + {0x00009a40, 0x00000089, 0x00000029},
2805 + {0x00009a44, 0x00000170, 0x00000069},
2806 + {0x00009a48, 0x000001b0, 0x00000190},
2807 + {0x00009a4c, 0x000001f0, 0x000001d0},
2808 + {0x00009a50, 0x00000030, 0x00000010},
2809 + {0x00009a54, 0x00000070, 0x00000050},
2810 + {0x00009a58, 0x00000191, 0x00000090},
2811 + {0x00009a5c, 0x000001d1, 0x00000151},
2812 + {0x00009a60, 0x00000011, 0x00000191},
2813 + {0x00009a64, 0x00000051, 0x000001d1},
2814 + {0x00009a68, 0x00000091, 0x00000011},
2815 + {0x00009a6c, 0x000001b8, 0x00000051},
2816 + {0x00009a70, 0x000001f8, 0x00000198},
2817 + {0x00009a74, 0x00000038, 0x000001d8},
2818 + {0x00009a78, 0x00000078, 0x00000018},
2819 + {0x00009a7c, 0x00000199, 0x00000058},
2820 + {0x00009a80, 0x000001d9, 0x00000098},
2821 + {0x00009a84, 0x00000019, 0x00000159},
2822 + {0x00009a88, 0x00000059, 0x00000199},
2823 + {0x00009a8c, 0x00000099, 0x000001d9},
2824 + {0x00009a90, 0x000000d9, 0x00000019},
2825 + {0x00009a94, 0x000000f9, 0x00000059},
2826 + {0x00009a98, 0x000000f9, 0x00000099},
2827 + {0x00009a9c, 0x000000f9, 0x000000d9},
2828 + {0x00009aa0, 0x000000f9, 0x000000f9},
2829 + {0x00009aa4, 0x000000f9, 0x000000f9},
2830 + {0x00009aa8, 0x000000f9, 0x000000f9},
2831 + {0x00009aac, 0x000000f9, 0x000000f9},
2832 + {0x00009ab0, 0x000000f9, 0x000000f9},
2833 + {0x00009ab4, 0x000000f9, 0x000000f9},
2834 + {0x00009ab8, 0x000000f9, 0x000000f9},
2835 + {0x00009abc, 0x000000f9, 0x000000f9},
2836 + {0x00009ac0, 0x000000f9, 0x000000f9},
2837 + {0x00009ac4, 0x000000f9, 0x000000f9},
2838 + {0x00009ac8, 0x000000f9, 0x000000f9},
2839 + {0x00009acc, 0x000000f9, 0x000000f9},
2840 + {0x00009ad0, 0x000000f9, 0x000000f9},
2841 + {0x00009ad4, 0x000000f9, 0x000000f9},
2842 + {0x00009ad8, 0x000000f9, 0x000000f9},
2843 + {0x00009adc, 0x000000f9, 0x000000f9},
2844 + {0x00009ae0, 0x000000f9, 0x000000f9},
2845 + {0x00009ae4, 0x000000f9, 0x000000f9},
2846 + {0x00009ae8, 0x000000f9, 0x000000f9},
2847 + {0x00009aec, 0x000000f9, 0x000000f9},
2848 + {0x00009af0, 0x000000f9, 0x000000f9},
2849 + {0x00009af4, 0x000000f9, 0x000000f9},
2850 + {0x00009af8, 0x000000f9, 0x000000f9},
2851 + {0x00009afc, 0x000000f9, 0x000000f9},
2852 +};
2853 +
2854 +static const u32 ar5416Bank1_9100[][2] = {
2855 + {0x000098b0, 0x02108421},
2856 + {0x000098ec, 0x00000008},
2857 +};
2858 +
2859 +static const u32 ar5416Bank2_9100[][2] = {
2860 + {0x000098b0, 0x0e73ff17},
2861 + {0x000098e0, 0x00000420},
2862 +};
2863 +
2864 +static const u32 ar5416Bank3_9100[][3] = {
2865 + {0x000098f0, 0x01400018, 0x01c00018},
2866 +};
2867 +
2868 +static const u32 ar5416Bank6_9100[][3] = {
2869 +
2870 + {0x0000989c, 0x00000000, 0x00000000},
2871 + {0x0000989c, 0x00000000, 0x00000000},
2872 + {0x0000989c, 0x00000000, 0x00000000},
2873 + {0x0000989c, 0x00e00000, 0x00e00000},
2874 + {0x0000989c, 0x005e0000, 0x005e0000},
2875 + {0x0000989c, 0x00120000, 0x00120000},
2876 + {0x0000989c, 0x00620000, 0x00620000},
2877 + {0x0000989c, 0x00020000, 0x00020000},
2878 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2879 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2880 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2881 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2882 + {0x0000989c, 0x005f0000, 0x005f0000},
2883 + {0x0000989c, 0x00870000, 0x00870000},
2884 + {0x0000989c, 0x00f90000, 0x00f90000},
2885 + {0x0000989c, 0x007b0000, 0x007b0000},
2886 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2887 + {0x0000989c, 0x00f50000, 0x00f50000},
2888 + {0x0000989c, 0x00dc0000, 0x00dc0000},
2889 + {0x0000989c, 0x00110000, 0x00110000},
2890 + {0x0000989c, 0x006100a8, 0x006100a8},
2891 + {0x0000989c, 0x004210a2, 0x004210a2},
2892 + {0x0000989c, 0x0014000f, 0x0014000f},
2893 + {0x0000989c, 0x00c40002, 0x00c40002},
2894 + {0x0000989c, 0x003000f2, 0x003000f2},
2895 + {0x0000989c, 0x00440016, 0x00440016},
2896 + {0x0000989c, 0x00410040, 0x00410040},
2897 + {0x0000989c, 0x000180d6, 0x000180d6},
2898 + {0x0000989c, 0x0000c0aa, 0x0000c0aa},
2899 + {0x0000989c, 0x000000b1, 0x000000b1},
2900 + {0x0000989c, 0x00002000, 0x00002000},
2901 + {0x0000989c, 0x000000d4, 0x000000d4},
2902 + {0x000098d0, 0x0000000f, 0x0010000f},
2903 +};
2904 +
2905 +static const u32 ar5416Bank6TPC_9100[][3] = {
2906 +
2907 + {0x0000989c, 0x00000000, 0x00000000},
2908 + {0x0000989c, 0x00000000, 0x00000000},
2909 + {0x0000989c, 0x00000000, 0x00000000},
2910 + {0x0000989c, 0x00e00000, 0x00e00000},
2911 + {0x0000989c, 0x005e0000, 0x005e0000},
2912 + {0x0000989c, 0x00120000, 0x00120000},
2913 + {0x0000989c, 0x00620000, 0x00620000},
2914 + {0x0000989c, 0x00020000, 0x00020000},
2915 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2916 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2917 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2918 + {0x0000989c, 0x40ff0000, 0x40ff0000},
2919 + {0x0000989c, 0x005f0000, 0x005f0000},
2920 + {0x0000989c, 0x00870000, 0x00870000},
2921 + {0x0000989c, 0x00f90000, 0x00f90000},
2922 + {0x0000989c, 0x007b0000, 0x007b0000},
2923 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2924 + {0x0000989c, 0x00f50000, 0x00f50000},
2925 + {0x0000989c, 0x00dc0000, 0x00dc0000},
2926 + {0x0000989c, 0x00110000, 0x00110000},
2927 + {0x0000989c, 0x006100a8, 0x006100a8},
2928 + {0x0000989c, 0x00423022, 0x00423022},
2929 + {0x0000989c, 0x2014008f, 0x2014008f},
2930 + {0x0000989c, 0x00c40002, 0x00c40002},
2931 + {0x0000989c, 0x003000f2, 0x003000f2},
2932 + {0x0000989c, 0x00440016, 0x00440016},
2933 + {0x0000989c, 0x00410040, 0x00410040},
2934 + {0x0000989c, 0x0001805e, 0x0001805e},
2935 + {0x0000989c, 0x0000c0ab, 0x0000c0ab},
2936 + {0x0000989c, 0x000000e1, 0x000000e1},
2937 + {0x0000989c, 0x00007080, 0x00007080},
2938 + {0x0000989c, 0x000000d4, 0x000000d4},
2939 + {0x000098d0, 0x0000000f, 0x0010000f},
2940 +};
2941 +
2942 +static const u32 ar5416Bank7_9100[][2] = {
2943 + {0x0000989c, 0x00000500},
2944 + {0x0000989c, 0x00000800},
2945 + {0x000098cc, 0x0000000e},
2946 +};
2947 +
2948 +static const u32 ar5416Addac_9100[][2] = {
2949 + {0x0000989c, 0x00000000},
2950 + {0x0000989c, 0x00000000},
2951 + {0x0000989c, 0x00000000},
2952 + {0x0000989c, 0x00000000},
2953 + {0x0000989c, 0x00000000},
2954 + {0x0000989c, 0x00000000},
2955 + {0x0000989c, 0x00000000},
2956 + {0x0000989c, 0x00000010},
2957 + {0x0000989c, 0x00000000},
2958 + {0x0000989c, 0x00000000},
2959 + {0x0000989c, 0x00000000},
2960 + {0x0000989c, 0x00000000},
2961 + {0x0000989c, 0x00000000},
2962 + {0x0000989c, 0x00000000},
2963 + {0x0000989c, 0x00000000},
2964 + {0x0000989c, 0x00000000},
2965 + {0x0000989c, 0x00000000},
2966 + {0x0000989c, 0x00000000},
2967 + {0x0000989c, 0x00000000},
2968 + {0x0000989c, 0x00000000},
2969 + {0x0000989c, 0x00000000},
2970 + {0x0000989c, 0x000000c0},
2971 + {0x0000989c, 0x00000015},
2972 + {0x0000989c, 0x00000000},
2973 + {0x0000989c, 0x00000000},
2974 + {0x0000989c, 0x00000000},
2975 + {0x0000989c, 0x00000000},
2976 + {0x0000989c, 0x00000000},
2977 + {0x0000989c, 0x00000000},
2978 + {0x0000989c, 0x00000000},
2979 + {0x0000989c, 0x00000000},
2980 + {0x000098cc, 0x00000000},
2981 +};
2982 +
2983 +static const u32 ar5416Modes_9160[][6] = {
2984 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
2985 + 0x000001e0},
2986 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
2987 + 0x000001e0},
2988 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
2989 + 0x00001180},
2990 + {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000,
2991 + 0x00014008},
2992 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00,
2993 + 0x06e006e0},
2994 + {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab,
2995 + 0x098813cf},
2996 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
2997 + 0x00000303},
2998 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
2999 + 0x02020200},
3000 + {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
3001 + 0x00000e0e},
3002 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
3003 + 0x0a020001},
3004 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
3005 + 0x00000e0e},
3006 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
3007 + 0x00000007},
3008 + {0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0,
3009 + 0x037216a0},
3010 + {0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
3011 + 0x00197a68},
3012 + {0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
3013 + 0x00197a68},
3014 + {0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
3015 + 0x00197a68},
3016 + {0x00009850, 0x6c48b4e2, 0x6c48b4e2, 0x6c48b0e2, 0x6c48b0e2,
3017 + 0x6c48b0e2},
3018 + {0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e,
3019 + 0x7ec82d2e},
3020 + {0x0000985c, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e,
3021 + 0x31395d5e},
3022 + {0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20,
3023 + 0x00048d18},
3024 + {0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00,
3025 + 0x0001ce00},
3026 + {0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0,
3027 + 0x409a40d0},
3028 + {0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081,
3029 + 0x050cb081},
3030 + {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898,
3031 + 0x000007d0},
3032 + {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b,
3033 + 0x00000016},
3034 + {0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d,
3035 + 0xd00a8a0d},
3036 + {0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020,
3037 + 0xffb81020},
3038 + {0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40,
3039 + 0x00009b40},
3040 + {0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40,
3041 + 0x00009b40},
3042 + {0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40,
3043 + 0x00009b40},
3044 + {0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120,
3045 + 0x00001120},
3046 + {0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce,
3047 + 0x000003ce},
3048 + {0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00,
3049 + 0x001a0c00},
3050 + {0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be,
3051 + 0x038919be},
3052 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
3053 + 0x06336f77},
3054 + {0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329,
3055 + 0x60f65329},
3056 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
3057 + 0x08f186c8},
3058 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
3059 + 0x00046384},
3060 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3061 + 0x00000000},
3062 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3063 + 0x00000000},
3064 + {0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880,
3065 + 0x00000880},
3066 + {0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788,
3067 + 0xd03e4788},
3068 + {0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120,
3069 + 0x002ac120},
3070 + {0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120,
3071 + 0x002ac120},
3072 + {0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120,
3073 + 0x002ac120},
3074 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
3075 + 0x1883800a},
3076 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
3077 + 0x00000000},
3078 + {0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa,
3079 + 0x0a1a7caa},
3080 + {0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000,
3081 + 0x18010000},
3082 + {0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402,
3083 + 0x2e032402},
3084 + {0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06,
3085 + 0x4a0a3c06},
3086 + {0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b,
3087 + 0x621a540b},
3088 + {0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b,
3089 + 0x764f6c1b},
3090 + {0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a,
3091 + 0x845b7a5a},
3092 + {0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf,
3093 + 0x950f8ccf},
3094 + {0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f,
3095 + 0xa5cf9b4f},
3096 + {0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f,
3097 + 0xbddfaf1f},
3098 + {0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f,
3099 + 0xd1ffc93f},
3100 + {0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000,
3101 + 0x00000000},
3102 + {0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3103 + 0x00000000},
3104 + {0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3105 + 0x00000000},
3106 + {0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3107 + 0x00000000},
3108 +};
3109 +
3110 +static const u32 ar5416Common_9160[][2] = {
3111 + {0x0000000c, 0x00000000},
3112 + {0x00000030, 0x00020015},
3113 + {0x00000034, 0x00000005},
3114 + {0x00000040, 0x00000000},
3115 + {0x00000044, 0x00000008},
3116 + {0x00000048, 0x00000008},
3117 + {0x0000004c, 0x00000010},
3118 + {0x00000050, 0x00000000},
3119 + {0x00000054, 0x0000001f},
3120 + {0x00000800, 0x00000000},
3121 + {0x00000804, 0x00000000},
3122 + {0x00000808, 0x00000000},
3123 + {0x0000080c, 0x00000000},
3124 + {0x00000810, 0x00000000},
3125 + {0x00000814, 0x00000000},
3126 + {0x00000818, 0x00000000},
3127 + {0x0000081c, 0x00000000},
3128 + {0x00000820, 0x00000000},
3129 + {0x00000824, 0x00000000},
3130 + {0x00001040, 0x002ffc0f},
3131 + {0x00001044, 0x002ffc0f},
3132 + {0x00001048, 0x002ffc0f},
3133 + {0x0000104c, 0x002ffc0f},
3134 + {0x00001050, 0x002ffc0f},
3135 + {0x00001054, 0x002ffc0f},
3136 + {0x00001058, 0x002ffc0f},
3137 + {0x0000105c, 0x002ffc0f},
3138 + {0x00001060, 0x002ffc0f},
3139 + {0x00001064, 0x002ffc0f},
3140 + {0x00001230, 0x00000000},
3141 + {0x00001270, 0x00000000},
3142 + {0x00001038, 0x00000000},
3143 + {0x00001078, 0x00000000},
3144 + {0x000010b8, 0x00000000},
3145 + {0x000010f8, 0x00000000},
3146 + {0x00001138, 0x00000000},
3147 + {0x00001178, 0x00000000},
3148 + {0x000011b8, 0x00000000},
3149 + {0x000011f8, 0x00000000},
3150 + {0x00001238, 0x00000000},
3151 + {0x00001278, 0x00000000},
3152 + {0x000012b8, 0x00000000},
3153 + {0x000012f8, 0x00000000},
3154 + {0x00001338, 0x00000000},
3155 + {0x00001378, 0x00000000},
3156 + {0x000013b8, 0x00000000},
3157 + {0x000013f8, 0x00000000},
3158 + {0x00001438, 0x00000000},
3159 + {0x00001478, 0x00000000},
3160 + {0x000014b8, 0x00000000},
3161 + {0x000014f8, 0x00000000},
3162 + {0x00001538, 0x00000000},
3163 + {0x00001578, 0x00000000},
3164 + {0x000015b8, 0x00000000},
3165 + {0x000015f8, 0x00000000},
3166 + {0x00001638, 0x00000000},
3167 + {0x00001678, 0x00000000},
3168 + {0x000016b8, 0x00000000},
3169 + {0x000016f8, 0x00000000},
3170 + {0x00001738, 0x00000000},
3171 + {0x00001778, 0x00000000},
3172 + {0x000017b8, 0x00000000},
3173 + {0x000017f8, 0x00000000},
3174 + {0x0000103c, 0x00000000},
3175 + {0x0000107c, 0x00000000},
3176 + {0x000010bc, 0x00000000},
3177 + {0x000010fc, 0x00000000},
3178 + {0x0000113c, 0x00000000},
3179 + {0x0000117c, 0x00000000},
3180 + {0x000011bc, 0x00000000},
3181 + {0x000011fc, 0x00000000},
3182 + {0x0000123c, 0x00000000},
3183 + {0x0000127c, 0x00000000},
3184 + {0x000012bc, 0x00000000},
3185 + {0x000012fc, 0x00000000},
3186 + {0x0000133c, 0x00000000},
3187 + {0x0000137c, 0x00000000},
3188 + {0x000013bc, 0x00000000},
3189 + {0x000013fc, 0x00000000},
3190 + {0x0000143c, 0x00000000},
3191 + {0x0000147c, 0x00000000},
3192 + {0x00004030, 0x00000002},
3193 + {0x0000403c, 0x00000002},
3194 + {0x00007010, 0x00000020},
3195 + {0x00007038, 0x000004c2},
3196 + {0x00008004, 0x00000000},
3197 + {0x00008008, 0x00000000},
3198 + {0x0000800c, 0x00000000},
3199 + {0x00008018, 0x00000700},
3200 + {0x00008020, 0x00000000},
3201 + {0x00008038, 0x00000000},
3202 + {0x0000803c, 0x00000000},
3203 + {0x00008048, 0x40000000},
3204 + {0x00008054, 0x00000000},
3205 + {0x00008058, 0x00000000},
3206 + {0x0000805c, 0x000fc78f},
3207 + {0x00008060, 0x0000000f},
3208 + {0x00008064, 0x00000000},
3209 + {0x000080c0, 0x2a82301a},
3210 + {0x000080c4, 0x05dc01e0},
3211 + {0x000080c8, 0x1f402710},
3212 + {0x000080cc, 0x01f40000},
3213 + {0x000080d0, 0x00001e00},
3214 + {0x000080d4, 0x00000000},
3215 + {0x000080d8, 0x00400000},
3216 + {0x000080e0, 0xffffffff},
3217 + {0x000080e4, 0x0000ffff},
3218 + {0x000080e8, 0x003f3f3f},
3219 + {0x000080ec, 0x00000000},
3220 + {0x000080f0, 0x00000000},
3221 + {0x000080f4, 0x00000000},
3222 + {0x000080f8, 0x00000000},
3223 + {0x000080fc, 0x00020000},
3224 + {0x00008100, 0x00020000},
3225 + {0x00008104, 0x00000001},
3226 + {0x00008108, 0x00000052},
3227 + {0x0000810c, 0x00000000},
3228 + {0x00008110, 0x00000168},
3229 + {0x00008118, 0x000100aa},
3230 + {0x0000811c, 0x00003210},
3231 + {0x00008120, 0x08f04800},
3232 + {0x00008124, 0x00000000},
3233 + {0x00008128, 0x00000000},
3234 + {0x0000812c, 0x00000000},
3235 + {0x00008130, 0x00000000},
3236 + {0x00008134, 0x00000000},
3237 + {0x00008138, 0x00000000},
3238 + {0x0000813c, 0x00000000},
3239 + {0x00008144, 0xffffffff},
3240 + {0x00008168, 0x00000000},
3241 + {0x0000816c, 0x00000000},
3242 + {0x00008170, 0x32143320},
3243 + {0x00008174, 0xfaa4fa50},
3244 + {0x00008178, 0x00000100},
3245 + {0x0000817c, 0x00000000},
3246 + {0x000081c4, 0x00000000},
3247 + {0x000081d0, 0x00003210},
3248 + {0x000081ec, 0x00000000},
3249 + {0x000081f0, 0x00000000},
3250 + {0x000081f4, 0x00000000},
3251 + {0x000081f8, 0x00000000},
3252 + {0x000081fc, 0x00000000},
3253 + {0x00008200, 0x00000000},
3254 + {0x00008204, 0x00000000},
3255 + {0x00008208, 0x00000000},
3256 + {0x0000820c, 0x00000000},
3257 + {0x00008210, 0x00000000},
3258 + {0x00008214, 0x00000000},
3259 + {0x00008218, 0x00000000},
3260 + {0x0000821c, 0x00000000},
3261 + {0x00008220, 0x00000000},
3262 + {0x00008224, 0x00000000},
3263 + {0x00008228, 0x00000000},
3264 + {0x0000822c, 0x00000000},
3265 + {0x00008230, 0x00000000},
3266 + {0x00008234, 0x00000000},
3267 + {0x00008238, 0x00000000},
3268 + {0x0000823c, 0x00000000},
3269 + {0x00008240, 0x00100000},
3270 + {0x00008244, 0x0010f400},
3271 + {0x00008248, 0x00000100},
3272 + {0x0000824c, 0x0001e800},
3273 + {0x00008250, 0x00000000},
3274 + {0x00008254, 0x00000000},
3275 + {0x00008258, 0x00000000},
3276 + {0x0000825c, 0x400000ff},
3277 + {0x00008260, 0x00080922},
3278 + {0x00008270, 0x00000000},
3279 + {0x00008274, 0x40000000},
3280 + {0x00008278, 0x003e4180},
3281 + {0x0000827c, 0x00000000},
3282 + {0x00008284, 0x0000002c},
3283 + {0x00008288, 0x0000002c},
3284 + {0x0000828c, 0x00000000},
3285 + {0x00008294, 0x00000000},
3286 + {0x00008298, 0x00000000},
3287 + {0x00008300, 0x00000000},
3288 + {0x00008304, 0x00000000},
3289 + {0x00008308, 0x00000000},
3290 + {0x0000830c, 0x00000000},
3291 + {0x00008310, 0x00000000},
3292 + {0x00008314, 0x00000000},
3293 + {0x00008318, 0x00000000},
3294 + {0x00008328, 0x00000000},
3295 + {0x0000832c, 0x00000007},
3296 + {0x00008330, 0x00000302},
3297 + {0x00008334, 0x00000e00},
3298 + {0x00008338, 0x00ff0000},
3299 + {0x0000833c, 0x00000000},
3300 + {0x00008340, 0x000107ff},
3301 + {0x00009808, 0x00000000},
3302 + {0x0000980c, 0xad848e19},
3303 + {0x00009810, 0x7d14e000},
3304 + {0x00009814, 0x9c0a9f6b},
3305 + {0x0000981c, 0x00000000},
3306 + {0x0000982c, 0x0000a000},
3307 + {0x00009830, 0x00000000},
3308 + {0x0000983c, 0x00200400},
3309 + {0x00009840, 0x206a01ae},
3310 + {0x0000984c, 0x1284233c},
3311 + {0x00009854, 0x00000859},
3312 + {0x00009900, 0x00000000},
3313 + {0x00009904, 0x00000000},
3314 + {0x00009908, 0x00000000},
3315 + {0x0000990c, 0x00000000},
3316 + {0x0000991c, 0x10000fff},
3317 + {0x00009920, 0x05100000},
3318 + {0x0000a920, 0x05100000},
3319 + {0x0000b920, 0x05100000},
3320 + {0x00009928, 0x00000001},
3321 + {0x0000992c, 0x00000004},
3322 + {0x00009934, 0x1e1f2022},
3323 + {0x00009938, 0x0a0b0c0d},
3324 + {0x0000993c, 0x00000000},
3325 + {0x00009948, 0x9280b212},
3326 + {0x0000994c, 0x00020028},
3327 + {0x00009954, 0x5f3ca3de},
3328 + {0x00009958, 0x2108ecff},
3329 + {0x00009940, 0x00750604},
3330 + {0x0000c95c, 0x004b6a8e},
3331 + {0x00009970, 0x190fb515},
3332 + {0x00009974, 0x00000000},
3333 + {0x00009978, 0x00000001},
3334 + {0x0000997c, 0x00000000},
3335 + {0x00009980, 0x00000000},
3336 + {0x00009984, 0x00000000},
3337 + {0x00009988, 0x00000000},
3338 + {0x0000998c, 0x00000000},
3339 + {0x00009990, 0x00000000},
3340 + {0x00009994, 0x00000000},
3341 + {0x00009998, 0x00000000},
3342 + {0x0000999c, 0x00000000},
3343 + {0x000099a0, 0x00000000},
3344 + {0x000099a4, 0x00000001},
3345 + {0x000099a8, 0x201fff00},
3346 + {0x000099ac, 0x006f0000},
3347 + {0x000099b0, 0x03051000},
3348 + {0x000099dc, 0x00000000},
3349 + {0x000099e0, 0x00000200},
3350 + {0x000099e4, 0xaaaaaaaa},
3351 + {0x000099e8, 0x3c466478},
3352 + {0x000099ec, 0x0cc80caa},
3353 + {0x000099fc, 0x00001042},
3354 + {0x00009b00, 0x00000000},
3355 + {0x00009b04, 0x00000001},
3356 + {0x00009b08, 0x00000002},
3357 + {0x00009b0c, 0x00000003},
3358 + {0x00009b10, 0x00000004},
3359 + {0x00009b14, 0x00000005},
3360 + {0x00009b18, 0x00000008},
3361 + {0x00009b1c, 0x00000009},
3362 + {0x00009b20, 0x0000000a},
3363 + {0x00009b24, 0x0000000b},
3364 + {0x00009b28, 0x0000000c},
3365 + {0x00009b2c, 0x0000000d},
3366 + {0x00009b30, 0x00000010},
3367 + {0x00009b34, 0x00000011},
3368 + {0x00009b38, 0x00000012},
3369 + {0x00009b3c, 0x00000013},
3370 + {0x00009b40, 0x00000014},
3371 + {0x00009b44, 0x00000015},
3372 + {0x00009b48, 0x00000018},
3373 + {0x00009b4c, 0x00000019},
3374 + {0x00009b50, 0x0000001a},
3375 + {0x00009b54, 0x0000001b},
3376 + {0x00009b58, 0x0000001c},
3377 + {0x00009b5c, 0x0000001d},
3378 + {0x00009b60, 0x00000020},
3379 + {0x00009b64, 0x00000021},
3380 + {0x00009b68, 0x00000022},
3381 + {0x00009b6c, 0x00000023},
3382 + {0x00009b70, 0x00000024},
3383 + {0x00009b74, 0x00000025},
3384 + {0x00009b78, 0x00000028},
3385 + {0x00009b7c, 0x00000029},
3386 + {0x00009b80, 0x0000002a},
3387 + {0x00009b84, 0x0000002b},
3388 + {0x00009b88, 0x0000002c},
3389 + {0x00009b8c, 0x0000002d},
3390 + {0x00009b90, 0x00000030},
3391 + {0x00009b94, 0x00000031},
3392 + {0x00009b98, 0x00000032},
3393 + {0x00009b9c, 0x00000033},
3394 + {0x00009ba0, 0x00000034},
3395 + {0x00009ba4, 0x00000035},
3396 + {0x00009ba8, 0x00000035},
3397 + {0x00009bac, 0x00000035},
3398 + {0x00009bb0, 0x00000035},
3399 + {0x00009bb4, 0x00000035},
3400 + {0x00009bb8, 0x00000035},
3401 + {0x00009bbc, 0x00000035},
3402 + {0x00009bc0, 0x00000035},
3403 + {0x00009bc4, 0x00000035},
3404 + {0x00009bc8, 0x00000035},
3405 + {0x00009bcc, 0x00000035},
3406 + {0x00009bd0, 0x00000035},
3407 + {0x00009bd4, 0x00000035},
3408 + {0x00009bd8, 0x00000035},
3409 + {0x00009bdc, 0x00000035},
3410 + {0x00009be0, 0x00000035},
3411 + {0x00009be4, 0x00000035},
3412 + {0x00009be8, 0x00000035},
3413 + {0x00009bec, 0x00000035},
3414 + {0x00009bf0, 0x00000035},
3415 + {0x00009bf4, 0x00000035},
3416 + {0x00009bf8, 0x00000010},
3417 + {0x00009bfc, 0x0000001a},
3418 + {0x0000a210, 0x40806333},
3419 + {0x0000a214, 0x00106c10},
3420 + {0x0000a218, 0x009c4060},
3421 + {0x0000a220, 0x018830c6},
3422 + {0x0000a224, 0x00000400},
3423 + {0x0000a228, 0x001a0bb5},
3424 + {0x0000a22c, 0x00000000},
3425 + {0x0000a234, 0x20202020},
3426 + {0x0000a238, 0x20202020},
3427 + {0x0000a23c, 0x13c889af},
3428 + {0x0000a240, 0x38490a20},
3429 + {0x0000a244, 0x00007bb6},
3430 + {0x0000a248, 0x0fff3ffc},
3431 + {0x0000a24c, 0x00000001},
3432 + {0x0000a250, 0x0000e000},
3433 + {0x0000a254, 0x00000000},
3434 + {0x0000a258, 0x0cc75380},
3435 + {0x0000a25c, 0x0f0f0f01},
3436 + {0x0000a260, 0xdfa91f01},
3437 + {0x0000a268, 0x00000001},
3438 + {0x0000a26c, 0x0ebae9c6},
3439 + {0x0000b26c, 0x0ebae9c6},
3440 + {0x0000c26c, 0x0ebae9c6},
3441 + {0x0000d270, 0x00820820},
3442 + {0x0000a278, 0x1ce739ce},
3443 + {0x0000a27c, 0x050701ce},
3444 + {0x0000a338, 0x00000000},
3445 + {0x0000a33c, 0x00000000},
3446 + {0x0000a340, 0x00000000},
3447 + {0x0000a344, 0x00000000},
3448 + {0x0000a348, 0x3fffffff},
3449 + {0x0000a34c, 0x3fffffff},
3450 + {0x0000a350, 0x3fffffff},
3451 + {0x0000a354, 0x0003ffff},
3452 + {0x0000a358, 0x79bfaa03},
3453 + {0x0000d35c, 0x07ffffef},
3454 + {0x0000d360, 0x0fffffe7},
3455 + {0x0000d364, 0x17ffffe5},
3456 + {0x0000d368, 0x1fffffe4},
3457 + {0x0000d36c, 0x37ffffe3},
3458 + {0x0000d370, 0x3fffffe3},
3459 + {0x0000d374, 0x57ffffe3},
3460 + {0x0000d378, 0x5fffffe2},
3461 + {0x0000d37c, 0x7fffffe2},
3462 + {0x0000d380, 0x7f3c7bba},
3463 + {0x0000d384, 0xf3307ff0},
3464 + {0x0000a388, 0x0c000000},
3465 + {0x0000a38c, 0x20202020},
3466 + {0x0000a390, 0x20202020},
3467 + {0x0000a394, 0x1ce739ce},
3468 + {0x0000a398, 0x000001ce},
3469 + {0x0000a39c, 0x00000001},
3470 + {0x0000a3a0, 0x00000000},
3471 + {0x0000a3a4, 0x00000000},
3472 + {0x0000a3a8, 0x00000000},
3473 + {0x0000a3ac, 0x00000000},
3474 + {0x0000a3b0, 0x00000000},
3475 + {0x0000a3b4, 0x00000000},
3476 + {0x0000a3b8, 0x00000000},
3477 + {0x0000a3bc, 0x00000000},
3478 + {0x0000a3c0, 0x00000000},
3479 + {0x0000a3c4, 0x00000000},
3480 + {0x0000a3c8, 0x00000246},
3481 + {0x0000a3cc, 0x20202020},
3482 + {0x0000a3d0, 0x20202020},
3483 + {0x0000a3d4, 0x20202020},
3484 + {0x0000a3dc, 0x1ce739ce},
3485 + {0x0000a3e0, 0x000001ce},
3486 +};
3487 +
3488 +static const u32 ar5416Bank0_9160[][2] = {
3489 + {0x000098b0, 0x1e5795e5},
3490 + {0x000098e0, 0x02008020},
3491 +};
3492 +
3493 +static const u32 ar5416BB_RfGain_9160[][3] = {
3494 + {0x00009a00, 0x00000000, 0x00000000},
3495 + {0x00009a04, 0x00000040, 0x00000040},
3496 + {0x00009a08, 0x00000080, 0x00000080},
3497 + {0x00009a0c, 0x000001a1, 0x00000141},
3498 + {0x00009a10, 0x000001e1, 0x00000181},
3499 + {0x00009a14, 0x00000021, 0x000001c1},
3500 + {0x00009a18, 0x00000061, 0x00000001},
3501 + {0x00009a1c, 0x00000168, 0x00000041},
3502 + {0x00009a20, 0x000001a8, 0x000001a8},
3503 + {0x00009a24, 0x000001e8, 0x000001e8},
3504 + {0x00009a28, 0x00000028, 0x00000028},
3505 + {0x00009a2c, 0x00000068, 0x00000068},
3506 + {0x00009a30, 0x00000189, 0x000000a8},
3507 + {0x00009a34, 0x000001c9, 0x00000169},
3508 + {0x00009a38, 0x00000009, 0x000001a9},
3509 + {0x00009a3c, 0x00000049, 0x000001e9},
3510 + {0x00009a40, 0x00000089, 0x00000029},
3511 + {0x00009a44, 0x00000170, 0x00000069},
3512 + {0x00009a48, 0x000001b0, 0x00000190},
3513 + {0x00009a4c, 0x000001f0, 0x000001d0},
3514 + {0x00009a50, 0x00000030, 0x00000010},
3515 + {0x00009a54, 0x00000070, 0x00000050},
3516 + {0x00009a58, 0x00000191, 0x00000090},
3517 + {0x00009a5c, 0x000001d1, 0x00000151},
3518 + {0x00009a60, 0x00000011, 0x00000191},
3519 + {0x00009a64, 0x00000051, 0x000001d1},
3520 + {0x00009a68, 0x00000091, 0x00000011},
3521 + {0x00009a6c, 0x000001b8, 0x00000051},
3522 + {0x00009a70, 0x000001f8, 0x00000198},
3523 + {0x00009a74, 0x00000038, 0x000001d8},
3524 + {0x00009a78, 0x00000078, 0x00000018},
3525 + {0x00009a7c, 0x00000199, 0x00000058},
3526 + {0x00009a80, 0x000001d9, 0x00000098},
3527 + {0x00009a84, 0x00000019, 0x00000159},
3528 + {0x00009a88, 0x00000059, 0x00000199},
3529 + {0x00009a8c, 0x00000099, 0x000001d9},
3530 + {0x00009a90, 0x000000d9, 0x00000019},
3531 + {0x00009a94, 0x000000f9, 0x00000059},
3532 + {0x00009a98, 0x000000f9, 0x00000099},
3533 + {0x00009a9c, 0x000000f9, 0x000000d9},
3534 + {0x00009aa0, 0x000000f9, 0x000000f9},
3535 + {0x00009aa4, 0x000000f9, 0x000000f9},
3536 + {0x00009aa8, 0x000000f9, 0x000000f9},
3537 + {0x00009aac, 0x000000f9, 0x000000f9},
3538 + {0x00009ab0, 0x000000f9, 0x000000f9},
3539 + {0x00009ab4, 0x000000f9, 0x000000f9},
3540 + {0x00009ab8, 0x000000f9, 0x000000f9},
3541 + {0x00009abc, 0x000000f9, 0x000000f9},
3542 + {0x00009ac0, 0x000000f9, 0x000000f9},
3543 + {0x00009ac4, 0x000000f9, 0x000000f9},
3544 + {0x00009ac8, 0x000000f9, 0x000000f9},
3545 + {0x00009acc, 0x000000f9, 0x000000f9},
3546 + {0x00009ad0, 0x000000f9, 0x000000f9},
3547 + {0x00009ad4, 0x000000f9, 0x000000f9},
3548 + {0x00009ad8, 0x000000f9, 0x000000f9},
3549 + {0x00009adc, 0x000000f9, 0x000000f9},
3550 + {0x00009ae0, 0x000000f9, 0x000000f9},
3551 + {0x00009ae4, 0x000000f9, 0x000000f9},
3552 + {0x00009ae8, 0x000000f9, 0x000000f9},
3553 + {0x00009aec, 0x000000f9, 0x000000f9},
3554 + {0x00009af0, 0x000000f9, 0x000000f9},
3555 + {0x00009af4, 0x000000f9, 0x000000f9},
3556 + {0x00009af8, 0x000000f9, 0x000000f9},
3557 + {0x00009afc, 0x000000f9, 0x000000f9},
3558 +};
3559 +
3560 +static const u32 ar5416Bank1_9160[][2] = {
3561 + {0x000098b0, 0x02108421},
3562 + {0x000098ec, 0x00000008},
3563 +};
3564 +
3565 +static const u32 ar5416Bank2_9160[][2] = {
3566 + {0x000098b0, 0x0e73ff17},
3567 + {0x000098e0, 0x00000420},
3568 +};
3569 +
3570 +static const u32 ar5416Bank3_9160[][3] = {
3571 + {0x000098f0, 0x01400018, 0x01c00018},
3572 +};
3573 +
3574 +static const u32 ar5416Bank6_9160[][3] = {
3575 + {0x0000989c, 0x00000000, 0x00000000},
3576 + {0x0000989c, 0x00000000, 0x00000000},
3577 + {0x0000989c, 0x00000000, 0x00000000},
3578 + {0x0000989c, 0x00e00000, 0x00e00000},
3579 + {0x0000989c, 0x005e0000, 0x005e0000},
3580 + {0x0000989c, 0x00120000, 0x00120000},
3581 + {0x0000989c, 0x00620000, 0x00620000},
3582 + {0x0000989c, 0x00020000, 0x00020000},
3583 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3584 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3585 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3586 + {0x0000989c, 0x40ff0000, 0x40ff0000},
3587 + {0x0000989c, 0x005f0000, 0x005f0000},
3588 + {0x0000989c, 0x00870000, 0x00870000},
3589 + {0x0000989c, 0x00f90000, 0x00f90000},
3590 + {0x0000989c, 0x007b0000, 0x007b0000},
3591 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3592 + {0x0000989c, 0x00f50000, 0x00f50000},
3593 + {0x0000989c, 0x00dc0000, 0x00dc0000},
3594 + {0x0000989c, 0x00110000, 0x00110000},
3595 + {0x0000989c, 0x006100a8, 0x006100a8},
3596 + {0x0000989c, 0x004210a2, 0x004210a2},
3597 + {0x0000989c, 0x0014008f, 0x0014008f},
3598 + {0x0000989c, 0x00c40003, 0x00c40003},
3599 + {0x0000989c, 0x003000f2, 0x003000f2},
3600 + {0x0000989c, 0x00440016, 0x00440016},
3601 + {0x0000989c, 0x00410040, 0x00410040},
3602 + {0x0000989c, 0x0001805e, 0x0001805e},
3603 + {0x0000989c, 0x0000c0ab, 0x0000c0ab},
3604 + {0x0000989c, 0x000000f1, 0x000000f1},
3605 + {0x0000989c, 0x00002081, 0x00002081},
3606 + {0x0000989c, 0x000000d4, 0x000000d4},
3607 + {0x000098d0, 0x0000000f, 0x0010000f},
3608 +};
3609 +
3610 +static const u32 ar5416Bank6TPC_9160[][3] = {
3611 + {0x0000989c, 0x00000000, 0x00000000},
3612 + {0x0000989c, 0x00000000, 0x00000000},
3613 + {0x0000989c, 0x00000000, 0x00000000},
3614 + {0x0000989c, 0x00e00000, 0x00e00000},
3615 + {0x0000989c, 0x005e0000, 0x005e0000},
3616 + {0x0000989c, 0x00120000, 0x00120000},
3617 + {0x0000989c, 0x00620000, 0x00620000},
3618 + {0x0000989c, 0x00020000, 0x00020000},
3619 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3620 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3621 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3622 + {0x0000989c, 0x40ff0000, 0x40ff0000},
3623 + {0x0000989c, 0x005f0000, 0x005f0000},
3624 + {0x0000989c, 0x00870000, 0x00870000},
3625 + {0x0000989c, 0x00f90000, 0x00f90000},
3626 + {0x0000989c, 0x007b0000, 0x007b0000},
3627 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3628 + {0x0000989c, 0x00f50000, 0x00f50000},
3629 + {0x0000989c, 0x00dc0000, 0x00dc0000},
3630 + {0x0000989c, 0x00110000, 0x00110000},
3631 + {0x0000989c, 0x006100a8, 0x006100a8},
3632 + {0x0000989c, 0x00423022, 0x00423022},
3633 + {0x0000989c, 0x2014008f, 0x2014008f},
3634 + {0x0000989c, 0x00c40002, 0x00c40002},
3635 + {0x0000989c, 0x003000f2, 0x003000f2},
3636 + {0x0000989c, 0x00440016, 0x00440016},
3637 + {0x0000989c, 0x00410040, 0x00410040},
3638 + {0x0000989c, 0x0001805e, 0x0001805e},
3639 + {0x0000989c, 0x0000c0ab, 0x0000c0ab},
3640 + {0x0000989c, 0x000000e1, 0x000000e1},
3641 + {0x0000989c, 0x00007080, 0x00007080},
3642 + {0x0000989c, 0x000000d4, 0x000000d4},
3643 + {0x000098d0, 0x0000000f, 0x0010000f},
3644 +};
3645 +
3646 +static const u32 ar5416Bank7_9160[][2] = {
3647 + {0x0000989c, 0x00000500},
3648 + {0x0000989c, 0x00000800},
3649 + {0x000098cc, 0x0000000e},
3650 +};
3651 +
3652 +static u32 ar5416Addac_9160[][2] = {
3653 + {0x0000989c, 0x00000000},
3654 + {0x0000989c, 0x00000000},
3655 + {0x0000989c, 0x00000000},
3656 + {0x0000989c, 0x00000000},
3657 + {0x0000989c, 0x00000000},
3658 + {0x0000989c, 0x00000000},
3659 + {0x0000989c, 0x000000c0},
3660 + {0x0000989c, 0x00000018},
3661 + {0x0000989c, 0x00000004},
3662 + {0x0000989c, 0x00000000},
3663 + {0x0000989c, 0x00000000},
3664 + {0x0000989c, 0x00000000},
3665 + {0x0000989c, 0x00000000},
3666 + {0x0000989c, 0x00000000},
3667 + {0x0000989c, 0x00000000},
3668 + {0x0000989c, 0x00000000},
3669 + {0x0000989c, 0x00000000},
3670 + {0x0000989c, 0x00000000},
3671 + {0x0000989c, 0x00000000},
3672 + {0x0000989c, 0x00000000},
3673 + {0x0000989c, 0x00000000},
3674 + {0x0000989c, 0x000000c0},
3675 + {0x0000989c, 0x00000019},
3676 + {0x0000989c, 0x00000004},
3677 + {0x0000989c, 0x00000000},
3678 + {0x0000989c, 0x00000000},
3679 + {0x0000989c, 0x00000000},
3680 + {0x0000989c, 0x00000004},
3681 + {0x0000989c, 0x00000003},
3682 + {0x0000989c, 0x00000008},
3683 + {0x0000989c, 0x00000000},
3684 + {0x000098cc, 0x00000000},
3685 +};
3686 +
3687 +static u32 ar5416Addac_91601_1[][2] = {
3688 + {0x0000989c, 0x00000000},
3689 + {0x0000989c, 0x00000000},
3690 + {0x0000989c, 0x00000000},
3691 + {0x0000989c, 0x00000000},
3692 + {0x0000989c, 0x00000000},
3693 + {0x0000989c, 0x00000000},
3694 + {0x0000989c, 0x000000c0},
3695 + {0x0000989c, 0x00000018},
3696 + {0x0000989c, 0x00000004},
3697 + {0x0000989c, 0x00000000},
3698 + {0x0000989c, 0x00000000},
3699 + {0x0000989c, 0x00000000},
3700 + {0x0000989c, 0x00000000},
3701 + {0x0000989c, 0x00000000},
3702 + {0x0000989c, 0x00000000},
3703 + {0x0000989c, 0x00000000},
3704 + {0x0000989c, 0x00000000},
3705 + {0x0000989c, 0x00000000},
3706 + {0x0000989c, 0x00000000},
3707 + {0x0000989c, 0x00000000},
3708 + {0x0000989c, 0x00000000},
3709 + {0x0000989c, 0x000000c0},
3710 + {0x0000989c, 0x00000019},
3711 + {0x0000989c, 0x00000004},
3712 + {0x0000989c, 0x00000000},
3713 + {0x0000989c, 0x00000000},
3714 + {0x0000989c, 0x00000000},
3715 + {0x0000989c, 0x00000000},
3716 + {0x0000989c, 0x00000000},
3717 + {0x0000989c, 0x00000000},
3718 + {0x0000989c, 0x00000000},
3719 + {0x000098cc, 0x00000000},
3720 +};
3721 diff --git a/drivers/net/wireless/ath/ath9k/ar9002_calib.c b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
3722 new file mode 100644
3723 index 0000000..4237269
3724 --- /dev/null
3725 +++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
3726 @@ -0,0 +1,988 @@
3727 +/*
3728 + * Copyright (c) 2008-2010 Atheros Communications Inc.
3729 + *
3730 + * Permission to use, copy, modify, and/or distribute this software for any
3731 + * purpose with or without fee is hereby granted, provided that the above
3732 + * copyright notice and this permission notice appear in all copies.
3733 + *
3734 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
3735 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
3736 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
3737 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
3738 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
3739 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
3740 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
3741 + */
3742 +
3743 +#include "hw.h"
3744 +#include "hw-ops.h"
3745 +#include "ar9002_phy.h"
3746 +
3747 +#define AR9285_CLCAL_REDO_THRESH 1
3748 +
3749 +static void ar9002_hw_setup_calibration(struct ath_hw *ah,
3750 + struct ath9k_cal_list *currCal)
3751 +{
3752 + struct ath_common *common = ath9k_hw_common(ah);
3753 +
3754 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
3755 + AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
3756 + currCal->calData->calCountMax);
3757 +
3758 + switch (currCal->calData->calType) {
3759 + case IQ_MISMATCH_CAL:
3760 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
3761 + ath_print(common, ATH_DBG_CALIBRATE,
3762 + "starting IQ Mismatch Calibration\n");
3763 + break;
3764 + case ADC_GAIN_CAL:
3765 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
3766 + ath_print(common, ATH_DBG_CALIBRATE,
3767 + "starting ADC Gain Calibration\n");
3768 + break;
3769 + case ADC_DC_CAL:
3770 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
3771 + ath_print(common, ATH_DBG_CALIBRATE,
3772 + "starting ADC DC Calibration\n");
3773 + break;
3774 + case ADC_DC_INIT_CAL:
3775 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
3776 + ath_print(common, ATH_DBG_CALIBRATE,
3777 + "starting Init ADC DC Calibration\n");
3778 + break;
3779 + case TEMP_COMP_CAL:
3780 + break; /* Not supported */
3781 + }
3782 +
3783 + REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
3784 + AR_PHY_TIMING_CTRL4_DO_CAL);
3785 +}
3786 +
3787 +static bool ar9002_hw_per_calibration(struct ath_hw *ah,
3788 + struct ath9k_channel *ichan,
3789 + u8 rxchainmask,
3790 + struct ath9k_cal_list *currCal)
3791 +{
3792 + bool iscaldone = false;
3793 +
3794 + if (currCal->calState == CAL_RUNNING) {
3795 + if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
3796 + AR_PHY_TIMING_CTRL4_DO_CAL)) {
3797 +
3798 + currCal->calData->calCollect(ah);
3799 + ah->cal_samples++;
3800 +
3801 + if (ah->cal_samples >= currCal->calData->calNumSamples) {
3802 + int i, numChains = 0;
3803 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3804 + if (rxchainmask & (1 << i))
3805 + numChains++;
3806 + }
3807 +
3808 + currCal->calData->calPostProc(ah, numChains);
3809 + ichan->CalValid |= currCal->calData->calType;
3810 + currCal->calState = CAL_DONE;
3811 + iscaldone = true;
3812 + } else {
3813 + ar9002_hw_setup_calibration(ah, currCal);
3814 + }
3815 + }
3816 + } else if (!(ichan->CalValid & currCal->calData->calType)) {
3817 + ath9k_hw_reset_calibration(ah, currCal);
3818 + }
3819 +
3820 + return iscaldone;
3821 +}
3822 +
3823 +/* Assumes you are talking about the currently configured channel */
3824 +static bool ar9002_hw_iscal_supported(struct ath_hw *ah,
3825 + enum ath9k_cal_types calType)
3826 +{
3827 + struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3828 +
3829 + switch (calType & ah->supp_cals) {
3830 + case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
3831 + return true;
3832 + case ADC_GAIN_CAL:
3833 + case ADC_DC_CAL:
3834 + if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
3835 + conf_is_ht20(conf)))
3836 + return true;
3837 + break;
3838 + }
3839 + return false;
3840 +}
3841 +
3842 +static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
3843 +{
3844 + int i;
3845 +
3846 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3847 + ah->totalPowerMeasI[i] +=
3848 + REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3849 + ah->totalPowerMeasQ[i] +=
3850 + REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3851 + ah->totalIqCorrMeas[i] +=
3852 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3853 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3854 + "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
3855 + ah->cal_samples, i, ah->totalPowerMeasI[i],
3856 + ah->totalPowerMeasQ[i],
3857 + ah->totalIqCorrMeas[i]);
3858 + }
3859 +}
3860 +
3861 +static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
3862 +{
3863 + int i;
3864 +
3865 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3866 + ah->totalAdcIOddPhase[i] +=
3867 + REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3868 + ah->totalAdcIEvenPhase[i] +=
3869 + REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3870 + ah->totalAdcQOddPhase[i] +=
3871 + REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3872 + ah->totalAdcQEvenPhase[i] +=
3873 + REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
3874 +
3875 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3876 + "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
3877 + "oddq=0x%08x; evenq=0x%08x;\n",
3878 + ah->cal_samples, i,
3879 + ah->totalAdcIOddPhase[i],
3880 + ah->totalAdcIEvenPhase[i],
3881 + ah->totalAdcQOddPhase[i],
3882 + ah->totalAdcQEvenPhase[i]);
3883 + }
3884 +}
3885 +
3886 +static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
3887 +{
3888 + int i;
3889 +
3890 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3891 + ah->totalAdcDcOffsetIOddPhase[i] +=
3892 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3893 + ah->totalAdcDcOffsetIEvenPhase[i] +=
3894 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3895 + ah->totalAdcDcOffsetQOddPhase[i] +=
3896 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3897 + ah->totalAdcDcOffsetQEvenPhase[i] +=
3898 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
3899 +
3900 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3901 + "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
3902 + "oddq=0x%08x; evenq=0x%08x;\n",
3903 + ah->cal_samples, i,
3904 + ah->totalAdcDcOffsetIOddPhase[i],
3905 + ah->totalAdcDcOffsetIEvenPhase[i],
3906 + ah->totalAdcDcOffsetQOddPhase[i],
3907 + ah->totalAdcDcOffsetQEvenPhase[i]);
3908 + }
3909 +}
3910 +
3911 +static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
3912 +{
3913 + struct ath_common *common = ath9k_hw_common(ah);
3914 + u32 powerMeasQ, powerMeasI, iqCorrMeas;
3915 + u32 qCoffDenom, iCoffDenom;
3916 + int32_t qCoff, iCoff;
3917 + int iqCorrNeg, i;
3918 +
3919 + for (i = 0; i < numChains; i++) {
3920 + powerMeasI = ah->totalPowerMeasI[i];
3921 + powerMeasQ = ah->totalPowerMeasQ[i];
3922 + iqCorrMeas = ah->totalIqCorrMeas[i];
3923 +
3924 + ath_print(common, ATH_DBG_CALIBRATE,
3925 + "Starting IQ Cal and Correction for Chain %d\n",
3926 + i);
3927 +
3928 + ath_print(common, ATH_DBG_CALIBRATE,
3929 + "Orignal: Chn %diq_corr_meas = 0x%08x\n",
3930 + i, ah->totalIqCorrMeas[i]);
3931 +
3932 + iqCorrNeg = 0;
3933 +
3934 + if (iqCorrMeas > 0x80000000) {
3935 + iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
3936 + iqCorrNeg = 1;
3937 + }
3938 +
3939 + ath_print(common, ATH_DBG_CALIBRATE,
3940 + "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
3941 + ath_print(common, ATH_DBG_CALIBRATE,
3942 + "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
3943 + ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
3944 + iqCorrNeg);
3945 +
3946 + iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
3947 + qCoffDenom = powerMeasQ / 64;
3948 +
3949 + if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
3950 + (qCoffDenom != 0)) {
3951 + iCoff = iqCorrMeas / iCoffDenom;
3952 + qCoff = powerMeasI / qCoffDenom - 64;
3953 + ath_print(common, ATH_DBG_CALIBRATE,
3954 + "Chn %d iCoff = 0x%08x\n", i, iCoff);
3955 + ath_print(common, ATH_DBG_CALIBRATE,
3956 + "Chn %d qCoff = 0x%08x\n", i, qCoff);
3957 +
3958 + iCoff = iCoff & 0x3f;
3959 + ath_print(common, ATH_DBG_CALIBRATE,
3960 + "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
3961 + if (iqCorrNeg == 0x0)
3962 + iCoff = 0x40 - iCoff;
3963 +
3964 + if (qCoff > 15)
3965 + qCoff = 15;
3966 + else if (qCoff <= -16)
3967 + qCoff = 16;
3968 +
3969 + ath_print(common, ATH_DBG_CALIBRATE,
3970 + "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
3971 + i, iCoff, qCoff);
3972 +
3973 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
3974 + AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
3975 + iCoff);
3976 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
3977 + AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
3978 + qCoff);
3979 + ath_print(common, ATH_DBG_CALIBRATE,
3980 + "IQ Cal and Correction done for Chain %d\n",
3981 + i);
3982 + }
3983 + }
3984 +
3985 + REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
3986 + AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
3987 +}
3988 +
3989 +static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
3990 +{
3991 + struct ath_common *common = ath9k_hw_common(ah);
3992 + u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
3993 + u32 qGainMismatch, iGainMismatch, val, i;
3994 +
3995 + for (i = 0; i < numChains; i++) {
3996 + iOddMeasOffset = ah->totalAdcIOddPhase[i];
3997 + iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
3998 + qOddMeasOffset = ah->totalAdcQOddPhase[i];
3999 + qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
4000 +
4001 + ath_print(common, ATH_DBG_CALIBRATE,
4002 + "Starting ADC Gain Cal for Chain %d\n", i);
4003 +
4004 + ath_print(common, ATH_DBG_CALIBRATE,
4005 + "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
4006 + iOddMeasOffset);
4007 + ath_print(common, ATH_DBG_CALIBRATE,
4008 + "Chn %d pwr_meas_even_i = 0x%08x\n", i,
4009 + iEvenMeasOffset);
4010 + ath_print(common, ATH_DBG_CALIBRATE,
4011 + "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
4012 + qOddMeasOffset);
4013 + ath_print(common, ATH_DBG_CALIBRATE,
4014 + "Chn %d pwr_meas_even_q = 0x%08x\n", i,
4015 + qEvenMeasOffset);
4016 +
4017 + if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
4018 + iGainMismatch =
4019 + ((iEvenMeasOffset * 32) /
4020 + iOddMeasOffset) & 0x3f;
4021 + qGainMismatch =
4022 + ((qOddMeasOffset * 32) /
4023 + qEvenMeasOffset) & 0x3f;
4024 +
4025 + ath_print(common, ATH_DBG_CALIBRATE,
4026 + "Chn %d gain_mismatch_i = 0x%08x\n", i,
4027 + iGainMismatch);
4028 + ath_print(common, ATH_DBG_CALIBRATE,
4029 + "Chn %d gain_mismatch_q = 0x%08x\n", i,
4030 + qGainMismatch);
4031 +
4032 + val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
4033 + val &= 0xfffff000;
4034 + val |= (qGainMismatch) | (iGainMismatch << 6);
4035 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
4036 +
4037 + ath_print(common, ATH_DBG_CALIBRATE,
4038 + "ADC Gain Cal done for Chain %d\n", i);
4039 + }
4040 + }
4041 +
4042 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
4043 + REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
4044 + AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
4045 +}
4046 +
4047 +static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
4048 +{
4049 + struct ath_common *common = ath9k_hw_common(ah);
4050 + u32 iOddMeasOffset, iEvenMeasOffset, val, i;
4051 + int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
4052 + const struct ath9k_percal_data *calData =
4053 + ah->cal_list_curr->calData;
4054 + u32 numSamples =
4055 + (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
4056 +
4057 + for (i = 0; i < numChains; i++) {
4058 + iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
4059 + iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
4060 + qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
4061 + qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
4062 +
4063 + ath_print(common, ATH_DBG_CALIBRATE,
4064 + "Starting ADC DC Offset Cal for Chain %d\n", i);
4065 +
4066 + ath_print(common, ATH_DBG_CALIBRATE,
4067 + "Chn %d pwr_meas_odd_i = %d\n", i,
4068 + iOddMeasOffset);
4069 + ath_print(common, ATH_DBG_CALIBRATE,
4070 + "Chn %d pwr_meas_even_i = %d\n", i,
4071 + iEvenMeasOffset);
4072 + ath_print(common, ATH_DBG_CALIBRATE,
4073 + "Chn %d pwr_meas_odd_q = %d\n", i,
4074 + qOddMeasOffset);
4075 + ath_print(common, ATH_DBG_CALIBRATE,
4076 + "Chn %d pwr_meas_even_q = %d\n", i,
4077 + qEvenMeasOffset);
4078 +
4079 + iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
4080 + numSamples) & 0x1ff;
4081 + qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
4082 + numSamples) & 0x1ff;
4083 +
4084 + ath_print(common, ATH_DBG_CALIBRATE,
4085 + "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
4086 + iDcMismatch);
4087 + ath_print(common, ATH_DBG_CALIBRATE,
4088 + "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
4089 + qDcMismatch);
4090 +
4091 + val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
4092 + val &= 0xc0000fff;
4093 + val |= (qDcMismatch << 12) | (iDcMismatch << 21);
4094 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
4095 +
4096 + ath_print(common, ATH_DBG_CALIBRATE,
4097 + "ADC DC Offset Cal done for Chain %d\n", i);
4098 + }
4099 +
4100 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
4101 + REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
4102 + AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
4103 +}
4104 +
4105 +static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
4106 +{
4107 + u32 rddata;
4108 + int32_t delta, currPDADC, slope;
4109 +
4110 + rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
4111 + currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
4112 +
4113 + if (ah->initPDADC == 0 || currPDADC == 0) {
4114 + /*
4115 + * Zero value indicates that no frames have been transmitted yet,
4116 + * can't do temperature compensation until frames are transmitted.
4117 + */
4118 + return;
4119 + } else {
4120 + slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
4121 +
4122 + if (slope == 0) { /* to avoid divide by zero case */
4123 + delta = 0;
4124 + } else {
4125 + delta = ((currPDADC - ah->initPDADC)*4) / slope;
4126 + }
4127 + REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
4128 + AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
4129 + REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
4130 + AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
4131 + }
4132 +}
4133 +
4134 +static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah)
4135 +{
4136 + u32 rddata, i;
4137 + int delta, currPDADC, regval;
4138 +
4139 + rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
4140 + currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
4141 +
4142 + if (ah->initPDADC == 0 || currPDADC == 0)
4143 + return;
4144 +
4145 + if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
4146 + delta = (currPDADC - ah->initPDADC + 4) / 8;
4147 + else
4148 + delta = (currPDADC - ah->initPDADC + 5) / 10;
4149 +
4150 + if (delta != ah->PDADCdelta) {
4151 + ah->PDADCdelta = delta;
4152 + for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
4153 + regval = ah->originalGain[i] - delta;
4154 + if (regval < 0)
4155 + regval = 0;
4156 +
4157 + REG_RMW_FIELD(ah,
4158 + AR_PHY_TX_GAIN_TBL1 + i * 4,
4159 + AR_PHY_TX_GAIN, regval);
4160 + }
4161 + }
4162 +}
4163 +
4164 +static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
4165 +{
4166 + u32 regVal;
4167 + unsigned int i;
4168 + u32 regList [][2] = {
4169 + { 0x786c, 0 },
4170 + { 0x7854, 0 },
4171 + { 0x7820, 0 },
4172 + { 0x7824, 0 },
4173 + { 0x7868, 0 },
4174 + { 0x783c, 0 },
4175 + { 0x7838, 0 } ,
4176 + { 0x7828, 0 } ,
4177 + };
4178 +
4179 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4180 + regList[i][1] = REG_READ(ah, regList[i][0]);
4181 +
4182 + regVal = REG_READ(ah, 0x7834);
4183 + regVal &= (~(0x1));
4184 + REG_WRITE(ah, 0x7834, regVal);
4185 + regVal = REG_READ(ah, 0x9808);
4186 + regVal |= (0x1 << 27);
4187 + REG_WRITE(ah, 0x9808, regVal);
4188 +
4189 + /* 786c,b23,1, pwddac=1 */
4190 + REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
4191 + /* 7854, b5,1, pdrxtxbb=1 */
4192 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
4193 + /* 7854, b7,1, pdv2i=1 */
4194 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
4195 + /* 7854, b8,1, pddacinterface=1 */
4196 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
4197 + /* 7824,b12,0, offcal=0 */
4198 + REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
4199 + /* 7838, b1,0, pwddb=0 */
4200 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
4201 + /* 7820,b11,0, enpacal=0 */
4202 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
4203 + /* 7820,b25,1, pdpadrv1=0 */
4204 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
4205 + /* 7820,b24,0, pdpadrv2=0 */
4206 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0);
4207 + /* 7820,b23,0, pdpaout=0 */
4208 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
4209 + /* 783c,b14-16,7, padrvgn2tab_0=7 */
4210 + REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
4211 + /*
4212 + * 7838,b29-31,0, padrvgn1tab_0=0
4213 + * does not matter since we turn it off
4214 + */
4215 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
4216 +
4217 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
4218 +
4219 + /* Set:
4220 + * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
4221 + * txon=1,paon=1,oscon=1,synthon_force=1
4222 + */
4223 + REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
4224 + udelay(30);
4225 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
4226 +
4227 + /* find off_6_1; */
4228 + for (i = 6; i > 0; i--) {
4229 + regVal = REG_READ(ah, 0x7834);
4230 + regVal |= (1 << (20 + i));
4231 + REG_WRITE(ah, 0x7834, regVal);
4232 + udelay(1);
4233 + //regVal = REG_READ(ah, 0x7834);
4234 + regVal &= (~(0x1 << (20 + i)));
4235 + regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
4236 + << (20 + i));
4237 + REG_WRITE(ah, 0x7834, regVal);
4238 + }
4239 +
4240 + regVal = (regVal >>20) & 0x7f;
4241 +
4242 + /* Update PA cal info */
4243 + if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
4244 + if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
4245 + ah->pacal_info.max_skipcount =
4246 + 2 * ah->pacal_info.max_skipcount;
4247 + ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
4248 + } else {
4249 + ah->pacal_info.max_skipcount = 1;
4250 + ah->pacal_info.skipcount = 0;
4251 + ah->pacal_info.prev_offset = regVal;
4252 + }
4253 +
4254 + regVal = REG_READ(ah, 0x7834);
4255 + regVal |= 0x1;
4256 + REG_WRITE(ah, 0x7834, regVal);
4257 + regVal = REG_READ(ah, 0x9808);
4258 + regVal &= (~(0x1 << 27));
4259 + REG_WRITE(ah, 0x9808, regVal);
4260 +
4261 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4262 + REG_WRITE(ah, regList[i][0], regList[i][1]);
4263 +}
4264 +
4265 +static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
4266 +{
4267 + struct ath_common *common = ath9k_hw_common(ah);
4268 + u32 regVal;
4269 + int i, offset, offs_6_1, offs_0;
4270 + u32 ccomp_org, reg_field;
4271 + u32 regList[][2] = {
4272 + { 0x786c, 0 },
4273 + { 0x7854, 0 },
4274 + { 0x7820, 0 },
4275 + { 0x7824, 0 },
4276 + { 0x7868, 0 },
4277 + { 0x783c, 0 },
4278 + { 0x7838, 0 },
4279 + };
4280 +
4281 + ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
4282 +
4283 + /* PA CAL is not needed for high power solution */
4284 + if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
4285 + AR5416_EEP_TXGAIN_HIGH_POWER)
4286 + return;
4287 +
4288 + if (AR_SREV_9285_11(ah)) {
4289 + REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
4290 + udelay(10);
4291 + }
4292 +
4293 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4294 + regList[i][1] = REG_READ(ah, regList[i][0]);
4295 +
4296 + regVal = REG_READ(ah, 0x7834);
4297 + regVal &= (~(0x1));
4298 + REG_WRITE(ah, 0x7834, regVal);
4299 + regVal = REG_READ(ah, 0x9808);
4300 + regVal |= (0x1 << 27);
4301 + REG_WRITE(ah, 0x9808, regVal);
4302 +
4303 + REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
4304 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
4305 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
4306 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
4307 + REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
4308 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
4309 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
4310 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
4311 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
4312 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
4313 + REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
4314 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
4315 + ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
4316 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
4317 +
4318 + REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
4319 + udelay(30);
4320 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
4321 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
4322 +
4323 + for (i = 6; i > 0; i--) {
4324 + regVal = REG_READ(ah, 0x7834);
4325 + regVal |= (1 << (19 + i));
4326 + REG_WRITE(ah, 0x7834, regVal);
4327 + udelay(1);
4328 + regVal = REG_READ(ah, 0x7834);
4329 + regVal &= (~(0x1 << (19 + i)));
4330 + reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
4331 + regVal |= (reg_field << (19 + i));
4332 + REG_WRITE(ah, 0x7834, regVal);
4333 + }
4334 +
4335 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
4336 + udelay(1);
4337 + reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
4338 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
4339 + offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
4340 + offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
4341 +
4342 + offset = (offs_6_1<<1) | offs_0;
4343 + offset = offset - 0;
4344 + offs_6_1 = offset>>1;
4345 + offs_0 = offset & 1;
4346 +
4347 + if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
4348 + if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
4349 + ah->pacal_info.max_skipcount =
4350 + 2 * ah->pacal_info.max_skipcount;
4351 + ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
4352 + } else {
4353 + ah->pacal_info.max_skipcount = 1;
4354 + ah->pacal_info.skipcount = 0;
4355 + ah->pacal_info.prev_offset = offset;
4356 + }
4357 +
4358 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
4359 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
4360 +
4361 + regVal = REG_READ(ah, 0x7834);
4362 + regVal |= 0x1;
4363 + REG_WRITE(ah, 0x7834, regVal);
4364 + regVal = REG_READ(ah, 0x9808);
4365 + regVal &= (~(0x1 << 27));
4366 + REG_WRITE(ah, 0x9808, regVal);
4367 +
4368 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4369 + REG_WRITE(ah, regList[i][0], regList[i][1]);
4370 +
4371 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
4372 +
4373 + if (AR_SREV_9285_11(ah))
4374 + REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
4375 +
4376 +}
4377 +
4378 +static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
4379 +{
4380 + if (AR_SREV_9271(ah)) {
4381 + if (is_reset || !ah->pacal_info.skipcount)
4382 + ar9271_hw_pa_cal(ah, is_reset);
4383 + else
4384 + ah->pacal_info.skipcount--;
4385 + } else if (AR_SREV_9285_11_OR_LATER(ah)) {
4386 + if (is_reset || !ah->pacal_info.skipcount)
4387 + ar9285_hw_pa_cal(ah, is_reset);
4388 + else
4389 + ah->pacal_info.skipcount--;
4390 + }
4391 +}
4392 +
4393 +static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
4394 +{
4395 + if (OLC_FOR_AR9287_10_LATER)
4396 + ar9287_hw_olc_temp_compensation(ah);
4397 + else if (OLC_FOR_AR9280_20_LATER)
4398 + ar9280_hw_olc_temp_compensation(ah);
4399 +}
4400 +
4401 +static bool ar9002_hw_calibrate(struct ath_hw *ah,
4402 + struct ath9k_channel *chan,
4403 + u8 rxchainmask,
4404 + bool longcal)
4405 +{
4406 + bool iscaldone = true;
4407 + struct ath9k_cal_list *currCal = ah->cal_list_curr;
4408 +
4409 + if (currCal &&
4410 + (currCal->calState == CAL_RUNNING ||
4411 + currCal->calState == CAL_WAITING)) {
4412 + iscaldone = ar9002_hw_per_calibration(ah, chan,
4413 + rxchainmask, currCal);
4414 + if (iscaldone) {
4415 + ah->cal_list_curr = currCal = currCal->calNext;
4416 +
4417 + if (currCal->calState == CAL_WAITING) {
4418 + iscaldone = false;
4419 + ath9k_hw_reset_calibration(ah, currCal);
4420 + }
4421 + }
4422 + }
4423 +
4424 + /* Do NF cal only at longer intervals */
4425 + if (longcal) {
4426 + /* Do periodic PAOffset Cal */
4427 + ar9002_hw_pa_cal(ah, false);
4428 + ar9002_hw_olc_temp_compensation(ah);
4429 +
4430 + /* Get the value from the previous NF cal and update history buffer */
4431 + ath9k_hw_getnf(ah, chan);
4432 +
4433 + /*
4434 + * Load the NF from history buffer of the current channel.
4435 + * NF is slow time-variant, so it is OK to use a historical value.
4436 + */
4437 + ath9k_hw_loadnf(ah, ah->curchan);
4438 +
4439 + ath9k_hw_start_nfcal(ah);
4440 + }
4441 +
4442 + return iscaldone;
4443 +}
4444 +
4445 +/* Carrier leakage Calibration fix */
4446 +static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
4447 +{
4448 + struct ath_common *common = ath9k_hw_common(ah);
4449 +
4450 + REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
4451 + if (IS_CHAN_HT20(chan)) {
4452 + REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
4453 + REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
4454 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
4455 + AR_PHY_AGC_CONTROL_FLTR_CAL);
4456 + REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
4457 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
4458 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
4459 + AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
4460 + ath_print(common, ATH_DBG_CALIBRATE, "offset "
4461 + "calibration failed to complete in "
4462 + "1ms; noisy ??\n");
4463 + return false;
4464 + }
4465 + REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
4466 + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
4467 + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
4468 + }
4469 + REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
4470 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
4471 + REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
4472 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
4473 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
4474 + 0, AH_WAIT_TIMEOUT)) {
4475 + ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
4476 + "failed to complete in 1ms; noisy ??\n");
4477 + return false;
4478 + }
4479 +
4480 + REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
4481 + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
4482 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
4483 +
4484 + return true;
4485 +}
4486 +
4487 +static bool ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan)
4488 +{
4489 + int i;
4490 + u_int32_t txgain_max;
4491 + u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
4492 + u_int32_t reg_clc_I0, reg_clc_Q0;
4493 + u_int32_t i0_num = 0;
4494 + u_int32_t q0_num = 0;
4495 + u_int32_t total_num = 0;
4496 + u_int32_t reg_rf2g5_org;
4497 + bool retv = true;
4498 +
4499 + if (!(ar9285_hw_cl_cal(ah, chan)))
4500 + return false;
4501 +
4502 + txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
4503 + AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
4504 +
4505 + for (i = 0; i < (txgain_max+1); i++) {
4506 + clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
4507 + AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
4508 + if (!(gain_mask & (1 << clc_gain))) {
4509 + gain_mask |= (1 << clc_gain);
4510 + clc_num++;
4511 + }
4512 + }
4513 +
4514 + for (i = 0; i < clc_num; i++) {
4515 + reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
4516 + & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
4517 + reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
4518 + & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
4519 + if (reg_clc_I0 == 0)
4520 + i0_num++;
4521 +
4522 + if (reg_clc_Q0 == 0)
4523 + q0_num++;
4524 + }
4525 + total_num = i0_num + q0_num;
4526 + if (total_num > AR9285_CLCAL_REDO_THRESH) {
4527 + reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
4528 + if (AR_SREV_9285E_20(ah)) {
4529 + REG_WRITE(ah, AR9285_RF2G5,
4530 + (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
4531 + AR9285_RF2G5_IC50TX_XE_SET);
4532 + } else {
4533 + REG_WRITE(ah, AR9285_RF2G5,
4534 + (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
4535 + AR9285_RF2G5_IC50TX_SET);
4536 + }
4537 + retv = ar9285_hw_cl_cal(ah, chan);
4538 + REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
4539 + }
4540 + return retv;
4541 +}
4542 +
4543 +static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
4544 +{
4545 + struct ath_common *common = ath9k_hw_common(ah);
4546 +
4547 + if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
4548 + if (!ar9285_hw_clc(ah, chan))
4549 + return false;
4550 + } else {
4551 + if (AR_SREV_9280_10_OR_LATER(ah)) {
4552 + if (!AR_SREV_9287_10_OR_LATER(ah))
4553 + REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
4554 + AR_PHY_ADC_CTL_OFF_PWDADC);
4555 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
4556 + AR_PHY_AGC_CONTROL_FLTR_CAL);
4557 + }
4558 +
4559 + /* Calibrate the AGC */
4560 + REG_WRITE(ah, AR_PHY_AGC_CONTROL,
4561 + REG_READ(ah, AR_PHY_AGC_CONTROL) |
4562 + AR_PHY_AGC_CONTROL_CAL);
4563 +
4564 + /* Poll for offset calibration complete */
4565 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
4566 + 0, AH_WAIT_TIMEOUT)) {
4567 + ath_print(common, ATH_DBG_CALIBRATE,
4568 + "offset calibration failed to "
4569 + "complete in 1ms; noisy environment?\n");
4570 + return false;
4571 + }
4572 +
4573 + if (AR_SREV_9280_10_OR_LATER(ah)) {
4574 + if (!AR_SREV_9287_10_OR_LATER(ah))
4575 + REG_SET_BIT(ah, AR_PHY_ADC_CTL,
4576 + AR_PHY_ADC_CTL_OFF_PWDADC);
4577 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
4578 + AR_PHY_AGC_CONTROL_FLTR_CAL);
4579 + }
4580 + }
4581 +
4582 + /* Do PA Calibration */
4583 + ar9002_hw_pa_cal(ah, true);
4584 +
4585 + /* Do NF Calibration after DC offset and other calibrations */
4586 + REG_WRITE(ah, AR_PHY_AGC_CONTROL,
4587 + REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
4588 +
4589 + ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
4590 +
4591 + /* Enable IQ, ADC Gain and ADC DC offset CALs */
4592 + if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
4593 + if (ar9002_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
4594 + INIT_CAL(&ah->adcgain_caldata);
4595 + INSERT_CAL(ah, &ah->adcgain_caldata);
4596 + ath_print(common, ATH_DBG_CALIBRATE,
4597 + "enabling ADC Gain Calibration.\n");
4598 + }
4599 + if (ar9002_hw_iscal_supported(ah, ADC_DC_CAL)) {
4600 + INIT_CAL(&ah->adcdc_caldata);
4601 + INSERT_CAL(ah, &ah->adcdc_caldata);
4602 + ath_print(common, ATH_DBG_CALIBRATE,
4603 + "enabling ADC DC Calibration.\n");
4604 + }
4605 + if (ar9002_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
4606 + INIT_CAL(&ah->iq_caldata);
4607 + INSERT_CAL(ah, &ah->iq_caldata);
4608 + ath_print(common, ATH_DBG_CALIBRATE,
4609 + "enabling IQ Calibration.\n");
4610 + }
4611 +
4612 + ah->cal_list_curr = ah->cal_list;
4613 +
4614 + if (ah->cal_list_curr)
4615 + ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
4616 + }
4617 +
4618 + chan->CalValid = 0;
4619 +
4620 + return true;
4621 +}
4622 +
4623 +static const struct ath9k_percal_data iq_cal_multi_sample = {
4624 + IQ_MISMATCH_CAL,
4625 + MAX_CAL_SAMPLES,
4626 + PER_MIN_LOG_COUNT,
4627 + ar9002_hw_iqcal_collect,
4628 + ar9002_hw_iqcalibrate
4629 +};
4630 +static const struct ath9k_percal_data iq_cal_single_sample = {
4631 + IQ_MISMATCH_CAL,
4632 + MIN_CAL_SAMPLES,
4633 + PER_MAX_LOG_COUNT,
4634 + ar9002_hw_iqcal_collect,
4635 + ar9002_hw_iqcalibrate
4636 +};
4637 +static const struct ath9k_percal_data adc_gain_cal_multi_sample = {
4638 + ADC_GAIN_CAL,
4639 + MAX_CAL_SAMPLES,
4640 + PER_MIN_LOG_COUNT,
4641 + ar9002_hw_adc_gaincal_collect,
4642 + ar9002_hw_adc_gaincal_calibrate
4643 +};
4644 +static const struct ath9k_percal_data adc_gain_cal_single_sample = {
4645 + ADC_GAIN_CAL,
4646 + MIN_CAL_SAMPLES,
4647 + PER_MAX_LOG_COUNT,
4648 + ar9002_hw_adc_gaincal_collect,
4649 + ar9002_hw_adc_gaincal_calibrate
4650 +};
4651 +static const struct ath9k_percal_data adc_dc_cal_multi_sample = {
4652 + ADC_DC_CAL,
4653 + MAX_CAL_SAMPLES,
4654 + PER_MIN_LOG_COUNT,
4655 + ar9002_hw_adc_dccal_collect,
4656 + ar9002_hw_adc_dccal_calibrate
4657 +};
4658 +static const struct ath9k_percal_data adc_dc_cal_single_sample = {
4659 + ADC_DC_CAL,
4660 + MIN_CAL_SAMPLES,
4661 + PER_MAX_LOG_COUNT,
4662 + ar9002_hw_adc_dccal_collect,
4663 + ar9002_hw_adc_dccal_calibrate
4664 +};
4665 +static const struct ath9k_percal_data adc_init_dc_cal = {
4666 + ADC_DC_INIT_CAL,
4667 + MIN_CAL_SAMPLES,
4668 + INIT_LOG_COUNT,
4669 + ar9002_hw_adc_dccal_collect,
4670 + ar9002_hw_adc_dccal_calibrate
4671 +};
4672 +
4673 +static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
4674 +{
4675 + if (AR_SREV_9100(ah)) {
4676 + ah->iq_caldata.calData = &iq_cal_multi_sample;
4677 + ah->supp_cals = IQ_MISMATCH_CAL;
4678 + return;
4679 + }
4680 +
4681 + if (AR_SREV_9160_10_OR_LATER(ah)) {
4682 + if (AR_SREV_9280_10_OR_LATER(ah)) {
4683 + ah->iq_caldata.calData = &iq_cal_single_sample;
4684 + ah->adcgain_caldata.calData =
4685 + &adc_gain_cal_single_sample;
4686 + ah->adcdc_caldata.calData =
4687 + &adc_dc_cal_single_sample;
4688 + ah->adcdc_calinitdata.calData =
4689 + &adc_init_dc_cal;
4690 + } else {
4691 + ah->iq_caldata.calData = &iq_cal_multi_sample;
4692 + ah->adcgain_caldata.calData =
4693 + &adc_gain_cal_multi_sample;
4694 + ah->adcdc_caldata.calData =
4695 + &adc_dc_cal_multi_sample;
4696 + ah->adcdc_calinitdata.calData =
4697 + &adc_init_dc_cal;
4698 + }
4699 + ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
4700 + }
4701 +}
4702 +
4703 +void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
4704 +{
4705 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
4706 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
4707 +
4708 + priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
4709 + priv_ops->init_cal = ar9002_hw_init_cal;
4710 + priv_ops->setup_calibration = ar9002_hw_setup_calibration;
4711 + priv_ops->iscal_supported = ar9002_hw_iscal_supported;
4712 +
4713 + ops->calibrate = ar9002_hw_calibrate;
4714 +}
4715 diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
4716 new file mode 100644
4717 index 0000000..c1b4f14
4718 --- /dev/null
4719 +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
4720 @@ -0,0 +1,601 @@
4721 +/*
4722 + * Copyright (c) 2008-2010 Atheros Communications Inc.
4723 + *
4724 + * Permission to use, copy, modify, and/or distribute this software for any
4725 + * purpose with or without fee is hereby granted, provided that the above
4726 + * copyright notice and this permission notice appear in all copies.
4727 + *
4728 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
4729 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
4730 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
4731 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
4732 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
4733 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
4734 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
4735 + */
4736 +
4737 +#include "hw.h"
4738 +#include "ar5008_initvals.h"
4739 +#include "ar9001_initvals.h"
4740 +#include "ar9002_initvals.h"
4741 +
4742 +/* General hardware code for the A5008/AR9001/AR9002 hadware families */
4743 +
4744 +static bool ar9002_hw_macversion_supported(u32 macversion)
4745 +{
4746 + switch (macversion) {
4747 + case AR_SREV_VERSION_5416_PCI:
4748 + case AR_SREV_VERSION_5416_PCIE:
4749 + case AR_SREV_VERSION_9160:
4750 + case AR_SREV_VERSION_9100:
4751 + case AR_SREV_VERSION_9280:
4752 + case AR_SREV_VERSION_9285:
4753 + case AR_SREV_VERSION_9287:
4754 + case AR_SREV_VERSION_9271:
4755 + return true;
4756 + default:
4757 + break;
4758 + }
4759 + return false;
4760 +}
4761 +
4762 +static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
4763 +{
4764 + if (AR_SREV_9271(ah)) {
4765 + INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
4766 + ARRAY_SIZE(ar9271Modes_9271), 6);
4767 + INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
4768 + ARRAY_SIZE(ar9271Common_9271), 2);
4769 + INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
4770 + ar9271Common_normal_cck_fir_coeff_9271,
4771 + ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
4772 + INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
4773 + ar9271Common_japan_2484_cck_fir_coeff_9271,
4774 + ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
4775 + INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
4776 + ar9271Modes_9271_1_0_only,
4777 + ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
4778 + INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
4779 + ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
4780 + INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
4781 + ar9271Modes_high_power_tx_gain_9271,
4782 + ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
4783 + INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
4784 + ar9271Modes_normal_power_tx_gain_9271,
4785 + ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
4786 + return;
4787 + }
4788 +
4789 + if (AR_SREV_9287_11_OR_LATER(ah)) {
4790 + INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
4791 + ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
4792 + INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
4793 + ARRAY_SIZE(ar9287Common_9287_1_1), 2);
4794 + if (ah->config.pcie_clock_req)
4795 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4796 + ar9287PciePhy_clkreq_off_L1_9287_1_1,
4797 + ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
4798 + else
4799 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4800 + ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
4801 + ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
4802 + 2);
4803 + } else if (AR_SREV_9287_10_OR_LATER(ah)) {
4804 + INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
4805 + ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
4806 + INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
4807 + ARRAY_SIZE(ar9287Common_9287_1_0), 2);
4808 +
4809 + if (ah->config.pcie_clock_req)
4810 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4811 + ar9287PciePhy_clkreq_off_L1_9287_1_0,
4812 + ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
4813 + else
4814 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4815 + ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
4816 + ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
4817 + 2);
4818 + } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4819 +
4820 +
4821 + INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
4822 + ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
4823 + INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
4824 + ARRAY_SIZE(ar9285Common_9285_1_2), 2);
4825 +
4826 + if (ah->config.pcie_clock_req) {
4827 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4828 + ar9285PciePhy_clkreq_off_L1_9285_1_2,
4829 + ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
4830 + } else {
4831 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4832 + ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
4833 + ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
4834 + 2);
4835 + }
4836 + } else if (AR_SREV_9285_10_OR_LATER(ah)) {
4837 + INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
4838 + ARRAY_SIZE(ar9285Modes_9285), 6);
4839 + INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
4840 + ARRAY_SIZE(ar9285Common_9285), 2);
4841 +
4842 + if (ah->config.pcie_clock_req) {
4843 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4844 + ar9285PciePhy_clkreq_off_L1_9285,
4845 + ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
4846 + } else {
4847 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4848 + ar9285PciePhy_clkreq_always_on_L1_9285,
4849 + ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
4850 + }
4851 + } else if (AR_SREV_9280_20_OR_LATER(ah)) {
4852 + INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
4853 + ARRAY_SIZE(ar9280Modes_9280_2), 6);
4854 + INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
4855 + ARRAY_SIZE(ar9280Common_9280_2), 2);
4856 +
4857 + if (ah->config.pcie_clock_req) {
4858 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4859 + ar9280PciePhy_clkreq_off_L1_9280,
4860 + ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
4861 + } else {
4862 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4863 + ar9280PciePhy_clkreq_always_on_L1_9280,
4864 + ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
4865 + }
4866 + INIT_INI_ARRAY(&ah->iniModesAdditional,
4867 + ar9280Modes_fast_clock_9280_2,
4868 + ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
4869 + } else if (AR_SREV_9280_10_OR_LATER(ah)) {
4870 + INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
4871 + ARRAY_SIZE(ar9280Modes_9280), 6);
4872 + INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
4873 + ARRAY_SIZE(ar9280Common_9280), 2);
4874 + } else if (AR_SREV_9160_10_OR_LATER(ah)) {
4875 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
4876 + ARRAY_SIZE(ar5416Modes_9160), 6);
4877 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
4878 + ARRAY_SIZE(ar5416Common_9160), 2);
4879 + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
4880 + ARRAY_SIZE(ar5416Bank0_9160), 2);
4881 + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
4882 + ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
4883 + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
4884 + ARRAY_SIZE(ar5416Bank1_9160), 2);
4885 + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
4886 + ARRAY_SIZE(ar5416Bank2_9160), 2);
4887 + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
4888 + ARRAY_SIZE(ar5416Bank3_9160), 3);
4889 + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
4890 + ARRAY_SIZE(ar5416Bank6_9160), 3);
4891 + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
4892 + ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
4893 + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
4894 + ARRAY_SIZE(ar5416Bank7_9160), 2);
4895 + if (AR_SREV_9160_11(ah)) {
4896 + INIT_INI_ARRAY(&ah->iniAddac,
4897 + ar5416Addac_91601_1,
4898 + ARRAY_SIZE(ar5416Addac_91601_1), 2);
4899 + } else {
4900 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
4901 + ARRAY_SIZE(ar5416Addac_9160), 2);
4902 + }
4903 + } else if (AR_SREV_9100_OR_LATER(ah)) {
4904 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
4905 + ARRAY_SIZE(ar5416Modes_9100), 6);
4906 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
4907 + ARRAY_SIZE(ar5416Common_9100), 2);
4908 + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
4909 + ARRAY_SIZE(ar5416Bank0_9100), 2);
4910 + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
4911 + ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
4912 + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
4913 + ARRAY_SIZE(ar5416Bank1_9100), 2);
4914 + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
4915 + ARRAY_SIZE(ar5416Bank2_9100), 2);
4916 + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
4917 + ARRAY_SIZE(ar5416Bank3_9100), 3);
4918 + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
4919 + ARRAY_SIZE(ar5416Bank6_9100), 3);
4920 + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
4921 + ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
4922 + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
4923 + ARRAY_SIZE(ar5416Bank7_9100), 2);
4924 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
4925 + ARRAY_SIZE(ar5416Addac_9100), 2);
4926 + } else {
4927 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
4928 + ARRAY_SIZE(ar5416Modes), 6);
4929 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
4930 + ARRAY_SIZE(ar5416Common), 2);
4931 + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
4932 + ARRAY_SIZE(ar5416Bank0), 2);
4933 + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
4934 + ARRAY_SIZE(ar5416BB_RfGain), 3);
4935 + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
4936 + ARRAY_SIZE(ar5416Bank1), 2);
4937 + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
4938 + ARRAY_SIZE(ar5416Bank2), 2);
4939 + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
4940 + ARRAY_SIZE(ar5416Bank3), 3);
4941 + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
4942 + ARRAY_SIZE(ar5416Bank6), 3);
4943 + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
4944 + ARRAY_SIZE(ar5416Bank6TPC), 3);
4945 + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
4946 + ARRAY_SIZE(ar5416Bank7), 2);
4947 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
4948 + ARRAY_SIZE(ar5416Addac), 2);
4949 + }
4950 +}
4951 +
4952 +/* Support for Japan ch.14 (2484) spread */
4953 +void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
4954 +{
4955 + if (AR_SREV_9287_11_OR_LATER(ah)) {
4956 + INIT_INI_ARRAY(&ah->iniCckfirNormal,
4957 + ar9287Common_normal_cck_fir_coeff_92871_1,
4958 + ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
4959 + INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
4960 + ar9287Common_japan_2484_cck_fir_coeff_92871_1,
4961 + ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
4962 + }
4963 +}
4964 +
4965 +static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
4966 +{
4967 + u32 rxgain_type;
4968 +
4969 + if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
4970 + rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
4971 +
4972 + if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
4973 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4974 + ar9280Modes_backoff_13db_rxgain_9280_2,
4975 + ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
4976 + else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
4977 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4978 + ar9280Modes_backoff_23db_rxgain_9280_2,
4979 + ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
4980 + else
4981 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4982 + ar9280Modes_original_rxgain_9280_2,
4983 + ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
4984 + } else {
4985 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4986 + ar9280Modes_original_rxgain_9280_2,
4987 + ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
4988 + }
4989 +}
4990 +
4991 +static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah)
4992 +{
4993 + u32 txgain_type;
4994 +
4995 + if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
4996 + txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
4997 +
4998 + if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
4999 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5000 + ar9280Modes_high_power_tx_gain_9280_2,
5001 + ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
5002 + else
5003 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5004 + ar9280Modes_original_tx_gain_9280_2,
5005 + ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
5006 + } else {
5007 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5008 + ar9280Modes_original_tx_gain_9280_2,
5009 + ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
5010 + }
5011 +}
5012 +
5013 +static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
5014 +{
5015 + if (AR_SREV_9287_11_OR_LATER(ah))
5016 + INIT_INI_ARRAY(&ah->iniModesRxGain,
5017 + ar9287Modes_rx_gain_9287_1_1,
5018 + ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
5019 + else if (AR_SREV_9287_10(ah))
5020 + INIT_INI_ARRAY(&ah->iniModesRxGain,
5021 + ar9287Modes_rx_gain_9287_1_0,
5022 + ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
5023 + else if (AR_SREV_9280_20(ah))
5024 + ar9280_20_hw_init_rxgain_ini(ah);
5025 +
5026 + if (AR_SREV_9287_11_OR_LATER(ah)) {
5027 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5028 + ar9287Modes_tx_gain_9287_1_1,
5029 + ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
5030 + } else if (AR_SREV_9287_10(ah)) {
5031 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5032 + ar9287Modes_tx_gain_9287_1_0,
5033 + ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
5034 + } else if (AR_SREV_9280_20(ah)) {
5035 + ar9280_20_hw_init_txgain_ini(ah);
5036 + } else if (AR_SREV_9285_12_OR_LATER(ah)) {
5037 + u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
5038 +
5039 + /* txgain table */
5040 + if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
5041 + if (AR_SREV_9285E_20(ah)) {
5042 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5043 + ar9285Modes_XE2_0_high_power,
5044 + ARRAY_SIZE(
5045 + ar9285Modes_XE2_0_high_power), 6);
5046 + } else {
5047 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5048 + ar9285Modes_high_power_tx_gain_9285_1_2,
5049 + ARRAY_SIZE(
5050 + ar9285Modes_high_power_tx_gain_9285_1_2), 6);
5051 + }
5052 + } else {
5053 + if (AR_SREV_9285E_20(ah)) {
5054 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5055 + ar9285Modes_XE2_0_normal_power,
5056 + ARRAY_SIZE(
5057 + ar9285Modes_XE2_0_normal_power), 6);
5058 + } else {
5059 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5060 + ar9285Modes_original_tx_gain_9285_1_2,
5061 + ARRAY_SIZE(
5062 + ar9285Modes_original_tx_gain_9285_1_2), 6);
5063 + }
5064 + }
5065 + }
5066 +}
5067 +
5068 +/*
5069 + * Helper for ASPM support.
5070 + *
5071 + * Disable PLL when in L0s as well as receiver clock when in L1.
5072 + * This power saving option must be enabled through the SerDes.
5073 + *
5074 + * Programming the SerDes must go through the same 288 bit serial shift
5075 + * register as the other analog registers. Hence the 9 writes.
5076 + */
5077 +static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
5078 + int restore,
5079 + int power_off)
5080 +{
5081 + u8 i;
5082 + u32 val;
5083 +
5084 + if (ah->is_pciexpress != true)
5085 + return;
5086 +
5087 + /* Do not touch SerDes registers */
5088 + if (ah->config.pcie_powersave_enable == 2)
5089 + return;
5090 +
5091 + /* Nothing to do on restore for 11N */
5092 + if (!restore) {
5093 + if (AR_SREV_9280_20_OR_LATER(ah)) {
5094 + /*
5095 + * AR9280 2.0 or later chips use SerDes values from the
5096 + * initvals.h initialized depending on chipset during
5097 + * __ath9k_hw_init()
5098 + */
5099 + for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
5100 + REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
5101 + INI_RA(&ah->iniPcieSerdes, i, 1));
5102 + }
5103 + } else if (AR_SREV_9280(ah) &&
5104 + (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
5105 + REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
5106 + REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
5107 +
5108 + /* RX shut off when elecidle is asserted */
5109 + REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
5110 + REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
5111 + REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
5112 +
5113 + /* Shut off CLKREQ active in L1 */
5114 + if (ah->config.pcie_clock_req)
5115 + REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
5116 + else
5117 + REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
5118 +
5119 + REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
5120 + REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
5121 + REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
5122 +
5123 + /* Load the new settings */
5124 + REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
5125 +
5126 + } else {
5127 + REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
5128 + REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
5129 +
5130 + /* RX shut off when elecidle is asserted */
5131 + REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
5132 + REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
5133 + REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
5134 +
5135 + /*
5136 + * Ignore ah->ah_config.pcie_clock_req setting for
5137 + * pre-AR9280 11n
5138 + */
5139 + REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
5140 +
5141 + REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
5142 + REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
5143 + REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
5144 +
5145 + /* Load the new settings */
5146 + REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
5147 + }
5148 +
5149 + udelay(1000);
5150 +
5151 + /* set bit 19 to allow forcing of pcie core into L1 state */
5152 + REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
5153 +
5154 + /* Several PCIe massages to ensure proper behaviour */
5155 + if (ah->config.pcie_waen) {
5156 + val = ah->config.pcie_waen;
5157 + if (!power_off)
5158 + val &= (~AR_WA_D3_L1_DISABLE);
5159 + } else {
5160 + if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
5161 + AR_SREV_9287(ah)) {
5162 + val = AR9285_WA_DEFAULT;
5163 + if (!power_off)
5164 + val &= (~AR_WA_D3_L1_DISABLE);
5165 + } else if (AR_SREV_9280(ah)) {
5166 + /*
5167 + * On AR9280 chips bit 22 of 0x4004 needs to be
5168 + * set otherwise card may disappear.
5169 + */
5170 + val = AR9280_WA_DEFAULT;
5171 + if (!power_off)
5172 + val &= (~AR_WA_D3_L1_DISABLE);
5173 + } else
5174 + val = AR_WA_DEFAULT;
5175 + }
5176 +
5177 + REG_WRITE(ah, AR_WA, val);
5178 + }
5179 +
5180 + if (power_off) {
5181 + /*
5182 + * Set PCIe workaround bits
5183 + * bit 14 in WA register (disable L1) should only
5184 + * be set when device enters D3 and be cleared
5185 + * when device comes back to D0.
5186 + */
5187 + if (ah->config.pcie_waen) {
5188 + if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
5189 + REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
5190 + } else {
5191 + if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
5192 + AR_SREV_9287(ah)) &&
5193 + (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
5194 + (AR_SREV_9280(ah) &&
5195 + (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
5196 + REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
5197 + }
5198 + }
5199 + }
5200 +}
5201 +
5202 +static void ar9002_hw_init_eeprom_fix(struct ath_hw *ah)
5203 +{
5204 + struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
5205 + struct ath_common *common = ath9k_hw_common(ah);
5206 +
5207 + ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
5208 + !AR_SREV_9285(ah) && !AR_SREV_9271(ah) &&
5209 + ((pBase->version & 0xff) > 0x0a) &&
5210 + (pBase->pwdclkind == 0);
5211 +
5212 + if (ah->need_an_top2_fixup)
5213 + ath_print(common, ATH_DBG_EEPROM,
5214 + "needs fixup for AR_AN_TOP2 register\n");
5215 +}
5216 +
5217 +
5218 +static int ar9002_hw_get_radiorev(struct ath_hw *ah)
5219 +{
5220 + u32 val;
5221 + int i;
5222 +
5223 + REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
5224 +
5225 + for (i = 0; i < 8; i++)
5226 + REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
5227 + val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
5228 + val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
5229 +
5230 + return ath9k_hw_reverse_bits(val, 8);
5231 +}
5232 +
5233 +int ar9002_hw_rf_claim(struct ath_hw *ah)
5234 +{
5235 + u32 val;
5236 +
5237 + REG_WRITE(ah, AR_PHY(0), 0x00000007);
5238 +
5239 + val = ar9002_hw_get_radiorev(ah);
5240 + switch (val & AR_RADIO_SREV_MAJOR) {
5241 + case 0:
5242 + val = AR_RAD5133_SREV_MAJOR;
5243 + break;
5244 + case AR_RAD5133_SREV_MAJOR:
5245 + case AR_RAD5122_SREV_MAJOR:
5246 + case AR_RAD2133_SREV_MAJOR:
5247 + case AR_RAD2122_SREV_MAJOR:
5248 + break;
5249 + default:
5250 + ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
5251 + "Radio Chip Rev 0x%02X not supported\n",
5252 + val & AR_RADIO_SREV_MAJOR);
5253 + return -EOPNOTSUPP;
5254 + }
5255 +
5256 + ah->hw_version.analog5GhzRev = val;
5257 +
5258 + return 0;
5259 +}
5260 +
5261 +/*
5262 + * Enable ASYNC FIFO
5263 + *
5264 + * If Async FIFO is enabled, the following counters change as MAC now runs
5265 + * at 117 Mhz instead of 88/44MHz when async FIFO is disabled.
5266 + *
5267 + * The values below tested for ht40 2 chain.
5268 + * Overwrite the delay/timeouts initialized in process ini.
5269 + */
5270 +void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
5271 +{
5272 + if (AR_SREV_9287_12_OR_LATER(ah)) {
5273 + REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
5274 + AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
5275 + REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
5276 + AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
5277 + REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
5278 + AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
5279 +
5280 + REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
5281 + REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
5282 +
5283 + REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
5284 + AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
5285 + REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
5286 + AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
5287 + }
5288 +}
5289 +
5290 +/*
5291 + * We don't enable WEP aggregation on mac80211 but we keep this
5292 + * around for HAL unification purposes.
5293 + */
5294 +void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
5295 +{
5296 + if (AR_SREV_9287_12_OR_LATER(ah)) {
5297 + REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
5298 + AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
5299 + }
5300 +}
5301 +
5302 +/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
5303 +void ar9002_hw_attach_ops(struct ath_hw *ah)
5304 +{
5305 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
5306 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
5307 +
5308 + priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
5309 + priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
5310 + priv_ops->macversion_supported = ar9002_hw_macversion_supported;
5311 +
5312 + ops->config_pci_powersave = ar9002_hw_configpcipowersave;
5313 +
5314 + ar5008_hw_attach_phy_ops(ah);
5315 + if (AR_SREV_9280_10_OR_LATER(ah))
5316 + ar9002_hw_attach_phy_ops(ah);
5317 +
5318 + ar9002_hw_attach_calib_ops(ah);
5319 + ar9002_hw_attach_mac_ops(ah);
5320 + ar9002_hw_init_eeprom_fix(ah);
5321 +}
5322 diff --git a/drivers/net/wireless/ath/ath9k/ar9002_initvals.h b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
5323 new file mode 100644
5324 index 0000000..a0711c7
5325 --- /dev/null
5326 +++ b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
5327 @@ -0,0 +1,7768 @@
5328 +/*
5329 + * Copyright (c) 2010 Atheros Communications Inc.
5330 + *
5331 + * Permission to use, copy, modify, and/or distribute this software for any
5332 + * purpose with or without fee is hereby granted, provided that the above
5333 + * copyright notice and this permission notice appear in all copies.
5334 + *
5335 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
5336 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
5337 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
5338 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
5339 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
5340 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
5341 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
5342 + */
5343 +
5344 +#ifndef INITVALS_9002_10_H
5345 +#define INITVALS_9002_10_H
5346 +
5347 +static const u32 ar9280Modes_9280[][6] = {
5348 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
5349 + 0x000001e0},
5350 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
5351 + 0x000001e0},
5352 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
5353 + 0x00001180},
5354 + {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000,
5355 + 0x00014008},
5356 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801080, 0x08400840,
5357 + 0x06e006e0},
5358 + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b,
5359 + 0x0988004f},
5360 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
5361 + 0x00000303},
5362 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
5363 + 0x02020200},
5364 + {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
5365 + 0x00000e0e},
5366 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
5367 + 0x0a020001},
5368 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
5369 + 0x00000e0e},
5370 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
5371 + 0x00000007},
5372 + {0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0,
5373 + 0x137216a0},
5374 + {0x00009848, 0x00028566, 0x00028566, 0x00028563, 0x00028563,
5375 + 0x00028563},
5376 + {0x0000a848, 0x00028566, 0x00028566, 0x00028563, 0x00028563,
5377 + 0x00028563},
5378 + {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2,
5379 + 0x6d4000e2},
5380 + {0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e,
5381 + 0x7ec82d2e},
5382 + {0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e,
5383 + 0x3139605e},
5384 + {0x00009860, 0x00049d18, 0x00049d18, 0x00049d20, 0x00049d20,
5385 + 0x00049d18},
5386 + {0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00,
5387 + 0x0001ce00},
5388 + {0x00009868, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190,
5389 + 0x5ac64190},
5390 + {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881,
5391 + 0x06903881},
5392 + {0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898,
5393 + 0x000007d0},
5394 + {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b,
5395 + 0x00000016},
5396 + {0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d,
5397 + 0xd00a8a0d},
5398 + {0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010,
5399 + 0xdfbc1010},
5400 + {0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010,
5401 + 0x00000010},
5402 + {0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010,
5403 + 0x00000010},
5404 + {0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210,
5405 + 0x00000210},
5406 + {0x0000c9b8, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a,
5407 + 0x0000001a},
5408 + {0x0000c9bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00,
5409 + 0x00000c00},
5410 + {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4,
5411 + 0x05eea6d4},
5412 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
5413 + 0x06336f77},
5414 + {0x000099c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c,
5415 + 0x60f6532c},
5416 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
5417 + 0x08f186c8},
5418 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
5419 + 0x00046384},
5420 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5421 + 0x00000000},
5422 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5423 + 0x00000000},
5424 + {0x00009a00, 0x00008184, 0x00008184, 0x00000214, 0x00000214,
5425 + 0x00000214},
5426 + {0x00009a04, 0x00008188, 0x00008188, 0x00000218, 0x00000218,
5427 + 0x00000218},
5428 + {0x00009a08, 0x0000818c, 0x0000818c, 0x00000224, 0x00000224,
5429 + 0x00000224},
5430 + {0x00009a0c, 0x00008190, 0x00008190, 0x00000228, 0x00000228,
5431 + 0x00000228},
5432 + {0x00009a10, 0x00008194, 0x00008194, 0x0000022c, 0x0000022c,
5433 + 0x0000022c},
5434 + {0x00009a14, 0x00008200, 0x00008200, 0x00000230, 0x00000230,
5435 + 0x00000230},
5436 + {0x00009a18, 0x00008204, 0x00008204, 0x000002a4, 0x000002a4,
5437 + 0x000002a4},
5438 + {0x00009a1c, 0x00008208, 0x00008208, 0x000002a8, 0x000002a8,
5439 + 0x000002a8},
5440 + {0x00009a20, 0x0000820c, 0x0000820c, 0x000002ac, 0x000002ac,
5441 + 0x000002ac},
5442 + {0x00009a24, 0x00008210, 0x00008210, 0x000002b0, 0x000002b0,
5443 + 0x000002b0},
5444 + {0x00009a28, 0x00008214, 0x00008214, 0x000002b4, 0x000002b4,
5445 + 0x000002b4},
5446 + {0x00009a2c, 0x00008280, 0x00008280, 0x000002b8, 0x000002b8,
5447 + 0x000002b8},
5448 + {0x00009a30, 0x00008284, 0x00008284, 0x00000390, 0x00000390,
5449 + 0x00000390},
5450 + {0x00009a34, 0x00008288, 0x00008288, 0x00000394, 0x00000394,
5451 + 0x00000394},
5452 + {0x00009a38, 0x0000828c, 0x0000828c, 0x00000398, 0x00000398,
5453 + 0x00000398},
5454 + {0x00009a3c, 0x00008290, 0x00008290, 0x00000334, 0x00000334,
5455 + 0x00000334},
5456 + {0x00009a40, 0x00008300, 0x00008300, 0x00000338, 0x00000338,
5457 + 0x00000338},
5458 + {0x00009a44, 0x00008304, 0x00008304, 0x000003ac, 0x000003ac,
5459 + 0x000003ac},
5460 + {0x00009a48, 0x00008308, 0x00008308, 0x000003b0, 0x000003b0,
5461 + 0x000003b0},
5462 + {0x00009a4c, 0x0000830c, 0x0000830c, 0x000003b4, 0x000003b4,
5463 + 0x000003b4},
5464 + {0x00009a50, 0x00008310, 0x00008310, 0x000003b8, 0x000003b8,
5465 + 0x000003b8},
5466 + {0x00009a54, 0x00008314, 0x00008314, 0x000003a5, 0x000003a5,
5467 + 0x000003a5},
5468 + {0x00009a58, 0x00008380, 0x00008380, 0x000003a9, 0x000003a9,
5469 + 0x000003a9},
5470 + {0x00009a5c, 0x00008384, 0x00008384, 0x000003ad, 0x000003ad,
5471 + 0x000003ad},
5472 + {0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194,
5473 + 0x00008194},
5474 + {0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0,
5475 + 0x000081a0},
5476 + {0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c,
5477 + 0x0000820c},
5478 + {0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8,
5479 + 0x000081a8},
5480 + {0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284,
5481 + 0x00008284},
5482 + {0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288,
5483 + 0x00008288},
5484 + {0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224,
5485 + 0x00008224},
5486 + {0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290,
5487 + 0x00008290},
5488 + {0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300,
5489 + 0x00008300},
5490 + {0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304,
5491 + 0x00008304},
5492 + {0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308,
5493 + 0x00008308},
5494 + {0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c,
5495 + 0x0000830c},
5496 + {0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380,
5497 + 0x00008380},
5498 + {0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384,
5499 + 0x00008384},
5500 + {0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700,
5501 + 0x00008700},
5502 + {0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704,
5503 + 0x00008704},
5504 + {0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708,
5505 + 0x00008708},
5506 + {0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c,
5507 + 0x0000870c},
5508 + {0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780,
5509 + 0x00008780},
5510 + {0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784,
5511 + 0x00008784},
5512 + {0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00,
5513 + 0x00008b00},
5514 + {0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04,
5515 + 0x00008b04},
5516 + {0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08,
5517 + 0x00008b08},
5518 + {0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c,
5519 + 0x00008b0c},
5520 + {0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80,
5521 + 0x00008b80},
5522 + {0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84,
5523 + 0x00008b84},
5524 + {0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88,
5525 + 0x00008b88},
5526 + {0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c,
5527 + 0x00008b8c},
5528 + {0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90,
5529 + 0x00008b90},
5530 + {0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80,
5531 + 0x00008f80},
5532 + {0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84,
5533 + 0x00008f84},
5534 + {0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88,
5535 + 0x00008f88},
5536 + {0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c,
5537 + 0x00008f8c},
5538 + {0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90,
5539 + 0x00008f90},
5540 + {0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c,
5541 + 0x0000930c},
5542 + {0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310,
5543 + 0x00009310},
5544 + {0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384,
5545 + 0x00009384},
5546 + {0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388,
5547 + 0x00009388},
5548 + {0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324,
5549 + 0x00009324},
5550 + {0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704,
5551 + 0x00009704},
5552 + {0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4,
5553 + 0x000096a4},
5554 + {0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8,
5555 + 0x000096a8},
5556 + {0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710,
5557 + 0x00009710},
5558 + {0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714,
5559 + 0x00009714},
5560 + {0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720,
5561 + 0x00009720},
5562 + {0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724,
5563 + 0x00009724},
5564 + {0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728,
5565 + 0x00009728},
5566 + {0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c,
5567 + 0x0000972c},
5568 + {0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0,
5569 + 0x000097a0},
5570 + {0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4,
5571 + 0x000097a4},
5572 + {0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8,
5573 + 0x000097a8},
5574 + {0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0,
5575 + 0x000097b0},
5576 + {0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4,
5577 + 0x000097b4},
5578 + {0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8,
5579 + 0x000097b8},
5580 + {0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5,
5581 + 0x000097a5},
5582 + {0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9,
5583 + 0x000097a9},
5584 + {0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad,
5585 + 0x000097ad},
5586 + {0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1,
5587 + 0x000097b1},
5588 + {0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5,
5589 + 0x000097b5},
5590 + {0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9,
5591 + 0x000097b9},
5592 + {0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5,
5593 + 0x000097c5},
5594 + {0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9,
5595 + 0x000097c9},
5596 + {0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1,
5597 + 0x000097d1},
5598 + {0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5,
5599 + 0x000097d5},
5600 + {0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9,
5601 + 0x000097d9},
5602 + {0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6,
5603 + 0x000097c6},
5604 + {0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca,
5605 + 0x000097ca},
5606 + {0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce,
5607 + 0x000097ce},
5608 + {0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2,
5609 + 0x000097d2},
5610 + {0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6,
5611 + 0x000097d6},
5612 + {0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3,
5613 + 0x000097c3},
5614 + {0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7,
5615 + 0x000097c7},
5616 + {0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb,
5617 + 0x000097cb},
5618 + {0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf,
5619 + 0x000097cf},
5620 + {0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7,
5621 + 0x000097d7},
5622 + {0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db,
5623 + 0x000097db},
5624 + {0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db,
5625 + 0x000097db},
5626 + {0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db,
5627 + 0x000097db},
5628 + {0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5629 + 0x000097db},
5630 + {0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5631 + 0x000097db},
5632 + {0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5633 + 0x000097db},
5634 + {0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5635 + 0x000097db},
5636 + {0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5637 + 0x000097db},
5638 + {0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5639 + 0x000097db},
5640 + {0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5641 + 0x000097db},
5642 + {0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5643 + 0x000097db},
5644 + {0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5645 + 0x000097db},
5646 + {0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5647 + 0x000097db},
5648 + {0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5649 + 0x000097db},
5650 + {0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5651 + 0x000097db},
5652 + {0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5653 + 0x000097db},
5654 + {0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5655 + 0x000097db},
5656 + {0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5657 + 0x000097db},
5658 + {0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5659 + 0x000097db},
5660 + {0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5661 + 0x000097db},
5662 + {0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5663 + 0x000097db},
5664 + {0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5665 + 0x000097db},
5666 + {0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5667 + 0x000097db},
5668 + {0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5669 + 0x000097db},
5670 + {0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5671 + 0x000097db},
5672 + {0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5673 + 0x000097db},
5674 + {0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5675 + 0x000097db},
5676 + {0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5677 + 0x000097db},
5678 + {0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5679 + 0x000097db},
5680 + {0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444,
5681 + 0x00000444},
5682 + {0x0000a208, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788,
5683 + 0x803e4788},
5684 + {0x0000a20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019,
5685 + 0x000c6019},
5686 + {0x0000b20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019,
5687 + 0x000c6019},
5688 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
5689 + 0x1883800a},
5690 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
5691 + 0x00000000},
5692 + {0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652,
5693 + 0x0a1aa652},
5694 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5695 + 0x00000000},
5696 + {0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002,
5697 + 0x00003002},
5698 + {0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009,
5699 + 0x00008009},
5700 + {0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b,
5701 + 0x0000b00b},
5702 + {0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012,
5703 + 0x0000e012},
5704 + {0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048,
5705 + 0x00012048},
5706 + {0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a,
5707 + 0x0001604a},
5708 + {0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211,
5709 + 0x0001a211},
5710 + {0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213,
5711 + 0x0001e213},
5712 + {0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b,
5713 + 0x0002121b},
5714 + {0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412,
5715 + 0x00024412},
5716 + {0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414,
5717 + 0x00028414},
5718 + {0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a,
5719 + 0x0002b44a},
5720 + {0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649,
5721 + 0x00030649},
5722 + {0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b,
5723 + 0x0003364b},
5724 + {0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49,
5725 + 0x00038a49},
5726 + {0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48,
5727 + 0x0003be48},
5728 + {0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a,
5729 + 0x0003ee4a},
5730 + {0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88,
5731 + 0x00042e88},
5732 + {0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a,
5733 + 0x00046e8a},
5734 + {0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9,
5735 + 0x00049ec9},
5736 + {0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42,
5737 + 0x0004bf42},
5738 + {0x0000784c, 0x0e4f048c, 0x0e4f048c, 0x0e4d048c, 0x0e4d048c,
5739 + 0x0e4d048c},
5740 + {0x00007854, 0x12031828, 0x12031828, 0x12035828, 0x12035828,
5741 + 0x12035828},
5742 + {0x00007870, 0x807ec400, 0x807ec400, 0x807ec000, 0x807ec000,
5743 + 0x807ec000},
5744 + {0x0000788c, 0x00010000, 0x00010000, 0x00110000, 0x00110000,
5745 + 0x00110000},
5746 +};
5747 +
5748 +static const u32 ar9280Common_9280[][2] = {
5749 + {0x0000000c, 0x00000000},
5750 + {0x00000030, 0x00020015},
5751 + {0x00000034, 0x00000005},
5752 + {0x00000040, 0x00000000},
5753 + {0x00000044, 0x00000008},
5754 + {0x00000048, 0x00000008},
5755 + {0x0000004c, 0x00000010},
5756 + {0x00000050, 0x00000000},
5757 + {0x00000054, 0x0000001f},
5758 + {0x00000800, 0x00000000},
5759 + {0x00000804, 0x00000000},
5760 + {0x00000808, 0x00000000},
5761 + {0x0000080c, 0x00000000},
5762 + {0x00000810, 0x00000000},
5763 + {0x00000814, 0x00000000},
5764 + {0x00000818, 0x00000000},
5765 + {0x0000081c, 0x00000000},
5766 + {0x00000820, 0x00000000},
5767 + {0x00000824, 0x00000000},
5768 + {0x00001040, 0x002ffc0f},
5769 + {0x00001044, 0x002ffc0f},
5770 + {0x00001048, 0x002ffc0f},
5771 + {0x0000104c, 0x002ffc0f},
5772 + {0x00001050, 0x002ffc0f},
5773 + {0x00001054, 0x002ffc0f},
5774 + {0x00001058, 0x002ffc0f},
5775 + {0x0000105c, 0x002ffc0f},
5776 + {0x00001060, 0x002ffc0f},
5777 + {0x00001064, 0x002ffc0f},
5778 + {0x00001230, 0x00000000},
5779 + {0x00001270, 0x00000000},
5780 + {0x00001038, 0x00000000},
5781 + {0x00001078, 0x00000000},
5782 + {0x000010b8, 0x00000000},
5783 + {0x000010f8, 0x00000000},
5784 + {0x00001138, 0x00000000},
5785 + {0x00001178, 0x00000000},
5786 + {0x000011b8, 0x00000000},
5787 + {0x000011f8, 0x00000000},
5788 + {0x00001238, 0x00000000},
5789 + {0x00001278, 0x00000000},
5790 + {0x000012b8, 0x00000000},
5791 + {0x000012f8, 0x00000000},
5792 + {0x00001338, 0x00000000},
5793 + {0x00001378, 0x00000000},
5794 + {0x000013b8, 0x00000000},
5795 + {0x000013f8, 0x00000000},
5796 + {0x00001438, 0x00000000},
5797 + {0x00001478, 0x00000000},
5798 + {0x000014b8, 0x00000000},
5799 + {0x000014f8, 0x00000000},
5800 + {0x00001538, 0x00000000},
5801 + {0x00001578, 0x00000000},
5802 + {0x000015b8, 0x00000000},
5803 + {0x000015f8, 0x00000000},
5804 + {0x00001638, 0x00000000},
5805 + {0x00001678, 0x00000000},
5806 + {0x000016b8, 0x00000000},
5807 + {0x000016f8, 0x00000000},
5808 + {0x00001738, 0x00000000},
5809 + {0x00001778, 0x00000000},
5810 + {0x000017b8, 0x00000000},
5811 + {0x000017f8, 0x00000000},
5812 + {0x0000103c, 0x00000000},
5813 + {0x0000107c, 0x00000000},
5814 + {0x000010bc, 0x00000000},
5815 + {0x000010fc, 0x00000000},
5816 + {0x0000113c, 0x00000000},
5817 + {0x0000117c, 0x00000000},
5818 + {0x000011bc, 0x00000000},
5819 + {0x000011fc, 0x00000000},
5820 + {0x0000123c, 0x00000000},
5821 + {0x0000127c, 0x00000000},
5822 + {0x000012bc, 0x00000000},
5823 + {0x000012fc, 0x00000000},
5824 + {0x0000133c, 0x00000000},
5825 + {0x0000137c, 0x00000000},
5826 + {0x000013bc, 0x00000000},
5827 + {0x000013fc, 0x00000000},
5828 + {0x0000143c, 0x00000000},
5829 + {0x0000147c, 0x00000000},
5830 + {0x00004030, 0x00000002},
5831 + {0x0000403c, 0x00000002},
5832 + {0x00004024, 0x0000001f},
5833 + {0x00007010, 0x00000033},
5834 + {0x00007038, 0x000004c2},
5835 + {0x00008004, 0x00000000},
5836 + {0x00008008, 0x00000000},
5837 + {0x0000800c, 0x00000000},
5838 + {0x00008018, 0x00000700},
5839 + {0x00008020, 0x00000000},
5840 + {0x00008038, 0x00000000},
5841 + {0x0000803c, 0x00000000},
5842 + {0x00008048, 0x40000000},
5843 + {0x00008054, 0x00000000},
5844 + {0x00008058, 0x00000000},
5845 + {0x0000805c, 0x000fc78f},
5846 + {0x00008060, 0x0000000f},
5847 + {0x00008064, 0x00000000},
5848 + {0x00008070, 0x00000000},
5849 + {0x000080c0, 0x2a82301a},
5850 + {0x000080c4, 0x05dc01e0},
5851 + {0x000080c8, 0x1f402710},
5852 + {0x000080cc, 0x01f40000},
5853 + {0x000080d0, 0x00001e00},
5854 + {0x000080d4, 0x00000000},
5855 + {0x000080d8, 0x00400000},
5856 + {0x000080e0, 0xffffffff},
5857 + {0x000080e4, 0x0000ffff},
5858 + {0x000080e8, 0x003f3f3f},
5859 + {0x000080ec, 0x00000000},
5860 + {0x000080f0, 0x00000000},
5861 + {0x000080f4, 0x00000000},
5862 + {0x000080f8, 0x00000000},
5863 + {0x000080fc, 0x00020000},
5864 + {0x00008100, 0x00020000},
5865 + {0x00008104, 0x00000001},
5866 + {0x00008108, 0x00000052},
5867 + {0x0000810c, 0x00000000},
5868 + {0x00008110, 0x00000168},
5869 + {0x00008118, 0x000100aa},
5870 + {0x0000811c, 0x00003210},
5871 + {0x00008120, 0x08f04800},
5872 + {0x00008124, 0x00000000},
5873 + {0x00008128, 0x00000000},
5874 + {0x0000812c, 0x00000000},
5875 + {0x00008130, 0x00000000},
5876 + {0x00008134, 0x00000000},
5877 + {0x00008138, 0x00000000},
5878 + {0x0000813c, 0x00000000},
5879 + {0x00008144, 0x00000000},
5880 + {0x00008168, 0x00000000},
5881 + {0x0000816c, 0x00000000},
5882 + {0x00008170, 0x32143320},
5883 + {0x00008174, 0xfaa4fa50},
5884 + {0x00008178, 0x00000100},
5885 + {0x0000817c, 0x00000000},
5886 + {0x000081c4, 0x00000000},
5887 + {0x000081d0, 0x00003210},
5888 + {0x000081ec, 0x00000000},
5889 + {0x000081f0, 0x00000000},
5890 + {0x000081f4, 0x00000000},
5891 + {0x000081f8, 0x00000000},
5892 + {0x000081fc, 0x00000000},
5893 + {0x00008200, 0x00000000},
5894 + {0x00008204, 0x00000000},
5895 + {0x00008208, 0x00000000},
5896 + {0x0000820c, 0x00000000},
5897 + {0x00008210, 0x00000000},
5898 + {0x00008214, 0x00000000},
5899 + {0x00008218, 0x00000000},
5900 + {0x0000821c, 0x00000000},
5901 + {0x00008220, 0x00000000},
5902 + {0x00008224, 0x00000000},
5903 + {0x00008228, 0x00000000},
5904 + {0x0000822c, 0x00000000},
5905 + {0x00008230, 0x00000000},
5906 + {0x00008234, 0x00000000},
5907 + {0x00008238, 0x00000000},
5908 + {0x0000823c, 0x00000000},
5909 + {0x00008240, 0x00100000},
5910 + {0x00008244, 0x0010f400},
5911 + {0x00008248, 0x00000100},
5912 + {0x0000824c, 0x0001e800},
5913 + {0x00008250, 0x00000000},
5914 + {0x00008254, 0x00000000},
5915 + {0x00008258, 0x00000000},
5916 + {0x0000825c, 0x400000ff},
5917 + {0x00008260, 0x00080922},
5918 + {0x00008270, 0x00000000},
5919 + {0x00008274, 0x40000000},
5920 + {0x00008278, 0x003e4180},
5921 + {0x0000827c, 0x00000000},
5922 + {0x00008284, 0x0000002c},
5923 + {0x00008288, 0x0000002c},
5924 + {0x0000828c, 0x00000000},
5925 + {0x00008294, 0x00000000},
5926 + {0x00008298, 0x00000000},
5927 + {0x00008300, 0x00000000},
5928 + {0x00008304, 0x00000000},
5929 + {0x00008308, 0x00000000},
5930 + {0x0000830c, 0x00000000},
5931 + {0x00008310, 0x00000000},
5932 + {0x00008314, 0x00000000},
5933 + {0x00008318, 0x00000000},
5934 + {0x00008328, 0x00000000},
5935 + {0x0000832c, 0x00000007},
5936 + {0x00008330, 0x00000302},
5937 + {0x00008334, 0x00000e00},
5938 + {0x00008338, 0x00000000},
5939 + {0x0000833c, 0x00000000},
5940 + {0x00008340, 0x000107ff},
5941 + {0x00008344, 0x00000000},
5942 + {0x00009808, 0x00000000},
5943 + {0x0000980c, 0xaf268e30},
5944 + {0x00009810, 0xfd14e000},
5945 + {0x00009814, 0x9c0a9f6b},
5946 + {0x0000981c, 0x00000000},
5947 + {0x0000982c, 0x0000a000},
5948 + {0x00009830, 0x00000000},
5949 + {0x0000983c, 0x00200400},
5950 + {0x00009840, 0x206a01ae},
5951 + {0x0000984c, 0x0040233c},
5952 + {0x0000a84c, 0x0040233c},
5953 + {0x00009854, 0x00000044},
5954 + {0x00009900, 0x00000000},
5955 + {0x00009904, 0x00000000},
5956 + {0x00009908, 0x00000000},
5957 + {0x0000990c, 0x00000000},
5958 + {0x0000991c, 0x10000fff},
5959 + {0x00009920, 0x04900000},
5960 + {0x0000a920, 0x04900000},
5961 + {0x00009928, 0x00000001},
5962 + {0x0000992c, 0x00000004},
5963 + {0x00009934, 0x1e1f2022},
5964 + {0x00009938, 0x0a0b0c0d},
5965 + {0x0000993c, 0x00000000},
5966 + {0x00009948, 0x9280c00a},
5967 + {0x0000994c, 0x00020028},
5968 + {0x00009954, 0xe250a51e},
5969 + {0x00009958, 0x3388ffff},
5970 + {0x00009940, 0x00781204},
5971 + {0x0000c95c, 0x004b6a8e},
5972 + {0x0000c968, 0x000003ce},
5973 + {0x00009970, 0x190fb514},
5974 + {0x00009974, 0x00000000},
5975 + {0x00009978, 0x00000001},
5976 + {0x0000997c, 0x00000000},
5977 + {0x00009980, 0x00000000},
5978 + {0x00009984, 0x00000000},
5979 + {0x00009988, 0x00000000},
5980 + {0x0000998c, 0x00000000},
5981 + {0x00009990, 0x00000000},
5982 + {0x00009994, 0x00000000},
5983 + {0x00009998, 0x00000000},
5984 + {0x0000999c, 0x00000000},
5985 + {0x000099a0, 0x00000000},
5986 + {0x000099a4, 0x00000001},
5987 + {0x000099a8, 0x201fff00},
5988 + {0x000099ac, 0x006f00c4},
5989 + {0x000099b0, 0x03051000},
5990 + {0x000099b4, 0x00000820},
5991 + {0x000099dc, 0x00000000},
5992 + {0x000099e0, 0x00000000},
5993 + {0x000099e4, 0xaaaaaaaa},
5994 + {0x000099e8, 0x3c466478},
5995 + {0x000099ec, 0x0cc80caa},
5996 + {0x000099fc, 0x00001042},
5997 + {0x0000a210, 0x4080a333},
5998 + {0x0000a214, 0x40206c10},
5999 + {0x0000a218, 0x009c4060},
6000 + {0x0000a220, 0x01834061},
6001 + {0x0000a224, 0x00000400},
6002 + {0x0000a228, 0x000003b5},
6003 + {0x0000a22c, 0x23277200},
6004 + {0x0000a234, 0x20202020},
6005 + {0x0000a238, 0x20202020},
6006 + {0x0000a23c, 0x13c889af},
6007 + {0x0000a240, 0x38490a20},
6008 + {0x0000a244, 0x00007bb6},
6009 + {0x0000a248, 0x0fff3ffc},
6010 + {0x0000a24c, 0x00000001},
6011 + {0x0000a250, 0x001da000},
6012 + {0x0000a254, 0x00000000},
6013 + {0x0000a258, 0x0cdbd380},
6014 + {0x0000a25c, 0x0f0f0f01},
6015 + {0x0000a260, 0xdfa91f01},
6016 + {0x0000a268, 0x00000000},
6017 + {0x0000a26c, 0x0ebae9c6},
6018 + {0x0000b26c, 0x0ebae9c6},
6019 + {0x0000d270, 0x00820820},
6020 + {0x0000a278, 0x1ce739ce},
6021 + {0x0000a27c, 0x050701ce},
6022 + {0x0000a358, 0x7999aa0f},
6023 + {0x0000d35c, 0x07ffffef},
6024 + {0x0000d360, 0x0fffffe7},
6025 + {0x0000d364, 0x17ffffe5},
6026 + {0x0000d368, 0x1fffffe4},
6027 + {0x0000d36c, 0x37ffffe3},
6028 + {0x0000d370, 0x3fffffe3},
6029 + {0x0000d374, 0x57ffffe3},
6030 + {0x0000d378, 0x5fffffe2},
6031 + {0x0000d37c, 0x7fffffe2},
6032 + {0x0000d380, 0x7f3c7bba},
6033 + {0x0000d384, 0xf3307ff0},
6034 + {0x0000a388, 0x0c000000},
6035 + {0x0000a38c, 0x20202020},
6036 + {0x0000a390, 0x20202020},
6037 + {0x0000a394, 0x1ce739ce},
6038 + {0x0000a398, 0x000001ce},
6039 + {0x0000a39c, 0x00000001},
6040 + {0x0000a3a0, 0x00000000},
6041 + {0x0000a3a4, 0x00000000},
6042 + {0x0000a3a8, 0x00000000},
6043 + {0x0000a3ac, 0x00000000},
6044 + {0x0000a3b0, 0x00000000},
6045 + {0x0000a3b4, 0x00000000},
6046 + {0x0000a3b8, 0x00000000},
6047 + {0x0000a3bc, 0x00000000},
6048 + {0x0000a3c0, 0x00000000},
6049 + {0x0000a3c4, 0x00000000},
6050 + {0x0000a3c8, 0x00000246},
6051 + {0x0000a3cc, 0x20202020},
6052 + {0x0000a3d0, 0x20202020},
6053 + {0x0000a3d4, 0x20202020},
6054 + {0x0000a3dc, 0x1ce739ce},
6055 + {0x0000a3e0, 0x000001ce},
6056 + {0x0000a3e4, 0x00000000},
6057 + {0x0000a3e8, 0x18c43433},
6058 + {0x0000a3ec, 0x00f38081},
6059 + {0x00007800, 0x00040000},
6060 + {0x00007804, 0xdb005012},
6061 + {0x00007808, 0x04924914},
6062 + {0x0000780c, 0x21084210},
6063 + {0x00007810, 0x6d801300},
6064 + {0x00007814, 0x0019beff},
6065 + {0x00007818, 0x07e40000},
6066 + {0x0000781c, 0x00492000},
6067 + {0x00007820, 0x92492480},
6068 + {0x00007824, 0x00040000},
6069 + {0x00007828, 0xdb005012},
6070 + {0x0000782c, 0x04924914},
6071 + {0x00007830, 0x21084210},
6072 + {0x00007834, 0x6d801300},
6073 + {0x00007838, 0x0019beff},
6074 + {0x0000783c, 0x07e40000},
6075 + {0x00007840, 0x00492000},
6076 + {0x00007844, 0x92492480},
6077 + {0x00007848, 0x00120000},
6078 + {0x00007850, 0x54214514},
6079 + {0x00007858, 0x92592692},
6080 + {0x00007860, 0x52802000},
6081 + {0x00007864, 0x0a8e370e},
6082 + {0x00007868, 0xc0102850},
6083 + {0x0000786c, 0x812d4000},
6084 + {0x00007874, 0x001b6db0},
6085 + {0x00007878, 0x00376b63},
6086 + {0x0000787c, 0x06db6db6},
6087 + {0x00007880, 0x006d8000},
6088 + {0x00007884, 0xffeffffe},
6089 + {0x00007888, 0xffeffffe},
6090 + {0x00007890, 0x00060aeb},
6091 + {0x00007894, 0x5a108000},
6092 + {0x00007898, 0x2a850160},
6093 +};
6094 +
6095 +/* XXX 9280 2 */
6096 +static const u32 ar9280Modes_9280_2[][6] = {
6097 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
6098 + 0x000001e0},
6099 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
6100 + 0x000001e0},
6101 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
6102 + 0x00001180},
6103 + {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6104 + 0x00000008},
6105 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00,
6106 + 0x06e006e0},
6107 + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b,
6108 + 0x0988004f},
6109 + {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810,
6110 + 0x08f04810},
6111 + {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a,
6112 + 0x0000320a},
6113 + {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440,
6114 + 0x00006880},
6115 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
6116 + 0x00000303},
6117 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
6118 + 0x02020200},
6119 + {0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e,
6120 + 0x01000e0e},
6121 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
6122 + 0x0a020001},
6123 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
6124 + 0x00000e0e},
6125 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
6126 + 0x00000007},
6127 + {0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e,
6128 + 0x206a012e},
6129 + {0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0,
6130 + 0x037216a0},
6131 + {0x00009850, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2,
6132 + 0x6c4000e2},
6133 + {0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e,
6134 + 0x7ec84d2e},
6135 + {0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e,
6136 + 0x31395d5e},
6137 + {0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20,
6138 + 0x00048d18},
6139 + {0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00,
6140 + 0x0001ce00},
6141 + {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0,
6142 + 0x5ac640d0},
6143 + {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881,
6144 + 0x06903881},
6145 + {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898,
6146 + 0x000007d0},
6147 + {0x00009918, 0x0000000a, 0x00000014, 0x00000268, 0x0000000b,
6148 + 0x00000016},
6149 + {0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d,
6150 + 0xd00a8a0d},
6151 + {0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010,
6152 + 0xffbc1010},
6153 + {0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010,
6154 + 0x00000010},
6155 + {0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010,
6156 + 0x00000010},
6157 + {0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210,
6158 + 0x00000210},
6159 + {0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce,
6160 + 0x000003ce},
6161 + {0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c,
6162 + 0x0000001c},
6163 + {0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00,
6164 + 0x00000c00},
6165 + {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4,
6166 + 0x05eea6d4},
6167 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
6168 + 0x06336f77},
6169 + {0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329,
6170 + 0x60f65329},
6171 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
6172 + 0x08f186c8},
6173 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
6174 + 0x00046384},
6175 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6176 + 0x00000000},
6177 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6178 + 0x00000000},
6179 + {0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444,
6180 + 0x00000444},
6181 + {0x0000a20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019,
6182 + 0x0001f019},
6183 + {0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019,
6184 + 0x0001f019},
6185 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
6186 + 0x1883800a},
6187 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
6188 + 0x00000000},
6189 + {0x0000a23c, 0x13c88000, 0x13c88000, 0x13c88001, 0x13c88000,
6190 + 0x13c88000},
6191 + {0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000,
6192 + 0x0004a000},
6193 + {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e,
6194 + 0x7999aa0e},
6195 + {0x0000a388, 0x0c000000, 0x0c000000, 0x08000000, 0x0c000000,
6196 + 0x0c000000},
6197 + {0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6198 + 0x00000000},
6199 + {0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000,
6200 + 0x5a508000},
6201 +};
6202 +
6203 +static const u32 ar9280Common_9280_2[][2] = {
6204 + {0x0000000c, 0x00000000},
6205 + {0x00000030, 0x00020015},
6206 + {0x00000034, 0x00000005},
6207 + {0x00000040, 0x00000000},
6208 + {0x00000044, 0x00000008},
6209 + {0x00000048, 0x00000008},
6210 + {0x0000004c, 0x00000010},
6211 + {0x00000050, 0x00000000},
6212 + {0x00000054, 0x0000001f},
6213 + {0x00000800, 0x00000000},
6214 + {0x00000804, 0x00000000},
6215 + {0x00000808, 0x00000000},
6216 + {0x0000080c, 0x00000000},
6217 + {0x00000810, 0x00000000},
6218 + {0x00000814, 0x00000000},
6219 + {0x00000818, 0x00000000},
6220 + {0x0000081c, 0x00000000},
6221 + {0x00000820, 0x00000000},
6222 + {0x00000824, 0x00000000},
6223 + {0x00001040, 0x002ffc0f},
6224 + {0x00001044, 0x002ffc0f},
6225 + {0x00001048, 0x002ffc0f},
6226 + {0x0000104c, 0x002ffc0f},
6227 + {0x00001050, 0x002ffc0f},
6228 + {0x00001054, 0x002ffc0f},
6229 + {0x00001058, 0x002ffc0f},
6230 + {0x0000105c, 0x002ffc0f},
6231 + {0x00001060, 0x002ffc0f},
6232 + {0x00001064, 0x002ffc0f},
6233 + {0x00001230, 0x00000000},
6234 + {0x00001270, 0x00000000},
6235 + {0x00001038, 0x00000000},
6236 + {0x00001078, 0x00000000},
6237 + {0x000010b8, 0x00000000},
6238 + {0x000010f8, 0x00000000},
6239 + {0x00001138, 0x00000000},
6240 + {0x00001178, 0x00000000},
6241 + {0x000011b8, 0x00000000},
6242 + {0x000011f8, 0x00000000},
6243 + {0x00001238, 0x00000000},
6244 + {0x00001278, 0x00000000},
6245 + {0x000012b8, 0x00000000},
6246 + {0x000012f8, 0x00000000},
6247 + {0x00001338, 0x00000000},
6248 + {0x00001378, 0x00000000},
6249 + {0x000013b8, 0x00000000},
6250 + {0x000013f8, 0x00000000},
6251 + {0x00001438, 0x00000000},
6252 + {0x00001478, 0x00000000},
6253 + {0x000014b8, 0x00000000},
6254 + {0x000014f8, 0x00000000},
6255 + {0x00001538, 0x00000000},
6256 + {0x00001578, 0x00000000},
6257 + {0x000015b8, 0x00000000},
6258 + {0x000015f8, 0x00000000},
6259 + {0x00001638, 0x00000000},
6260 + {0x00001678, 0x00000000},
6261 + {0x000016b8, 0x00000000},
6262 + {0x000016f8, 0x00000000},
6263 + {0x00001738, 0x00000000},
6264 + {0x00001778, 0x00000000},
6265 + {0x000017b8, 0x00000000},
6266 + {0x000017f8, 0x00000000},
6267 + {0x0000103c, 0x00000000},
6268 + {0x0000107c, 0x00000000},
6269 + {0x000010bc, 0x00000000},
6270 + {0x000010fc, 0x00000000},
6271 + {0x0000113c, 0x00000000},
6272 + {0x0000117c, 0x00000000},
6273 + {0x000011bc, 0x00000000},
6274 + {0x000011fc, 0x00000000},
6275 + {0x0000123c, 0x00000000},
6276 + {0x0000127c, 0x00000000},
6277 + {0x000012bc, 0x00000000},
6278 + {0x000012fc, 0x00000000},
6279 + {0x0000133c, 0x00000000},
6280 + {0x0000137c, 0x00000000},
6281 + {0x000013bc, 0x00000000},
6282 + {0x000013fc, 0x00000000},
6283 + {0x0000143c, 0x00000000},
6284 + {0x0000147c, 0x00000000},
6285 + {0x00004030, 0x00000002},
6286 + {0x0000403c, 0x00000002},
6287 + {0x00004024, 0x0000001f},
6288 + {0x00004060, 0x00000000},
6289 + {0x00004064, 0x00000000},
6290 + {0x00007010, 0x00000033},
6291 + {0x00007034, 0x00000002},
6292 + {0x00007038, 0x000004c2},
6293 + {0x00008004, 0x00000000},
6294 + {0x00008008, 0x00000000},
6295 + {0x0000800c, 0x00000000},
6296 + {0x00008018, 0x00000700},
6297 + {0x00008020, 0x00000000},
6298 + {0x00008038, 0x00000000},
6299 + {0x0000803c, 0x00000000},
6300 + {0x00008048, 0x40000000},
6301 + {0x00008054, 0x00000000},
6302 + {0x00008058, 0x00000000},
6303 + {0x0000805c, 0x000fc78f},
6304 + {0x00008060, 0x0000000f},
6305 + {0x00008064, 0x00000000},
6306 + {0x00008070, 0x00000000},
6307 + {0x000080c0, 0x2a80001a},
6308 + {0x000080c4, 0x05dc01e0},
6309 + {0x000080c8, 0x1f402710},
6310 + {0x000080cc, 0x01f40000},
6311 + {0x000080d0, 0x00001e00},
6312 + {0x000080d4, 0x00000000},
6313 + {0x000080d8, 0x00400000},
6314 + {0x000080e0, 0xffffffff},
6315 + {0x000080e4, 0x0000ffff},
6316 + {0x000080e8, 0x003f3f3f},
6317 + {0x000080ec, 0x00000000},
6318 + {0x000080f0, 0x00000000},
6319 + {0x000080f4, 0x00000000},
6320 + {0x000080f8, 0x00000000},
6321 + {0x000080fc, 0x00020000},
6322 + {0x00008100, 0x00020000},
6323 + {0x00008104, 0x00000001},
6324 + {0x00008108, 0x00000052},
6325 + {0x0000810c, 0x00000000},
6326 + {0x00008110, 0x00000168},
6327 + {0x00008118, 0x000100aa},
6328 + {0x0000811c, 0x00003210},
6329 + {0x00008124, 0x00000000},
6330 + {0x00008128, 0x00000000},
6331 + {0x0000812c, 0x00000000},
6332 + {0x00008130, 0x00000000},
6333 + {0x00008134, 0x00000000},
6334 + {0x00008138, 0x00000000},
6335 + {0x0000813c, 0x00000000},
6336 + {0x00008144, 0xffffffff},
6337 + {0x00008168, 0x00000000},
6338 + {0x0000816c, 0x00000000},
6339 + {0x00008170, 0x32143320},
6340 + {0x00008174, 0xfaa4fa50},
6341 + {0x00008178, 0x00000100},
6342 + {0x0000817c, 0x00000000},
6343 + {0x000081c0, 0x00000000},
6344 + {0x000081ec, 0x00000000},
6345 + {0x000081f0, 0x00000000},
6346 + {0x000081f4, 0x00000000},
6347 + {0x000081f8, 0x00000000},
6348 + {0x000081fc, 0x00000000},
6349 + {0x00008200, 0x00000000},
6350 + {0x00008204, 0x00000000},
6351 + {0x00008208, 0x00000000},
6352 + {0x0000820c, 0x00000000},
6353 + {0x00008210, 0x00000000},
6354 + {0x00008214, 0x00000000},
6355 + {0x00008218, 0x00000000},
6356 + {0x0000821c, 0x00000000},
6357 + {0x00008220, 0x00000000},
6358 + {0x00008224, 0x00000000},
6359 + {0x00008228, 0x00000000},
6360 + {0x0000822c, 0x00000000},
6361 + {0x00008230, 0x00000000},
6362 + {0x00008234, 0x00000000},
6363 + {0x00008238, 0x00000000},
6364 + {0x0000823c, 0x00000000},
6365 + {0x00008240, 0x00100000},
6366 + {0x00008244, 0x0010f400},
6367 + {0x00008248, 0x00000100},
6368 + {0x0000824c, 0x0001e800},
6369 + {0x00008250, 0x00000000},
6370 + {0x00008254, 0x00000000},
6371 + {0x00008258, 0x00000000},
6372 + {0x0000825c, 0x400000ff},
6373 + {0x00008260, 0x00080922},
6374 + {0x00008264, 0xa8a00010},
6375 + {0x00008270, 0x00000000},
6376 + {0x00008274, 0x40000000},
6377 + {0x00008278, 0x003e4180},
6378 + {0x0000827c, 0x00000000},
6379 + {0x00008284, 0x0000002c},
6380 + {0x00008288, 0x0000002c},
6381 + {0x0000828c, 0x00000000},
6382 + {0x00008294, 0x00000000},
6383 + {0x00008298, 0x00000000},
6384 + {0x0000829c, 0x00000000},
6385 + {0x00008300, 0x00000040},
6386 + {0x00008314, 0x00000000},
6387 + {0x00008328, 0x00000000},
6388 + {0x0000832c, 0x00000007},
6389 + {0x00008330, 0x00000302},
6390 + {0x00008334, 0x00000e00},
6391 + {0x00008338, 0x00ff0000},
6392 + {0x0000833c, 0x00000000},
6393 + {0x00008340, 0x000107ff},
6394 + {0x00008344, 0x00481043},
6395 + {0x00009808, 0x00000000},
6396 + {0x0000980c, 0xafa68e30},
6397 + {0x00009810, 0xfd14e000},
6398 + {0x00009814, 0x9c0a9f6b},
6399 + {0x0000981c, 0x00000000},
6400 + {0x0000982c, 0x0000a000},
6401 + {0x00009830, 0x00000000},
6402 + {0x0000983c, 0x00200400},
6403 + {0x0000984c, 0x0040233c},
6404 + {0x0000a84c, 0x0040233c},
6405 + {0x00009854, 0x00000044},
6406 + {0x00009900, 0x00000000},
6407 + {0x00009904, 0x00000000},
6408 + {0x00009908, 0x00000000},
6409 + {0x0000990c, 0x00000000},
6410 + {0x00009910, 0x01002310},
6411 + {0x0000991c, 0x10000fff},
6412 + {0x00009920, 0x04900000},
6413 + {0x0000a920, 0x04900000},
6414 + {0x00009928, 0x00000001},
6415 + {0x0000992c, 0x00000004},
6416 + {0x00009934, 0x1e1f2022},
6417 + {0x00009938, 0x0a0b0c0d},
6418 + {0x0000993c, 0x00000000},
6419 + {0x00009948, 0x9280c00a},
6420 + {0x0000994c, 0x00020028},
6421 + {0x00009954, 0x5f3ca3de},
6422 + {0x00009958, 0x2108ecff},
6423 + {0x00009940, 0x14750604},
6424 + {0x0000c95c, 0x004b6a8e},
6425 + {0x00009970, 0x190fb515},
6426 + {0x00009974, 0x00000000},
6427 + {0x00009978, 0x00000001},
6428 + {0x0000997c, 0x00000000},
6429 + {0x00009980, 0x00000000},
6430 + {0x00009984, 0x00000000},
6431 + {0x00009988, 0x00000000},
6432 + {0x0000998c, 0x00000000},
6433 + {0x00009990, 0x00000000},
6434 + {0x00009994, 0x00000000},
6435 + {0x00009998, 0x00000000},
6436 + {0x0000999c, 0x00000000},
6437 + {0x000099a0, 0x00000000},
6438 + {0x000099a4, 0x00000001},
6439 + {0x000099a8, 0x201fff00},
6440 + {0x000099ac, 0x006f0000},
6441 + {0x000099b0, 0x03051000},
6442 + {0x000099b4, 0x00000820},
6443 + {0x000099dc, 0x00000000},
6444 + {0x000099e0, 0x00000000},
6445 + {0x000099e4, 0xaaaaaaaa},
6446 + {0x000099e8, 0x3c466478},
6447 + {0x000099ec, 0x0cc80caa},
6448 + {0x000099f0, 0x00000000},
6449 + {0x000099fc, 0x00001042},
6450 + {0x0000a208, 0x803e4788},
6451 + {0x0000a210, 0x4080a333},
6452 + {0x0000a214, 0x40206c10},
6453 + {0x0000a218, 0x009c4060},
6454 + {0x0000a220, 0x01834061},
6455 + {0x0000a224, 0x00000400},
6456 + {0x0000a228, 0x000003b5},
6457 + {0x0000a22c, 0x233f7180},
6458 + {0x0000a234, 0x20202020},
6459 + {0x0000a238, 0x20202020},
6460 + {0x0000a240, 0x38490a20},
6461 + {0x0000a244, 0x00007bb6},
6462 + {0x0000a248, 0x0fff3ffc},
6463 + {0x0000a24c, 0x00000000},
6464 + {0x0000a254, 0x00000000},
6465 + {0x0000a258, 0x0cdbd380},
6466 + {0x0000a25c, 0x0f0f0f01},
6467 + {0x0000a260, 0xdfa91f01},
6468 + {0x0000a268, 0x00000000},
6469 + {0x0000a26c, 0x0e79e5c6},
6470 + {0x0000b26c, 0x0e79e5c6},
6471 + {0x0000d270, 0x00820820},
6472 + {0x0000a278, 0x1ce739ce},
6473 + {0x0000d35c, 0x07ffffef},
6474 + {0x0000d360, 0x0fffffe7},
6475 + {0x0000d364, 0x17ffffe5},
6476 + {0x0000d368, 0x1fffffe4},
6477 + {0x0000d36c, 0x37ffffe3},
6478 + {0x0000d370, 0x3fffffe3},
6479 + {0x0000d374, 0x57ffffe3},
6480 + {0x0000d378, 0x5fffffe2},
6481 + {0x0000d37c, 0x7fffffe2},
6482 + {0x0000d380, 0x7f3c7bba},
6483 + {0x0000d384, 0xf3307ff0},
6484 + {0x0000a38c, 0x20202020},
6485 + {0x0000a390, 0x20202020},
6486 + {0x0000a394, 0x1ce739ce},
6487 + {0x0000a398, 0x000001ce},
6488 + {0x0000a39c, 0x00000001},
6489 + {0x0000a3a0, 0x00000000},
6490 + {0x0000a3a4, 0x00000000},
6491 + {0x0000a3a8, 0x00000000},
6492 + {0x0000a3ac, 0x00000000},
6493 + {0x0000a3b0, 0x00000000},
6494 + {0x0000a3b4, 0x00000000},
6495 + {0x0000a3b8, 0x00000000},
6496 + {0x0000a3bc, 0x00000000},
6497 + {0x0000a3c0, 0x00000000},
6498 + {0x0000a3c4, 0x00000000},
6499 + {0x0000a3c8, 0x00000246},
6500 + {0x0000a3cc, 0x20202020},
6501 + {0x0000a3d0, 0x20202020},
6502 + {0x0000a3d4, 0x20202020},
6503 + {0x0000a3dc, 0x1ce739ce},
6504 + {0x0000a3e0, 0x000001ce},
6505 + {0x0000a3e4, 0x00000000},
6506 + {0x0000a3e8, 0x18c43433},
6507 + {0x0000a3ec, 0x00f70081},
6508 + {0x00007800, 0x00040000},
6509 + {0x00007804, 0xdb005012},
6510 + {0x00007808, 0x04924914},
6511 + {0x0000780c, 0x21084210},
6512 + {0x00007810, 0x6d801300},
6513 + {0x00007818, 0x07e41000},
6514 + {0x00007824, 0x00040000},
6515 + {0x00007828, 0xdb005012},
6516 + {0x0000782c, 0x04924914},
6517 + {0x00007830, 0x21084210},
6518 + {0x00007834, 0x6d801300},
6519 + {0x0000783c, 0x07e40000},
6520 + {0x00007848, 0x00100000},
6521 + {0x0000784c, 0x773f0567},
6522 + {0x00007850, 0x54214514},
6523 + {0x00007854, 0x12035828},
6524 + {0x00007858, 0x9259269a},
6525 + {0x00007860, 0x52802000},
6526 + {0x00007864, 0x0a8e370e},
6527 + {0x00007868, 0xc0102850},
6528 + {0x0000786c, 0x812d4000},
6529 + {0x00007870, 0x807ec400},
6530 + {0x00007874, 0x001b6db0},
6531 + {0x00007878, 0x00376b63},
6532 + {0x0000787c, 0x06db6db6},
6533 + {0x00007880, 0x006d8000},
6534 + {0x00007884, 0xffeffffe},
6535 + {0x00007888, 0xffeffffe},
6536 + {0x0000788c, 0x00010000},
6537 + {0x00007890, 0x02060aeb},
6538 + {0x00007898, 0x2a850160},
6539 +};
6540 +
6541 +static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
6542 + {0x00001030, 0x00000268, 0x000004d0},
6543 + {0x00001070, 0x0000018c, 0x00000318},
6544 + {0x000010b0, 0x00000fd0, 0x00001fa0},
6545 + {0x00008014, 0x044c044c, 0x08980898},
6546 + {0x0000801c, 0x148ec02b, 0x148ec057},
6547 + {0x00008318, 0x000044c0, 0x00008980},
6548 + {0x00009820, 0x02020200, 0x02020200},
6549 + {0x00009824, 0x01000f0f, 0x01000f0f},
6550 + {0x00009828, 0x0b020001, 0x0b020001},
6551 + {0x00009834, 0x00000f0f, 0x00000f0f},
6552 + {0x00009844, 0x03721821, 0x03721821},
6553 + {0x00009914, 0x00000898, 0x00001130},
6554 + {0x00009918, 0x0000000b, 0x00000016},
6555 +};
6556 +
6557 +static const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = {
6558 + {0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290,
6559 + 0x00000290},
6560 + {0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300,
6561 + 0x00000300},
6562 + {0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304,
6563 + 0x00000304},
6564 + {0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308,
6565 + 0x00000308},
6566 + {0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c,
6567 + 0x0000030c},
6568 + {0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000,
6569 + 0x00008000},
6570 + {0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004,
6571 + 0x00008004},
6572 + {0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008,
6573 + 0x00008008},
6574 + {0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c,
6575 + 0x0000800c},
6576 + {0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080,
6577 + 0x00008080},
6578 + {0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084,
6579 + 0x00008084},
6580 + {0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088,
6581 + 0x00008088},
6582 + {0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c,
6583 + 0x0000808c},
6584 + {0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100,
6585 + 0x00008100},
6586 + {0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104,
6587 + 0x00008104},
6588 + {0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108,
6589 + 0x00008108},
6590 + {0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c,
6591 + 0x0000810c},
6592 + {0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110,
6593 + 0x00008110},
6594 + {0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114,
6595 + 0x00008114},
6596 + {0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180,
6597 + 0x00008180},
6598 + {0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184,
6599 + 0x00008184},
6600 + {0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188,
6601 + 0x00008188},
6602 + {0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c,
6603 + 0x0000818c},
6604 + {0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190,
6605 + 0x00008190},
6606 + {0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194,
6607 + 0x00008194},
6608 + {0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0,
6609 + 0x000081a0},
6610 + {0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c,
6611 + 0x0000820c},
6612 + {0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8,
6613 + 0x000081a8},
6614 + {0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284,
6615 + 0x00008284},
6616 + {0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288,
6617 + 0x00008288},
6618 + {0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224,
6619 + 0x00008224},
6620 + {0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290,
6621 + 0x00008290},
6622 + {0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300,
6623 + 0x00008300},
6624 + {0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304,
6625 + 0x00008304},
6626 + {0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308,
6627 + 0x00008308},
6628 + {0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c,
6629 + 0x0000830c},
6630 + {0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380,
6631 + 0x00008380},
6632 + {0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384,
6633 + 0x00008384},
6634 + {0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700,
6635 + 0x00008700},
6636 + {0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704,
6637 + 0x00008704},
6638 + {0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708,
6639 + 0x00008708},
6640 + {0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c,
6641 + 0x0000870c},
6642 + {0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780,
6643 + 0x00008780},
6644 + {0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784,
6645 + 0x00008784},
6646 + {0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00,
6647 + 0x00008b00},
6648 + {0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04,
6649 + 0x00008b04},
6650 + {0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08,
6651 + 0x00008b08},
6652 + {0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c,
6653 + 0x00008b0c},
6654 + {0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b10, 0x00008b10,
6655 + 0x00008b10},
6656 + {0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b14, 0x00008b14,
6657 + 0x00008b14},
6658 + {0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b01, 0x00008b01,
6659 + 0x00008b01},
6660 + {0x00009acc, 0x0000b380, 0x0000b380, 0x00008b05, 0x00008b05,
6661 + 0x00008b05},
6662 + {0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b09, 0x00008b09,
6663 + 0x00008b09},
6664 + {0x00009ad4, 0x0000b388, 0x0000b388, 0x00008b0d, 0x00008b0d,
6665 + 0x00008b0d},
6666 + {0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008b11, 0x00008b11,
6667 + 0x00008b11},
6668 + {0x00009adc, 0x0000b390, 0x0000b390, 0x00008b15, 0x00008b15,
6669 + 0x00008b15},
6670 + {0x00009ae0, 0x0000b394, 0x0000b394, 0x00008b02, 0x00008b02,
6671 + 0x00008b02},
6672 + {0x00009ae4, 0x0000b398, 0x0000b398, 0x00008b06, 0x00008b06,
6673 + 0x00008b06},
6674 + {0x00009ae8, 0x0000b780, 0x0000b780, 0x00008b0a, 0x00008b0a,
6675 + 0x00008b0a},
6676 + {0x00009aec, 0x0000b784, 0x0000b784, 0x00008b0e, 0x00008b0e,
6677 + 0x00008b0e},
6678 + {0x00009af0, 0x0000b788, 0x0000b788, 0x00008b12, 0x00008b12,
6679 + 0x00008b12},
6680 + {0x00009af4, 0x0000b78c, 0x0000b78c, 0x00008b16, 0x00008b16,
6681 + 0x00008b16},
6682 + {0x00009af8, 0x0000b790, 0x0000b790, 0x00008b03, 0x00008b03,
6683 + 0x00008b03},
6684 + {0x00009afc, 0x0000b794, 0x0000b794, 0x00008b07, 0x00008b07,
6685 + 0x00008b07},
6686 + {0x00009b00, 0x0000b798, 0x0000b798, 0x00008b0b, 0x00008b0b,
6687 + 0x00008b0b},
6688 + {0x00009b04, 0x0000d784, 0x0000d784, 0x00008b0f, 0x00008b0f,
6689 + 0x00008b0f},
6690 + {0x00009b08, 0x0000d788, 0x0000d788, 0x00008b13, 0x00008b13,
6691 + 0x00008b13},
6692 + {0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00008b17, 0x00008b17,
6693 + 0x00008b17},
6694 + {0x00009b10, 0x0000d790, 0x0000d790, 0x00008b23, 0x00008b23,
6695 + 0x00008b23},
6696 + {0x00009b14, 0x0000f780, 0x0000f780, 0x00008b27, 0x00008b27,
6697 + 0x00008b27},
6698 + {0x00009b18, 0x0000f784, 0x0000f784, 0x00008b2b, 0x00008b2b,
6699 + 0x00008b2b},
6700 + {0x00009b1c, 0x0000f788, 0x0000f788, 0x00008b2f, 0x00008b2f,
6701 + 0x00008b2f},
6702 + {0x00009b20, 0x0000f78c, 0x0000f78c, 0x00008b33, 0x00008b33,
6703 + 0x00008b33},
6704 + {0x00009b24, 0x0000f790, 0x0000f790, 0x00008b37, 0x00008b37,
6705 + 0x00008b37},
6706 + {0x00009b28, 0x0000f794, 0x0000f794, 0x00008b43, 0x00008b43,
6707 + 0x00008b43},
6708 + {0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x00008b47, 0x00008b47,
6709 + 0x00008b47},
6710 + {0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00008b4b, 0x00008b4b,
6711 + 0x00008b4b},
6712 + {0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00008b4f, 0x00008b4f,
6713 + 0x00008b4f},
6714 + {0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00008b53, 0x00008b53,
6715 + 0x00008b53},
6716 + {0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00008b57, 0x00008b57,
6717 + 0x00008b57},
6718 + {0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x00008b5b, 0x00008b5b,
6719 + 0x00008b5b},
6720 + {0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x00008b5b, 0x00008b5b,
6721 + 0x00008b5b},
6722 + {0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00008b5b, 0x00008b5b,
6723 + 0x00008b5b},
6724 + {0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00008b5b, 0x00008b5b,
6725 + 0x00008b5b},
6726 + {0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00008b5b, 0x00008b5b,
6727 + 0x00008b5b},
6728 + {0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00008b5b, 0x00008b5b,
6729 + 0x00008b5b},
6730 + {0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x00008b5b, 0x00008b5b,
6731 + 0x00008b5b},
6732 + {0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x00008b5b, 0x00008b5b,
6733 + 0x00008b5b},
6734 + {0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00008b5b, 0x00008b5b,
6735 + 0x00008b5b},
6736 + {0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00008b5b, 0x00008b5b,
6737 + 0x00008b5b},
6738 + {0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x00008b5b, 0x00008b5b,
6739 + 0x00008b5b},
6740 + {0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x00008b5b, 0x00008b5b,
6741 + 0x00008b5b},
6742 + {0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x00008b5b, 0x00008b5b,
6743 + 0x00008b5b},
6744 + {0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x00008b5b, 0x00008b5b,
6745 + 0x00008b5b},
6746 + {0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x00008b5b, 0x00008b5b,
6747 + 0x00008b5b},
6748 + {0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x00008b5b, 0x00008b5b,
6749 + 0x00008b5b},
6750 + {0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x00008b5b, 0x00008b5b,
6751 + 0x00008b5b},
6752 + {0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x00008b5b, 0x00008b5b,
6753 + 0x00008b5b},
6754 + {0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x00008b5b, 0x00008b5b,
6755 + 0x00008b5b},
6756 + {0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x00008b5b, 0x00008b5b,
6757 + 0x00008b5b},
6758 + {0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x00008b5b, 0x00008b5b,
6759 + 0x00008b5b},
6760 + {0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x00008b5b, 0x00008b5b,
6761 + 0x00008b5b},
6762 + {0x00009b98, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6763 + 0x00008b5b},
6764 + {0x00009b9c, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6765 + 0x00008b5b},
6766 + {0x00009ba0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6767 + 0x00008b5b},
6768 + {0x00009ba4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6769 + 0x00008b5b},
6770 + {0x00009ba8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6771 + 0x00008b5b},
6772 + {0x00009bac, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6773 + 0x00008b5b},
6774 + {0x00009bb0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6775 + 0x00008b5b},
6776 + {0x00009bb4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6777 + 0x00008b5b},
6778 + {0x00009bb8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6779 + 0x00008b5b},
6780 + {0x00009bbc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6781 + 0x00008b5b},
6782 + {0x00009bc0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6783 + 0x00008b5b},
6784 + {0x00009bc4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6785 + 0x00008b5b},
6786 + {0x00009bc8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6787 + 0x00008b5b},
6788 + {0x00009bcc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6789 + 0x00008b5b},
6790 + {0x00009bd0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6791 + 0x00008b5b},
6792 + {0x00009bd4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6793 + 0x00008b5b},
6794 + {0x00009bd8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6795 + 0x00008b5b},
6796 + {0x00009bdc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6797 + 0x00008b5b},
6798 + {0x00009be0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6799 + 0x00008b5b},
6800 + {0x00009be4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6801 + 0x00008b5b},
6802 + {0x00009be8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6803 + 0x00008b5b},
6804 + {0x00009bec, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6805 + 0x00008b5b},
6806 + {0x00009bf0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6807 + 0x00008b5b},
6808 + {0x00009bf4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6809 + 0x00008b5b},
6810 + {0x00009bf8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6811 + 0x00008b5b},
6812 + {0x00009bfc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6813 + 0x00008b5b},
6814 + {0x00009848, 0x00001066, 0x00001066, 0x00001050, 0x00001050,
6815 + 0x00001050},
6816 + {0x0000a848, 0x00001066, 0x00001066, 0x00001050, 0x00001050,
6817 + 0x00001050},
6818 +};
6819 +
6820 +static const u32 ar9280Modes_original_rxgain_9280_2[][6] = {
6821 + {0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290,
6822 + 0x00000290},
6823 + {0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300,
6824 + 0x00000300},
6825 + {0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304,
6826 + 0x00000304},
6827 + {0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308,
6828 + 0x00000308},
6829 + {0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c,
6830 + 0x0000030c},
6831 + {0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000,
6832 + 0x00008000},
6833 + {0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004,
6834 + 0x00008004},
6835 + {0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008,
6836 + 0x00008008},
6837 + {0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c,
6838 + 0x0000800c},
6839 + {0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080,
6840 + 0x00008080},
6841 + {0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084,
6842 + 0x00008084},
6843 + {0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088,
6844 + 0x00008088},
6845 + {0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c,
6846 + 0x0000808c},
6847 + {0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100,
6848 + 0x00008100},
6849 + {0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104,
6850 + 0x00008104},
6851 + {0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108,
6852 + 0x00008108},
6853 + {0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c,
6854 + 0x0000810c},
6855 + {0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110,
6856 + 0x00008110},
6857 + {0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114,
6858 + 0x00008114},
6859 + {0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180,
6860 + 0x00008180},
6861 + {0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184,
6862 + 0x00008184},
6863 + {0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188,
6864 + 0x00008188},
6865 + {0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c,
6866 + 0x0000818c},
6867 + {0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190,
6868 + 0x00008190},
6869 + {0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194,
6870 + 0x00008194},
6871 + {0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0,
6872 + 0x000081a0},
6873 + {0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c,
6874 + 0x0000820c},
6875 + {0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8,
6876 + 0x000081a8},
6877 + {0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284,
6878 + 0x00008284},
6879 + {0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288,
6880 + 0x00008288},
6881 + {0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224,
6882 + 0x00008224},
6883 + {0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290,
6884 + 0x00008290},
6885 + {0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300,
6886 + 0x00008300},
6887 + {0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304,
6888 + 0x00008304},
6889 + {0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308,
6890 + 0x00008308},
6891 + {0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c,
6892 + 0x0000830c},
6893 + {0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380,
6894 + 0x00008380},
6895 + {0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384,
6896 + 0x00008384},
6897 + {0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700,
6898 + 0x00008700},
6899 + {0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704,
6900 + 0x00008704},
6901 + {0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708,
6902 + 0x00008708},
6903 + {0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c,
6904 + 0x0000870c},
6905 + {0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780,
6906 + 0x00008780},
6907 + {0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784,
6908 + 0x00008784},
6909 + {0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00,
6910 + 0x00008b00},
6911 + {0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04,
6912 + 0x00008b04},
6913 + {0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08,
6914 + 0x00008b08},
6915 + {0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c,
6916 + 0x00008b0c},
6917 + {0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80,
6918 + 0x00008b80},
6919 + {0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84,
6920 + 0x00008b84},
6921 + {0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88,
6922 + 0x00008b88},
6923 + {0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c,
6924 + 0x00008b8c},
6925 + {0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90,
6926 + 0x00008b90},
6927 + {0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80,
6928 + 0x00008f80},
6929 + {0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84,
6930 + 0x00008f84},
6931 + {0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88,
6932 + 0x00008f88},
6933 + {0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c,
6934 + 0x00008f8c},
6935 + {0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90,
6936 + 0x00008f90},
6937 + {0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c,
6938 + 0x0000930c},
6939 + {0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310,
6940 + 0x00009310},
6941 + {0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384,
6942 + 0x00009384},
6943 + {0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388,
6944 + 0x00009388},
6945 + {0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324,
6946 + 0x00009324},
6947 + {0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704,
6948 + 0x00009704},
6949 + {0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4,
6950 + 0x000096a4},
6951 + {0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8,
6952 + 0x000096a8},
6953 + {0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710,
6954 + 0x00009710},
6955 + {0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714,
6956 + 0x00009714},
6957 + {0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720,
6958 + 0x00009720},
6959 + {0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724,
6960 + 0x00009724},
6961 + {0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728,
6962 + 0x00009728},
6963 + {0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c,
6964 + 0x0000972c},
6965 + {0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0,
6966 + 0x000097a0},
6967 + {0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4,
6968 + 0x000097a4},
6969 + {0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8,
6970 + 0x000097a8},
6971 + {0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0,
6972 + 0x000097b0},
6973 + {0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4,
6974 + 0x000097b4},
6975 + {0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8,
6976 + 0x000097b8},
6977 + {0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5,
6978 + 0x000097a5},
6979 + {0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9,
6980 + 0x000097a9},
6981 + {0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad,
6982 + 0x000097ad},
6983 + {0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1,
6984 + 0x000097b1},
6985 + {0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5,
6986 + 0x000097b5},
6987 + {0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9,
6988 + 0x000097b9},
6989 + {0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5,
6990 + 0x000097c5},
6991 + {0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9,
6992 + 0x000097c9},
6993 + {0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1,
6994 + 0x000097d1},
6995 + {0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5,
6996 + 0x000097d5},
6997 + {0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9,
6998 + 0x000097d9},
6999 + {0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6,
7000 + 0x000097c6},
7001 + {0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca,
7002 + 0x000097ca},
7003 + {0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce,
7004 + 0x000097ce},
7005 + {0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2,
7006 + 0x000097d2},
7007 + {0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6,
7008 + 0x000097d6},
7009 + {0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3,
7010 + 0x000097c3},
7011 + {0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7,
7012 + 0x000097c7},
7013 + {0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb,
7014 + 0x000097cb},
7015 + {0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf,
7016 + 0x000097cf},
7017 + {0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7,
7018 + 0x000097d7},
7019 + {0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db,
7020 + 0x000097db},
7021 + {0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db,
7022 + 0x000097db},
7023 + {0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db,
7024 + 0x000097db},
7025 + {0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7026 + 0x000097db},
7027 + {0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7028 + 0x000097db},
7029 + {0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7030 + 0x000097db},
7031 + {0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7032 + 0x000097db},
7033 + {0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7034 + 0x000097db},
7035 + {0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7036 + 0x000097db},
7037 + {0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7038 + 0x000097db},
7039 + {0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7040 + 0x000097db},
7041 + {0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7042 + 0x000097db},
7043 + {0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7044 + 0x000097db},
7045 + {0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7046 + 0x000097db},
7047 + {0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7048 + 0x000097db},
7049 + {0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7050 + 0x000097db},
7051 + {0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7052 + 0x000097db},
7053 + {0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7054 + 0x000097db},
7055 + {0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7056 + 0x000097db},
7057 + {0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7058 + 0x000097db},
7059 + {0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7060 + 0x000097db},
7061 + {0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7062 + 0x000097db},
7063 + {0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7064 + 0x000097db},
7065 + {0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7066 + 0x000097db},
7067 + {0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7068 + 0x000097db},
7069 + {0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7070 + 0x000097db},
7071 + {0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7072 + 0x000097db},
7073 + {0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7074 + 0x000097db},
7075 + {0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7076 + 0x000097db},
7077 + {0x00009848, 0x00001066, 0x00001066, 0x00001063, 0x00001063,
7078 + 0x00001063},
7079 + {0x0000a848, 0x00001066, 0x00001066, 0x00001063, 0x00001063,
7080 + 0x00001063},
7081 +};
7082 +
7083 +static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
7084 + {0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290,
7085 + 0x00000290},
7086 + {0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300,
7087 + 0x00000300},
7088 + {0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304,
7089 + 0x00000304},
7090 + {0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308,
7091 + 0x00000308},
7092 + {0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c,
7093 + 0x0000030c},
7094 + {0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000,
7095 + 0x00008000},
7096 + {0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004,
7097 + 0x00008004},
7098 + {0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008,
7099 + 0x00008008},
7100 + {0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c,
7101 + 0x0000800c},
7102 + {0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080,
7103 + 0x00008080},
7104 + {0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084,
7105 + 0x00008084},
7106 + {0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088,
7107 + 0x00008088},
7108 + {0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c,
7109 + 0x0000808c},
7110 + {0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100,
7111 + 0x00008100},
7112 + {0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104,
7113 + 0x00008104},
7114 + {0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108,
7115 + 0x00008108},
7116 + {0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c,
7117 + 0x0000810c},
7118 + {0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110,
7119 + 0x00008110},
7120 + {0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114,
7121 + 0x00008114},
7122 + {0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180,
7123 + 0x00008180},
7124 + {0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184,
7125 + 0x00008184},
7126 + {0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188,
7127 + 0x00008188},
7128 + {0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c,
7129 + 0x0000818c},
7130 + {0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190,
7131 + 0x00008190},
7132 + {0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194,
7133 + 0x00008194},
7134 + {0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0,
7135 + 0x000081a0},
7136 + {0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c,
7137 + 0x0000820c},
7138 + {0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8,
7139 + 0x000081a8},
7140 + {0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284,
7141 + 0x00008284},
7142 + {0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288,
7143 + 0x00008288},
7144 + {0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224,
7145 + 0x00008224},
7146 + {0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290,
7147 + 0x00008290},
7148 + {0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300,
7149 + 0x00008300},
7150 + {0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304,
7151 + 0x00008304},
7152 + {0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308,
7153 + 0x00008308},
7154 + {0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c,
7155 + 0x0000830c},
7156 + {0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380,
7157 + 0x00008380},
7158 + {0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384,
7159 + 0x00008384},
7160 + {0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700,
7161 + 0x00008700},
7162 + {0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704,
7163 + 0x00008704},
7164 + {0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708,
7165 + 0x00008708},
7166 + {0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c,
7167 + 0x0000870c},
7168 + {0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780,
7169 + 0x00008780},
7170 + {0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784,
7171 + 0x00008784},
7172 + {0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00,
7173 + 0x00008b00},
7174 + {0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04,
7175 + 0x00008b04},
7176 + {0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08,
7177 + 0x00008b08},
7178 + {0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c,
7179 + 0x00008b0c},
7180 + {0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80,
7181 + 0x00008b80},
7182 + {0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84,
7183 + 0x00008b84},
7184 + {0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88,
7185 + 0x00008b88},
7186 + {0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c,
7187 + 0x00008b8c},
7188 + {0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90,
7189 + 0x00008b90},
7190 + {0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80,
7191 + 0x00008f80},
7192 + {0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84,
7193 + 0x00008f84},
7194 + {0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88,
7195 + 0x00008f88},
7196 + {0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c,
7197 + 0x00008f8c},
7198 + {0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90,
7199 + 0x00008f90},
7200 + {0x00009ae8, 0x0000b780, 0x0000b780, 0x00009310, 0x00009310,
7201 + 0x00009310},
7202 + {0x00009aec, 0x0000b784, 0x0000b784, 0x00009314, 0x00009314,
7203 + 0x00009314},
7204 + {0x00009af0, 0x0000b788, 0x0000b788, 0x00009320, 0x00009320,
7205 + 0x00009320},
7206 + {0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009324, 0x00009324,
7207 + 0x00009324},
7208 + {0x00009af8, 0x0000b790, 0x0000b790, 0x00009328, 0x00009328,
7209 + 0x00009328},
7210 + {0x00009afc, 0x0000b794, 0x0000b794, 0x0000932c, 0x0000932c,
7211 + 0x0000932c},
7212 + {0x00009b00, 0x0000b798, 0x0000b798, 0x00009330, 0x00009330,
7213 + 0x00009330},
7214 + {0x00009b04, 0x0000d784, 0x0000d784, 0x00009334, 0x00009334,
7215 + 0x00009334},
7216 + {0x00009b08, 0x0000d788, 0x0000d788, 0x00009321, 0x00009321,
7217 + 0x00009321},
7218 + {0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009325, 0x00009325,
7219 + 0x00009325},
7220 + {0x00009b10, 0x0000d790, 0x0000d790, 0x00009329, 0x00009329,
7221 + 0x00009329},
7222 + {0x00009b14, 0x0000f780, 0x0000f780, 0x0000932d, 0x0000932d,
7223 + 0x0000932d},
7224 + {0x00009b18, 0x0000f784, 0x0000f784, 0x00009331, 0x00009331,
7225 + 0x00009331},
7226 + {0x00009b1c, 0x0000f788, 0x0000f788, 0x00009335, 0x00009335,
7227 + 0x00009335},
7228 + {0x00009b20, 0x0000f78c, 0x0000f78c, 0x00009322, 0x00009322,
7229 + 0x00009322},
7230 + {0x00009b24, 0x0000f790, 0x0000f790, 0x00009326, 0x00009326,
7231 + 0x00009326},
7232 + {0x00009b28, 0x0000f794, 0x0000f794, 0x0000932a, 0x0000932a,
7233 + 0x0000932a},
7234 + {0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x0000932e, 0x0000932e,
7235 + 0x0000932e},
7236 + {0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00009332, 0x00009332,
7237 + 0x00009332},
7238 + {0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00009336, 0x00009336,
7239 + 0x00009336},
7240 + {0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00009323, 0x00009323,
7241 + 0x00009323},
7242 + {0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00009327, 0x00009327,
7243 + 0x00009327},
7244 + {0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x0000932b, 0x0000932b,
7245 + 0x0000932b},
7246 + {0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x0000932f, 0x0000932f,
7247 + 0x0000932f},
7248 + {0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00009333, 0x00009333,
7249 + 0x00009333},
7250 + {0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00009337, 0x00009337,
7251 + 0x00009337},
7252 + {0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00009343, 0x00009343,
7253 + 0x00009343},
7254 + {0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00009347, 0x00009347,
7255 + 0x00009347},
7256 + {0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x0000934b, 0x0000934b,
7257 + 0x0000934b},
7258 + {0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x0000934f, 0x0000934f,
7259 + 0x0000934f},
7260 + {0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00009353, 0x00009353,
7261 + 0x00009353},
7262 + {0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00009357, 0x00009357,
7263 + 0x00009357},
7264 + {0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x0000935b, 0x0000935b,
7265 + 0x0000935b},
7266 + {0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x0000935b, 0x0000935b,
7267 + 0x0000935b},
7268 + {0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x0000935b, 0x0000935b,
7269 + 0x0000935b},
7270 + {0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x0000935b, 0x0000935b,
7271 + 0x0000935b},
7272 + {0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x0000935b, 0x0000935b,
7273 + 0x0000935b},
7274 + {0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x0000935b, 0x0000935b,
7275 + 0x0000935b},
7276 + {0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x0000935b, 0x0000935b,
7277 + 0x0000935b},
7278 + {0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x0000935b, 0x0000935b,
7279 + 0x0000935b},
7280 + {0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x0000935b, 0x0000935b,
7281 + 0x0000935b},
7282 + {0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x0000935b, 0x0000935b,
7283 + 0x0000935b},
7284 + {0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x0000935b, 0x0000935b,
7285 + 0x0000935b},
7286 + {0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x0000935b, 0x0000935b,
7287 + 0x0000935b},
7288 + {0x00009b98, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7289 + 0x0000935b},
7290 + {0x00009b9c, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7291 + 0x0000935b},
7292 + {0x00009ba0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7293 + 0x0000935b},
7294 + {0x00009ba4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7295 + 0x0000935b},
7296 + {0x00009ba8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7297 + 0x0000935b},
7298 + {0x00009bac, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7299 + 0x0000935b},
7300 + {0x00009bb0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7301 + 0x0000935b},
7302 + {0x00009bb4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7303 + 0x0000935b},
7304 + {0x00009bb8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7305 + 0x0000935b},
7306 + {0x00009bbc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7307 + 0x0000935b},
7308 + {0x00009bc0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7309 + 0x0000935b},
7310 + {0x00009bc4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7311 + 0x0000935b},
7312 + {0x00009bc8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7313 + 0x0000935b},
7314 + {0x00009bcc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7315 + 0x0000935b},
7316 + {0x00009bd0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7317 + 0x0000935b},
7318 + {0x00009bd4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7319 + 0x0000935b},
7320 + {0x00009bd8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7321 + 0x0000935b},
7322 + {0x00009bdc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7323 + 0x0000935b},
7324 + {0x00009be0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7325 + 0x0000935b},
7326 + {0x00009be4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7327 + 0x0000935b},
7328 + {0x00009be8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7329 + 0x0000935b},
7330 + {0x00009bec, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7331 + 0x0000935b},
7332 + {0x00009bf0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7333 + 0x0000935b},
7334 + {0x00009bf4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7335 + 0x0000935b},
7336 + {0x00009bf8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7337 + 0x0000935b},
7338 + {0x00009bfc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7339 + 0x0000935b},
7340 + {0x00009848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a,
7341 + 0x0000105a},
7342 + {0x0000a848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a,
7343 + 0x0000105a},
7344 +};
7345 +
7346 +static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
7347 + {0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652,
7348 + 0x0a1aa652},
7349 + {0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce,
7350 + 0x050739ce},
7351 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
7352 + 0x00000000},
7353 + {0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002,
7354 + 0x00004002},
7355 + {0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008,
7356 + 0x00007008},
7357 + {0x0000a30c, 0x0000a006, 0x0000a006, 0x0000c010, 0x0000c010,
7358 + 0x0000c010},
7359 + {0x0000a310, 0x0000e012, 0x0000e012, 0x00010012, 0x00010012,
7360 + 0x00010012},
7361 + {0x0000a314, 0x00011014, 0x00011014, 0x00013014, 0x00013014,
7362 + 0x00013014},
7363 + {0x0000a318, 0x0001504a, 0x0001504a, 0x0001820a, 0x0001820a,
7364 + 0x0001820a},
7365 + {0x0000a31c, 0x0001904c, 0x0001904c, 0x0001b211, 0x0001b211,
7366 + 0x0001b211},
7367 + {0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213,
7368 + 0x0001e213},
7369 + {0x0000a324, 0x00021092, 0x00021092, 0x00022411, 0x00022411,
7370 + 0x00022411},
7371 + {0x0000a328, 0x0002510a, 0x0002510a, 0x00025413, 0x00025413,
7372 + 0x00025413},
7373 + {0x0000a32c, 0x0002910c, 0x0002910c, 0x00029811, 0x00029811,
7374 + 0x00029811},
7375 + {0x0000a330, 0x0002c18b, 0x0002c18b, 0x0002c813, 0x0002c813,
7376 + 0x0002c813},
7377 + {0x0000a334, 0x0002f1cc, 0x0002f1cc, 0x00030a14, 0x00030a14,
7378 + 0x00030a14},
7379 + {0x0000a338, 0x000321eb, 0x000321eb, 0x00035a50, 0x00035a50,
7380 + 0x00035a50},
7381 + {0x0000a33c, 0x000341ec, 0x000341ec, 0x00039c4c, 0x00039c4c,
7382 + 0x00039c4c},
7383 + {0x0000a340, 0x000341ec, 0x000341ec, 0x0003de8a, 0x0003de8a,
7384 + 0x0003de8a},
7385 + {0x0000a344, 0x000341ec, 0x000341ec, 0x00042e92, 0x00042e92,
7386 + 0x00042e92},
7387 + {0x0000a348, 0x000341ec, 0x000341ec, 0x00046ed2, 0x00046ed2,
7388 + 0x00046ed2},
7389 + {0x0000a34c, 0x000341ec, 0x000341ec, 0x0004bed5, 0x0004bed5,
7390 + 0x0004bed5},
7391 + {0x0000a350, 0x000341ec, 0x000341ec, 0x0004ff54, 0x0004ff54,
7392 + 0x0004ff54},
7393 + {0x0000a354, 0x000341ec, 0x000341ec, 0x00055fd5, 0x00055fd5,
7394 + 0x00055fd5},
7395 + {0x00007814, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff,
7396 + 0x00198eff},
7397 + {0x00007838, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff,
7398 + 0x00198eff},
7399 + {0x0000781c, 0x00172000, 0x00172000, 0x00172000, 0x00172000,
7400 + 0x00172000},
7401 + {0x00007840, 0x00172000, 0x00172000, 0x00172000, 0x00172000,
7402 + 0x00172000},
7403 + {0x00007820, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480,
7404 + 0xf258a480},
7405 + {0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480,
7406 + 0xf258a480},
7407 +};
7408 +
7409 +static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
7410 + {0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652,
7411 + 0x0a1aa652},
7412 + {0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce,
7413 + 0x050701ce},
7414 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
7415 + 0x00000000},
7416 + {0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002,
7417 + 0x00003002},
7418 + {0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009,
7419 + 0x00008009},
7420 + {0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b,
7421 + 0x0000b00b},
7422 + {0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012,
7423 + 0x0000e012},
7424 + {0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048,
7425 + 0x00012048},
7426 + {0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a,
7427 + 0x0001604a},
7428 + {0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211,
7429 + 0x0001a211},
7430 + {0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213,
7431 + 0x0001e213},
7432 + {0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b,
7433 + 0x0002121b},
7434 + {0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412,
7435 + 0x00024412},
7436 + {0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414,
7437 + 0x00028414},
7438 + {0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a,
7439 + 0x0002b44a},
7440 + {0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649,
7441 + 0x00030649},
7442 + {0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b,
7443 + 0x0003364b},
7444 + {0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49,
7445 + 0x00038a49},
7446 + {0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48,
7447 + 0x0003be48},
7448 + {0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a,
7449 + 0x0003ee4a},
7450 + {0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88,
7451 + 0x00042e88},
7452 + {0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a,
7453 + 0x00046e8a},
7454 + {0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9,
7455 + 0x00049ec9},
7456 + {0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42,
7457 + 0x0004bf42},
7458 + {0x00007814, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff,
7459 + 0x0019beff},
7460 + {0x00007838, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff,
7461 + 0x0019beff},
7462 + {0x0000781c, 0x00392000, 0x00392000, 0x00392000, 0x00392000,
7463 + 0x00392000},
7464 + {0x00007840, 0x00392000, 0x00392000, 0x00392000, 0x00392000,
7465 + 0x00392000},
7466 + {0x00007820, 0x92592480, 0x92592480, 0x92592480, 0x92592480,
7467 + 0x92592480},
7468 + {0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480,
7469 + 0x92592480},
7470 +};
7471 +
7472 +static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
7473 + {0x00004040, 0x9248fd00},
7474 + {0x00004040, 0x24924924},
7475 + {0x00004040, 0xa8000019},
7476 + {0x00004040, 0x13160820},
7477 + {0x00004040, 0xe5980560},
7478 + {0x00004040, 0xc01dcffc},
7479 + {0x00004040, 0x1aaabe41},
7480 + {0x00004040, 0xbe105554},
7481 + {0x00004040, 0x00043007},
7482 + {0x00004044, 0x00000000},
7483 +};
7484 +
7485 +static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
7486 + {0x00004040, 0x9248fd00},
7487 + {0x00004040, 0x24924924},
7488 + {0x00004040, 0xa8000019},
7489 + {0x00004040, 0x13160820},
7490 + {0x00004040, 0xe5980560},
7491 + {0x00004040, 0xc01dcffd},
7492 + {0x00004040, 0x1aaabe41},
7493 + {0x00004040, 0xbe105554},
7494 + {0x00004040, 0x00043007},
7495 + {0x00004044, 0x00000000},
7496 +};
7497 +
7498 +/* AR9285 Revsion 10*/
7499 +static const u_int32_t ar9285Modes_9285[][6] = {
7500 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
7501 + 0x000001e0},
7502 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
7503 + 0x000001e0},
7504 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
7505 + 0x00001180},
7506 + {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
7507 + 0x00000008},
7508 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00,
7509 + 0x06e006e0},
7510 + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b,
7511 + 0x0988004f},
7512 + {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440,
7513 + 0x00006880},
7514 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
7515 + 0x00000303},
7516 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
7517 + 0x02020200},
7518 + {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
7519 + 0x00000e0e},
7520 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
7521 + 0x0a020001},
7522 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
7523 + 0x00000e0e},
7524 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
7525 + 0x00000007},
7526 + {0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e,
7527 + 0x206a012e},
7528 + {0x00009844, 0x0372161e, 0x0372161e, 0x03720020, 0x03720020,
7529 + 0x037216a0},
7530 + {0x00009848, 0x00001066, 0x00001066, 0x0000004e, 0x0000004e,
7531 + 0x00001059},
7532 + {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2,
7533 + 0x6d4000e2},
7534 + {0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e,
7535 + 0x7ec84d2e},
7536 + {0x0000985c, 0x3139605e, 0x3139605e, 0x3136605e, 0x3136605e,
7537 + 0x3139605e},
7538 + {0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20,
7539 + 0x00058d18},
7540 + {0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00,
7541 + 0x0001ce00},
7542 + {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0,
7543 + 0x5ac640d0},
7544 + {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881,
7545 + 0x06903881},
7546 + {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898,
7547 + 0x000007d0},
7548 + {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b,
7549 + 0x00000016},
7550 + {0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d,
7551 + 0xd00a800d},
7552 + {0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1020, 0xdfbc1020,
7553 + 0xdfbc1010},
7554 + {0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
7555 + 0x00000000},
7556 + {0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
7557 + 0x00000000},
7558 + {0x000099b8, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c,
7559 + 0x00cf4d1c},
7560 + {0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00,
7561 + 0x00000c00},
7562 + {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4,
7563 + 0x05eea6d4},
7564 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
7565 + 0x06336f77},
7566 + {0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329,
7567 + 0x60f65329},
7568 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
7569 + 0x08f186c8},
7570 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
7571 + 0x00046384},
7572 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
7573 + 0x00000000},
7574 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
7575 + 0x00000000},
7576 + {0x00009a00, 0x00000000, 0x00000000, 0x00068084, 0x00068084,
7577 + 0x00000000},
7578 + {0x00009a04, 0x00000000, 0x00000000, 0x00068088, 0x00068088,
7579 + 0x00000000},
7580 + {0x00009a08, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c,
7581 + 0x00000000},
7582 + {0x00009a0c, 0x00000000, 0x00000000, 0x00068100, 0x00068100,
7583 + 0x00000000},
7584 + {0x00009a10, 0x00000000, 0x00000000, 0x00068104, 0x00068104,
7585 + 0x00000000},
7586 + {0x00009a14, 0x00000000, 0x00000000, 0x00068108, 0x00068108,
7587 + 0x00000000},
7588 + {0x00009a18, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c,
7589 + 0x00000000},
7590 + {0x00009a1c, 0x00000000, 0x00000000, 0x00068110, 0x00068110,
7591 + 0x00000000},
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7962 + {0x0000ab04, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8,
7963 + 0x00000000},
7964 + {0x0000ab08, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac,
7965 + 0x00000000},
7966 + {0x0000ab0c, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac,
7967 + 0x00000000},
7968 + {0x0000ab10, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0,
7969 + 0x00000000},
7970 + {0x0000ab14, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8,
7971 + 0x00000000},
7972 + {0x0000ab18, 0x00000000, 0x00000000, 0x000fb7bc, 0x000fb7bc,
7973 + 0x00000000},
7974 + {0x0000ab1c, 0x00000000, 0x00000000, 0x000fb7a1, 0x000fb7a1,
7975 + 0x00000000},
7976 + {0x0000ab20, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5,
7977 + 0x00000000},
7978 + {0x0000ab24, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9,
7979 + 0x00000000},
7980 + {0x0000ab28, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1,
7981 + 0x00000000},
7982 + {0x0000ab2c, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5,
7983 + 0x00000000},
7984 + {0x0000ab30, 0x00000000, 0x00000000, 0x000fb7bd, 0x000fb7bd,
7985 + 0x00000000},
7986 + {0x0000ab34, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9,
7987 + 0x00000000},
7988 + {0x0000ab38, 0x00000000, 0x00000000, 0x000fb7cd, 0x000fb7cd,
7989 + 0x00000000},
7990 + {0x0000ab3c, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1,
7991 + 0x00000000},
7992 + {0x0000ab40, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9,
7993 + 0x00000000},
7994 + {0x0000ab44, 0x00000000, 0x00000000, 0x000fb7c2, 0x000fb7c2,
7995 + 0x00000000},
7996 + {0x0000ab48, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6,
7997 + 0x00000000},
7998 + {0x0000ab4c, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca,
7999 + 0x00000000},
8000 + {0x0000ab50, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce,
8001 + 0x00000000},
8002 + {0x0000ab54, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2,
8003 + 0x00000000},
8004 + {0x0000ab58, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6,
8005 + 0x00000000},
8006 + {0x0000ab5c, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3,
8007 + 0x00000000},
8008 + {0x0000ab60, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb,
8009 + 0x00000000},
8010 + {0x0000ab64, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8011 + 0x00000000},
8012 + {0x0000ab68, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8013 + 0x00000000},
8014 + {0x0000ab6c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8015 + 0x00000000},
8016 + {0x0000ab70, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8017 + 0x00000000},
8018 + {0x0000ab74, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8019 + 0x00000000},
8020 + {0x0000ab78, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8021 + 0x00000000},
8022 + {0x0000ab7c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8023 + 0x00000000},
8024 + {0x0000ab80, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8025 + 0x00000000},
8026 + {0x0000ab84, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8027 + 0x00000000},
8028 + {0x0000ab88, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8029 + 0x00000000},
8030 + {0x0000ab8c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8031 + 0x00000000},
8032 + {0x0000ab90, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8033 + 0x00000000},
8034 + {0x0000ab94, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8035 + 0x00000000},
8036 + {0x0000ab98, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8037 + 0x00000000},
8038 + {0x0000ab9c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8039 + 0x00000000},
8040 + {0x0000aba0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8041 + 0x00000000},
8042 + {0x0000aba4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8043 + 0x00000000},
8044 + {0x0000aba8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8045 + 0x00000000},
8046 + {0x0000abac, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8047 + 0x00000000},
8048 + {0x0000abb0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8049 + 0x00000000},
8050 + {0x0000abb4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8051 + 0x00000000},
8052 + {0x0000abb8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8053 + 0x00000000},
8054 + {0x0000abbc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8055 + 0x00000000},
8056 + {0x0000abc0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8057 + 0x00000000},
8058 + {0x0000abc4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8059 + 0x00000000},
8060 + {0x0000abc8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8061 + 0x00000000},
8062 + {0x0000abcc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8063 + 0x00000000},
8064 + {0x0000abd0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8065 + 0x00000000},
8066 + {0x0000abd4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8067 + 0x00000000},
8068 + {0x0000abd8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8069 + 0x00000000},
8070 + {0x0000abdc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8071 + 0x00000000},
8072 + {0x0000abe0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8073 + 0x00000000},
8074 + {0x0000abe4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8075 + 0x00000000},
8076 + {0x0000abe8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8077 + 0x00000000},
8078 + {0x0000abec, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8079 + 0x00000000},
8080 + {0x0000abf0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8081 + 0x00000000},
8082 + {0x0000abf4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8083 + 0x00000000},
8084 + {0x0000abf8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8085 + 0x00000000},
8086 + {0x0000abfc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8087 + 0x00000000},
8088 + {0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004,
8089 + 0x00000004},
8090 + {0x0000a20c, 0x00000014, 0x00000014, 0x00000000, 0x00000000,
8091 + 0x0001f000},
8092 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
8093 + 0x1883800a},
8094 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
8095 + 0x00000000},
8096 + {0x0000a250, 0x001ff000, 0x001ff000, 0x001ca000, 0x001ca000,
8097 + 0x001da000},
8098 + {0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652,
8099 + 0x0a82a652},
8100 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
8101 + 0x00000000},
8102 + {0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201,
8103 + 0x00000000},
8104 + {0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408,
8105 + 0x00000000},
8106 + {0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a,
8107 + 0x00000000},
8108 + {0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818,
8109 + 0x00000000},
8110 + {0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858,
8111 + 0x00000000},
8112 + {0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859,
8113 + 0x00000000},
8114 + {0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b,
8115 + 0x00000000},
8116 + {0x0000a320, 0x00000000, 0x00000000, 0x0002c89a, 0x0002c89a,
8117 + 0x00000000},
8118 + {0x0000a324, 0x00000000, 0x00000000, 0x0002e89b, 0x0002e89b,
8119 + 0x00000000},
8120 + {0x0000a328, 0x00000000, 0x00000000, 0x0003089c, 0x0003089c,
8121 + 0x00000000},
8122 + {0x0000a32c, 0x00000000, 0x00000000, 0x0003289d, 0x0003289d,
8123 + 0x00000000},
8124 + {0x0000a330, 0x00000000, 0x00000000, 0x0003489e, 0x0003489e,
8125 + 0x00000000},
8126 + {0x0000a334, 0x00000000, 0x00000000, 0x000388de, 0x000388de,
8127 + 0x00000000},
8128 + {0x0000a338, 0x00000000, 0x00000000, 0x0003b91e, 0x0003b91e,
8129 + 0x00000000},
8130 + {0x0000a33c, 0x00000000, 0x00000000, 0x0003d95e, 0x0003d95e,
8131 + 0x00000000},
8132 + {0x0000a340, 0x00000000, 0x00000000, 0x000419df, 0x000419df,
8133 + 0x00000000},
8134 + {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
8135 + 0x00000000},
8136 + {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e,
8137 + 0x7999aa0e},
8138 +};
8139 +
8140 +static const u_int32_t ar9285Common_9285[][2] = {
8141 + {0x0000000c, 0x00000000},
8142 + {0x00000030, 0x00020045},
8143 + {0x00000034, 0x00000005},
8144 + {0x00000040, 0x00000000},
8145 + {0x00000044, 0x00000008},
8146 + {0x00000048, 0x00000008},
8147 + {0x0000004c, 0x00000010},
8148 + {0x00000050, 0x00000000},
8149 + {0x00000054, 0x0000001f},
8150 + {0x00000800, 0x00000000},
8151 + {0x00000804, 0x00000000},
8152 + {0x00000808, 0x00000000},
8153 + {0x0000080c, 0x00000000},
8154 + {0x00000810, 0x00000000},
8155 + {0x00000814, 0x00000000},
8156 + {0x00000818, 0x00000000},
8157 + {0x0000081c, 0x00000000},
8158 + {0x00000820, 0x00000000},
8159 + {0x00000824, 0x00000000},
8160 + {0x00001040, 0x002ffc0f},
8161 + {0x00001044, 0x002ffc0f},
8162 + {0x00001048, 0x002ffc0f},
8163 + {0x0000104c, 0x002ffc0f},
8164 + {0x00001050, 0x002ffc0f},
8165 + {0x00001054, 0x002ffc0f},
8166 + {0x00001058, 0x002ffc0f},
8167 + {0x0000105c, 0x002ffc0f},
8168 + {0x00001060, 0x002ffc0f},
8169 + {0x00001064, 0x002ffc0f},
8170 + {0x00001230, 0x00000000},
8171 + {0x00001270, 0x00000000},
8172 + {0x00001038, 0x00000000},
8173 + {0x00001078, 0x00000000},
8174 + {0x000010b8, 0x00000000},
8175 + {0x000010f8, 0x00000000},
8176 + {0x00001138, 0x00000000},
8177 + {0x00001178, 0x00000000},
8178 + {0x000011b8, 0x00000000},
8179 + {0x000011f8, 0x00000000},
8180 + {0x00001238, 0x00000000},
8181 + {0x00001278, 0x00000000},
8182 + {0x000012b8, 0x00000000},
8183 + {0x000012f8, 0x00000000},
8184 + {0x00001338, 0x00000000},
8185 + {0x00001378, 0x00000000},
8186 + {0x000013b8, 0x00000000},
8187 + {0x000013f8, 0x00000000},
8188 + {0x00001438, 0x00000000},
8189 + {0x00001478, 0x00000000},
8190 + {0x000014b8, 0x00000000},
8191 + {0x000014f8, 0x00000000},
8192 + {0x00001538, 0x00000000},
8193 + {0x00001578, 0x00000000},
8194 + {0x000015b8, 0x00000000},
8195 + {0x000015f8, 0x00000000},
8196 + {0x00001638, 0x00000000},
8197 + {0x00001678, 0x00000000},
8198 + {0x000016b8, 0x00000000},
8199 + {0x000016f8, 0x00000000},
8200 + {0x00001738, 0x00000000},
8201 + {0x00001778, 0x00000000},
8202 + {0x000017b8, 0x00000000},
8203 + {0x000017f8, 0x00000000},
8204 + {0x0000103c, 0x00000000},
8205 + {0x0000107c, 0x00000000},
8206 + {0x000010bc, 0x00000000},
8207 + {0x000010fc, 0x00000000},
8208 + {0x0000113c, 0x00000000},
8209 + {0x0000117c, 0x00000000},
8210 + {0x000011bc, 0x00000000},
8211 + {0x000011fc, 0x00000000},
8212 + {0x0000123c, 0x00000000},
8213 + {0x0000127c, 0x00000000},
8214 + {0x000012bc, 0x00000000},
8215 + {0x000012fc, 0x00000000},
8216 + {0x0000133c, 0x00000000},
8217 + {0x0000137c, 0x00000000},
8218 + {0x000013bc, 0x00000000},
8219 + {0x000013fc, 0x00000000},
8220 + {0x0000143c, 0x00000000},
8221 + {0x0000147c, 0x00000000},
8222 + {0x00004030, 0x00000002},
8223 + {0x0000403c, 0x00000002},
8224 + {0x00004024, 0x0000001f},
8225 + {0x00004060, 0x00000000},
8226 + {0x00004064, 0x00000000},
8227 + {0x00007010, 0x00000031},
8228 + {0x00007034, 0x00000002},
8229 + {0x00007038, 0x000004c2},
8230 + {0x00008004, 0x00000000},
8231 + {0x00008008, 0x00000000},
8232 + {0x0000800c, 0x00000000},
8233 + {0x00008018, 0x00000700},
8234 + {0x00008020, 0x00000000},
8235 + {0x00008038, 0x00000000},
8236 + {0x0000803c, 0x00000000},
8237 + {0x00008048, 0x00000000},
8238 + {0x00008054, 0x00000000},
8239 + {0x00008058, 0x00000000},
8240 + {0x0000805c, 0x000fc78f},
8241 + {0x00008060, 0x0000000f},
8242 + {0x00008064, 0x00000000},
8243 + {0x00008070, 0x00000000},
8244 + {0x000080c0, 0x2a80001a},
8245 + {0x000080c4, 0x05dc01e0},
8246 + {0x000080c8, 0x1f402710},
8247 + {0x000080cc, 0x01f40000},
8248 + {0x000080d0, 0x00001e00},
8249 + {0x000080d4, 0x00000000},
8250 + {0x000080d8, 0x00400000},
8251 + {0x000080e0, 0xffffffff},
8252 + {0x000080e4, 0x0000ffff},
8253 + {0x000080e8, 0x003f3f3f},
8254 + {0x000080ec, 0x00000000},
8255 + {0x000080f0, 0x00000000},
8256 + {0x000080f4, 0x00000000},
8257 + {0x000080f8, 0x00000000},
8258 + {0x000080fc, 0x00020000},
8259 + {0x00008100, 0x00020000},
8260 + {0x00008104, 0x00000001},
8261 + {0x00008108, 0x00000052},
8262 + {0x0000810c, 0x00000000},
8263 + {0x00008110, 0x00000168},
8264 + {0x00008118, 0x000100aa},
8265 + {0x0000811c, 0x00003210},
8266 + {0x00008120, 0x08f04800},
8267 + {0x00008124, 0x00000000},
8268 + {0x00008128, 0x00000000},
8269 + {0x0000812c, 0x00000000},
8270 + {0x00008130, 0x00000000},
8271 + {0x00008134, 0x00000000},
8272 + {0x00008138, 0x00000000},
8273 + {0x0000813c, 0x00000000},
8274 + {0x00008144, 0x00000000},
8275 + {0x00008168, 0x00000000},
8276 + {0x0000816c, 0x00000000},
8277 + {0x00008170, 0x32143320},
8278 + {0x00008174, 0xfaa4fa50},
8279 + {0x00008178, 0x00000100},
8280 + {0x0000817c, 0x00000000},
8281 + {0x000081c0, 0x00000000},
8282 + {0x000081d0, 0x00003210},
8283 + {0x000081ec, 0x00000000},
8284 + {0x000081f0, 0x00000000},
8285 + {0x000081f4, 0x00000000},
8286 + {0x000081f8, 0x00000000},
8287 + {0x000081fc, 0x00000000},
8288 + {0x00008200, 0x00000000},
8289 + {0x00008204, 0x00000000},
8290 + {0x00008208, 0x00000000},
8291 + {0x0000820c, 0x00000000},
8292 + {0x00008210, 0x00000000},
8293 + {0x00008214, 0x00000000},
8294 + {0x00008218, 0x00000000},
8295 + {0x0000821c, 0x00000000},
8296 + {0x00008220, 0x00000000},
8297 + {0x00008224, 0x00000000},
8298 + {0x00008228, 0x00000000},
8299 + {0x0000822c, 0x00000000},
8300 + {0x00008230, 0x00000000},
8301 + {0x00008234, 0x00000000},
8302 + {0x00008238, 0x00000000},
8303 + {0x0000823c, 0x00000000},
8304 + {0x00008240, 0x00100000},
8305 + {0x00008244, 0x0010f400},
8306 + {0x00008248, 0x00000100},
8307 + {0x0000824c, 0x0001e800},
8308 + {0x00008250, 0x00000000},
8309 + {0x00008254, 0x00000000},
8310 + {0x00008258, 0x00000000},
8311 + {0x0000825c, 0x400000ff},
8312 + {0x00008260, 0x00080922},
8313 + {0x00008264, 0xa8a00010},
8314 + {0x00008270, 0x00000000},
8315 + {0x00008274, 0x40000000},
8316 + {0x00008278, 0x003e4180},
8317 + {0x0000827c, 0x00000000},
8318 + {0x00008284, 0x0000002c},
8319 + {0x00008288, 0x0000002c},
8320 + {0x0000828c, 0x00000000},
8321 + {0x00008294, 0x00000000},
8322 + {0x00008298, 0x00000000},
8323 + {0x0000829c, 0x00000000},
8324 + {0x00008300, 0x00000040},
8325 + {0x00008314, 0x00000000},
8326 + {0x00008328, 0x00000000},
8327 + {0x0000832c, 0x00000001},
8328 + {0x00008330, 0x00000302},
8329 + {0x00008334, 0x00000e00},
8330 + {0x00008338, 0x00000000},
8331 + {0x0000833c, 0x00000000},
8332 + {0x00008340, 0x00010380},
8333 + {0x00008344, 0x00481043},
8334 + {0x00009808, 0x00000000},
8335 + {0x0000980c, 0xafe68e30},
8336 + {0x00009810, 0xfd14e000},
8337 + {0x00009814, 0x9c0a9f6b},
8338 + {0x0000981c, 0x00000000},
8339 + {0x0000982c, 0x0000a000},
8340 + {0x00009830, 0x00000000},
8341 + {0x0000983c, 0x00200400},
8342 + {0x0000984c, 0x0040233c},
8343 + {0x00009854, 0x00000044},
8344 + {0x00009900, 0x00000000},
8345 + {0x00009904, 0x00000000},
8346 + {0x00009908, 0x00000000},
8347 + {0x0000990c, 0x00000000},
8348 + {0x00009910, 0x01002310},
8349 + {0x0000991c, 0x10000fff},
8350 + {0x00009920, 0x04900000},
8351 + {0x00009928, 0x00000001},
8352 + {0x0000992c, 0x00000004},
8353 + {0x00009934, 0x1e1f2022},
8354 + {0x00009938, 0x0a0b0c0d},
8355 + {0x0000993c, 0x00000000},
8356 + {0x00009940, 0x14750604},
8357 + {0x00009948, 0x9280c00a},
8358 + {0x0000994c, 0x00020028},
8359 + {0x00009954, 0x5f3ca3de},
8360 + {0x00009958, 0x2108ecff},
8361 + {0x00009968, 0x000003ce},
8362 + {0x00009970, 0x1927b515},
8363 + {0x00009974, 0x00000000},
8364 + {0x00009978, 0x00000001},
8365 + {0x0000997c, 0x00000000},
8366 + {0x00009980, 0x00000000},
8367 + {0x00009984, 0x00000000},
8368 + {0x00009988, 0x00000000},
8369 + {0x0000998c, 0x00000000},
8370 + {0x00009990, 0x00000000},
8371 + {0x00009994, 0x00000000},
8372 + {0x00009998, 0x00000000},
8373 + {0x0000999c, 0x00000000},
8374 + {0x000099a0, 0x00000000},
8375 + {0x000099a4, 0x00000001},
8376 + {0x000099a8, 0x201fff00},
8377 + {0x000099ac, 0x2def0a00},
8378 + {0x000099b0, 0x03051000},
8379 + {0x000099b4, 0x00000820},
8380 + {0x000099dc, 0x00000000},
8381 + {0x000099e0, 0x00000000},
8382 + {0x000099e4, 0xaaaaaaaa},
8383 + {0x000099e8, 0x3c466478},
8384 + {0x000099ec, 0x0cc80caa},
8385 + {0x000099f0, 0x00000000},
8386 + {0x0000a208, 0x803e6788},
8387 + {0x0000a210, 0x4080a333},
8388 + {0x0000a214, 0x00206c10},
8389 + {0x0000a218, 0x009c4060},
8390 + {0x0000a220, 0x01834061},
8391 + {0x0000a224, 0x00000400},
8392 + {0x0000a228, 0x000003b5},
8393 + {0x0000a22c, 0x00000000},
8394 + {0x0000a234, 0x20202020},
8395 + {0x0000a238, 0x20202020},
8396 + {0x0000a244, 0x00000000},
8397 + {0x0000a248, 0xfffffffc},
8398 + {0x0000a24c, 0x00000000},
8399 + {0x0000a254, 0x00000000},
8400 + {0x0000a258, 0x0ccb5380},
8401 + {0x0000a25c, 0x15151501},
8402 + {0x0000a260, 0xdfa90f01},
8403 + {0x0000a268, 0x00000000},
8404 + {0x0000a26c, 0x0ebae9e6},
8405 + {0x0000d270, 0x0d820820},
8406 + {0x0000a278, 0x39ce739c},
8407 + {0x0000a27c, 0x050e039c},
8408 + {0x0000d35c, 0x07ffffef},
8409 + {0x0000d360, 0x0fffffe7},
8410 + {0x0000d364, 0x17ffffe5},
8411 + {0x0000d368, 0x1fffffe4},
8412 + {0x0000d36c, 0x37ffffe3},
8413 + {0x0000d370, 0x3fffffe3},
8414 + {0x0000d374, 0x57ffffe3},
8415 + {0x0000d378, 0x5fffffe2},
8416 + {0x0000d37c, 0x7fffffe2},
8417 + {0x0000d380, 0x7f3c7bba},
8418 + {0x0000d384, 0xf3307ff0},
8419 + {0x0000a388, 0x0c000000},
8420 + {0x0000a38c, 0x20202020},
8421 + {0x0000a390, 0x20202020},
8422 + {0x0000a394, 0x39ce739c},
8423 + {0x0000a398, 0x0000039c},
8424 + {0x0000a39c, 0x00000001},
8425 + {0x0000a3a0, 0x00000000},
8426 + {0x0000a3a4, 0x00000000},
8427 + {0x0000a3a8, 0x00000000},
8428 + {0x0000a3ac, 0x00000000},
8429 + {0x0000a3b0, 0x00000000},
8430 + {0x0000a3b4, 0x00000000},
8431 + {0x0000a3b8, 0x00000000},
8432 + {0x0000a3bc, 0x00000000},
8433 + {0x0000a3c0, 0x00000000},
8434 + {0x0000a3c4, 0x00000000},
8435 + {0x0000a3cc, 0x20202020},
8436 + {0x0000a3d0, 0x20202020},
8437 + {0x0000a3d4, 0x20202020},
8438 + {0x0000a3dc, 0x39ce739c},
8439 + {0x0000a3e0, 0x0000039c},
8440 + {0x0000a3e4, 0x00000000},
8441 + {0x0000a3e8, 0x18c43433},
8442 + {0x0000a3ec, 0x00f70081},
8443 + {0x00007800, 0x00140000},
8444 + {0x00007804, 0x0e4548d8},
8445 + {0x00007808, 0x54214514},
8446 + {0x0000780c, 0x02025820},
8447 + {0x00007810, 0x71c0d388},
8448 + {0x00007814, 0x924934a8},
8449 + {0x0000781c, 0x00000000},
8450 + {0x00007820, 0x00000c04},
8451 + {0x00007824, 0x00d86fff},
8452 + {0x00007828, 0x26d2491b},
8453 + {0x0000782c, 0x6e36d97b},
8454 + {0x00007830, 0xedb6d96c},
8455 + {0x00007834, 0x71400086},
8456 + {0x00007838, 0xfac68800},
8457 + {0x0000783c, 0x0001fffe},
8458 + {0x00007840, 0xffeb1a20},
8459 + {0x00007844, 0x000c0db6},
8460 + {0x00007848, 0x6db61b6f},
8461 + {0x0000784c, 0x6d9b66db},
8462 + {0x00007850, 0x6d8c6dba},
8463 + {0x00007854, 0x00040000},
8464 + {0x00007858, 0xdb003012},
8465 + {0x0000785c, 0x04924914},
8466 + {0x00007860, 0x21084210},
8467 + {0x00007864, 0xf7d7ffde},
8468 + {0x00007868, 0xc2034080},
8469 + {0x0000786c, 0x48609eb4},
8470 + {0x00007870, 0x10142c00},
8471 +};
8472 +
8473 +static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
8474 + {0x00004040, 0x9248fd00},
8475 + {0x00004040, 0x24924924},
8476 + {0x00004040, 0xa8000019},
8477 + {0x00004040, 0x13160820},
8478 + {0x00004040, 0xe5980560},
8479 + {0x00004040, 0xc01dcffd},
8480 + {0x00004040, 0x1aaabe41},
8481 + {0x00004040, 0xbe105554},
8482 + {0x00004040, 0x00043007},
8483 + {0x00004044, 0x00000000},
8484 +};
8485 +
8486 +static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285[][2] = {
8487 + {0x00004040, 0x9248fd00},
8488 + {0x00004040, 0x24924924},
8489 + {0x00004040, 0xa8000019},
8490 + {0x00004040, 0x13160820},
8491 + {0x00004040, 0xe5980560},
8492 + {0x00004040, 0xc01dcffc},
8493 + {0x00004040, 0x1aaabe41},
8494 + {0x00004040, 0xbe105554},
8495 + {0x00004040, 0x00043007},
8496 + {0x00004044, 0x00000000},
8497 +};
8498 +
8499 +/* AR9285 v1_2 PCI Register Writes. Created: 04/13/09 */
8500 +static const u_int32_t ar9285Modes_9285_1_2[][6] = {
8501 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
8502 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
8503 + 0x000001e0},
8504 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
8505 + 0x000001e0},
8506 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
8507 + 0x00001180},
8508 + {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
8509 + 0x00000008},
8510 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00,
8511 + 0x06e006e0},
8512 + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b,
8513 + 0x0988004f},
8514 + {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440,
8515 + 0x00006880},
8516 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
8517 + 0x00000303},
8518 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
8519 + 0x02020200},
8520 + {0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e,
8521 + 0x01000e0e},
8522 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
8523 + 0x0a020001},
8524 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
8525 + 0x00000e0e},
8526 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
8527 + 0x00000007},
8528 + {0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e,
8529 + 0x206a012e},
8530 + {0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620,
8531 + 0x037216a0},
8532 + {0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053,
8533 + 0x00001059},
8534 + {0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053,
8535 + 0x00001059},
8536 + {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2,
8537 + 0x6d4000e2},
8538 + {0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e,
8539 + 0x7ec84d2e},
8540 + {0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e,
8541 + 0x3139605e},
8542 + {0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20,
8543 + 0x00058d18},
8544 + {0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00,
8545 + 0x0001ce00},
8546 + {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0,
8547 + 0x5ac640d0},
8548 + {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881,
8549 + 0x06903881},
8550 + {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898,
8551 + 0x000007d0},
8552 + {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b,
8553 + 0x00000016},
8554 + {0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d,
8555 + 0xd00a800d},
8556 + {0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020,
8557 + 0xffbc1010},
8558 + {0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
8559 + 0x00000000},
8560 + {0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
8561 + 0x00000000},
8562 + {0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c,
8563 + 0x0000421c},
8564 + {0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00,
8565 + 0x00000c00},
8566 + {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4,
8567 + 0x05eea6d4},
8568 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
8569 + 0x06336f77},
8570 + {0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f,
8571 + 0x6af6532f},
8572 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
8573 + 0x08f186c8},
8574 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
8575 + 0x00046384},
8576 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
8577 + 0x00000000},
8578 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
8579 + 0x00000000},
8580 + {0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084,
8581 + 0x00000000},
8582 + {0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088,
8583 + 0x00000000},
8584 + {0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c,
8585 + 0x00000000},
8586 + {0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100,
8587 + 0x00000000},
8588 + {0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104,
8589 + 0x00000000},
8590 + {0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108,
8591 + 0x00000000},
8592 + {0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c,
8593 + 0x00000000},
8594 + {0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110,
8595 + 0x00000000},
8596 + {0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114,
8597 + 0x00000000},
8598 + {0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180,
8599 + 0x00000000},
8600 + {0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184,
8601 + 0x00000000},
8602 + {0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188,
8603 + 0x00000000},
8604 + {0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c,
8605 + 0x00000000},
8606 + {0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190,
8607 + 0x00000000},
8608 + {0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194,
8609 + 0x00000000},
8610 + {0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0,
8611 + 0x00000000},
8612 + {0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c,
8613 + 0x00000000},
8614 + {0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8,
8615 + 0x00000000},
8616 + {0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284,
8617 + 0x00000000},
8618 + {0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288,
8619 + 0x00000000},
8620 + {0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224,
8621 + 0x00000000},
8622 + {0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290,
8623 + 0x00000000},
8624 + {0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300,
8625 + 0x00000000},
8626 + {0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304,
8627 + 0x00000000},
8628 + {0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308,
8629 + 0x00000000},
8630 + {0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c,
8631 + 0x00000000},
8632 + {0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380,
8633 + 0x00000000},
8634 + {0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384,
8635 + 0x00000000},
8636 + {0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700,
8637 + 0x00000000},
8638 + {0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704,
8639 + 0x00000000},
8640 + {0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708,
8641 + 0x00000000},
8642 + {0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c,
8643 + 0x00000000},
8644 + {0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780,
8645 + 0x00000000},
8646 + {0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784,
8647 + 0x00000000},
8648 + {0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00,
8649 + 0x00000000},
8650 + {0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04,
8651 + 0x00000000},
8652 + {0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08,
8653 + 0x00000000},
8654 + {0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c,
8655 + 0x00000000},
8656 + {0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80,
8657 + 0x00000000},
8658 + {0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84,
8659 + 0x00000000},
8660 + {0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88,
8661 + 0x00000000},
8662 + {0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c,
8663 + 0x00000000},
8664 + {0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90,
8665 + 0x00000000},
8666 + {0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80,
8667 + 0x00000000},
8668 + {0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84,
8669 + 0x00000000},
8670 + {0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88,
8671 + 0x00000000},
8672 + {0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c,
8673 + 0x00000000},
8674 + {0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90,
8675 + 0x00000000},
8676 + {0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c,
8677 + 0x00000000},
8678 + {0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310,
8679 + 0x00000000},
8680 + {0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384,
8681 + 0x00000000},
8682 + {0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388,
8683 + 0x00000000},
8684 + {0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324,
8685 + 0x00000000},
8686 + {0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704,
8687 + 0x00000000},
8688 + {0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4,
8689 + 0x00000000},
8690 + {0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8,
8691 + 0x00000000},
8692 + {0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710,
8693 + 0x00000000},
8694 + {0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714,
8695 + 0x00000000},
8696 + {0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720,
8697 + 0x00000000},
8698 + {0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724,
8699 + 0x00000000},
8700 + {0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728,
8701 + 0x00000000},
8702 + {0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c,
8703 + 0x00000000},
8704 + {0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0,
8705 + 0x00000000},
8706 + {0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4,
8707 + 0x00000000},
8708 + {0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8,
8709 + 0x00000000},
8710 + {0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0,
8711 + 0x00000000},
8712 + {0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4,
8713 + 0x00000000},
8714 + {0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8,
8715 + 0x00000000},
8716 + {0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5,
8717 + 0x00000000},
8718 + {0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9,
8719 + 0x00000000},
8720 + {0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad,
8721 + 0x00000000},
8722 + {0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1,
8723 + 0x00000000},
8724 + {0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5,
8725 + 0x00000000},
8726 + {0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9,
8727 + 0x00000000},
8728 + {0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5,
8729 + 0x00000000},
8730 + {0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9,
8731 + 0x00000000},
8732 + {0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1,
8733 + 0x00000000},
8734 + {0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5,
8735 + 0x00000000},
8736 + {0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9,
8737 + 0x00000000},
8738 + {0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6,
8739 + 0x00000000},
8740 + {0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca,
8741 + 0x00000000},
8742 + {0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce,
8743 + 0x00000000},
8744 + {0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2,
8745 + 0x00000000},
8746 + {0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6,
8747 + 0x00000000},
8748 + {0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3,
8749 + 0x00000000},
8750 + {0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7,
8751 + 0x00000000},
8752 + {0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb,
8753 + 0x00000000},
8754 + {0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf,
8755 + 0x00000000},
8756 + {0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7,
8757 + 0x00000000},
8758 + {0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8759 + 0x00000000},
8760 + {0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8761 + 0x00000000},
8762 + {0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8763 + 0x00000000},
8764 + {0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8765 + 0x00000000},
8766 + {0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8767 + 0x00000000},
8768 + {0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8769 + 0x00000000},
8770 + {0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8771 + 0x00000000},
8772 + {0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8773 + 0x00000000},
8774 + {0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8775 + 0x00000000},
8776 + {0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8777 + 0x00000000},
8778 + {0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8779 + 0x00000000},
8780 + {0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8781 + 0x00000000},
8782 + {0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8783 + 0x00000000},
8784 + {0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8785 + 0x00000000},
8786 + {0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8787 + 0x00000000},
8788 + {0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8789 + 0x00000000},
8790 + {0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8791 + 0x00000000},
8792 + {0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8793 + 0x00000000},
8794 + {0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8795 + 0x00000000},
8796 + {0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8797 + 0x00000000},
8798 + {0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8799 + 0x00000000},
8800 + {0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8801 + 0x00000000},
8802 + {0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8803 + 0x00000000},
8804 + {0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8805 + 0x00000000},
8806 + {0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8807 + 0x00000000},
8808 + {0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8809 + 0x00000000},
8810 + {0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8811 + 0x00000000},
8812 + {0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8813 + 0x00000000},
8814 + {0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8815 + 0x00000000},
8816 + {0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8817 + 0x00000000},
8818 + {0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8819 + 0x00000000},
8820 + {0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8821 + 0x00000000},
8822 + {0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8823 + 0x00000000},
8824 + {0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8825 + 0x00000000},
8826 + {0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8827 + 0x00000000},
8828 + {0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8829 + 0x00000000},
8830 + {0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8831 + 0x00000000},
8832 + {0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8833 + 0x00000000},
8834 + {0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8835 + 0x00000000},
8836 + {0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084,
8837 + 0x00000000},
8838 + {0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088,
8839 + 0x00000000},
8840 + {0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c,
8841 + 0x00000000},
8842 + {0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100,
8843 + 0x00000000},
8844 + {0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104,
8845 + 0x00000000},
8846 + {0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108,
8847 + 0x00000000},
8848 + {0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c,
8849 + 0x00000000},
8850 + {0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110,
8851 + 0x00000000},
8852 + {0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114,
8853 + 0x00000000},
8854 + {0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180,
8855 + 0x00000000},
8856 + {0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184,
8857 + 0x00000000},
8858 + {0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188,
8859 + 0x00000000},
8860 + {0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c,
8861 + 0x00000000},
8862 + {0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190,
8863 + 0x00000000},
8864 + {0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194,
8865 + 0x00000000},
8866 + {0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0,
8867 + 0x00000000},
8868 + {0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c,
8869 + 0x00000000},
8870 + {0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8,
8871 + 0x00000000},
8872 + {0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284,
8873 + 0x00000000},
8874 + {0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288,
8875 + 0x00000000},
8876 + {0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224,
8877 + 0x00000000},
8878 + {0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290,
8879 + 0x00000000},
8880 + {0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300,
8881 + 0x00000000},
8882 + {0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304,
8883 + 0x00000000},
8884 + {0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308,
8885 + 0x00000000},
8886 + {0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c,
8887 + 0x00000000},
8888 + {0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380,
8889 + 0x00000000},
8890 + {0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384,
8891 + 0x00000000},
8892 + {0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700,
8893 + 0x00000000},
8894 + {0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704,
8895 + 0x00000000},
8896 + {0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708,
8897 + 0x00000000},
8898 + {0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c,
8899 + 0x00000000},
8900 + {0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780,
8901 + 0x00000000},
8902 + {0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784,
8903 + 0x00000000},
8904 + {0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00,
8905 + 0x00000000},
8906 + {0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04,
8907 + 0x00000000},
8908 + {0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08,
8909 + 0x00000000},
8910 + {0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c,
8911 + 0x00000000},
8912 + {0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80,
8913 + 0x00000000},
8914 + {0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84,
8915 + 0x00000000},
8916 + {0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88,
8917 + 0x00000000},
8918 + {0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c,
8919 + 0x00000000},
8920 + {0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90,
8921 + 0x00000000},
8922 + {0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80,
8923 + 0x00000000},
8924 + {0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84,
8925 + 0x00000000},
8926 + {0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88,
8927 + 0x00000000},
8928 + {0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c,
8929 + 0x00000000},
8930 + {0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90,
8931 + 0x00000000},
8932 + {0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c,
8933 + 0x00000000},
8934 + {0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310,
8935 + 0x00000000},
8936 + {0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384,
8937 + 0x00000000},
8938 + {0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388,
8939 + 0x00000000},
8940 + {0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324,
8941 + 0x00000000},
8942 + {0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704,
8943 + 0x00000000},
8944 + {0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4,
8945 + 0x00000000},
8946 + {0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8,
8947 + 0x00000000},
8948 + {0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710,
8949 + 0x00000000},
8950 + {0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714,
8951 + 0x00000000},
8952 + {0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720,
8953 + 0x00000000},
8954 + {0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724,
8955 + 0x00000000},
8956 + {0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728,
8957 + 0x00000000},
8958 + {0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c,
8959 + 0x00000000},
8960 + {0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0,
8961 + 0x00000000},
8962 + {0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4,
8963 + 0x00000000},
8964 + {0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8,
8965 + 0x00000000},
8966 + {0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0,
8967 + 0x00000000},
8968 + {0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4,
8969 + 0x00000000},
8970 + {0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8,
8971 + 0x00000000},
8972 + {0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5,
8973 + 0x00000000},
8974 + {0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9,
8975 + 0x00000000},
8976 + {0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad,
8977 + 0x00000000},
8978 + {0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1,
8979 + 0x00000000},
8980 + {0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5,
8981 + 0x00000000},
8982 + {0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9,
8983 + 0x00000000},
8984 + {0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5,
8985 + 0x00000000},
8986 + {0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9,
8987 + 0x00000000},
8988 + {0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1,
8989 + 0x00000000},
8990 + {0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5,
8991 + 0x00000000},
8992 + {0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9,
8993 + 0x00000000},
8994 + {0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6,
8995 + 0x00000000},
8996 + {0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca,
8997 + 0x00000000},
8998 + {0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce,
8999 + 0x00000000},
9000 + {0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2,
9001 + 0x00000000},
9002 + {0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6,
9003 + 0x00000000},
9004 + {0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3,
9005 + 0x00000000},
9006 + {0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7,
9007 + 0x00000000},
9008 + {0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb,
9009 + 0x00000000},
9010 + {0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf,
9011 + 0x00000000},
9012 + {0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7,
9013 + 0x00000000},
9014 + {0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9015 + 0x00000000},
9016 + {0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9017 + 0x00000000},
9018 + {0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9019 + 0x00000000},
9020 + {0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9021 + 0x00000000},
9022 + {0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9023 + 0x00000000},
9024 + {0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9025 + 0x00000000},
9026 + {0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9027 + 0x00000000},
9028 + {0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9029 + 0x00000000},
9030 + {0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9031 + 0x00000000},
9032 + {0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9033 + 0x00000000},
9034 + {0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9035 + 0x00000000},
9036 + {0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9037 + 0x00000000},
9038 + {0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9039 + 0x00000000},
9040 + {0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9041 + 0x00000000},
9042 + {0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9043 + 0x00000000},
9044 + {0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9045 + 0x00000000},
9046 + {0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9047 + 0x00000000},
9048 + {0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9049 + 0x00000000},
9050 + {0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9051 + 0x00000000},
9052 + {0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9053 + 0x00000000},
9054 + {0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9055 + 0x00000000},
9056 + {0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9057 + 0x00000000},
9058 + {0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9059 + 0x00000000},
9060 + {0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9061 + 0x00000000},
9062 + {0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9063 + 0x00000000},
9064 + {0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9065 + 0x00000000},
9066 + {0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9067 + 0x00000000},
9068 + {0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9069 + 0x00000000},
9070 + {0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9071 + 0x00000000},
9072 + {0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9073 + 0x00000000},
9074 + {0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9075 + 0x00000000},
9076 + {0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9077 + 0x00000000},
9078 + {0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9079 + 0x00000000},
9080 + {0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9081 + 0x00000000},
9082 + {0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9083 + 0x00000000},
9084 + {0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9085 + 0x00000000},
9086 + {0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9087 + 0x00000000},
9088 + {0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9089 + 0x00000000},
9090 + {0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9091 + 0x00000000},
9092 + {0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004,
9093 + 0x00000004},
9094 + {0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000,
9095 + 0x0001f000},
9096 + {0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000,
9097 + 0x0001f000},
9098 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
9099 + 0x1883800a},
9100 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
9101 + 0x00000000},
9102 + {0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000,
9103 + 0x0004a000},
9104 + {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e,
9105 + 0x7999aa0e},
9106 +};
9107 +
9108 +static const u_int32_t ar9285Common_9285_1_2[][2] = {
9109 + {0x0000000c, 0x00000000},
9110 + {0x00000030, 0x00020045},
9111 + {0x00000034, 0x00000005},
9112 + {0x00000040, 0x00000000},
9113 + {0x00000044, 0x00000008},
9114 + {0x00000048, 0x00000008},
9115 + {0x0000004c, 0x00000010},
9116 + {0x00000050, 0x00000000},
9117 + {0x00000054, 0x0000001f},
9118 + {0x00000800, 0x00000000},
9119 + {0x00000804, 0x00000000},
9120 + {0x00000808, 0x00000000},
9121 + {0x0000080c, 0x00000000},
9122 + {0x00000810, 0x00000000},
9123 + {0x00000814, 0x00000000},
9124 + {0x00000818, 0x00000000},
9125 + {0x0000081c, 0x00000000},
9126 + {0x00000820, 0x00000000},
9127 + {0x00000824, 0x00000000},
9128 + {0x00001040, 0x002ffc0f},
9129 + {0x00001044, 0x002ffc0f},
9130 + {0x00001048, 0x002ffc0f},
9131 + {0x0000104c, 0x002ffc0f},
9132 + {0x00001050, 0x002ffc0f},
9133 + {0x00001054, 0x002ffc0f},
9134 + {0x00001058, 0x002ffc0f},
9135 + {0x0000105c, 0x002ffc0f},
9136 + {0x00001060, 0x002ffc0f},
9137 + {0x00001064, 0x002ffc0f},
9138 + {0x00001230, 0x00000000},
9139 + {0x00001270, 0x00000000},
9140 + {0x00001038, 0x00000000},
9141 + {0x00001078, 0x00000000},
9142 + {0x000010b8, 0x00000000},
9143 + {0x000010f8, 0x00000000},
9144 + {0x00001138, 0x00000000},
9145 + {0x00001178, 0x00000000},
9146 + {0x000011b8, 0x00000000},
9147 + {0x000011f8, 0x00000000},
9148 + {0x00001238, 0x00000000},
9149 + {0x00001278, 0x00000000},
9150 + {0x000012b8, 0x00000000},
9151 + {0x000012f8, 0x00000000},
9152 + {0x00001338, 0x00000000},
9153 + {0x00001378, 0x00000000},
9154 + {0x000013b8, 0x00000000},
9155 + {0x000013f8, 0x00000000},
9156 + {0x00001438, 0x00000000},
9157 + {0x00001478, 0x00000000},
9158 + {0x000014b8, 0x00000000},
9159 + {0x000014f8, 0x00000000},
9160 + {0x00001538, 0x00000000},
9161 + {0x00001578, 0x00000000},
9162 + {0x000015b8, 0x00000000},
9163 + {0x000015f8, 0x00000000},
9164 + {0x00001638, 0x00000000},
9165 + {0x00001678, 0x00000000},
9166 + {0x000016b8, 0x00000000},
9167 + {0x000016f8, 0x00000000},
9168 + {0x00001738, 0x00000000},
9169 + {0x00001778, 0x00000000},
9170 + {0x000017b8, 0x00000000},
9171 + {0x000017f8, 0x00000000},
9172 + {0x0000103c, 0x00000000},
9173 + {0x0000107c, 0x00000000},
9174 + {0x000010bc, 0x00000000},
9175 + {0x000010fc, 0x00000000},
9176 + {0x0000113c, 0x00000000},
9177 + {0x0000117c, 0x00000000},
9178 + {0x000011bc, 0x00000000},
9179 + {0x000011fc, 0x00000000},
9180 + {0x0000123c, 0x00000000},
9181 + {0x0000127c, 0x00000000},
9182 + {0x000012bc, 0x00000000},
9183 + {0x000012fc, 0x00000000},
9184 + {0x0000133c, 0x00000000},
9185 + {0x0000137c, 0x00000000},
9186 + {0x000013bc, 0x00000000},
9187 + {0x000013fc, 0x00000000},
9188 + {0x0000143c, 0x00000000},
9189 + {0x0000147c, 0x00000000},
9190 + {0x00004030, 0x00000002},
9191 + {0x0000403c, 0x00000002},
9192 + {0x00004024, 0x0000001f},
9193 + {0x00004060, 0x00000000},
9194 + {0x00004064, 0x00000000},
9195 + {0x00007010, 0x00000031},
9196 + {0x00007034, 0x00000002},
9197 + {0x00007038, 0x000004c2},
9198 + {0x00008004, 0x00000000},
9199 + {0x00008008, 0x00000000},
9200 + {0x0000800c, 0x00000000},
9201 + {0x00008018, 0x00000700},
9202 + {0x00008020, 0x00000000},
9203 + {0x00008038, 0x00000000},
9204 + {0x0000803c, 0x00000000},
9205 + {0x00008048, 0x00000000},
9206 + {0x00008054, 0x00000000},
9207 + {0x00008058, 0x00000000},
9208 + {0x0000805c, 0x000fc78f},
9209 + {0x00008060, 0x0000000f},
9210 + {0x00008064, 0x00000000},
9211 + {0x00008070, 0x00000000},
9212 + {0x000080c0, 0x2a80001a},
9213 + {0x000080c4, 0x05dc01e0},
9214 + {0x000080c8, 0x1f402710},
9215 + {0x000080cc, 0x01f40000},
9216 + {0x000080d0, 0x00001e00},
9217 + {0x000080d4, 0x00000000},
9218 + {0x000080d8, 0x00400000},
9219 + {0x000080e0, 0xffffffff},
9220 + {0x000080e4, 0x0000ffff},
9221 + {0x000080e8, 0x003f3f3f},
9222 + {0x000080ec, 0x00000000},
9223 + {0x000080f0, 0x00000000},
9224 + {0x000080f4, 0x00000000},
9225 + {0x000080f8, 0x00000000},
9226 + {0x000080fc, 0x00020000},
9227 + {0x00008100, 0x00020000},
9228 + {0x00008104, 0x00000001},
9229 + {0x00008108, 0x00000052},
9230 + {0x0000810c, 0x00000000},
9231 + {0x00008110, 0x00000168},
9232 + {0x00008118, 0x000100aa},
9233 + {0x0000811c, 0x00003210},
9234 + {0x00008120, 0x08f04810},
9235 + {0x00008124, 0x00000000},
9236 + {0x00008128, 0x00000000},
9237 + {0x0000812c, 0x00000000},
9238 + {0x00008130, 0x00000000},
9239 + {0x00008134, 0x00000000},
9240 + {0x00008138, 0x00000000},
9241 + {0x0000813c, 0x00000000},
9242 + {0x00008144, 0xffffffff},
9243 + {0x00008168, 0x00000000},
9244 + {0x0000816c, 0x00000000},
9245 + {0x00008170, 0x32143320},
9246 + {0x00008174, 0xfaa4fa50},
9247 + {0x00008178, 0x00000100},
9248 + {0x0000817c, 0x00000000},
9249 + {0x000081c0, 0x00000000},
9250 + {0x000081d0, 0x0000320a},
9251 + {0x000081ec, 0x00000000},
9252 + {0x000081f0, 0x00000000},
9253 + {0x000081f4, 0x00000000},
9254 + {0x000081f8, 0x00000000},
9255 + {0x000081fc, 0x00000000},
9256 + {0x00008200, 0x00000000},
9257 + {0x00008204, 0x00000000},
9258 + {0x00008208, 0x00000000},
9259 + {0x0000820c, 0x00000000},
9260 + {0x00008210, 0x00000000},
9261 + {0x00008214, 0x00000000},
9262 + {0x00008218, 0x00000000},
9263 + {0x0000821c, 0x00000000},
9264 + {0x00008220, 0x00000000},
9265 + {0x00008224, 0x00000000},
9266 + {0x00008228, 0x00000000},
9267 + {0x0000822c, 0x00000000},
9268 + {0x00008230, 0x00000000},
9269 + {0x00008234, 0x00000000},
9270 + {0x00008238, 0x00000000},
9271 + {0x0000823c, 0x00000000},
9272 + {0x00008240, 0x00100000},
9273 + {0x00008244, 0x0010f400},
9274 + {0x00008248, 0x00000100},
9275 + {0x0000824c, 0x0001e800},
9276 + {0x00008250, 0x00000000},
9277 + {0x00008254, 0x00000000},
9278 + {0x00008258, 0x00000000},
9279 + {0x0000825c, 0x400000ff},
9280 + {0x00008260, 0x00080922},
9281 + {0x00008264, 0x88a00010},
9282 + {0x00008270, 0x00000000},
9283 + {0x00008274, 0x40000000},
9284 + {0x00008278, 0x003e4180},
9285 + {0x0000827c, 0x00000000},
9286 + {0x00008284, 0x0000002c},
9287 + {0x00008288, 0x0000002c},
9288 + {0x0000828c, 0x00000000},
9289 + {0x00008294, 0x00000000},
9290 + {0x00008298, 0x00000000},
9291 + {0x0000829c, 0x00000000},
9292 + {0x00008300, 0x00000040},
9293 + {0x00008314, 0x00000000},
9294 + {0x00008328, 0x00000000},
9295 + {0x0000832c, 0x00000001},
9296 + {0x00008330, 0x00000302},
9297 + {0x00008334, 0x00000e00},
9298 + {0x00008338, 0x00ff0000},
9299 + {0x0000833c, 0x00000000},
9300 + {0x00008340, 0x00010380},
9301 + {0x00008344, 0x00481043},
9302 + {0x00009808, 0x00000000},
9303 + {0x0000980c, 0xafe68e30},
9304 + {0x00009810, 0xfd14e000},
9305 + {0x00009814, 0x9c0a9f6b},
9306 + {0x0000981c, 0x00000000},
9307 + {0x0000982c, 0x0000a000},
9308 + {0x00009830, 0x00000000},
9309 + {0x0000983c, 0x00200400},
9310 + {0x0000984c, 0x0040233c},
9311 + {0x00009854, 0x00000044},
9312 + {0x00009900, 0x00000000},
9313 + {0x00009904, 0x00000000},
9314 + {0x00009908, 0x00000000},
9315 + {0x0000990c, 0x00000000},
9316 + {0x00009910, 0x01002310},
9317 + {0x0000991c, 0x10000fff},
9318 + {0x00009920, 0x04900000},
9319 + {0x00009928, 0x00000001},
9320 + {0x0000992c, 0x00000004},
9321 + {0x00009934, 0x1e1f2022},
9322 + {0x00009938, 0x0a0b0c0d},
9323 + {0x0000993c, 0x00000000},
9324 + {0x00009940, 0x14750604},
9325 + {0x00009948, 0x9280c00a},
9326 + {0x0000994c, 0x00020028},
9327 + {0x00009954, 0x5f3ca3de},
9328 + {0x00009958, 0x2108ecff},
9329 + {0x00009968, 0x000003ce},
9330 + {0x00009970, 0x192bb514},
9331 + {0x00009974, 0x00000000},
9332 + {0x00009978, 0x00000001},
9333 + {0x0000997c, 0x00000000},
9334 + {0x00009980, 0x00000000},
9335 + {0x00009984, 0x00000000},
9336 + {0x00009988, 0x00000000},
9337 + {0x0000998c, 0x00000000},
9338 + {0x00009990, 0x00000000},
9339 + {0x00009994, 0x00000000},
9340 + {0x00009998, 0x00000000},
9341 + {0x0000999c, 0x00000000},
9342 + {0x000099a0, 0x00000000},
9343 + {0x000099a4, 0x00000001},
9344 + {0x000099a8, 0x201fff00},
9345 + {0x000099ac, 0x2def0400},
9346 + {0x000099b0, 0x03051000},
9347 + {0x000099b4, 0x00000820},
9348 + {0x000099dc, 0x00000000},
9349 + {0x000099e0, 0x00000000},
9350 + {0x000099e4, 0xaaaaaaaa},
9351 + {0x000099e8, 0x3c466478},
9352 + {0x000099ec, 0x0cc80caa},
9353 + {0x000099f0, 0x00000000},
9354 + {0x0000a208, 0x803e68c8},
9355 + {0x0000a210, 0x4080a333},
9356 + {0x0000a214, 0x00206c10},
9357 + {0x0000a218, 0x009c4060},
9358 + {0x0000a220, 0x01834061},
9359 + {0x0000a224, 0x00000400},
9360 + {0x0000a228, 0x000003b5},
9361 + {0x0000a22c, 0x00000000},
9362 + {0x0000a234, 0x20202020},
9363 + {0x0000a238, 0x20202020},
9364 + {0x0000a244, 0x00000000},
9365 + {0x0000a248, 0xfffffffc},
9366 + {0x0000a24c, 0x00000000},
9367 + {0x0000a254, 0x00000000},
9368 + {0x0000a258, 0x0ccb5380},
9369 + {0x0000a25c, 0x15151501},
9370 + {0x0000a260, 0xdfa90f01},
9371 + {0x0000a268, 0x00000000},
9372 + {0x0000a26c, 0x0ebae9e6},
9373 + {0x0000d270, 0x0d820820},
9374 + {0x0000d35c, 0x07ffffef},
9375 + {0x0000d360, 0x0fffffe7},
9376 + {0x0000d364, 0x17ffffe5},
9377 + {0x0000d368, 0x1fffffe4},
9378 + {0x0000d36c, 0x37ffffe3},
9379 + {0x0000d370, 0x3fffffe3},
9380 + {0x0000d374, 0x57ffffe3},
9381 + {0x0000d378, 0x5fffffe2},
9382 + {0x0000d37c, 0x7fffffe2},
9383 + {0x0000d380, 0x7f3c7bba},
9384 + {0x0000d384, 0xf3307ff0},
9385 + {0x0000a388, 0x0c000000},
9386 + {0x0000a38c, 0x20202020},
9387 + {0x0000a390, 0x20202020},
9388 + {0x0000a39c, 0x00000001},
9389 + {0x0000a3a0, 0x00000000},
9390 + {0x0000a3a4, 0x00000000},
9391 + {0x0000a3a8, 0x00000000},
9392 + {0x0000a3ac, 0x00000000},
9393 + {0x0000a3b0, 0x00000000},
9394 + {0x0000a3b4, 0x00000000},
9395 + {0x0000a3b8, 0x00000000},
9396 + {0x0000a3bc, 0x00000000},
9397 + {0x0000a3c0, 0x00000000},
9398 + {0x0000a3c4, 0x00000000},
9399 + {0x0000a3cc, 0x20202020},
9400 + {0x0000a3d0, 0x20202020},
9401 + {0x0000a3d4, 0x20202020},
9402 + {0x0000a3e4, 0x00000000},
9403 + {0x0000a3e8, 0x18c43433},
9404 + {0x0000a3ec, 0x00f70081},
9405 + {0x00007800, 0x00140000},
9406 + {0x00007804, 0x0e4548d8},
9407 + {0x00007808, 0x54214514},
9408 + {0x0000780c, 0x02025830},
9409 + {0x00007810, 0x71c0d388},
9410 + {0x0000781c, 0x00000000},
9411 + {0x00007824, 0x00d86fff},
9412 + {0x0000782c, 0x6e36d97b},
9413 + {0x00007834, 0x71400087},
9414 + {0x00007844, 0x000c0db6},
9415 + {0x00007848, 0x6db6246f},
9416 + {0x0000784c, 0x6d9b66db},
9417 + {0x00007850, 0x6d8c6dba},
9418 + {0x00007854, 0x00040000},
9419 + {0x00007858, 0xdb003012},
9420 + {0x0000785c, 0x04924914},
9421 + {0x00007860, 0x21084210},
9422 + {0x00007864, 0xf7d7ffde},
9423 + {0x00007868, 0xc2034080},
9424 + {0x00007870, 0x10142c00},
9425 +};
9426 +
9427 +static const u_int32_t ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
9428 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
9429 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9430 + 0x00000000},
9431 + {0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200,
9432 + 0x00000000},
9433 + {0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201,
9434 + 0x00000000},
9435 + {0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240,
9436 + 0x00000000},
9437 + {0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241,
9438 + 0x00000000},
9439 + {0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600,
9440 + 0x00000000},
9441 + {0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800,
9442 + 0x00000000},
9443 + {0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802,
9444 + 0x00000000},
9445 + {0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805,
9446 + 0x00000000},
9447 + {0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80,
9448 + 0x00000000},
9449 + {0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00,
9450 + 0x00000000},
9451 + {0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40,
9452 + 0x00000000},
9453 + {0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80,
9454 + 0x00000000},
9455 + {0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82,
9456 + 0x00000000},
9457 + {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e,
9458 + 0x00000000},
9459 + {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e,
9460 + 0x00000000},
9461 + {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9462 + 0x00000000},
9463 + {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9464 + 0x00000000},
9465 + {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9466 + 0x00000000},
9467 + {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9468 + 0x00000000},
9469 + {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9470 + 0x00000000},
9471 + {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9472 + 0x00000000},
9473 + {0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8,
9474 + 0x924934a8},
9475 + {0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b,
9476 + 0x26d2491b},
9477 + {0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e,
9478 + 0xedb6d96e},
9479 + {0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803,
9480 + 0xfac68803},
9481 + {0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe,
9482 + 0x0001fffe},
9483 + {0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20,
9484 + 0xffeb1a20},
9485 + {0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe,
9486 + 0x08609ebe},
9487 + {0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00,
9488 + 0x00000c00},
9489 + {0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652,
9490 + 0x0a22a652},
9491 + {0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7,
9492 + 0x0e739ce7},
9493 + {0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7,
9494 + 0x050380e7},
9495 + {0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7,
9496 + 0x0e739ce7},
9497 + {0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7,
9498 + 0x000000e7},
9499 + {0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7,
9500 + 0x0e739ce7},
9501 + {0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7,
9502 + 0x000000e7},
9503 +};
9504 +
9505 +static const u_int32_t ar9285Modes_original_tx_gain_9285_1_2[][6] = {
9506 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
9507 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9508 + 0x00000000},
9509 + {0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200,
9510 + 0x00000000},
9511 + {0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208,
9512 + 0x00000000},
9513 + {0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608,
9514 + 0x00000000},
9515 + {0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618,
9516 + 0x00000000},
9517 + {0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9,
9518 + 0x00000000},
9519 + {0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710,
9520 + 0x00000000},
9521 + {0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718,
9522 + 0x00000000},
9523 + {0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758,
9524 + 0x00000000},
9525 + {0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a,
9526 + 0x00000000},
9527 + {0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c,
9528 + 0x00000000},
9529 + {0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e,
9530 + 0x00000000},
9531 + {0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f,
9532 + 0x00000000},
9533 + {0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df,
9534 + 0x00000000},
9535 + {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e,
9536 + 0x00000000},
9537 + {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e,
9538 + 0x00000000},
9539 + {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9540 + 0x00000000},
9541 + {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9542 + 0x00000000},
9543 + {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9544 + 0x00000000},
9545 + {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9546 + 0x00000000},
9547 + {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9548 + 0x00000000},
9549 + {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9550 + 0x00000000},
9551 + {0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8,
9552 + 0x924934a8},
9553 + {0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b,
9554 + 0x26d2491b},
9555 + {0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e,
9556 + 0xedb6d96e},
9557 + {0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801,
9558 + 0xfac68801},
9559 + {0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe,
9560 + 0x0001fffe},
9561 + {0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20,
9562 + 0xffeb1a20},
9563 + {0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4,
9564 + 0x48609eb4},
9565 + {0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04,
9566 + 0x00000c04},
9567 + {0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652,
9568 + 0x0a22a652},
9569 + {0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c,
9570 + 0x39ce739c},
9571 + {0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c,
9572 + 0x050e039c},
9573 + {0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c,
9574 + 0x39ce739c},
9575 + {0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c,
9576 + 0x0000039c},
9577 + {0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c,
9578 + 0x39ce739c},
9579 + {0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c,
9580 + 0x0000039c},
9581 +};
9582 +
9583 +static const u_int32_t ar9285Modes_XE2_0_normal_power[][6] = {
9584 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9585 + 0x00000000},
9586 + {0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200,
9587 + 0x00000000},
9588 + {0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208,
9589 + 0x00000000},
9590 + {0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608,
9591 + 0x00000000},
9592 + {0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618,
9593 + 0x00000000},
9594 + {0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9,
9595 + 0x00000000},
9596 + {0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710,
9597 + 0x00000000},
9598 + {0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718,
9599 + 0x00000000},
9600 + {0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758,
9601 + 0x00000000},
9602 + {0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a,
9603 + 0x00000000},
9604 + {0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c,
9605 + 0x00000000},
9606 + {0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e,
9607 + 0x00000000},
9608 + {0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f,
9609 + 0x00000000},
9610 + {0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df,
9611 + 0x00000000},
9612 + {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e,
9613 + 0x00000000},
9614 + {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e,
9615 + 0x00000000},
9616 + {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9617 + 0x00000000},
9618 + {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9619 + 0x00000000},
9620 + {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9621 + 0x00000000},
9622 + {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9623 + 0x00000000},
9624 + {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9625 + 0x00000000},
9626 + {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9627 + 0x00000000},
9628 + {0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8,
9629 + 0x92497ca8},
9630 + {0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b,
9631 + 0x4ad2491b},
9632 + {0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e,
9633 + 0xedb6dbae},
9634 + {0x00007838, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441,
9635 + 0xdac71441},
9636 + {0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe,
9637 + 0x2481f6fe},
9638 + {0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c,
9639 + 0xba5f638c},
9640 + {0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4,
9641 + 0x48609eb4},
9642 + {0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04,
9643 + 0x00000c04},
9644 + {0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652,
9645 + 0x0a22a652},
9646 + {0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c,
9647 + 0x39ce739c},
9648 + {0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c,
9649 + 0x050e039c},
9650 + {0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c,
9651 + 0x39ce739c},
9652 + {0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c,
9653 + 0x0000039c},
9654 + {0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c,
9655 + 0x39ce739c},
9656 + {0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c,
9657 + 0x0000039c},
9658 +};
9659 +
9660 +static const u_int32_t ar9285Modes_XE2_0_high_power[][6] = {
9661 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9662 + 0x00000000},
9663 + {0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200,
9664 + 0x00000000},
9665 + {0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201,
9666 + 0x00000000},
9667 + {0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240,
9668 + 0x00000000},
9669 + {0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241,
9670 + 0x00000000},
9671 + {0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600,
9672 + 0x00000000},
9673 + {0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800,
9674 + 0x00000000},
9675 + {0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802,
9676 + 0x00000000},
9677 + {0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805,
9678 + 0x00000000},
9679 + {0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80,
9680 + 0x00000000},
9681 + {0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00,
9682 + 0x00000000},
9683 + {0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40,
9684 + 0x00000000},
9685 + {0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80,
9686 + 0x00000000},
9687 + {0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82,
9688 + 0x00000000},
9689 + {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e,
9690 + 0x00000000},
9691 + {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e,
9692 + 0x00000000},
9693 + {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9694 + 0x00000000},
9695 + {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9696 + 0x00000000},
9697 + {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9698 + 0x00000000},
9699 + {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9700 + 0x00000000},
9701 + {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9702 + 0x00000000},
9703 + {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9704 + 0x00000000},
9705 + {0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8,
9706 + 0x92497ca8},
9707 + {0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b,
9708 + 0x4ad2491b},
9709 + {0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e,
9710 + 0xedb6da6e},
9711 + {0x00007838, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443,
9712 + 0xdac71443},
9713 + {0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe,
9714 + 0x2481f6fe},
9715 + {0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c,
9716 + 0xba5f638c},
9717 + {0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe,
9718 + 0x08609ebe},
9719 + {0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00,
9720 + 0x00000c00},
9721 + {0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652,
9722 + 0x0a22a652},
9723 + {0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7,
9724 + 0x0e739ce7},
9725 + {0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7,
9726 + 0x050380e7},
9727 + {0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7,
9728 + 0x0e739ce7},
9729 + {0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7,
9730 + 0x000000e7},
9731 + {0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7,
9732 + 0x0e739ce7},
9733 + {0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7,
9734 + 0x000000e7},
9735 +};
9736 +
9737 +static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
9738 + {0x00004040, 0x9248fd00},
9739 + {0x00004040, 0x24924924},
9740 + {0x00004040, 0xa8000019},
9741 + {0x00004040, 0x13160820},
9742 + {0x00004040, 0xe5980560},
9743 + {0x00004040, 0xc01dcffd},
9744 + {0x00004040, 0x1aaabe41},
9745 + {0x00004040, 0xbe105554},
9746 + {0x00004040, 0x00043007},
9747 + {0x00004044, 0x00000000},
9748 +};
9749 +
9750 +static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
9751 + {0x00004040, 0x9248fd00},
9752 + {0x00004040, 0x24924924},
9753 + {0x00004040, 0xa8000019},
9754 + {0x00004040, 0x13160820},
9755 + {0x00004040, 0xe5980560},
9756 + {0x00004040, 0xc01dcffc},
9757 + {0x00004040, 0x1aaabe41},
9758 + {0x00004040, 0xbe105554},
9759 + {0x00004040, 0x00043007},
9760 + {0x00004044, 0x00000000},
9761 +};
9762 +
9763 +/* AR9287 Revision 10 */
9764 +static const u_int32_t ar9287Modes_9287_1_0[][6] = {
9765 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
9766 + {0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160,
9767 + 0x000001e0},
9768 + {0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c,
9769 + 0x000001e0},
9770 + {0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38,
9771 + 0x00001180},
9772 + {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9773 + 0x00000008},
9774 + {0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00,
9775 + 0x06e006e0},
9776 + {0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b,
9777 + 0x0988004f},
9778 + {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810,
9779 + 0x08f04810},
9780 + {0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a,
9781 + 0x0000320a},
9782 + {0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440,
9783 + 0x00006880},
9784 + {0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300,
9785 + 0x00000303},
9786 + {0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200,
9787 + 0x02020200},
9788 + {0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e,
9789 + 0x01000e0e},
9790 + {0x00009828, 0x00000000, 0x00000000, 0x0a020001, 0x0a020001,
9791 + 0x0a020001},
9792 + {0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e,
9793 + 0x00000e0e},
9794 + {0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007,
9795 + 0x00000007},
9796 + {0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e,
9797 + 0x206a012e},
9798 + {0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0,
9799 + 0x037216a0},
9800 + {0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2,
9801 + 0x6c4000e2},
9802 + {0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e,
9803 + 0x7ec84d2e},
9804 + {0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e,
9805 + 0x31395d5e},
9806 + {0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20,
9807 + 0x00058d18},
9808 + {0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00,
9809 + 0x0001ce00},
9810 + {0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0,
9811 + 0x5ac640d0},
9812 + {0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881,
9813 + 0x06903881},
9814 + {0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898,
9815 + 0x000007d0},
9816 + {0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b,
9817 + 0x00000016},
9818 + {0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d,
9819 + 0xd00a8a0d},
9820 + {0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010,
9821 + 0xefbc1010},
9822 + {0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010,
9823 + 0x00000010},
9824 + {0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010,
9825 + 0x00000010},
9826 + {0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210,
9827 + 0x00000210},
9828 + {0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce,
9829 + 0x000003ce},
9830 + {0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c,
9831 + 0x0000001c},
9832 + {0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00,
9833 + 0x00000c00},
9834 + {0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4,
9835 + 0x05eea6d4},
9836 + {0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444,
9837 + 0x00000444},
9838 + {0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9839 + 0x00000000},
9840 + {0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9841 + 0x00000000},
9842 + {0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a,
9843 + 0x1883800a},
9844 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
9845 + 0x00000000},
9846 + {0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000,
9847 + 0x0004a000},
9848 + {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e,
9849 + 0x7999aa0e},
9850 + {0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9851 + 0x00000000},
9852 +};
9853 +
9854 +static const u_int32_t ar9287Common_9287_1_0[][2] = {
9855 + {0x0000000c, 0x00000000},
9856 + {0x00000030, 0x00020015},
9857 + {0x00000034, 0x00000005},
9858 + {0x00000040, 0x00000000},
9859 + {0x00000044, 0x00000008},
9860 + {0x00000048, 0x00000008},
9861 + {0x0000004c, 0x00000010},
9862 + {0x00000050, 0x00000000},
9863 + {0x00000054, 0x0000001f},
9864 + {0x00000800, 0x00000000},
9865 + {0x00000804, 0x00000000},
9866 + {0x00000808, 0x00000000},
9867 + {0x0000080c, 0x00000000},
9868 + {0x00000810, 0x00000000},
9869 + {0x00000814, 0x00000000},
9870 + {0x00000818, 0x00000000},
9871 + {0x0000081c, 0x00000000},
9872 + {0x00000820, 0x00000000},
9873 + {0x00000824, 0x00000000},
9874 + {0x00001040, 0x002ffc0f},
9875 + {0x00001044, 0x002ffc0f},
9876 + {0x00001048, 0x002ffc0f},
9877 + {0x0000104c, 0x002ffc0f},
9878 + {0x00001050, 0x002ffc0f},
9879 + {0x00001054, 0x002ffc0f},
9880 + {0x00001058, 0x002ffc0f},
9881 + {0x0000105c, 0x002ffc0f},
9882 + {0x00001060, 0x002ffc0f},
9883 + {0x00001064, 0x002ffc0f},
9884 + {0x00001230, 0x00000000},
9885 + {0x00001270, 0x00000000},
9886 + {0x00001038, 0x00000000},
9887 + {0x00001078, 0x00000000},
9888 + {0x000010b8, 0x00000000},
9889 + {0x000010f8, 0x00000000},
9890 + {0x00001138, 0x00000000},
9891 + {0x00001178, 0x00000000},
9892 + {0x000011b8, 0x00000000},
9893 + {0x000011f8, 0x00000000},
9894 + {0x00001238, 0x00000000},
9895 + {0x00001278, 0x00000000},
9896 + {0x000012b8, 0x00000000},
9897 + {0x000012f8, 0x00000000},
9898 + {0x00001338, 0x00000000},
9899 + {0x00001378, 0x00000000},
9900 + {0x000013b8, 0x00000000},
9901 + {0x000013f8, 0x00000000},
9902 + {0x00001438, 0x00000000},
9903 + {0x00001478, 0x00000000},
9904 + {0x000014b8, 0x00000000},
9905 + {0x000014f8, 0x00000000},
9906 + {0x00001538, 0x00000000},
9907 + {0x00001578, 0x00000000},
9908 + {0x000015b8, 0x00000000},
9909 + {0x000015f8, 0x00000000},
9910 + {0x00001638, 0x00000000},
9911 + {0x00001678, 0x00000000},
9912 + {0x000016b8, 0x00000000},
9913 + {0x000016f8, 0x00000000},
9914 + {0x00001738, 0x00000000},
9915 + {0x00001778, 0x00000000},
9916 + {0x000017b8, 0x00000000},
9917 + {0x000017f8, 0x00000000},
9918 + {0x0000103c, 0x00000000},
9919 + {0x0000107c, 0x00000000},
9920 + {0x000010bc, 0x00000000},
9921 + {0x000010fc, 0x00000000},
9922 + {0x0000113c, 0x00000000},
9923 + {0x0000117c, 0x00000000},
9924 + {0x000011bc, 0x00000000},
9925 + {0x000011fc, 0x00000000},
9926 + {0x0000123c, 0x00000000},
9927 + {0x0000127c, 0x00000000},
9928 + {0x000012bc, 0x00000000},
9929 + {0x000012fc, 0x00000000},
9930 + {0x0000133c, 0x00000000},
9931 + {0x0000137c, 0x00000000},
9932 + {0x000013bc, 0x00000000},
9933 + {0x000013fc, 0x00000000},
9934 + {0x0000143c, 0x00000000},
9935 + {0x0000147c, 0x00000000},
9936 + {0x00004030, 0x00000002},
9937 + {0x0000403c, 0x00000002},
9938 + {0x00004024, 0x0000001f},
9939 + {0x00004060, 0x00000000},
9940 + {0x00004064, 0x00000000},
9941 + {0x00007010, 0x00000033},
9942 + {0x00007020, 0x00000000},
9943 + {0x00007034, 0x00000002},
9944 + {0x00007038, 0x000004c2},
9945 + {0x00008004, 0x00000000},
9946 + {0x00008008, 0x00000000},
9947 + {0x0000800c, 0x00000000},
9948 + {0x00008018, 0x00000700},
9949 + {0x00008020, 0x00000000},
9950 + {0x00008038, 0x00000000},
9951 + {0x0000803c, 0x00000000},
9952 + {0x00008048, 0x40000000},
9953 + {0x00008054, 0x00000000},
9954 + {0x00008058, 0x00000000},
9955 + {0x0000805c, 0x000fc78f},
9956 + {0x00008060, 0x0000000f},
9957 + {0x00008064, 0x00000000},
9958 + {0x00008070, 0x00000000},
9959 + {0x000080c0, 0x2a80001a},
9960 + {0x000080c4, 0x05dc01e0},
9961 + {0x000080c8, 0x1f402710},
9962 + {0x000080cc, 0x01f40000},
9963 + {0x000080d0, 0x00001e00},
9964 + {0x000080d4, 0x00000000},
9965 + {0x000080d8, 0x00400000},
9966 + {0x000080e0, 0xffffffff},
9967 + {0x000080e4, 0x0000ffff},
9968 + {0x000080e8, 0x003f3f3f},
9969 + {0x000080ec, 0x00000000},
9970 + {0x000080f0, 0x00000000},
9971 + {0x000080f4, 0x00000000},
9972 + {0x000080f8, 0x00000000},
9973 + {0x000080fc, 0x00020000},
9974 + {0x00008100, 0x00020000},
9975 + {0x00008104, 0x00000001},
9976 + {0x00008108, 0x00000052},
9977 + {0x0000810c, 0x00000000},
9978 + {0x00008110, 0x00000168},
9979 + {0x00008118, 0x000100aa},
9980 + {0x0000811c, 0x00003210},
9981 + {0x00008124, 0x00000000},
9982 + {0x00008128, 0x00000000},
9983 + {0x0000812c, 0x00000000},
9984 + {0x00008130, 0x00000000},
9985 + {0x00008134, 0x00000000},
9986 + {0x00008138, 0x00000000},
9987 + {0x0000813c, 0x00000000},
9988 + {0x00008144, 0xffffffff},
9989 + {0x00008168, 0x00000000},
9990 + {0x0000816c, 0x00000000},
9991 + {0x00008170, 0x18487320},
9992 + {0x00008174, 0xfaa4fa50},
9993 + {0x00008178, 0x00000100},
9994 + {0x0000817c, 0x00000000},
9995 + {0x000081c0, 0x00000000},
9996 + {0x000081c4, 0x00000000},
9997 + {0x000081d4, 0x00000000},
9998 + {0x000081ec, 0x00000000},
9999 + {0x000081f0, 0x00000000},
10000 + {0x000081f4, 0x00000000},
10001 + {0x000081f8, 0x00000000},
10002 + {0x000081fc, 0x00000000},
10003 + {0x00008200, 0x00000000},
10004 + {0x00008204, 0x00000000},
10005 + {0x00008208, 0x00000000},
10006 + {0x0000820c, 0x00000000},
10007 + {0x00008210, 0x00000000},
10008 + {0x00008214, 0x00000000},
10009 + {0x00008218, 0x00000000},
10010 + {0x0000821c, 0x00000000},
10011 + {0x00008220, 0x00000000},
10012 + {0x00008224, 0x00000000},
10013 + {0x00008228, 0x00000000},
10014 + {0x0000822c, 0x00000000},
10015 + {0x00008230, 0x00000000},
10016 + {0x00008234, 0x00000000},
10017 + {0x00008238, 0x00000000},
10018 + {0x0000823c, 0x00000000},
10019 + {0x00008240, 0x00100000},
10020 + {0x00008244, 0x0010f400},
10021 + {0x00008248, 0x00000100},
10022 + {0x0000824c, 0x0001e800},
10023 + {0x00008250, 0x00000000},
10024 + {0x00008254, 0x00000000},
10025 + {0x00008258, 0x00000000},
10026 + {0x0000825c, 0x400000ff},
10027 + {0x00008260, 0x00080922},
10028 + {0x00008264, 0xa8a00010},
10029 + {0x00008270, 0x00000000},
10030 + {0x00008274, 0x40000000},
10031 + {0x00008278, 0x003e4180},
10032 + {0x0000827c, 0x00000000},
10033 + {0x00008284, 0x0000002c},
10034 + {0x00008288, 0x0000002c},
10035 + {0x0000828c, 0x000000ff},
10036 + {0x00008294, 0x00000000},
10037 + {0x00008298, 0x00000000},
10038 + {0x0000829c, 0x00000000},
10039 + {0x00008300, 0x00000040},
10040 + {0x00008314, 0x00000000},
10041 + {0x00008328, 0x00000000},
10042 + {0x0000832c, 0x00000007},
10043 + {0x00008330, 0x00000302},
10044 + {0x00008334, 0x00000e00},
10045 + {0x00008338, 0x00ff0000},
10046 + {0x0000833c, 0x00000000},
10047 + {0x00008340, 0x000107ff},
10048 + {0x00008344, 0x01c81043},
10049 + {0x00008360, 0xffffffff},
10050 + {0x00008364, 0xffffffff},
10051 + {0x00008368, 0x00000000},
10052 + {0x00008370, 0x00000000},
10053 + {0x00008374, 0x000000ff},
10054 + {0x00008378, 0x00000000},
10055 + {0x0000837c, 0x00000000},
10056 + {0x00008380, 0xffffffff},
10057 + {0x00008384, 0xffffffff},
10058 + {0x00008390, 0x0fffffff},
10059 + {0x00008394, 0x0fffffff},
10060 + {0x00008398, 0x00000000},
10061 + {0x0000839c, 0x00000000},
10062 + {0x000083a0, 0x00000000},
10063 + {0x00009808, 0x00000000},
10064 + {0x0000980c, 0xafe68e30},
10065 + {0x00009810, 0xfd14e000},
10066 + {0x00009814, 0x9c0a9f6b},
10067 + {0x0000981c, 0x00000000},
10068 + {0x0000982c, 0x0000a000},
10069 + {0x00009830, 0x00000000},
10070 + {0x0000983c, 0x00200400},
10071 + {0x0000984c, 0x0040233c},
10072 + {0x0000a84c, 0x0040233c},
10073 + {0x00009854, 0x00000044},
10074 + {0x00009900, 0x00000000},
10075 + {0x00009904, 0x00000000},
10076 + {0x00009908, 0x00000000},
10077 + {0x0000990c, 0x00000000},
10078 + {0x00009910, 0x10002310},
10079 + {0x0000991c, 0x10000fff},
10080 + {0x00009920, 0x04900000},
10081 + {0x0000a920, 0x04900000},
10082 + {0x00009928, 0x00000001},
10083 + {0x0000992c, 0x00000004},
10084 + {0x00009930, 0x00000000},
10085 + {0x0000a930, 0x00000000},
10086 + {0x00009934, 0x1e1f2022},
10087 + {0x00009938, 0x0a0b0c0d},
10088 + {0x0000993c, 0x00000000},
10089 + {0x00009948, 0x9280c00a},
10090 + {0x0000994c, 0x00020028},
10091 + {0x00009954, 0x5f3ca3de},
10092 + {0x00009958, 0x0108ecff},
10093 + {0x00009940, 0x14750604},
10094 + {0x0000c95c, 0x004b6a8e},
10095 + {0x00009970, 0x990bb515},
10096 + {0x00009974, 0x00000000},
10097 + {0x00009978, 0x00000001},
10098 + {0x0000997c, 0x00000000},
10099 + {0x000099a0, 0x00000000},
10100 + {0x000099a4, 0x00000001},
10101 + {0x000099a8, 0x201fff00},
10102 + {0x000099ac, 0x0c6f0000},
10103 + {0x000099b0, 0x03051000},
10104 + {0x000099b4, 0x00000820},
10105 + {0x000099c4, 0x06336f77},
10106 + {0x000099c8, 0x6af65329},
10107 + {0x000099cc, 0x08f186c8},
10108 + {0x000099d0, 0x00046384},
10109 + {0x000099dc, 0x00000000},
10110 + {0x000099e0, 0x00000000},
10111 + {0x000099e4, 0xaaaaaaaa},
10112 + {0x000099e8, 0x3c466478},
10113 + {0x000099ec, 0x0cc80caa},
10114 + {0x000099f0, 0x00000000},
10115 + {0x000099fc, 0x00001042},
10116 + {0x0000a1f4, 0x00fffeff},
10117 + {0x0000a1f8, 0x00f5f9ff},
10118 + {0x0000a1fc, 0xb79f6427},
10119 + {0x0000a208, 0x803e4788},
10120 + {0x0000a210, 0x4080a333},
10121 + {0x0000a214, 0x40206c10},
10122 + {0x0000a218, 0x009c4060},
10123 + {0x0000a220, 0x01834061},
10124 + {0x0000a224, 0x00000400},
10125 + {0x0000a228, 0x000003b5},
10126 + {0x0000a22c, 0x233f7180},
10127 + {0x0000a234, 0x20202020},
10128 + {0x0000a238, 0x20202020},
10129 + {0x0000a23c, 0x13c889af},
10130 + {0x0000a240, 0x38490a20},
10131 + {0x0000a244, 0x00000000},
10132 + {0x0000a248, 0xfffffffc},
10133 + {0x0000a24c, 0x00000000},
10134 + {0x0000a254, 0x00000000},
10135 + {0x0000a258, 0x0cdbd380},
10136 + {0x0000a25c, 0x0f0f0f01},
10137 + {0x0000a260, 0xdfa91f01},
10138 + {0x0000a264, 0x00418a11},
10139 + {0x0000b264, 0x00418a11},
10140 + {0x0000a268, 0x00000000},
10141 + {0x0000a26c, 0x0e79e5c6},
10142 + {0x0000b26c, 0x0e79e5c6},
10143 + {0x0000d270, 0x00820820},
10144 + {0x0000a278, 0x1ce739ce},
10145 + {0x0000a27c, 0x050701ce},
10146 + {0x0000d35c, 0x07ffffef},
10147 + {0x0000d360, 0x0fffffe7},
10148 + {0x0000d364, 0x17ffffe5},
10149 + {0x0000d368, 0x1fffffe4},
10150 + {0x0000d36c, 0x37ffffe3},
10151 + {0x0000d370, 0x3fffffe3},
10152 + {0x0000d374, 0x57ffffe3},
10153 + {0x0000d378, 0x5fffffe2},
10154 + {0x0000d37c, 0x7fffffe2},
10155 + {0x0000d380, 0x7f3c7bba},
10156 + {0x0000d384, 0xf3307ff0},
10157 + {0x0000a388, 0x0c000000},
10158 + {0x0000a38c, 0x20202020},
10159 + {0x0000a390, 0x20202020},
10160 + {0x0000a394, 0x1ce739ce},
10161 + {0x0000a398, 0x000001ce},
10162 + {0x0000b398, 0x000001ce},
10163 + {0x0000a39c, 0x00000001},
10164 + {0x0000a3c8, 0x00000246},
10165 + {0x0000a3cc, 0x20202020},
10166 + {0x0000a3d0, 0x20202020},
10167 + {0x0000a3d4, 0x20202020},
10168 + {0x0000a3dc, 0x1ce739ce},
10169 + {0x0000a3e0, 0x000001ce},
10170 + {0x0000a3e4, 0x00000000},
10171 + {0x0000a3e8, 0x18c43433},
10172 + {0x0000a3ec, 0x00f70081},
10173 + {0x0000a3f0, 0x01036a1e},
10174 + {0x0000a3f4, 0x00000000},
10175 + {0x0000b3f4, 0x00000000},
10176 + {0x0000a7d8, 0x00000001},
10177 + {0x00007800, 0x00000800},
10178 + {0x00007804, 0x6c35ffb0},
10179 + {0x00007808, 0x6db6c000},
10180 + {0x0000780c, 0x6db6cb30},
10181 + {0x00007810, 0x6db6cb6c},
10182 + {0x00007814, 0x0501e200},
10183 + {0x00007818, 0x0094128d},
10184 + {0x0000781c, 0x976ee392},
10185 + {0x00007820, 0xf75ff6fc},
10186 + {0x00007824, 0x00040000},
10187 + {0x00007828, 0xdb003012},
10188 + {0x0000782c, 0x04924914},
10189 + {0x00007830, 0x21084210},
10190 + {0x00007834, 0x00140000},
10191 + {0x00007838, 0x0e4548d8},
10192 + {0x0000783c, 0x54214514},
10193 + {0x00007840, 0x02025820},
10194 + {0x00007844, 0x71c0d388},
10195 + {0x00007848, 0x934934a8},
10196 + {0x00007850, 0x00000000},
10197 + {0x00007854, 0x00000800},
10198 + {0x00007858, 0x6c35ffb0},
10199 + {0x0000785c, 0x6db6c000},
10200 + {0x00007860, 0x6db6cb2c},
10201 + {0x00007864, 0x6db6cb6c},
10202 + {0x00007868, 0x0501e200},
10203 + {0x0000786c, 0x0094128d},
10204 + {0x00007870, 0x976ee392},
10205 + {0x00007874, 0xf75ff6fc},
10206 + {0x00007878, 0x00040000},
10207 + {0x0000787c, 0xdb003012},
10208 + {0x00007880, 0x04924914},
10209 + {0x00007884, 0x21084210},
10210 + {0x00007888, 0x001b6db0},
10211 + {0x0000788c, 0x00376b63},
10212 + {0x00007890, 0x06db6db6},
10213 + {0x00007894, 0x006d8000},
10214 + {0x00007898, 0x48100000},
10215 + {0x0000789c, 0x00000000},
10216 + {0x000078a0, 0x08000000},
10217 + {0x000078a4, 0x0007ffd8},
10218 + {0x000078a8, 0x0007ffd8},
10219 + {0x000078ac, 0x001c0020},
10220 + {0x000078b0, 0x000611eb},
10221 + {0x000078b4, 0x40008080},
10222 + {0x000078b8, 0x2a850160},
10223 +};
10224 +
10225 +static const u_int32_t ar9287Modes_tx_gain_9287_1_0[][6] = {
10226 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
10227 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
10228 + 0x00000000},
10229 + {0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002,
10230 + 0x00004002},
10231 + {0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004,
10232 + 0x00008004},
10233 + {0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a,
10234 + 0x0000c00a},
10235 + {0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c,
10236 + 0x0001000c},
10237 + {0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b,
10238 + 0x0001420b},
10239 + {0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a,
10240 + 0x0001824a},
10241 + {0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a,
10242 + 0x0001c44a},
10243 + {0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a,
10244 + 0x0002064a},
10245 + {0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a,
10246 + 0x0002484a},
10247 + {0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a,
10248 + 0x00028a4a},
10249 + {0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a,
10250 + 0x0002cc4a},
10251 + {0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a,
10252 + 0x00030e4a},
10253 + {0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a,
10254 + 0x00034e8a},
10255 + {0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c,
10256 + 0x00038e8c},
10257 + {0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc,
10258 + 0x0003cecc},
10259 + {0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4,
10260 + 0x00040ed4},
10261 + {0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc,
10262 + 0x00044edc},
10263 + {0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede,
10264 + 0x00048ede},
10265 + {0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e,
10266 + 0x0004cf1e},
10267 + {0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e,
10268 + 0x00050f5e},
10269 + {0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e,
10270 + 0x00054f9e},
10271 + {0x0000a780, 0x00000000, 0x00000000, 0x00000060, 0x00000060,
10272 + 0x00000060},
10273 + {0x0000a784, 0x00000000, 0x00000000, 0x00004062, 0x00004062,
10274 + 0x00004062},
10275 + {0x0000a788, 0x00000000, 0x00000000, 0x00008064, 0x00008064,
10276 + 0x00008064},
10277 + {0x0000a78c, 0x00000000, 0x00000000, 0x0000c0a4, 0x0000c0a4,
10278 + 0x0000c0a4},
10279 + {0x0000a790, 0x00000000, 0x00000000, 0x000100b0, 0x000100b0,
10280 + 0x000100b0},
10281 + {0x0000a794, 0x00000000, 0x00000000, 0x000140b2, 0x000140b2,
10282 + 0x000140b2},
10283 + {0x0000a798, 0x00000000, 0x00000000, 0x000180b4, 0x000180b4,
10284 + 0x000180b4},
10285 + {0x0000a79c, 0x00000000, 0x00000000, 0x0001c0f4, 0x0001c0f4,
10286 + 0x0001c0f4},
10287 + {0x0000a7a0, 0x00000000, 0x00000000, 0x00020134, 0x00020134,
10288 + 0x00020134},
10289 + {0x0000a7a4, 0x00000000, 0x00000000, 0x000240fe, 0x000240fe,
10290 + 0x000240fe},
10291 + {0x0000a7a8, 0x00000000, 0x00000000, 0x0002813e, 0x0002813e,
10292 + 0x0002813e},
10293 + {0x0000a7ac, 0x00000000, 0x00000000, 0x0002c17e, 0x0002c17e,
10294 + 0x0002c17e},
10295 + {0x0000a7b0, 0x00000000, 0x00000000, 0x000301be, 0x000301be,
10296 + 0x000301be},
10297 + {0x0000a7b4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10298 + 0x000341fe},
10299 + {0x0000a7b8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10300 + 0x000341fe},
10301 + {0x0000a7bc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10302 + 0x000341fe},
10303 + {0x0000a7c0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10304 + 0x000341fe},
10305 + {0x0000a7c4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10306 + 0x000341fe},
10307 + {0x0000a7c8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10308 + 0x000341fe},
10309 + {0x0000a7cc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10310 + 0x000341fe},
10311 + {0x0000a7d0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10312 + 0x000341fe},
10313 + {0x0000a7d4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10314 + 0x000341fe},
10315 + {0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000,
10316 + 0x0a1aa000},
10317 +};
10318 +
10319 +static const u_int32_t ar9287Modes_rx_gain_9287_1_0[][6] = {
10320 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
10321 + {0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120,
10322 + 0x0000a120},
10323 + {0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124,
10324 + 0x0000a124},
10325 + {0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128,
10326 + 0x0000a128},
10327 + {0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c,
10328 + 0x0000a12c},
10329 + {0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130,
10330 + 0x0000a130},
10331 + {0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194,
10332 + 0x0000a194},
10333 + {0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198,
10334 + 0x0000a198},
10335 + {0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c,
10336 + 0x0000a20c},
10337 + {0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210,
10338 + 0x0000a210},
10339 + {0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284,
10340 + 0x0000a284},
10341 + {0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288,
10342 + 0x0000a288},
10343 + {0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c,
10344 + 0x0000a28c},
10345 + {0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290,
10346 + 0x0000a290},
10347 + {0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294,
10348 + 0x0000a294},
10349 + {0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0,
10350 + 0x0000a2a0},
10351 + {0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4,
10352 + 0x0000a2a4},
10353 + {0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8,
10354 + 0x0000a2a8},
10355 + {0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac,
10356 + 0x0000a2ac},
10357 + {0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0,
10358 + 0x0000a2b0},
10359 + {0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4,
10360 + 0x0000a2b4},
10361 + {0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8,
10362 + 0x0000a2b8},
10363 + {0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4,
10364 + 0x0000a2c4},
10365 + {0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708,
10366 + 0x0000a708},
10367 + {0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c,
10368 + 0x0000a70c},
10369 + {0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710,
10370 + 0x0000a710},
10371 + {0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04,
10372 + 0x0000ab04},
10373 + {0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08,
10374 + 0x0000ab08},
10375 + {0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c,
10376 + 0x0000ab0c},
10377 + {0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10,
10378 + 0x0000ab10},
10379 + {0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14,
10380 + 0x0000ab14},
10381 + {0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18,
10382 + 0x0000ab18},
10383 + {0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c,
10384 + 0x0000ab8c},
10385 + {0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90,
10386 + 0x0000ab90},
10387 + {0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94,
10388 + 0x0000ab94},
10389 + {0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98,
10390 + 0x0000ab98},
10391 + {0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4,
10392 + 0x0000aba4},
10393 + {0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8,
10394 + 0x0000aba8},
10395 + {0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04,
10396 + 0x0000cb04},
10397 + {0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08,
10398 + 0x0000cb08},
10399 + {0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c,
10400 + 0x0000cb0c},
10401 + {0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10,
10402 + 0x0000cb10},
10403 + {0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14,
10404 + 0x0000cb14},
10405 + {0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18,
10406 + 0x0000cb18},
10407 + {0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c,
10408 + 0x0000cb8c},
10409 + {0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90,
10410 + 0x0000cb90},
10411 + {0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18,
10412 + 0x0000cf18},
10413 + {0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24,
10414 + 0x0000cf24},
10415 + {0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28,
10416 + 0x0000cf28},
10417 + {0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314,
10418 + 0x0000d314},
10419 + {0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318,
10420 + 0x0000d318},
10421 + {0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c,
10422 + 0x0000d38c},
10423 + {0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390,
10424 + 0x0000d390},
10425 + {0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394,
10426 + 0x0000d394},
10427 + {0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398,
10428 + 0x0000d398},
10429 + {0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4,
10430 + 0x0000d3a4},
10431 + {0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8,
10432 + 0x0000d3a8},
10433 + {0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac,
10434 + 0x0000d3ac},
10435 + {0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0,
10436 + 0x0000d3b0},
10437 + {0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380,
10438 + 0x0000f380},
10439 + {0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384,
10440 + 0x0000f384},
10441 + {0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388,
10442 + 0x0000f388},
10443 + {0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710,
10444 + 0x0000f710},
10445 + {0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714,
10446 + 0x0000f714},
10447 + {0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718,
10448 + 0x0000f718},
10449 + {0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10,
10450 + 0x0000fb10},
10451 + {0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14,
10452 + 0x0000fb14},
10453 + {0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18,
10454 + 0x0000fb18},
10455 + {0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c,
10456 + 0x0000fb8c},
10457 + {0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90,
10458 + 0x0000fb90},
10459 + {0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94,
10460 + 0x0000fb94},
10461 + {0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c,
10462 + 0x0000ff8c},
10463 + {0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90,
10464 + 0x0000ff90},
10465 + {0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94,
10466 + 0x0000ff94},
10467 + {0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0,
10468 + 0x0000ffa0},
10469 + {0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4,
10470 + 0x0000ffa4},
10471 + {0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8,
10472 + 0x0000ffa8},
10473 + {0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac,
10474 + 0x0000ffac},
10475 + {0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0,
10476 + 0x0000ffb0},
10477 + {0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4,
10478 + 0x0000ffb4},
10479 + {0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1,
10480 + 0x0000ffa1},
10481 + {0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5,
10482 + 0x0000ffa5},
10483 + {0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9,
10484 + 0x0000ffa9},
10485 + {0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad,
10486 + 0x0000ffad},
10487 + {0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1,
10488 + 0x0000ffb1},
10489 + {0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5,
10490 + 0x0000ffb5},
10491 + {0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9,
10492 + 0x0000ffb9},
10493 + {0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5,
10494 + 0x0000ffc5},
10495 + {0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9,
10496 + 0x0000ffc9},
10497 + {0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd,
10498 + 0x0000ffcd},
10499 + {0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1,
10500 + 0x0000ffd1},
10501 + {0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5,
10502 + 0x0000ffd5},
10503 + {0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2,
10504 + 0x0000ffc2},
10505 + {0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6,
10506 + 0x0000ffc6},
10507 + {0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca,
10508 + 0x0000ffca},
10509 + {0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce,
10510 + 0x0000ffce},
10511 + {0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2,
10512 + 0x0000ffd2},
10513 + {0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6,
10514 + 0x0000ffd6},
10515 + {0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda,
10516 + 0x0000ffda},
10517 + {0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7,
10518 + 0x0000ffc7},
10519 + {0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb,
10520 + 0x0000ffcb},
10521 + {0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf,
10522 + 0x0000ffcf},
10523 + {0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3,
10524 + 0x0000ffd3},
10525 + {0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7,
10526 + 0x0000ffd7},
10527 + {0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10528 + 0x0000ffdb},
10529 + {0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10530 + 0x0000ffdb},
10531 + {0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10532 + 0x0000ffdb},
10533 + {0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10534 + 0x0000ffdb},
10535 + {0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10536 + 0x0000ffdb},
10537 + {0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10538 + 0x0000ffdb},
10539 + {0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10540 + 0x0000ffdb},
10541 + {0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10542 + 0x0000ffdb},
10543 + {0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10544 + 0x0000ffdb},
10545 + {0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10546 + 0x0000ffdb},
10547 + {0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10548 + 0x0000ffdb},
10549 + {0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10550 + 0x0000ffdb},
10551 + {0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10552 + 0x0000ffdb},
10553 + {0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10554 + 0x0000ffdb},
10555 + {0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10556 + 0x0000ffdb},
10557 + {0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10558 + 0x0000ffdb},
10559 + {0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10560 + 0x0000ffdb},
10561 + {0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10562 + 0x0000ffdb},
10563 + {0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10564 + 0x0000ffdb},
10565 + {0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10566 + 0x0000ffdb},
10567 + {0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10568 + 0x0000ffdb},
10569 + {0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10570 + 0x0000ffdb},
10571 + {0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10572 + 0x0000ffdb},
10573 + {0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10574 + 0x0000ffdb},
10575 + {0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10576 + 0x0000ffdb},
10577 + {0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120,
10578 + 0x0000a120},
10579 + {0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124,
10580 + 0x0000a124},
10581 + {0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128,
10582 + 0x0000a128},
10583 + {0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c,
10584 + 0x0000a12c},
10585 + {0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130,
10586 + 0x0000a130},
10587 + {0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194,
10588 + 0x0000a194},
10589 + {0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198,
10590 + 0x0000a198},
10591 + {0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c,
10592 + 0x0000a20c},
10593 + {0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210,
10594 + 0x0000a210},
10595 + {0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284,
10596 + 0x0000a284},
10597 + {0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288,
10598 + 0x0000a288},
10599 + {0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c,
10600 + 0x0000a28c},
10601 + {0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290,
10602 + 0x0000a290},
10603 + {0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294,
10604 + 0x0000a294},
10605 + {0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0,
10606 + 0x0000a2a0},
10607 + {0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4,
10608 + 0x0000a2a4},
10609 + {0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8,
10610 + 0x0000a2a8},
10611 + {0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac,
10612 + 0x0000a2ac},
10613 + {0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0,
10614 + 0x0000a2b0},
10615 + {0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4,
10616 + 0x0000a2b4},
10617 + {0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8,
10618 + 0x0000a2b8},
10619 + {0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4,
10620 + 0x0000a2c4},
10621 + {0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708,
10622 + 0x0000a708},
10623 + {0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c,
10624 + 0x0000a70c},
10625 + {0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710,
10626 + 0x0000a710},
10627 + {0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04,
10628 + 0x0000ab04},
10629 + {0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08,
10630 + 0x0000ab08},
10631 + {0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c,
10632 + 0x0000ab0c},
10633 + {0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10,
10634 + 0x0000ab10},
10635 + {0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14,
10636 + 0x0000ab14},
10637 + {0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18,
10638 + 0x0000ab18},
10639 + {0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c,
10640 + 0x0000ab8c},
10641 + {0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90,
10642 + 0x0000ab90},
10643 + {0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94,
10644 + 0x0000ab94},
10645 + {0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98,
10646 + 0x0000ab98},
10647 + {0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4,
10648 + 0x0000aba4},
10649 + {0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8,
10650 + 0x0000aba8},
10651 + {0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04,
10652 + 0x0000cb04},
10653 + {0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08,
10654 + 0x0000cb08},
10655 + {0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c,
10656 + 0x0000cb0c},
10657 + {0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10,
10658 + 0x0000cb10},
10659 + {0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14,
10660 + 0x0000cb14},
10661 + {0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18,
10662 + 0x0000cb18},
10663 + {0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c,
10664 + 0x0000cb8c},
10665 + {0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90,
10666 + 0x0000cb90},
10667 + {0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18,
10668 + 0x0000cf18},
10669 + {0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24,
10670 + 0x0000cf24},
10671 + {0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28,
10672 + 0x0000cf28},
10673 + {0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314,
10674 + 0x0000d314},
10675 + {0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318,
10676 + 0x0000d318},
10677 + {0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c,
10678 + 0x0000d38c},
10679 + {0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390,
10680 + 0x0000d390},
10681 + {0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394,
10682 + 0x0000d394},
10683 + {0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398,
10684 + 0x0000d398},
10685 + {0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4,
10686 + 0x0000d3a4},
10687 + {0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8,
10688 + 0x0000d3a8},
10689 + {0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac,
10690 + 0x0000d3ac},
10691 + {0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0,
10692 + 0x0000d3b0},
10693 + {0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380,
10694 + 0x0000f380},
10695 + {0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384,
10696 + 0x0000f384},
10697 + {0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388,
10698 + 0x0000f388},
10699 + {0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710,
10700 + 0x0000f710},
10701 + {0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714,
10702 + 0x0000f714},
10703 + {0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718,
10704 + 0x0000f718},
10705 + {0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10,
10706 + 0x0000fb10},
10707 + {0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14,
10708 + 0x0000fb14},
10709 + {0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18,
10710 + 0x0000fb18},
10711 + {0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c,
10712 + 0x0000fb8c},
10713 + {0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90,
10714 + 0x0000fb90},
10715 + {0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94,
10716 + 0x0000fb94},
10717 + {0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c,
10718 + 0x0000ff8c},
10719 + {0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90,
10720 + 0x0000ff90},
10721 + {0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94,
10722 + 0x0000ff94},
10723 + {0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0,
10724 + 0x0000ffa0},
10725 + {0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4,
10726 + 0x0000ffa4},
10727 + {0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8,
10728 + 0x0000ffa8},
10729 + {0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac,
10730 + 0x0000ffac},
10731 + {0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0,
10732 + 0x0000ffb0},
10733 + {0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4,
10734 + 0x0000ffb4},
10735 + {0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1,
10736 + 0x0000ffa1},
10737 + {0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5,
10738 + 0x0000ffa5},
10739 + {0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9,
10740 + 0x0000ffa9},
10741 + {0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad,
10742 + 0x0000ffad},
10743 + {0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1,
10744 + 0x0000ffb1},
10745 + {0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5,
10746 + 0x0000ffb5},
10747 + {0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9,
10748 + 0x0000ffb9},
10749 + {0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5,
10750 + 0x0000ffc5},
10751 + {0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9,
10752 + 0x0000ffc9},
10753 + {0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd,
10754 + 0x0000ffcd},
10755 + {0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1,
10756 + 0x0000ffd1},
10757 + {0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5,
10758 + 0x0000ffd5},
10759 + {0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2,
10760 + 0x0000ffc2},
10761 + {0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6,
10762 + 0x0000ffc6},
10763 + {0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca,
10764 + 0x0000ffca},
10765 + {0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce,
10766 + 0x0000ffce},
10767 + {0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2,
10768 + 0x0000ffd2},
10769 + {0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6,
10770 + 0x0000ffd6},
10771 + {0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda,
10772 + 0x0000ffda},
10773 + {0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7,
10774 + 0x0000ffc7},
10775 + {0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb,
10776 + 0x0000ffcb},
10777 + {0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf,
10778 + 0x0000ffcf},
10779 + {0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3,
10780 + 0x0000ffd3},
10781 + {0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7,
10782 + 0x0000ffd7},
10783 + {0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10784 + 0x0000ffdb},
10785 + {0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10786 + 0x0000ffdb},
10787 + {0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10788 + 0x0000ffdb},
10789 + {0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10790 + 0x0000ffdb},
10791 + {0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10792 + 0x0000ffdb},
10793 + {0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10794 + 0x0000ffdb},
10795 + {0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10796 + 0x0000ffdb},
10797 + {0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10798 + 0x0000ffdb},
10799 + {0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10800 + 0x0000ffdb},
10801 + {0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10802 + 0x0000ffdb},
10803 + {0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10804 + 0x0000ffdb},
10805 + {0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10806 + 0x0000ffdb},
10807 + {0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10808 + 0x0000ffdb},
10809 + {0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10810 + 0x0000ffdb},
10811 + {0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10812 + 0x0000ffdb},
10813 + {0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10814 + 0x0000ffdb},
10815 + {0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10816 + 0x0000ffdb},
10817 + {0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10818 + 0x0000ffdb},
10819 + {0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10820 + 0x0000ffdb},
10821 + {0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10822 + 0x0000ffdb},
10823 + {0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10824 + 0x0000ffdb},
10825 + {0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10826 + 0x0000ffdb},
10827 + {0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10828 + 0x0000ffdb},
10829 + {0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10830 + 0x0000ffdb},
10831 + {0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10832 + 0x0000ffdb},
10833 + {0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067,
10834 + 0x00001067},
10835 + {0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067,
10836 + 0x00001067},
10837 +};
10838 +
10839 +static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_0[][2] = {
10840 + {0x00004040, 0x9248fd00},
10841 + {0x00004040, 0x24924924},
10842 + {0x00004040, 0xa8000019},
10843 + {0x00004040, 0x13160820},
10844 + {0x00004040, 0xe5980560},
10845 + {0x00004040, 0xc01dcffd},
10846 + {0x00004040, 0x1aaabe41},
10847 + {0x00004040, 0xbe105554},
10848 + {0x00004040, 0x00043007},
10849 + {0x00004044, 0x00000000},
10850 +};
10851 +
10852 +static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_0[][2] = {
10853 + {0x00004040, 0x9248fd00},
10854 + {0x00004040, 0x24924924},
10855 + {0x00004040, 0xa8000019},
10856 + {0x00004040, 0x13160820},
10857 + {0x00004040, 0xe5980560},
10858 + {0x00004040, 0xc01dcffc},
10859 + {0x00004040, 0x1aaabe41},
10860 + {0x00004040, 0xbe105554},
10861 + {0x00004040, 0x00043007},
10862 + {0x00004044, 0x00000000},
10863 +};
10864 +
10865 +/* AR9287 Revision 11 */
10866 +
10867 +static const u_int32_t ar9287Modes_9287_1_1[][6] = {
10868 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
10869 + {0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160,
10870 + 0x000001e0},
10871 + {0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c,
10872 + 0x000001e0},
10873 + {0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38,
10874 + 0x00001180},
10875 + {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
10876 + 0x00000008},
10877 + {0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00,
10878 + 0x06e006e0},
10879 + {0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b,
10880 + 0x0988004f},
10881 + {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810,
10882 + 0x08f04810},
10883 + {0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a,
10884 + 0x0000320a},
10885 + {0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440,
10886 + 0x00006880},
10887 + {0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300,
10888 + 0x00000303},
10889 + {0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200,
10890 + 0x02020200},
10891 + {0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e,
10892 + 0x01000e0e},
10893 + {0x00009828, 0x00000000, 0x00000000, 0x3a020001, 0x3a020001,
10894 + 0x3a020001},
10895 + {0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e,
10896 + 0x00000e0e},
10897 + {0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007,
10898 + 0x00000007},
10899 + {0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e,
10900 + 0x206a012e},
10901 + {0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0,
10902 + 0x037216a0},
10903 + {0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2,
10904 + 0x6c4000e2},
10905 + {0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e,
10906 + 0x7ec84d2e},
10907 + {0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e,
10908 + 0x31395d5e},
10909 + {0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20,
10910 + 0x00058d18},
10911 + {0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00,
10912 + 0x0001ce00},
10913 + {0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0,
10914 + 0x5ac640d0},
10915 + {0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881,
10916 + 0x06903881},
10917 + {0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898,
10918 + 0x000007d0},
10919 + {0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b,
10920 + 0x00000016},
10921 + {0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d,
10922 + 0xd00a8a0d},
10923 + {0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010,
10924 + 0xefbc1010},
10925 + {0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010,
10926 + 0x00000010},
10927 + {0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010,
10928 + 0x00000010},
10929 + {0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210,
10930 + 0x00000210},
10931 + {0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce,
10932 + 0x000003ce},
10933 + {0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c,
10934 + 0x0000001c},
10935 + {0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00,
10936 + 0x00000c00},
10937 + {0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4,
10938 + 0x05eea6d4},
10939 + {0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444,
10940 + 0x00000444},
10941 + {0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
10942 + 0x00000000},
10943 + {0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
10944 + 0x00000000},
10945 + {0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a,
10946 + 0x1883800a},
10947 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
10948 + 0x00000000},
10949 + {0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000,
10950 + 0x0004a000},
10951 + {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e,
10952 + 0x7999aa0e},
10953 + {0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
10954 + 0x00000000},
10955 +};
10956 +
10957 +static const u_int32_t ar9287Common_9287_1_1[][2] = {
10958 + {0x0000000c, 0x00000000},
10959 + {0x00000030, 0x00020015},
10960 + {0x00000034, 0x00000005},
10961 + {0x00000040, 0x00000000},
10962 + {0x00000044, 0x00000008},
10963 + {0x00000048, 0x00000008},
10964 + {0x0000004c, 0x00000010},
10965 + {0x00000050, 0x00000000},
10966 + {0x00000054, 0x0000001f},
10967 + {0x00000800, 0x00000000},
10968 + {0x00000804, 0x00000000},
10969 + {0x00000808, 0x00000000},
10970 + {0x0000080c, 0x00000000},
10971 + {0x00000810, 0x00000000},
10972 + {0x00000814, 0x00000000},
10973 + {0x00000818, 0x00000000},
10974 + {0x0000081c, 0x00000000},
10975 + {0x00000820, 0x00000000},
10976 + {0x00000824, 0x00000000},
10977 + {0x00001040, 0x002ffc0f},
10978 + {0x00001044, 0x002ffc0f},
10979 + {0x00001048, 0x002ffc0f},
10980 + {0x0000104c, 0x002ffc0f},
10981 + {0x00001050, 0x002ffc0f},
10982 + {0x00001054, 0x002ffc0f},
10983 + {0x00001058, 0x002ffc0f},
10984 + {0x0000105c, 0x002ffc0f},
10985 + {0x00001060, 0x002ffc0f},
10986 + {0x00001064, 0x002ffc0f},
10987 + {0x00001230, 0x00000000},
10988 + {0x00001270, 0x00000000},
10989 + {0x00001038, 0x00000000},
10990 + {0x00001078, 0x00000000},
10991 + {0x000010b8, 0x00000000},
10992 + {0x000010f8, 0x00000000},
10993 + {0x00001138, 0x00000000},
10994 + {0x00001178, 0x00000000},
10995 + {0x000011b8, 0x00000000},
10996 + {0x000011f8, 0x00000000},
10997 + {0x00001238, 0x00000000},
10998 + {0x00001278, 0x00000000},
10999 + {0x000012b8, 0x00000000},
11000 + {0x000012f8, 0x00000000},
11001 + {0x00001338, 0x00000000},
11002 + {0x00001378, 0x00000000},
11003 + {0x000013b8, 0x00000000},
11004 + {0x000013f8, 0x00000000},
11005 + {0x00001438, 0x00000000},
11006 + {0x00001478, 0x00000000},
11007 + {0x000014b8, 0x00000000},
11008 + {0x000014f8, 0x00000000},
11009 + {0x00001538, 0x00000000},
11010 + {0x00001578, 0x00000000},
11011 + {0x000015b8, 0x00000000},
11012 + {0x000015f8, 0x00000000},
11013 + {0x00001638, 0x00000000},
11014 + {0x00001678, 0x00000000},
11015 + {0x000016b8, 0x00000000},
11016 + {0x000016f8, 0x00000000},
11017 + {0x00001738, 0x00000000},
11018 + {0x00001778, 0x00000000},
11019 + {0x000017b8, 0x00000000},
11020 + {0x000017f8, 0x00000000},
11021 + {0x0000103c, 0x00000000},
11022 + {0x0000107c, 0x00000000},
11023 + {0x000010bc, 0x00000000},
11024 + {0x000010fc, 0x00000000},
11025 + {0x0000113c, 0x00000000},
11026 + {0x0000117c, 0x00000000},
11027 + {0x000011bc, 0x00000000},
11028 + {0x000011fc, 0x00000000},
11029 + {0x0000123c, 0x00000000},
11030 + {0x0000127c, 0x00000000},
11031 + {0x000012bc, 0x00000000},
11032 + {0x000012fc, 0x00000000},
11033 + {0x0000133c, 0x00000000},
11034 + {0x0000137c, 0x00000000},
11035 + {0x000013bc, 0x00000000},
11036 + {0x000013fc, 0x00000000},
11037 + {0x0000143c, 0x00000000},
11038 + {0x0000147c, 0x00000000},
11039 + {0x00004030, 0x00000002},
11040 + {0x0000403c, 0x00000002},
11041 + {0x00004024, 0x0000001f},
11042 + {0x00004060, 0x00000000},
11043 + {0x00004064, 0x00000000},
11044 + {0x00007010, 0x00000033},
11045 + {0x00007020, 0x00000000},
11046 + {0x00007034, 0x00000002},
11047 + {0x00007038, 0x000004c2},
11048 + {0x00008004, 0x00000000},
11049 + {0x00008008, 0x00000000},
11050 + {0x0000800c, 0x00000000},
11051 + {0x00008018, 0x00000700},
11052 + {0x00008020, 0x00000000},
11053 + {0x00008038, 0x00000000},
11054 + {0x0000803c, 0x00000000},
11055 + {0x00008048, 0x40000000},
11056 + {0x00008054, 0x00000000},
11057 + {0x00008058, 0x00000000},
11058 + {0x0000805c, 0x000fc78f},
11059 + {0x00008060, 0x0000000f},
11060 + {0x00008064, 0x00000000},
11061 + {0x00008070, 0x00000000},
11062 + {0x000080c0, 0x2a80001a},
11063 + {0x000080c4, 0x05dc01e0},
11064 + {0x000080c8, 0x1f402710},
11065 + {0x000080cc, 0x01f40000},
11066 + {0x000080d0, 0x00001e00},
11067 + {0x000080d4, 0x00000000},
11068 + {0x000080d8, 0x00400000},
11069 + {0x000080e0, 0xffffffff},
11070 + {0x000080e4, 0x0000ffff},
11071 + {0x000080e8, 0x003f3f3f},
11072 + {0x000080ec, 0x00000000},
11073 + {0x000080f0, 0x00000000},
11074 + {0x000080f4, 0x00000000},
11075 + {0x000080f8, 0x00000000},
11076 + {0x000080fc, 0x00020000},
11077 + {0x00008100, 0x00020000},
11078 + {0x00008104, 0x00000001},
11079 + {0x00008108, 0x00000052},
11080 + {0x0000810c, 0x00000000},
11081 + {0x00008110, 0x00000168},
11082 + {0x00008118, 0x000100aa},
11083 + {0x0000811c, 0x00003210},
11084 + {0x00008124, 0x00000000},
11085 + {0x00008128, 0x00000000},
11086 + {0x0000812c, 0x00000000},
11087 + {0x00008130, 0x00000000},
11088 + {0x00008134, 0x00000000},
11089 + {0x00008138, 0x00000000},
11090 + {0x0000813c, 0x00000000},
11091 + {0x00008144, 0xffffffff},
11092 + {0x00008168, 0x00000000},
11093 + {0x0000816c, 0x00000000},
11094 + {0x00008170, 0x18487320},
11095 + {0x00008174, 0xfaa4fa50},
11096 + {0x00008178, 0x00000100},
11097 + {0x0000817c, 0x00000000},
11098 + {0x000081c0, 0x00000000},
11099 + {0x000081c4, 0x00000000},
11100 + {0x000081d4, 0x00000000},
11101 + {0x000081ec, 0x00000000},
11102 + {0x000081f0, 0x00000000},
11103 + {0x000081f4, 0x00000000},
11104 + {0x000081f8, 0x00000000},
11105 + {0x000081fc, 0x00000000},
11106 + {0x00008200, 0x00000000},
11107 + {0x00008204, 0x00000000},
11108 + {0x00008208, 0x00000000},
11109 + {0x0000820c, 0x00000000},
11110 + {0x00008210, 0x00000000},
11111 + {0x00008214, 0x00000000},
11112 + {0x00008218, 0x00000000},
11113 + {0x0000821c, 0x00000000},
11114 + {0x00008220, 0x00000000},
11115 + {0x00008224, 0x00000000},
11116 + {0x00008228, 0x00000000},
11117 + {0x0000822c, 0x00000000},
11118 + {0x00008230, 0x00000000},
11119 + {0x00008234, 0x00000000},
11120 + {0x00008238, 0x00000000},
11121 + {0x0000823c, 0x00000000},
11122 + {0x00008240, 0x00100000},
11123 + {0x00008244, 0x0010f400},
11124 + {0x00008248, 0x00000100},
11125 + {0x0000824c, 0x0001e800},
11126 + {0x00008250, 0x00000000},
11127 + {0x00008254, 0x00000000},
11128 + {0x00008258, 0x00000000},
11129 + {0x0000825c, 0x400000ff},
11130 + {0x00008260, 0x00080922},
11131 + {0x00008264, 0x88a00010},
11132 + {0x00008270, 0x00000000},
11133 + {0x00008274, 0x40000000},
11134 + {0x00008278, 0x003e4180},
11135 + {0x0000827c, 0x00000000},
11136 + {0x00008284, 0x0000002c},
11137 + {0x00008288, 0x0000002c},
11138 + {0x0000828c, 0x000000ff},
11139 + {0x00008294, 0x00000000},
11140 + {0x00008298, 0x00000000},
11141 + {0x0000829c, 0x00000000},
11142 + {0x00008300, 0x00000040},
11143 + {0x00008314, 0x00000000},
11144 + {0x00008328, 0x00000000},
11145 + {0x0000832c, 0x00000007},
11146 + {0x00008330, 0x00000302},
11147 + {0x00008334, 0x00000e00},
11148 + {0x00008338, 0x00ff0000},
11149 + {0x0000833c, 0x00000000},
11150 + {0x00008340, 0x000107ff},
11151 + {0x00008344, 0x01c81043},
11152 + {0x00008360, 0xffffffff},
11153 + {0x00008364, 0xffffffff},
11154 + {0x00008368, 0x00000000},
11155 + {0x00008370, 0x00000000},
11156 + {0x00008374, 0x000000ff},
11157 + {0x00008378, 0x00000000},
11158 + {0x0000837c, 0x00000000},
11159 + {0x00008380, 0xffffffff},
11160 + {0x00008384, 0xffffffff},
11161 + {0x00008390, 0x0fffffff},
11162 + {0x00008394, 0x0fffffff},
11163 + {0x00008398, 0x00000000},
11164 + {0x0000839c, 0x00000000},
11165 + {0x000083a0, 0x00000000},
11166 + {0x00009808, 0x00000000},
11167 + {0x0000980c, 0xafe68e30},
11168 + {0x00009810, 0xfd14e000},
11169 + {0x00009814, 0x9c0a9f6b},
11170 + {0x0000981c, 0x00000000},
11171 + {0x0000982c, 0x0000a000},
11172 + {0x00009830, 0x00000000},
11173 + {0x0000983c, 0x00200400},
11174 + {0x0000984c, 0x0040233c},
11175 + {0x0000a84c, 0x0040233c},
11176 + {0x00009854, 0x00000044},
11177 + {0x00009900, 0x00000000},
11178 + {0x00009904, 0x00000000},
11179 + {0x00009908, 0x00000000},
11180 + {0x0000990c, 0x00000000},
11181 + {0x00009910, 0x10002310},
11182 + {0x0000991c, 0x10000fff},
11183 + {0x00009920, 0x04900000},
11184 + {0x0000a920, 0x04900000},
11185 + {0x00009928, 0x00000001},
11186 + {0x0000992c, 0x00000004},
11187 + {0x00009930, 0x00000000},
11188 + {0x0000a930, 0x00000000},
11189 + {0x00009934, 0x1e1f2022},
11190 + {0x00009938, 0x0a0b0c0d},
11191 + {0x0000993c, 0x00000000},
11192 + {0x00009948, 0x9280c00a},
11193 + {0x0000994c, 0x00020028},
11194 + {0x00009954, 0x5f3ca3de},
11195 + {0x00009958, 0x0108ecff},
11196 + {0x00009940, 0x14750604},
11197 + {0x0000c95c, 0x004b6a8e},
11198 + {0x00009970, 0x990bb514},
11199 + {0x00009974, 0x00000000},
11200 + {0x00009978, 0x00000001},
11201 + {0x0000997c, 0x00000000},
11202 + {0x000099a0, 0x00000000},
11203 + {0x000099a4, 0x00000001},
11204 + {0x000099a8, 0x201fff00},
11205 + {0x000099ac, 0x0c6f0000},
11206 + {0x000099b0, 0x03051000},
11207 + {0x000099b4, 0x00000820},
11208 + {0x000099c4, 0x06336f77},
11209 + {0x000099c8, 0x6af6532f},
11210 + {0x000099cc, 0x08f186c8},
11211 + {0x000099d0, 0x00046384},
11212 + {0x000099dc, 0x00000000},
11213 + {0x000099e0, 0x00000000},
11214 + {0x000099e4, 0xaaaaaaaa},
11215 + {0x000099e8, 0x3c466478},
11216 + {0x000099ec, 0x0cc80caa},
11217 + {0x000099f0, 0x00000000},
11218 + {0x000099fc, 0x00001042},
11219 + {0x0000a208, 0x803e4788},
11220 + {0x0000a210, 0x4080a333},
11221 + {0x0000a214, 0x40206c10},
11222 + {0x0000a218, 0x009c4060},
11223 + {0x0000a220, 0x01834061},
11224 + {0x0000a224, 0x00000400},
11225 + {0x0000a228, 0x000003b5},
11226 + {0x0000a22c, 0x233f7180},
11227 + {0x0000a234, 0x20202020},
11228 + {0x0000a238, 0x20202020},
11229 + {0x0000a23c, 0x13c889af},
11230 + {0x0000a240, 0x38490a20},
11231 + {0x0000a244, 0x00000000},
11232 + {0x0000a248, 0xfffffffc},
11233 + {0x0000a24c, 0x00000000},
11234 + {0x0000a254, 0x00000000},
11235 + {0x0000a258, 0x0cdbd380},
11236 + {0x0000a25c, 0x0f0f0f01},
11237 + {0x0000a260, 0xdfa91f01},
11238 + {0x0000a264, 0x00418a11},
11239 + {0x0000b264, 0x00418a11},
11240 + {0x0000a268, 0x00000000},
11241 + {0x0000a26c, 0x0e79e5c6},
11242 + {0x0000b26c, 0x0e79e5c6},
11243 + {0x0000d270, 0x00820820},
11244 + {0x0000a278, 0x1ce739ce},
11245 + {0x0000a27c, 0x050701ce},
11246 + {0x0000d35c, 0x07ffffef},
11247 + {0x0000d360, 0x0fffffe7},
11248 + {0x0000d364, 0x17ffffe5},
11249 + {0x0000d368, 0x1fffffe4},
11250 + {0x0000d36c, 0x37ffffe3},
11251 + {0x0000d370, 0x3fffffe3},
11252 + {0x0000d374, 0x57ffffe3},
11253 + {0x0000d378, 0x5fffffe2},
11254 + {0x0000d37c, 0x7fffffe2},
11255 + {0x0000d380, 0x7f3c7bba},
11256 + {0x0000d384, 0xf3307ff0},
11257 + {0x0000a388, 0x0c000000},
11258 + {0x0000a38c, 0x20202020},
11259 + {0x0000a390, 0x20202020},
11260 + {0x0000a394, 0x1ce739ce},
11261 + {0x0000a398, 0x000001ce},
11262 + {0x0000b398, 0x000001ce},
11263 + {0x0000a39c, 0x00000001},
11264 + {0x0000a3c8, 0x00000246},
11265 + {0x0000a3cc, 0x20202020},
11266 + {0x0000a3d0, 0x20202020},
11267 + {0x0000a3d4, 0x20202020},
11268 + {0x0000a3dc, 0x1ce739ce},
11269 + {0x0000a3e0, 0x000001ce},
11270 + {0x0000a3e4, 0x00000000},
11271 + {0x0000a3e8, 0x18c43433},
11272 + {0x0000a3ec, 0x00f70081},
11273 + {0x0000a3f0, 0x01036a1e},
11274 + {0x0000a3f4, 0x00000000},
11275 + {0x0000b3f4, 0x00000000},
11276 + {0x0000a7d8, 0x000003f1},
11277 + {0x00007800, 0x00000800},
11278 + {0x00007804, 0x6c35ffd2},
11279 + {0x00007808, 0x6db6c000},
11280 + {0x0000780c, 0x6db6cb30},
11281 + {0x00007810, 0x6db6cb6c},
11282 + {0x00007814, 0x0501e200},
11283 + {0x00007818, 0x0094128d},
11284 + {0x0000781c, 0x976ee392},
11285 + {0x00007820, 0xf75ff6fc},
11286 + {0x00007824, 0x00040000},
11287 + {0x00007828, 0xdb003012},
11288 + {0x0000782c, 0x04924914},
11289 + {0x00007830, 0x21084210},
11290 + {0x00007834, 0x00140000},
11291 + {0x00007838, 0x0e4548d8},
11292 + {0x0000783c, 0x54214514},
11293 + {0x00007840, 0x02025830},
11294 + {0x00007844, 0x71c0d388},
11295 + {0x00007848, 0x934934a8},
11296 + {0x00007850, 0x00000000},
11297 + {0x00007854, 0x00000800},
11298 + {0x00007858, 0x6c35ffd2},
11299 + {0x0000785c, 0x6db6c000},
11300 + {0x00007860, 0x6db6cb30},
11301 + {0x00007864, 0x6db6cb6c},
11302 + {0x00007868, 0x0501e200},
11303 + {0x0000786c, 0x0094128d},
11304 + {0x00007870, 0x976ee392},
11305 + {0x00007874, 0xf75ff6fc},
11306 + {0x00007878, 0x00040000},
11307 + {0x0000787c, 0xdb003012},
11308 + {0x00007880, 0x04924914},
11309 + {0x00007884, 0x21084210},
11310 + {0x00007888, 0x001b6db0},
11311 + {0x0000788c, 0x00376b63},
11312 + {0x00007890, 0x06db6db6},
11313 + {0x00007894, 0x006d8000},
11314 + {0x00007898, 0x48100000},
11315 + {0x0000789c, 0x00000000},
11316 + {0x000078a0, 0x08000000},
11317 + {0x000078a4, 0x0007ffd8},
11318 + {0x000078a8, 0x0007ffd8},
11319 + {0x000078ac, 0x001c0020},
11320 + {0x000078b0, 0x00060aeb},
11321 + {0x000078b4, 0x40008080},
11322 + {0x000078b8, 0x2a850160},
11323 +};
11324 +
11325 +/*
11326 + * For Japanese regulatory requirements, 2484 MHz requires the following three
11327 + * registers be programmed differently from the channel between 2412 and 2472 MHz.
11328 + */
11329 +static const u_int32_t ar9287Common_normal_cck_fir_coeff_92871_1[][2] = {
11330 + {0x0000a1f4, 0x00fffeff},
11331 + {0x0000a1f8, 0x00f5f9ff},
11332 + {0x0000a1fc, 0xb79f6427},
11333 +};
11334 +
11335 +static const u_int32_t ar9287Common_japan_2484_cck_fir_coeff_92871_1[][2] = {
11336 + {0x0000a1f4, 0x00000000},
11337 + {0x0000a1f8, 0xefff0301},
11338 + {0x0000a1fc, 0xca9228ee},
11339 +};
11340 +
11341 +static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = {
11342 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
11343 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
11344 + 0x00000000},
11345 + {0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002,
11346 + 0x00004002},
11347 + {0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004,
11348 + 0x00008004},
11349 + {0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a,
11350 + 0x0000c00a},
11351 + {0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c,
11352 + 0x0001000c},
11353 + {0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b,
11354 + 0x0001420b},
11355 + {0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a,
11356 + 0x0001824a},
11357 + {0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a,
11358 + 0x0001c44a},
11359 + {0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a,
11360 + 0x0002064a},
11361 + {0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a,
11362 + 0x0002484a},
11363 + {0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a,
11364 + 0x00028a4a},
11365 + {0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a,
11366 + 0x0002cc4a},
11367 + {0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a,
11368 + 0x00030e4a},
11369 + {0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a,
11370 + 0x00034e8a},
11371 + {0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c,
11372 + 0x00038e8c},
11373 + {0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc,
11374 + 0x0003cecc},
11375 + {0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4,
11376 + 0x00040ed4},
11377 + {0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc,
11378 + 0x00044edc},
11379 + {0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede,
11380 + 0x00048ede},
11381 + {0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e,
11382 + 0x0004cf1e},
11383 + {0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e,
11384 + 0x00050f5e},
11385 + {0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e,
11386 + 0x00054f9e},
11387 + {0x0000a780, 0x00000000, 0x00000000, 0x00000062, 0x00000062,
11388 + 0x00000062},
11389 + {0x0000a784, 0x00000000, 0x00000000, 0x00004064, 0x00004064,
11390 + 0x00004064},
11391 + {0x0000a788, 0x00000000, 0x00000000, 0x000080a4, 0x000080a4,
11392 + 0x000080a4},
11393 + {0x0000a78c, 0x00000000, 0x00000000, 0x0000c0aa, 0x0000c0aa,
11394 + 0x0000c0aa},
11395 + {0x0000a790, 0x00000000, 0x00000000, 0x000100ac, 0x000100ac,
11396 + 0x000100ac},
11397 + {0x0000a794, 0x00000000, 0x00000000, 0x000140b4, 0x000140b4,
11398 + 0x000140b4},
11399 + {0x0000a798, 0x00000000, 0x00000000, 0x000180f4, 0x000180f4,
11400 + 0x000180f4},
11401 + {0x0000a79c, 0x00000000, 0x00000000, 0x0001c134, 0x0001c134,
11402 + 0x0001c134},
11403 + {0x0000a7a0, 0x00000000, 0x00000000, 0x00020174, 0x00020174,
11404 + 0x00020174},
11405 + {0x0000a7a4, 0x00000000, 0x00000000, 0x0002417c, 0x0002417c,
11406 + 0x0002417c},
11407 + {0x0000a7a8, 0x00000000, 0x00000000, 0x0002817e, 0x0002817e,
11408 + 0x0002817e},
11409 + {0x0000a7ac, 0x00000000, 0x00000000, 0x0002c1be, 0x0002c1be,
11410 + 0x0002c1be},
11411 + {0x0000a7b0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11412 + 0x000301fe},
11413 + {0x0000a7b4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11414 + 0x000301fe},
11415 + {0x0000a7b8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11416 + 0x000301fe},
11417 + {0x0000a7bc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11418 + 0x000301fe},
11419 + {0x0000a7c0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11420 + 0x000301fe},
11421 + {0x0000a7c4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11422 + 0x000301fe},
11423 + {0x0000a7c8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11424 + 0x000301fe},
11425 + {0x0000a7cc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11426 + 0x000301fe},
11427 + {0x0000a7d0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11428 + 0x000301fe},
11429 + {0x0000a7d4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11430 + 0x000301fe},
11431 + {0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000,
11432 + 0x0a1aa000},
11433 +};
11434 +
11435 +static const u_int32_t ar9287Modes_rx_gain_9287_1_1[][6] = {
11436 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
11437 + {0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120,
11438 + 0x0000a120},
11439 + {0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124,
11440 + 0x0000a124},
11441 + {0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128,
11442 + 0x0000a128},
11443 + {0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c,
11444 + 0x0000a12c},
11445 + {0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130,
11446 + 0x0000a130},
11447 + {0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194,
11448 + 0x0000a194},
11449 + {0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198,
11450 + 0x0000a198},
11451 + {0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c,
11452 + 0x0000a20c},
11453 + {0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210,
11454 + 0x0000a210},
11455 + {0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284,
11456 + 0x0000a284},
11457 + {0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288,
11458 + 0x0000a288},
11459 + {0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c,
11460 + 0x0000a28c},
11461 + {0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290,
11462 + 0x0000a290},
11463 + {0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294,
11464 + 0x0000a294},
11465 + {0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0,
11466 + 0x0000a2a0},
11467 + {0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4,
11468 + 0x0000a2a4},
11469 + {0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8,
11470 + 0x0000a2a8},
11471 + {0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac,
11472 + 0x0000a2ac},
11473 + {0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0,
11474 + 0x0000a2b0},
11475 + {0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4,
11476 + 0x0000a2b4},
11477 + {0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8,
11478 + 0x0000a2b8},
11479 + {0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4,
11480 + 0x0000a2c4},
11481 + {0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708,
11482 + 0x0000a708},
11483 + {0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c,
11484 + 0x0000a70c},
11485 + {0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710,
11486 + 0x0000a710},
11487 + {0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04,
11488 + 0x0000ab04},
11489 + {0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08,
11490 + 0x0000ab08},
11491 + {0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c,
11492 + 0x0000ab0c},
11493 + {0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10,
11494 + 0x0000ab10},
11495 + {0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14,
11496 + 0x0000ab14},
11497 + {0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18,
11498 + 0x0000ab18},
11499 + {0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c,
11500 + 0x0000ab8c},
11501 + {0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90,
11502 + 0x0000ab90},
11503 + {0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94,
11504 + 0x0000ab94},
11505 + {0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98,
11506 + 0x0000ab98},
11507 + {0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4,
11508 + 0x0000aba4},
11509 + {0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8,
11510 + 0x0000aba8},
11511 + {0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04,
11512 + 0x0000cb04},
11513 + {0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08,
11514 + 0x0000cb08},
11515 + {0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c,
11516 + 0x0000cb0c},
11517 + {0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10,
11518 + 0x0000cb10},
11519 + {0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14,
11520 + 0x0000cb14},
11521 + {0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18,
11522 + 0x0000cb18},
11523 + {0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c,
11524 + 0x0000cb8c},
11525 + {0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90,
11526 + 0x0000cb90},
11527 + {0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18,
11528 + 0x0000cf18},
11529 + {0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24,
11530 + 0x0000cf24},
11531 + {0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28,
11532 + 0x0000cf28},
11533 + {0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314,
11534 + 0x0000d314},
11535 + {0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318,
11536 + 0x0000d318},
11537 + {0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c,
11538 + 0x0000d38c},
11539 + {0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390,
11540 + 0x0000d390},
11541 + {0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394,
11542 + 0x0000d394},
11543 + {0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398,
11544 + 0x0000d398},
11545 + {0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4,
11546 + 0x0000d3a4},
11547 + {0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8,
11548 + 0x0000d3a8},
11549 + {0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac,
11550 + 0x0000d3ac},
11551 + {0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0,
11552 + 0x0000d3b0},
11553 + {0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380,
11554 + 0x0000f380},
11555 + {0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384,
11556 + 0x0000f384},
11557 + {0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388,
11558 + 0x0000f388},
11559 + {0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710,
11560 + 0x0000f710},
11561 + {0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714,
11562 + 0x0000f714},
11563 + {0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718,
11564 + 0x0000f718},
11565 + {0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10,
11566 + 0x0000fb10},
11567 + {0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14,
11568 + 0x0000fb14},
11569 + {0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18,
11570 + 0x0000fb18},
11571 + {0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c,
11572 + 0x0000fb8c},
11573 + {0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90,
11574 + 0x0000fb90},
11575 + {0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94,
11576 + 0x0000fb94},
11577 + {0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c,
11578 + 0x0000ff8c},
11579 + {0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90,
11580 + 0x0000ff90},
11581 + {0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94,
11582 + 0x0000ff94},
11583 + {0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0,
11584 + 0x0000ffa0},
11585 + {0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4,
11586 + 0x0000ffa4},
11587 + {0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8,
11588 + 0x0000ffa8},
11589 + {0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac,
11590 + 0x0000ffac},
11591 + {0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0,
11592 + 0x0000ffb0},
11593 + {0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4,
11594 + 0x0000ffb4},
11595 + {0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1,
11596 + 0x0000ffa1},
11597 + {0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5,
11598 + 0x0000ffa5},
11599 + {0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9,
11600 + 0x0000ffa9},
11601 + {0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad,
11602 + 0x0000ffad},
11603 + {0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1,
11604 + 0x0000ffb1},
11605 + {0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5,
11606 + 0x0000ffb5},
11607 + {0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9,
11608 + 0x0000ffb9},
11609 + {0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5,
11610 + 0x0000ffc5},
11611 + {0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9,
11612 + 0x0000ffc9},
11613 + {0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd,
11614 + 0x0000ffcd},
11615 + {0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1,
11616 + 0x0000ffd1},
11617 + {0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5,
11618 + 0x0000ffd5},
11619 + {0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2,
11620 + 0x0000ffc2},
11621 + {0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6,
11622 + 0x0000ffc6},
11623 + {0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca,
11624 + 0x0000ffca},
11625 + {0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce,
11626 + 0x0000ffce},
11627 + {0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2,
11628 + 0x0000ffd2},
11629 + {0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6,
11630 + 0x0000ffd6},
11631 + {0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda,
11632 + 0x0000ffda},
11633 + {0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7,
11634 + 0x0000ffc7},
11635 + {0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb,
11636 + 0x0000ffcb},
11637 + {0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf,
11638 + 0x0000ffcf},
11639 + {0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3,
11640 + 0x0000ffd3},
11641 + {0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7,
11642 + 0x0000ffd7},
11643 + {0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11644 + 0x0000ffdb},
11645 + {0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11646 + 0x0000ffdb},
11647 + {0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11648 + 0x0000ffdb},
11649 + {0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11650 + 0x0000ffdb},
11651 + {0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11652 + 0x0000ffdb},
11653 + {0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11654 + 0x0000ffdb},
11655 + {0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11656 + 0x0000ffdb},
11657 + {0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11658 + 0x0000ffdb},
11659 + {0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11660 + 0x0000ffdb},
11661 + {0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11662 + 0x0000ffdb},
11663 + {0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11664 + 0x0000ffdb},
11665 + {0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11666 + 0x0000ffdb},
11667 + {0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11668 + 0x0000ffdb},
11669 + {0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11670 + 0x0000ffdb},
11671 + {0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11672 + 0x0000ffdb},
11673 + {0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11674 + 0x0000ffdb},
11675 + {0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11676 + 0x0000ffdb},
11677 + {0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11678 + 0x0000ffdb},
11679 + {0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11680 + 0x0000ffdb},
11681 + {0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11682 + 0x0000ffdb},
11683 + {0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11684 + 0x0000ffdb},
11685 + {0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11686 + 0x0000ffdb},
11687 + {0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11688 + 0x0000ffdb},
11689 + {0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11690 + 0x0000ffdb},
11691 + {0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11692 + 0x0000ffdb},
11693 + {0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120,
11694 + 0x0000a120},
11695 + {0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124,
11696 + 0x0000a124},
11697 + {0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128,
11698 + 0x0000a128},
11699 + {0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c,
11700 + 0x0000a12c},
11701 + {0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130,
11702 + 0x0000a130},
11703 + {0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194,
11704 + 0x0000a194},
11705 + {0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198,
11706 + 0x0000a198},
11707 + {0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c,
11708 + 0x0000a20c},
11709 + {0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210,
11710 + 0x0000a210},
11711 + {0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284,
11712 + 0x0000a284},
11713 + {0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288,
11714 + 0x0000a288},
11715 + {0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c,
11716 + 0x0000a28c},
11717 + {0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290,
11718 + 0x0000a290},
11719 + {0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294,
11720 + 0x0000a294},
11721 + {0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0,
11722 + 0x0000a2a0},
11723 + {0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4,
11724 + 0x0000a2a4},
11725 + {0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8,
11726 + 0x0000a2a8},
11727 + {0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac,
11728 + 0x0000a2ac},
11729 + {0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0,
11730 + 0x0000a2b0},
11731 + {0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4,
11732 + 0x0000a2b4},
11733 + {0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8,
11734 + 0x0000a2b8},
11735 + {0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4,
11736 + 0x0000a2c4},
11737 + {0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708,
11738 + 0x0000a708},
11739 + {0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c,
11740 + 0x0000a70c},
11741 + {0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710,
11742 + 0x0000a710},
11743 + {0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04,
11744 + 0x0000ab04},
11745 + {0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08,
11746 + 0x0000ab08},
11747 + {0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c,
11748 + 0x0000ab0c},
11749 + {0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10,
11750 + 0x0000ab10},
11751 + {0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14,
11752 + 0x0000ab14},
11753 + {0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18,
11754 + 0x0000ab18},
11755 + {0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c,
11756 + 0x0000ab8c},
11757 + {0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90,
11758 + 0x0000ab90},
11759 + {0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94,
11760 + 0x0000ab94},
11761 + {0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98,
11762 + 0x0000ab98},
11763 + {0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4,
11764 + 0x0000aba4},
11765 + {0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8,
11766 + 0x0000aba8},
11767 + {0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04,
11768 + 0x0000cb04},
11769 + {0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08,
11770 + 0x0000cb08},
11771 + {0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c,
11772 + 0x0000cb0c},
11773 + {0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10,
11774 + 0x0000cb10},
11775 + {0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14,
11776 + 0x0000cb14},
11777 + {0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18,
11778 + 0x0000cb18},
11779 + {0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c,
11780 + 0x0000cb8c},
11781 + {0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90,
11782 + 0x0000cb90},
11783 + {0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18,
11784 + 0x0000cf18},
11785 + {0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24,
11786 + 0x0000cf24},
11787 + {0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28,
11788 + 0x0000cf28},
11789 + {0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314,
11790 + 0x0000d314},
11791 + {0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318,
11792 + 0x0000d318},
11793 + {0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c,
11794 + 0x0000d38c},
11795 + {0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390,
11796 + 0x0000d390},
11797 + {0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394,
11798 + 0x0000d394},
11799 + {0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398,
11800 + 0x0000d398},
11801 + {0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4,
11802 + 0x0000d3a4},
11803 + {0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8,
11804 + 0x0000d3a8},
11805 + {0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac,
11806 + 0x0000d3ac},
11807 + {0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0,
11808 + 0x0000d3b0},
11809 + {0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380,
11810 + 0x0000f380},
11811 + {0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384,
11812 + 0x0000f384},
11813 + {0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388,
11814 + 0x0000f388},
11815 + {0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710,
11816 + 0x0000f710},
11817 + {0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714,
11818 + 0x0000f714},
11819 + {0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718,
11820 + 0x0000f718},
11821 + {0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10,
11822 + 0x0000fb10},
11823 + {0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14,
11824 + 0x0000fb14},
11825 + {0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18,
11826 + 0x0000fb18},
11827 + {0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c,
11828 + 0x0000fb8c},
11829 + {0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90,
11830 + 0x0000fb90},
11831 + {0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94,
11832 + 0x0000fb94},
11833 + {0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c,
11834 + 0x0000ff8c},
11835 + {0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90,
11836 + 0x0000ff90},
11837 + {0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94,
11838 + 0x0000ff94},
11839 + {0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0,
11840 + 0x0000ffa0},
11841 + {0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4,
11842 + 0x0000ffa4},
11843 + {0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8,
11844 + 0x0000ffa8},
11845 + {0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac,
11846 + 0x0000ffac},
11847 + {0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0,
11848 + 0x0000ffb0},
11849 + {0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4,
11850 + 0x0000ffb4},
11851 + {0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1,
11852 + 0x0000ffa1},
11853 + {0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5,
11854 + 0x0000ffa5},
11855 + {0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9,
11856 + 0x0000ffa9},
11857 + {0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad,
11858 + 0x0000ffad},
11859 + {0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1,
11860 + 0x0000ffb1},
11861 + {0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5,
11862 + 0x0000ffb5},
11863 + {0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9,
11864 + 0x0000ffb9},
11865 + {0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5,
11866 + 0x0000ffc5},
11867 + {0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9,
11868 + 0x0000ffc9},
11869 + {0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd,
11870 + 0x0000ffcd},
11871 + {0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1,
11872 + 0x0000ffd1},
11873 + {0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5,
11874 + 0x0000ffd5},
11875 + {0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2,
11876 + 0x0000ffc2},
11877 + {0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6,
11878 + 0x0000ffc6},
11879 + {0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca,
11880 + 0x0000ffca},
11881 + {0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce,
11882 + 0x0000ffce},
11883 + {0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2,
11884 + 0x0000ffd2},
11885 + {0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6,
11886 + 0x0000ffd6},
11887 + {0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda,
11888 + 0x0000ffda},
11889 + {0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7,
11890 + 0x0000ffc7},
11891 + {0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb,
11892 + 0x0000ffcb},
11893 + {0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf,
11894 + 0x0000ffcf},
11895 + {0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3,
11896 + 0x0000ffd3},
11897 + {0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7,
11898 + 0x0000ffd7},
11899 + {0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11900 + 0x0000ffdb},
11901 + {0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11902 + 0x0000ffdb},
11903 + {0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11904 + 0x0000ffdb},
11905 + {0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11906 + 0x0000ffdb},
11907 + {0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11908 + 0x0000ffdb},
11909 + {0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11910 + 0x0000ffdb},
11911 + {0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11912 + 0x0000ffdb},
11913 + {0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11914 + 0x0000ffdb},
11915 + {0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11916 + 0x0000ffdb},
11917 + {0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11918 + 0x0000ffdb},
11919 + {0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11920 + 0x0000ffdb},
11921 + {0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11922 + 0x0000ffdb},
11923 + {0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11924 + 0x0000ffdb},
11925 + {0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11926 + 0x0000ffdb},
11927 + {0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11928 + 0x0000ffdb},
11929 + {0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11930 + 0x0000ffdb},
11931 + {0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11932 + 0x0000ffdb},
11933 + {0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11934 + 0x0000ffdb},
11935 + {0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11936 + 0x0000ffdb},
11937 + {0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11938 + 0x0000ffdb},
11939 + {0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11940 + 0x0000ffdb},
11941 + {0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11942 + 0x0000ffdb},
11943 + {0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11944 + 0x0000ffdb},
11945 + {0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11946 + 0x0000ffdb},
11947 + {0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11948 + 0x0000ffdb},
11949 + {0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067,
11950 + 0x00001067},
11951 + {0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067,
11952 + 0x00001067},
11953 +};
11954 +
11955 +static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
11956 + {0x00004040, 0x9248fd00},
11957 + {0x00004040, 0x24924924},
11958 + {0x00004040, 0xa8000019},
11959 + {0x00004040, 0x13160820},
11960 + {0x00004040, 0xe5980560},
11961 + {0x00004040, 0xc01dcffd},
11962 + {0x00004040, 0x1aaabe41},
11963 + {0x00004040, 0xbe105554},
11964 + {0x00004040, 0x00043007},
11965 + {0x00004044, 0x00000000},
11966 +};
11967 +
11968 +static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
11969 + {0x00004040, 0x9248fd00},
11970 + {0x00004040, 0x24924924},
11971 + {0x00004040, 0xa8000019},
11972 + {0x00004040, 0x13160820},
11973 + {0x00004040, 0xe5980560},
11974 + {0x00004040, 0xc01dcffc},
11975 + {0x00004040, 0x1aaabe41},
11976 + {0x00004040, 0xbe105554},
11977 + {0x00004040, 0x00043007},
11978 + {0x00004044, 0x00000000},
11979 +};
11980 +
11981 +/* AR9271 initialization values automaticaly created: 06/04/09 */
11982 +static const u_int32_t ar9271Modes_9271[][6] = {
11983 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
11984 + 0x000001e0},
11985 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
11986 + 0x000001e0},
11987 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
11988 + 0x00001180},
11989 + {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
11990 + 0x00000008},
11991 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00,
11992 + 0x06e006e0},
11993 + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b,
11994 + 0x0988004f},
11995 + {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440,
11996 + 0x00006880},
11997 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
11998 + 0x00000303},
11999 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
12000 + 0x02020200},
12001 + {0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e,
12002 + 0x01000e0e},
12003 + {0x00009828, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001,
12004 + 0x3a020001},
12005 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
12006 + 0x00000e0e},
12007 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
12008 + 0x00000007},
12009 + {0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e,
12010 + 0x206a012e},
12011 + {0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620,
12012 + 0x037216a0},
12013 + {0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053,
12014 + 0x00001059},
12015 + {0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053,
12016 + 0x00001059},
12017 + {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2,
12018 + 0x6d4000e2},
12019 + {0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e,
12020 + 0x7ec84d2e},
12021 + {0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e,
12022 + 0x3139605e},
12023 + {0x00009860, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18,
12024 + 0x00058d18},
12025 + {0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00,
12026 + 0x0001ce00},
12027 + {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0,
12028 + 0x5ac640d0},
12029 + {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881,
12030 + 0x06903881},
12031 + {0x00009910, 0x30002310, 0x30002310, 0x30002310, 0x30002310,
12032 + 0x30002310},
12033 + {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898,
12034 + 0x000007d0},
12035 + {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b,
12036 + 0x00000016},
12037 + {0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d,
12038 + 0xd00a800d},
12039 + {0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020,
12040 + 0xffbc1010},
12041 + {0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
12042 + 0x00000000},
12043 + {0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
12044 + 0x00000000},
12045 + {0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c,
12046 + 0x0000421c},
12047 + {0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00,
12048 + 0x00000c00},
12049 + {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4,
12050 + 0x05eea6d4},
12051 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
12052 + 0x06336f77},
12053 + {0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f,
12054 + 0x6af6532f},
12055 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
12056 + 0x08f186c8},
12057 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
12058 + 0x00046384},
12059 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
12060 + 0x00000000},
12061 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
12062 + 0x00000000},
12063 + {0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084,
12064 + 0x00000000},
12065 + {0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088,
12066 + 0x00000000},
12067 + {0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c,
12068 + 0x00000000},
12069 + {0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100,
12070 + 0x00000000},
12071 + {0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104,
12072 + 0x00000000},
12073 + {0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108,
12074 + 0x00000000},
12075 + {0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c,
12076 + 0x00000000},
12077 + {0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110,
12078 + 0x00000000},
12079 + {0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114,
12080 + 0x00000000},
12081 + {0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180,
12082 + 0x00000000},
12083 + {0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184,
12084 + 0x00000000},
12085 + {0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188,
12086 + 0x00000000},
12087 + {0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c,
12088 + 0x00000000},
12089 + {0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190,
12090 + 0x00000000},
12091 + {0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194,
12092 + 0x00000000},
12093 + {0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0,
12094 + 0x00000000},
12095 + {0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c,
12096 + 0x00000000},
12097 + {0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8,
12098 + 0x00000000},
12099 + {0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284,
12100 + 0x00000000},
12101 + {0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288,
12102 + 0x00000000},
12103 + {0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224,
12104 + 0x00000000},
12105 + {0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290,
12106 + 0x00000000},
12107 + {0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300,
12108 + 0x00000000},
12109 + {0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304,
12110 + 0x00000000},
12111 + {0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308,
12112 + 0x00000000},
12113 + {0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c,
12114 + 0x00000000},
12115 + {0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380,
12116 + 0x00000000},
12117 + {0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384,
12118 + 0x00000000},
12119 + {0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700,
12120 + 0x00000000},
12121 + {0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704,
12122 + 0x00000000},
12123 + {0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708,
12124 + 0x00000000},
12125 + {0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c,
12126 + 0x00000000},
12127 + {0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780,
12128 + 0x00000000},
12129 + {0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784,
12130 + 0x00000000},
12131 + {0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00,
12132 + 0x00000000},
12133 + {0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04,
12134 + 0x00000000},
12135 + {0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08,
12136 + 0x00000000},
12137 + {0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c,
12138 + 0x00000000},
12139 + {0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80,
12140 + 0x00000000},
12141 + {0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84,
12142 + 0x00000000},
12143 + {0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88,
12144 + 0x00000000},
12145 + {0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c,
12146 + 0x00000000},
12147 + {0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90,
12148 + 0x00000000},
12149 + {0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80,
12150 + 0x00000000},
12151 + {0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84,
12152 + 0x00000000},
12153 + {0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88,
12154 + 0x00000000},
12155 + {0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c,
12156 + 0x00000000},
12157 + {0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90,
12158 + 0x00000000},
12159 + {0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c,
12160 + 0x00000000},
12161 + {0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310,
12162 + 0x00000000},
12163 + {0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384,
12164 + 0x00000000},
12165 + {0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388,
12166 + 0x00000000},
12167 + {0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324,
12168 + 0x00000000},
12169 + {0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704,
12170 + 0x00000000},
12171 + {0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4,
12172 + 0x00000000},
12173 + {0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8,
12174 + 0x00000000},
12175 + {0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710,
12176 + 0x00000000},
12177 + {0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714,
12178 + 0x00000000},
12179 + {0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720,
12180 + 0x00000000},
12181 + {0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724,
12182 + 0x00000000},
12183 + {0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728,
12184 + 0x00000000},
12185 + {0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c,
12186 + 0x00000000},
12187 + {0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0,
12188 + 0x00000000},
12189 + {0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4,
12190 + 0x00000000},
12191 + {0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8,
12192 + 0x00000000},
12193 + {0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0,
12194 + 0x00000000},
12195 + {0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4,
12196 + 0x00000000},
12197 + {0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8,
12198 + 0x00000000},
12199 + {0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5,
12200 + 0x00000000},
12201 + {0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9,
12202 + 0x00000000},
12203 + {0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad,
12204 + 0x00000000},
12205 + {0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1,
12206 + 0x00000000},
12207 + {0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5,
12208 + 0x00000000},
12209 + {0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9,
12210 + 0x00000000},
12211 + {0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5,
12212 + 0x00000000},
12213 + {0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9,
12214 + 0x00000000},
12215 + {0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1,
12216 + 0x00000000},
12217 + {0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5,
12218 + 0x00000000},
12219 + {0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9,
12220 + 0x00000000},
12221 + {0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6,
12222 + 0x00000000},
12223 + {0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca,
12224 + 0x00000000},
12225 + {0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce,
12226 + 0x00000000},
12227 + {0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2,
12228 + 0x00000000},
12229 + {0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6,
12230 + 0x00000000},
12231 + {0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3,
12232 + 0x00000000},
12233 + {0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7,
12234 + 0x00000000},
12235 + {0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb,
12236 + 0x00000000},
12237 + {0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf,
12238 + 0x00000000},
12239 + {0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7,
12240 + 0x00000000},
12241 + {0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12242 + 0x00000000},
12243 + {0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12244 + 0x00000000},
12245 + {0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12246 + 0x00000000},
12247 + {0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12248 + 0x00000000},
12249 + {0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12250 + 0x00000000},
12251 + {0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12252 + 0x00000000},
12253 + {0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12254 + 0x00000000},
12255 + {0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12256 + 0x00000000},
12257 + {0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12258 + 0x00000000},
12259 + {0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12260 + 0x00000000},
12261 + {0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12262 + 0x00000000},
12263 + {0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12264 + 0x00000000},
12265 + {0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12266 + 0x00000000},
12267 + {0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12268 + 0x00000000},
12269 + {0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12270 + 0x00000000},
12271 + {0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12272 + 0x00000000},
12273 + {0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12274 + 0x00000000},
12275 + {0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12276 + 0x00000000},
12277 + {0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12278 + 0x00000000},
12279 + {0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12280 + 0x00000000},
12281 + {0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12282 + 0x00000000},
12283 + {0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12284 + 0x00000000},
12285 + {0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12286 + 0x00000000},
12287 + {0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12288 + 0x00000000},
12289 + {0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12290 + 0x00000000},
12291 + {0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12292 + 0x00000000},
12293 + {0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12294 + 0x00000000},
12295 + {0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12296 + 0x00000000},
12297 + {0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12298 + 0x00000000},
12299 + {0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12300 + 0x00000000},
12301 + {0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12302 + 0x00000000},
12303 + {0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12304 + 0x00000000},
12305 + {0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12306 + 0x00000000},
12307 + {0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12308 + 0x00000000},
12309 + {0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12310 + 0x00000000},
12311 + {0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12312 + 0x00000000},
12313 + {0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12314 + 0x00000000},
12315 + {0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12316 + 0x00000000},
12317 + {0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12318 + 0x00000000},
12319 + {0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084,
12320 + 0x00000000},
12321 + {0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088,
12322 + 0x00000000},
12323 + {0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c,
12324 + 0x00000000},
12325 + {0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100,
12326 + 0x00000000},
12327 + {0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104,
12328 + 0x00000000},
12329 + {0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108,
12330 + 0x00000000},
12331 + {0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c,
12332 + 0x00000000},
12333 + {0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110,
12334 + 0x00000000},
12335 + {0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114,
12336 + 0x00000000},
12337 + {0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180,
12338 + 0x00000000},
12339 + {0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184,
12340 + 0x00000000},
12341 + {0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188,
12342 + 0x00000000},
12343 + {0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c,
12344 + 0x00000000},
12345 + {0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190,
12346 + 0x00000000},
12347 + {0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194,
12348 + 0x00000000},
12349 + {0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0,
12350 + 0x00000000},
12351 + {0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c,
12352 + 0x00000000},
12353 + {0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8,
12354 + 0x00000000},
12355 + {0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284,
12356 + 0x00000000},
12357 + {0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288,
12358 + 0x00000000},
12359 + {0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224,
12360 + 0x00000000},
12361 + {0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290,
12362 + 0x00000000},
12363 + {0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300,
12364 + 0x00000000},
12365 + {0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304,
12366 + 0x00000000},
12367 + {0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308,
12368 + 0x00000000},
12369 + {0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c,
12370 + 0x00000000},
12371 + {0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380,
12372 + 0x00000000},
12373 + {0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384,
12374 + 0x00000000},
12375 + {0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700,
12376 + 0x00000000},
12377 + {0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704,
12378 + 0x00000000},
12379 + {0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708,
12380 + 0x00000000},
12381 + {0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c,
12382 + 0x00000000},
12383 + {0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780,
12384 + 0x00000000},
12385 + {0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784,
12386 + 0x00000000},
12387 + {0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00,
12388 + 0x00000000},
12389 + {0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04,
12390 + 0x00000000},
12391 + {0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08,
12392 + 0x00000000},
12393 + {0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c,
12394 + 0x00000000},
12395 + {0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80,
12396 + 0x00000000},
12397 + {0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84,
12398 + 0x00000000},
12399 + {0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88,
12400 + 0x00000000},
12401 + {0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c,
12402 + 0x00000000},
12403 + {0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90,
12404 + 0x00000000},
12405 + {0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80,
12406 + 0x00000000},
12407 + {0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84,
12408 + 0x00000000},
12409 + {0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88,
12410 + 0x00000000},
12411 + {0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c,
12412 + 0x00000000},
12413 + {0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90,
12414 + 0x00000000},
12415 + {0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c,
12416 + 0x00000000},
12417 + {0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310,
12418 + 0x00000000},
12419 + {0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384,
12420 + 0x00000000},
12421 + {0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388,
12422 + 0x00000000},
12423 + {0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324,
12424 + 0x00000000},
12425 + {0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704,
12426 + 0x00000000},
12427 + {0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4,
12428 + 0x00000000},
12429 + {0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8,
12430 + 0x00000000},
12431 + {0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710,
12432 + 0x00000000},
12433 + {0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714,
12434 + 0x00000000},
12435 + {0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720,
12436 + 0x00000000},
12437 + {0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724,
12438 + 0x00000000},
12439 + {0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728,
12440 + 0x00000000},
12441 + {0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c,
12442 + 0x00000000},
12443 + {0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0,
12444 + 0x00000000},
12445 + {0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4,
12446 + 0x00000000},
12447 + {0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8,
12448 + 0x00000000},
12449 + {0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0,
12450 + 0x00000000},
12451 + {0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4,
12452 + 0x00000000},
12453 + {0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8,
12454 + 0x00000000},
12455 + {0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5,
12456 + 0x00000000},
12457 + {0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9,
12458 + 0x00000000},
12459 + {0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad,
12460 + 0x00000000},
12461 + {0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1,
12462 + 0x00000000},
12463 + {0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5,
12464 + 0x00000000},
12465 + {0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9,
12466 + 0x00000000},
12467 + {0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5,
12468 + 0x00000000},
12469 + {0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9,
12470 + 0x00000000},
12471 + {0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1,
12472 + 0x00000000},
12473 + {0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5,
12474 + 0x00000000},
12475 + {0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9,
12476 + 0x00000000},
12477 + {0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6,
12478 + 0x00000000},
12479 + {0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca,
12480 + 0x00000000},
12481 + {0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce,
12482 + 0x00000000},
12483 + {0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2,
12484 + 0x00000000},
12485 + {0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6,
12486 + 0x00000000},
12487 + {0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3,
12488 + 0x00000000},
12489 + {0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7,
12490 + 0x00000000},
12491 + {0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb,
12492 + 0x00000000},
12493 + {0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf,
12494 + 0x00000000},
12495 + {0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7,
12496 + 0x00000000},
12497 + {0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12498 + 0x00000000},
12499 + {0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12500 + 0x00000000},
12501 + {0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12502 + 0x00000000},
12503 + {0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12504 + 0x00000000},
12505 + {0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12506 + 0x00000000},
12507 + {0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12508 + 0x00000000},
12509 + {0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12510 + 0x00000000},
12511 + {0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12512 + 0x00000000},
12513 + {0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12514 + 0x00000000},
12515 + {0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12516 + 0x00000000},
12517 + {0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12518 + 0x00000000},
12519 + {0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12520 + 0x00000000},
12521 + {0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12522 + 0x00000000},
12523 + {0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12524 + 0x00000000},
12525 + {0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12526 + 0x00000000},
12527 + {0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12528 + 0x00000000},
12529 + {0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12530 + 0x00000000},
12531 + {0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12532 + 0x00000000},
12533 + {0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12534 + 0x00000000},
12535 + {0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12536 + 0x00000000},
12537 + {0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12538 + 0x00000000},
12539 + {0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12540 + 0x00000000},
12541 + {0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12542 + 0x00000000},
12543 + {0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12544 + 0x00000000},
12545 + {0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12546 + 0x00000000},
12547 + {0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12548 + 0x00000000},
12549 + {0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12550 + 0x00000000},
12551 + {0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12552 + 0x00000000},
12553 + {0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12554 + 0x00000000},
12555 + {0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12556 + 0x00000000},
12557 + {0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12558 + 0x00000000},
12559 + {0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12560 + 0x00000000},
12561 + {0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12562 + 0x00000000},
12563 + {0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12564 + 0x00000000},
12565 + {0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12566 + 0x00000000},
12567 + {0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12568 + 0x00000000},
12569 + {0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12570 + 0x00000000},
12571 + {0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12572 + 0x00000000},
12573 + {0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12574 + 0x00000000},
12575 + {0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004,
12576 + 0x00000004},
12577 + {0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000,
12578 + 0x0001f000},
12579 + {0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000,
12580 + 0x0001f000},
12581 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
12582 + 0x1883800a},
12583 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
12584 + 0x00000000},
12585 + {0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000,
12586 + 0x0004a000},
12587 + {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e,
12588 + 0x7999aa0e},
12589 +};
12590 +
12591 +static const u_int32_t ar9271Common_9271[][2] = {
12592 + {0x0000000c, 0x00000000},
12593 + {0x00000030, 0x00020045},
12594 + {0x00000034, 0x00000005},
12595 + {0x00000040, 0x00000000},
12596 + {0x00000044, 0x00000008},
12597 + {0x00000048, 0x00000008},
12598 + {0x0000004c, 0x00000010},
12599 + {0x00000050, 0x00000000},
12600 + {0x00000054, 0x0000001f},
12601 + {0x00000800, 0x00000000},
12602 + {0x00000804, 0x00000000},
12603 + {0x00000808, 0x00000000},
12604 + {0x0000080c, 0x00000000},
12605 + {0x00000810, 0x00000000},
12606 + {0x00000814, 0x00000000},
12607 + {0x00000818, 0x00000000},
12608 + {0x0000081c, 0x00000000},
12609 + {0x00000820, 0x00000000},
12610 + {0x00000824, 0x00000000},
12611 + {0x00001040, 0x002ffc0f},
12612 + {0x00001044, 0x002ffc0f},
12613 + {0x00001048, 0x002ffc0f},
12614 + {0x0000104c, 0x002ffc0f},
12615 + {0x00001050, 0x002ffc0f},
12616 + {0x00001054, 0x002ffc0f},
12617 + {0x00001058, 0x002ffc0f},
12618 + {0x0000105c, 0x002ffc0f},
12619 + {0x00001060, 0x002ffc0f},
12620 + {0x00001064, 0x002ffc0f},
12621 + {0x00001230, 0x00000000},
12622 + {0x00001270, 0x00000000},
12623 + {0x00001038, 0x00000000},
12624 + {0x00001078, 0x00000000},
12625 + {0x000010b8, 0x00000000},
12626 + {0x000010f8, 0x00000000},
12627 + {0x00001138, 0x00000000},
12628 + {0x00001178, 0x00000000},
12629 + {0x000011b8, 0x00000000},
12630 + {0x000011f8, 0x00000000},
12631 + {0x00001238, 0x00000000},
12632 + {0x00001278, 0x00000000},
12633 + {0x000012b8, 0x00000000},
12634 + {0x000012f8, 0x00000000},
12635 + {0x00001338, 0x00000000},
12636 + {0x00001378, 0x00000000},
12637 + {0x000013b8, 0x00000000},
12638 + {0x000013f8, 0x00000000},
12639 + {0x00001438, 0x00000000},
12640 + {0x00001478, 0x00000000},
12641 + {0x000014b8, 0x00000000},
12642 + {0x000014f8, 0x00000000},
12643 + {0x00001538, 0x00000000},
12644 + {0x00001578, 0x00000000},
12645 + {0x000015b8, 0x00000000},
12646 + {0x000015f8, 0x00000000},
12647 + {0x00001638, 0x00000000},
12648 + {0x00001678, 0x00000000},
12649 + {0x000016b8, 0x00000000},
12650 + {0x000016f8, 0x00000000},
12651 + {0x00001738, 0x00000000},
12652 + {0x00001778, 0x00000000},
12653 + {0x000017b8, 0x00000000},
12654 + {0x000017f8, 0x00000000},
12655 + {0x0000103c, 0x00000000},
12656 + {0x0000107c, 0x00000000},
12657 + {0x000010bc, 0x00000000},
12658 + {0x000010fc, 0x00000000},
12659 + {0x0000113c, 0x00000000},
12660 + {0x0000117c, 0x00000000},
12661 + {0x000011bc, 0x00000000},
12662 + {0x000011fc, 0x00000000},
12663 + {0x0000123c, 0x00000000},
12664 + {0x0000127c, 0x00000000},
12665 + {0x000012bc, 0x00000000},
12666 + {0x000012fc, 0x00000000},
12667 + {0x0000133c, 0x00000000},
12668 + {0x0000137c, 0x00000000},
12669 + {0x000013bc, 0x00000000},
12670 + {0x000013fc, 0x00000000},
12671 + {0x0000143c, 0x00000000},
12672 + {0x0000147c, 0x00000000},
12673 + {0x00004030, 0x00000002},
12674 + {0x0000403c, 0x00000002},
12675 + {0x00004024, 0x0000001f},
12676 + {0x00004060, 0x00000000},
12677 + {0x00004064, 0x00000000},
12678 + {0x00008004, 0x00000000},
12679 + {0x00008008, 0x00000000},
12680 + {0x0000800c, 0x00000000},
12681 + {0x00008018, 0x00000700},
12682 + {0x00008020, 0x00000000},
12683 + {0x00008038, 0x00000000},
12684 + {0x0000803c, 0x00000000},
12685 + {0x00008048, 0x00000000},
12686 + {0x00008054, 0x00000000},
12687 + {0x00008058, 0x00000000},
12688 + {0x0000805c, 0x000fc78f},
12689 + {0x00008060, 0x0000000f},
12690 + {0x00008064, 0x00000000},
12691 + {0x00008070, 0x00000000},
12692 + {0x000080b0, 0x00000000},
12693 + {0x000080b4, 0x00000000},
12694 + {0x000080b8, 0x00000000},
12695 + {0x000080bc, 0x00000000},
12696 + {0x000080c0, 0x2a80001a},
12697 + {0x000080c4, 0x05dc01e0},
12698 + {0x000080c8, 0x1f402710},
12699 + {0x000080cc, 0x01f40000},
12700 + {0x000080d0, 0x00001e00},
12701 + {0x000080d4, 0x00000000},
12702 + {0x000080d8, 0x00400000},
12703 + {0x000080e0, 0xffffffff},
12704 + {0x000080e4, 0x0000ffff},
12705 + {0x000080e8, 0x003f3f3f},
12706 + {0x000080ec, 0x00000000},
12707 + {0x000080f0, 0x00000000},
12708 + {0x000080f4, 0x00000000},
12709 + {0x000080f8, 0x00000000},
12710 + {0x000080fc, 0x00020000},
12711 + {0x00008100, 0x00020000},
12712 + {0x00008104, 0x00000001},
12713 + {0x00008108, 0x00000052},
12714 + {0x0000810c, 0x00000000},
12715 + {0x00008110, 0x00000168},
12716 + {0x00008118, 0x000100aa},
12717 + {0x0000811c, 0x00003210},
12718 + {0x00008120, 0x08f04810},
12719 + {0x00008124, 0x00000000},
12720 + {0x00008128, 0x00000000},
12721 + {0x0000812c, 0x00000000},
12722 + {0x00008130, 0x00000000},
12723 + {0x00008134, 0x00000000},
12724 + {0x00008138, 0x00000000},
12725 + {0x0000813c, 0x00000000},
12726 + {0x00008144, 0xffffffff},
12727 + {0x00008168, 0x00000000},
12728 + {0x0000816c, 0x00000000},
12729 + {0x00008170, 0x32143320},
12730 + {0x00008174, 0xfaa4fa50},
12731 + {0x00008178, 0x00000100},
12732 + {0x0000817c, 0x00000000},
12733 + {0x000081c0, 0x00000000},
12734 + {0x000081d0, 0x0000320a},
12735 + {0x000081ec, 0x00000000},
12736 + {0x000081f0, 0x00000000},
12737 + {0x000081f4, 0x00000000},
12738 + {0x000081f8, 0x00000000},
12739 + {0x000081fc, 0x00000000},
12740 + {0x00008200, 0x00000000},
12741 + {0x00008204, 0x00000000},
12742 + {0x00008208, 0x00000000},
12743 + {0x0000820c, 0x00000000},
12744 + {0x00008210, 0x00000000},
12745 + {0x00008214, 0x00000000},
12746 + {0x00008218, 0x00000000},
12747 + {0x0000821c, 0x00000000},
12748 + {0x00008220, 0x00000000},
12749 + {0x00008224, 0x00000000},
12750 + {0x00008228, 0x00000000},
12751 + {0x0000822c, 0x00000000},
12752 + {0x00008230, 0x00000000},
12753 + {0x00008234, 0x00000000},
12754 + {0x00008238, 0x00000000},
12755 + {0x0000823c, 0x00000000},
12756 + {0x00008240, 0x00100000},
12757 + {0x00008244, 0x0010f400},
12758 + {0x00008248, 0x00000100},
12759 + {0x0000824c, 0x0001e800},
12760 + {0x00008250, 0x00000000},
12761 + {0x00008254, 0x00000000},
12762 + {0x00008258, 0x00000000},
12763 + {0x0000825c, 0x400000ff},
12764 + {0x00008260, 0x00080922},
12765 + {0x00008264, 0xa8a00010},
12766 + {0x00008270, 0x00000000},
12767 + {0x00008274, 0x40000000},
12768 + {0x00008278, 0x003e4180},
12769 + {0x0000827c, 0x00000000},
12770 + {0x00008284, 0x0000002c},
12771 + {0x00008288, 0x0000002c},
12772 + {0x0000828c, 0x00000000},
12773 + {0x00008294, 0x00000000},
12774 + {0x00008298, 0x00000000},
12775 + {0x0000829c, 0x00000000},
12776 + {0x00008300, 0x00000040},
12777 + {0x00008314, 0x00000000},
12778 + {0x00008328, 0x00000000},
12779 + {0x0000832c, 0x00000001},
12780 + {0x00008330, 0x00000302},
12781 + {0x00008334, 0x00000e00},
12782 + {0x00008338, 0x00ff0000},
12783 + {0x0000833c, 0x00000000},
12784 + {0x00008340, 0x00010380},
12785 + {0x00008344, 0x00581043},
12786 + {0x00007010, 0x00000030},
12787 + {0x00007034, 0x00000002},
12788 + {0x00007038, 0x000004c2},
12789 + {0x00007800, 0x00140000},
12790 + {0x00007804, 0x0e4548d8},
12791 + {0x00007808, 0x54214514},
12792 + {0x0000780c, 0x02025820},
12793 + {0x00007810, 0x71c0d388},
12794 + {0x00007814, 0x924934a8},
12795 + {0x0000781c, 0x00000000},
12796 + {0x00007828, 0x66964300},
12797 + {0x0000782c, 0x8db6d961},
12798 + {0x00007830, 0x8db6d96c},
12799 + {0x00007834, 0x6140008b},
12800 + {0x0000783c, 0x72ee0a72},
12801 + {0x00007840, 0xbbfffffc},
12802 + {0x00007844, 0x000c0db6},
12803 + {0x00007848, 0x6db61b6f},
12804 + {0x0000784c, 0x6d9b66db},
12805 + {0x00007850, 0x6d8c6dba},
12806 + {0x00007854, 0x00040000},
12807 + {0x00007858, 0xdb003012},
12808 + {0x0000785c, 0x04924914},
12809 + {0x00007860, 0x21084210},
12810 + {0x00007864, 0xf7d7ffde},
12811 + {0x00007868, 0xc2034080},
12812 + {0x00007870, 0x10142c00},
12813 + {0x00009808, 0x00000000},
12814 + {0x0000980c, 0xafe68e30},
12815 + {0x00009810, 0xfd14e000},
12816 + {0x00009814, 0x9c0a9f6b},
12817 + {0x0000981c, 0x00000000},
12818 + {0x0000982c, 0x0000a000},
12819 + {0x00009830, 0x00000000},
12820 + {0x0000983c, 0x00200400},
12821 + {0x0000984c, 0x0040233c},
12822 + {0x00009854, 0x00000044},
12823 + {0x00009900, 0x00000000},
12824 + {0x00009904, 0x00000000},
12825 + {0x00009908, 0x00000000},
12826 + {0x0000990c, 0x00000000},
12827 + {0x0000991c, 0x10000fff},
12828 + {0x00009920, 0x04900000},
12829 + {0x00009928, 0x00000001},
12830 + {0x0000992c, 0x00000004},
12831 + {0x00009934, 0x1e1f2022},
12832 + {0x00009938, 0x0a0b0c0d},
12833 + {0x0000993c, 0x00000000},
12834 + {0x00009940, 0x14750604},
12835 + {0x00009948, 0x9280c00a},
12836 + {0x0000994c, 0x00020028},
12837 + {0x00009954, 0x5f3ca3de},
12838 + {0x00009958, 0x0108ecff},
12839 + {0x00009968, 0x000003ce},
12840 + {0x00009970, 0x192bb514},
12841 + {0x00009974, 0x00000000},
12842 + {0x00009978, 0x00000001},
12843 + {0x0000997c, 0x00000000},
12844 + {0x00009980, 0x00000000},
12845 + {0x00009984, 0x00000000},
12846 + {0x00009988, 0x00000000},
12847 + {0x0000998c, 0x00000000},
12848 + {0x00009990, 0x00000000},
12849 + {0x00009994, 0x00000000},
12850 + {0x00009998, 0x00000000},
12851 + {0x0000999c, 0x00000000},
12852 + {0x000099a0, 0x00000000},
12853 + {0x000099a4, 0x00000001},
12854 + {0x000099a8, 0x201fff00},
12855 + {0x000099ac, 0x2def0400},
12856 + {0x000099b0, 0x03051000},
12857 + {0x000099b4, 0x00000820},
12858 + {0x000099dc, 0x00000000},
12859 + {0x000099e0, 0x00000000},
12860 + {0x000099e4, 0xaaaaaaaa},
12861 + {0x000099e8, 0x3c466478},
12862 + {0x000099ec, 0x0cc80caa},
12863 + {0x000099f0, 0x00000000},
12864 + {0x0000a208, 0x803e68c8},
12865 + {0x0000a210, 0x4080a333},
12866 + {0x0000a214, 0x00206c10},
12867 + {0x0000a218, 0x009c4060},
12868 + {0x0000a220, 0x01834061},
12869 + {0x0000a224, 0x00000400},
12870 + {0x0000a228, 0x000003b5},
12871 + {0x0000a22c, 0x00000000},
12872 + {0x0000a234, 0x20202020},
12873 + {0x0000a238, 0x20202020},
12874 + {0x0000a244, 0x00000000},
12875 + {0x0000a248, 0xfffffffc},
12876 + {0x0000a24c, 0x00000000},
12877 + {0x0000a254, 0x00000000},
12878 + {0x0000a258, 0x0ccb5380},
12879 + {0x0000a25c, 0x15151501},
12880 + {0x0000a260, 0xdfa90f01},
12881 + {0x0000a268, 0x00000000},
12882 + {0x0000a26c, 0x0ebae9e6},
12883 + {0x0000a388, 0x0c000000},
12884 + {0x0000a38c, 0x20202020},
12885 + {0x0000a390, 0x20202020},
12886 + {0x0000a39c, 0x00000001},
12887 + {0x0000a3a0, 0x00000000},
12888 + {0x0000a3a4, 0x00000000},
12889 + {0x0000a3a8, 0x00000000},
12890 + {0x0000a3ac, 0x00000000},
12891 + {0x0000a3b0, 0x00000000},
12892 + {0x0000a3b4, 0x00000000},
12893 + {0x0000a3b8, 0x00000000},
12894 + {0x0000a3bc, 0x00000000},
12895 + {0x0000a3c0, 0x00000000},
12896 + {0x0000a3c4, 0x00000000},
12897 + {0x0000a3cc, 0x20202020},
12898 + {0x0000a3d0, 0x20202020},
12899 + {0x0000a3d4, 0x20202020},
12900 + {0x0000a3e4, 0x00000000},
12901 + {0x0000a3e8, 0x18c43433},
12902 + {0x0000a3ec, 0x00f70081},
12903 + {0x0000a3f0, 0x01036a2f},
12904 + {0x0000a3f4, 0x00000000},
12905 + {0x0000d270, 0x0d820820},
12906 + {0x0000d35c, 0x07ffffef},
12907 + {0x0000d360, 0x0fffffe7},
12908 + {0x0000d364, 0x17ffffe5},
12909 + {0x0000d368, 0x1fffffe4},
12910 + {0x0000d36c, 0x37ffffe3},
12911 + {0x0000d370, 0x3fffffe3},
12912 + {0x0000d374, 0x57ffffe3},
12913 + {0x0000d378, 0x5fffffe2},
12914 + {0x0000d37c, 0x7fffffe2},
12915 + {0x0000d380, 0x7f3c7bba},
12916 + {0x0000d384, 0xf3307ff0},
12917 +};
12918 +
12919 +static const u_int32_t ar9271Common_normal_cck_fir_coeff_9271[][2] = {
12920 + {0x0000a1f4, 0x00fffeff},
12921 + {0x0000a1f8, 0x00f5f9ff},
12922 + {0x0000a1fc, 0xb79f6427},
12923 +};
12924 +
12925 +static const u_int32_t ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = {
12926 + {0x0000a1f4, 0x00000000},
12927 + {0x0000a1f8, 0xefff0301},
12928 + {0x0000a1fc, 0xca9228ee},
12929 +};
12930 +
12931 +static const u_int32_t ar9271Modes_9271_1_0_only[][6] = {
12932 + {0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311,
12933 + 0x30002311},
12934 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
12935 + 0x0a020001},
12936 +};
12937 +
12938 +static const u_int32_t ar9271Modes_9271_ANI_reg[][6] = {
12939 + {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2,
12940 + 0x6d4000e2},
12941 + {0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e,
12942 + 0x3139605e},
12943 + {0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e,
12944 + 0x7ec84d2e},
12945 + {0x0000986c, 0x06903881, 0x06903881, 0x06903881, 0x06903881,
12946 + 0x06903881},
12947 + {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0,
12948 + 0x5ac640d0},
12949 + {0x0000a208, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8,
12950 + 0x803e68c8},
12951 + {0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d,
12952 + 0xd00a800d},
12953 + {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4,
12954 + 0x05eea6d4},
12955 +};
12956 +
12957 +static const u_int32_t ar9271Modes_normal_power_tx_gain_9271[][6] = {
12958 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
12959 + 0x00000000},
12960 + {0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200,
12961 + 0x00000000},
12962 + {0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208,
12963 + 0x00000000},
12964 + {0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608,
12965 + 0x00000000},
12966 + {0x0000a310, 0x00000000, 0x00000000, 0x0001e610, 0x0001e610,
12967 + 0x00000000},
12968 + {0x0000a314, 0x00000000, 0x00000000, 0x0002d6d0, 0x0002d6d0,
12969 + 0x00000000},
12970 + {0x0000a318, 0x00000000, 0x00000000, 0x00039758, 0x00039758,
12971 + 0x00000000},
12972 + {0x0000a31c, 0x00000000, 0x00000000, 0x0003b759, 0x0003b759,
12973 + 0x00000000},
12974 + {0x0000a320, 0x00000000, 0x00000000, 0x0003d75a, 0x0003d75a,
12975 + 0x00000000},
12976 + {0x0000a324, 0x00000000, 0x00000000, 0x0004175c, 0x0004175c,
12977 + 0x00000000},
12978 + {0x0000a328, 0x00000000, 0x00000000, 0x0004575e, 0x0004575e,
12979 + 0x00000000},
12980 + {0x0000a32c, 0x00000000, 0x00000000, 0x0004979f, 0x0004979f,
12981 + 0x00000000},
12982 + {0x0000a330, 0x00000000, 0x00000000, 0x0004d7df, 0x0004d7df,
12983 + 0x00000000},
12984 + {0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de,
12985 + 0x00000000},
12986 + {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e,
12987 + 0x00000000},
12988 + {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e,
12989 + 0x00000000},
12990 + {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
12991 + 0x00000000},
12992 + {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
12993 + 0x00000000},
12994 + {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
12995 + 0x00000000},
12996 + {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
12997 + 0x00000000},
12998 + {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
12999 + 0x00000000},
13000 + {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
13001 + 0x00000000},
13002 + {0x00007838, 0x00000029, 0x00000029, 0x00000029, 0x00000029,
13003 + 0x00000029},
13004 + {0x00007824, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff,
13005 + 0x00d8abff},
13006 + {0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4,
13007 + 0x48609eb4},
13008 + {0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04,
13009 + 0x00000c04},
13010 + {0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a218652, 0x0a218652,
13011 + 0x0a22a652},
13012 + {0x0000a278, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd,
13013 + 0x3bdef7bd},
13014 + {0x0000a27c, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd,
13015 + 0x050e83bd},
13016 + {0x0000a394, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd,
13017 + 0x3bdef7bd},
13018 + {0x0000a398, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd,
13019 + 0x000003bd},
13020 + {0x0000a3dc, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd,
13021 + 0x3bdef7bd},
13022 + {0x0000a3e0, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd,
13023 + 0x000003bd},
13024 +};
13025 +
13026 +static const u_int32_t ar9271Modes_high_power_tx_gain_9271[][6] = {
13027 + {0x0000a300, 0x00000000, 0x00000000, 0x00010000, 0x00010000,
13028 + 0x00000000},
13029 + {0x0000a304, 0x00000000, 0x00000000, 0x00016200, 0x00016200,
13030 + 0x00000000},
13031 + {0x0000a308, 0x00000000, 0x00000000, 0x00018201, 0x00018201,
13032 + 0x00000000},
13033 + {0x0000a30c, 0x00000000, 0x00000000, 0x0001b240, 0x0001b240,
13034 + 0x00000000},
13035 + {0x0000a310, 0x00000000, 0x00000000, 0x0001d241, 0x0001d241,
13036 + 0x00000000},
13037 + {0x0000a314, 0x00000000, 0x00000000, 0x0001f600, 0x0001f600,
13038 + 0x00000000},
13039 + {0x0000a318, 0x00000000, 0x00000000, 0x00022800, 0x00022800,
13040 + 0x00000000},
13041 + {0x0000a31c, 0x00000000, 0x00000000, 0x00026802, 0x00026802,
13042 + 0x00000000},
13043 + {0x0000a320, 0x00000000, 0x00000000, 0x0002b805, 0x0002b805,
13044 + 0x00000000},
13045 + {0x0000a324, 0x00000000, 0x00000000, 0x0002ea41, 0x0002ea41,
13046 + 0x00000000},
13047 + {0x0000a328, 0x00000000, 0x00000000, 0x00038b00, 0x00038b00,
13048 + 0x00000000},
13049 + {0x0000a32c, 0x00000000, 0x00000000, 0x0003ab40, 0x0003ab40,
13050 + 0x00000000},
13051 + {0x0000a330, 0x00000000, 0x00000000, 0x0003cd80, 0x0003cd80,
13052 + 0x00000000},
13053 + {0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de,
13054 + 0x00000000},
13055 + {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e,
13056 + 0x00000000},
13057 + {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e,
13058 + 0x00000000},
13059 + {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
13060 + 0x00000000},
13061 + {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
13062 + 0x00000000},
13063 + {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
13064 + 0x00000000},
13065 + {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
13066 + 0x00000000},
13067 + {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
13068 + 0x00000000},
13069 + {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
13070 + 0x00000000},
13071 + {0x00007838, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b,
13072 + 0x0000002b},
13073 + {0x00007824, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff,
13074 + 0x00d8a7ff},
13075 + {0x0000786c, 0x08609eb6, 0x08609eb6, 0x08609eba, 0x08609eba,
13076 + 0x08609eb6},
13077 + {0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00,
13078 + 0x00000c00},
13079 + {0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a212652, 0x0a212652,
13080 + 0x0a22a652},
13081 + {0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7,
13082 + 0x0e739ce7},
13083 + {0x0000a27c, 0x05018063, 0x05038063, 0x05018063, 0x05018063,
13084 + 0x05018063},
13085 + {0x0000a394, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63,
13086 + 0x06318c63},
13087 + {0x0000a398, 0x00000063, 0x00000063, 0x00000063, 0x00000063,
13088 + 0x00000063},
13089 + {0x0000a3dc, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63,
13090 + 0x06318c63},
13091 + {0x0000a3e0, 0x00000063, 0x00000063, 0x00000063, 0x00000063,
13092 + 0x00000063},
13093 +};
13094 +
13095 +#endif /* INITVALS_9002_10_H */
13096 diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
13097 new file mode 100644
13098 index 0000000..d36085c
13099 --- /dev/null
13100 +++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
13101 @@ -0,0 +1,474 @@
13102 +/*
13103 + * Copyright (c) 2008-2010 Atheros Communications Inc.
13104 + *
13105 + * Permission to use, copy, modify, and/or distribute this software for any
13106 + * purpose with or without fee is hereby granted, provided that the above
13107 + * copyright notice and this permission notice appear in all copies.
13108 + *
13109 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13110 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13111 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13112 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13113 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13114 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
13115 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
13116 + */
13117 +
13118 +#include "hw.h"
13119 +
13120 +static void ar9002_hw_rx_enable(struct ath_hw *ah)
13121 +{
13122 + REG_WRITE(ah, AR_CR, AR_CR_RXE);
13123 +}
13124 +
13125 +static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
13126 +{
13127 + ((struct ath_desc*) ds)->ds_link = ds_link;
13128 +}
13129 +
13130 +static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
13131 +{
13132 + *ds_link = &((struct ath_desc *)ds)->ds_link;
13133 +}
13134 +
13135 +static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
13136 +{
13137 + u32 isr = 0;
13138 + u32 mask2 = 0;
13139 + struct ath9k_hw_capabilities *pCap = &ah->caps;
13140 + u32 sync_cause = 0;
13141 + bool fatal_int = false;
13142 + struct ath_common *common = ath9k_hw_common(ah);
13143 +
13144 + if (!AR_SREV_9100(ah)) {
13145 + if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
13146 + if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
13147 + == AR_RTC_STATUS_ON) {
13148 + isr = REG_READ(ah, AR_ISR);
13149 + }
13150 + }
13151 +
13152 + sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
13153 + AR_INTR_SYNC_DEFAULT;
13154 +
13155 + *masked = 0;
13156 +
13157 + if (!isr && !sync_cause)
13158 + return false;
13159 + } else {
13160 + *masked = 0;
13161 + isr = REG_READ(ah, AR_ISR);
13162 + }
13163 +
13164 + if (isr) {
13165 + if (isr & AR_ISR_BCNMISC) {
13166 + u32 isr2;
13167 + isr2 = REG_READ(ah, AR_ISR_S2);
13168 + if (isr2 & AR_ISR_S2_TIM)
13169 + mask2 |= ATH9K_INT_TIM;
13170 + if (isr2 & AR_ISR_S2_DTIM)
13171 + mask2 |= ATH9K_INT_DTIM;
13172 + if (isr2 & AR_ISR_S2_DTIMSYNC)
13173 + mask2 |= ATH9K_INT_DTIMSYNC;
13174 + if (isr2 & (AR_ISR_S2_CABEND))
13175 + mask2 |= ATH9K_INT_CABEND;
13176 + if (isr2 & AR_ISR_S2_GTT)
13177 + mask2 |= ATH9K_INT_GTT;
13178 + if (isr2 & AR_ISR_S2_CST)
13179 + mask2 |= ATH9K_INT_CST;
13180 + if (isr2 & AR_ISR_S2_TSFOOR)
13181 + mask2 |= ATH9K_INT_TSFOOR;
13182 + }
13183 +
13184 + isr = REG_READ(ah, AR_ISR_RAC);
13185 + if (isr == 0xffffffff) {
13186 + *masked = 0;
13187 + return false;
13188 + }
13189 +
13190 + *masked = isr & ATH9K_INT_COMMON;
13191 +
13192 + if (ah->config.rx_intr_mitigation) {
13193 + if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
13194 + *masked |= ATH9K_INT_RX;
13195 + }
13196 +
13197 + if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
13198 + *masked |= ATH9K_INT_RX;
13199 + if (isr &
13200 + (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
13201 + AR_ISR_TXEOL)) {
13202 + u32 s0_s, s1_s;
13203 +
13204 + *masked |= ATH9K_INT_TX;
13205 +
13206 + s0_s = REG_READ(ah, AR_ISR_S0_S);
13207 + ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
13208 + ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
13209 +
13210 + s1_s = REG_READ(ah, AR_ISR_S1_S);
13211 + ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
13212 + ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
13213 + }
13214 +
13215 + if (isr & AR_ISR_RXORN) {
13216 + ath_print(common, ATH_DBG_INTERRUPT,
13217 + "receive FIFO overrun interrupt\n");
13218 + }
13219 +
13220 + if (!AR_SREV_9100(ah)) {
13221 + if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
13222 + u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
13223 + if (isr5 & AR_ISR_S5_TIM_TIMER)
13224 + *masked |= ATH9K_INT_TIM_TIMER;
13225 + }
13226 + }
13227 +
13228 + *masked |= mask2;
13229 + }
13230 +
13231 + if (AR_SREV_9100(ah))
13232 + return true;
13233 +
13234 + if (isr & AR_ISR_GENTMR) {
13235 + u32 s5_s;
13236 +
13237 + s5_s = REG_READ(ah, AR_ISR_S5_S);
13238 + if (isr & AR_ISR_GENTMR) {
13239 + ah->intr_gen_timer_trigger =
13240 + MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
13241 +
13242 + ah->intr_gen_timer_thresh =
13243 + MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
13244 +
13245 + if (ah->intr_gen_timer_trigger)
13246 + *masked |= ATH9K_INT_GENTIMER;
13247 +
13248 + }
13249 + }
13250 +
13251 + if (sync_cause) {
13252 + fatal_int =
13253 + (sync_cause &
13254 + (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
13255 + ? true : false;
13256 +
13257 + if (fatal_int) {
13258 + if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
13259 + ath_print(common, ATH_DBG_ANY,
13260 + "received PCI FATAL interrupt\n");
13261 + }
13262 + if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
13263 + ath_print(common, ATH_DBG_ANY,
13264 + "received PCI PERR interrupt\n");
13265 + }
13266 + *masked |= ATH9K_INT_FATAL;
13267 + }
13268 + if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
13269 + ath_print(common, ATH_DBG_INTERRUPT,
13270 + "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
13271 + REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
13272 + REG_WRITE(ah, AR_RC, 0);
13273 + *masked |= ATH9K_INT_FATAL;
13274 + }
13275 + if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
13276 + ath_print(common, ATH_DBG_INTERRUPT,
13277 + "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
13278 + }
13279 +
13280 + REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
13281 + (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
13282 + }
13283 + return true;
13284 +}
13285 +
13286 +static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
13287 + bool is_firstseg, bool is_lastseg,
13288 + const void *ds0, dma_addr_t buf_addr,
13289 + unsigned int qcu)
13290 +{
13291 + struct ar5416_desc *ads = AR5416DESC(ds);
13292 +
13293 + ads->ds_data = buf_addr;
13294 +
13295 + if (is_firstseg) {
13296 + ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
13297 + } else if (is_lastseg) {
13298 + ads->ds_ctl0 = 0;
13299 + ads->ds_ctl1 = seglen;
13300 + ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
13301 + ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
13302 + } else {
13303 + ads->ds_ctl0 = 0;
13304 + ads->ds_ctl1 = seglen | AR_TxMore;
13305 + ads->ds_ctl2 = 0;
13306 + ads->ds_ctl3 = 0;
13307 + }
13308 + ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
13309 + ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
13310 + ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
13311 + ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
13312 + ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
13313 +}
13314 +
13315 +static void ar9002_hw_clear_txdesc(struct ath_hw *ah, void *ds)
13316 +{
13317 + struct ar5416_desc *ads = AR5416DESC(ds);
13318 +
13319 + ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
13320 + ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
13321 + ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
13322 + ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
13323 + ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
13324 +}
13325 +
13326 +static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
13327 + struct ath_tx_status *ts)
13328 +{
13329 + struct ar5416_desc *ads = AR5416DESC(ds);
13330 +
13331 + if ((ads->ds_txstatus9 & AR_TxDone) == 0)
13332 + return -EINPROGRESS;
13333 +
13334 + ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
13335 + ts->ts_tstamp = ads->AR_SendTimestamp;
13336 + ts->ts_status = 0;
13337 + ts->ts_flags = 0;
13338 +
13339 + if (ads->ds_txstatus1 & AR_FrmXmitOK)
13340 + ts->ts_status |= ATH9K_TX_ACKED;
13341 + if (ads->ds_txstatus1 & AR_ExcessiveRetries)
13342 + ts->ts_status |= ATH9K_TXERR_XRETRY;
13343 + if (ads->ds_txstatus1 & AR_Filtered)
13344 + ts->ts_status |= ATH9K_TXERR_FILT;
13345 + if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
13346 + ts->ts_status |= ATH9K_TXERR_FIFO;
13347 + ath9k_hw_updatetxtriglevel(ah, true);
13348 + }
13349 + if (ads->ds_txstatus9 & AR_TxOpExceeded)
13350 + ts->ts_status |= ATH9K_TXERR_XTXOP;
13351 + if (ads->ds_txstatus1 & AR_TxTimerExpired)
13352 + ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
13353 +
13354 + if (ads->ds_txstatus1 & AR_DescCfgErr)
13355 + ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
13356 + if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
13357 + ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
13358 + ath9k_hw_updatetxtriglevel(ah, true);
13359 + }
13360 + if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
13361 + ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
13362 + ath9k_hw_updatetxtriglevel(ah, true);
13363 + }
13364 + if (ads->ds_txstatus0 & AR_TxBaStatus) {
13365 + ts->ts_flags |= ATH9K_TX_BA;
13366 + ts->ba_low = ads->AR_BaBitmapLow;
13367 + ts->ba_high = ads->AR_BaBitmapHigh;
13368 + }
13369 +
13370 + ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
13371 + switch (ts->ts_rateindex) {
13372 + case 0:
13373 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
13374 + break;
13375 + case 1:
13376 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
13377 + break;
13378 + case 2:
13379 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
13380 + break;
13381 + case 3:
13382 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
13383 + break;
13384 + }
13385 +
13386 + ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
13387 + ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
13388 + ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
13389 + ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
13390 + ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
13391 + ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
13392 + ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
13393 + ts->evm0 = ads->AR_TxEVM0;
13394 + ts->evm1 = ads->AR_TxEVM1;
13395 + ts->evm2 = ads->AR_TxEVM2;
13396 + ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
13397 + ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
13398 + ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
13399 + ts->ts_antenna = 0;
13400 +
13401 + return 0;
13402 +}
13403 +
13404 +static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
13405 + u32 pktLen, enum ath9k_pkt_type type,
13406 + u32 txPower, u32 keyIx,
13407 + enum ath9k_key_type keyType, u32 flags)
13408 +{
13409 + struct ar5416_desc *ads = AR5416DESC(ds);
13410 +
13411 +
13412 + txPower += ah->txpower_indexoffset;
13413 + if (txPower > 63)
13414 + txPower = 63;
13415 +
13416 + ads->ds_ctl0 = (pktLen & AR_FrameLen)
13417 + | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
13418 + | SM(txPower, AR_XmitPower)
13419 + | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
13420 + | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
13421 + | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
13422 + | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
13423 +
13424 + ads->ds_ctl1 =
13425 + (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
13426 + | SM(type, AR_FrameType)
13427 + | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
13428 + | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
13429 + | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
13430 +
13431 + ads->ds_ctl6 = SM(keyType, AR_EncrType);
13432 +
13433 + if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
13434 + ads->ds_ctl8 = 0;
13435 + ads->ds_ctl9 = 0;
13436 + ads->ds_ctl10 = 0;
13437 + ads->ds_ctl11 = 0;
13438 + }
13439 +}
13440 +
13441 +static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
13442 + void *lastds,
13443 + u32 durUpdateEn, u32 rtsctsRate,
13444 + u32 rtsctsDuration,
13445 + struct ath9k_11n_rate_series series[],
13446 + u32 nseries, u32 flags)
13447 +{
13448 + struct ar5416_desc *ads = AR5416DESC(ds);
13449 + struct ar5416_desc *last_ads = AR5416DESC(lastds);
13450 + u32 ds_ctl0;
13451 +
13452 + if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
13453 + ds_ctl0 = ads->ds_ctl0;
13454 +
13455 + if (flags & ATH9K_TXDESC_RTSENA) {
13456 + ds_ctl0 &= ~AR_CTSEnable;
13457 + ds_ctl0 |= AR_RTSEnable;
13458 + } else {
13459 + ds_ctl0 &= ~AR_RTSEnable;
13460 + ds_ctl0 |= AR_CTSEnable;
13461 + }
13462 +
13463 + ads->ds_ctl0 = ds_ctl0;
13464 + } else {
13465 + ads->ds_ctl0 =
13466 + (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
13467 + }
13468 +
13469 + ads->ds_ctl2 = set11nTries(series, 0)
13470 + | set11nTries(series, 1)
13471 + | set11nTries(series, 2)
13472 + | set11nTries(series, 3)
13473 + | (durUpdateEn ? AR_DurUpdateEna : 0)
13474 + | SM(0, AR_BurstDur);
13475 +
13476 + ads->ds_ctl3 = set11nRate(series, 0)
13477 + | set11nRate(series, 1)
13478 + | set11nRate(series, 2)
13479 + | set11nRate(series, 3);
13480 +
13481 + ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
13482 + | set11nPktDurRTSCTS(series, 1);
13483 +
13484 + ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
13485 + | set11nPktDurRTSCTS(series, 3);
13486 +
13487 + ads->ds_ctl7 = set11nRateFlags(series, 0)
13488 + | set11nRateFlags(series, 1)
13489 + | set11nRateFlags(series, 2)
13490 + | set11nRateFlags(series, 3)
13491 + | SM(rtsctsRate, AR_RTSCTSRate);
13492 + last_ads->ds_ctl2 = ads->ds_ctl2;
13493 + last_ads->ds_ctl3 = ads->ds_ctl3;
13494 +}
13495 +
13496 +static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
13497 + u32 aggrLen)
13498 +{
13499 + struct ar5416_desc *ads = AR5416DESC(ds);
13500 +
13501 + ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
13502 + ads->ds_ctl6 &= ~AR_AggrLen;
13503 + ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
13504 +}
13505 +
13506 +static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
13507 + u32 numDelims)
13508 +{
13509 + struct ar5416_desc *ads = AR5416DESC(ds);
13510 + unsigned int ctl6;
13511 +
13512 + ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
13513 +
13514 + ctl6 = ads->ds_ctl6;
13515 + ctl6 &= ~AR_PadDelim;
13516 + ctl6 |= SM(numDelims, AR_PadDelim);
13517 + ads->ds_ctl6 = ctl6;
13518 +}
13519 +
13520 +static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
13521 +{
13522 + struct ar5416_desc *ads = AR5416DESC(ds);
13523 +
13524 + ads->ds_ctl1 |= AR_IsAggr;
13525 + ads->ds_ctl1 &= ~AR_MoreAggr;
13526 + ads->ds_ctl6 &= ~AR_PadDelim;
13527 +}
13528 +
13529 +static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
13530 +{
13531 + struct ar5416_desc *ads = AR5416DESC(ds);
13532 +
13533 + ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
13534 +}
13535 +
13536 +static void ar9002_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
13537 + u32 burstDuration)
13538 +{
13539 + struct ar5416_desc *ads = AR5416DESC(ds);
13540 +
13541 + ads->ds_ctl2 &= ~AR_BurstDur;
13542 + ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
13543 +}
13544 +
13545 +static void ar9002_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
13546 + u32 vmf)
13547 +{
13548 + struct ar5416_desc *ads = AR5416DESC(ds);
13549 +
13550 + if (vmf)
13551 + ads->ds_ctl0 |= AR_VirtMoreFrag;
13552 + else
13553 + ads->ds_ctl0 &= ~AR_VirtMoreFrag;
13554 +}
13555 +
13556 +void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
13557 +{
13558 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
13559 +
13560 + ops->rx_enable = ar9002_hw_rx_enable;
13561 + ops->set_desc_link = ar9002_hw_set_desc_link;
13562 + ops->get_desc_link = ar9002_hw_get_desc_link;
13563 + ops->get_isr = ar9002_hw_get_isr;
13564 + ops->fill_txdesc = ar9002_hw_fill_txdesc;
13565 + ops->clear_txdesc = ar9002_hw_clear_txdesc;
13566 + ops->proc_txdesc = ar9002_hw_proc_txdesc;
13567 + ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
13568 + ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
13569 + ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
13570 + ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
13571 + ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
13572 + ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
13573 + ops->set11n_burstduration = ar9002_hw_set11n_burstduration;
13574 + ops->set11n_virtualmorefrag = ar9002_hw_set11n_virtualmorefrag;
13575 +}
13576 diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.c b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
13577 new file mode 100644
13578 index 0000000..7790d93
13579 --- /dev/null
13580 +++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
13581 @@ -0,0 +1,601 @@
13582 +/*
13583 + * Copyright (c) 2008-2010 Atheros Communications Inc.
13584 + *
13585 + * Permission to use, copy, modify, and/or distribute this software for any
13586 + * purpose with or without fee is hereby granted, provided that the above
13587 + * copyright notice and this permission notice appear in all copies.
13588 + *
13589 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13590 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13591 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13592 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13593 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13594 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
13595 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
13596 + */
13597 +
13598 +/**
13599 + * DOC: Programming Atheros 802.11n analog front end radios
13600 + *
13601 + * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
13602 + * devices have either an external AR2133 analog front end radio for single
13603 + * band 2.4 GHz communication or an AR5133 analog front end radio for dual
13604 + * band 2.4 GHz / 5 GHz communication.
13605 + *
13606 + * All devices after the AR5416 and AR5418 family starting with the AR9280
13607 + * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
13608 + * into a single-chip and require less programming.
13609 + *
13610 + * The following single-chips exist with a respective embedded radio:
13611 + *
13612 + * AR9280 - 11n dual-band 2x2 MIMO for PCIe
13613 + * AR9281 - 11n single-band 1x2 MIMO for PCIe
13614 + * AR9285 - 11n single-band 1x1 for PCIe
13615 + * AR9287 - 11n single-band 2x2 MIMO for PCIe
13616 + *
13617 + * AR9220 - 11n dual-band 2x2 MIMO for PCI
13618 + * AR9223 - 11n single-band 2x2 MIMO for PCI
13619 + *
13620 + * AR9287 - 11n single-band 1x1 MIMO for USB
13621 + */
13622 +
13623 +#include "hw.h"
13624 +#include "ar9002_phy.h"
13625 +
13626 +/**
13627 + * ar9002_hw_set_channel - set channel on single-chip device
13628 + * @ah: atheros hardware structure
13629 + * @chan:
13630 + *
13631 + * This is the function to change channel on single-chip devices, that is
13632 + * all devices after ar9280.
13633 + *
13634 + * This function takes the channel value in MHz and sets
13635 + * hardware channel value. Assumes writes have been enabled to analog bus.
13636 + *
13637 + * Actual Expression,
13638 + *
13639 + * For 2GHz channel,
13640 + * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
13641 + * (freq_ref = 40MHz)
13642 + *
13643 + * For 5GHz channel,
13644 + * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
13645 + * (freq_ref = 40MHz/(24>>amodeRefSel))
13646 + */
13647 +static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
13648 +{
13649 + u16 bMode, fracMode, aModeRefSel = 0;
13650 + u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
13651 + struct chan_centers centers;
13652 + u32 refDivA = 24;
13653 +
13654 + ath9k_hw_get_channel_centers(ah, chan, &centers);
13655 + freq = centers.synth_center;
13656 +
13657 + reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
13658 + reg32 &= 0xc0000000;
13659 +
13660 + if (freq < 4800) { /* 2 GHz, fractional mode */
13661 + u32 txctl;
13662 + int regWrites = 0;
13663 +
13664 + bMode = 1;
13665 + fracMode = 1;
13666 + aModeRefSel = 0;
13667 + channelSel = CHANSEL_2G(freq);
13668 +
13669 + if (AR_SREV_9287_11_OR_LATER(ah)) {
13670 + if (freq == 2484) {
13671 + /* Enable channel spreading for channel 14 */
13672 + REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
13673 + 1, regWrites);
13674 + } else {
13675 + REG_WRITE_ARRAY(&ah->iniCckfirNormal,
13676 + 1, regWrites);
13677 + }
13678 + } else {
13679 + txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
13680 + if (freq == 2484) {
13681 + /* Enable channel spreading for channel 14 */
13682 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
13683 + txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
13684 + } else {
13685 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
13686 + txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
13687 + }
13688 + }
13689 + } else {
13690 + bMode = 0;
13691 + fracMode = 0;
13692 +
13693 + switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
13694 + case 0:
13695 + if ((freq % 20) == 0) {
13696 + aModeRefSel = 3;
13697 + } else if ((freq % 10) == 0) {
13698 + aModeRefSel = 2;
13699 + }
13700 + if (aModeRefSel)
13701 + break;
13702 + case 1:
13703 + default:
13704 + aModeRefSel = 0;
13705 + /*
13706 + * Enable 2G (fractional) mode for channels
13707 + * which are 5MHz spaced.
13708 + */
13709 + fracMode = 1;
13710 + refDivA = 1;
13711 + channelSel = CHANSEL_5G(freq);
13712 +
13713 + /* RefDivA setting */
13714 + REG_RMW_FIELD(ah, AR_AN_SYNTH9,
13715 + AR_AN_SYNTH9_REFDIVA, refDivA);
13716 +
13717 + }
13718 +
13719 + if (!fracMode) {
13720 + ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
13721 + channelSel = ndiv & 0x1ff;
13722 + channelFrac = (ndiv & 0xfffffe00) * 2;
13723 + channelSel = (channelSel << 17) | channelFrac;
13724 + }
13725 + }
13726 +
13727 + reg32 = reg32 |
13728 + (bMode << 29) |
13729 + (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
13730 +
13731 + REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
13732 +
13733 + ah->curchan = chan;
13734 + ah->curchan_rad_index = -1;
13735 +
13736 + return 0;
13737 +}
13738 +
13739 +/**
13740 + * ar9002_hw_spur_mitigate - convert baseband spur frequency
13741 + * @ah: atheros hardware structure
13742 + * @chan:
13743 + *
13744 + * For single-chip solutions. Converts to baseband spur frequency given the
13745 + * input channel frequency and compute register settings below.
13746 + */
13747 +static void ar9002_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
13748 +{
13749 + int bb_spur = AR_NO_SPUR;
13750 + int freq;
13751 + int bin, cur_bin;
13752 + int bb_spur_off, spur_subchannel_sd;
13753 + int spur_freq_sd;
13754 + int spur_delta_phase;
13755 + int denominator;
13756 + int upper, lower, cur_vit_mask;
13757 + int tmp, newVal;
13758 + int i;
13759 + int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
13760 + AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
13761 + };
13762 + int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
13763 + AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
13764 + };
13765 + int inc[4] = { 0, 100, 0, 0 };
13766 + struct chan_centers centers;
13767 +
13768 + int8_t mask_m[123];
13769 + int8_t mask_p[123];
13770 + int8_t mask_amt;
13771 + int tmp_mask;
13772 + int cur_bb_spur;
13773 + bool is2GHz = IS_CHAN_2GHZ(chan);
13774 +
13775 + memset(&mask_m, 0, sizeof(int8_t) * 123);
13776 + memset(&mask_p, 0, sizeof(int8_t) * 123);
13777 +
13778 + ath9k_hw_get_channel_centers(ah, chan, &centers);
13779 + freq = centers.synth_center;
13780 +
13781 + ah->config.spurmode = SPUR_ENABLE_EEPROM;
13782 + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
13783 + cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
13784 +
13785 + if (is2GHz)
13786 + cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
13787 + else
13788 + cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
13789 +
13790 + if (AR_NO_SPUR == cur_bb_spur)
13791 + break;
13792 + cur_bb_spur = cur_bb_spur - freq;
13793 +
13794 + if (IS_CHAN_HT40(chan)) {
13795 + if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
13796 + (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
13797 + bb_spur = cur_bb_spur;
13798 + break;
13799 + }
13800 + } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
13801 + (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
13802 + bb_spur = cur_bb_spur;
13803 + break;
13804 + }
13805 + }
13806 +
13807 + if (AR_NO_SPUR == bb_spur) {
13808 + REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
13809 + AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
13810 + return;
13811 + } else {
13812 + REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
13813 + AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
13814 + }
13815 +
13816 + bin = bb_spur * 320;
13817 +
13818 + tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
13819 +
13820 + newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
13821 + AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
13822 + AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
13823 + AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
13824 + REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
13825 +
13826 + newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
13827 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
13828 + AR_PHY_SPUR_REG_MASK_RATE_SELECT |
13829 + AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
13830 + SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
13831 + REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
13832 +
13833 + if (IS_CHAN_HT40(chan)) {
13834 + if (bb_spur < 0) {
13835 + spur_subchannel_sd = 1;
13836 + bb_spur_off = bb_spur + 10;
13837 + } else {
13838 + spur_subchannel_sd = 0;
13839 + bb_spur_off = bb_spur - 10;
13840 + }
13841 + } else {
13842 + spur_subchannel_sd = 0;
13843 + bb_spur_off = bb_spur;
13844 + }
13845 +
13846 + if (IS_CHAN_HT40(chan))
13847 + spur_delta_phase =
13848 + ((bb_spur * 262144) /
13849 + 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
13850 + else
13851 + spur_delta_phase =
13852 + ((bb_spur * 524288) /
13853 + 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
13854 +
13855 + denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
13856 + spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
13857 +
13858 + newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
13859 + SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
13860 + SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
13861 + REG_WRITE(ah, AR_PHY_TIMING11, newVal);
13862 +
13863 + newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
13864 + REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
13865 +
13866 + cur_bin = -6000;
13867 + upper = bin + 100;
13868 + lower = bin - 100;
13869 +
13870 + for (i = 0; i < 4; i++) {
13871 + int pilot_mask = 0;
13872 + int chan_mask = 0;
13873 + int bp = 0;
13874 + for (bp = 0; bp < 30; bp++) {
13875 + if ((cur_bin > lower) && (cur_bin < upper)) {
13876 + pilot_mask = pilot_mask | 0x1 << bp;
13877 + chan_mask = chan_mask | 0x1 << bp;
13878 + }
13879 + cur_bin += 100;
13880 + }
13881 + cur_bin += inc[i];
13882 + REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
13883 + REG_WRITE(ah, chan_mask_reg[i], chan_mask);
13884 + }
13885 +
13886 + cur_vit_mask = 6100;
13887 + upper = bin + 120;
13888 + lower = bin - 120;
13889 +
13890 + for (i = 0; i < 123; i++) {
13891 + if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
13892 +
13893 + /* workaround for gcc bug #37014 */
13894 + volatile int tmp_v = abs(cur_vit_mask - bin);
13895 +
13896 + if (tmp_v < 75)
13897 + mask_amt = 1;
13898 + else
13899 + mask_amt = 0;
13900 + if (cur_vit_mask < 0)
13901 + mask_m[abs(cur_vit_mask / 100)] = mask_amt;
13902 + else
13903 + mask_p[cur_vit_mask / 100] = mask_amt;
13904 + }
13905 + cur_vit_mask -= 100;
13906 + }
13907 +
13908 + tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
13909 + | (mask_m[48] << 26) | (mask_m[49] << 24)
13910 + | (mask_m[50] << 22) | (mask_m[51] << 20)
13911 + | (mask_m[52] << 18) | (mask_m[53] << 16)
13912 + | (mask_m[54] << 14) | (mask_m[55] << 12)
13913 + | (mask_m[56] << 10) | (mask_m[57] << 8)
13914 + | (mask_m[58] << 6) | (mask_m[59] << 4)
13915 + | (mask_m[60] << 2) | (mask_m[61] << 0);
13916 + REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
13917 + REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
13918 +
13919 + tmp_mask = (mask_m[31] << 28)
13920 + | (mask_m[32] << 26) | (mask_m[33] << 24)
13921 + | (mask_m[34] << 22) | (mask_m[35] << 20)
13922 + | (mask_m[36] << 18) | (mask_m[37] << 16)
13923 + | (mask_m[48] << 14) | (mask_m[39] << 12)
13924 + | (mask_m[40] << 10) | (mask_m[41] << 8)
13925 + | (mask_m[42] << 6) | (mask_m[43] << 4)
13926 + | (mask_m[44] << 2) | (mask_m[45] << 0);
13927 + REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
13928 + REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
13929 +
13930 + tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
13931 + | (mask_m[18] << 26) | (mask_m[18] << 24)
13932 + | (mask_m[20] << 22) | (mask_m[20] << 20)
13933 + | (mask_m[22] << 18) | (mask_m[22] << 16)
13934 + | (mask_m[24] << 14) | (mask_m[24] << 12)
13935 + | (mask_m[25] << 10) | (mask_m[26] << 8)
13936 + | (mask_m[27] << 6) | (mask_m[28] << 4)
13937 + | (mask_m[29] << 2) | (mask_m[30] << 0);
13938 + REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
13939 + REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
13940 +
13941 + tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
13942 + | (mask_m[2] << 26) | (mask_m[3] << 24)
13943 + | (mask_m[4] << 22) | (mask_m[5] << 20)
13944 + | (mask_m[6] << 18) | (mask_m[7] << 16)
13945 + | (mask_m[8] << 14) | (mask_m[9] << 12)
13946 + | (mask_m[10] << 10) | (mask_m[11] << 8)
13947 + | (mask_m[12] << 6) | (mask_m[13] << 4)
13948 + | (mask_m[14] << 2) | (mask_m[15] << 0);
13949 + REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
13950 + REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
13951 +
13952 + tmp_mask = (mask_p[15] << 28)
13953 + | (mask_p[14] << 26) | (mask_p[13] << 24)
13954 + | (mask_p[12] << 22) | (mask_p[11] << 20)
13955 + | (mask_p[10] << 18) | (mask_p[9] << 16)
13956 + | (mask_p[8] << 14) | (mask_p[7] << 12)
13957 + | (mask_p[6] << 10) | (mask_p[5] << 8)
13958 + | (mask_p[4] << 6) | (mask_p[3] << 4)
13959 + | (mask_p[2] << 2) | (mask_p[1] << 0);
13960 + REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
13961 + REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
13962 +
13963 + tmp_mask = (mask_p[30] << 28)
13964 + | (mask_p[29] << 26) | (mask_p[28] << 24)
13965 + | (mask_p[27] << 22) | (mask_p[26] << 20)
13966 + | (mask_p[25] << 18) | (mask_p[24] << 16)
13967 + | (mask_p[23] << 14) | (mask_p[22] << 12)
13968 + | (mask_p[21] << 10) | (mask_p[20] << 8)
13969 + | (mask_p[19] << 6) | (mask_p[18] << 4)
13970 + | (mask_p[17] << 2) | (mask_p[16] << 0);
13971 + REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
13972 + REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
13973 +
13974 + tmp_mask = (mask_p[45] << 28)
13975 + | (mask_p[44] << 26) | (mask_p[43] << 24)
13976 + | (mask_p[42] << 22) | (mask_p[41] << 20)
13977 + | (mask_p[40] << 18) | (mask_p[39] << 16)
13978 + | (mask_p[38] << 14) | (mask_p[37] << 12)
13979 + | (mask_p[36] << 10) | (mask_p[35] << 8)
13980 + | (mask_p[34] << 6) | (mask_p[33] << 4)
13981 + | (mask_p[32] << 2) | (mask_p[31] << 0);
13982 + REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
13983 + REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
13984 +
13985 + tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
13986 + | (mask_p[59] << 26) | (mask_p[58] << 24)
13987 + | (mask_p[57] << 22) | (mask_p[56] << 20)
13988 + | (mask_p[55] << 18) | (mask_p[54] << 16)
13989 + | (mask_p[53] << 14) | (mask_p[52] << 12)
13990 + | (mask_p[51] << 10) | (mask_p[50] << 8)
13991 + | (mask_p[49] << 6) | (mask_p[48] << 4)
13992 + | (mask_p[47] << 2) | (mask_p[46] << 0);
13993 + REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
13994 + REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
13995 +}
13996 +
13997 +static void ar9002_olc_init(struct ath_hw *ah)
13998 +{
13999 + u32 i;
14000 +
14001 + if (!OLC_FOR_AR9280_20_LATER)
14002 + return;
14003 +
14004 + if (OLC_FOR_AR9287_10_LATER) {
14005 + REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
14006 + AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
14007 + ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
14008 + AR9287_AN_TXPC0_TXPCMODE,
14009 + AR9287_AN_TXPC0_TXPCMODE_S,
14010 + AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
14011 + udelay(100);
14012 + } else {
14013 + for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
14014 + ah->originalGain[i] =
14015 + MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
14016 + AR_PHY_TX_GAIN);
14017 + ah->PDADCdelta = 0;
14018 + }
14019 +}
14020 +
14021 +static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
14022 + struct ath9k_channel *chan)
14023 +{
14024 + u32 pll;
14025 +
14026 + pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
14027 +
14028 + if (chan && IS_CHAN_HALF_RATE(chan))
14029 + pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
14030 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
14031 + pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
14032 +
14033 + if (chan && IS_CHAN_5GHZ(chan)) {
14034 + pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
14035 +
14036 +
14037 + if (AR_SREV_9280_20(ah)) {
14038 + if (((chan->channel % 20) == 0)
14039 + || ((chan->channel % 10) == 0))
14040 + pll = 0x2850;
14041 + else
14042 + pll = 0x142c;
14043 + }
14044 + } else {
14045 + pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
14046 + }
14047 +
14048 + return pll;
14049 +}
14050 +
14051 +static void ar9002_hw_do_getnf(struct ath_hw *ah,
14052 + int16_t nfarray[NUM_NF_READINGS])
14053 +{
14054 + struct ath_common *common = ath9k_hw_common(ah);
14055 + int16_t nf;
14056 +
14057 + nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
14058 +
14059 + if (nf & 0x100)
14060 + nf = 0 - ((nf ^ 0x1ff) + 1);
14061 + ath_print(common, ATH_DBG_CALIBRATE,
14062 + "NF calibrated [ctl] [chain 0] is %d\n", nf);
14063 +
14064 + if (AR_SREV_9271(ah) && (nf >= -114))
14065 + nf = -116;
14066 +
14067 + nfarray[0] = nf;
14068 +
14069 + if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
14070 + nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
14071 + AR9280_PHY_CH1_MINCCA_PWR);
14072 +
14073 + if (nf & 0x100)
14074 + nf = 0 - ((nf ^ 0x1ff) + 1);
14075 + ath_print(common, ATH_DBG_CALIBRATE,
14076 + "NF calibrated [ctl] [chain 1] is %d\n", nf);
14077 + nfarray[1] = nf;
14078 + }
14079 +
14080 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
14081 + if (nf & 0x100)
14082 + nf = 0 - ((nf ^ 0x1ff) + 1);
14083 + ath_print(common, ATH_DBG_CALIBRATE,
14084 + "NF calibrated [ext] [chain 0] is %d\n", nf);
14085 +
14086 + if (AR_SREV_9271(ah) && (nf >= -114))
14087 + nf = -116;
14088 +
14089 + nfarray[3] = nf;
14090 +
14091 + if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
14092 + nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
14093 + AR9280_PHY_CH1_EXT_MINCCA_PWR);
14094 +
14095 + if (nf & 0x100)
14096 + nf = 0 - ((nf ^ 0x1ff) + 1);
14097 + ath_print(common, ATH_DBG_CALIBRATE,
14098 + "NF calibrated [ext] [chain 1] is %d\n", nf);
14099 + nfarray[4] = nf;
14100 + }
14101 +}
14102 +
14103 +static void ar9002_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
14104 +{
14105 + struct ath9k_nfcal_hist *h;
14106 + int i, j;
14107 + int32_t val;
14108 + const u32 ar5416_cca_regs[6] = {
14109 + AR_PHY_CCA,
14110 + AR_PHY_CH1_CCA,
14111 + AR_PHY_CH2_CCA,
14112 + AR_PHY_EXT_CCA,
14113 + AR_PHY_CH1_EXT_CCA,
14114 + AR_PHY_CH2_EXT_CCA
14115 + };
14116 + u8 chainmask, rx_chain_status;
14117 +
14118 + rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
14119 + if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
14120 + chainmask = 0x9;
14121 + else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
14122 + if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
14123 + chainmask = 0x1B;
14124 + else
14125 + chainmask = 0x09;
14126 + } else {
14127 + if (rx_chain_status & 0x4)
14128 + chainmask = 0x3F;
14129 + else if (rx_chain_status & 0x2)
14130 + chainmask = 0x1B;
14131 + else
14132 + chainmask = 0x09;
14133 + }
14134 +
14135 + h = ah->nfCalHist;
14136 +
14137 + for (i = 0; i < NUM_NF_READINGS; i++) {
14138 + if (chainmask & (1 << i)) {
14139 + val = REG_READ(ah, ar5416_cca_regs[i]);
14140 + val &= 0xFFFFFE00;
14141 + val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
14142 + REG_WRITE(ah, ar5416_cca_regs[i], val);
14143 + }
14144 + }
14145 +
14146 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
14147 + AR_PHY_AGC_CONTROL_ENABLE_NF);
14148 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
14149 + AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
14150 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
14151 +
14152 + for (j = 0; j < 5; j++) {
14153 + if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
14154 + AR_PHY_AGC_CONTROL_NF) == 0)
14155 + break;
14156 + udelay(50);
14157 + }
14158 +
14159 + for (i = 0; i < NUM_NF_READINGS; i++) {
14160 + if (chainmask & (1 << i)) {
14161 + val = REG_READ(ah, ar5416_cca_regs[i]);
14162 + val &= 0xFFFFFE00;
14163 + val |= (((u32) (-50) << 1) & 0x1ff);
14164 + REG_WRITE(ah, ar5416_cca_regs[i], val);
14165 + }
14166 + }
14167 +}
14168 +
14169 +void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
14170 +{
14171 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
14172 +
14173 + priv_ops->set_rf_regs = NULL;
14174 + priv_ops->rf_alloc_ext_banks = NULL;
14175 + priv_ops->rf_free_ext_banks = NULL;
14176 + priv_ops->rf_set_freq = ar9002_hw_set_channel;
14177 + priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
14178 + priv_ops->olc_init = ar9002_olc_init;
14179 + priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
14180 + priv_ops->do_getnf = ar9002_hw_do_getnf;
14181 + priv_ops->loadnf = ar9002_hw_loadnf;
14182 +}
14183 diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.h b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
14184 new file mode 100644
14185 index 0000000..07be17a
14186 --- /dev/null
14187 +++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
14188 @@ -0,0 +1,572 @@
14189 +/*
14190 + * Copyright (c) 2008-2010 Atheros Communications Inc.
14191 + *
14192 + * Permission to use, copy, modify, and/or distribute this software for any
14193 + * purpose with or without fee is hereby granted, provided that the above
14194 + * copyright notice and this permission notice appear in all copies.
14195 + *
14196 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14197 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14198 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14199 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14200 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14201 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14202 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14203 + */
14204 +#ifndef AR9002_PHY_H
14205 +#define AR9002_PHY_H
14206 +
14207 +#define AR_PHY_TEST 0x9800
14208 +#define PHY_AGC_CLR 0x10000000
14209 +#define RFSILENT_BB 0x00002000
14210 +
14211 +#define AR_PHY_TURBO 0x9804
14212 +#define AR_PHY_FC_TURBO_MODE 0x00000001
14213 +#define AR_PHY_FC_TURBO_SHORT 0x00000002
14214 +#define AR_PHY_FC_DYN2040_EN 0x00000004
14215 +#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
14216 +#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
14217 +/* For 25 MHz channel spacing -- not used but supported by hw */
14218 +#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
14219 +#define AR_PHY_FC_HT_EN 0x00000040
14220 +#define AR_PHY_FC_SHORT_GI_40 0x00000080
14221 +#define AR_PHY_FC_WALSH 0x00000100
14222 +#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
14223 +#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
14224 +
14225 +#define AR_PHY_TEST2 0x9808
14226 +
14227 +#define AR_PHY_TIMING2 0x9810
14228 +#define AR_PHY_TIMING3 0x9814
14229 +#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
14230 +#define AR_PHY_TIMING3_DSC_MAN_S 17
14231 +#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
14232 +#define AR_PHY_TIMING3_DSC_EXP_S 13
14233 +
14234 +#define AR_PHY_CHIP_ID_REV_0 0x80
14235 +#define AR_PHY_CHIP_ID_REV_1 0x81
14236 +#define AR_PHY_CHIP_ID_9160_REV_0 0xb0
14237 +
14238 +#define AR_PHY_ACTIVE 0x981C
14239 +#define AR_PHY_ACTIVE_EN 0x00000001
14240 +#define AR_PHY_ACTIVE_DIS 0x00000000
14241 +
14242 +#define AR_PHY_RF_CTL2 0x9824
14243 +#define AR_PHY_TX_END_DATA_START 0x000000FF
14244 +#define AR_PHY_TX_END_DATA_START_S 0
14245 +#define AR_PHY_TX_END_PA_ON 0x0000FF00
14246 +#define AR_PHY_TX_END_PA_ON_S 8
14247 +
14248 +#define AR_PHY_RF_CTL3 0x9828
14249 +#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
14250 +#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
14251 +
14252 +#define AR_PHY_ADC_CTL 0x982C
14253 +#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
14254 +#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
14255 +#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
14256 +#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
14257 +#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
14258 +#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
14259 +#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
14260 +
14261 +#define AR_PHY_ADC_SERIAL_CTL 0x9830
14262 +#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
14263 +#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
14264 +
14265 +#define AR_PHY_RF_CTL4 0x9834
14266 +#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
14267 +#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
14268 +#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
14269 +#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
14270 +#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
14271 +#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
14272 +#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
14273 +#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
14274 +
14275 +#define AR_PHY_TSTDAC_CONST 0x983c
14276 +
14277 +#define AR_PHY_SETTLING 0x9844
14278 +#define AR_PHY_SETTLING_SWITCH 0x00003F80
14279 +#define AR_PHY_SETTLING_SWITCH_S 7
14280 +
14281 +#define AR_PHY_RXGAIN 0x9848
14282 +#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
14283 +#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
14284 +#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
14285 +#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
14286 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
14287 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
14288 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
14289 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
14290 +
14291 +#define AR_PHY_DESIRED_SZ 0x9850
14292 +#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
14293 +#define AR_PHY_DESIRED_SZ_ADC_S 0
14294 +#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
14295 +#define AR_PHY_DESIRED_SZ_PGA_S 8
14296 +#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
14297 +#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
14298 +
14299 +#define AR_PHY_FIND_SIG 0x9858
14300 +#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
14301 +#define AR_PHY_FIND_SIG_FIRSTEP_S 12
14302 +#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
14303 +#define AR_PHY_FIND_SIG_FIRPWR_S 18
14304 +
14305 +#define AR_PHY_AGC_CTL1 0x985C
14306 +#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
14307 +#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
14308 +#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
14309 +#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
14310 +
14311 +#define AR_PHY_CCA 0x9864
14312 +#define AR_PHY_MINCCA_PWR 0x0FF80000
14313 +#define AR_PHY_MINCCA_PWR_S 19
14314 +#define AR_PHY_CCA_THRESH62 0x0007F000
14315 +#define AR_PHY_CCA_THRESH62_S 12
14316 +#define AR9280_PHY_MINCCA_PWR 0x1FF00000
14317 +#define AR9280_PHY_MINCCA_PWR_S 20
14318 +#define AR9280_PHY_CCA_THRESH62 0x000FF000
14319 +#define AR9280_PHY_CCA_THRESH62_S 12
14320 +
14321 +#define AR_PHY_SFCORR_LOW 0x986C
14322 +#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
14323 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
14324 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
14325 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
14326 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
14327 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
14328 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
14329 +
14330 +#define AR_PHY_SFCORR 0x9868
14331 +#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
14332 +#define AR_PHY_SFCORR_M2COUNT_THR_S 0
14333 +#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
14334 +#define AR_PHY_SFCORR_M1_THRESH_S 17
14335 +#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
14336 +#define AR_PHY_SFCORR_M2_THRESH_S 24
14337 +
14338 +#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
14339 +#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
14340 +#define AR_PHY_SYNTH_CONTROL 0x9874
14341 +#define AR_PHY_SLEEP_SCAL 0x9878
14342 +
14343 +#define AR_PHY_PLL_CTL 0x987c
14344 +#define AR_PHY_PLL_CTL_40 0xaa
14345 +#define AR_PHY_PLL_CTL_40_5413 0x04
14346 +#define AR_PHY_PLL_CTL_44 0xab
14347 +#define AR_PHY_PLL_CTL_44_2133 0xeb
14348 +#define AR_PHY_PLL_CTL_40_2133 0xea
14349 +
14350 +#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
14351 +#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
14352 +#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
14353 +#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
14354 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
14355 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
14356 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
14357 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
14358 +#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
14359 +#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
14360 +#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
14361 +#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
14362 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
14363 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
14364 +
14365 +#define AR_PHY_RX_DELAY 0x9914
14366 +#define AR_PHY_SEARCH_START_DELAY 0x9918
14367 +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
14368 +
14369 +#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
14370 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
14371 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
14372 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
14373 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
14374 +#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
14375 +#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
14376 +#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
14377 +#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
14378 +
14379 +#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
14380 +#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
14381 +#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
14382 +#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
14383 +
14384 +#define AR_PHY_TIMING5 0x9924
14385 +#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
14386 +#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
14387 +
14388 +#define AR_PHY_POWER_TX_RATE1 0x9934
14389 +#define AR_PHY_POWER_TX_RATE2 0x9938
14390 +#define AR_PHY_POWER_TX_RATE_MAX 0x993c
14391 +#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
14392 +
14393 +#define AR_PHY_FRAME_CTL 0x9944
14394 +#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
14395 +#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
14396 +
14397 +#define AR_PHY_TXPWRADJ 0x994C
14398 +#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
14399 +#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
14400 +#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
14401 +#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
14402 +
14403 +#define AR_PHY_RADAR_EXT 0x9940
14404 +#define AR_PHY_RADAR_EXT_ENA 0x00004000
14405 +
14406 +#define AR_PHY_RADAR_0 0x9954
14407 +#define AR_PHY_RADAR_0_ENA 0x00000001
14408 +#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
14409 +#define AR_PHY_RADAR_0_INBAND 0x0000003e
14410 +#define AR_PHY_RADAR_0_INBAND_S 1
14411 +#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
14412 +#define AR_PHY_RADAR_0_PRSSI_S 6
14413 +#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
14414 +#define AR_PHY_RADAR_0_HEIGHT_S 12
14415 +#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
14416 +#define AR_PHY_RADAR_0_RRSSI_S 18
14417 +#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
14418 +#define AR_PHY_RADAR_0_FIRPWR_S 24
14419 +
14420 +#define AR_PHY_RADAR_1 0x9958
14421 +#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
14422 +#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
14423 +#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
14424 +#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
14425 +#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
14426 +#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
14427 +#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
14428 +#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
14429 +#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
14430 +#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
14431 +#define AR_PHY_RADAR_1_MAXLEN_S 0
14432 +
14433 +#define AR_PHY_SWITCH_CHAIN_0 0x9960
14434 +#define AR_PHY_SWITCH_COM 0x9964
14435 +
14436 +#define AR_PHY_SIGMA_DELTA 0x996C
14437 +#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
14438 +#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
14439 +#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
14440 +#define AR_PHY_SIGMA_DELTA_FILT2_S 3
14441 +#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
14442 +#define AR_PHY_SIGMA_DELTA_FILT1_S 8
14443 +#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
14444 +#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
14445 +
14446 +#define AR_PHY_RESTART 0x9970
14447 +#define AR_PHY_RESTART_DIV_GC 0x001C0000
14448 +#define AR_PHY_RESTART_DIV_GC_S 18
14449 +
14450 +#define AR_PHY_RFBUS_REQ 0x997C
14451 +#define AR_PHY_RFBUS_REQ_EN 0x00000001
14452 +
14453 +#define AR_PHY_TIMING7 0x9980
14454 +#define AR_PHY_TIMING8 0x9984
14455 +#define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
14456 +#define AR_PHY_TIMING8_PILOT_MASK_2_S 0
14457 +
14458 +#define AR_PHY_BIN_MASK2_1 0x9988
14459 +#define AR_PHY_BIN_MASK2_2 0x998c
14460 +#define AR_PHY_BIN_MASK2_3 0x9990
14461 +#define AR_PHY_BIN_MASK2_4 0x9994
14462 +
14463 +#define AR_PHY_BIN_MASK_1 0x9900
14464 +#define AR_PHY_BIN_MASK_2 0x9904
14465 +#define AR_PHY_BIN_MASK_3 0x9908
14466 +
14467 +#define AR_PHY_MASK_CTL 0x990c
14468 +
14469 +#define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
14470 +#define AR_PHY_BIN_MASK2_4_MASK_4_S 0
14471 +
14472 +#define AR_PHY_TIMING9 0x9998
14473 +#define AR_PHY_TIMING10 0x999c
14474 +#define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
14475 +#define AR_PHY_TIMING10_PILOT_MASK_2_S 0
14476 +
14477 +#define AR_PHY_TIMING11 0x99a0
14478 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
14479 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
14480 +#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
14481 +#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
14482 +
14483 +#define AR_PHY_RX_CHAINMASK 0x99a4
14484 +#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
14485 +#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
14486 +#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
14487 +
14488 +#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
14489 +#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
14490 +#define AR_PHY_9285_ANT_DIV_CTL 0x01000000
14491 +#define AR_PHY_9285_ANT_DIV_CTL_S 24
14492 +#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
14493 +#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
14494 +#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
14495 +#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
14496 +#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
14497 +#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
14498 +#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
14499 +#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
14500 +#define AR_PHY_9285_ANT_DIV_LNA1 2
14501 +#define AR_PHY_9285_ANT_DIV_LNA2 1
14502 +#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
14503 +#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
14504 +#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
14505 +#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
14506 +
14507 +#define AR_PHY_EXT_CCA0 0x99b8
14508 +#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
14509 +#define AR_PHY_EXT_CCA0_THRESH62_S 0
14510 +
14511 +#define AR_PHY_EXT_CCA 0x99bc
14512 +#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
14513 +#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
14514 +#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
14515 +#define AR_PHY_EXT_CCA_THRESH62_S 16
14516 +#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
14517 +#define AR_PHY_EXT_MINCCA_PWR_S 23
14518 +#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
14519 +#define AR9280_PHY_EXT_MINCCA_PWR_S 16
14520 +
14521 +#define AR_PHY_SFCORR_EXT 0x99c0
14522 +#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
14523 +#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
14524 +#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
14525 +#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
14526 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
14527 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
14528 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
14529 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
14530 +#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
14531 +
14532 +#define AR_PHY_HALFGI 0x99D0
14533 +#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
14534 +#define AR_PHY_HALFGI_DSC_MAN_S 4
14535 +#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
14536 +#define AR_PHY_HALFGI_DSC_EXP_S 0
14537 +
14538 +#define AR_PHY_CHAN_INFO_MEMORY 0x99DC
14539 +#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
14540 +
14541 +#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
14542 +
14543 +#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC
14544 +#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
14545 +
14546 +#define AR_PHY_M_SLEEP 0x99f0
14547 +#define AR_PHY_REFCLKDLY 0x99f4
14548 +#define AR_PHY_REFCLKPD 0x99f8
14549 +
14550 +#define AR_PHY_CALMODE 0x99f0
14551 +
14552 +#define AR_PHY_CALMODE_IQ 0x00000000
14553 +#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
14554 +#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
14555 +#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
14556 +
14557 +#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
14558 +#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
14559 +#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
14560 +#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
14561 +
14562 +#define AR_PHY_CURRENT_RSSI 0x9c1c
14563 +#define AR9280_PHY_CURRENT_RSSI 0x9c3c
14564 +
14565 +#define AR_PHY_RFBUS_GRANT 0x9C20
14566 +#define AR_PHY_RFBUS_GRANT_EN 0x00000001
14567 +
14568 +#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
14569 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
14570 +
14571 +#define AR_PHY_CHAN_INFO_GAIN 0x9CFC
14572 +
14573 +#define AR_PHY_MODE 0xA200
14574 +#define AR_PHY_MODE_ASYNCFIFO 0x80
14575 +#define AR_PHY_MODE_AR2133 0x08
14576 +#define AR_PHY_MODE_AR5111 0x00
14577 +#define AR_PHY_MODE_AR5112 0x08
14578 +#define AR_PHY_MODE_DYNAMIC 0x04
14579 +#define AR_PHY_MODE_RF2GHZ 0x02
14580 +#define AR_PHY_MODE_RF5GHZ 0x00
14581 +#define AR_PHY_MODE_CCK 0x01
14582 +#define AR_PHY_MODE_OFDM 0x00
14583 +#define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
14584 +
14585 +#define AR_PHY_CCK_TX_CTRL 0xA204
14586 +#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
14587 +#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
14588 +#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
14589 +
14590 +#define AR_PHY_CCK_DETECT 0xA208
14591 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
14592 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
14593 +/* [12:6] settling time for antenna switch */
14594 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
14595 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
14596 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
14597 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
14598 +
14599 +#define AR_PHY_GAIN_2GHZ 0xA20C
14600 +#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
14601 +#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
14602 +#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
14603 +#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
14604 +#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
14605 +#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
14606 +
14607 +#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
14608 +#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
14609 +#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
14610 +#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
14611 +#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
14612 +#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
14613 +#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
14614 +#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
14615 +
14616 +#define AR_PHY_CCK_RXCTRL4 0xA21C
14617 +#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
14618 +#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
14619 +
14620 +#define AR_PHY_DAG_CTRLCCK 0xA228
14621 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
14622 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
14623 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
14624 +
14625 +#define AR_PHY_FORCE_CLKEN_CCK 0xA22C
14626 +#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
14627 +
14628 +#define AR_PHY_POWER_TX_RATE3 0xA234
14629 +#define AR_PHY_POWER_TX_RATE4 0xA238
14630 +
14631 +#define AR_PHY_SCRM_SEQ_XR 0xA23C
14632 +#define AR_PHY_HEADER_DETECT_XR 0xA240
14633 +#define AR_PHY_CHIRP_DETECTED_XR 0xA244
14634 +#define AR_PHY_BLUETOOTH 0xA254
14635 +
14636 +#define AR_PHY_TPCRG1 0xA258
14637 +#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
14638 +#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
14639 +
14640 +#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
14641 +#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
14642 +#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
14643 +#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
14644 +#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
14645 +#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
14646 +
14647 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
14648 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
14649 +
14650 +#define AR_PHY_TX_PWRCTRL4 0xa264
14651 +#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
14652 +#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
14653 +#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
14654 +#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
14655 +
14656 +#define AR_PHY_TX_PWRCTRL6_0 0xa270
14657 +#define AR_PHY_TX_PWRCTRL6_1 0xb270
14658 +#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
14659 +#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
14660 +
14661 +#define AR_PHY_TX_PWRCTRL7 0xa274
14662 +#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
14663 +#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
14664 +
14665 +#define AR_PHY_TX_PWRCTRL9 0xa27C
14666 +#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
14667 +#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
14668 +#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
14669 +#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
14670 +
14671 +#define AR_PHY_TX_GAIN_TBL1 0xa300
14672 +#define AR_PHY_TX_GAIN 0x0007F000
14673 +#define AR_PHY_TX_GAIN_S 12
14674 +
14675 +#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
14676 +#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
14677 +#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00
14678 +#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
14679 +
14680 +#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
14681 +#define AR_PHY_MASK2_M_31_45 0xa3a4
14682 +#define AR_PHY_MASK2_M_16_30 0xa3a8
14683 +#define AR_PHY_MASK2_M_00_15 0xa3ac
14684 +#define AR_PHY_MASK2_P_15_01 0xa3b8
14685 +#define AR_PHY_MASK2_P_30_16 0xa3bc
14686 +#define AR_PHY_MASK2_P_45_31 0xa3c0
14687 +#define AR_PHY_MASK2_P_61_45 0xa3c4
14688 +#define AR_PHY_SPUR_REG 0x994c
14689 +
14690 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
14691 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
14692 +
14693 +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
14694 +#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
14695 +#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
14696 +#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
14697 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
14698 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
14699 +
14700 +#define AR_PHY_PILOT_MASK_01_30 0xa3b0
14701 +#define AR_PHY_PILOT_MASK_31_60 0xa3b4
14702 +
14703 +#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
14704 +#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
14705 +
14706 +#define AR_PHY_ANALOG_SWAP 0xa268
14707 +#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
14708 +
14709 +#define AR_PHY_TPCRG5 0xA26C
14710 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
14711 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
14712 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
14713 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
14714 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
14715 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
14716 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
14717 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
14718 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
14719 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
14720 +
14721 +/* Carrier leak calibration control, do it after AGC calibration */
14722 +#define AR_PHY_CL_CAL_CTL 0xA358
14723 +#define AR_PHY_CL_CAL_ENABLE 0x00000002
14724 +#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
14725 +
14726 +#define AR_PHY_POWER_TX_RATE5 0xA38C
14727 +#define AR_PHY_POWER_TX_RATE6 0xA390
14728 +
14729 +#define AR_PHY_CAL_CHAINMASK 0xA39C
14730 +
14731 +#define AR_PHY_POWER_TX_SUB 0xA3C8
14732 +#define AR_PHY_POWER_TX_RATE7 0xA3CC
14733 +#define AR_PHY_POWER_TX_RATE8 0xA3D0
14734 +#define AR_PHY_POWER_TX_RATE9 0xA3D4
14735 +
14736 +#define AR_PHY_XPA_CFG 0xA3D8
14737 +#define AR_PHY_FORCE_XPA_CFG 0x000000001
14738 +#define AR_PHY_FORCE_XPA_CFG_S 0
14739 +
14740 +#define AR_PHY_CH1_CCA 0xa864
14741 +#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
14742 +#define AR_PHY_CH1_MINCCA_PWR_S 19
14743 +#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
14744 +#define AR9280_PHY_CH1_MINCCA_PWR_S 20
14745 +
14746 +#define AR_PHY_CH2_CCA 0xb864
14747 +#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
14748 +#define AR_PHY_CH2_MINCCA_PWR_S 19
14749 +
14750 +#define AR_PHY_CH1_EXT_CCA 0xa9bc
14751 +#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
14752 +#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
14753 +#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
14754 +#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
14755 +
14756 +#define AR_PHY_CH2_EXT_CCA 0xb9bc
14757 +#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
14758 +#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
14759 +
14760 +#endif
14761 diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
14762 new file mode 100644
14763 index 0000000..498f60a
14764 --- /dev/null
14765 +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
14766 @@ -0,0 +1,798 @@
14767 +/*
14768 + * Copyright (c) 2010 Atheros Communications Inc.
14769 + *
14770 + * Permission to use, copy, modify, and/or distribute this software for any
14771 + * purpose with or without fee is hereby granted, provided that the above
14772 + * copyright notice and this permission notice appear in all copies.
14773 + *
14774 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14775 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14776 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14777 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14778 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14779 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14780 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14781 + */
14782 +
14783 +#include "hw.h"
14784 +#include "hw-ops.h"
14785 +#include "ar9003_phy.h"
14786 +
14787 +static void ar9003_hw_setup_calibration(struct ath_hw *ah,
14788 + struct ath9k_cal_list *currCal)
14789 +{
14790 + struct ath_common *common = ath9k_hw_common(ah);
14791 +
14792 + /* Select calibration to run */
14793 + switch(currCal->calData->calType) {
14794 + case IQ_MISMATCH_CAL:
14795 + /*
14796 + * Start calibration with
14797 + * 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples
14798 + */
14799 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
14800 + AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX,
14801 + currCal->calData->calCountMax);
14802 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
14803 +
14804 + ath_print(common, ATH_DBG_CALIBRATE,
14805 + "starting IQ Mismatch Calibration\n");
14806 +
14807 + /* Kick-off cal */
14808 + REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
14809 + break;
14810 + case TEMP_COMP_CAL:
14811 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
14812 + AR_PHY_65NM_CH0_THERM_LOCAL, 1);
14813 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
14814 + AR_PHY_65NM_CH0_THERM_START, 1);
14815 +
14816 + ath_print(common, ATH_DBG_CALIBRATE,
14817 + "starting Temperature Compensation Calibration\n");
14818 + break;
14819 + case ADC_DC_INIT_CAL:
14820 + case ADC_GAIN_CAL:
14821 + case ADC_DC_CAL:
14822 + /* Not yet */
14823 + break;
14824 + }
14825 +}
14826 +
14827 +/*
14828 + * Generic calibration routine.
14829 + * Recalibrate the lower PHY chips to account for temperature/environment
14830 + * changes.
14831 + */
14832 +static bool ar9003_hw_per_calibration(struct ath_hw *ah,
14833 + struct ath9k_channel *ichan,
14834 + u8 rxchainmask,
14835 + struct ath9k_cal_list *currCal)
14836 +{
14837 + /* Cal is assumed not done until explicitly set below */
14838 + bool iscaldone = false;
14839 +
14840 + /* Calibration in progress. */
14841 + if (currCal->calState == CAL_RUNNING) {
14842 + /* Check to see if it has finished. */
14843 + if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) {
14844 + /*
14845 + * Accumulate cal measures for active chains
14846 + */
14847 + currCal->calData->calCollect(ah);
14848 + ah->cal_samples++;
14849 +
14850 + if (ah->cal_samples >=
14851 + currCal->calData->calNumSamples) {
14852 + unsigned int i, numChains = 0;
14853 + for (i = 0; i < AR9300_MAX_CHAINS; i++) {
14854 + if (rxchainmask & (1 << i))
14855 + numChains++;
14856 + }
14857 +
14858 + /*
14859 + * Process accumulated data
14860 + */
14861 + currCal->calData->calPostProc(ah, numChains);
14862 +
14863 + /* Calibration has finished. */
14864 + ichan->CalValid |= currCal->calData->calType;
14865 + currCal->calState = CAL_DONE;
14866 + iscaldone = true;
14867 + } else {
14868 + /*
14869 + * Set-up collection of another sub-sample until we
14870 + * get desired number
14871 + */
14872 + ar9003_hw_setup_calibration(ah, currCal);
14873 + }
14874 + }
14875 + } else if (!(ichan->CalValid & currCal->calData->calType)) {
14876 + /* If current cal is marked invalid in channel, kick it off */
14877 + ath9k_hw_reset_calibration(ah, currCal);
14878 + }
14879 +
14880 + return iscaldone;
14881 +}
14882 +
14883 +static bool ar9003_hw_calibrate(struct ath_hw *ah,
14884 + struct ath9k_channel *chan,
14885 + u8 rxchainmask,
14886 + bool longcal)
14887 +{
14888 + bool iscaldone = true;
14889 + struct ath9k_cal_list *currCal = ah->cal_list_curr;
14890 +
14891 + /*
14892 + * For given calibration:
14893 + * 1. Call generic cal routine
14894 + * 2. When this cal is done (isCalDone) if we have more cals waiting
14895 + * (eg after reset), mask this to upper layers by not propagating
14896 + * isCalDone if it is set to TRUE.
14897 + * Instead, change isCalDone to FALSE and setup the waiting cal(s)
14898 + * to be run.
14899 + */
14900 + if (currCal &&
14901 + (currCal->calState == CAL_RUNNING ||
14902 + currCal->calState == CAL_WAITING)) {
14903 + iscaldone = ar9003_hw_per_calibration(ah, chan,
14904 + rxchainmask, currCal);
14905 + if (iscaldone) {
14906 + ah->cal_list_curr = currCal = currCal->calNext;
14907 +
14908 + if (currCal->calState == CAL_WAITING) {
14909 + iscaldone = false;
14910 + ath9k_hw_reset_calibration(ah, currCal);
14911 + }
14912 + }
14913 + }
14914 +
14915 + /* Do NF cal only at longer intervals */
14916 + if (longcal) {
14917 + /*
14918 + * Load the NF from history buffer of the current channel.
14919 + * NF is slow time-variant, so it is OK to use a historical value.
14920 + */
14921 + ath9k_hw_loadnf(ah, ah->curchan);
14922 +
14923 + /* start NF calibration, without updating BB NF register */
14924 + ath9k_hw_start_nfcal(ah);
14925 + }
14926 +
14927 + return iscaldone;
14928 +}
14929 +
14930 +static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
14931 +{
14932 + int i;
14933 +
14934 + /* Accumulate IQ cal measures for active chains */
14935 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
14936 + ah->totalPowerMeasI[i] +=
14937 + REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
14938 + ah->totalPowerMeasQ[i] +=
14939 + REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
14940 + ah->totalIqCorrMeas[i] +=
14941 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
14942 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
14943 + "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
14944 + ah->cal_samples, i, ah->totalPowerMeasI[i],
14945 + ah->totalPowerMeasQ[i],
14946 + ah->totalIqCorrMeas[i]);
14947 + }
14948 +}
14949 +
14950 +static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
14951 +{
14952 + struct ath_common *common = ath9k_hw_common(ah);
14953 + u32 powerMeasQ, powerMeasI, iqCorrMeas;
14954 + u32 qCoffDenom, iCoffDenom;
14955 + int32_t qCoff, iCoff;
14956 + int iqCorrNeg, i;
14957 + const u_int32_t offset_array[3] = {
14958 + AR_PHY_RX_IQCAL_CORR_B0,
14959 + AR_PHY_RX_IQCAL_CORR_B1,
14960 + AR_PHY_RX_IQCAL_CORR_B2,
14961 + };
14962 +
14963 + for (i = 0; i < numChains; i++) {
14964 + powerMeasI = ah->totalPowerMeasI[i];
14965 + powerMeasQ = ah->totalPowerMeasQ[i];
14966 + iqCorrMeas = ah->totalIqCorrMeas[i];
14967 +
14968 + ath_print(common, ATH_DBG_CALIBRATE,
14969 + "Starting IQ Cal and Correction for Chain %d\n",
14970 + i);
14971 +
14972 + ath_print(common, ATH_DBG_CALIBRATE,
14973 + "Orignal: Chn %diq_corr_meas = 0x%08x\n",
14974 + i, ah->totalIqCorrMeas[i]);
14975 +
14976 + iqCorrNeg = 0;
14977 +
14978 + if (iqCorrMeas > 0x80000000) {
14979 + iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
14980 + iqCorrNeg = 1;
14981 + }
14982 +
14983 + ath_print(common, ATH_DBG_CALIBRATE,
14984 + "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
14985 + ath_print(common, ATH_DBG_CALIBRATE,
14986 + "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
14987 + ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
14988 + iqCorrNeg);
14989 +
14990 + iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
14991 + qCoffDenom = powerMeasQ / 64;
14992 +
14993 + if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
14994 + iCoff = iqCorrMeas / iCoffDenom;
14995 + qCoff = powerMeasI / qCoffDenom - 64;
14996 + ath_print(common, ATH_DBG_CALIBRATE,
14997 + "Chn %d iCoff = 0x%08x\n", i, iCoff);
14998 + ath_print(common, ATH_DBG_CALIBRATE,
14999 + "Chn %d qCoff = 0x%08x\n", i, qCoff);
15000 +
15001 + /* Force bounds on iCoff */
15002 + if (iCoff >= 63)
15003 + iCoff = 63;
15004 + else if (iCoff <= -63)
15005 + iCoff = -63;
15006 +
15007 + /* Negate iCoff if iqCorrNeg == 0 */
15008 + if (iqCorrNeg == 0x0)
15009 + iCoff = -iCoff;
15010 +
15011 + /* Force bounds on qCoff */
15012 + if (qCoff >= 63)
15013 + qCoff = 63;
15014 + else if (qCoff <= -63)
15015 + qCoff = -63;
15016 +
15017 + iCoff = iCoff & 0x7f;
15018 + qCoff = qCoff & 0x7f;
15019 +
15020 + ath_print(common, ATH_DBG_CALIBRATE,
15021 + "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
15022 + i, iCoff, qCoff);
15023 + ath_print(common, ATH_DBG_CALIBRATE,
15024 + "Register offset (0x%04x) "
15025 + "before update = 0x%x\n",
15026 + offset_array[i],
15027 + REG_READ(ah, offset_array[i]));
15028 +
15029 + REG_RMW_FIELD(ah, offset_array[i],
15030 + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
15031 + iCoff);
15032 + REG_RMW_FIELD(ah, offset_array[i],
15033 + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
15034 + qCoff);
15035 + ath_print(common, ATH_DBG_CALIBRATE,
15036 + "Register offset (0x%04x) QI COFF "
15037 + "(bitfields 0x%08x) after update = 0x%x\n",
15038 + offset_array[i],
15039 + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
15040 + REG_READ(ah, offset_array[i]));
15041 + ath_print(common, ATH_DBG_CALIBRATE,
15042 + "Register offset (0x%04x) QQ COFF "
15043 + "(bitfields 0x%08x) after update = 0x%x\n",
15044 + offset_array[i], AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
15045 + REG_READ(ah, offset_array[i]));
15046 +
15047 + ath_print(common, ATH_DBG_CALIBRATE,
15048 + "IQ Cal and Correction done for Chain %d\n",
15049 + i);
15050 + }
15051 + }
15052 +
15053 + REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
15054 + AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
15055 + ath_print(common, ATH_DBG_CALIBRATE,
15056 + "IQ Cal and Correction (offset 0x%04x) enabled "
15057 + "(bit position 0x%08x). New Value 0x%08x\n",
15058 + (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
15059 + AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
15060 + REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
15061 +}
15062 +
15063 +static const struct ath9k_percal_data iq_cal_single_sample = {
15064 + IQ_MISMATCH_CAL,
15065 + MIN_CAL_SAMPLES,
15066 + PER_MAX_LOG_COUNT,
15067 + ar9003_hw_iqcal_collect,
15068 + ar9003_hw_iqcalibrate
15069 +};
15070 +
15071 +static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
15072 +{
15073 + ah->iq_caldata.calData = &iq_cal_single_sample;
15074 + ah->supp_cals = IQ_MISMATCH_CAL;
15075 +}
15076 +
15077 +static bool ar9003_hw_iscal_supported(struct ath_hw *ah,
15078 + enum ath9k_cal_types calType)
15079 +{
15080 + switch (calType & ah->supp_cals) {
15081 + case IQ_MISMATCH_CAL:
15082 + /*
15083 + * XXX: Run IQ Mismatch for non-CCK only
15084 + * Note that CHANNEL_B is never set though.
15085 + */
15086 + return true;
15087 + case ADC_GAIN_CAL:
15088 + case ADC_DC_CAL:
15089 + return false;
15090 + case TEMP_COMP_CAL:
15091 + return true;
15092 + }
15093 +
15094 + return false;
15095 +}
15096 +
15097 +/*
15098 + * solve 4x4 linear equation used in loopback iq cal.
15099 + */
15100 +static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
15101 + s32 sin_2phi_1,
15102 + s32 cos_2phi_1,
15103 + s32 sin_2phi_2,
15104 + s32 cos_2phi_2,
15105 + s32 mag_a0_d0,
15106 + s32 phs_a0_d0,
15107 + s32 mag_a1_d0,
15108 + s32 phs_a1_d0,
15109 + s32 solved_eq[])
15110 +{
15111 + s32 f1 = cos_2phi_1 - cos_2phi_2,
15112 + f3 = sin_2phi_1 - sin_2phi_2,
15113 + f2;
15114 + s32 mag_tx, phs_tx, mag_rx, phs_rx;
15115 + const s32 result_shift = 1 << 15;
15116 + struct ath_common *common = ath9k_hw_common(ah);
15117 +
15118 + f2 = (f1 * f1 + f3 * f3) / result_shift;
15119 +
15120 + if (!f2) {
15121 + ath_print(common, ATH_DBG_CALIBRATE, "Divide by 0\n");
15122 + return false;
15123 + }
15124 +
15125 + /* mag mismatch, tx */
15126 + mag_tx = f1 * (mag_a0_d0 - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0);
15127 + /* phs mismatch, tx */
15128 + phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0);
15129 +
15130 + mag_tx = (mag_tx / f2);
15131 + phs_tx = (phs_tx / f2);
15132 +
15133 + /* mag mismatch, rx */
15134 + mag_rx = mag_a0_d0 - (cos_2phi_1 * mag_tx + sin_2phi_1 * phs_tx) /
15135 + result_shift;
15136 + /* phs mismatch, rx */
15137 + phs_rx = phs_a0_d0 + (sin_2phi_1 * mag_tx - cos_2phi_1 * phs_tx) /
15138 + result_shift;
15139 +
15140 + solved_eq[0] = mag_tx;
15141 + solved_eq[1] = phs_tx;
15142 + solved_eq[2] = mag_rx;
15143 + solved_eq[3] = phs_rx;
15144 +
15145 + return true;
15146 +}
15147 +
15148 +static s32 ar9003_hw_find_mag_approx(struct ath_hw *ah, s32 in_re, s32 in_im)
15149 +{
15150 + s32 abs_i = abs(in_re),
15151 + abs_q = abs(in_im),
15152 + max_abs, min_abs;
15153 +
15154 + if (abs_i > abs_q) {
15155 + max_abs = abs_i;
15156 + min_abs = abs_q;
15157 + } else {
15158 + max_abs = abs_q;
15159 + min_abs = abs_i;
15160 + }
15161 +
15162 + return (max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4));
15163 +}
15164 +
15165 +#define DELPT 32
15166 +
15167 +static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
15168 + s32 chain_idx,
15169 + const s32 iq_res[],
15170 + s32 iqc_coeff[])
15171 +{
15172 + s32 i2_m_q2_a0_d0, i2_p_q2_a0_d0, iq_corr_a0_d0,
15173 + i2_m_q2_a0_d1, i2_p_q2_a0_d1, iq_corr_a0_d1,
15174 + i2_m_q2_a1_d0, i2_p_q2_a1_d0, iq_corr_a1_d0,
15175 + i2_m_q2_a1_d1, i2_p_q2_a1_d1, iq_corr_a1_d1;
15176 + s32 mag_a0_d0, mag_a1_d0, mag_a0_d1, mag_a1_d1,
15177 + phs_a0_d0, phs_a1_d0, phs_a0_d1, phs_a1_d1,
15178 + sin_2phi_1, cos_2phi_1,
15179 + sin_2phi_2, cos_2phi_2;
15180 + s32 mag_tx, phs_tx, mag_rx, phs_rx;
15181 + s32 solved_eq[4], mag_corr_tx, phs_corr_tx, mag_corr_rx, phs_corr_rx,
15182 + q_q_coff, q_i_coff;
15183 + const s32 res_scale = 1 << 15;
15184 + const s32 delpt_shift = 1 << 8;
15185 + s32 mag1, mag2;
15186 + struct ath_common *common = ath9k_hw_common(ah);
15187 +
15188 + i2_m_q2_a0_d0 = iq_res[0] & 0xfff;
15189 + i2_p_q2_a0_d0 = (iq_res[0] >> 12) & 0xfff;
15190 + iq_corr_a0_d0 = ((iq_res[0] >> 24) & 0xff) + ((iq_res[1] & 0xf) << 8);
15191 +
15192 + if (i2_m_q2_a0_d0 > 0x800)
15193 + i2_m_q2_a0_d0 = -((0xfff - i2_m_q2_a0_d0) + 1);
15194 +
15195 + if (i2_p_q2_a0_d0 > 0x800)
15196 + i2_p_q2_a0_d0 = -((0xfff - i2_p_q2_a0_d0) + 1);
15197 +
15198 + if (iq_corr_a0_d0 > 0x800)
15199 + iq_corr_a0_d0 = -((0xfff - iq_corr_a0_d0) + 1);
15200 +
15201 + i2_m_q2_a0_d1 = (iq_res[1] >> 4) & 0xfff;
15202 + i2_p_q2_a0_d1 = (iq_res[2] & 0xfff);
15203 + iq_corr_a0_d1 = (iq_res[2] >> 12) & 0xfff;
15204 +
15205 + if (i2_m_q2_a0_d1 > 0x800)
15206 + i2_m_q2_a0_d1 = -((0xfff - i2_m_q2_a0_d1) + 1);
15207 +
15208 + if (i2_p_q2_a0_d1 > 0x800)
15209 + i2_p_q2_a0_d1 = -((0xfff - i2_p_q2_a0_d1) + 1);
15210 +
15211 + if (iq_corr_a0_d1 > 0x800)
15212 + iq_corr_a0_d1 = -((0xfff - iq_corr_a0_d1) + 1);
15213 +
15214 + i2_m_q2_a1_d0 = ((iq_res[2] >> 24) & 0xff) + ((iq_res[3] & 0xf) << 8);
15215 + i2_p_q2_a1_d0 = (iq_res[3] >> 4) & 0xfff;
15216 + iq_corr_a1_d0 = iq_res[4] & 0xfff;
15217 +
15218 + if (i2_m_q2_a1_d0 > 0x800)
15219 + i2_m_q2_a1_d0 = -((0xfff - i2_m_q2_a1_d0) + 1);
15220 +
15221 + if (i2_p_q2_a1_d0 > 0x800)
15222 + i2_p_q2_a1_d0 = -((0xfff - i2_p_q2_a1_d0) + 1);
15223 +
15224 + if (iq_corr_a1_d0 > 0x800)
15225 + iq_corr_a1_d0 = -((0xfff - iq_corr_a1_d0) + 1);
15226 +
15227 + i2_m_q2_a1_d1 = (iq_res[4] >> 12) & 0xfff;
15228 + i2_p_q2_a1_d1 = ((iq_res[4] >> 24) & 0xff) + ((iq_res[5] & 0xf) << 8);
15229 + iq_corr_a1_d1 = (iq_res[5] >> 4) & 0xfff;
15230 +
15231 + if (i2_m_q2_a1_d1 > 0x800)
15232 + i2_m_q2_a1_d1 = -((0xfff - i2_m_q2_a1_d1) + 1);
15233 +
15234 + if (i2_p_q2_a1_d1 > 0x800)
15235 + i2_p_q2_a1_d1 = -((0xfff - i2_p_q2_a1_d1) + 1);
15236 +
15237 + if (iq_corr_a1_d1 > 0x800)
15238 + iq_corr_a1_d1 = -((0xfff - iq_corr_a1_d1) + 1);
15239 +
15240 + if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
15241 + (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
15242 + ath_print(common, ATH_DBG_CALIBRATE,
15243 + "Divide by 0:\na0_d0=%d\n"
15244 + "a0_d1=%d\na2_d0=%d\na1_d1=%d\n",
15245 + i2_p_q2_a0_d0, i2_p_q2_a0_d1,
15246 + i2_p_q2_a1_d0, i2_p_q2_a1_d1);
15247 + return false;
15248 + }
15249 +
15250 + mag_a0_d0 = (i2_m_q2_a0_d0 * res_scale) / i2_p_q2_a0_d0;
15251 + phs_a0_d0 = (iq_corr_a0_d0 * res_scale) / i2_p_q2_a0_d0;
15252 +
15253 + mag_a0_d1 = (i2_m_q2_a0_d1 * res_scale) / i2_p_q2_a0_d1;
15254 + phs_a0_d1 = (iq_corr_a0_d1 * res_scale) / i2_p_q2_a0_d1;
15255 +
15256 + mag_a1_d0 = (i2_m_q2_a1_d0 * res_scale) / i2_p_q2_a1_d0;
15257 + phs_a1_d0 = (iq_corr_a1_d0 * res_scale) / i2_p_q2_a1_d0;
15258 +
15259 + mag_a1_d1 = (i2_m_q2_a1_d1 * res_scale) / i2_p_q2_a1_d1;
15260 + phs_a1_d1 = (iq_corr_a1_d1 * res_scale) / i2_p_q2_a1_d1;
15261 +
15262 + /* w/o analog phase shift */
15263 + sin_2phi_1 = (((mag_a0_d0 - mag_a0_d1) * delpt_shift) / DELPT);
15264 + /* w/o analog phase shift */
15265 + cos_2phi_1 = (((phs_a0_d1 - phs_a0_d0) * delpt_shift) / DELPT);
15266 + /* w/ analog phase shift */
15267 + sin_2phi_2 = (((mag_a1_d0 - mag_a1_d1) * delpt_shift) / DELPT);
15268 + /* w/ analog phase shift */
15269 + cos_2phi_2 = (((phs_a1_d1 - phs_a1_d0) * delpt_shift) / DELPT);
15270 +
15271 + /*
15272 + * force sin^2 + cos^2 = 1;
15273 + * find magnitude by approximation
15274 + */
15275 + mag1 = ar9003_hw_find_mag_approx(ah, cos_2phi_1, sin_2phi_1);
15276 + mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
15277 +
15278 + if ((mag1 == 0) || (mag2 == 0)) {
15279 + ath_print(common, ATH_DBG_CALIBRATE,
15280 + "Divide by 0: mag1=%d, mag2=%d\n",
15281 + mag1, mag2);
15282 + return false;
15283 + }
15284 +
15285 + /* normalization sin and cos by mag */
15286 + sin_2phi_1 = (sin_2phi_1 * res_scale / mag1);
15287 + cos_2phi_1 = (cos_2phi_1 * res_scale / mag1);
15288 + sin_2phi_2 = (sin_2phi_2 * res_scale / mag2);
15289 + cos_2phi_2 = (cos_2phi_2 * res_scale / mag2);
15290 +
15291 + /* calculate IQ mismatch */
15292 + if (!ar9003_hw_solve_iq_cal(ah,
15293 + sin_2phi_1, cos_2phi_1,
15294 + sin_2phi_2, cos_2phi_2,
15295 + mag_a0_d0, phs_a0_d0,
15296 + mag_a1_d0,
15297 + phs_a1_d0, solved_eq)) {
15298 + ath_print(common, ATH_DBG_CALIBRATE,
15299 + "Call to ar9003_hw_solve_iq_cal() failed.\n");
15300 + return false;
15301 + }
15302 +
15303 + mag_tx = solved_eq[0];
15304 + phs_tx = solved_eq[1];
15305 + mag_rx = solved_eq[2];
15306 + phs_rx = solved_eq[3];
15307 +
15308 + ath_print(common, ATH_DBG_CALIBRATE,
15309 + "chain %d: mag mismatch=%d phase mismatch=%d\n",
15310 + chain_idx, mag_tx/res_scale, phs_tx/res_scale);
15311 +
15312 + if (res_scale == mag_tx) {
15313 + ath_print(common, ATH_DBG_CALIBRATE,
15314 + "Divide by 0: mag_tx=%d, res_scale=%d\n",
15315 + mag_tx, res_scale);
15316 + return false;
15317 + }
15318 +
15319 + /* calculate and quantize Tx IQ correction factor */
15320 + mag_corr_tx = (mag_tx * res_scale) / (res_scale - mag_tx);
15321 + phs_corr_tx = -phs_tx;
15322 +
15323 + q_q_coff = (mag_corr_tx * 128 / res_scale);
15324 + q_i_coff = (phs_corr_tx * 256 / res_scale);
15325 +
15326 + ath_print(common, ATH_DBG_CALIBRATE,
15327 + "tx chain %d: mag corr=%d phase corr=%d\n",
15328 + chain_idx, q_q_coff, q_i_coff);
15329 +
15330 + if (q_i_coff < -63)
15331 + q_i_coff = -63;
15332 + if (q_i_coff > 63)
15333 + q_i_coff = 63;
15334 + if (q_q_coff < -63)
15335 + q_q_coff = -63;
15336 + if (q_q_coff > 63)
15337 + q_q_coff = 63;
15338 +
15339 + iqc_coeff[0] = (q_q_coff * 128) + q_i_coff;
15340 +
15341 + ath_print(common, ATH_DBG_CALIBRATE,
15342 + "tx chain %d: iq corr coeff=%x\n",
15343 + chain_idx, iqc_coeff[0]);
15344 +
15345 + if (-mag_rx == res_scale) {
15346 + ath_print(common, ATH_DBG_CALIBRATE,
15347 + "Divide by 0: mag_rx=%d, res_scale=%d\n",
15348 + mag_rx, res_scale);
15349 + return false;
15350 + }
15351 +
15352 + /* calculate and quantize Rx IQ correction factors */
15353 + mag_corr_rx = (-mag_rx * res_scale) / (res_scale + mag_rx);
15354 + phs_corr_rx = -phs_rx;
15355 +
15356 + q_q_coff = (mag_corr_rx * 128 / res_scale);
15357 + q_i_coff = (phs_corr_rx * 256 / res_scale);
15358 +
15359 + ath_print(common, ATH_DBG_CALIBRATE,
15360 + "rx chain %d: mag corr=%d phase corr=%d\n",
15361 + chain_idx, q_q_coff, q_i_coff);
15362 +
15363 + if (q_i_coff < -63)
15364 + q_i_coff = -63;
15365 + if (q_i_coff > 63)
15366 + q_i_coff = 63;
15367 + if (q_q_coff < -63)
15368 + q_q_coff = -63;
15369 + if (q_q_coff > 63)
15370 + q_q_coff = 63;
15371 +
15372 + iqc_coeff[1] = (q_q_coff * 128) + q_i_coff;
15373 +
15374 + ath_print(common, ATH_DBG_CALIBRATE,
15375 + "rx chain %d: iq corr coeff=%x\n",
15376 + chain_idx, iqc_coeff[1]);
15377 +
15378 + return true;
15379 +}
15380 +
15381 +static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
15382 +{
15383 + struct ath_common *common = ath9k_hw_common(ah);
15384 + const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
15385 + AR_PHY_TX_IQCAL_STATUS_B0,
15386 + AR_PHY_TX_IQCAL_STATUS_B1,
15387 + AR_PHY_TX_IQCAL_STATUS_B2,
15388 + };
15389 + const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = {
15390 + AR_PHY_TX_IQCAL_CORR_COEFF_01_B0,
15391 + AR_PHY_TX_IQCAL_CORR_COEFF_01_B1,
15392 + AR_PHY_TX_IQCAL_CORR_COEFF_01_B2,
15393 + };
15394 + const u32 rx_corr[AR9300_MAX_CHAINS] = {
15395 + AR_PHY_RX_IQCAL_CORR_B0,
15396 + AR_PHY_RX_IQCAL_CORR_B1,
15397 + AR_PHY_RX_IQCAL_CORR_B2,
15398 + };
15399 + const u_int32_t chan_info_tab[] = {
15400 + AR_PHY_CHAN_INFO_TAB_0,
15401 + AR_PHY_CHAN_INFO_TAB_1,
15402 + AR_PHY_CHAN_INFO_TAB_2,
15403 + };
15404 + s32 iq_res[6];
15405 + s32 iqc_coeff[2];
15406 + s32 i, j;
15407 + u32 num_chains = 0;
15408 +
15409 + for (i = 0; i < AR9300_MAX_CHAINS; i++) {
15410 + if (ah->txchainmask & (1 << i))
15411 + num_chains++;
15412 + }
15413 +
15414 + REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
15415 + AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
15416 + DELPT);
15417 + REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
15418 + AR_PHY_TX_IQCAL_START_DO_CAL,
15419 + AR_PHY_TX_IQCAL_START_DO_CAL);
15420 +
15421 + if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
15422 + AR_PHY_TX_IQCAL_START_DO_CAL,
15423 + 0, AH_WAIT_TIMEOUT)) {
15424 + ath_print(common, ATH_DBG_CALIBRATE,
15425 + "Tx IQ Cal not complete.\n");
15426 + goto TX_IQ_CAL_FAILED;
15427 + }
15428 +
15429 + for (i = 0; i < num_chains; i++) {
15430 + ath_print(common, ATH_DBG_CALIBRATE,
15431 + "Doing Tx IQ Cal for chain %d.\n", i);
15432 +
15433 + if (REG_READ(ah, txiqcal_status[i]) &
15434 + AR_PHY_TX_IQCAL_STATUS_FAILED) {
15435 + ath_print(common, ATH_DBG_CALIBRATE,
15436 + "Tx IQ Cal failed for chain %d.\n", i);
15437 + goto TX_IQ_CAL_FAILED;
15438 + }
15439 +
15440 + for (j = 0; j < 3; j++) {
15441 + u_int8_t idx = 2 * j,
15442 + offset = 4 * j;
15443 +
15444 + REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
15445 + AR_PHY_CHAN_INFO_TAB_S2_READ, 0);
15446 +
15447 + /* 32 bits */
15448 + iq_res[idx] = REG_READ(ah, chan_info_tab[i] + offset);
15449 +
15450 + REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
15451 + AR_PHY_CHAN_INFO_TAB_S2_READ, 1);
15452 +
15453 + /* 16 bits */
15454 + iq_res[idx+1] = 0xffff & REG_READ(ah, chan_info_tab[i] + offset);
15455 +
15456 + ath_print(common, ATH_DBG_CALIBRATE,
15457 + "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
15458 + idx, iq_res[idx], idx+1, iq_res[idx+1]);
15459 + }
15460 +
15461 + if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) {
15462 + ath_print(common, ATH_DBG_CALIBRATE,
15463 + "Failed in calculation of IQ correction.\n");
15464 + goto TX_IQ_CAL_FAILED;
15465 + }
15466 +
15467 + ath_print(common, ATH_DBG_CALIBRATE,
15468 + "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n",
15469 + iqc_coeff[0], iqc_coeff[1]);
15470 +
15471 + REG_RMW_FIELD(ah, tx_corr_coeff[i],
15472 + AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
15473 + iqc_coeff[0]);
15474 + REG_RMW_FIELD(ah, rx_corr[i],
15475 + AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,
15476 + iqc_coeff[1] >> 7);
15477 + REG_RMW_FIELD(ah, rx_corr[i],
15478 + AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
15479 + iqc_coeff[1]);
15480 + }
15481 +
15482 + REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
15483 + AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
15484 + REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
15485 + AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
15486 +
15487 + return;
15488 +
15489 +TX_IQ_CAL_FAILED:
15490 + ath_print(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
15491 + return;
15492 +}
15493 +
15494 +static bool ar9003_hw_init_cal(struct ath_hw *ah,
15495 + struct ath9k_channel *chan)
15496 +{
15497 + struct ath_common *common = ath9k_hw_common(ah);
15498 +
15499 + /*
15500 + * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
15501 + * running AGC/TxIQ cals
15502 + */
15503 + ar9003_hw_modify_chain_masks(ah, 0x7, 0x7);
15504 +
15505 + /* Calibrate the AGC */
15506 + REG_WRITE(ah, AR_PHY_AGC_CONTROL,
15507 + REG_READ(ah, AR_PHY_AGC_CONTROL) |
15508 + AR_PHY_AGC_CONTROL_CAL);
15509 +
15510 + /* Poll for offset calibration complete */
15511 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
15512 + 0, AH_WAIT_TIMEOUT)) {
15513 + ath_print(common, ATH_DBG_CALIBRATE,
15514 + "offset calibration failed to "
15515 + "complete in 1ms; noisy environment?\n");
15516 + return false;
15517 + }
15518 +
15519 + /* Do Tx IQ Calibration */
15520 + ar9003_hw_tx_iq_cal(ah);
15521 +
15522 + /* Revert chainmasks to their original values before NF cal */
15523 + ar9003_hw_modify_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
15524 +
15525 + /* Initialize list pointers */
15526 + ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
15527 +
15528 + if (ar9003_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
15529 + INIT_CAL(&ah->iq_caldata);
15530 + INSERT_CAL(ah, &ah->iq_caldata);
15531 + ath_print(common, ATH_DBG_CALIBRATE,
15532 + "enabling IQ Calibration.\n");
15533 + }
15534 +
15535 + if (ar9003_hw_iscal_supported(ah, TEMP_COMP_CAL)) {
15536 + INIT_CAL(&ah->tempCompCalData);
15537 + INSERT_CAL(ah, &ah->tempCompCalData);
15538 + ath_print(common, ATH_DBG_CALIBRATE,
15539 + "enabling Temperature Compensation Calibration.\n");
15540 + }
15541 +
15542 + /* Initialize current pointer to first element in list */
15543 + ah->cal_list_curr = ah->cal_list;
15544 +
15545 + if (ah->cal_list_curr)
15546 + ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
15547 +
15548 + chan->CalValid = 0;
15549 +
15550 + return true;
15551 +}
15552 +
15553 +void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
15554 +{
15555 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
15556 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
15557 +
15558 + priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
15559 + priv_ops->init_cal = ar9003_hw_init_cal;
15560 + priv_ops->setup_calibration = ar9003_hw_setup_calibration;
15561 + priv_ops->iscal_supported = ar9003_hw_iscal_supported;
15562 +
15563 + ops->calibrate = ar9003_hw_calibrate;
15564 +}
15565 diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
15566 new file mode 100644
15567 index 0000000..a3e5c70
15568 --- /dev/null
15569 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
15570 @@ -0,0 +1,1841 @@
15571 +/*
15572 + * Copyright (c) 2010 Atheros Communications Inc.
15573 + *
15574 + * Permission to use, copy, modify, and/or distribute this software for any
15575 + * purpose with or without fee is hereby granted, provided that the above
15576 + * copyright notice and this permission notice appear in all copies.
15577 + *
15578 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15579 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15580 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15581 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15582 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15583 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15584 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15585 + */
15586 +
15587 +#include "hw.h"
15588 +#include "ar9003_phy.h"
15589 +#include "ar9003_eeprom.h"
15590 +
15591 +#define COMP_HDR_LEN 4
15592 +#define COMP_CKSUM_LEN 2
15593 +
15594 +#define AR_CH0_TOP (0x00016288)
15595 +#define AR_CH0_TOP_XPABIASLVL (0x3)
15596 +#define AR_CH0_TOP_XPABIASLVL_S (8)
15597 +
15598 +#define AR_CH0_THERM (0x00016290)
15599 +#define AR_CH0_THERM_SPARE (0x3f)
15600 +#define AR_CH0_THERM_SPARE_S (0)
15601 +
15602 +#define AR_SWITCH_TABLE_COM_ALL (0xffff)
15603 +#define AR_SWITCH_TABLE_COM_ALL_S (0)
15604 +
15605 +#define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
15606 +#define AR_SWITCH_TABLE_COM2_ALL_S (0)
15607 +
15608 +#define AR_SWITCH_TABLE_ALL (0xfff)
15609 +#define AR_SWITCH_TABLE_ALL_S (0)
15610 +
15611 +static const struct ar9300_eeprom ar9300_default = {
15612 + .eepromVersion = 2,
15613 + .templateVersion = 2,
15614 + .macAddr = {1, 2, 3, 4, 5, 6},
15615 + .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15616 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
15617 + .baseEepHeader = {
15618 + .regDmn = {0, 0x1f},
15619 + .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
15620 + .opCapFlags = {
15621 + .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
15622 + .eepMisc = 0,
15623 + },
15624 + .rfSilent = 0,
15625 + .blueToothOptions = 0,
15626 + .deviceCap = 0,
15627 + .deviceType = 5, /* takes lower byte in eeprom location */
15628 + .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
15629 + .params_for_tuning_caps = {0, 0},
15630 + .featureEnable = 0x0c,
15631 + /*
15632 + * bit0 - enable tx temp comp - disabled
15633 + * bit1 - enable tx volt comp - disabled
15634 + * bit2 - enable fastClock - enabled
15635 + * bit3 - enable doubling - enabled
15636 + * bit4 - enable internal regulator - disabled
15637 + */
15638 + .miscConfiguration = 0, /* bit0 - turn down drivestrength */
15639 + .eepromWriteEnableGpio = 3,
15640 + .wlanDisableGpio = 0,
15641 + .wlanLedGpio = 8,
15642 + .rxBandSelectGpio = 0xff,
15643 + .txrxgain = 0,
15644 + .swreg = 0,
15645 + },
15646 + .modalHeader2G = {
15647 + /* ar9300_modal_eep_header 2g */
15648 + /* 4 idle,t1,t2,b(4 bits per setting) */
15649 + .antCtrlCommon = 0x110,
15650 + /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
15651 + .antCtrlCommon2 = 0x22222,
15652 +
15653 + /*
15654 + * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
15655 + * rx1, rx12, b (2 bits each)
15656 + */
15657 + .antCtrlChain = {0x150, 0x150, 0x150},
15658 +
15659 + /*
15660 + * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
15661 + * for ar9280 (0xa20c/b20c 5:0)
15662 + */
15663 + .xatten1DB = {0, 0, 0},
15664 +
15665 + /*
15666 + * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
15667 + * for ar9280 (0xa20c/b20c 16:12
15668 + */
15669 + .xatten1Margin = {0, 0, 0},
15670 + .tempSlope = 36,
15671 + .voltSlope = 0,
15672 +
15673 + /*
15674 + * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
15675 + * channels in usual fbin coding format
15676 + */
15677 + .spurChans = {0, 0, 0, 0, 0},
15678 +
15679 + /*
15680 + * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
15681 + * if the register is per chain
15682 + */
15683 + .noiseFloorThreshCh = {-1, 0, 0},
15684 + .ob = {1, 1, 1},/* 3 chain */
15685 + .db_stage2 = {1, 1, 1}, /* 3 chain */
15686 + .db_stage3 = {0, 0, 0},
15687 + .db_stage4 = {0, 0, 0},
15688 + .xpaBiasLvl = 0,
15689 + .txFrameToDataStart = 0x0e,
15690 + .txFrameToPaOn = 0x0e,
15691 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
15692 + .antennaGain = 0,
15693 + .switchSettling = 0x2c,
15694 + .adcDesiredSize = -30,
15695 + .txEndToXpaOff = 0,
15696 + .txEndToRxOn = 0x2,
15697 + .txFrameToXpaOn = 0xe,
15698 + .thresh62 = 28,
15699 + .futureModal = { /* [32] */
15700 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15701 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
15702 + },
15703 + },
15704 + .calFreqPier2G = {
15705 + FREQ2FBIN(2412, 1),
15706 + FREQ2FBIN(2437, 1),
15707 + FREQ2FBIN(2472, 1),
15708 + },
15709 + /* ar9300_cal_data_per_freq_op_loop 2g */
15710 + .calPierData2G = {
15711 + {{0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}},
15712 + {{0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}},
15713 + {{0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}},
15714 + },
15715 + .calTarget_freqbin_Cck = {
15716 + FREQ2FBIN(2412, 1),
15717 + FREQ2FBIN(2484, 1),
15718 + },
15719 + .calTarget_freqbin_2G = {
15720 + FREQ2FBIN(2412, 1),
15721 + FREQ2FBIN(2437, 1),
15722 + FREQ2FBIN(2472, 1)
15723 + },
15724 + .calTarget_freqbin_2GHT20 = {
15725 + FREQ2FBIN(2412, 1),
15726 + FREQ2FBIN(2437, 1),
15727 + FREQ2FBIN(2472, 1)
15728 + },
15729 + .calTarget_freqbin_2GHT40 = {
15730 + FREQ2FBIN(2412, 1),
15731 + FREQ2FBIN(2437, 1),
15732 + FREQ2FBIN(2472, 1)
15733 + },
15734 + .calTargetPowerCck = {
15735 + /* 1L-5L,5S,11L,11S */
15736 + {{36, 36, 36, 36}},
15737 + {{36, 36, 36, 36}},
15738 + },
15739 + .calTargetPower2G = {
15740 + /* 6-24,36,48,54 */
15741 + {{32, 32, 28, 24}},
15742 + {{32, 32, 28, 24}},
15743 + {{32, 32, 28, 24}},
15744 + },
15745 + .calTargetPower2GHT20 = {
15746 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
15747 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
15748 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
15749 + },
15750 + .calTargetPower2GHT40 = {
15751 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
15752 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
15753 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
15754 + },
15755 + .ctlIndex_2G = {
15756 + 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
15757 + 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
15758 + },
15759 + .ctl_freqbin_2G = {
15760 + {
15761 + FREQ2FBIN(2412, 1),
15762 + FREQ2FBIN(2417, 1),
15763 + FREQ2FBIN(2457, 1),
15764 + FREQ2FBIN(2462, 1)
15765 + },
15766 + {
15767 + FREQ2FBIN(2412, 1),
15768 + FREQ2FBIN(2417, 1),
15769 + FREQ2FBIN(2462, 1),
15770 + 0xFF,
15771 + },
15772 +
15773 + {
15774 + FREQ2FBIN(2412, 1),
15775 + FREQ2FBIN(2417, 1),
15776 + FREQ2FBIN(2462, 1),
15777 + 0xFF,
15778 + },
15779 + {
15780 + FREQ2FBIN(2422, 1),
15781 + FREQ2FBIN(2427, 1),
15782 + FREQ2FBIN(2447, 1),
15783 + FREQ2FBIN(2452, 1)
15784 + },
15785 +
15786 + {
15787 + /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
15788 + /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
15789 + /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
15790 + /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
15791 + },
15792 +
15793 + {
15794 + /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
15795 + /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
15796 + /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
15797 + 0,
15798 + },
15799 +
15800 + {
15801 + /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
15802 + /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
15803 + FREQ2FBIN(2472, 1),
15804 + 0,
15805 + },
15806 +
15807 + {
15808 + /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
15809 + /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
15810 + /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
15811 + /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
15812 + },
15813 +
15814 + {
15815 + /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
15816 + /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
15817 + /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
15818 + },
15819 +
15820 + {
15821 + /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
15822 + /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
15823 + /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
15824 + 0
15825 + },
15826 +
15827 + {
15828 + /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
15829 + /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
15830 + /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
15831 + 0
15832 + },
15833 +
15834 + {
15835 + /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
15836 + /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
15837 + /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
15838 + /* Data[11].ctlEdges[3].bChannel */
15839 + FREQ2FBIN(2462, 1),
15840 + }
15841 + },
15842 + .ctlPowerData_2G = {
15843 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
15844 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
15845 + {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}},
15846 +
15847 + {{{60, 1}, {60, 0}, {0, 0}, {0, 0}}},
15848 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
15849 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
15850 +
15851 + {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}},
15852 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
15853 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
15854 +
15855 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
15856 + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}},
15857 + },
15858 + .modalHeader5G = {
15859 + /* 4 idle,t1,t2,b (4 bits per setting) */
15860 + .antCtrlCommon = 0x110,
15861 + /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
15862 + .antCtrlCommon2 = 0x22222,
15863 + /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
15864 + .antCtrlChain = {
15865 + 0x000, 0x000, 0x000,
15866 + },
15867 + /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
15868 + .xatten1DB = {0, 0, 0},
15869 +
15870 + /*
15871 + * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
15872 + * for merlin (0xa20c/b20c 16:12
15873 + */
15874 + .xatten1Margin = {0, 0, 0},
15875 + .tempSlope = 68,
15876 + .voltSlope = 0,
15877 + /* spurChans spur channels in usual fbin coding format */
15878 + .spurChans = {0, 0, 0, 0, 0},
15879 + /* noiseFloorThreshCh Check if the register is per chain */
15880 + .noiseFloorThreshCh = {-1, 0, 0},
15881 + .ob = {3, 3, 3}, /* 3 chain */
15882 + .db_stage2 = {3, 3, 3}, /* 3 chain */
15883 + .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
15884 + .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
15885 + .xpaBiasLvl = 0,
15886 + .txFrameToDataStart = 0x0e,
15887 + .txFrameToPaOn = 0x0e,
15888 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
15889 + .antennaGain = 0,
15890 + .switchSettling = 0x2d,
15891 + .adcDesiredSize = -30,
15892 + .txEndToXpaOff = 0,
15893 + .txEndToRxOn = 0x2,
15894 + .txFrameToXpaOn = 0xe,
15895 + .thresh62 = 28,
15896 + .futureModal = {
15897 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15898 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
15899 + },
15900 + },
15901 + .calFreqPier5G = {
15902 + FREQ2FBIN(5180, 0),
15903 + FREQ2FBIN(5220, 0),
15904 + FREQ2FBIN(5320, 0),
15905 + FREQ2FBIN(5400, 0),
15906 + FREQ2FBIN(5500, 0),
15907 + FREQ2FBIN(5600, 0),
15908 + FREQ2FBIN(5725, 0),
15909 + FREQ2FBIN(5825, 0)
15910 + },
15911 + .calPierData5G = {
15912 + {
15913 + {0, 0, 0, 0, 0},
15914 + {0, 0, 0, 0, 0},
15915 + {0, 0, 0, 0, 0},
15916 + {0, 0, 0, 0, 0},
15917 + {0, 0, 0, 0, 0},
15918 + {0, 0, 0, 0, 0},
15919 + {0, 0, 0, 0, 0},
15920 + {0, 0, 0, 0, 0},
15921 + },
15922 + {
15923 + {0, 0, 0, 0, 0},
15924 + {0, 0, 0, 0, 0},
15925 + {0, 0, 0, 0, 0},
15926 + {0, 0, 0, 0, 0},
15927 + {0, 0, 0, 0, 0},
15928 + {0, 0, 0, 0, 0},
15929 + {0, 0, 0, 0, 0},
15930 + {0, 0, 0, 0, 0},
15931 + },
15932 + {
15933 + {0, 0, 0, 0, 0},
15934 + {0, 0, 0, 0, 0},
15935 + {0, 0, 0, 0, 0},
15936 + {0, 0, 0, 0, 0},
15937 + {0, 0, 0, 0, 0},
15938 + {0, 0, 0, 0, 0},
15939 + {0, 0, 0, 0, 0},
15940 + {0, 0, 0, 0, 0},
15941 + },
15942 +
15943 + },
15944 + .calTarget_freqbin_5G = {
15945 + FREQ2FBIN(5180, 0),
15946 + FREQ2FBIN(5220, 0),
15947 + FREQ2FBIN(5320, 0),
15948 + FREQ2FBIN(5400, 0),
15949 + FREQ2FBIN(5500, 0),
15950 + FREQ2FBIN(5600, 0),
15951 + FREQ2FBIN(5725, 0),
15952 + FREQ2FBIN(5825, 0)
15953 + },
15954 + .calTarget_freqbin_5GHT20 = {
15955 + FREQ2FBIN(5180, 0),
15956 + FREQ2FBIN(5240, 0),
15957 + FREQ2FBIN(5320, 0),
15958 + FREQ2FBIN(5500, 0),
15959 + FREQ2FBIN(5700, 0),
15960 + FREQ2FBIN(5745, 0),
15961 + FREQ2FBIN(5725, 0),
15962 + FREQ2FBIN(5825, 0)
15963 + },
15964 + .calTarget_freqbin_5GHT40 = {
15965 + FREQ2FBIN(5180, 0),
15966 + FREQ2FBIN(5240, 0),
15967 + FREQ2FBIN(5320, 0),
15968 + FREQ2FBIN(5500, 0),
15969 + FREQ2FBIN(5700, 0),
15970 + FREQ2FBIN(5745, 0),
15971 + FREQ2FBIN(5725, 0),
15972 + FREQ2FBIN(5825, 0)
15973 + },
15974 + .calTargetPower5G = {
15975 + /* 6-24,36,48,54 */
15976 + {{20, 20, 20, 10}},
15977 + {{20, 20, 20, 10}},
15978 + {{20, 20, 20, 10}},
15979 + {{20, 20, 20, 10}},
15980 + {{20, 20, 20, 10}},
15981 + {{20, 20, 20, 10}},
15982 + {{20, 20, 20, 10}},
15983 + {{20, 20, 20, 10}},
15984 + },
15985 + .calTargetPower5GHT20 = {
15986 + /*
15987 + * 0_8_16,1-3_9-11_17-19,
15988 + * 4,5,6,7,12,13,14,15,20,21,22,23
15989 + */
15990 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15991 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15992 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15993 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15994 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15995 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15996 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15997 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15998 + },
15999 + .calTargetPower5GHT40 = {
16000 + /*
16001 + * 0_8_16,1-3_9-11_17-19,
16002 + * 4,5,6,7,12,13,14,15,20,21,22,23
16003 + */
16004 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
16005 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
16006 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
16007 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
16008 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
16009 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
16010 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
16011 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
16012 + },
16013 + .ctlIndex_5G = {
16014 + 0x10, 0x16, 0x18, 0x40, 0x46,
16015 + 0x48, 0x30, 0x36, 0x38
16016 + },
16017 + .ctl_freqbin_5G = {
16018 + {
16019 + /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
16020 + /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
16021 + /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
16022 + /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
16023 + /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
16024 + /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
16025 + /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
16026 + /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
16027 + },
16028 + {
16029 + /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
16030 + /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
16031 + /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
16032 + /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
16033 + /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
16034 + /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
16035 + /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
16036 + /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
16037 + },
16038 +
16039 + {
16040 + /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
16041 + /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
16042 + /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
16043 + /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
16044 + /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
16045 + /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
16046 + /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
16047 + /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
16048 + },
16049 +
16050 + {
16051 + /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
16052 + /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
16053 + /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
16054 + /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
16055 + /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
16056 + /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
16057 + /* Data[3].ctlEdges[6].bChannel */ 0xFF,
16058 + /* Data[3].ctlEdges[7].bChannel */ 0xFF,
16059 + },
16060 +
16061 + {
16062 + /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
16063 + /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
16064 + /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
16065 + /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
16066 + /* Data[4].ctlEdges[4].bChannel */ 0xFF,
16067 + /* Data[4].ctlEdges[5].bChannel */ 0xFF,
16068 + /* Data[4].ctlEdges[6].bChannel */ 0xFF,
16069 + /* Data[4].ctlEdges[7].bChannel */ 0xFF,
16070 + },
16071 +
16072 + {
16073 + /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
16074 + /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
16075 + /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
16076 + /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
16077 + /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
16078 + /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
16079 + /* Data[5].ctlEdges[6].bChannel */ 0xFF,
16080 + /* Data[5].ctlEdges[7].bChannel */ 0xFF
16081 + },
16082 +
16083 + {
16084 + /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
16085 + /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
16086 + /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
16087 + /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
16088 + /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
16089 + /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
16090 + /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
16091 + /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
16092 + },
16093 +
16094 + {
16095 + /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
16096 + /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
16097 + /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
16098 + /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
16099 + /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
16100 + /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
16101 + /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
16102 + /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
16103 + },
16104 +
16105 + {
16106 + /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
16107 + /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
16108 + /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
16109 + /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
16110 + /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
16111 + /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
16112 + /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
16113 + /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
16114 + }
16115 + },
16116 + .ctlPowerData_5G = {
16117 + {
16118 + {
16119 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
16120 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
16121 + }
16122 + },
16123 + {
16124 + {
16125 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
16126 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
16127 + }
16128 + },
16129 + {
16130 + {
16131 + {60, 0}, {60, 1}, {60, 0}, {60, 1},
16132 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
16133 + }
16134 + },
16135 + {
16136 + {
16137 + {60, 0}, {60, 1}, {60, 1}, {60, 0},
16138 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
16139 + }
16140 + },
16141 + {
16142 + {
16143 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
16144 + {60, 0}, {60, 0}, {60, 0}, {60, 0},
16145 + }
16146 + },
16147 + {
16148 + {
16149 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
16150 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
16151 + }
16152 + },
16153 + {
16154 + {
16155 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
16156 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
16157 + }
16158 + },
16159 + {
16160 + {
16161 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
16162 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
16163 + }
16164 + },
16165 + {
16166 + {
16167 + {60, 1}, {60, 0}, {60, 1}, {60, 1},
16168 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
16169 + }
16170 + },
16171 + }
16172 +};
16173 +
16174 +static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
16175 +{
16176 + return 0;
16177 +}
16178 +
16179 +static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
16180 + enum eeprom_param param)
16181 +{
16182 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16183 + struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
16184 +
16185 + switch (param) {
16186 + case EEP_MAC_LSW:
16187 + return eep->macAddr[0] << 8 | eep->macAddr[1];
16188 + case EEP_MAC_MID:
16189 + return eep->macAddr[2] << 8 | eep->macAddr[3];
16190 + case EEP_MAC_MSW:
16191 + return eep->macAddr[4] << 8 | eep->macAddr[5];
16192 + case EEP_REG_0:
16193 + return pBase->regDmn[0];
16194 + case EEP_REG_1:
16195 + return pBase->regDmn[1];
16196 + case EEP_OP_CAP:
16197 + return pBase->deviceCap;
16198 + case EEP_OP_MODE:
16199 + return pBase->opCapFlags.opFlags;
16200 + case EEP_RF_SILENT:
16201 + return pBase->rfSilent;
16202 + case EEP_TX_MASK:
16203 + return (pBase->txrxMask >> 4) & 0xf;
16204 + case EEP_RX_MASK:
16205 + return pBase->txrxMask & 0xf;
16206 + case EEP_DRIVE_STRENGTH:
16207 +#define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
16208 + return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
16209 + case EEP_INTERNAL_REGULATOR:
16210 + /* Bit 4 is internal regulator flag */
16211 + return ((pBase->featureEnable & 0x10) >> 4);
16212 + case EEP_SWREG:
16213 + return (pBase->swreg);
16214 + default:
16215 + return 0;
16216 + }
16217 +}
16218 +
16219 +#ifdef __BIG_ENDIAN
16220 +static void ar9300_swap_eeprom(struct ar9300_eeprom *eep)
16221 +{
16222 + u32 dword;
16223 + u16 word;
16224 + int i;
16225 +
16226 + word = swab16(eep->baseEepHeader.regDmn[0]);
16227 + eep->baseEepHeader.regDmn[0] = word;
16228 +
16229 + word = swab16(eep->baseEepHeader.regDmn[1]);
16230 + eep->baseEepHeader.regDmn[1] = word;
16231 +
16232 + dword = swab32(eep->modalHeader2G.antCtrlCommon);
16233 + eep->modalHeader2G.antCtrlCommon = dword;
16234 +
16235 + dword = swab32(eep->modalHeader2G.antCtrlCommon2);
16236 + eep->modalHeader2G.antCtrlCommon2 = dword;
16237 +
16238 + dword = swab32(eep->modalHeader5G.antCtrlCommon);
16239 + eep->modalHeader5G.antCtrlCommon = dword;
16240 +
16241 + dword = swab32(eep->modalHeader5G.antCtrlCommon2);
16242 + eep->modalHeader5G.antCtrlCommon2 = dword;
16243 +
16244 + for (i = 0; i < AR9300_MAX_CHAINS; i++) {
16245 + word = swab16(eep->modalHeader2G.antCtrlChain[i]);
16246 + eep->modalHeader2G.antCtrlChain[i] = word;
16247 +
16248 + word = swab16(eep->modalHeader5G.antCtrlChain[i]);
16249 + eep->modalHeader5G.antCtrlChain[i] = word;
16250 + }
16251 +}
16252 +#endif
16253 +
16254 +static bool ar9300_hw_read_eeprom(struct ath_hw *ah,
16255 + long address, u8 * buffer, int many)
16256 +{
16257 + int i;
16258 + u8 value[2];
16259 + unsigned long eepAddr;
16260 + unsigned long byteAddr;
16261 + u16 *svalue;
16262 + struct ath_common *common = ath9k_hw_common(ah);
16263 +
16264 + if ((address < 0) || ((address + many) > AR9300_EEPROM_SIZE - 1)) {
16265 + ath_print(common, ATH_DBG_EEPROM,
16266 + "eeprom address not in range \n");
16267 + return false;
16268 + }
16269 +
16270 + for (i = 0; i < many; i++) {
16271 + eepAddr = (u16) (address + i) / 2;
16272 + byteAddr = (u16) (address + i) % 2;
16273 + svalue = (u16 *) value;
16274 + if (!ath9k_hw_nvram_read(common, eepAddr, svalue)) {
16275 + ath_print(common, ATH_DBG_EEPROM,
16276 + "unable to read eeprom region\n");
16277 + return false;
16278 + }
16279 + *svalue = le16_to_cpu(*svalue);
16280 + buffer[i] = value[byteAddr];
16281 + }
16282 +
16283 + return true;
16284 +}
16285 +
16286 +static bool ar9300_read_eeprom(struct ath_hw *ah,
16287 + int address, u8 * buffer, int many)
16288 +{
16289 + int it;
16290 +
16291 + for (it = 0; it < many; it++)
16292 + if (!ar9300_hw_read_eeprom(ah, (address - it), (buffer + it), 1))
16293 + return false;
16294 + return true;
16295 +}
16296 +
16297 +static void ar9300_comp_hdr_unpack(u8 * best, int *code, int *reference,
16298 + int *length, int *major, int *minor)
16299 +{
16300 + unsigned long value[4];
16301 +
16302 + value[0] = best[0];
16303 + value[1] = best[1];
16304 + value[2] = best[2];
16305 + value[3] = best[3];
16306 + *code = ((value[0] >> 5) & 0x0007);
16307 + *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
16308 + *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
16309 + *major = (value[2] & 0x000f);
16310 + *minor = (value[3] & 0x00ff);
16311 +}
16312 +
16313 +static u16 ar9300_comp_cksum(u8 * data, int dsize)
16314 +{
16315 + int it, checksum = 0;
16316 +
16317 + for (it = 0; it < dsize; it++) {
16318 + checksum += data[it];
16319 + checksum &= 0xffff;
16320 + }
16321 +
16322 + return checksum;
16323 +}
16324 +
16325 +static bool ar9300_uncompress_block(struct ath_hw *ah,
16326 + u8 *mptr,
16327 + int mdataSize,
16328 + u8 *block,
16329 + int size)
16330 +{
16331 + int it;
16332 + int spot;
16333 + int offset;
16334 + int length;
16335 + struct ath_common *common = ath9k_hw_common(ah);
16336 +
16337 + spot = 0;
16338 +
16339 + for (it = 0; it < size; it += (length+2)) {
16340 + offset = block[it];
16341 + offset &= 0xff;
16342 + spot += offset;
16343 + length = block[it+1];
16344 + length &= 0xff;
16345 +
16346 + if (length > 0 && spot >= 0 && spot+length < mdataSize) {
16347 + ath_print(common, ATH_DBG_EEPROM,
16348 + "Restore at %d: spot=%d offset=%d length=%d\n",
16349 + it, spot, offset, length);
16350 + memcpy(&mptr[spot],&block[it+2],length);
16351 + spot += length;
16352 + } else if (length > 0) {
16353 + ath_print(common, ATH_DBG_EEPROM,
16354 + "Bad restore at %d: spot=%d offset=%d length=%d\n",
16355 + it, spot, offset, length);
16356 + return false;
16357 + }
16358 + }
16359 + return true;
16360 +}
16361 +
16362 +static int ar9300_compress_decision(struct ath_hw *ah,
16363 + int it,
16364 + int code,
16365 + int reference,
16366 + u8 * mptr,
16367 + u8 * word, int length, int mdata_size)
16368 +{
16369 + struct ath_common *common = ath9k_hw_common(ah);
16370 + u8 *dptr;
16371 +
16372 + switch (code) {
16373 + case _CompressNone:
16374 + if (length != mdata_size) {
16375 + ath_print(common, ATH_DBG_EEPROM,
16376 + "EEPROM structure size mismatch"
16377 + "memory=%d eeprom=%d\n", mdata_size, length);
16378 + return -1;
16379 + }
16380 + memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
16381 + ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:"
16382 + " uncompressed, length %d\n", it, length);
16383 + break;
16384 + case _CompressBlock:
16385 + if (reference == 0) {
16386 + dptr = mptr;
16387 + } else {
16388 + if (reference != 2) {
16389 + ath_print(common, ATH_DBG_EEPROM,
16390 + "cant find reference eeprom"
16391 + "struct %d\n", reference);
16392 + return -1;
16393 + }
16394 + memcpy(mptr, &ar9300_default, mdata_size);
16395 + }
16396 + ath_print(common, ATH_DBG_EEPROM,
16397 + "restore eeprom %d: block, reference %d,"
16398 + " length %d\n", it, reference, length);
16399 + ar9300_uncompress_block(ah, mptr, mdata_size,
16400 + (u8 *) (word + COMP_HDR_LEN), length);
16401 + break;
16402 + default:
16403 + ath_print(common, ATH_DBG_EEPROM, "unknown compression"
16404 + " code %d\n", code);
16405 + return -1;
16406 + }
16407 + return 0;
16408 +}
16409 +
16410 +/*
16411 + * Read the configuration data from the eeprom.
16412 + * The data can be put in any specified memory buffer.
16413 + *
16414 + * Returns -1 on error.
16415 + * Returns address of next memory location on success.
16416 + */
16417 +static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
16418 + u8 * mptr, int mdata_size)
16419 +{
16420 +#define MDEFAULT 15
16421 +#define MSTATE 100
16422 + int cptr;
16423 + u8 *word;
16424 + int code;
16425 + int reference, length, major, minor;
16426 + int osize;
16427 + int it;
16428 + u16 checksum, mchecksum;
16429 + struct ath_common *common = ath9k_hw_common(ah);
16430 +
16431 + word = kzalloc(2048, GFP_KERNEL);
16432 + if (!word)
16433 + return -1;
16434 +
16435 + memcpy(mptr, &ar9300_default, mdata_size);
16436 +
16437 + cptr = AR9300_BASE_ADDR;
16438 + for (it = 0; it < MSTATE; it++) {
16439 + if (!ar9300_read_eeprom(ah, cptr, word, COMP_HDR_LEN))
16440 + goto fail;
16441 +
16442 + if ((word[0] == 0 && word[1] == 0 && word[2] == 0 &&
16443 + word[3] == 0) || (word[0] == 0xff && word[1] == 0xff
16444 + && word[2] == 0xff && word[3] == 0xff))
16445 + break;
16446 +
16447 + ar9300_comp_hdr_unpack(word, &code, &reference,
16448 + &length, &major, &minor);
16449 + ath_print(common, ATH_DBG_EEPROM,
16450 + "Found block at %x: code=%d ref=%d"
16451 + "length=%d major=%d minor=%d\n", cptr, code,
16452 + reference, length, major, minor);
16453 + if (length >= 1024) {
16454 + ath_print(common, ATH_DBG_EEPROM,
16455 + "Skipping bad header\n");
16456 + cptr -= COMP_HDR_LEN;
16457 + continue;
16458 + }
16459 +
16460 + osize = length;
16461 + ar9300_read_eeprom(ah, cptr, word,
16462 + COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
16463 + checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
16464 + mchecksum = word[COMP_HDR_LEN + osize] |
16465 + (word[COMP_HDR_LEN + osize + 1] << 8);
16466 + ath_print(common, ATH_DBG_EEPROM,
16467 + "checksum %x %x\n", checksum, mchecksum);
16468 + if (checksum == mchecksum) {
16469 + ar9300_compress_decision(ah, it, code, reference, mptr,
16470 + word, length, mdata_size);
16471 + } else {
16472 + ath_print(common, ATH_DBG_EEPROM,
16473 + "skipping block with bad checksum\n");
16474 + }
16475 + cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
16476 + }
16477 +
16478 + kfree(word);
16479 + return cptr;
16480 +
16481 +fail:
16482 + kfree(word);
16483 + return -1;
16484 +}
16485 +
16486 +/*
16487 + * Restore the configuration structure by reading the eeprom.
16488 + * This function destroys any existing in-memory structure
16489 + * content.
16490 + */
16491 +static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
16492 +{
16493 + u8 *mptr = NULL;
16494 + int mdata_size;
16495 +
16496 + mptr = (u8 *) & ah->eeprom.ar9300_eep;
16497 + mdata_size = sizeof(struct ar9300_eeprom);
16498 +
16499 + if (mptr && mdata_size > 0) {
16500 + /* At this point, mptr points to the eeprom data structure
16501 + * in it's "default" state. If this is big endian, swap the
16502 + * data structures back to "little endian"
16503 + */
16504 + /* First swap, default to Little Endian */
16505 +#ifdef __BIG_ENDIAN
16506 + ar9300_swap_eeprom((struct ar9300_eeprom *)mptr);
16507 +#endif
16508 + if (ar9300_eeprom_restore_internal(ah, mptr, mdata_size) >= 0)
16509 + return true;
16510 +
16511 + /* Second Swap, back to Big Endian */
16512 +#ifdef __BIG_ENDIAN
16513 + ar9300_swap_eeprom((struct ar9300_eeprom *)mptr);
16514 +#endif
16515 + }
16516 + return false;
16517 +}
16518 +
16519 +/* XXX: review hardware docs */
16520 +static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
16521 +{
16522 + return ah->eeprom.ar9300_eep.eepromVersion;
16523 +}
16524 +
16525 +/* XXX: could be read from the eepromVersion, not sure yet */
16526 +static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
16527 +{
16528 + return 0;
16529 +}
16530 +
16531 +static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
16532 + enum ieee80211_band freq_band)
16533 +{
16534 + return 1;
16535 +}
16536 +
16537 +static u16 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
16538 + struct ath9k_channel *chan)
16539 +{
16540 + return -EINVAL;
16541 +}
16542 +
16543 +static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
16544 +{
16545 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16546 +
16547 + if (is2ghz)
16548 + return eep->modalHeader2G.xpaBiasLvl;
16549 + else
16550 + return eep->modalHeader5G.xpaBiasLvl;
16551 +}
16552 +
16553 +static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
16554 +{
16555 + int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
16556 + REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, (bias & 0x3));
16557 + REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_SPARE,
16558 + ((bias >> 2) & 0x3));
16559 +}
16560 +
16561 +static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
16562 +{
16563 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16564 +
16565 + if (is2ghz)
16566 + return eep->modalHeader2G.antCtrlCommon;
16567 + else
16568 + return eep->modalHeader5G.antCtrlCommon;
16569 +}
16570 +
16571 +static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
16572 +{
16573 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16574 +
16575 + if (is2ghz)
16576 + return eep->modalHeader2G.antCtrlCommon2;
16577 + else
16578 + return eep->modalHeader5G.antCtrlCommon2;
16579 +}
16580 +
16581 +static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, bool is2ghz)
16582 +{
16583 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16584 +
16585 + if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
16586 + if (is2ghz)
16587 + return eep->modalHeader2G.antCtrlChain[chain];
16588 + else
16589 + return eep->modalHeader5G.antCtrlChain[chain];
16590 + }
16591 +
16592 + return 0;
16593 +}
16594 +
16595 +static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
16596 +{
16597 + u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
16598 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
16599 +
16600 + value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
16601 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
16602 +
16603 + value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
16604 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
16605 +
16606 + value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
16607 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
16608 +
16609 + value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
16610 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
16611 +}
16612 +
16613 +static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
16614 +{
16615 + int drive_strength;
16616 + unsigned long reg;
16617 +
16618 + drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
16619 +
16620 + if (!drive_strength)
16621 + return;
16622 +
16623 + reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
16624 + reg &= ~0x00ffffc0;
16625 + reg |= 0x5 << 21;
16626 + reg |= 0x5 << 18;
16627 + reg |= 0x5 << 15;
16628 + reg |= 0x5 << 12;
16629 + reg |= 0x5 << 9;
16630 + reg |= 0x5 << 6;
16631 + REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
16632 +
16633 + reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
16634 + reg &= ~0xffffffe0;
16635 + reg |= 0x5 << 29;
16636 + reg |= 0x5 << 26;
16637 + reg |= 0x5 << 23;
16638 + reg |= 0x5 << 20;
16639 + reg |= 0x5 << 17;
16640 + reg |= 0x5 << 14;
16641 + reg |= 0x5 << 11;
16642 + reg |= 0x5 << 8;
16643 + reg |= 0x5 << 5;
16644 + REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
16645 +
16646 + reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
16647 + reg &= ~0xff800000;
16648 + reg |= 0x5 << 29;
16649 + reg |= 0x5 << 26;
16650 + reg |= 0x5 << 23;
16651 + REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
16652 +}
16653 +
16654 +static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
16655 +{
16656 + int internal_regulator =
16657 + ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
16658 +
16659 + if (internal_regulator) {
16660 + /* Internal regulator is ON. Write swreg register. */
16661 + int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
16662 + REG_WRITE(ah, AR_RTC_REG_CONTROL1,
16663 + REG_READ(ah, AR_RTC_REG_CONTROL1) &
16664 + (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
16665 + REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
16666 + /* Set REG_CONTROL1.SWREG_PROGRAM */
16667 + REG_WRITE(ah, AR_RTC_REG_CONTROL1,
16668 + REG_READ(ah,
16669 + AR_RTC_REG_CONTROL1) |
16670 + AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
16671 + } else {
16672 + REG_WRITE(ah, AR_RTC_SLEEP_CLK,
16673 + (REG_READ(ah,
16674 + AR_RTC_SLEEP_CLK) |
16675 + AR_RTC_FORCE_SWREG_PRD));
16676 + }
16677 +}
16678 +
16679 +static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
16680 + struct ath9k_channel *chan)
16681 +{
16682 + ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
16683 + ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
16684 + ar9003_hw_drive_strength_apply(ah);
16685 + ar9003_hw_internal_regulator_apply(ah);
16686 +}
16687 +
16688 +static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
16689 + struct ath9k_channel *chan)
16690 +{
16691 +}
16692 +
16693 +/*
16694 + * Returns the interpolated y value corresponding to the specified x value
16695 + * from the np ordered pairs of data (px,py).
16696 + * The pairs do not have to be in any order.
16697 + * If the specified x value is less than any of the px,
16698 + * the returned y value is equal to the py for the lowest px.
16699 + * If the specified x value is greater than any of the px,
16700 + * the returned y value is equal to the py for the highest px.
16701 + */
16702 +static int ar9003_hw_power_interpolate(int32_t x,
16703 + int32_t * px, int32_t * py, u_int16_t np)
16704 +{
16705 + int ip = 0;
16706 + int lx = 0, ly = 0, lhave = 0;
16707 + int hx = 0, hy = 0, hhave = 0;
16708 + int dx = 0;
16709 + int y = 0;
16710 +
16711 + lhave = 0;
16712 + hhave = 0;
16713 +
16714 + /* identify best lower and higher x calibration measurement */
16715 + for (ip = 0; ip < np; ip++) {
16716 + dx = x - px[ip];
16717 +
16718 + /* this measurement is higher than our desired x */
16719 + if (dx <= 0) {
16720 + if (!hhave || dx > (x - hx)) {
16721 + /* new best higher x measurement */
16722 + hx = px[ip];
16723 + hy = py[ip];
16724 + hhave = 1;
16725 + }
16726 + }
16727 + /* this measurement is lower than our desired x */
16728 + if (dx >= 0) {
16729 + if (!lhave || dx < (x - lx)) {
16730 + /* new best lower x measurement */
16731 + lx = px[ip];
16732 + ly = py[ip];
16733 + lhave = 1;
16734 + }
16735 + }
16736 + }
16737 +
16738 + /* the low x is good */
16739 + if (lhave) {
16740 + /* so is the high x */
16741 + if (hhave) {
16742 + /* they're the same, so just pick one */
16743 + if (hx == lx)
16744 + y = ly;
16745 + else /* interpolate */
16746 + y = ly + (((x - lx) * (hy - ly)) / (hx - lx));
16747 + } else /* only low is good, use it */
16748 + y = ly;
16749 + } else if (hhave) /* only high is good, use it */
16750 + y = hy;
16751 + else /* nothing is good,this should never happen unless np=0, ???? */
16752 + y = -(1 << 30);
16753 + return y;
16754 +}
16755 +
16756 +static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
16757 + u16 rateIndex, u16 freq, bool is2GHz)
16758 +{
16759 + u16 numPiers, i;
16760 + s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
16761 + s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
16762 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16763 + struct cal_tgt_pow_legacy *pEepromTargetPwr;
16764 + u8 *pFreqBin;
16765 +
16766 + if (is2GHz) {
16767 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
16768 + pEepromTargetPwr = eep->calTargetPower2G;
16769 + pFreqBin = eep->calTarget_freqbin_2G;
16770 + } else {
16771 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
16772 + pEepromTargetPwr = eep->calTargetPower5G;
16773 + pFreqBin = eep->calTarget_freqbin_5G;
16774 + }
16775 +
16776 + /*
16777 + * create array of channels and targetpower from
16778 + * targetpower piers stored on eeprom
16779 + */
16780 + for (i = 0; i < numPiers; i++) {
16781 + freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
16782 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
16783 + }
16784 +
16785 + /* interpolate to get target power for given frequency */
16786 + return ((u8) ar9003_hw_power_interpolate((s32) freq,
16787 + freqArray,
16788 + targetPowerArray, numPiers));
16789 +}
16790 +
16791 +static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
16792 + u16 rateIndex,
16793 + u16 freq, bool is2GHz)
16794 +{
16795 + u16 numPiers, i;
16796 + s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
16797 + s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
16798 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16799 + struct cal_tgt_pow_ht *pEepromTargetPwr;
16800 + u8 *pFreqBin;
16801 +
16802 + if (is2GHz) {
16803 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
16804 + pEepromTargetPwr = eep->calTargetPower2GHT20;
16805 + pFreqBin = eep->calTarget_freqbin_2GHT20;
16806 + } else {
16807 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
16808 + pEepromTargetPwr = eep->calTargetPower5GHT20;
16809 + pFreqBin = eep->calTarget_freqbin_5GHT20;
16810 + }
16811 +
16812 + /*
16813 + * create array of channels and targetpower
16814 + * from targetpower piers stored on eeprom
16815 + */
16816 + for (i = 0; i < numPiers; i++) {
16817 + freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
16818 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
16819 + }
16820 +
16821 + /* interpolate to get target power for given frequency */
16822 + return ((u8) ar9003_hw_power_interpolate((s32) freq,
16823 + freqArray,
16824 + targetPowerArray, numPiers));
16825 +}
16826 +
16827 +static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
16828 + u16 rateIndex,
16829 + u16 freq, bool is2GHz)
16830 +{
16831 + u16 numPiers, i;
16832 + s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
16833 + s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
16834 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16835 + struct cal_tgt_pow_ht *pEepromTargetPwr;
16836 + u8 *pFreqBin;
16837 +
16838 + if (is2GHz) {
16839 + numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
16840 + pEepromTargetPwr = eep->calTargetPower2GHT40;
16841 + pFreqBin = eep->calTarget_freqbin_2GHT40;
16842 + } else {
16843 + numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
16844 + pEepromTargetPwr = eep->calTargetPower5GHT40;
16845 + pFreqBin = eep->calTarget_freqbin_5GHT40;
16846 + }
16847 +
16848 + /*
16849 + * create array of channels and targetpower from
16850 + * targetpower piers stored on eeprom
16851 + */
16852 + for (i = 0; i < numPiers; i++) {
16853 + freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
16854 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
16855 + }
16856 +
16857 + /* interpolate to get target power for given frequency */
16858 + return ((u8) ar9003_hw_power_interpolate((s32) freq,
16859 + freqArray,
16860 + targetPowerArray, numPiers));
16861 +}
16862 +
16863 +static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
16864 + u16 rateIndex, u16 freq)
16865 +{
16866 + u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
16867 + s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
16868 + s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
16869 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16870 + struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
16871 + u8 *pFreqBin = eep->calTarget_freqbin_Cck;
16872 +
16873 + /*
16874 + * create array of channels and targetpower from
16875 + * targetpower piers stored on eeprom
16876 + */
16877 + for (i = 0; i < numPiers; i++) {
16878 + freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
16879 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
16880 + }
16881 +
16882 + /* interpolate to get target power for given frequency */
16883 + return ((u8) ar9003_hw_power_interpolate((s32) freq,
16884 + freqArray,
16885 + targetPowerArray, numPiers));
16886 +}
16887 +
16888 +/* Set tx power registers to array of values passed in */
16889 +static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
16890 +{
16891 +#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
16892 + /* make sure forced gain is not set */
16893 + REG_WRITE(ah, 0xa458, 0);
16894 +
16895 + /* Write the OFDM power per rate set */
16896 +
16897 + /* 6 (LSB), 9, 12, 18 (MSB) */
16898 + REG_WRITE(ah, 0xa3c0,
16899 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
16900 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
16901 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
16902 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
16903 +
16904 + /* 24 (LSB), 36, 48, 54 (MSB) */
16905 + REG_WRITE(ah, 0xa3c4,
16906 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
16907 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
16908 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
16909 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
16910 +
16911 + /* Write the CCK power per rate set */
16912 +
16913 + /* 1L (LSB), reserved, 2L, 2S (MSB) */
16914 + REG_WRITE(ah, 0xa3c8,
16915 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
16916 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
16917 + // POW_SM(txPowerTimes2, 8) | /* this is reserved for AR9003 */
16918 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
16919 +
16920 + /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
16921 + REG_WRITE(ah, 0xa3cc,
16922 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
16923 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
16924 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
16925 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
16926 + );
16927 +
16928 + /* Write the HT20 power per rate set */
16929 +
16930 + /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
16931 + REG_WRITE(ah, 0xa3d0,
16932 + POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
16933 + POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
16934 + POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
16935 + POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
16936 + );
16937 +
16938 + /* 6 (LSB), 7, 12, 13 (MSB) */
16939 + REG_WRITE(ah, 0xa3d4,
16940 + POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
16941 + POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
16942 + POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
16943 + POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
16944 + );
16945 +
16946 + /* 14 (LSB), 15, 20, 21 */
16947 + REG_WRITE(ah, 0xa3e4,
16948 + POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
16949 + POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
16950 + POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
16951 + POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
16952 + );
16953 +
16954 + /* Mixed HT20 and HT40 rates */
16955 +
16956 + /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
16957 + REG_WRITE(ah, 0xa3e8,
16958 + POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
16959 + POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
16960 + POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
16961 + POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
16962 + );
16963 +
16964 + /* Write the HT40 power per rate set */
16965 + // correct PAR difference between HT40 and HT20/LEGACY
16966 + /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
16967 + REG_WRITE(ah, 0xa3d8,
16968 + POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
16969 + POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
16970 + POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
16971 + POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
16972 + );
16973 +
16974 + /* 6 (LSB), 7, 12, 13 (MSB) */
16975 + REG_WRITE(ah, 0xa3dc,
16976 + POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
16977 + POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
16978 + POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
16979 + POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
16980 + );
16981 +
16982 + /* 14 (LSB), 15, 20, 21 */
16983 + REG_WRITE(ah, 0xa3ec,
16984 + POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
16985 + POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
16986 + POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
16987 + POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
16988 + );
16989 +
16990 + return 0;
16991 +#undef POW_SM
16992 +}
16993 +
16994 +static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq)
16995 +{
16996 + u8 targetPowerValT2[ar9300RateSize];
16997 + /* XXX: hard code for now, need to get from eeprom struct */
16998 + u8 ht40PowerIncForPdadc = 0;
16999 + bool is2GHz = false;
17000 + unsigned int i = 0;
17001 + struct ath_common *common = ath9k_hw_common(ah);
17002 +
17003 + if (freq < 4000)
17004 + is2GHz = true;
17005 +
17006 + targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
17007 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
17008 + is2GHz);
17009 + targetPowerValT2[ALL_TARGET_LEGACY_36] =
17010 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
17011 + is2GHz);
17012 + targetPowerValT2[ALL_TARGET_LEGACY_48] =
17013 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
17014 + is2GHz);
17015 + targetPowerValT2[ALL_TARGET_LEGACY_54] =
17016 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
17017 + is2GHz);
17018 + targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
17019 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
17020 + freq);
17021 + targetPowerValT2[ALL_TARGET_LEGACY_5S] =
17022 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
17023 + targetPowerValT2[ALL_TARGET_LEGACY_11L] =
17024 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
17025 + targetPowerValT2[ALL_TARGET_LEGACY_11S] =
17026 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
17027 + targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
17028 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
17029 + is2GHz);
17030 + targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
17031 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
17032 + freq, is2GHz);
17033 + targetPowerValT2[ALL_TARGET_HT20_4] =
17034 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
17035 + is2GHz);
17036 + targetPowerValT2[ALL_TARGET_HT20_5] =
17037 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
17038 + is2GHz);
17039 + targetPowerValT2[ALL_TARGET_HT20_6] =
17040 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
17041 + is2GHz);
17042 + targetPowerValT2[ALL_TARGET_HT20_7] =
17043 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
17044 + is2GHz);
17045 + targetPowerValT2[ALL_TARGET_HT20_12] =
17046 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
17047 + is2GHz);
17048 + targetPowerValT2[ALL_TARGET_HT20_13] =
17049 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
17050 + is2GHz);
17051 + targetPowerValT2[ALL_TARGET_HT20_14] =
17052 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
17053 + is2GHz);
17054 + targetPowerValT2[ALL_TARGET_HT20_15] =
17055 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
17056 + is2GHz);
17057 + targetPowerValT2[ALL_TARGET_HT20_20] =
17058 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
17059 + is2GHz);
17060 + targetPowerValT2[ALL_TARGET_HT20_21] =
17061 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
17062 + is2GHz);
17063 + targetPowerValT2[ALL_TARGET_HT20_22] =
17064 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
17065 + is2GHz);
17066 + targetPowerValT2[ALL_TARGET_HT20_23] =
17067 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
17068 + is2GHz);
17069 + targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
17070 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
17071 + is2GHz) + ht40PowerIncForPdadc;
17072 + targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
17073 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
17074 + freq,
17075 + is2GHz) + ht40PowerIncForPdadc;
17076 + targetPowerValT2[ALL_TARGET_HT40_4] =
17077 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
17078 + is2GHz) + ht40PowerIncForPdadc;
17079 + targetPowerValT2[ALL_TARGET_HT40_5] =
17080 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
17081 + is2GHz) + ht40PowerIncForPdadc;
17082 + targetPowerValT2[ALL_TARGET_HT40_6] =
17083 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
17084 + is2GHz) + ht40PowerIncForPdadc;
17085 + targetPowerValT2[ALL_TARGET_HT40_7] =
17086 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
17087 + is2GHz) + ht40PowerIncForPdadc;
17088 + targetPowerValT2[ALL_TARGET_HT40_12] =
17089 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
17090 + is2GHz) + ht40PowerIncForPdadc;
17091 + targetPowerValT2[ALL_TARGET_HT40_13] =
17092 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
17093 + is2GHz) + ht40PowerIncForPdadc;
17094 + targetPowerValT2[ALL_TARGET_HT40_14] =
17095 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
17096 + is2GHz) + ht40PowerIncForPdadc;
17097 + targetPowerValT2[ALL_TARGET_HT40_15] =
17098 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
17099 + is2GHz) + ht40PowerIncForPdadc;
17100 + targetPowerValT2[ALL_TARGET_HT40_20] =
17101 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
17102 + is2GHz) + ht40PowerIncForPdadc;
17103 + targetPowerValT2[ALL_TARGET_HT40_21] =
17104 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
17105 + is2GHz) + ht40PowerIncForPdadc;
17106 + targetPowerValT2[ALL_TARGET_HT40_22] =
17107 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
17108 + is2GHz) + ht40PowerIncForPdadc;
17109 + targetPowerValT2[ALL_TARGET_HT40_23] =
17110 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
17111 + is2GHz) + ht40PowerIncForPdadc;
17112 +
17113 + while (i < ar9300RateSize) {
17114 + ath_print(common, ATH_DBG_EEPROM,
17115 + "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
17116 + i++;
17117 +
17118 + ath_print(common, ATH_DBG_EEPROM,
17119 + "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
17120 + i++;
17121 +
17122 + ath_print(common, ATH_DBG_EEPROM,
17123 + "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
17124 + i++;
17125 +
17126 + ath_print(common, ATH_DBG_EEPROM,
17127 + "TPC[%02d] 0x%08x \n", i, targetPowerValT2[i]);
17128 + i++;
17129 + }
17130 +
17131 + /* Write target power array to registers */
17132 + ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
17133 +}
17134 +
17135 +static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
17136 + int mode,
17137 + int ipier,
17138 + int ichain,
17139 + int *pfrequency,
17140 + int *pcorrection,
17141 + int *ptemperature, int *pvoltage)
17142 +{
17143 + u8 *pCalPier;
17144 + struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
17145 + int is2GHz;
17146 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
17147 + struct ath_common *common = ath9k_hw_common(ah);
17148 +
17149 + if (ichain >= AR9300_MAX_CHAINS) {
17150 + ath_print(common, ATH_DBG_EEPROM,
17151 + "Invalid chain index, must be less than %d\n",
17152 + AR9300_MAX_CHAINS);
17153 + return -1;
17154 + }
17155 +
17156 + if (mode) { /* 5GHz */
17157 + if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
17158 + ath_print(common, ATH_DBG_EEPROM,
17159 + "Invalid 5GHz cal pier index, must be less than %d\n",
17160 + AR9300_NUM_5G_CAL_PIERS);
17161 + return -1;
17162 + }
17163 + pCalPier = &(eep->calFreqPier5G[ipier]);
17164 + pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
17165 + is2GHz = 0;
17166 + } else {
17167 + if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
17168 + ath_print(common, ATH_DBG_EEPROM,
17169 + "Invalid 2GHz cal pier index, must "
17170 + "be less than %d\n", AR9300_NUM_2G_CAL_PIERS);
17171 + return -1;
17172 + }
17173 +
17174 + pCalPier = &(eep->calFreqPier2G[ipier]);
17175 + pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
17176 + is2GHz = 1;
17177 + }
17178 +
17179 + *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
17180 + *pcorrection = pCalPierStruct->refPower;
17181 + *ptemperature = pCalPierStruct->tempMeas;
17182 + *pvoltage = pCalPierStruct->voltMeas;
17183 +
17184 + return 0;
17185 +}
17186 +
17187 +static int ar9003_hw_power_control_override(struct ath_hw *ah,
17188 + int frequency,
17189 + int *correction,
17190 + int *voltage, int *temperature)
17191 +{
17192 + int tempSlope = 0;
17193 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
17194 +
17195 + REG_RMW(ah, AR_PHY_TPC_11_B0,
17196 + (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
17197 + AR_PHY_TPC_OLPC_GAIN_DELTA);
17198 + REG_RMW(ah, AR_PHY_TPC_11_B1,
17199 + (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
17200 + AR_PHY_TPC_OLPC_GAIN_DELTA);
17201 + REG_RMW(ah, AR_PHY_TPC_11_B2,
17202 + (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
17203 + AR_PHY_TPC_OLPC_GAIN_DELTA);
17204 +
17205 + /* enable open loop power control on chip */
17206 + REG_RMW(ah, AR_PHY_TPC_6_B0,
17207 + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
17208 + AR_PHY_TPC_6_ERROR_EST_MODE);
17209 + REG_RMW(ah, AR_PHY_TPC_6_B1,
17210 + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
17211 + AR_PHY_TPC_6_ERROR_EST_MODE);
17212 + REG_RMW(ah, AR_PHY_TPC_6_B2,
17213 + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
17214 + AR_PHY_TPC_6_ERROR_EST_MODE);
17215 +
17216 + /*
17217 + * enable temperature compensation
17218 + * Need to use register names
17219 + */
17220 + if (frequency < 4000)
17221 + tempSlope = eep->modalHeader2G.tempSlope;
17222 + else
17223 + tempSlope = eep->modalHeader5G.tempSlope;
17224 +
17225 + REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
17226 + REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
17227 + temperature[0]);
17228 +
17229 + return 0;
17230 +}
17231 +
17232 +/* Apply the recorded correction values. */
17233 +static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
17234 +{
17235 + int ichain, ipier, npier;
17236 + int mode;
17237 + int lfrequency[AR9300_MAX_CHAINS],
17238 + lcorrection[AR9300_MAX_CHAINS],
17239 + ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
17240 + int hfrequency[AR9300_MAX_CHAINS],
17241 + hcorrection[AR9300_MAX_CHAINS],
17242 + htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
17243 + int fdiff;
17244 + int correction[AR9300_MAX_CHAINS],
17245 + voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
17246 + int pfrequency, pcorrection, ptemperature, pvoltage;
17247 + struct ath_common *common = ath9k_hw_common(ah);
17248 +
17249 + mode = (frequency >= 4000);
17250 + if (mode)
17251 + npier = AR9300_NUM_5G_CAL_PIERS;
17252 + else
17253 + npier = AR9300_NUM_2G_CAL_PIERS;
17254 +
17255 + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
17256 + lfrequency[ichain] = 0;
17257 + hfrequency[ichain] = 100000;
17258 + }
17259 + /* identify best lower and higher frequency calibration measurement */
17260 + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
17261 + for (ipier = 0; ipier < npier; ipier++) {
17262 + if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
17263 + &pfrequency, &pcorrection,
17264 + &ptemperature, &pvoltage)) {
17265 + fdiff = frequency - pfrequency;
17266 +
17267 + /*
17268 + * this measurement is higher than
17269 + * our desired frequency
17270 + */
17271 + if (fdiff <= 0) {
17272 + if (hfrequency[ichain] <= 0 ||
17273 + hfrequency[ichain] >= 100000 ||
17274 + fdiff >
17275 + (frequency - hfrequency[ichain])) {
17276 + /* new best higher frequency measurement */
17277 + hfrequency[ichain] = pfrequency;
17278 + hcorrection[ichain] =
17279 + pcorrection;
17280 + htemperature[ichain] =
17281 + ptemperature;
17282 + hvoltage[ichain] = pvoltage;
17283 + }
17284 + }
17285 + if (fdiff >= 0) {
17286 + if (lfrequency[ichain] <= 0
17287 + || fdiff <
17288 + (frequency - lfrequency[ichain])) {
17289 + /* new best lower frequency measurement */
17290 + lfrequency[ichain] = pfrequency;
17291 + lcorrection[ichain] =
17292 + pcorrection;
17293 + ltemperature[ichain] =
17294 + ptemperature;
17295 + lvoltage[ichain] = pvoltage;
17296 + }
17297 + }
17298 + }
17299 + }
17300 + }
17301 +
17302 + /* interpolate */
17303 + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
17304 + ath_print(common, ATH_DBG_EEPROM,
17305 + "ch=%d f=%d low=%d %d h=%d %d\n",
17306 + ichain, frequency, lfrequency[ichain],
17307 + lcorrection[ichain], hfrequency[ichain],
17308 + hcorrection[ichain]);
17309 + /* they're the same, so just pick one */
17310 + if (hfrequency[ichain] == lfrequency[ichain]) {
17311 + correction[ichain] = lcorrection[ichain];
17312 + voltage[ichain] = lvoltage[ichain];
17313 + temperature[ichain] = ltemperature[ichain];
17314 + }
17315 + /* the low frequency is good */
17316 + else if (frequency - lfrequency[ichain] < 1000) {
17317 + /* so is the high frequency, interpolate */
17318 + if (hfrequency[ichain] - frequency < 1000) {
17319 +
17320 + correction[ichain] = lcorrection[ichain] +
17321 + (((frequency - lfrequency[ichain]) *
17322 + (hcorrection[ichain] -
17323 + lcorrection[ichain])) /
17324 + (hfrequency[ichain] - lfrequency[ichain]));
17325 +
17326 + temperature[ichain] = ltemperature[ichain] +
17327 + (((frequency - lfrequency[ichain]) *
17328 + (htemperature[ichain] -
17329 + ltemperature[ichain])) /
17330 + (hfrequency[ichain] - lfrequency[ichain]));
17331 +
17332 + voltage[ichain] =
17333 + lvoltage[ichain] +
17334 + (((frequency -
17335 + lfrequency[ichain]) * (hvoltage[ichain] -
17336 + lvoltage[ichain]))
17337 + / (hfrequency[ichain] -
17338 + lfrequency[ichain]));
17339 + }
17340 + /* only low is good, use it */
17341 + else {
17342 + correction[ichain] = lcorrection[ichain];
17343 + temperature[ichain] = ltemperature[ichain];
17344 + voltage[ichain] = lvoltage[ichain];
17345 + }
17346 + }
17347 + /* only high is good, use it */
17348 + else if (hfrequency[ichain] - frequency < 1000) {
17349 + correction[ichain] = hcorrection[ichain];
17350 + temperature[ichain] = htemperature[ichain];
17351 + voltage[ichain] = hvoltage[ichain];
17352 + } else { /* nothing is good, presume 0???? */
17353 + correction[ichain] = 0;
17354 + temperature[ichain] = 0;
17355 + voltage[ichain] = 0;
17356 + }
17357 + }
17358 +
17359 + ar9003_hw_power_control_override(ah, frequency, correction, voltage,
17360 + temperature);
17361 +
17362 + ath_print(common, ATH_DBG_EEPROM,
17363 + "for frequency=%d, calibration correction = %d %d %d\n",
17364 + frequency, correction[0], correction[1], correction[2]);
17365 +
17366 + return 0;
17367 +}
17368 +
17369 +static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
17370 + struct ath9k_channel *chan, u16 cfgCtl,
17371 + u8 twiceAntennaReduction,
17372 + u8 twiceMaxRegulatoryPower,
17373 + u8 powerLimit)
17374 +{
17375 + ar9003_hw_set_target_power_eeprom(ah, chan->channel);
17376 + ar9003_hw_calibration_apply(ah, chan->channel);
17377 +}
17378 +
17379 +static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
17380 + u16 i, bool is2GHz)
17381 +{
17382 + return AR_NO_SPUR;
17383 +}
17384 +
17385 +s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
17386 +{
17387 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
17388 +
17389 + return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
17390 +}
17391 +
17392 +s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
17393 +{
17394 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
17395 +
17396 + return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
17397 +}
17398 +
17399 +const struct eeprom_ops eep_ar9300_ops = {
17400 + .check_eeprom = ath9k_hw_ar9300_check_eeprom,
17401 + .get_eeprom = ath9k_hw_ar9300_get_eeprom,
17402 + .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
17403 + .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
17404 + .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
17405 + .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
17406 + .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
17407 + .set_board_values = ath9k_hw_ar9300_set_board_values,
17408 + .set_addac = ath9k_hw_ar9300_set_addac,
17409 + .set_txpower = ath9k_hw_ar9300_set_txpower,
17410 + .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
17411 +};
17412 diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
17413 new file mode 100644
17414 index 0000000..c3e330a
17415 --- /dev/null
17416 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
17417 @@ -0,0 +1,323 @@
17418 +#ifndef AR9003_EEPROM_H
17419 +#define AR9003_EEPROM_H
17420 +
17421 +#include <linux/types.h>
17422 +
17423 +#define AR9300_EEP_VER 0xD000
17424 +#define AR9300_EEP_VER_MINOR_MASK 0xFFF
17425 +#define AR9300_EEP_MINOR_VER_1 0x1
17426 +#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
17427 +
17428 +// 16-bit offset location start of calibration struct
17429 +#define AR9300_EEP_START_LOC 256
17430 +#define AR9300_NUM_5G_CAL_PIERS 8
17431 +#define AR9300_NUM_2G_CAL_PIERS 3
17432 +#define AR9300_NUM_5G_20_TARGET_POWERS 8
17433 +#define AR9300_NUM_5G_40_TARGET_POWERS 8
17434 +#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
17435 +#define AR9300_NUM_2G_20_TARGET_POWERS 3
17436 +#define AR9300_NUM_2G_40_TARGET_POWERS 3
17437 +//#define AR9300_NUM_CTLS 21
17438 +#define AR9300_NUM_CTLS_5G 9
17439 +#define AR9300_NUM_CTLS_2G 12
17440 +#define AR9300_CTL_MODE_M 0xF
17441 +#define AR9300_NUM_BAND_EDGES_5G 8
17442 +#define AR9300_NUM_BAND_EDGES_2G 4
17443 +#define AR9300_NUM_PD_GAINS 4
17444 +#define AR9300_PD_GAINS_IN_MASK 4
17445 +#define AR9300_PD_GAIN_ICEPTS 5
17446 +#define AR9300_EEPROM_MODAL_SPURS 5
17447 +#define AR9300_MAX_RATE_POWER 63
17448 +#define AR9300_NUM_PDADC_VALUES 128
17449 +#define AR9300_NUM_RATES 16
17450 +#define AR9300_BCHAN_UNUSED 0xFF
17451 +#define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64
17452 +#define AR9300_OPFLAGS_11A 0x01
17453 +#define AR9300_OPFLAGS_11G 0x02
17454 +#define AR9300_OPFLAGS_5G_HT40 0x04
17455 +#define AR9300_OPFLAGS_2G_HT40 0x08
17456 +#define AR9300_OPFLAGS_5G_HT20 0x10
17457 +#define AR9300_OPFLAGS_2G_HT20 0x20
17458 +#define AR9300_EEPMISC_BIG_ENDIAN 0x01
17459 +#define AR9300_EEPMISC_WOW 0x02
17460 +#define AR9300_CUSTOMER_DATA_SIZE 20
17461 +
17462 +#define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
17463 +#define FBIN2FREQ(x,y) ((y) ? (2300 + x) : (4800 + 5 * x))
17464 +#define AR9300_MAX_CHAINS 3
17465 +#define AR9300_ANT_16S 25
17466 +#define AR9300_FUTURE_MODAL_SZ 6
17467 +
17468 +#define AR9300_NUM_ANT_CHAIN_FIELDS 7
17469 +#define AR9300_NUM_ANT_COMMON_FIELDS 4
17470 +#define AR9300_SIZE_ANT_CHAIN_FIELD 3
17471 +#define AR9300_SIZE_ANT_COMMON_FIELD 4
17472 +#define AR9300_ANT_CHAIN_MASK 0x7
17473 +#define AR9300_ANT_COMMON_MASK 0xf
17474 +#define AR9300_CHAIN_0_IDX 0
17475 +#define AR9300_CHAIN_1_IDX 1
17476 +#define AR9300_CHAIN_2_IDX 2
17477 +
17478 +#define AR928X_NUM_ANT_CHAIN_FIELDS 6
17479 +#define AR928X_SIZE_ANT_CHAIN_FIELD 2
17480 +#define AR928X_ANT_CHAIN_MASK 0x3
17481 +
17482 +/* Delta from which to start power to pdadc table */
17483 +/* This offset is used in both open loop and closed loop power control
17484 + * schemes. In open loop power control, it is not really needed, but for
17485 + * the "sake of consistency" it was kept. For certain AP designs, this
17486 + * value is overwritten by the value in the flag "pwrTableOffset" just
17487 + * before writing the pdadc vs pwr into the chip registers.
17488 + */
17489 +#define AR9300_PWR_TABLE_OFFSET 0
17490 +
17491 +/* enable flags for voltage and temp compensation */
17492 +#define ENABLE_TEMP_COMPENSATION 0x01
17493 +#define ENABLE_VOLT_COMPENSATION 0x02
17494 +/* byte addressable */
17495 +#define AR9300_EEPROM_SIZE 16*1024
17496 +#define FIXED_CCA_THRESHOLD 15
17497 +
17498 +#define AR9300_BASE_ADDR 0x3ff
17499 +
17500 +enum targetPowerHTRates {
17501 + HT_TARGET_RATE_0_8_16,
17502 + HT_TARGET_RATE_1_3_9_11_17_19,
17503 + HT_TARGET_RATE_4,
17504 + HT_TARGET_RATE_5,
17505 + HT_TARGET_RATE_6,
17506 + HT_TARGET_RATE_7,
17507 + HT_TARGET_RATE_12,
17508 + HT_TARGET_RATE_13,
17509 + HT_TARGET_RATE_14,
17510 + HT_TARGET_RATE_15,
17511 + HT_TARGET_RATE_20,
17512 + HT_TARGET_RATE_21,
17513 + HT_TARGET_RATE_22,
17514 + HT_TARGET_RATE_23
17515 +};
17516 +
17517 +enum targetPowerLegacyRates {
17518 + LEGACY_TARGET_RATE_6_24,
17519 + LEGACY_TARGET_RATE_36,
17520 + LEGACY_TARGET_RATE_48,
17521 + LEGACY_TARGET_RATE_54
17522 +};
17523 +
17524 +enum targetPowerCckRates {
17525 + LEGACY_TARGET_RATE_1L_5L,
17526 + LEGACY_TARGET_RATE_5S,
17527 + LEGACY_TARGET_RATE_11L,
17528 + LEGACY_TARGET_RATE_11S
17529 +};
17530 +
17531 +enum ar9300_Rates {
17532 + ALL_TARGET_LEGACY_6_24,
17533 + ALL_TARGET_LEGACY_36,
17534 + ALL_TARGET_LEGACY_48,
17535 + ALL_TARGET_LEGACY_54,
17536 + ALL_TARGET_LEGACY_1L_5L,
17537 + ALL_TARGET_LEGACY_5S,
17538 + ALL_TARGET_LEGACY_11L,
17539 + ALL_TARGET_LEGACY_11S,
17540 + ALL_TARGET_HT20_0_8_16,
17541 + ALL_TARGET_HT20_1_3_9_11_17_19,
17542 + ALL_TARGET_HT20_4,
17543 + ALL_TARGET_HT20_5,
17544 + ALL_TARGET_HT20_6,
17545 + ALL_TARGET_HT20_7,
17546 + ALL_TARGET_HT20_12,
17547 + ALL_TARGET_HT20_13,
17548 + ALL_TARGET_HT20_14,
17549 + ALL_TARGET_HT20_15,
17550 + ALL_TARGET_HT20_20,
17551 + ALL_TARGET_HT20_21,
17552 + ALL_TARGET_HT20_22,
17553 + ALL_TARGET_HT20_23,
17554 + ALL_TARGET_HT40_0_8_16,
17555 + ALL_TARGET_HT40_1_3_9_11_17_19,
17556 + ALL_TARGET_HT40_4,
17557 + ALL_TARGET_HT40_5,
17558 + ALL_TARGET_HT40_6,
17559 + ALL_TARGET_HT40_7,
17560 + ALL_TARGET_HT40_12,
17561 + ALL_TARGET_HT40_13,
17562 + ALL_TARGET_HT40_14,
17563 + ALL_TARGET_HT40_15,
17564 + ALL_TARGET_HT40_20,
17565 + ALL_TARGET_HT40_21,
17566 + ALL_TARGET_HT40_22,
17567 + ALL_TARGET_HT40_23,
17568 + ar9300RateSize,
17569 +};
17570 +
17571 +
17572 +struct eepFlags {
17573 + u8 opFlags;
17574 + u8 eepMisc;
17575 +} __packed;
17576 +
17577 +enum CompressAlgorithm {
17578 + _CompressNone = 0,
17579 + _CompressLzma,
17580 + _CompressPairs,
17581 + _CompressBlock,
17582 + _Compress4,
17583 + _Compress5,
17584 + _Compress6,
17585 + _Compress7,
17586 +};
17587 +
17588 +struct ar9300_base_eep_hdr {
17589 + u16 regDmn[2];
17590 + /* 4 bits tx and 4 bits rx */
17591 + u8 txrxMask;
17592 + struct eepFlags opCapFlags;
17593 + u8 rfSilent;
17594 + u8 blueToothOptions;
17595 + u8 deviceCap;
17596 + /* takes lower byte in eeprom location */
17597 + u8 deviceType;
17598 + /* offset in dB to be added to beginning
17599 + * of pdadc table in calibration
17600 + */
17601 + int8_t pwrTableOffset;
17602 + u8 params_for_tuning_caps[2];
17603 + /*
17604 + * bit0 - enable tx temp comp
17605 + * bit1 - enable tx volt comp
17606 + * bit2 - enable fastClock - default to 1
17607 + * bit3 - enable doubling - default to 1
17608 + * bit4 - enable internal regulator - default to 1
17609 + */
17610 + u8 featureEnable;
17611 + /* misc flags: bit0 - turn down drivestrength */
17612 + u8 miscConfiguration;
17613 + u8 eepromWriteEnableGpio;
17614 + u8 wlanDisableGpio;
17615 + u8 wlanLedGpio;
17616 + u8 rxBandSelectGpio;
17617 + u8 txrxgain;
17618 + /* SW controlled internal regulator fields */
17619 + u32 swreg;
17620 +} __packed;
17621 +
17622 +struct ar9300_modal_eep_header {
17623 + /* 4 idle, t1, t2, b (4 bits per setting) */
17624 + u32 antCtrlCommon;
17625 + /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
17626 + u32 antCtrlCommon2;
17627 + /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
17628 + u16 antCtrlChain[AR9300_MAX_CHAINS];
17629 + /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
17630 + u8 xatten1DB[AR9300_MAX_CHAINS];
17631 + /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
17632 + u8 xatten1Margin[AR9300_MAX_CHAINS];
17633 + int8_t tempSlope;
17634 + int8_t voltSlope;
17635 + /* spur channels in usual fbin coding format */
17636 + u8 spurChans[AR9300_EEPROM_MODAL_SPURS];
17637 + /* 3 Check if the register is per chain */
17638 + int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
17639 + u8 ob[AR9300_MAX_CHAINS];
17640 + u8 db_stage2[AR9300_MAX_CHAINS];
17641 + u8 db_stage3[AR9300_MAX_CHAINS];
17642 + u8 db_stage4[AR9300_MAX_CHAINS];
17643 + u8 xpaBiasLvl;
17644 + u8 txFrameToDataStart;
17645 + u8 txFrameToPaOn;
17646 + u8 txClip;
17647 + int8_t antennaGain;
17648 + u8 switchSettling;
17649 + int8_t adcDesiredSize;
17650 + u8 txEndToXpaOff;
17651 + u8 txEndToRxOn;
17652 + u8 txFrameToXpaOn;
17653 + u8 thresh62;
17654 + u8 futureModal[32];
17655 +} __packed;
17656 +
17657 +struct ar9300_cal_data_per_freq_op_loop {
17658 + int8_t refPower;
17659 + /* pdadc voltage at power measurement */
17660 + u8 voltMeas;
17661 + /* pcdac used for power measurement */
17662 + u8 tempMeas;
17663 + /* range is -60 to -127 create a mapping equation 1db resolution */
17664 + int8_t rxNoisefloorCal;
17665 + /*range is same as noisefloor */
17666 + int8_t rxNoisefloorPower;
17667 + /* temp measured when noisefloor cal was performed */
17668 + u8 rxTempMeas;
17669 +} __packed;
17670 +
17671 +struct cal_tgt_pow_legacy {
17672 + u8 tPow2x[4];
17673 +} __packed;
17674 +
17675 +struct cal_tgt_pow_ht {
17676 + u8 tPow2x[14];
17677 +} __packed;
17678 +
17679 +struct cal_ctl_edge_pwr {
17680 + u8 tPower :6,
17681 + flag :2;
17682 +} __packed;
17683 +
17684 +struct cal_ctl_data_2g {
17685 + struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
17686 +} __packed;
17687 +
17688 +struct cal_ctl_data_5g {
17689 + struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
17690 +} __packed;
17691 +
17692 +struct ar9300_eeprom {
17693 + u8 eepromVersion;
17694 + u8 templateVersion;
17695 + u8 macAddr[6];
17696 + u8 custData[AR9300_CUSTOMER_DATA_SIZE];
17697 +
17698 + struct ar9300_base_eep_hdr baseEepHeader;
17699 +
17700 + struct ar9300_modal_eep_header modalHeader2G;
17701 + u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
17702 + struct ar9300_cal_data_per_freq_op_loop
17703 + calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
17704 + u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
17705 + u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
17706 + u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
17707 + u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
17708 + struct cal_tgt_pow_legacy
17709 + calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
17710 + struct cal_tgt_pow_legacy
17711 + calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
17712 + struct cal_tgt_pow_ht
17713 + calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
17714 + struct cal_tgt_pow_ht
17715 + calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
17716 + u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
17717 + u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
17718 + struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
17719 + struct ar9300_modal_eep_header modalHeader5G;
17720 + u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
17721 + struct ar9300_cal_data_per_freq_op_loop
17722 + calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
17723 + u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
17724 + u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
17725 + u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
17726 + struct cal_tgt_pow_legacy
17727 + calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
17728 + struct cal_tgt_pow_ht
17729 + calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
17730 + struct cal_tgt_pow_ht
17731 + calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
17732 + u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
17733 + u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
17734 + struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
17735 +} __packed;
17736 +
17737 +s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
17738 +s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
17739 +
17740 +#endif
17741 diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
17742 new file mode 100644
17743 index 0000000..95edd25
17744 --- /dev/null
17745 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
17746 @@ -0,0 +1,205 @@
17747 +/*
17748 + * Copyright (c) 2008-2010 Atheros Communications Inc.
17749 + *
17750 + * Permission to use, copy, modify, and/or distribute this software for any
17751 + * purpose with or without fee is hereby granted, provided that the above
17752 + * copyright notice and this permission notice appear in all copies.
17753 + *
17754 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17755 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17756 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17757 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17758 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17759 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17760 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17761 + */
17762 +
17763 +#include "hw.h"
17764 +#include "ar9003_initvals.h"
17765 +
17766 +/* General hardware code for the AR9003 hadware family */
17767 +
17768 +static bool ar9003_hw_macversion_supported(u32 macversion)
17769 +{
17770 + switch (macversion) {
17771 + case AR_SREV_VERSION_9300:
17772 + return true;
17773 + default:
17774 + break;
17775 + }
17776 + return false;
17777 +}
17778 +
17779 +/* AR9003 2.0 - new INI format (pre, core, post arrays per subsystem) */
17780 +/*
17781 + * XXX: move TX/RX gain INI to its own init_mode_gain_regs after
17782 + * ensuring it does not affect hardware bring up
17783 + */
17784 +static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
17785 +{
17786 + /* mac */
17787 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
17788 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
17789 + ar9300_2p0_mac_core,
17790 + ARRAY_SIZE(ar9300_2p0_mac_core), 2);
17791 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
17792 + ar9300_2p0_mac_postamble,
17793 + ARRAY_SIZE(ar9300_2p0_mac_postamble), 5);
17794 +
17795 + /* bb */
17796 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
17797 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
17798 + ar9300_2p0_baseband_core,
17799 + ARRAY_SIZE(ar9300_2p0_baseband_core), 2);
17800 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
17801 + ar9300_2p0_baseband_postamble,
17802 + ARRAY_SIZE(ar9300_2p0_baseband_postamble), 5);
17803 +
17804 + /* radio */
17805 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
17806 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
17807 + ar9300_2p0_radio_core,
17808 + ARRAY_SIZE(ar9300_2p0_radio_core), 2);
17809 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
17810 + ar9300_2p0_radio_postamble,
17811 + ARRAY_SIZE(ar9300_2p0_radio_postamble), 5);
17812 +
17813 + /* soc */
17814 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
17815 + ar9300_2p0_soc_preamble,
17816 + ARRAY_SIZE(ar9300_2p0_soc_preamble), 2);
17817 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
17818 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
17819 + ar9300_2p0_soc_postamble,
17820 + ARRAY_SIZE(ar9300_2p0_soc_postamble), 5);
17821 +
17822 + /* rx/tx gain */
17823 + INIT_INI_ARRAY(&ah->iniModesRxGain,
17824 + ar9300Common_rx_gain_table_2p0,
17825 + ARRAY_SIZE(ar9300Common_rx_gain_table_2p0), 2);
17826 + INIT_INI_ARRAY(&ah->iniModesTxGain,
17827 + ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
17828 + ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
17829 + 5);
17830 +
17831 + /* Load PCIE SERDES settings from INI */
17832 +
17833 + /* Awake Setting */
17834 +
17835 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
17836 + ar9300PciePhy_pll_on_clkreq_disable_L1_2p0,
17837 + ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p0),
17838 + 2);
17839 +
17840 + /* Sleep Setting */
17841 +
17842 + INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
17843 + ar9300PciePhy_clkreq_enable_L1_2p0,
17844 + ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p0),
17845 + 2);
17846 +
17847 + /* Fast clock modal settings */
17848 + INIT_INI_ARRAY(&ah->iniModesAdditional,
17849 + ar9300Modes_fast_clock_2p0,
17850 + ARRAY_SIZE(ar9300Modes_fast_clock_2p0),
17851 + 3);
17852 +}
17853 +
17854 +static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
17855 +{
17856 + switch(ar9003_hw_get_tx_gain_idx(ah)) {
17857 + case 0:
17858 + default:
17859 + INIT_INI_ARRAY(&ah->iniModesTxGain,
17860 + ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
17861 + ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
17862 + 5);
17863 + break;
17864 + case 1:
17865 + INIT_INI_ARRAY(&ah->iniModesTxGain,
17866 + ar9300Modes_high_ob_db_tx_gain_table_2p0,
17867 + ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p0),
17868 + 5);
17869 + break;
17870 + case 2:
17871 + INIT_INI_ARRAY(&ah->iniModesTxGain,
17872 + ar9300Modes_low_ob_db_tx_gain_table_2p0,
17873 + ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p0),
17874 + 5);
17875 + break;
17876 + }
17877 +}
17878 +
17879 +static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
17880 +{
17881 + switch(ar9003_hw_get_rx_gain_idx(ah))
17882 + {
17883 + case 0:
17884 + default:
17885 + INIT_INI_ARRAY(&ah->iniModesRxGain, ar9300Common_rx_gain_table_2p0,
17886 + ARRAY_SIZE(ar9300Common_rx_gain_table_2p0),
17887 + 2);
17888 + break;
17889 + case 1:
17890 + INIT_INI_ARRAY(&ah->iniModesRxGain,
17891 + ar9300Common_wo_xlna_rx_gain_table_2p0,
17892 + ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p0),
17893 + 2);
17894 + break;
17895 + }
17896 +}
17897 +
17898 +/* set gain table pointers according to values read from the eeprom */
17899 +static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
17900 +{
17901 + ar9003_tx_gain_table_apply(ah);
17902 + ar9003_rx_gain_table_apply(ah);
17903 +}
17904 +
17905 +/*
17906 + * Helper for ASPM support.
17907 + *
17908 + * Disable PLL when in L0s as well as receiver clock when in L1.
17909 + * This power saving option must be enabled through the SerDes.
17910 + *
17911 + * Programming the SerDes must go through the same 288 bit serial shift
17912 + * register as the other analog registers. Hence the 9 writes.
17913 + */
17914 +static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
17915 + int restore,
17916 + int power_off)
17917 +{
17918 + if (ah->is_pciexpress != true)
17919 + return;
17920 +
17921 + /* Do not touch SerDes registers */
17922 + if (ah->config.pcie_powersave_enable == 2)
17923 + return;
17924 +
17925 + /* Nothing to do on restore for 11N */
17926 + if (!restore) {
17927 + /* set bit 19 to allow forcing of pcie core into L1 state */
17928 + REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
17929 +
17930 + /* Several PCIe massages to ensure proper behaviour */
17931 + if (ah->config.pcie_waen)
17932 + REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
17933 + }
17934 +}
17935 +
17936 +/* Sets up the AR9003 hardware familiy callbacks */
17937 +void ar9003_hw_attach_ops(struct ath_hw *ah)
17938 +{
17939 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
17940 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
17941 +
17942 + priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
17943 + priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
17944 + priv_ops->macversion_supported = ar9003_hw_macversion_supported;
17945 +
17946 + ops->config_pci_powersave = ar9003_hw_configpcipowersave;
17947 +
17948 + ar9003_hw_attach_phy_ops(ah);
17949 + ar9003_hw_attach_calib_ops(ah);
17950 + ar9003_hw_attach_mac_ops(ah);
17951 +}
17952 diff --git a/drivers/net/wireless/ath/ath9k/ar9003_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_initvals.h
17953 new file mode 100644
17954 index 0000000..e0391b1
17955 --- /dev/null
17956 +++ b/drivers/net/wireless/ath/ath9k/ar9003_initvals.h
17957 @@ -0,0 +1,1793 @@
17958 +/*
17959 + * Copyright (c) 2010 Atheros Communications Inc.
17960 + *
17961 + * Permission to use, copy, modify, and/or distribute this software for any
17962 + * purpose with or without fee is hereby granted, provided that the above
17963 + * copyright notice and this permission notice appear in all copies.
17964 + *
17965 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17966 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17967 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17968 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17969 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17970 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17971 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17972 + */
17973 +
17974 +#ifndef INITVALS_9003_H
17975 +#define INITVALS_9003_H
17976 +
17977 +/* AR9003 2.0 */
17978 +
17979 +static const u32 ar9300_2p0_radio_postamble[][5] = {
17980 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
17981 + {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
17982 + {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
17983 + {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
17984 + {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
17985 + {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
17986 + {0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
17987 +};
17988 +
17989 +static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p0[][5] = {
17990 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
17991 + {0x0000a410, 0x000050da, 0x000050da, 0x000050da, 0x000050da},
17992 + {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
17993 + {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
17994 + {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
17995 + {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
17996 + {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
17997 + {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
17998 + {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
17999 + {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
18000 + {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
18001 + {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
18002 + {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
18003 + {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
18004 + {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
18005 + {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
18006 + {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
18007 + {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
18008 + {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
18009 + {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
18010 + {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
18011 + {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
18012 + {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
18013 + {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
18014 + {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
18015 + {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
18016 + {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
18017 + {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
18018 + {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
18019 + {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
18020 + {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
18021 + {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
18022 + {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
18023 + {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
18024 + {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
18025 + {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
18026 + {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
18027 + {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
18028 + {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
18029 + {0x0000a594, 0x1c800223, 0x1c800223, 0x12800400, 0x12800400},
18030 + {0x0000a598, 0x21820220, 0x21820220, 0x16800402, 0x16800402},
18031 + {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
18032 + {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1c800603, 0x1c800603},
18033 + {0x0000a5a4, 0x2f822222, 0x2f822222, 0x21800a02, 0x21800a02},
18034 + {0x0000a5a8, 0x34822225, 0x34822225, 0x25800a04, 0x25800a04},
18035 + {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x28800a20, 0x28800a20},
18036 + {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2c800e20, 0x2c800e20},
18037 + {0x0000a5b4, 0x4282242a, 0x4282242a, 0x30800e22, 0x30800e22},
18038 + {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
18039 + {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
18040 + {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
18041 + {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
18042 + {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
18043 + {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x47801a83, 0x47801a83},
18044 + {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x4a801c84, 0x4a801c84},
18045 + {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x4e801ce3, 0x4e801ce3},
18046 + {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x52801ce5, 0x52801ce5},
18047 + {0x0000a5dc, 0x7086308c, 0x7086308c, 0x56801ce9, 0x56801ce9},
18048 + {0x0000a5e0, 0x738a308a, 0x738a308a, 0x5a801ceb, 0x5a801ceb},
18049 + {0x0000a5e4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
18050 + {0x0000a5e8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
18051 + {0x0000a5ec, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
18052 + {0x0000a5f0, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
18053 + {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
18054 + {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
18055 + {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
18056 + {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
18057 + {0x00016048, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
18058 + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
18059 + {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
18060 + {0x00016448, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
18061 + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
18062 + {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
18063 + {0x00016848, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
18064 + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
18065 +};
18066 +
18067 +static const u32 ar9300Modes_fast_clock_2p0[][3] = {
18068 + /* Addr 5G_HT20 5G_HT40 */
18069 + {0x00001030, 0x00000268, 0x000004d0},
18070 + {0x00001070, 0x0000018c, 0x00000318},
18071 + {0x000010b0, 0x00000fd0, 0x00001fa0},
18072 + {0x00008014, 0x044c044c, 0x08980898},
18073 + {0x0000801c, 0x148ec02b, 0x148ec057},
18074 + {0x00008318, 0x000044c0, 0x00008980},
18075 + {0x00009e00, 0x03721821, 0x03721821},
18076 + {0x0000a230, 0x0000000b, 0x00000016},
18077 + {0x0000a254, 0x00000898, 0x00001130},
18078 +};
18079 +
18080 +static const u32 ar9300_2p0_radio_core[][2] = {
18081 + /* Addr allmodes */
18082 + {0x00016000, 0x36db6db6},
18083 + {0x00016004, 0x6db6db40},
18084 + {0x00016008, 0x73f00000},
18085 + {0x0001600c, 0x00000000},
18086 + {0x00016040, 0x7f80fff8},
18087 + {0x0001604c, 0x76d005b5},
18088 + {0x00016050, 0x556cf031},
18089 + {0x00016054, 0x43449440},
18090 + {0x00016058, 0x0c51c92c},
18091 + {0x0001605c, 0x3db7fffc},
18092 + {0x00016060, 0xfffffffc},
18093 + {0x00016064, 0x000f0278},
18094 + {0x0001606c, 0x6db60000},
18095 + {0x00016080, 0x00000000},
18096 + {0x00016084, 0x0e48048c},
18097 + {0x00016088, 0x54214514},
18098 + {0x0001608c, 0x119f481e},
18099 + {0x00016090, 0x24926490},
18100 + {0x00016098, 0xd2888888},
18101 + {0x000160a0, 0x0a108ffe},
18102 + {0x000160a4, 0x812fc370},
18103 + {0x000160a8, 0x423c8000},
18104 + {0x000160b4, 0x92480080},
18105 + {0x000160c0, 0x00adb6d0},
18106 + {0x000160c4, 0x6db6db60},
18107 + {0x000160c8, 0x6db6db6c},
18108 + {0x000160cc, 0x01e6c000},
18109 + {0x00016100, 0x3fffbe01},
18110 + {0x00016104, 0xfff80000},
18111 + {0x00016108, 0x00080010},
18112 + {0x00016140, 0x10804008},
18113 + {0x00016144, 0x02084080},
18114 + {0x00016148, 0x00000000},
18115 + {0x00016280, 0x058a0001},
18116 + {0x00016284, 0x3d840208},
18117 + {0x00016288, 0x01a20408},
18118 + {0x0001628c, 0x00038c07},
18119 + {0x00016290, 0x40000004},
18120 + {0x00016294, 0x458aa14f},
18121 + {0x00016380, 0x00000000},
18122 + {0x00016384, 0x00000000},
18123 + {0x00016388, 0x00800700},
18124 + {0x0001638c, 0x00800700},
18125 + {0x00016390, 0x00800700},
18126 + {0x00016394, 0x00000000},
18127 + {0x00016398, 0x00000000},
18128 + {0x0001639c, 0x00000000},
18129 + {0x000163a0, 0x00000001},
18130 + {0x000163a4, 0x00000001},
18131 + {0x000163a8, 0x00000000},
18132 + {0x000163ac, 0x00000000},
18133 + {0x000163b0, 0x00000000},
18134 + {0x000163b4, 0x00000000},
18135 + {0x000163b8, 0x00000000},
18136 + {0x000163bc, 0x00000000},
18137 + {0x000163c0, 0x000000a0},
18138 + {0x000163c4, 0x000c0000},
18139 + {0x000163c8, 0x14021402},
18140 + {0x000163cc, 0x00001402},
18141 + {0x000163d0, 0x00000000},
18142 + {0x000163d4, 0x00000000},
18143 + {0x00016400, 0x36db6db6},
18144 + {0x00016404, 0x6db6db40},
18145 + {0x00016408, 0x73f00000},
18146 + {0x0001640c, 0x00000000},
18147 + {0x00016440, 0x7f80fff8},
18148 + {0x0001644c, 0x76d005b5},
18149 + {0x00016450, 0x556cf031},
18150 + {0x00016454, 0x43449440},
18151 + {0x00016458, 0x0c51c92c},
18152 + {0x0001645c, 0x3db7fffc},
18153 + {0x00016460, 0xfffffffc},
18154 + {0x00016464, 0x000f0278},
18155 + {0x0001646c, 0x6db60000},
18156 + {0x00016500, 0x3fffbe01},
18157 + {0x00016504, 0xfff80000},
18158 + {0x00016508, 0x00080010},
18159 + {0x00016540, 0x10804008},
18160 + {0x00016544, 0x02084080},
18161 + {0x00016548, 0x00000000},
18162 + {0x00016780, 0x00000000},
18163 + {0x00016784, 0x00000000},
18164 + {0x00016788, 0x00800700},
18165 + {0x0001678c, 0x00800700},
18166 + {0x00016790, 0x00800700},
18167 + {0x00016794, 0x00000000},
18168 + {0x00016798, 0x00000000},
18169 + {0x0001679c, 0x00000000},
18170 + {0x000167a0, 0x00000001},
18171 + {0x000167a4, 0x00000001},
18172 + {0x000167a8, 0x00000000},
18173 + {0x000167ac, 0x00000000},
18174 + {0x000167b0, 0x00000000},
18175 + {0x000167b4, 0x00000000},
18176 + {0x000167b8, 0x00000000},
18177 + {0x000167bc, 0x00000000},
18178 + {0x000167c0, 0x000000a0},
18179 + {0x000167c4, 0x000c0000},
18180 + {0x000167c8, 0x14021402},
18181 + {0x000167cc, 0x00001402},
18182 + {0x000167d0, 0x00000000},
18183 + {0x000167d4, 0x00000000},
18184 + {0x00016800, 0x36db6db6},
18185 + {0x00016804, 0x6db6db40},
18186 + {0x00016808, 0x73f00000},
18187 + {0x0001680c, 0x00000000},
18188 + {0x00016840, 0x7f80fff8},
18189 + {0x0001684c, 0x76d005b5},
18190 + {0x00016850, 0x556cf031},
18191 + {0x00016854, 0x43449440},
18192 + {0x00016858, 0x0c51c92c},
18193 + {0x0001685c, 0x3db7fffc},
18194 + {0x00016860, 0xfffffffc},
18195 + {0x00016864, 0x000f0278},
18196 + {0x0001686c, 0x6db60000},
18197 + {0x00016900, 0x3fffbe01},
18198 + {0x00016904, 0xfff80000},
18199 + {0x00016908, 0x00080010},
18200 + {0x00016940, 0x10804008},
18201 + {0x00016944, 0x02084080},
18202 + {0x00016948, 0x00000000},
18203 + {0x00016b80, 0x00000000},
18204 + {0x00016b84, 0x00000000},
18205 + {0x00016b88, 0x00800700},
18206 + {0x00016b8c, 0x00800700},
18207 + {0x00016b90, 0x00800700},
18208 + {0x00016b94, 0x00000000},
18209 + {0x00016b98, 0x00000000},
18210 + {0x00016b9c, 0x00000000},
18211 + {0x00016ba0, 0x00000001},
18212 + {0x00016ba4, 0x00000001},
18213 + {0x00016ba8, 0x00000000},
18214 + {0x00016bac, 0x00000000},
18215 + {0x00016bb0, 0x00000000},
18216 + {0x00016bb4, 0x00000000},
18217 + {0x00016bb8, 0x00000000},
18218 + {0x00016bbc, 0x00000000},
18219 + {0x00016bc0, 0x000000a0},
18220 + {0x00016bc4, 0x000c0000},
18221 + {0x00016bc8, 0x14021402},
18222 + {0x00016bcc, 0x00001402},
18223 + {0x00016bd0, 0x00000000},
18224 + {0x00016bd4, 0x00000000},
18225 +};
18226 +
18227 +static const u32 ar9300Common_rx_gain_table_merlin_2p0[][2] = {
18228 + /* Addr allmodes */
18229 + {0x0000a000, 0x02000101},
18230 + {0x0000a004, 0x02000102},
18231 + {0x0000a008, 0x02000103},
18232 + {0x0000a00c, 0x02000104},
18233 + {0x0000a010, 0x02000200},
18234 + {0x0000a014, 0x02000201},
18235 + {0x0000a018, 0x02000202},
18236 + {0x0000a01c, 0x02000203},
18237 + {0x0000a020, 0x02000204},
18238 + {0x0000a024, 0x02000205},
18239 + {0x0000a028, 0x02000208},
18240 + {0x0000a02c, 0x02000302},
18241 + {0x0000a030, 0x02000303},
18242 + {0x0000a034, 0x02000304},
18243 + {0x0000a038, 0x02000400},
18244 + {0x0000a03c, 0x02010300},
18245 + {0x0000a040, 0x02010301},
18246 + {0x0000a044, 0x02010302},
18247 + {0x0000a048, 0x02000500},
18248 + {0x0000a04c, 0x02010400},
18249 + {0x0000a050, 0x02020300},
18250 + {0x0000a054, 0x02020301},
18251 + {0x0000a058, 0x02020302},
18252 + {0x0000a05c, 0x02020303},
18253 + {0x0000a060, 0x02020400},
18254 + {0x0000a064, 0x02030300},
18255 + {0x0000a068, 0x02030301},
18256 + {0x0000a06c, 0x02030302},
18257 + {0x0000a070, 0x02030303},
18258 + {0x0000a074, 0x02030400},
18259 + {0x0000a078, 0x02040300},
18260 + {0x0000a07c, 0x02040301},
18261 + {0x0000a080, 0x02040302},
18262 + {0x0000a084, 0x02040303},
18263 + {0x0000a088, 0x02030500},
18264 + {0x0000a08c, 0x02040400},
18265 + {0x0000a090, 0x02050203},
18266 + {0x0000a094, 0x02050204},
18267 + {0x0000a098, 0x02050205},
18268 + {0x0000a09c, 0x02040500},
18269 + {0x0000a0a0, 0x02050301},
18270 + {0x0000a0a4, 0x02050302},
18271 + {0x0000a0a8, 0x02050303},
18272 + {0x0000a0ac, 0x02050400},
18273 + {0x0000a0b0, 0x02050401},
18274 + {0x0000a0b4, 0x02050402},
18275 + {0x0000a0b8, 0x02050403},
18276 + {0x0000a0bc, 0x02050500},
18277 + {0x0000a0c0, 0x02050501},
18278 + {0x0000a0c4, 0x02050502},
18279 + {0x0000a0c8, 0x02050503},
18280 + {0x0000a0cc, 0x02050504},
18281 + {0x0000a0d0, 0x02050600},
18282 + {0x0000a0d4, 0x02050601},
18283 + {0x0000a0d8, 0x02050602},
18284 + {0x0000a0dc, 0x02050603},
18285 + {0x0000a0e0, 0x02050604},
18286 + {0x0000a0e4, 0x02050700},
18287 + {0x0000a0e8, 0x02050701},
18288 + {0x0000a0ec, 0x02050702},
18289 + {0x0000a0f0, 0x02050703},
18290 + {0x0000a0f4, 0x02050704},
18291 + {0x0000a0f8, 0x02050705},
18292 + {0x0000a0fc, 0x02050708},
18293 + {0x0000a100, 0x02050709},
18294 + {0x0000a104, 0x0205070a},
18295 + {0x0000a108, 0x0205070b},
18296 + {0x0000a10c, 0x0205070c},
18297 + {0x0000a110, 0x0205070d},
18298 + {0x0000a114, 0x02050710},
18299 + {0x0000a118, 0x02050711},
18300 + {0x0000a11c, 0x02050712},
18301 + {0x0000a120, 0x02050713},
18302 + {0x0000a124, 0x02050714},
18303 + {0x0000a128, 0x02050715},
18304 + {0x0000a12c, 0x02050730},
18305 + {0x0000a130, 0x02050731},
18306 + {0x0000a134, 0x02050732},
18307 + {0x0000a138, 0x02050733},
18308 + {0x0000a13c, 0x02050734},
18309 + {0x0000a140, 0x02050735},
18310 + {0x0000a144, 0x02050750},
18311 + {0x0000a148, 0x02050751},
18312 + {0x0000a14c, 0x02050752},
18313 + {0x0000a150, 0x02050753},
18314 + {0x0000a154, 0x02050754},
18315 + {0x0000a158, 0x02050755},
18316 + {0x0000a15c, 0x02050770},
18317 + {0x0000a160, 0x02050771},
18318 + {0x0000a164, 0x02050772},
18319 + {0x0000a168, 0x02050773},
18320 + {0x0000a16c, 0x02050774},
18321 + {0x0000a170, 0x02050775},
18322 + {0x0000a174, 0x00000776},
18323 + {0x0000a178, 0x00000776},
18324 + {0x0000a17c, 0x00000776},
18325 + {0x0000a180, 0x00000776},
18326 + {0x0000a184, 0x00000776},
18327 + {0x0000a188, 0x00000776},
18328 + {0x0000a18c, 0x00000776},
18329 + {0x0000a190, 0x00000776},
18330 + {0x0000a194, 0x00000776},
18331 + {0x0000a198, 0x00000776},
18332 + {0x0000a19c, 0x00000776},
18333 + {0x0000a1a0, 0x00000776},
18334 + {0x0000a1a4, 0x00000776},
18335 + {0x0000a1a8, 0x00000776},
18336 + {0x0000a1ac, 0x00000776},
18337 + {0x0000a1b0, 0x00000776},
18338 + {0x0000a1b4, 0x00000776},
18339 + {0x0000a1b8, 0x00000776},
18340 + {0x0000a1bc, 0x00000776},
18341 + {0x0000a1c0, 0x00000776},
18342 + {0x0000a1c4, 0x00000776},
18343 + {0x0000a1c8, 0x00000776},
18344 + {0x0000a1cc, 0x00000776},
18345 + {0x0000a1d0, 0x00000776},
18346 + {0x0000a1d4, 0x00000776},
18347 + {0x0000a1d8, 0x00000776},
18348 + {0x0000a1dc, 0x00000776},
18349 + {0x0000a1e0, 0x00000776},
18350 + {0x0000a1e4, 0x00000776},
18351 + {0x0000a1e8, 0x00000776},
18352 + {0x0000a1ec, 0x00000776},
18353 + {0x0000a1f0, 0x00000776},
18354 + {0x0000a1f4, 0x00000776},
18355 + {0x0000a1f8, 0x00000776},
18356 + {0x0000a1fc, 0x00000776},
18357 + {0x0000b000, 0x02000101},
18358 + {0x0000b004, 0x02000102},
18359 + {0x0000b008, 0x02000103},
18360 + {0x0000b00c, 0x02000104},
18361 + {0x0000b010, 0x02000200},
18362 + {0x0000b014, 0x02000201},
18363 + {0x0000b018, 0x02000202},
18364 + {0x0000b01c, 0x02000203},
18365 + {0x0000b020, 0x02000204},
18366 + {0x0000b024, 0x02000205},
18367 + {0x0000b028, 0x02000208},
18368 + {0x0000b02c, 0x02000302},
18369 + {0x0000b030, 0x02000303},
18370 + {0x0000b034, 0x02000304},
18371 + {0x0000b038, 0x02000400},
18372 + {0x0000b03c, 0x02010300},
18373 + {0x0000b040, 0x02010301},
18374 + {0x0000b044, 0x02010302},
18375 + {0x0000b048, 0x02000500},
18376 + {0x0000b04c, 0x02010400},
18377 + {0x0000b050, 0x02020300},
18378 + {0x0000b054, 0x02020301},
18379 + {0x0000b058, 0x02020302},
18380 + {0x0000b05c, 0x02020303},
18381 + {0x0000b060, 0x02020400},
18382 + {0x0000b064, 0x02030300},
18383 + {0x0000b068, 0x02030301},
18384 + {0x0000b06c, 0x02030302},
18385 + {0x0000b070, 0x02030303},
18386 + {0x0000b074, 0x02030400},
18387 + {0x0000b078, 0x02040300},
18388 + {0x0000b07c, 0x02040301},
18389 + {0x0000b080, 0x02040302},
18390 + {0x0000b084, 0x02040303},
18391 + {0x0000b088, 0x02030500},
18392 + {0x0000b08c, 0x02040400},
18393 + {0x0000b090, 0x02050203},
18394 + {0x0000b094, 0x02050204},
18395 + {0x0000b098, 0x02050205},
18396 + {0x0000b09c, 0x02040500},
18397 + {0x0000b0a0, 0x02050301},
18398 + {0x0000b0a4, 0x02050302},
18399 + {0x0000b0a8, 0x02050303},
18400 + {0x0000b0ac, 0x02050400},
18401 + {0x0000b0b0, 0x02050401},
18402 + {0x0000b0b4, 0x02050402},
18403 + {0x0000b0b8, 0x02050403},
18404 + {0x0000b0bc, 0x02050500},
18405 + {0x0000b0c0, 0x02050501},
18406 + {0x0000b0c4, 0x02050502},
18407 + {0x0000b0c8, 0x02050503},
18408 + {0x0000b0cc, 0x02050504},
18409 + {0x0000b0d0, 0x02050600},
18410 + {0x0000b0d4, 0x02050601},
18411 + {0x0000b0d8, 0x02050602},
18412 + {0x0000b0dc, 0x02050603},
18413 + {0x0000b0e0, 0x02050604},
18414 + {0x0000b0e4, 0x02050700},
18415 + {0x0000b0e8, 0x02050701},
18416 + {0x0000b0ec, 0x02050702},
18417 + {0x0000b0f0, 0x02050703},
18418 + {0x0000b0f4, 0x02050704},
18419 + {0x0000b0f8, 0x02050705},
18420 + {0x0000b0fc, 0x02050708},
18421 + {0x0000b100, 0x02050709},
18422 + {0x0000b104, 0x0205070a},
18423 + {0x0000b108, 0x0205070b},
18424 + {0x0000b10c, 0x0205070c},
18425 + {0x0000b110, 0x0205070d},
18426 + {0x0000b114, 0x02050710},
18427 + {0x0000b118, 0x02050711},
18428 + {0x0000b11c, 0x02050712},
18429 + {0x0000b120, 0x02050713},
18430 + {0x0000b124, 0x02050714},
18431 + {0x0000b128, 0x02050715},
18432 + {0x0000b12c, 0x02050730},
18433 + {0x0000b130, 0x02050731},
18434 + {0x0000b134, 0x02050732},
18435 + {0x0000b138, 0x02050733},
18436 + {0x0000b13c, 0x02050734},
18437 + {0x0000b140, 0x02050735},
18438 + {0x0000b144, 0x02050750},
18439 + {0x0000b148, 0x02050751},
18440 + {0x0000b14c, 0x02050752},
18441 + {0x0000b150, 0x02050753},
18442 + {0x0000b154, 0x02050754},
18443 + {0x0000b158, 0x02050755},
18444 + {0x0000b15c, 0x02050770},
18445 + {0x0000b160, 0x02050771},
18446 + {0x0000b164, 0x02050772},
18447 + {0x0000b168, 0x02050773},
18448 + {0x0000b16c, 0x02050774},
18449 + {0x0000b170, 0x02050775},
18450 + {0x0000b174, 0x00000776},
18451 + {0x0000b178, 0x00000776},
18452 + {0x0000b17c, 0x00000776},
18453 + {0x0000b180, 0x00000776},
18454 + {0x0000b184, 0x00000776},
18455 + {0x0000b188, 0x00000776},
18456 + {0x0000b18c, 0x00000776},
18457 + {0x0000b190, 0x00000776},
18458 + {0x0000b194, 0x00000776},
18459 + {0x0000b198, 0x00000776},
18460 + {0x0000b19c, 0x00000776},
18461 + {0x0000b1a0, 0x00000776},
18462 + {0x0000b1a4, 0x00000776},
18463 + {0x0000b1a8, 0x00000776},
18464 + {0x0000b1ac, 0x00000776},
18465 + {0x0000b1b0, 0x00000776},
18466 + {0x0000b1b4, 0x00000776},
18467 + {0x0000b1b8, 0x00000776},
18468 + {0x0000b1bc, 0x00000776},
18469 + {0x0000b1c0, 0x00000776},
18470 + {0x0000b1c4, 0x00000776},
18471 + {0x0000b1c8, 0x00000776},
18472 + {0x0000b1cc, 0x00000776},
18473 + {0x0000b1d0, 0x00000776},
18474 + {0x0000b1d4, 0x00000776},
18475 + {0x0000b1d8, 0x00000776},
18476 + {0x0000b1dc, 0x00000776},
18477 + {0x0000b1e0, 0x00000776},
18478 + {0x0000b1e4, 0x00000776},
18479 + {0x0000b1e8, 0x00000776},
18480 + {0x0000b1ec, 0x00000776},
18481 + {0x0000b1f0, 0x00000776},
18482 + {0x0000b1f4, 0x00000776},
18483 + {0x0000b1f8, 0x00000776},
18484 + {0x0000b1fc, 0x00000776},
18485 +};
18486 +
18487 +static const u32 ar9300_2p0_mac_postamble[][5] = {
18488 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
18489 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
18490 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
18491 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
18492 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
18493 + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
18494 + {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
18495 + {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
18496 + {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
18497 +};
18498 +
18499 +static const u32 ar9300_2p0_soc_postamble[][5] = {
18500 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
18501 + {0x00007010, 0x00000023, 0x00000023, 0x00000022, 0x00000022},
18502 +};
18503 +
18504 +static const u32 ar9200_merlin_2p0_radio_core[][2] = {
18505 + /* Addr common */
18506 + {0x00007800, 0x00040000},
18507 + {0x00007804, 0xdb005012},
18508 + {0x00007808, 0x04924914},
18509 + {0x0000780c, 0x21084210},
18510 + {0x00007810, 0x6d801300},
18511 + {0x00007814, 0x0019beff},
18512 + {0x00007818, 0x07e41000},
18513 + {0x0000781c, 0x00392000},
18514 + {0x00007820, 0x92592480},
18515 + {0x00007824, 0x00040000},
18516 + {0x00007828, 0xdb005012},
18517 + {0x0000782c, 0x04924914},
18518 + {0x00007830, 0x21084210},
18519 + {0x00007834, 0x6d801300},
18520 + {0x00007838, 0x0019beff},
18521 + {0x0000783c, 0x07e40000},
18522 + {0x00007840, 0x00392000},
18523 + {0x00007844, 0x92592480},
18524 + {0x00007848, 0x00100000},
18525 + {0x0000784c, 0x773f0567},
18526 + {0x00007850, 0x54214514},
18527 + {0x00007854, 0x12035828},
18528 + {0x00007858, 0x92592692},
18529 + {0x0000785c, 0x00000000},
18530 + {0x00007860, 0x56400000},
18531 + {0x00007864, 0x0a8e370e},
18532 + {0x00007868, 0xc0102850},
18533 + {0x0000786c, 0x812d4000},
18534 + {0x00007870, 0x807ec400},
18535 + {0x00007874, 0x001b6db0},
18536 + {0x00007878, 0x00376b63},
18537 + {0x0000787c, 0x06db6db6},
18538 + {0x00007880, 0x006d8000},
18539 + {0x00007884, 0xffeffffe},
18540 + {0x00007888, 0xffeffffe},
18541 + {0x0000788c, 0x00010000},
18542 + {0x00007890, 0x02060aeb},
18543 + {0x00007894, 0x5a108000},
18544 +};
18545 +
18546 +static const u32 ar9300_2p0_baseband_postamble[][5] = {
18547 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
18548 + {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
18549 + {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
18550 + {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
18551 + {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
18552 + {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
18553 + {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
18554 + {0x00009c00, 0x00000044, 0x000000c4, 0x000000c4, 0x00000044},
18555 + {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
18556 + {0x00009e04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
18557 + {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
18558 + {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e},
18559 + {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
18560 + {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
18561 + {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
18562 + {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
18563 + {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
18564 + {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
18565 + {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
18566 + {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
18567 + {0x0000a204, 0x000037c0, 0x000037c4, 0x000037c4, 0x000037c0},
18568 + {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
18569 + {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
18570 + {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
18571 + {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
18572 + {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
18573 + {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
18574 + {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
18575 + {0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501},
18576 + {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
18577 + {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
18578 + {0x0000a284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
18579 + {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
18580 + {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
18581 + {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
18582 + {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
18583 + {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
18584 + {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
18585 + {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
18586 + {0x0000ae04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
18587 + {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
18588 + {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
18589 + {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
18590 + {0x0000b284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
18591 + {0x0000b830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
18592 + {0x0000be04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
18593 + {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
18594 + {0x0000be1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
18595 + {0x0000be20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
18596 + {0x0000c284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
18597 +};
18598 +
18599 +static const u32 ar9300_2p0_baseband_core[][2] = {
18600 + /* Addr allmodes */
18601 + {0x00009800, 0xafe68e30},
18602 + {0x00009804, 0xfd14e000},
18603 + {0x00009808, 0x9c0a9f6b},
18604 + {0x0000980c, 0x04900000},
18605 + {0x00009814, 0x9280c00a},
18606 + {0x00009818, 0x00000000},
18607 + {0x0000981c, 0x00020028},
18608 + {0x00009834, 0x5f3ca3de},
18609 + {0x00009838, 0x0108ecff},
18610 + {0x0000983c, 0x14750600},
18611 + {0x00009880, 0x201fff00},
18612 + {0x00009884, 0x00001042},
18613 + {0x000098a4, 0x00200400},
18614 + {0x000098b0, 0x52440bbe},
18615 + {0x000098d0, 0x004b6a8e},
18616 + {0x000098d4, 0x00000820},
18617 + {0x000098dc, 0x00000000},
18618 + {0x000098f0, 0x00000000},
18619 + {0x000098f4, 0x00000000},
18620 + {0x00009c04, 0xff55ff55},
18621 + {0x00009c08, 0x0320ff55},
18622 + {0x00009c0c, 0x00000000},
18623 + {0x00009c10, 0x00000000},
18624 + {0x00009c14, 0x00046384},
18625 + {0x00009c18, 0x05b6b440},
18626 + {0x00009c1c, 0x00b6b440},
18627 + {0x00009d00, 0xc080a333},
18628 + {0x00009d04, 0x40206c10},
18629 + {0x00009d08, 0x009c4060},
18630 + {0x00009d0c, 0x9883800a},
18631 + {0x00009d10, 0x01834061},
18632 + {0x00009d14, 0x00c0040b},
18633 + {0x00009d18, 0x00000000},
18634 + {0x00009e08, 0x0038233c},
18635 + {0x00009e24, 0x990bb515},
18636 + {0x00009e28, 0x0c6f0000},
18637 + {0x00009e30, 0x06336f77},
18638 + {0x00009e34, 0x6af6532f},
18639 + {0x00009e38, 0x0cc80c00},
18640 + {0x00009e3c, 0xcf946222},
18641 + {0x00009e40, 0x0d261820},
18642 + {0x00009e4c, 0x00001004},
18643 + {0x00009e50, 0x00ff03f1},
18644 + {0x00009e54, 0x00000000},
18645 + {0x00009fc0, 0x803e4788},
18646 + {0x00009fc4, 0x0001efb5},
18647 + {0x00009fcc, 0x40000014},
18648 + {0x00009fd0, 0x01193b93},
18649 + {0x0000a20c, 0x00000000},
18650 + {0x0000a220, 0x00000000},
18651 + {0x0000a224, 0x00000000},
18652 + {0x0000a228, 0x10002310},
18653 + {0x0000a22c, 0x01036a1e},
18654 + {0x0000a234, 0x10000fff},
18655 + {0x0000a23c, 0x00000000},
18656 + {0x0000a244, 0x0c000000},
18657 + {0x0000a2a0, 0x00000001},
18658 + {0x0000a2c0, 0x00000001},
18659 + {0x0000a2c8, 0x00000000},
18660 + {0x0000a2cc, 0x18c43433},
18661 + {0x0000a2d4, 0x00000000},
18662 + {0x0000a2dc, 0x00000000},
18663 + {0x0000a2e0, 0x00000000},
18664 + {0x0000a2e4, 0x00000000},
18665 + {0x0000a2e8, 0x00000000},
18666 + {0x0000a2ec, 0x00000000},
18667 + {0x0000a2f0, 0x00000000},
18668 + {0x0000a2f4, 0x00000000},
18669 + {0x0000a2f8, 0x00000000},
18670 + {0x0000a344, 0x00000000},
18671 + {0x0000a34c, 0x00000000},
18672 + {0x0000a350, 0x0000a000},
18673 + {0x0000a364, 0x00000000},
18674 + {0x0000a370, 0x00000000},
18675 + {0x0000a390, 0x00000001},
18676 + {0x0000a394, 0x00000444},
18677 + {0x0000a398, 0x001f0e0f},
18678 + {0x0000a39c, 0x0075393f},
18679 + {0x0000a3a0, 0xb79f6427},
18680 + {0x0000a3a4, 0x00000000},
18681 + {0x0000a3a8, 0xaaaaaaaa},
18682 + {0x0000a3ac, 0x3c466478},
18683 + {0x0000a3c0, 0x20202020},
18684 + {0x0000a3c4, 0x22222220},
18685 + {0x0000a3c8, 0x20200020},
18686 + {0x0000a3cc, 0x20202020},
18687 + {0x0000a3d0, 0x20202020},
18688 + {0x0000a3d4, 0x20202020},
18689 + {0x0000a3d8, 0x20202020},
18690 + {0x0000a3dc, 0x20202020},
18691 + {0x0000a3e0, 0x20202020},
18692 + {0x0000a3e4, 0x20202020},
18693 + {0x0000a3e8, 0x20202020},
18694 + {0x0000a3ec, 0x20202020},
18695 + {0x0000a3f0, 0x00000000},
18696 + {0x0000a3f4, 0x00000246},
18697 + {0x0000a3f8, 0x0cdbd380},
18698 + {0x0000a3fc, 0x000f0f01},
18699 + {0x0000a400, 0x8fa91f01},
18700 + {0x0000a404, 0x00000000},
18701 + {0x0000a408, 0x0e79e5c6},
18702 + {0x0000a40c, 0x00820820},
18703 + {0x0000a414, 0x1ce739ce},
18704 + {0x0000a418, 0x7d001dce},
18705 + {0x0000a41c, 0x1ce739ce},
18706 + {0x0000a420, 0x000001ce},
18707 + {0x0000a424, 0x1ce739ce},
18708 + {0x0000a428, 0x000001ce},
18709 + {0x0000a42c, 0x1ce739ce},
18710 + {0x0000a430, 0x1ce739ce},
18711 + {0x0000a434, 0x00000000},
18712 + {0x0000a438, 0x00001801},
18713 + {0x0000a43c, 0x00000000},
18714 + {0x0000a440, 0x00000000},
18715 + {0x0000a444, 0x00000000},
18716 + {0x0000a448, 0x07000080},
18717 + {0x0000a44c, 0x00000001},
18718 + {0x0000a450, 0x00010000},
18719 + {0x0000a458, 0x00000000},
18720 + {0x0000a600, 0x00000000},
18721 + {0x0000a604, 0x00000000},
18722 + {0x0000a608, 0x00000000},
18723 + {0x0000a60c, 0x00000000},
18724 + {0x0000a610, 0x00000000},
18725 + {0x0000a614, 0x00000000},
18726 + {0x0000a618, 0x00000000},
18727 + {0x0000a61c, 0x00000000},
18728 + {0x0000a620, 0x00000000},
18729 + {0x0000a624, 0x00000000},
18730 + {0x0000a628, 0x00000000},
18731 + {0x0000a62c, 0x00000000},
18732 + {0x0000a630, 0x00000000},
18733 + {0x0000a634, 0x00000000},
18734 + {0x0000a638, 0x00000000},
18735 + {0x0000a63c, 0x00000000},
18736 + {0x0000a640, 0x00000000},
18737 + {0x0000a644, 0x3ffd9d74},
18738 + {0x0000a648, 0x0048060a},
18739 + {0x0000a64c, 0x00000637},
18740 + {0x0000a670, 0x03020100},
18741 + {0x0000a674, 0x09080504},
18742 + {0x0000a678, 0x0d0c0b0a},
18743 + {0x0000a67c, 0x13121110},
18744 + {0x0000a680, 0x31301514},
18745 + {0x0000a684, 0x35343332},
18746 + {0x0000a688, 0x00000036},
18747 + {0x0000a690, 0x00000838},
18748 + {0x0000a7c0, 0x00000000},
18749 + {0x0000a7c4, 0xfffffffc},
18750 + {0x0000a7c8, 0x00000000},
18751 + {0x0000a7cc, 0x00000000},
18752 + {0x0000a7d0, 0x00000000},
18753 + {0x0000a7d4, 0x00000004},
18754 + {0x0000a7dc, 0x00000001},
18755 + {0x0000a8d0, 0x004b6a8e},
18756 + {0x0000a8d4, 0x00000820},
18757 + {0x0000a8dc, 0x00000000},
18758 + {0x0000a8f0, 0x00000000},
18759 + {0x0000a8f4, 0x00000000},
18760 + {0x0000b2d0, 0x00000080},
18761 + {0x0000b2d4, 0x00000000},
18762 + {0x0000b2dc, 0x00000000},
18763 + {0x0000b2e0, 0x00000000},
18764 + {0x0000b2e4, 0x00000000},
18765 + {0x0000b2e8, 0x00000000},
18766 + {0x0000b2ec, 0x00000000},
18767 + {0x0000b2f0, 0x00000000},
18768 + {0x0000b2f4, 0x00000000},
18769 + {0x0000b2f8, 0x00000000},
18770 + {0x0000b408, 0x0e79e5c0},
18771 + {0x0000b40c, 0x00820820},
18772 + {0x0000b420, 0x00000000},
18773 + {0x0000b8d0, 0x004b6a8e},
18774 + {0x0000b8d4, 0x00000820},
18775 + {0x0000b8dc, 0x00000000},
18776 + {0x0000b8f0, 0x00000000},
18777 + {0x0000b8f4, 0x00000000},
18778 + {0x0000c2d0, 0x00000080},
18779 + {0x0000c2d4, 0x00000000},
18780 + {0x0000c2dc, 0x00000000},
18781 + {0x0000c2e0, 0x00000000},
18782 + {0x0000c2e4, 0x00000000},
18783 + {0x0000c2e8, 0x00000000},
18784 + {0x0000c2ec, 0x00000000},
18785 + {0x0000c2f0, 0x00000000},
18786 + {0x0000c2f4, 0x00000000},
18787 + {0x0000c2f8, 0x00000000},
18788 + {0x0000c408, 0x0e79e5c0},
18789 + {0x0000c40c, 0x00820820},
18790 + {0x0000c420, 0x00000000},
18791 +};
18792 +
18793 +static const u32 ar9300Modes_high_power_tx_gain_table_2p0[][5] = {
18794 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
18795 + {0x0000a410, 0x000050d9, 0x000050d9, 0x000050da, 0x000050da},
18796 + {0x0000a500, 0x00020220, 0x00020220, 0x00000000, 0x00000000},
18797 + {0x0000a504, 0x06020223, 0x06020223, 0x04000002, 0x04000002},
18798 + {0x0000a508, 0x0b022220, 0x0b022220, 0x08000004, 0x08000004},
18799 + {0x0000a50c, 0x10022223, 0x10022223, 0x0b000200, 0x0b000200},
18800 + {0x0000a510, 0x17022620, 0x17022620, 0x0f000202, 0x0f000202},
18801 + {0x0000a514, 0x1b022622, 0x1b022622, 0x11000400, 0x11000400},
18802 + {0x0000a518, 0x1f022822, 0x1f022822, 0x15000402, 0x15000402},
18803 + {0x0000a51c, 0x24022842, 0x24022842, 0x19000404, 0x19000404},
18804 + {0x0000a520, 0x28042840, 0x28042840, 0x1b000603, 0x1b000603},
18805 + {0x0000a524, 0x2c042842, 0x2c042842, 0x1f000a02, 0x1f000a02},
18806 + {0x0000a528, 0x30042844, 0x30042844, 0x23000a04, 0x23000a04},
18807 + {0x0000a52c, 0x34042846, 0x34042846, 0x26000a20, 0x26000a20},
18808 + {0x0000a530, 0x39042869, 0x39042869, 0x2a000e20, 0x2a000e20},
18809 + {0x0000a534, 0x3d062869, 0x3d062869, 0x2e000e22, 0x2e000e22},
18810 + {0x0000a538, 0x44062c69, 0x44062c69, 0x31000e24, 0x31000e24},
18811 + {0x0000a53c, 0x48063069, 0x48063069, 0x34001640, 0x34001640},
18812 + {0x0000a540, 0x4c0a3065, 0x4c0a3065, 0x38001660, 0x38001660},
18813 + {0x0000a544, 0x500a3069, 0x500a3069, 0x3b001861, 0x3b001861},
18814 + {0x0000a548, 0x530a3469, 0x530a3469, 0x3e001a81, 0x3e001a81},
18815 + {0x0000a54c, 0x590a7464, 0x590a7464, 0x42001a83, 0x42001a83},
18816 + {0x0000a550, 0x5e0a7865, 0x5e0a7865, 0x44001c84, 0x44001c84},
18817 + {0x0000a554, 0x630a7e66, 0x630a7e66, 0x48001ce3, 0x48001ce3},
18818 + {0x0000a558, 0x680a7e89, 0x680a7e89, 0x4c001ce5, 0x4c001ce5},
18819 + {0x0000a55c, 0x6e0a7e8c, 0x6e0a7e8c, 0x50001ce9, 0x50001ce9},
18820 + {0x0000a560, 0x730e7e8c, 0x730e7e8c, 0x54001ceb, 0x54001ceb},
18821 + {0x0000a564, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18822 + {0x0000a568, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18823 + {0x0000a56c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18824 + {0x0000a570, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18825 + {0x0000a574, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18826 + {0x0000a578, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18827 + {0x0000a57c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18828 + {0x0000a580, 0x00820220, 0x00820220, 0x00800000, 0x00800000},
18829 + {0x0000a584, 0x06820223, 0x06820223, 0x04800002, 0x04800002},
18830 + {0x0000a588, 0x0b822220, 0x0b822220, 0x08800004, 0x08800004},
18831 + {0x0000a58c, 0x10822223, 0x10822223, 0x0b800200, 0x0b800200},
18832 + {0x0000a590, 0x17822620, 0x17822620, 0x0f800202, 0x0f800202},
18833 + {0x0000a594, 0x1b822622, 0x1b822622, 0x11800400, 0x11800400},
18834 + {0x0000a598, 0x1f822822, 0x1f822822, 0x15800402, 0x15800402},
18835 + {0x0000a59c, 0x24822842, 0x24822842, 0x19800404, 0x19800404},
18836 + {0x0000a5a0, 0x28842840, 0x28842840, 0x1b800603, 0x1b800603},
18837 + {0x0000a5a4, 0x2c842842, 0x2c842842, 0x1f800a02, 0x1f800a02},
18838 + {0x0000a5a8, 0x30842844, 0x30842844, 0x23800a04, 0x23800a04},
18839 + {0x0000a5ac, 0x34842846, 0x34842846, 0x26800a20, 0x26800a20},
18840 + {0x0000a5b0, 0x39842869, 0x39842869, 0x2a800e20, 0x2a800e20},
18841 + {0x0000a5b4, 0x3d862869, 0x3d862869, 0x2e800e22, 0x2e800e22},
18842 + {0x0000a5b8, 0x44862c69, 0x44862c69, 0x31800e24, 0x31800e24},
18843 + {0x0000a5bc, 0x48863069, 0x48863069, 0x34801640, 0x34801640},
18844 + {0x0000a5c0, 0x4c8a3065, 0x4c8a3065, 0x38801660, 0x38801660},
18845 + {0x0000a5c4, 0x508a3069, 0x508a3069, 0x3b801861, 0x3b801861},
18846 + {0x0000a5c8, 0x538a3469, 0x538a3469, 0x3e801a81, 0x3e801a81},
18847 + {0x0000a5cc, 0x598a7464, 0x598a7464, 0x42801a83, 0x42801a83},
18848 + {0x0000a5d0, 0x5e8a7865, 0x5e8a7865, 0x44801c84, 0x44801c84},
18849 + {0x0000a5d4, 0x638a7e66, 0x638a7e66, 0x48801ce3, 0x48801ce3},
18850 + {0x0000a5d8, 0x688a7e89, 0x688a7e89, 0x4c801ce5, 0x4c801ce5},
18851 + {0x0000a5dc, 0x6e8a7e8c, 0x6e8a7e8c, 0x50801ce9, 0x50801ce9},
18852 + {0x0000a5e0, 0x738e7e8c, 0x738e7e8c, 0x54801ceb, 0x54801ceb},
18853 + {0x0000a5e4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18854 + {0x0000a5e8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18855 + {0x0000a5ec, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18856 + {0x0000a5f0, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18857 + {0x0000a5f4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18858 + {0x0000a5f8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18859 + {0x0000a5fc, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18860 + {0x00016044, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
18861 + {0x00016048, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
18862 + {0x00016068, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
18863 + {0x00016444, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
18864 + {0x00016448, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
18865 + {0x00016468, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
18866 + {0x00016844, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
18867 + {0x00016848, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
18868 + {0x00016868, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
18869 +};
18870 +
18871 +static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p0[][5] = {
18872 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
18873 + {0x0000a410, 0x000050d9, 0x000050d9, 0x000050da, 0x000050da},
18874 + {0x0000a500, 0x00020220, 0x00020220, 0x00000000, 0x00000000},
18875 + {0x0000a504, 0x06020223, 0x06020223, 0x04000002, 0x04000002},
18876 + {0x0000a508, 0x0b022220, 0x0b022220, 0x08000004, 0x08000004},
18877 + {0x0000a50c, 0x10022223, 0x10022223, 0x0b000200, 0x0b000200},
18878 + {0x0000a510, 0x17022620, 0x17022620, 0x0f000202, 0x0f000202},
18879 + {0x0000a514, 0x1b022622, 0x1b022622, 0x11000400, 0x11000400},
18880 + {0x0000a518, 0x1f022822, 0x1f022822, 0x15000402, 0x15000402},
18881 + {0x0000a51c, 0x24022842, 0x24022842, 0x19000404, 0x19000404},
18882 + {0x0000a520, 0x28042840, 0x28042840, 0x1b000603, 0x1b000603},
18883 + {0x0000a524, 0x2c042842, 0x2c042842, 0x1f000a02, 0x1f000a02},
18884 + {0x0000a528, 0x30042844, 0x30042844, 0x23000a04, 0x23000a04},
18885 + {0x0000a52c, 0x34042846, 0x34042846, 0x26000a20, 0x26000a20},
18886 + {0x0000a530, 0x39042869, 0x39042869, 0x2a000e20, 0x2a000e20},
18887 + {0x0000a534, 0x3d062869, 0x3d062869, 0x2e000e22, 0x2e000e22},
18888 + {0x0000a538, 0x44062c69, 0x44062c69, 0x31000e24, 0x31000e24},
18889 + {0x0000a53c, 0x48063069, 0x48063069, 0x34001640, 0x34001640},
18890 + {0x0000a540, 0x4c0a3065, 0x4c0a3065, 0x38001660, 0x38001660},
18891 + {0x0000a544, 0x500a3069, 0x500a3069, 0x3b001861, 0x3b001861},
18892 + {0x0000a548, 0x530a3469, 0x530a3469, 0x3e001a81, 0x3e001a81},
18893 + {0x0000a54c, 0x590a7464, 0x590a7464, 0x42001a83, 0x42001a83},
18894 + {0x0000a550, 0x5e0a7865, 0x5e0a7865, 0x44001c84, 0x44001c84},
18895 + {0x0000a554, 0x630a7e66, 0x630a7e66, 0x48001ce3, 0x48001ce3},
18896 + {0x0000a558, 0x680a7e89, 0x680a7e89, 0x4c001ce5, 0x4c001ce5},
18897 + {0x0000a55c, 0x6e0a7e8c, 0x6e0a7e8c, 0x50001ce9, 0x50001ce9},
18898 + {0x0000a560, 0x730e7e8c, 0x730e7e8c, 0x54001ceb, 0x54001ceb},
18899 + {0x0000a564, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18900 + {0x0000a568, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18901 + {0x0000a56c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18902 + {0x0000a570, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18903 + {0x0000a574, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18904 + {0x0000a578, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18905 + {0x0000a57c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18906 + {0x0000a580, 0x00820220, 0x00820220, 0x00800000, 0x00800000},
18907 + {0x0000a584, 0x06820223, 0x06820223, 0x04800002, 0x04800002},
18908 + {0x0000a588, 0x0b822220, 0x0b822220, 0x08800004, 0x08800004},
18909 + {0x0000a58c, 0x10822223, 0x10822223, 0x0b800200, 0x0b800200},
18910 + {0x0000a590, 0x17822620, 0x17822620, 0x0f800202, 0x0f800202},
18911 + {0x0000a594, 0x1b822622, 0x1b822622, 0x11800400, 0x11800400},
18912 + {0x0000a598, 0x1f822822, 0x1f822822, 0x15800402, 0x15800402},
18913 + {0x0000a59c, 0x24822842, 0x24822842, 0x19800404, 0x19800404},
18914 + {0x0000a5a0, 0x28842840, 0x28842840, 0x1b800603, 0x1b800603},
18915 + {0x0000a5a4, 0x2c842842, 0x2c842842, 0x1f800a02, 0x1f800a02},
18916 + {0x0000a5a8, 0x30842844, 0x30842844, 0x23800a04, 0x23800a04},
18917 + {0x0000a5ac, 0x34842846, 0x34842846, 0x26800a20, 0x26800a20},
18918 + {0x0000a5b0, 0x39842869, 0x39842869, 0x2a800e20, 0x2a800e20},
18919 + {0x0000a5b4, 0x3d862869, 0x3d862869, 0x2e800e22, 0x2e800e22},
18920 + {0x0000a5b8, 0x44862c69, 0x44862c69, 0x31800e24, 0x31800e24},
18921 + {0x0000a5bc, 0x48863069, 0x48863069, 0x34801640, 0x34801640},
18922 + {0x0000a5c0, 0x4c8a3065, 0x4c8a3065, 0x38801660, 0x38801660},
18923 + {0x0000a5c4, 0x508a3069, 0x508a3069, 0x3b801861, 0x3b801861},
18924 + {0x0000a5c8, 0x538a3469, 0x538a3469, 0x3e801a81, 0x3e801a81},
18925 + {0x0000a5cc, 0x598a7464, 0x598a7464, 0x42801a83, 0x42801a83},
18926 + {0x0000a5d0, 0x5e8a7865, 0x5e8a7865, 0x44801c84, 0x44801c84},
18927 + {0x0000a5d4, 0x638a7e66, 0x638a7e66, 0x48801ce3, 0x48801ce3},
18928 + {0x0000a5d8, 0x688a7e89, 0x688a7e89, 0x4c801ce5, 0x4c801ce5},
18929 + {0x0000a5dc, 0x6e8a7e8c, 0x6e8a7e8c, 0x50801ce9, 0x50801ce9},
18930 + {0x0000a5e0, 0x738e7e8c, 0x738e7e8c, 0x54801ceb, 0x54801ceb},
18931 + {0x0000a5e4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18932 + {0x0000a5e8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18933 + {0x0000a5ec, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18934 + {0x0000a5f0, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18935 + {0x0000a5f4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18936 + {0x0000a5f8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18937 + {0x0000a5fc, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18938 + {0x00016044, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
18939 + {0x00016048, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
18940 + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
18941 + {0x00016444, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
18942 + {0x00016448, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
18943 + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
18944 + {0x00016844, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
18945 + {0x00016848, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
18946 + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
18947 +};
18948 +
18949 +static const u32 ar9300Common_rx_gain_table_2p0[][2] = {
18950 + /* Addr allmodes */
18951 + {0x0000a000, 0x00010000},
18952 + {0x0000a004, 0x00030002},
18953 + {0x0000a008, 0x00050004},
18954 + {0x0000a00c, 0x00810080},
18955 + {0x0000a010, 0x01800082},
18956 + {0x0000a014, 0x01820181},
18957 + {0x0000a018, 0x01840183},
18958 + {0x0000a01c, 0x01880185},
18959 + {0x0000a020, 0x018a0189},
18960 + {0x0000a024, 0x02850284},
18961 + {0x0000a028, 0x02890288},
18962 + {0x0000a02c, 0x028b028a},
18963 + {0x0000a030, 0x028d028c},
18964 + {0x0000a034, 0x02910290},
18965 + {0x0000a038, 0x02930292},
18966 + {0x0000a03c, 0x03910390},
18967 + {0x0000a040, 0x03930392},
18968 + {0x0000a044, 0x03950394},
18969 + {0x0000a048, 0x00000396},
18970 + {0x0000a04c, 0x00000000},
18971 + {0x0000a050, 0x00000000},
18972 + {0x0000a054, 0x00000000},
18973 + {0x0000a058, 0x00000000},
18974 + {0x0000a05c, 0x00000000},
18975 + {0x0000a060, 0x00000000},
18976 + {0x0000a064, 0x00000000},
18977 + {0x0000a068, 0x00000000},
18978 + {0x0000a06c, 0x00000000},
18979 + {0x0000a070, 0x00000000},
18980 + {0x0000a074, 0x00000000},
18981 + {0x0000a078, 0x00000000},
18982 + {0x0000a07c, 0x00000000},
18983 + {0x0000a080, 0x28282828},
18984 + {0x0000a084, 0x21212128},
18985 + {0x0000a088, 0x21212121},
18986 + {0x0000a08c, 0x1c1c1c21},
18987 + {0x0000a090, 0x1c1c1c1c},
18988 + {0x0000a094, 0x17171c1c},
18989 + {0x0000a098, 0x02020212},
18990 + {0x0000a09c, 0x02020202},
18991 + {0x0000a0a0, 0x00000000},
18992 + {0x0000a0a4, 0x00000000},
18993 + {0x0000a0a8, 0x00000000},
18994 + {0x0000a0ac, 0x00000000},
18995 + {0x0000a0b0, 0x00000000},
18996 + {0x0000a0b4, 0x00000000},
18997 + {0x0000a0b8, 0x00000000},
18998 + {0x0000a0bc, 0x00000000},
18999 + {0x0000a0c0, 0x001f0000},
19000 + {0x0000a0c4, 0x011f0100},
19001 + {0x0000a0c8, 0x011d011e},
19002 + {0x0000a0cc, 0x011b011c},
19003 + {0x0000a0d0, 0x02030204},
19004 + {0x0000a0d4, 0x02010202},
19005 + {0x0000a0d8, 0x021f0200},
19006 + {0x0000a0dc, 0x021d021e},
19007 + {0x0000a0e0, 0x03010302},
19008 + {0x0000a0e4, 0x031f0300},
19009 + {0x0000a0e8, 0x0402031e},
19010 + {0x0000a0ec, 0x04000401},
19011 + {0x0000a0f0, 0x041e041f},
19012 + {0x0000a0f4, 0x05010502},
19013 + {0x0000a0f8, 0x051f0500},
19014 + {0x0000a0fc, 0x0602051e},
19015 + {0x0000a100, 0x06000601},
19016 + {0x0000a104, 0x061e061f},
19017 + {0x0000a108, 0x0703061d},
19018 + {0x0000a10c, 0x07010702},
19019 + {0x0000a110, 0x00000700},
19020 + {0x0000a114, 0x00000000},
19021 + {0x0000a118, 0x00000000},
19022 + {0x0000a11c, 0x00000000},
19023 + {0x0000a120, 0x00000000},
19024 + {0x0000a124, 0x00000000},
19025 + {0x0000a128, 0x00000000},
19026 + {0x0000a12c, 0x00000000},
19027 + {0x0000a130, 0x00000000},
19028 + {0x0000a134, 0x00000000},
19029 + {0x0000a138, 0x00000000},
19030 + {0x0000a13c, 0x00000000},
19031 + {0x0000a140, 0x001f0000},
19032 + {0x0000a144, 0x011f0100},
19033 + {0x0000a148, 0x011d011e},
19034 + {0x0000a14c, 0x011b011c},
19035 + {0x0000a150, 0x02030204},
19036 + {0x0000a154, 0x02010202},
19037 + {0x0000a158, 0x021f0200},
19038 + {0x0000a15c, 0x021d021e},
19039 + {0x0000a160, 0x03010302},
19040 + {0x0000a164, 0x031f0300},
19041 + {0x0000a168, 0x0402031e},
19042 + {0x0000a16c, 0x04000401},
19043 + {0x0000a170, 0x041e041f},
19044 + {0x0000a174, 0x05010502},
19045 + {0x0000a178, 0x051f0500},
19046 + {0x0000a17c, 0x0602051e},
19047 + {0x0000a180, 0x06000601},
19048 + {0x0000a184, 0x061e061f},
19049 + {0x0000a188, 0x0703061d},
19050 + {0x0000a18c, 0x07010702},
19051 + {0x0000a190, 0x00000700},
19052 + {0x0000a194, 0x00000000},
19053 + {0x0000a198, 0x00000000},
19054 + {0x0000a19c, 0x00000000},
19055 + {0x0000a1a0, 0x00000000},
19056 + {0x0000a1a4, 0x00000000},
19057 + {0x0000a1a8, 0x00000000},
19058 + {0x0000a1ac, 0x00000000},
19059 + {0x0000a1b0, 0x00000000},
19060 + {0x0000a1b4, 0x00000000},
19061 + {0x0000a1b8, 0x00000000},
19062 + {0x0000a1bc, 0x00000000},
19063 + {0x0000a1c0, 0x00000000},
19064 + {0x0000a1c4, 0x00000000},
19065 + {0x0000a1c8, 0x00000000},
19066 + {0x0000a1cc, 0x00000000},
19067 + {0x0000a1d0, 0x00000000},
19068 + {0x0000a1d4, 0x00000000},
19069 + {0x0000a1d8, 0x00000000},
19070 + {0x0000a1dc, 0x00000000},
19071 + {0x0000a1e0, 0x00000000},
19072 + {0x0000a1e4, 0x00000000},
19073 + {0x0000a1e8, 0x00000000},
19074 + {0x0000a1ec, 0x00000000},
19075 + {0x0000a1f0, 0x00000396},
19076 + {0x0000a1f4, 0x00000396},
19077 + {0x0000a1f8, 0x00000396},
19078 + {0x0000a1fc, 0x00000196},
19079 + {0x0000b000, 0x00010000},
19080 + {0x0000b004, 0x00030002},
19081 + {0x0000b008, 0x00050004},
19082 + {0x0000b00c, 0x00810080},
19083 + {0x0000b010, 0x00830082},
19084 + {0x0000b014, 0x01810180},
19085 + {0x0000b018, 0x01830182},
19086 + {0x0000b01c, 0x01850184},
19087 + {0x0000b020, 0x02810280},
19088 + {0x0000b024, 0x02830282},
19089 + {0x0000b028, 0x02850284},
19090 + {0x0000b02c, 0x02890288},
19091 + {0x0000b030, 0x028b028a},
19092 + {0x0000b034, 0x0388028c},
19093 + {0x0000b038, 0x038a0389},
19094 + {0x0000b03c, 0x038c038b},
19095 + {0x0000b040, 0x0390038d},
19096 + {0x0000b044, 0x03920391},
19097 + {0x0000b048, 0x03940393},
19098 + {0x0000b04c, 0x03960395},
19099 + {0x0000b050, 0x00000000},
19100 + {0x0000b054, 0x00000000},
19101 + {0x0000b058, 0x00000000},
19102 + {0x0000b05c, 0x00000000},
19103 + {0x0000b060, 0x00000000},
19104 + {0x0000b064, 0x00000000},
19105 + {0x0000b068, 0x00000000},
19106 + {0x0000b06c, 0x00000000},
19107 + {0x0000b070, 0x00000000},
19108 + {0x0000b074, 0x00000000},
19109 + {0x0000b078, 0x00000000},
19110 + {0x0000b07c, 0x00000000},
19111 + {0x0000b080, 0x32323232},
19112 + {0x0000b084, 0x2f2f3232},
19113 + {0x0000b088, 0x23282a2d},
19114 + {0x0000b08c, 0x1c1e2123},
19115 + {0x0000b090, 0x14171919},
19116 + {0x0000b094, 0x0e0e1214},
19117 + {0x0000b098, 0x03050707},
19118 + {0x0000b09c, 0x00030303},
19119 + {0x0000b0a0, 0x00000000},
19120 + {0x0000b0a4, 0x00000000},
19121 + {0x0000b0a8, 0x00000000},
19122 + {0x0000b0ac, 0x00000000},
19123 + {0x0000b0b0, 0x00000000},
19124 + {0x0000b0b4, 0x00000000},
19125 + {0x0000b0b8, 0x00000000},
19126 + {0x0000b0bc, 0x00000000},
19127 + {0x0000b0c0, 0x003f0020},
19128 + {0x0000b0c4, 0x00400041},
19129 + {0x0000b0c8, 0x0140005f},
19130 + {0x0000b0cc, 0x0160015f},
19131 + {0x0000b0d0, 0x017e017f},
19132 + {0x0000b0d4, 0x02410242},
19133 + {0x0000b0d8, 0x025f0240},
19134 + {0x0000b0dc, 0x027f0260},
19135 + {0x0000b0e0, 0x0341027e},
19136 + {0x0000b0e4, 0x035f0340},
19137 + {0x0000b0e8, 0x037f0360},
19138 + {0x0000b0ec, 0x04400441},
19139 + {0x0000b0f0, 0x0460045f},
19140 + {0x0000b0f4, 0x0541047f},
19141 + {0x0000b0f8, 0x055f0540},
19142 + {0x0000b0fc, 0x057f0560},
19143 + {0x0000b100, 0x06400641},
19144 + {0x0000b104, 0x0660065f},
19145 + {0x0000b108, 0x067e067f},
19146 + {0x0000b10c, 0x07410742},
19147 + {0x0000b110, 0x075f0740},
19148 + {0x0000b114, 0x077f0760},
19149 + {0x0000b118, 0x07800781},
19150 + {0x0000b11c, 0x07a0079f},
19151 + {0x0000b120, 0x07c107bf},
19152 + {0x0000b124, 0x000007c0},
19153 + {0x0000b128, 0x00000000},
19154 + {0x0000b12c, 0x00000000},
19155 + {0x0000b130, 0x00000000},
19156 + {0x0000b134, 0x00000000},
19157 + {0x0000b138, 0x00000000},
19158 + {0x0000b13c, 0x00000000},
19159 + {0x0000b140, 0x003f0020},
19160 + {0x0000b144, 0x00400041},
19161 + {0x0000b148, 0x0140005f},
19162 + {0x0000b14c, 0x0160015f},
19163 + {0x0000b150, 0x017e017f},
19164 + {0x0000b154, 0x02410242},
19165 + {0x0000b158, 0x025f0240},
19166 + {0x0000b15c, 0x027f0260},
19167 + {0x0000b160, 0x0341027e},
19168 + {0x0000b164, 0x035f0340},
19169 + {0x0000b168, 0x037f0360},
19170 + {0x0000b16c, 0x04400441},
19171 + {0x0000b170, 0x0460045f},
19172 + {0x0000b174, 0x0541047f},
19173 + {0x0000b178, 0x055f0540},
19174 + {0x0000b17c, 0x057f0560},
19175 + {0x0000b180, 0x06400641},
19176 + {0x0000b184, 0x0660065f},
19177 + {0x0000b188, 0x067e067f},
19178 + {0x0000b18c, 0x07410742},
19179 + {0x0000b190, 0x075f0740},
19180 + {0x0000b194, 0x077f0760},
19181 + {0x0000b198, 0x07800781},
19182 + {0x0000b19c, 0x07a0079f},
19183 + {0x0000b1a0, 0x07c107bf},
19184 + {0x0000b1a4, 0x000007c0},
19185 + {0x0000b1a8, 0x00000000},
19186 + {0x0000b1ac, 0x00000000},
19187 + {0x0000b1b0, 0x00000000},
19188 + {0x0000b1b4, 0x00000000},
19189 + {0x0000b1b8, 0x00000000},
19190 + {0x0000b1bc, 0x00000000},
19191 + {0x0000b1c0, 0x00000000},
19192 + {0x0000b1c4, 0x00000000},
19193 + {0x0000b1c8, 0x00000000},
19194 + {0x0000b1cc, 0x00000000},
19195 + {0x0000b1d0, 0x00000000},
19196 + {0x0000b1d4, 0x00000000},
19197 + {0x0000b1d8, 0x00000000},
19198 + {0x0000b1dc, 0x00000000},
19199 + {0x0000b1e0, 0x00000000},
19200 + {0x0000b1e4, 0x00000000},
19201 + {0x0000b1e8, 0x00000000},
19202 + {0x0000b1ec, 0x00000000},
19203 + {0x0000b1f0, 0x00000396},
19204 + {0x0000b1f4, 0x00000396},
19205 + {0x0000b1f8, 0x00000396},
19206 + {0x0000b1fc, 0x00000196},
19207 +};
19208 +
19209 +static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p0[][5] = {
19210 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
19211 + {0x0000a410, 0x000050da, 0x000050da, 0x000050da, 0x000050da},
19212 + {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
19213 + {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
19214 + {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
19215 + {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
19216 + {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
19217 + {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
19218 + {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
19219 + {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
19220 + {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
19221 + {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
19222 + {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
19223 + {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
19224 + {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
19225 + {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
19226 + {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
19227 + {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
19228 + {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
19229 + {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
19230 + {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
19231 + {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
19232 + {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
19233 + {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
19234 + {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
19235 + {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
19236 + {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
19237 + {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
19238 + {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
19239 + {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
19240 + {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
19241 + {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
19242 + {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
19243 + {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
19244 + {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
19245 + {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
19246 + {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
19247 + {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
19248 + {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
19249 + {0x0000a594, 0x1c800223, 0x1c800223, 0x12800400, 0x12800400},
19250 + {0x0000a598, 0x21820220, 0x21820220, 0x16800402, 0x16800402},
19251 + {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
19252 + {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1c800603, 0x1c800603},
19253 + {0x0000a5a4, 0x2f822222, 0x2f822222, 0x21800a02, 0x21800a02},
19254 + {0x0000a5a8, 0x34822225, 0x34822225, 0x25800a04, 0x25800a04},
19255 + {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x28800a20, 0x28800a20},
19256 + {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2c800e20, 0x2c800e20},
19257 + {0x0000a5b4, 0x4282242a, 0x4282242a, 0x30800e22, 0x30800e22},
19258 + {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
19259 + {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
19260 + {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
19261 + {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
19262 + {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
19263 + {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x47801a83, 0x47801a83},
19264 + {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x4a801c84, 0x4a801c84},
19265 + {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x4e801ce3, 0x4e801ce3},
19266 + {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x52801ce5, 0x52801ce5},
19267 + {0x0000a5dc, 0x7086308c, 0x7086308c, 0x56801ce9, 0x56801ce9},
19268 + {0x0000a5e0, 0x738a308a, 0x738a308a, 0x5a801ceb, 0x5a801ceb},
19269 + {0x0000a5e4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
19270 + {0x0000a5e8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
19271 + {0x0000a5ec, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
19272 + {0x0000a5f0, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
19273 + {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
19274 + {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
19275 + {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
19276 + {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
19277 + {0x00016048, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
19278 + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
19279 + {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
19280 + {0x00016448, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
19281 + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
19282 + {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
19283 + {0x00016848, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
19284 + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
19285 +};
19286 +
19287 +static const u32 ar9300_2p0_mac_core[][2] = {
19288 + /* Addr allmodes */
19289 + {0x00000008, 0x00000000},
19290 + {0x00000030, 0x00020085},
19291 + {0x00000034, 0x00000005},
19292 + {0x00000040, 0x00000000},
19293 + {0x00000044, 0x00000000},
19294 + {0x00000048, 0x00000008},
19295 + {0x0000004c, 0x00000010},
19296 + {0x00000050, 0x00000000},
19297 + {0x00001040, 0x002ffc0f},
19298 + {0x00001044, 0x002ffc0f},
19299 + {0x00001048, 0x002ffc0f},
19300 + {0x0000104c, 0x002ffc0f},
19301 + {0x00001050, 0x002ffc0f},
19302 + {0x00001054, 0x002ffc0f},
19303 + {0x00001058, 0x002ffc0f},
19304 + {0x0000105c, 0x002ffc0f},
19305 + {0x00001060, 0x002ffc0f},
19306 + {0x00001064, 0x002ffc0f},
19307 + {0x000010f0, 0x00000100},
19308 + {0x00001270, 0x00000000},
19309 + {0x000012b0, 0x00000000},
19310 + {0x000012f0, 0x00000000},
19311 + {0x0000143c, 0x00000000},
19312 + {0x0000147c, 0x00000000},
19313 + {0x00008000, 0x00000000},
19314 + {0x00008004, 0x00000000},
19315 + {0x00008008, 0x00000000},
19316 + {0x0000800c, 0x00000000},
19317 + {0x00008018, 0x00000000},
19318 + {0x00008020, 0x00000000},
19319 + {0x00008038, 0x00000000},
19320 + {0x0000803c, 0x00000000},
19321 + {0x00008040, 0x00000000},
19322 + {0x00008044, 0x00000000},
19323 + {0x00008048, 0x00000000},
19324 + {0x0000804c, 0xffffffff},
19325 + {0x00008054, 0x00000000},
19326 + {0x00008058, 0x00000000},
19327 + {0x0000805c, 0x000fc78f},
19328 + {0x00008060, 0x0000000f},
19329 + {0x00008064, 0x00000000},
19330 + {0x00008070, 0x00000310},
19331 + {0x00008074, 0x00000020},
19332 + {0x00008078, 0x00000000},
19333 + {0x0000809c, 0x0000000f},
19334 + {0x000080a0, 0x00000000},
19335 + {0x000080a4, 0x02ff0000},
19336 + {0x000080a8, 0x0e070605},
19337 + {0x000080ac, 0x0000000d},
19338 + {0x000080b0, 0x00000000},
19339 + {0x000080b4, 0x00000000},
19340 + {0x000080b8, 0x00000000},
19341 + {0x000080bc, 0x00000000},
19342 + {0x000080c0, 0x2a800000},
19343 + {0x000080c4, 0x06900168},
19344 + {0x000080c8, 0x13881c20},
19345 + {0x000080cc, 0x01f40000},
19346 + {0x000080d0, 0x00252500},
19347 + {0x000080d4, 0x00a00000},
19348 + {0x000080d8, 0x00400000},
19349 + {0x000080dc, 0x00000000},
19350 + {0x000080e0, 0xffffffff},
19351 + {0x000080e4, 0x0000ffff},
19352 + {0x000080e8, 0x3f3f3f3f},
19353 + {0x000080ec, 0x00000000},
19354 + {0x000080f0, 0x00000000},
19355 + {0x000080f4, 0x00000000},
19356 + {0x000080fc, 0x00020000},
19357 + {0x00008100, 0x00000000},
19358 + {0x00008108, 0x00000052},
19359 + {0x0000810c, 0x00000000},
19360 + {0x00008110, 0x00000000},
19361 + {0x00008114, 0x000007ff},
19362 + {0x00008118, 0x000000aa},
19363 + {0x0000811c, 0x00003210},
19364 + {0x00008124, 0x00000000},
19365 + {0x00008128, 0x00000000},
19366 + {0x0000812c, 0x00000000},
19367 + {0x00008130, 0x00000000},
19368 + {0x00008134, 0x00000000},
19369 + {0x00008138, 0x00000000},
19370 + {0x0000813c, 0x0000ffff},
19371 + {0x00008144, 0xffffffff},
19372 + {0x00008168, 0x00000000},
19373 + {0x0000816c, 0x00000000},
19374 + {0x00008170, 0x18486200},
19375 + {0x00008174, 0x33332210},
19376 + {0x00008178, 0x00000000},
19377 + {0x0000817c, 0x00020000},
19378 + {0x000081c0, 0x00000000},
19379 + {0x000081c4, 0x33332210},
19380 + {0x000081c8, 0x00000000},
19381 + {0x000081cc, 0x00000000},
19382 + {0x000081d4, 0x00000000},
19383 + {0x000081ec, 0x00000000},
19384 + {0x000081f0, 0x00000000},
19385 + {0x000081f4, 0x00000000},
19386 + {0x000081f8, 0x00000000},
19387 + {0x000081fc, 0x00000000},
19388 + {0x00008240, 0x00100000},
19389 + {0x00008244, 0x0010f424},
19390 + {0x00008248, 0x00000800},
19391 + {0x0000824c, 0x0001e848},
19392 + {0x00008250, 0x00000000},
19393 + {0x00008254, 0x00000000},
19394 + {0x00008258, 0x00000000},
19395 + {0x0000825c, 0x40000000},
19396 + {0x00008260, 0x00080922},
19397 + {0x00008264, 0x98a00010},
19398 + {0x00008268, 0xffffffff},
19399 + {0x0000826c, 0x0000ffff},
19400 + {0x00008270, 0x00000000},
19401 + {0x00008274, 0x40000000},
19402 + {0x00008278, 0x003e4180},
19403 + {0x0000827c, 0x00000004},
19404 + {0x00008284, 0x0000002c},
19405 + {0x00008288, 0x0000002c},
19406 + {0x0000828c, 0x000000ff},
19407 + {0x00008294, 0x00000000},
19408 + {0x00008298, 0x00000000},
19409 + {0x0000829c, 0x00000000},
19410 + {0x00008300, 0x00000140},
19411 + {0x00008314, 0x00000000},
19412 + {0x0000831c, 0x0000010d},
19413 + {0x00008328, 0x00000000},
19414 + {0x0000832c, 0x00000007},
19415 + {0x00008330, 0x00000302},
19416 + {0x00008334, 0x00000700},
19417 + {0x00008338, 0x00ff0000},
19418 + {0x0000833c, 0x02400000},
19419 + {0x00008340, 0x000107ff},
19420 + {0x00008344, 0xaa48105b},
19421 + {0x00008348, 0x008f0000},
19422 + {0x0000835c, 0x00000000},
19423 + {0x00008360, 0xffffffff},
19424 + {0x00008364, 0xffffffff},
19425 + {0x00008368, 0x00000000},
19426 + {0x00008370, 0x00000000},
19427 + {0x00008374, 0x000000ff},
19428 + {0x00008378, 0x00000000},
19429 + {0x0000837c, 0x00000000},
19430 + {0x00008380, 0xffffffff},
19431 + {0x00008384, 0xffffffff},
19432 + {0x00008390, 0xffffffff},
19433 + {0x00008394, 0xffffffff},
19434 + {0x00008398, 0x00000000},
19435 + {0x0000839c, 0x00000000},
19436 + {0x000083a0, 0x00000000},
19437 + {0x000083a4, 0x0000fa14},
19438 + {0x000083a8, 0x000f0c00},
19439 + {0x000083ac, 0x33332210},
19440 + {0x000083b0, 0x33332210},
19441 + {0x000083b4, 0x33332210},
19442 + {0x000083b8, 0x33332210},
19443 + {0x000083bc, 0x00000000},
19444 + {0x000083c0, 0x00000000},
19445 + {0x000083c4, 0x00000000},
19446 + {0x000083c8, 0x00000000},
19447 + {0x000083cc, 0x00000200},
19448 + {0x000083d0, 0x000301ff},
19449 +};
19450 +
19451 +static const u32 ar9300Common_wo_xlna_rx_gain_table_2p0[][2] = {
19452 + /* Addr allmodes */
19453 + {0x0000a000, 0x00010000},
19454 + {0x0000a004, 0x00030002},
19455 + {0x0000a008, 0x00050004},
19456 + {0x0000a00c, 0x00810080},
19457 + {0x0000a010, 0x01800082},
19458 + {0x0000a014, 0x01820181},
19459 + {0x0000a018, 0x01840183},
19460 + {0x0000a01c, 0x01880185},
19461 + {0x0000a020, 0x018a0189},
19462 + {0x0000a024, 0x02850284},
19463 + {0x0000a028, 0x02890288},
19464 + {0x0000a02c, 0x03850384},
19465 + {0x0000a030, 0x03890388},
19466 + {0x0000a034, 0x038b038a},
19467 + {0x0000a038, 0x038d038c},
19468 + {0x0000a03c, 0x03910390},
19469 + {0x0000a040, 0x03930392},
19470 + {0x0000a044, 0x03950394},
19471 + {0x0000a048, 0x00000396},
19472 + {0x0000a04c, 0x00000000},
19473 + {0x0000a050, 0x00000000},
19474 + {0x0000a054, 0x00000000},
19475 + {0x0000a058, 0x00000000},
19476 + {0x0000a05c, 0x00000000},
19477 + {0x0000a060, 0x00000000},
19478 + {0x0000a064, 0x00000000},
19479 + {0x0000a068, 0x00000000},
19480 + {0x0000a06c, 0x00000000},
19481 + {0x0000a070, 0x00000000},
19482 + {0x0000a074, 0x00000000},
19483 + {0x0000a078, 0x00000000},
19484 + {0x0000a07c, 0x00000000},
19485 + {0x0000a080, 0x28282828},
19486 + {0x0000a084, 0x28282828},
19487 + {0x0000a088, 0x28282828},
19488 + {0x0000a08c, 0x28282828},
19489 + {0x0000a090, 0x28282828},
19490 + {0x0000a094, 0x21212128},
19491 + {0x0000a098, 0x171c1c1c},
19492 + {0x0000a09c, 0x02020212},
19493 + {0x0000a0a0, 0x00000202},
19494 + {0x0000a0a4, 0x00000000},
19495 + {0x0000a0a8, 0x00000000},
19496 + {0x0000a0ac, 0x00000000},
19497 + {0x0000a0b0, 0x00000000},
19498 + {0x0000a0b4, 0x00000000},
19499 + {0x0000a0b8, 0x00000000},
19500 + {0x0000a0bc, 0x00000000},
19501 + {0x0000a0c0, 0x001f0000},
19502 + {0x0000a0c4, 0x011f0100},
19503 + {0x0000a0c8, 0x011d011e},
19504 + {0x0000a0cc, 0x011b011c},
19505 + {0x0000a0d0, 0x02030204},
19506 + {0x0000a0d4, 0x02010202},
19507 + {0x0000a0d8, 0x021f0200},
19508 + {0x0000a0dc, 0x021d021e},
19509 + {0x0000a0e0, 0x03010302},
19510 + {0x0000a0e4, 0x031f0300},
19511 + {0x0000a0e8, 0x0402031e},
19512 + {0x0000a0ec, 0x04000401},
19513 + {0x0000a0f0, 0x041e041f},
19514 + {0x0000a0f4, 0x05010502},
19515 + {0x0000a0f8, 0x051f0500},
19516 + {0x0000a0fc, 0x0602051e},
19517 + {0x0000a100, 0x06000601},
19518 + {0x0000a104, 0x061e061f},
19519 + {0x0000a108, 0x0703061d},
19520 + {0x0000a10c, 0x07010702},
19521 + {0x0000a110, 0x00000700},
19522 + {0x0000a114, 0x00000000},
19523 + {0x0000a118, 0x00000000},
19524 + {0x0000a11c, 0x00000000},
19525 + {0x0000a120, 0x00000000},
19526 + {0x0000a124, 0x00000000},
19527 + {0x0000a128, 0x00000000},
19528 + {0x0000a12c, 0x00000000},
19529 + {0x0000a130, 0x00000000},
19530 + {0x0000a134, 0x00000000},
19531 + {0x0000a138, 0x00000000},
19532 + {0x0000a13c, 0x00000000},
19533 + {0x0000a140, 0x001f0000},
19534 + {0x0000a144, 0x011f0100},
19535 + {0x0000a148, 0x011d011e},
19536 + {0x0000a14c, 0x011b011c},
19537 + {0x0000a150, 0x02030204},
19538 + {0x0000a154, 0x02010202},
19539 + {0x0000a158, 0x021f0200},
19540 + {0x0000a15c, 0x021d021e},
19541 + {0x0000a160, 0x03010302},
19542 + {0x0000a164, 0x031f0300},
19543 + {0x0000a168, 0x0402031e},
19544 + {0x0000a16c, 0x04000401},
19545 + {0x0000a170, 0x041e041f},
19546 + {0x0000a174, 0x05010502},
19547 + {0x0000a178, 0x051f0500},
19548 + {0x0000a17c, 0x0602051e},
19549 + {0x0000a180, 0x06000601},
19550 + {0x0000a184, 0x061e061f},
19551 + {0x0000a188, 0x0703061d},
19552 + {0x0000a18c, 0x07010702},
19553 + {0x0000a190, 0x00000700},
19554 + {0x0000a194, 0x00000000},
19555 + {0x0000a198, 0x00000000},
19556 + {0x0000a19c, 0x00000000},
19557 + {0x0000a1a0, 0x00000000},
19558 + {0x0000a1a4, 0x00000000},
19559 + {0x0000a1a8, 0x00000000},
19560 + {0x0000a1ac, 0x00000000},
19561 + {0x0000a1b0, 0x00000000},
19562 + {0x0000a1b4, 0x00000000},
19563 + {0x0000a1b8, 0x00000000},
19564 + {0x0000a1bc, 0x00000000},
19565 + {0x0000a1c0, 0x00000000},
19566 + {0x0000a1c4, 0x00000000},
19567 + {0x0000a1c8, 0x00000000},
19568 + {0x0000a1cc, 0x00000000},
19569 + {0x0000a1d0, 0x00000000},
19570 + {0x0000a1d4, 0x00000000},
19571 + {0x0000a1d8, 0x00000000},
19572 + {0x0000a1dc, 0x00000000},
19573 + {0x0000a1e0, 0x00000000},
19574 + {0x0000a1e4, 0x00000000},
19575 + {0x0000a1e8, 0x00000000},
19576 + {0x0000a1ec, 0x00000000},
19577 + {0x0000a1f0, 0x00000396},
19578 + {0x0000a1f4, 0x00000396},
19579 + {0x0000a1f8, 0x00000396},
19580 + {0x0000a1fc, 0x00000296},
19581 + {0x0000b000, 0x00010000},
19582 + {0x0000b004, 0x00030002},
19583 + {0x0000b008, 0x00050004},
19584 + {0x0000b00c, 0x00810080},
19585 + {0x0000b010, 0x00830082},
19586 + {0x0000b014, 0x01810180},
19587 + {0x0000b018, 0x01830182},
19588 + {0x0000b01c, 0x01850184},
19589 + {0x0000b020, 0x02810280},
19590 + {0x0000b024, 0x02830282},
19591 + {0x0000b028, 0x02850284},
19592 + {0x0000b02c, 0x02890288},
19593 + {0x0000b030, 0x028b028a},
19594 + {0x0000b034, 0x0388028c},
19595 + {0x0000b038, 0x038a0389},
19596 + {0x0000b03c, 0x038c038b},
19597 + {0x0000b040, 0x0390038d},
19598 + {0x0000b044, 0x03920391},
19599 + {0x0000b048, 0x03940393},
19600 + {0x0000b04c, 0x03960395},
19601 + {0x0000b050, 0x00000000},
19602 + {0x0000b054, 0x00000000},
19603 + {0x0000b058, 0x00000000},
19604 + {0x0000b05c, 0x00000000},
19605 + {0x0000b060, 0x00000000},
19606 + {0x0000b064, 0x00000000},
19607 + {0x0000b068, 0x00000000},
19608 + {0x0000b06c, 0x00000000},
19609 + {0x0000b070, 0x00000000},
19610 + {0x0000b074, 0x00000000},
19611 + {0x0000b078, 0x00000000},
19612 + {0x0000b07c, 0x00000000},
19613 + {0x0000b080, 0x32323232},
19614 + {0x0000b084, 0x2f2f3232},
19615 + {0x0000b088, 0x23282a2d},
19616 + {0x0000b08c, 0x1c1e2123},
19617 + {0x0000b090, 0x14171919},
19618 + {0x0000b094, 0x0e0e1214},
19619 + {0x0000b098, 0x03050707},
19620 + {0x0000b09c, 0x00030303},
19621 + {0x0000b0a0, 0x00000000},
19622 + {0x0000b0a4, 0x00000000},
19623 + {0x0000b0a8, 0x00000000},
19624 + {0x0000b0ac, 0x00000000},
19625 + {0x0000b0b0, 0x00000000},
19626 + {0x0000b0b4, 0x00000000},
19627 + {0x0000b0b8, 0x00000000},
19628 + {0x0000b0bc, 0x00000000},
19629 + {0x0000b0c0, 0x003f0020},
19630 + {0x0000b0c4, 0x00400041},
19631 + {0x0000b0c8, 0x0140005f},
19632 + {0x0000b0cc, 0x0160015f},
19633 + {0x0000b0d0, 0x017e017f},
19634 + {0x0000b0d4, 0x02410242},
19635 + {0x0000b0d8, 0x025f0240},
19636 + {0x0000b0dc, 0x027f0260},
19637 + {0x0000b0e0, 0x0341027e},
19638 + {0x0000b0e4, 0x035f0340},
19639 + {0x0000b0e8, 0x037f0360},
19640 + {0x0000b0ec, 0x04400441},
19641 + {0x0000b0f0, 0x0460045f},
19642 + {0x0000b0f4, 0x0541047f},
19643 + {0x0000b0f8, 0x055f0540},
19644 + {0x0000b0fc, 0x057f0560},
19645 + {0x0000b100, 0x06400641},
19646 + {0x0000b104, 0x0660065f},
19647 + {0x0000b108, 0x067e067f},
19648 + {0x0000b10c, 0x07410742},
19649 + {0x0000b110, 0x075f0740},
19650 + {0x0000b114, 0x077f0760},
19651 + {0x0000b118, 0x07800781},
19652 + {0x0000b11c, 0x07a0079f},
19653 + {0x0000b120, 0x07c107bf},
19654 + {0x0000b124, 0x000007c0},
19655 + {0x0000b128, 0x00000000},
19656 + {0x0000b12c, 0x00000000},
19657 + {0x0000b130, 0x00000000},
19658 + {0x0000b134, 0x00000000},
19659 + {0x0000b138, 0x00000000},
19660 + {0x0000b13c, 0x00000000},
19661 + {0x0000b140, 0x003f0020},
19662 + {0x0000b144, 0x00400041},
19663 + {0x0000b148, 0x0140005f},
19664 + {0x0000b14c, 0x0160015f},
19665 + {0x0000b150, 0x017e017f},
19666 + {0x0000b154, 0x02410242},
19667 + {0x0000b158, 0x025f0240},
19668 + {0x0000b15c, 0x027f0260},
19669 + {0x0000b160, 0x0341027e},
19670 + {0x0000b164, 0x035f0340},
19671 + {0x0000b168, 0x037f0360},
19672 + {0x0000b16c, 0x04400441},
19673 + {0x0000b170, 0x0460045f},
19674 + {0x0000b174, 0x0541047f},
19675 + {0x0000b178, 0x055f0540},
19676 + {0x0000b17c, 0x057f0560},
19677 + {0x0000b180, 0x06400641},
19678 + {0x0000b184, 0x0660065f},
19679 + {0x0000b188, 0x067e067f},
19680 + {0x0000b18c, 0x07410742},
19681 + {0x0000b190, 0x075f0740},
19682 + {0x0000b194, 0x077f0760},
19683 + {0x0000b198, 0x07800781},
19684 + {0x0000b19c, 0x07a0079f},
19685 + {0x0000b1a0, 0x07c107bf},
19686 + {0x0000b1a4, 0x000007c0},
19687 + {0x0000b1a8, 0x00000000},
19688 + {0x0000b1ac, 0x00000000},
19689 + {0x0000b1b0, 0x00000000},
19690 + {0x0000b1b4, 0x00000000},
19691 + {0x0000b1b8, 0x00000000},
19692 + {0x0000b1bc, 0x00000000},
19693 + {0x0000b1c0, 0x00000000},
19694 + {0x0000b1c4, 0x00000000},
19695 + {0x0000b1c8, 0x00000000},
19696 + {0x0000b1cc, 0x00000000},
19697 + {0x0000b1d0, 0x00000000},
19698 + {0x0000b1d4, 0x00000000},
19699 + {0x0000b1d8, 0x00000000},
19700 + {0x0000b1dc, 0x00000000},
19701 + {0x0000b1e0, 0x00000000},
19702 + {0x0000b1e4, 0x00000000},
19703 + {0x0000b1e8, 0x00000000},
19704 + {0x0000b1ec, 0x00000000},
19705 + {0x0000b1f0, 0x00000396},
19706 + {0x0000b1f4, 0x00000396},
19707 + {0x0000b1f8, 0x00000396},
19708 + {0x0000b1fc, 0x00000196},
19709 +};
19710 +
19711 +static const u32 ar9300_2p0_soc_preamble[][2] = {
19712 + /* Addr allmodes */
19713 + {0x000040a4, 0x00a0c1c9},
19714 + {0x00007008, 0x00000000},
19715 + {0x00007020, 0x00000000},
19716 + {0x00007034, 0x00000002},
19717 + {0x00007038, 0x000004c2},
19718 +};
19719 +
19720 +/*
19721 + * PCIE-PHY programming array, to be used prior to entering
19722 + * full sleep (holding RTC in reset, PLL is ON in L1 mode)
19723 + */
19724 +static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0[][2] = {
19725 + {0x00004040, 0x08212e5e},
19726 + {0x00004040, 0x0008003b},
19727 + {0x00004044, 0x00000000},
19728 +};
19729 +
19730 +/*
19731 + * PCIE-PHY programming array, to be used when not in
19732 + * full sleep (holding RTC in reset)
19733 + */
19734 +static const u32 ar9300PciePhy_clkreq_enable_L1_2p0[][2] = {
19735 + {0x00004040, 0x08253e5e},
19736 + {0x00004040, 0x0008003b},
19737 + {0x00004044, 0x00000000},
19738 +};
19739 +
19740 +/*
19741 + * PCIE-PHY programming array, to be used prior to entering
19742 + * full sleep (holding RTC in reset)
19743 + */
19744 +static const u32 ar9300PciePhy_clkreq_disable_L1_2p0[][2] = {
19745 + {0x00004040, 0x08213e5e},
19746 + {0x00004040, 0x0008003b},
19747 + {0x00004044, 0x00000000},
19748 +};
19749 +
19750 +#endif /* INITVALS_9003_H */
19751 diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
19752 new file mode 100644
19753 index 0000000..098fbad
19754 --- /dev/null
19755 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
19756 @@ -0,0 +1,618 @@
19757 +/*
19758 + * Copyright (c) 2010 Atheros Communications Inc.
19759 + *
19760 + * Permission to use, copy, modify, and/or distribute this software for any
19761 + * purpose with or without fee is hereby granted, provided that the above
19762 + * copyright notice and this permission notice appear in all copies.
19763 + *
19764 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
19765 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
19766 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
19767 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
19768 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19769 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19770 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19771 + */
19772 +#include "hw.h"
19773 +
19774 +static void ar9003_hw_rx_enable(struct ath_hw *hw)
19775 +{
19776 + REG_WRITE(hw, AR_CR, 0);
19777 +}
19778 +
19779 +static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
19780 +{
19781 + int checksum;
19782 +
19783 + checksum = ads->info + ads->link
19784 + + ads->data0 + ads->ctl3
19785 + + ads->data1 + ads->ctl5
19786 + + ads->data2 + ads->ctl7
19787 + + ads->data3 + ads->ctl9;
19788 +
19789 + return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
19790 +}
19791 +
19792 +static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
19793 +{
19794 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
19795 +
19796 + ads->link = ds_link;
19797 + ads->ctl10 &= ~AR_TxPtrChkSum;
19798 + ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
19799 +}
19800 +
19801 +static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
19802 +{
19803 + *ds_link = &((struct ar9003_txc *) ds)->link;
19804 +}
19805 +
19806 +static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
19807 +{
19808 + u32 isr = 0;
19809 + u32 mask2 = 0;
19810 + struct ath9k_hw_capabilities *pCap = &ah->caps;
19811 + u32 sync_cause = 0;
19812 + struct ath_common *common = ath9k_hw_common(ah);
19813 +
19814 + if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
19815 + if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
19816 + == AR_RTC_STATUS_ON)
19817 + isr = REG_READ(ah, AR_ISR);
19818 + }
19819 +
19820 + sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
19821 +
19822 + *masked = 0;
19823 +
19824 + if (!isr && !sync_cause)
19825 + return false;
19826 +
19827 + if (isr) {
19828 + if (isr & AR_ISR_BCNMISC) {
19829 + u32 isr2;
19830 + isr2 = REG_READ(ah, AR_ISR_S2);
19831 +
19832 + mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
19833 + MAP_ISR_S2_TIM);
19834 + mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
19835 + MAP_ISR_S2_DTIM);
19836 + mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
19837 + MAP_ISR_S2_DTIMSYNC);
19838 + mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
19839 + MAP_ISR_S2_CABEND);
19840 + mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
19841 + MAP_ISR_S2_GTT);
19842 + mask2 |= ((isr2 & AR_ISR_S2_CST) <<
19843 + MAP_ISR_S2_CST);
19844 + mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
19845 + MAP_ISR_S2_TSFOOR);
19846 +
19847 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
19848 + REG_WRITE(ah, AR_ISR_S2, isr2);
19849 + isr &= ~AR_ISR_BCNMISC;
19850 + }
19851 + }
19852 +
19853 + if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
19854 + isr = REG_READ(ah, AR_ISR_RAC);
19855 +
19856 + if (isr == 0xffffffff) {
19857 + *masked = 0;
19858 + return false;
19859 + }
19860 +
19861 + *masked = isr & ATH9K_INT_COMMON;
19862 +
19863 + if (ah->config.rx_intr_mitigation)
19864 + if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
19865 + *masked |= ATH9K_INT_RXLP;
19866 +
19867 + if (ah->config.tx_intr_mitigation)
19868 + if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
19869 + *masked |= ATH9K_INT_TX;
19870 +
19871 + if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
19872 + *masked |= ATH9K_INT_RXLP;
19873 +
19874 + if (isr & AR_ISR_HP_RXOK)
19875 + *masked |= ATH9K_INT_RXHP;
19876 +
19877 + if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
19878 + *masked |= ATH9K_INT_TX;
19879 +
19880 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
19881 + u32 s0, s1;
19882 + s0 = REG_READ(ah, AR_ISR_S0);
19883 + REG_WRITE(ah, AR_ISR_S0, s0);
19884 + s1 = REG_READ(ah, AR_ISR_S1);
19885 + REG_WRITE(ah, AR_ISR_S1, s1);
19886 +
19887 + isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
19888 + AR_ISR_TXEOL);
19889 + }
19890 + }
19891 +
19892 + if (isr & AR_ISR_GENTMR) {
19893 + u32 s5;
19894 +
19895 + if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
19896 + s5 = REG_READ(ah, AR_ISR_S5_S);
19897 + else
19898 + s5 = REG_READ(ah, AR_ISR_S5);
19899 +
19900 + ah->intr_gen_timer_trigger =
19901 + MS(s5, AR_ISR_S5_GENTIMER_TRIG);
19902 +
19903 + ah->intr_gen_timer_thresh =
19904 + MS(s5, AR_ISR_S5_GENTIMER_THRESH);
19905 +
19906 + if (ah->intr_gen_timer_trigger)
19907 + *masked |= ATH9K_INT_GENTIMER;
19908 +
19909 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
19910 + REG_WRITE(ah, AR_ISR_S5, s5);
19911 + isr &= ~AR_ISR_GENTMR;
19912 + }
19913 +
19914 + }
19915 +
19916 + *masked |= mask2;
19917 +
19918 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
19919 + REG_WRITE(ah, AR_ISR, isr);
19920 +
19921 + (void) REG_READ(ah, AR_ISR);
19922 + }
19923 + }
19924 +
19925 + if (sync_cause) {
19926 + if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
19927 + REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
19928 + REG_WRITE(ah, AR_RC, 0);
19929 + *masked |= ATH9K_INT_FATAL;
19930 + }
19931 +
19932 + if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
19933 + ath_print(common, ATH_DBG_INTERRUPT,
19934 + "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
19935 +
19936 + REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
19937 + (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
19938 +
19939 + }
19940 + return true;
19941 +}
19942 +
19943 +static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
19944 + bool is_firstseg, bool is_lastseg,
19945 + const void *ds0, dma_addr_t buf_addr,
19946 + unsigned int qcu)
19947 +{
19948 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
19949 + unsigned int descid = 0;
19950 +
19951 + ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) |
19952 + (1 << AR_TxRxDesc_S) |
19953 + (1 << AR_CtrlStat_S) |
19954 + (qcu << AR_TxQcuNum_S) | 0x17;
19955 +
19956 + ads->data0 = buf_addr;
19957 + ads->data1 = 0;
19958 + ads->data2 = 0;
19959 + ads->data3 = 0;
19960 +
19961 + ads->ctl3 = (seglen << AR_BufLen_S);
19962 + ads->ctl3 &= AR_BufLen;
19963 +
19964 + /* Fill in pointer checksum and descriptor id */
19965 + ads->ctl10 = ar9003_calc_ptr_chksum(ads);
19966 + ads->ctl10 |= (descid << AR_TxDescId_S);
19967 +
19968 + if (is_firstseg) {
19969 + ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore);
19970 + } else if (is_lastseg) {
19971 + ads->ctl11 = 0;
19972 + ads->ctl12 = 0;
19973 + ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13;
19974 + ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14;
19975 + } else {
19976 + /* XXX Intermediate descriptor in a multi-descriptor frame.*/
19977 + ads->ctl11 = 0;
19978 + ads->ctl12 = AR_TxMore;
19979 + ads->ctl13 = 0;
19980 + ads->ctl14 = 0;
19981 + }
19982 +}
19983 +
19984 +static void ar9003_hw_clear_txdesc(struct ath_hw *ah, void *ds)
19985 +{
19986 + struct ar9003_txs *ads = (struct ar9003_txs *) ds;
19987 + ads->status1 = ads->status2 = 0;
19988 + ads->status3 = ads->status4 = 0;
19989 + ads->status5 = ads->status6 = 0;
19990 + ads->status7 = ads->status8 = 0;
19991 +}
19992 +
19993 +static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
19994 + struct ath_tx_status *ts)
19995 +{
19996 + struct ar9003_txs *ads;
19997 +
19998 + ads = &ah->ts_ring[ah->ts_tail];
19999 +
20000 + if ((ads->status8 & AR_TxDone) == 0)
20001 + return -EINPROGRESS;
20002 +
20003 + ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
20004 +
20005 + if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
20006 + (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
20007 + ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
20008 + "Tx Descriptor error %x\n", ads->ds_info);
20009 + memset(ads, 0, sizeof(*ads));
20010 + return -EIO;
20011 + }
20012 +
20013 + ts->qid = MS(ads->ds_info, AR_TxQcuNum);
20014 + ts->desc_id = MS(ads->status1, AR_TxDescId);
20015 + ts->ts_seqnum = MS(ads->status8, AR_SeqNum);
20016 + ts->ts_tstamp = ads->status4;
20017 + ts->ts_status = 0;
20018 + ts->ts_flags = 0;
20019 +
20020 + if (ads->status3 & AR_ExcessiveRetries)
20021 + ts->ts_status |= ATH9K_TXERR_XRETRY;
20022 + if (ads->status3 & AR_Filtered)
20023 + ts->ts_status |= ATH9K_TXERR_FILT;
20024 + if (ads->status3 & AR_FIFOUnderrun) {
20025 + ts->ts_status |= ATH9K_TXERR_FIFO;
20026 + ath9k_hw_updatetxtriglevel(ah, true);
20027 + }
20028 + if (ads->status8 & AR_TxOpExceeded)
20029 + ts->ts_status |= ATH9K_TXERR_XTXOP;
20030 + if (ads->status3 & AR_TxTimerExpired)
20031 + ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
20032 +
20033 + if (ads->status3 & AR_DescCfgErr)
20034 + ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
20035 + if (ads->status3 & AR_TxDataUnderrun) {
20036 + ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
20037 + ath9k_hw_updatetxtriglevel(ah, true);
20038 + }
20039 + if (ads->status3 & AR_TxDelimUnderrun) {
20040 + ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
20041 + ath9k_hw_updatetxtriglevel(ah, true);
20042 + }
20043 + if (ads->status2 & AR_TxBaStatus) {
20044 + ts->ts_flags |= ATH9K_TX_BA;
20045 + ts->ba_low = ads->status5;
20046 + ts->ba_high = ads->status6;
20047 + }
20048 +
20049 + ts->ts_rateindex = MS(ads->status8, AR_FinalTxIdx);
20050 +
20051 + ts->ts_rssi = MS(ads->status7, AR_TxRSSICombined);
20052 + ts->ts_rssi_ctl0 = MS(ads->status2, AR_TxRSSIAnt00);
20053 + ts->ts_rssi_ctl1 = MS(ads->status2, AR_TxRSSIAnt01);
20054 + ts->ts_rssi_ctl2 = MS(ads->status2, AR_TxRSSIAnt02);
20055 + ts->ts_rssi_ext0 = MS(ads->status7, AR_TxRSSIAnt10);
20056 + ts->ts_rssi_ext1 = MS(ads->status7, AR_TxRSSIAnt11);
20057 + ts->ts_rssi_ext2 = MS(ads->status7, AR_TxRSSIAnt12);
20058 + ts->ts_shortretry = MS(ads->status3, AR_RTSFailCnt);
20059 + ts->ts_longretry = MS(ads->status3, AR_DataFailCnt);
20060 + ts->ts_virtcol = MS(ads->status3, AR_VirtRetryCnt);
20061 + ts->ts_antenna = 0;
20062 +
20063 + ts->tid = MS(ads->status8, AR_TxTid);
20064 +
20065 + memset(ads, 0, sizeof(*ads));
20066 +
20067 + return 0;
20068 +}
20069 +
20070 +static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
20071 + u32 pktlen, enum ath9k_pkt_type type, u32 txpower,
20072 + u32 keyIx, enum ath9k_key_type keyType, u32 flags)
20073 +{
20074 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20075 +
20076 + txpower += ah->txpower_indexoffset;
20077 + if (txpower > 63)
20078 + txpower = 63;
20079 +
20080 + ads->ctl11 = (pktlen & AR_FrameLen)
20081 + | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
20082 + | SM(txpower, AR_XmitPower)
20083 + | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
20084 + | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
20085 + | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
20086 + | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
20087 +
20088 + ads->ctl12 =
20089 + (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
20090 + | SM(type, AR_FrameType)
20091 + | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
20092 + | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
20093 + | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
20094 +
20095 + ads->ctl17 = SM(keyType, AR_EncrType) |
20096 + (flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
20097 + ads->ctl18 = 0;
20098 + ads->ctl19 = AR_Not_Sounding;
20099 +
20100 + ads->ctl20 = 0;
20101 + ads->ctl21 = 0;
20102 + ads->ctl22 = 0;
20103 +}
20104 +
20105 +static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
20106 + void *lastds,
20107 + u32 durUpdateEn, u32 rtsctsRate,
20108 + u32 rtsctsDuration,
20109 + struct ath9k_11n_rate_series series[],
20110 + u32 nseries, u32 flags)
20111 +{
20112 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20113 + struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds;
20114 + u_int32_t ctl11;
20115 +
20116 + if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
20117 + ctl11 = ads->ctl11;
20118 +
20119 + if (flags & ATH9K_TXDESC_RTSENA) {
20120 + ctl11 &= ~AR_CTSEnable;
20121 + ctl11 |= AR_RTSEnable;
20122 + } else {
20123 + ctl11 &= ~AR_RTSEnable;
20124 + ctl11 |= AR_CTSEnable;
20125 + }
20126 +
20127 + ads->ctl11 = ctl11;
20128 + } else {
20129 + ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable));
20130 + }
20131 +
20132 + ads->ctl13 = set11nTries(series, 0)
20133 + | set11nTries(series, 1)
20134 + | set11nTries(series, 2)
20135 + | set11nTries(series, 3)
20136 + | (durUpdateEn ? AR_DurUpdateEna : 0)
20137 + | SM(0, AR_BurstDur);
20138 +
20139 + ads->ctl14 = set11nRate(series, 0)
20140 + | set11nRate(series, 1)
20141 + | set11nRate(series, 2)
20142 + | set11nRate(series, 3);
20143 +
20144 + ads->ctl15 = set11nPktDurRTSCTS(series, 0)
20145 + | set11nPktDurRTSCTS(series, 1);
20146 +
20147 + ads->ctl16 = set11nPktDurRTSCTS(series, 2)
20148 + | set11nPktDurRTSCTS(series, 3);
20149 +
20150 + ads->ctl18 = set11nRateFlags(series, 0)
20151 + | set11nRateFlags(series, 1)
20152 + | set11nRateFlags(series, 2)
20153 + | set11nRateFlags(series, 3)
20154 + | SM(rtsctsRate, AR_RTSCTSRate);
20155 + ads->ctl19 = AR_Not_Sounding;
20156 +
20157 + last_ads->ctl13 = ads->ctl13;
20158 + last_ads->ctl14 = ads->ctl14;
20159 +}
20160 +
20161 +static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
20162 + u32 aggrLen)
20163 +{
20164 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20165 +
20166 + ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
20167 +
20168 + ads->ctl17 &= ~AR_AggrLen;
20169 + ads->ctl17 |= SM(aggrLen, AR_AggrLen);
20170 +}
20171 +
20172 +static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
20173 + u32 numDelims)
20174 +{
20175 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20176 + unsigned int ctl17;
20177 +
20178 + ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
20179 +
20180 + /*
20181 + * We use a stack variable to manipulate ctl6 to reduce uncached
20182 + * read modify, modfiy, write.
20183 + */
20184 + ctl17 = ads->ctl17;
20185 + ctl17 &= ~AR_PadDelim;
20186 + ctl17 |= SM(numDelims, AR_PadDelim);
20187 + ads->ctl17 = ctl17;
20188 +}
20189 +
20190 +static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
20191 +{
20192 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20193 +
20194 + ads->ctl12 |= AR_IsAggr;
20195 + ads->ctl12 &= ~AR_MoreAggr;
20196 + ads->ctl17 &= ~AR_PadDelim;
20197 +}
20198 +
20199 +static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
20200 +{
20201 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20202 +
20203 + ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
20204 +}
20205 +
20206 +static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
20207 + u32 burstDuration)
20208 +{
20209 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20210 +
20211 + ads->ctl13 &= ~AR_BurstDur;
20212 + ads->ctl13 |= SM(burstDuration, AR_BurstDur);
20213 +
20214 +}
20215 +
20216 +static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
20217 + u32 vmf)
20218 +{
20219 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20220 +
20221 + if (vmf)
20222 + ads->ctl11 |= AR_VirtMoreFrag;
20223 + else
20224 + ads->ctl11 &= ~AR_VirtMoreFrag;
20225 +}
20226 +
20227 +void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
20228 +{
20229 + struct ath_hw_ops *ops = ath9k_hw_ops(hw);
20230 +
20231 + ops->rx_enable = ar9003_hw_rx_enable;
20232 + ops->set_desc_link = ar9003_hw_set_desc_link;
20233 + ops->get_desc_link = ar9003_hw_get_desc_link;
20234 + ops->get_isr = ar9003_hw_get_isr;
20235 + ops->fill_txdesc = ar9003_hw_fill_txdesc;
20236 + ops->clear_txdesc = ar9003_hw_clear_txdesc;
20237 + ops->proc_txdesc = ar9003_hw_proc_txdesc;
20238 + ops->set11n_txdesc = ar9003_hw_set11n_txdesc;
20239 + ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario;
20240 + ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first;
20241 + ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
20242 + ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
20243 + ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
20244 + ops->set11n_burstduration = ar9003_hw_set11n_burstduration;
20245 + ops->set11n_virtualmorefrag = ar9003_hw_set11n_virtualmorefrag;
20246 +}
20247 +
20248 +void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
20249 +{
20250 + REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
20251 +}
20252 +EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize);
20253 +
20254 +void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
20255 + enum ath9k_rx_qtype qtype)
20256 +{
20257 + if (qtype == ATH9K_RX_QUEUE_HP)
20258 + REG_WRITE(ah, AR_HP_RXDP, rxdp);
20259 + else
20260 + REG_WRITE(ah, AR_LP_RXDP, rxdp);
20261 +}
20262 +EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma);
20263 +
20264 +int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
20265 + void *buf_addr)
20266 +{
20267 + struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
20268 + unsigned int phyerr;
20269 +
20270 + /* TODO: byte swap on big endian for ar9300_10 */
20271 +
20272 + if ((rxsp->status11 & AR_RxDone) == 0)
20273 + return -EINPROGRESS;
20274 +
20275 + if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
20276 + return -EINVAL;
20277 +
20278 + if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
20279 + return -EINPROGRESS;
20280 +
20281 + if (!rxs)
20282 + return 0;
20283 +
20284 + rxs->rs_status = 0;
20285 + rxs->rs_flags = 0;
20286 +
20287 + rxs->rs_datalen = rxsp->status2 & AR_DataLen;
20288 + rxs->rs_tstamp = rxsp->status3;
20289 +
20290 + /* XXX: Keycache */
20291 + rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
20292 + rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
20293 + rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
20294 + rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
20295 + rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
20296 + rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
20297 + rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
20298 +
20299 + if (rxsp->status11 & AR_RxKeyIdxValid)
20300 + rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
20301 + else
20302 + rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
20303 +
20304 + rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
20305 + rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
20306 +
20307 + rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
20308 + rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
20309 + rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
20310 + rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
20311 + rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
20312 +
20313 + rxs->evm0 = rxsp->status6;
20314 + rxs->evm1 = rxsp->status7;
20315 + rxs->evm2 = rxsp->status8;
20316 + rxs->evm3 = rxsp->status9;
20317 + rxs->evm4 = (rxsp->status10 & 0xffff);
20318 +
20319 + if (rxsp->status11 & AR_PreDelimCRCErr)
20320 + rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
20321 +
20322 + if (rxsp->status11 & AR_PostDelimCRCErr)
20323 + rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
20324 +
20325 + if (rxsp->status11 & AR_DecryptBusyErr)
20326 + rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
20327 +
20328 + if ((rxsp->status11 & AR_RxFrameOK) == 0) {
20329 + if (rxsp->status11 & AR_CRCErr) {
20330 + rxs->rs_status |= ATH9K_RXERR_CRC;
20331 + } else if (rxsp->status11 & AR_PHYErr) {
20332 + rxs->rs_status |= ATH9K_RXERR_PHY;
20333 + phyerr = MS(rxsp->status11, AR_PHYErrCode);
20334 + rxs->rs_phyerr = phyerr;
20335 + } else if (rxsp->status11 & AR_DecryptCRCErr) {
20336 + rxs->rs_status |= ATH9K_RXERR_DECRYPT;
20337 + } else if (rxsp->status11 & AR_MichaelErr) {
20338 + rxs->rs_status |= ATH9K_RXERR_MIC;
20339 + }
20340 + }
20341 +
20342 + return 0;
20343 +}
20344 +EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);
20345 +
20346 +void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
20347 +{
20348 + ah->ts_tail = 0;
20349 +
20350 + memset((void *) ah->ts_ring, 0,
20351 + ah->ts_size * sizeof(struct ar9003_txs));
20352 +
20353 + ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
20354 + "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
20355 + ah->ts_paddr_start, ah->ts_paddr_end,
20356 + ah->ts_ring, ah->ts_size);
20357 +
20358 + REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
20359 + REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
20360 +}
20361 +
20362 +void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
20363 + u32 ts_paddr_start,
20364 + u8 size)
20365 +{
20366 +
20367 + ah->ts_paddr_start = ts_paddr_start;
20368 + ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
20369 + ah->ts_size = size;
20370 + ah->ts_ring = (struct ar9003_txs *) ts_start;
20371 +
20372 + ath9k_hw_reset_txstatus_ring(ah);
20373 +}
20374 +EXPORT_SYMBOL(ath9k_hw_setup_statusring);
20375 diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.h b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
20376 new file mode 100644
20377 index 0000000..87fb6e1
20378 --- /dev/null
20379 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
20380 @@ -0,0 +1,124 @@
20381 +/*
20382 + * Copyright (c) 2010 Atheros Communications Inc.
20383 + *
20384 + * Permission to use, copy, modify, and/or distribute this software for any
20385 + * purpose with or without fee is hereby granted, provided that the above
20386 + * copyright notice and this permission notice appear in all copies.
20387 + *
20388 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
20389 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
20390 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
20391 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
20392 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
20393 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20394 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20395 + */
20396 +
20397 +#ifndef ar9003_MAC_H
20398 +#define ar9003_MAC_H
20399 +
20400 +#define AR_DescId 0xffff0000
20401 +#define AR_DescId_S 16
20402 +#define AR_CtrlStat 0x00004000
20403 +#define AR_CtrlStat_S 14
20404 +#define AR_TxRxDesc 0x00008000
20405 +#define AR_TxRxDesc_S 15
20406 +#define AR_TxQcuNum 0x00000f00
20407 +#define AR_TxQcuNum_S 8
20408 +#define AR_BufLen_S 16
20409 +
20410 +#define AR_TxDescId 0xffff0000
20411 +#define AR_TxDescId_S 16
20412 +#define AR_TxPtrChkSum 0x0000ffff
20413 +
20414 +#define AR_TxTid 0xf0000000
20415 +#define AR_TxTid_S 28
20416 +
20417 +#define AR_LowRxChain 0x00004000
20418 +
20419 +#define AR_Not_Sounding 0x20000000
20420 +
20421 +#define MAP_ISR_S2_CST 6
20422 +#define MAP_ISR_S2_GTT 6
20423 +#define MAP_ISR_S2_TIM 3
20424 +#define MAP_ISR_S2_CABEND 0
20425 +#define MAP_ISR_S2_DTIMSYNC 7
20426 +#define MAP_ISR_S2_DTIM 7
20427 +#define MAP_ISR_S2_TSFOOR 4
20428 +
20429 +#define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds)
20430 +
20431 +enum ath9k_rx_qtype {
20432 + ATH9K_RX_QUEUE_HP,
20433 + ATH9K_RX_QUEUE_LP,
20434 + ATH9K_RX_QUEUE_MAX,
20435 +};
20436 +
20437 +struct ar9003_rxs {
20438 + u32 ds_info;
20439 + u32 status1;
20440 + u32 status2;
20441 + u32 status3;
20442 + u32 status4;
20443 + u32 status5;
20444 + u32 status6;
20445 + u32 status7;
20446 + u32 status8;
20447 + u32 status9;
20448 + u32 status10;
20449 + u32 status11;
20450 +} __packed;
20451 +
20452 +/* Transmit Control Descriptor */
20453 +struct ar9003_txc {
20454 + u32 info; /* descriptor information */
20455 + u32 link; /* link pointer */
20456 + u32 data0; /* data pointer to 1st buffer */
20457 + u32 ctl3; /* DMA control 3 */
20458 + u32 data1; /* data pointer to 2nd buffer */
20459 + u32 ctl5; /* DMA control 5 */
20460 + u32 data2; /* data pointer to 3rd buffer */
20461 + u32 ctl7; /* DMA control 7 */
20462 + u32 data3; /* data pointer to 4th buffer */
20463 + u32 ctl9; /* DMA control 9 */
20464 + u32 ctl10; /* DMA control 10 */
20465 + u32 ctl11; /* DMA control 11 */
20466 + u32 ctl12; /* DMA control 12 */
20467 + u32 ctl13; /* DMA control 13 */
20468 + u32 ctl14; /* DMA control 14 */
20469 + u32 ctl15; /* DMA control 15 */
20470 + u32 ctl16; /* DMA control 16 */
20471 + u32 ctl17; /* DMA control 17 */
20472 + u32 ctl18; /* DMA control 18 */
20473 + u32 ctl19; /* DMA control 19 */
20474 + u32 ctl20; /* DMA control 20 */
20475 + u32 ctl21; /* DMA control 21 */
20476 + u32 ctl22; /* DMA control 22 */
20477 + u32 pad[9]; /* pad to cache line (128 bytes/32 dwords) */
20478 +} __packed;
20479 +
20480 +struct ar9003_txs {
20481 + u32 ds_info;
20482 + u32 status1;
20483 + u32 status2;
20484 + u32 status3;
20485 + u32 status4;
20486 + u32 status5;
20487 + u32 status6;
20488 + u32 status7;
20489 + u32 status8;
20490 +} __packed;
20491 +
20492 +void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
20493 +void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
20494 +void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
20495 + enum ath9k_rx_qtype qtype);
20496 +
20497 +int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah,
20498 + struct ath_rx_status *rxs,
20499 + void *buf_addr);
20500 +void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah);
20501 +void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
20502 + u32 ts_paddr_start,
20503 + u8 size);
20504 +#endif
20505 diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
20506 new file mode 100644
20507 index 0000000..e9b8474
20508 --- /dev/null
20509 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
20510 @@ -0,0 +1,1145 @@
20511 +/*
20512 + * Copyright (c) 2010 Atheros Communications Inc.
20513 + *
20514 + * Permission to use, copy, modify, and/or distribute this software for any
20515 + * purpose with or without fee is hereby granted, provided that the above
20516 + * copyright notice and this permission notice appear in all copies.
20517 + *
20518 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
20519 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
20520 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
20521 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
20522 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
20523 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20524 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20525 + */
20526 +
20527 +#include "hw.h"
20528 +#include "ar9003_phy.h"
20529 +
20530 +/**
20531 + * ar9003_hw_set_channel - set channel on single-chip device
20532 + * @ah: atheros hardware structure
20533 + * @chan:
20534 + *
20535 + * This is the function to change channel on single-chip devices, that is
20536 + * all devices after ar9280.
20537 + *
20538 + * This function takes the channel value in MHz and sets
20539 + * hardware channel value. Assumes writes have been enabled to analog bus.
20540 + *
20541 + * Actual Expression,
20542 + *
20543 + * For 2GHz channel,
20544 + * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
20545 + * (freq_ref = 40MHz)
20546 + *
20547 + * For 5GHz channel,
20548 + * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
20549 + * (freq_ref = 40MHz/(24>>amodeRefSel))
20550 + *
20551 + * For 5GHz channels which are 5MHz spaced,
20552 + * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
20553 + * (freq_ref = 40MHz)
20554 + */
20555 +static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
20556 +{
20557 + u16 bMode, fracMode = 0, aModeRefSel = 0;
20558 + u32 freq, channelSel = 0, reg32 = 0;
20559 + struct chan_centers centers;
20560 + int loadSynthChannel;
20561 +
20562 + ath9k_hw_get_channel_centers(ah, chan, &centers);
20563 + freq = centers.synth_center;
20564 +
20565 + if (freq < 4800) { /* 2 GHz, fractional mode */
20566 + channelSel = CHANSEL_2G(freq);
20567 + /* Set to 2G mode */
20568 + bMode = 1;
20569 + } else {
20570 + channelSel = CHANSEL_5G(freq);
20571 + /* Doubler is ON, so, divide channelSel by 2. */
20572 + channelSel >>= 1;
20573 + /* Set to 5G mode */
20574 + bMode = 0;
20575 + }
20576 +
20577 + /* Enable fractional mode for all channels */
20578 + fracMode = 1;
20579 + aModeRefSel = 0;
20580 + loadSynthChannel = 0;
20581 +
20582 + reg32 = (bMode << 29);
20583 + REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
20584 +
20585 + /* Enable Long shift Select for Synthesizer */
20586 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
20587 + AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
20588 +
20589 + /* Program Synth. setting */
20590 + reg32 = (channelSel << 2 ) | (fracMode << 30) |
20591 + (aModeRefSel << 28) | (loadSynthChannel << 31);
20592 + REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
20593 +
20594 + /* Toggle Load Synth channel bit */
20595 + loadSynthChannel = 1;
20596 + reg32 = (channelSel << 2 ) | (fracMode << 30) |
20597 + (aModeRefSel << 28) | (loadSynthChannel << 31);
20598 + REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
20599 +
20600 + ah->curchan = chan;
20601 + ah->curchan_rad_index = -1;
20602 +
20603 + return 0;
20604 +}
20605 +
20606 +/**
20607 + * ar9003_hw_spur_mitigate - convert baseband spur frequency
20608 + * @ah: atheros hardware structure
20609 + * @chan:
20610 + *
20611 + * For single-chip solutions. Converts to baseband spur frequency given the
20612 + * input channel frequency and compute register settings below.
20613 + *
20614 + * Spur mitigation for MRC CCK
20615 + */
20616 +static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
20617 + struct ath9k_channel *chan)
20618 +{
20619 + u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
20620 + int cur_bb_spur, negative = 0, cck_spur_freq;
20621 + int i;
20622 +
20623 + /*
20624 + * Need to verify range +/- 10 MHz in control channel, otherwise spur
20625 + * is out-of-band and can be ignored.
20626 + */
20627 +
20628 + for (i = 0; i < 4; i++) {
20629 + negative = 0;
20630 + cur_bb_spur = spur_freq[i] - chan->channel;
20631 +
20632 + if(cur_bb_spur < 0) {
20633 + negative = 1;
20634 + cur_bb_spur = -cur_bb_spur;
20635 + }
20636 + if (cur_bb_spur < 10) {
20637 + cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
20638 +
20639 + if (negative == 1)
20640 + cck_spur_freq = -cck_spur_freq;
20641 +
20642 + cck_spur_freq = cck_spur_freq & 0xfffff;
20643 +
20644 + REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
20645 + AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
20646 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
20647 + AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
20648 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
20649 + AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 0x2);
20650 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
20651 + AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x1);
20652 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
20653 + AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, cck_spur_freq);
20654 +
20655 + return;
20656 + }
20657 + }
20658 +
20659 + REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
20660 + AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
20661 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
20662 + AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
20663 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
20664 + AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
20665 +}
20666 +
20667 +/* Clean all spur register fields */
20668 +static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
20669 +{
20670 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20671 + AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
20672 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20673 + AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
20674 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20675 + AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
20676 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
20677 + AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
20678 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20679 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
20680 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20681 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
20682 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20683 + AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
20684 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20685 + AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
20686 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20687 + AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
20688 +
20689 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20690 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
20691 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20692 + AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
20693 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20694 + AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
20695 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
20696 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
20697 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
20698 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
20699 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
20700 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
20701 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
20702 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
20703 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
20704 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
20705 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
20706 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
20707 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20708 + AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
20709 +}
20710 +
20711 +static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
20712 + int freq_offset,
20713 + int spur_freq_sd,
20714 + int spur_delta_phase,
20715 + int spur_subchannel_sd)
20716 +{
20717 + int mask_index = 0;
20718 +
20719 + /* OFDM Spur mitigation */
20720 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20721 + AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
20722 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20723 + AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
20724 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20725 + AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
20726 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
20727 + AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
20728 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20729 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
20730 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20731 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
20732 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20733 + AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
20734 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20735 + AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
20736 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20737 + AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
20738 +
20739 + if (REG_READ_FIELD(ah, AR_PHY_MODE,
20740 + AR_PHY_MODE_DYNAMIC) == 0x1)
20741 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20742 + AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
20743 +
20744 + mask_index = (freq_offset << 4) / 5;
20745 + if (mask_index < 0)
20746 + mask_index = mask_index - 1;
20747 +
20748 + mask_index = mask_index & 0x7f;
20749 +
20750 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20751 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
20752 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20753 + AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
20754 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20755 + AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
20756 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
20757 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
20758 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
20759 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
20760 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
20761 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
20762 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
20763 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
20764 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
20765 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
20766 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
20767 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
20768 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20769 + AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
20770 +}
20771 +
20772 +static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
20773 + struct ath9k_channel *chan,
20774 + int freq_offset)
20775 +{
20776 + int spur_freq_sd = 0;
20777 + int spur_subchannel_sd = 0;
20778 + int spur_delta_phase = 0;
20779 +
20780 + if (IS_CHAN_HT40(chan)) {
20781 + if (freq_offset < 0) {
20782 + if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
20783 + AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
20784 + spur_subchannel_sd = 1;
20785 + else
20786 + spur_subchannel_sd = 0;
20787 +
20788 + spur_freq_sd = ((freq_offset + 10) << 9) / 11;
20789 +
20790 + } else {
20791 + if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
20792 + AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
20793 + spur_subchannel_sd = 0;
20794 + else
20795 + spur_subchannel_sd = 1;
20796 +
20797 + spur_freq_sd = ((freq_offset - 10) << 9) / 11;
20798 +
20799 + }
20800 +
20801 + spur_delta_phase = (freq_offset << 17) / 5;
20802 +
20803 + } else {
20804 + spur_subchannel_sd = 0;
20805 + spur_freq_sd = (freq_offset << 9) /11;
20806 + spur_delta_phase = (freq_offset << 18) / 5;
20807 + }
20808 +
20809 + spur_freq_sd = spur_freq_sd & 0x3ff;
20810 + spur_delta_phase = spur_delta_phase & 0xfffff;
20811 +
20812 + ar9003_hw_spur_ofdm(ah,
20813 + freq_offset,
20814 + spur_freq_sd,
20815 + spur_delta_phase,
20816 + spur_subchannel_sd);
20817 +}
20818 +
20819 +/* Spur mitigation for OFDM */
20820 +static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
20821 + struct ath9k_channel *chan)
20822 +{
20823 + int synth_freq;
20824 + int range = 10;
20825 + int freq_offset = 0;
20826 + int mode;
20827 + u8* spurChansPtr;
20828 + unsigned int i;
20829 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
20830 +
20831 + if (IS_CHAN_5GHZ(chan)) {
20832 + spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
20833 + mode = 0;
20834 + }
20835 + else {
20836 + spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
20837 + mode = 1;
20838 + }
20839 +
20840 + if (spurChansPtr[0] == 0)
20841 + return; /* No spur in the mode */
20842 +
20843 + if (IS_CHAN_HT40(chan)) {
20844 + range = 19;
20845 + if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
20846 + AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
20847 + synth_freq = chan->channel - 10;
20848 + else
20849 + synth_freq = chan->channel + 10;
20850 + } else {
20851 + range = 10;
20852 + synth_freq = chan->channel;
20853 + }
20854 +
20855 + ar9003_hw_spur_ofdm_clear(ah);
20856 +
20857 + for (i = 0; spurChansPtr[i] && i < 5; i++) {
20858 + freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
20859 + if (abs(freq_offset) < range) {
20860 + ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
20861 + break;
20862 + }
20863 + }
20864 +}
20865 +
20866 +static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
20867 + struct ath9k_channel *chan)
20868 +{
20869 + ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
20870 + ar9003_hw_spur_mitigate_ofdm(ah, chan);
20871 +}
20872 +
20873 +static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
20874 + struct ath9k_channel *chan)
20875 +{
20876 + u32 pll;
20877 +
20878 + pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
20879 +
20880 + if (chan && IS_CHAN_HALF_RATE(chan))
20881 + pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
20882 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
20883 + pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
20884 +
20885 + if (chan && IS_CHAN_5GHZ(chan)) {
20886 + pll |= SM(0x28, AR_RTC_9300_PLL_DIV);
20887 +
20888 + /*
20889 + * When doing fast clock, set PLL to 0x142c
20890 + */
20891 + if (IS_CHAN_A_5MHZ_SPACED(chan))
20892 + pll = 0x142c;
20893 + } else
20894 + pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
20895 +
20896 + return pll;
20897 +}
20898 +
20899 +static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
20900 + struct ath9k_channel *chan)
20901 +{
20902 + u32 phymode;
20903 + u32 enableDacFifo = 0;
20904 +
20905 + enableDacFifo =
20906 + (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
20907 +
20908 + /* Enable 11n HT, 20 MHz */
20909 + phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
20910 + AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
20911 +
20912 + /* Configure baseband for dynamic 20/40 operation */
20913 + if (IS_CHAN_HT40(chan)) {
20914 + phymode |= AR_PHY_GC_DYN2040_EN;
20915 + /* Configure control (primary) channel at +-10MHz */
20916 + if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
20917 + (chan->chanmode == CHANNEL_G_HT40PLUS))
20918 + phymode |= AR_PHY_GC_DYN2040_PRI_CH;
20919 +
20920 + }
20921 +
20922 + /* make sure we preserve INI settings */
20923 + phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
20924 + /* turn off Green Field detection for STA for now */
20925 + phymode &= ~AR_PHY_GC_GF_DETECT_EN;
20926 +
20927 + REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
20928 +
20929 + /* Configure MAC for 20/40 operation */
20930 + ath9k_hw_set11nmac2040(ah);
20931 +
20932 + /* global transmit timeout (25 TUs default)*/
20933 + REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
20934 + /* carrier sense timeout */
20935 + REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
20936 +}
20937 +
20938 +static void ar9003_hw_init_bb(struct ath_hw *ah,
20939 + struct ath9k_channel *chan)
20940 +{
20941 + u32 synthDelay;
20942 +
20943 + /*
20944 + * Wait for the frequency synth to settle (synth goes on
20945 + * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
20946 + * Value is in 100ns increments.
20947 + */
20948 + synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
20949 + if (IS_CHAN_B(chan))
20950 + synthDelay = (4 * synthDelay) / 22;
20951 + else
20952 + synthDelay /= 10;
20953 +
20954 + /* Activate the PHY (includes baseband activate + synthesizer on) */
20955 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
20956 +
20957 + /*
20958 + * There is an issue if the AP starts the calibration before
20959 + * the base band timeout completes. This could result in the
20960 + * rx_clear false triggering. As a workaround we add delay an
20961 + * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
20962 + * does not happen.
20963 + */
20964 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
20965 +}
20966 +
20967 +void ar9003_hw_modify_chain_masks(struct ath_hw *ah,
20968 + u8 rx_chainmask,
20969 + u8 tx_chainmask)
20970 +{
20971 + switch (rx_chainmask) {
20972 + case 0x5:
20973 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
20974 + AR_PHY_SWAP_ALT_CHAIN);
20975 + case 0x3:
20976 + case 0x1:
20977 + case 0x2:
20978 + case 0x7:
20979 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
20980 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
20981 + break;
20982 + default:
20983 + break;
20984 + }
20985 +
20986 + REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
20987 + if (tx_chainmask == 0x5) {
20988 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
20989 + AR_PHY_SWAP_ALT_CHAIN);
20990 + }
20991 +}
20992 +
20993 +static void ar9003_hw_init_chain_masks(struct ath_hw *ah)
20994 +{
20995 + ar9003_hw_modify_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
20996 +}
20997 +
20998 +/*
20999 + * Override INI values with chip specific configuration.
21000 + */
21001 +static void ar9003_hw_override_ini(struct ath_hw *ah)
21002 +{
21003 + u32 val;
21004 +
21005 + /*
21006 + * Set the RX_ABORT and RX_DIS and clear it only after
21007 + * RXE is set for MAC. This prevents frames with
21008 + * corrupted descriptor status.
21009 + */
21010 + REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
21011 +
21012 + /*
21013 + * For AR9280 and above, there is a new feature that allows
21014 + * Multicast search based on both MAC Address and Key ID. By default,
21015 + * this feature is enabled. But since the driver is not using this
21016 + * feature, we switch it off; otherwise multicast search based on
21017 + * MAC addr only will fail.
21018 + */
21019 + val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
21020 + REG_WRITE(ah, AR_PCU_MISC_MODE2, val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
21021 +}
21022 +
21023 +static void ar9003_hw_prog_ini(struct ath_hw *ah,
21024 + struct ar5416IniArray *iniArr,
21025 + int column)
21026 +{
21027 + unsigned int i, regWrites = 0;
21028 +
21029 + /* New INI format: Array may be undefined (pre, core, post arrays) */
21030 + if (!iniArr->ia_array)
21031 + return;
21032 +
21033 + /*
21034 + * New INI format: Pre, core, and post arrays for a given subsystem
21035 + * may be modal (> 2 columns) or non-modal (2 columns). Determine if
21036 + * the array is non-modal and force the column to 1.
21037 + */
21038 + if (column >= iniArr->ia_columns)
21039 + column = 1;
21040 +
21041 + for (i = 0; i < iniArr->ia_rows; i++) {
21042 + u32 reg = INI_RA(iniArr, i, 0);
21043 + u32 val = INI_RA(iniArr, i, column);
21044 +
21045 + REG_WRITE(ah, reg, val);
21046 +
21047 + /*
21048 + * Determine if this is a shift register value, and insert the
21049 + * configured delay if so.
21050 + */
21051 + if (reg >= 0x16000 && reg < 0x17000
21052 + && ah->config.analog_shiftreg)
21053 + udelay(100);
21054 +
21055 + DO_DELAY(regWrites);
21056 + }
21057 +}
21058 +
21059 +static int ar9003_hw_process_ini(struct ath_hw *ah,
21060 + struct ath9k_channel *chan)
21061 +{
21062 + struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
21063 + unsigned int regWrites = 0, i;
21064 + struct ieee80211_channel *channel = chan->chan;
21065 + u32 modesIndex, freqIndex;
21066 +
21067 + switch (chan->chanmode) {
21068 + case CHANNEL_A:
21069 + case CHANNEL_A_HT20:
21070 + modesIndex = 1;
21071 + freqIndex = 1;
21072 + break;
21073 + case CHANNEL_A_HT40PLUS:
21074 + case CHANNEL_A_HT40MINUS:
21075 + modesIndex = 2;
21076 + freqIndex = 1;
21077 + break;
21078 + case CHANNEL_G:
21079 + case CHANNEL_G_HT20:
21080 + case CHANNEL_B:
21081 + modesIndex = 4;
21082 + freqIndex = 2;
21083 + break;
21084 + case CHANNEL_G_HT40PLUS:
21085 + case CHANNEL_G_HT40MINUS:
21086 + modesIndex = 3;
21087 + freqIndex = 2;
21088 + break;
21089 +
21090 + default:
21091 + return -EINVAL;
21092 + }
21093 +
21094 + for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
21095 + ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
21096 + ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
21097 + ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
21098 + ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
21099 + }
21100 +
21101 + REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
21102 + REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
21103 +
21104 + /*
21105 + * For 5GHz channels requiring Fast Clock, apply
21106 + * different modal values.
21107 + */
21108 + if (IS_CHAN_A_5MHZ_SPACED(chan))
21109 + REG_WRITE_ARRAY(&ah->iniModesAdditional,
21110 + modesIndex, regWrites);
21111 +
21112 + ar9003_hw_override_ini(ah);
21113 + ar9003_hw_set_channel_regs(ah, chan);
21114 + ar9003_hw_init_chain_masks(ah);
21115 +
21116 + /* Set TX power */
21117 + ah->eep_ops->set_txpower(ah, chan,
21118 + ath9k_regd_get_ctl(regulatory, chan),
21119 + channel->max_antenna_gain * 2,
21120 + channel->max_power * 2,
21121 + min((u32) MAX_RATE_POWER,
21122 + (u32) regulatory->power_limit));
21123 +
21124 + return 0;
21125 +}
21126 +
21127 +static void ar9003_hw_set_rfmode(struct ath_hw *ah,
21128 + struct ath9k_channel *chan)
21129 +{
21130 + u32 rfMode = 0;
21131 +
21132 + if (chan == NULL)
21133 + return;
21134 +
21135 + rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
21136 + ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
21137 +
21138 + if (IS_CHAN_A_5MHZ_SPACED(chan))
21139 + rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
21140 +
21141 + REG_WRITE(ah, AR_PHY_MODE, rfMode);
21142 +}
21143 +
21144 +static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
21145 +{
21146 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
21147 +}
21148 +
21149 +static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
21150 + struct ath9k_channel *chan)
21151 +{
21152 + u32 coef_scaled, ds_coef_exp, ds_coef_man;
21153 + u32 clockMhzScaled = 0x64000000;
21154 + struct chan_centers centers;
21155 +
21156 + /*
21157 + * half and quarter rate can divide the scaled clock by 2 or 4
21158 + * scale for selected channel bandwidth
21159 + */
21160 + if (IS_CHAN_HALF_RATE(chan))
21161 + clockMhzScaled = clockMhzScaled >> 1;
21162 + else if (IS_CHAN_QUARTER_RATE(chan))
21163 + clockMhzScaled = clockMhzScaled >> 2;
21164 +
21165 + /*
21166 + * ALGO -> coef = 1e8/fcarrier*fclock/40;
21167 + * scaled coef to provide precision for this floating calculation
21168 + */
21169 + ath9k_hw_get_channel_centers(ah, chan, &centers);
21170 + coef_scaled = clockMhzScaled / centers.synth_center;
21171 +
21172 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
21173 + &ds_coef_exp);
21174 +
21175 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
21176 + AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
21177 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
21178 + AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
21179 +
21180 + /*
21181 + * For Short GI,
21182 + * scaled coeff is 9/10 that of normal coeff
21183 + */
21184 + coef_scaled = (9 * coef_scaled) / 10;
21185 +
21186 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
21187 + &ds_coef_exp);
21188 +
21189 + /* for short gi */
21190 + REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
21191 + AR_PHY_SGI_DSC_MAN, ds_coef_man);
21192 + REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
21193 + AR_PHY_SGI_DSC_EXP, ds_coef_exp);
21194 +}
21195 +
21196 +static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
21197 +{
21198 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
21199 + return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
21200 + AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
21201 +}
21202 +
21203 +/*
21204 + * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
21205 + * Read the phy active delay register. Value is in 100ns increments.
21206 + */
21207 +static void ar9003_hw_rfbus_done(struct ath_hw *ah)
21208 +{
21209 + u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
21210 + if (IS_CHAN_B(ah->curchan))
21211 + synthDelay = (4 * synthDelay) / 22;
21212 + else
21213 + synthDelay /= 10;
21214 +
21215 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
21216 +
21217 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
21218 +}
21219 +
21220 +/*
21221 + * Set the interrupt and GPIO values so the ISR can disable RF
21222 + * on a switch signal. Assumes GPIO port and interrupt polarity
21223 + * are set prior to call.
21224 + */
21225 +static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
21226 +{
21227 + /* Connect rfsilent_bb_l to baseband */
21228 + REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
21229 + AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
21230 + /* Set input mux for rfsilent_bb_l to GPIO #0 */
21231 + REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
21232 + AR_GPIO_INPUT_MUX2_RFSILENT);
21233 +
21234 + /*
21235 + * Configure the desired GPIO port for input and
21236 + * enable baseband rf silence.
21237 + */
21238 + ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
21239 + REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
21240 +}
21241 +
21242 +static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
21243 +{
21244 + u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
21245 + if (value)
21246 + v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
21247 + else
21248 + v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
21249 + REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
21250 +}
21251 +
21252 +static bool ar9003_hw_ani_control(struct ath_hw *ah,
21253 + enum ath9k_ani_cmd cmd, int param)
21254 +{
21255 + struct ar5416AniState *aniState = ah->curani;
21256 + struct ath_common *common = ath9k_hw_common(ah);
21257 +
21258 + switch (cmd & ah->ani_function) {
21259 + case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
21260 + u32 level = param;
21261 +
21262 + if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
21263 + ath_print(common, ATH_DBG_ANI,
21264 + "level out of range (%u > %u)\n",
21265 + level,
21266 + (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
21267 + return false;
21268 + }
21269 +
21270 + REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
21271 + AR_PHY_DESIRED_SZ_TOT_DES,
21272 + ah->totalSizeDesired[level]);
21273 + REG_RMW_FIELD(ah, AR_PHY_AGC,
21274 + AR_PHY_AGC_COARSE_LOW,
21275 + ah->coarse_low[level]);
21276 + REG_RMW_FIELD(ah, AR_PHY_AGC,
21277 + AR_PHY_AGC_COARSE_HIGH,
21278 + ah->coarse_high[level]);
21279 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
21280 + AR_PHY_FIND_SIG_FIRPWR, ah->firpwr[level]);
21281 +
21282 + if (level > aniState->noiseImmunityLevel)
21283 + ah->stats.ast_ani_niup++;
21284 + else if (level < aniState->noiseImmunityLevel)
21285 + ah->stats.ast_ani_nidown++;
21286 + aniState->noiseImmunityLevel = level;
21287 + break;
21288 + }
21289 + case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
21290 + const int m1ThreshLow[] = { 127, 50 };
21291 + const int m2ThreshLow[] = { 127, 40 };
21292 + const int m1Thresh[] = { 127, 0x4d };
21293 + const int m2Thresh[] = { 127, 0x40 };
21294 + const int m2CountThr[] = { 31, 16 };
21295 + const int m2CountThrLow[] = { 63, 48 };
21296 + u32 on = param ? 1 : 0;
21297 +
21298 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
21299 + AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
21300 + m1ThreshLow[on]);
21301 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
21302 + AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
21303 + m2ThreshLow[on]);
21304 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
21305 + AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
21306 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
21307 + AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
21308 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
21309 + AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
21310 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
21311 + AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2CountThrLow[on]);
21312 +
21313 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
21314 + AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);
21315 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
21316 + AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);
21317 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
21318 + AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);
21319 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
21320 + AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);
21321 +
21322 + if (on)
21323 + REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
21324 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
21325 + else
21326 + REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
21327 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
21328 +
21329 + if (!on != aniState->ofdmWeakSigDetectOff) {
21330 + if (on)
21331 + ah->stats.ast_ani_ofdmon++;
21332 + else
21333 + ah->stats.ast_ani_ofdmoff++;
21334 + aniState->ofdmWeakSigDetectOff = !on;
21335 + }
21336 + break;
21337 + }
21338 + case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
21339 + const int weakSigThrCck[] = { 8, 6 };
21340 + u32 high = param ? 1 : 0;
21341 +
21342 + REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
21343 + AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
21344 + weakSigThrCck[high]);
21345 + if (high != aniState->cckWeakSigThreshold) {
21346 + if (high)
21347 + ah->stats.ast_ani_cckhigh++;
21348 + else
21349 + ah->stats.ast_ani_ccklow++;
21350 + aniState->cckWeakSigThreshold = high;
21351 + }
21352 + break;
21353 + }
21354 + case ATH9K_ANI_FIRSTEP_LEVEL:{
21355 + const int firstep[] = { 0, 4, 8 };
21356 + u32 level = param;
21357 +
21358 + if (level >= ARRAY_SIZE(firstep)) {
21359 + ath_print(common, ATH_DBG_ANI,
21360 + "level out of range (%u > %u)\n",
21361 + level,
21362 + (unsigned) ARRAY_SIZE(firstep));
21363 + return false;
21364 + }
21365 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
21366 + AR_PHY_FIND_SIG_FIRSTEP,
21367 + firstep[level]);
21368 + if (level > aniState->firstepLevel)
21369 + ah->stats.ast_ani_stepup++;
21370 + else if (level < aniState->firstepLevel)
21371 + ah->stats.ast_ani_stepdown++;
21372 + aniState->firstepLevel = level;
21373 + break;
21374 + }
21375 + case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
21376 + const int cycpwrThr1[] =
21377 + { 2, 4, 6, 8, 10, 12, 14, 16 };
21378 + u32 level = param;
21379 +
21380 + if (level >= ARRAY_SIZE(cycpwrThr1)) {
21381 + ath_print(common, ATH_DBG_ANI,
21382 + "level out of range (%u > %u)\n",
21383 + level,
21384 + (unsigned) ARRAY_SIZE(cycpwrThr1));
21385 + return false;
21386 + }
21387 + REG_RMW_FIELD(ah, AR_PHY_TIMING5,
21388 + AR_PHY_TIMING5_CYCPWR_THR1,
21389 + cycpwrThr1[level]);
21390 + if (level > aniState->spurImmunityLevel)
21391 + ah->stats.ast_ani_spurup++;
21392 + else if (level < aniState->spurImmunityLevel)
21393 + ah->stats.ast_ani_spurdown++;
21394 + aniState->spurImmunityLevel = level;
21395 + break;
21396 + }
21397 + case ATH9K_ANI_PRESENT:
21398 + break;
21399 + default:
21400 + ath_print(common, ATH_DBG_ANI,
21401 + "invalid cmd %u\n", cmd);
21402 + return false;
21403 + }
21404 +
21405 + ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
21406 + ath_print(common, ATH_DBG_ANI,
21407 + "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
21408 + "ofdmWeakSigDetectOff=%d\n",
21409 + aniState->noiseImmunityLevel,
21410 + aniState->spurImmunityLevel,
21411 + !aniState->ofdmWeakSigDetectOff);
21412 + ath_print(common, ATH_DBG_ANI,
21413 + "cckWeakSigThreshold=%d, "
21414 + "firstepLevel=%d, listenTime=%d\n",
21415 + aniState->cckWeakSigThreshold,
21416 + aniState->firstepLevel,
21417 + aniState->listenTime);
21418 + ath_print(common, ATH_DBG_ANI,
21419 + "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
21420 + aniState->cycleCount,
21421 + aniState->ofdmPhyErrCount,
21422 + aniState->cckPhyErrCount);
21423 +
21424 + return true;
21425 +}
21426 +
21427 +static void ar9003_hw_nf_sanitize_2g(struct ath_hw *ah, s16 *nf)
21428 +{
21429 + struct ath_common *common = ath9k_hw_common(ah);
21430 +
21431 + if (*nf > ah->nf_2g_max) {
21432 + ath_print(common, ATH_DBG_CALIBRATE,
21433 + "2 GHz NF (%d) > MAX (%d), "
21434 + "correcting to MAX",
21435 + *nf, ah->nf_2g_max);
21436 + *nf = ah->nf_2g_max;
21437 + } else if (*nf < ah->nf_2g_min) {
21438 + ath_print(common, ATH_DBG_CALIBRATE,
21439 + "2 GHz NF (%d) < MIN (%d), "
21440 + "correcting to MIN",
21441 + *nf, ah->nf_2g_min);
21442 + *nf = ah->nf_2g_min;
21443 + }
21444 +}
21445 +
21446 +static void ar9003_hw_nf_sanitize_5g(struct ath_hw *ah, s16 *nf)
21447 +{
21448 + struct ath_common *common = ath9k_hw_common(ah);
21449 +
21450 + if (*nf > ah->nf_5g_max) {
21451 + ath_print(common, ATH_DBG_CALIBRATE,
21452 + "5 GHz NF (%d) > MAX (%d), "
21453 + "correcting to MAX",
21454 + *nf, ah->nf_5g_max);
21455 + *nf = ah->nf_5g_max;
21456 + } else if (*nf < ah->nf_5g_min) {
21457 + ath_print(common, ATH_DBG_CALIBRATE,
21458 + "5 GHz NF (%d) < MIN (%d), "
21459 + "correcting to MIN",
21460 + *nf, ah->nf_5g_min);
21461 + *nf = ah->nf_5g_min;
21462 + }
21463 +}
21464 +
21465 +static void ar9003_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
21466 +{
21467 + if (IS_CHAN_2GHZ(ah->curchan))
21468 + ar9003_hw_nf_sanitize_2g(ah, nf);
21469 + else
21470 + ar9003_hw_nf_sanitize_5g(ah, nf);
21471 +}
21472 +
21473 +static void ar9003_hw_do_getnf(struct ath_hw *ah,
21474 + int16_t nfarray[NUM_NF_READINGS])
21475 +{
21476 + struct ath_common *common = ath9k_hw_common(ah);
21477 + int16_t nf;
21478 +
21479 + nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
21480 + if (nf & 0x100)
21481 + nf = 0 - ((nf ^ 0x1ff) + 1);
21482 + ar9003_hw_nf_sanitize(ah, &nf);
21483 + ath_print(common, ATH_DBG_CALIBRATE,
21484 + "NF calibrated [ctl] [chain 0] is %d\n", nf);
21485 + nfarray[0] = nf;
21486 +
21487 + nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
21488 + if (nf & 0x100)
21489 + nf = 0 - ((nf ^ 0x1ff) + 1);
21490 + ar9003_hw_nf_sanitize(ah, &nf);
21491 + ath_print(common, ATH_DBG_CALIBRATE,
21492 + "NF calibrated [ctl] [chain 1] is %d\n", nf);
21493 + nfarray[1] = nf;
21494 +
21495 + nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
21496 + if (nf & 0x100)
21497 + nf = 0 - ((nf ^ 0x1ff) + 1);
21498 + ar9003_hw_nf_sanitize(ah, &nf);
21499 + ath_print(common, ATH_DBG_CALIBRATE,
21500 + "NF calibrated [ctl] [chain 2] is %d\n", nf);
21501 + nfarray[2] = nf;
21502 +
21503 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
21504 + if (nf & 0x100)
21505 + nf = 0 - ((nf ^ 0x1ff) + 1);
21506 + ar9003_hw_nf_sanitize(ah, &nf);
21507 + ath_print(common, ATH_DBG_CALIBRATE,
21508 + "NF calibrated [ext] [chain 0] is %d\n", nf);
21509 + nfarray[3] = nf;
21510 +
21511 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
21512 + if (nf & 0x100)
21513 + nf = 0 - ((nf ^ 0x1ff) + 1);
21514 + ar9003_hw_nf_sanitize(ah, &nf);
21515 + ath_print(common, ATH_DBG_CALIBRATE,
21516 + "NF calibrated [ext] [chain 1] is %d\n", nf);
21517 + nfarray[4] = nf;
21518 +
21519 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
21520 + if (nf & 0x100)
21521 + nf = 0 - ((nf ^ 0x1ff) + 1);
21522 + ar9003_hw_nf_sanitize(ah, &nf);
21523 + ath_print(common, ATH_DBG_CALIBRATE,
21524 + "NF calibrated [ext] [chain 2] is %d\n", nf);
21525 + nfarray[5] = nf;
21526 +}
21527 +
21528 +void ar9003_hw_set_nf_limits(struct ath_hw *ah)
21529 +{
21530 + ah->nf_2g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
21531 + ah->nf_2g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
21532 + ah->nf_5g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
21533 + ah->nf_5g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
21534 +}
21535 +
21536 +/*
21537 + * Find out which of the RX chains are enabled
21538 + */
21539 +static u32 ar9003_hw_get_rx_chainmask(struct ath_hw *ah)
21540 +{
21541 + u32 chain = REG_READ(ah, AR_PHY_RX_CHAINMASK);
21542 + /*
21543 + * The bits [2:0] indicate the rx chain mask and are to be
21544 + * interpreted as follows:
21545 + * 00x => Only chain 0 is enabled
21546 + * 01x => Chain 1 and 0 enabled
21547 + * 1xx => Chain 2,1 and 0 enabled
21548 + */
21549 + return (chain & 0x7);
21550 +}
21551 +
21552 +static void ar9003_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
21553 +{
21554 + struct ath9k_nfcal_hist *h;
21555 + unsigned i, j;
21556 + int32_t val;
21557 + const u32 ar9300_cca_regs[6] = {
21558 + AR_PHY_CCA_0,
21559 + AR_PHY_CCA_1,
21560 + AR_PHY_CCA_2,
21561 + AR_PHY_EXT_CCA,
21562 + AR_PHY_EXT_CCA_1,
21563 + AR_PHY_EXT_CCA_2,
21564 + };
21565 + u8 chainmask, rx_chain_status;
21566 + struct ath_common *common = ath9k_hw_common(ah);
21567 +
21568 + rx_chain_status = ar9003_hw_get_rx_chainmask(ah);
21569 +
21570 + chainmask = 0x3F;
21571 + h = ah->nfCalHist;
21572 +
21573 + for (i = 0; i < NUM_NF_READINGS; i++) {
21574 + if (chainmask & (1 << i)) {
21575 + val = REG_READ(ah, ar9300_cca_regs[i]);
21576 + val &= 0xFFFFFE00;
21577 + val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
21578 + REG_WRITE(ah, ar9300_cca_regs[i], val);
21579 + }
21580 + }
21581 +
21582 + /*
21583 + * Load software filtered NF value into baseband internal minCCApwr
21584 + * variable.
21585 + */
21586 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
21587 + AR_PHY_AGC_CONTROL_ENABLE_NF);
21588 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
21589 + AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
21590 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
21591 +
21592 + /*
21593 + * Wait for load to complete, should be fast, a few 10s of us.
21594 + * The max delay was changed from an original 250us to 10000us
21595 + * since 250us often results in NF load timeout and causes deaf
21596 + * condition during stress testing 12/12/2009
21597 + */
21598 + for (j = 0; j < 1000; j++) {
21599 + if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
21600 + AR_PHY_AGC_CONTROL_NF) == 0)
21601 + break;
21602 + udelay(10);
21603 + }
21604 +
21605 + /*
21606 + * We timed out waiting for the noisefloor to load, probably due to an
21607 + * in-progress rx. Simply return here and allow the load plenty of time
21608 + * to complete before the next calibration interval. We need to avoid
21609 + * trying to load -50 (which happens below) while the previous load is
21610 + * still in progress as this can cause rx deafness. Instead by returning
21611 + * here, the baseband nf cal will just be capped by our present
21612 + * noisefloor until the next calibration timer.
21613 + */
21614 + if (j == 1000) {
21615 + ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf "
21616 + "to load: AR_PHY_AGC_CONTROL=0x%x\n",
21617 + REG_READ(ah, AR_PHY_AGC_CONTROL));
21618 + }
21619 +
21620 + /*
21621 + * Restore maxCCAPower register parameter again so that we're not capped
21622 + * by the median we just loaded. This will be initial (and max) value
21623 + * of next noise floor calibration the baseband does.
21624 + */
21625 + for (i = 0; i < NUM_NF_READINGS; i++) {
21626 + if (chainmask & (1 << i)) {
21627 + val = REG_READ(ah, ar9300_cca_regs[i]);
21628 + val &= 0xFFFFFE00;
21629 + val |= (((u32) (-50) << 1) & 0x1ff);
21630 + REG_WRITE(ah, ar9300_cca_regs[i], val);
21631 + }
21632 + }
21633 +}
21634 +
21635 +void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
21636 +{
21637 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
21638 +
21639 + priv_ops->rf_set_freq = ar9003_hw_set_channel;
21640 + priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
21641 + priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
21642 + priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
21643 + priv_ops->init_bb = ar9003_hw_init_bb;
21644 + priv_ops->process_ini = ar9003_hw_process_ini;
21645 + priv_ops->set_rfmode = ar9003_hw_set_rfmode;
21646 + priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
21647 + priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
21648 + priv_ops->rfbus_req = ar9003_hw_rfbus_req;
21649 + priv_ops->rfbus_done = ar9003_hw_rfbus_done;
21650 + priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
21651 + priv_ops->set_diversity = ar9003_hw_set_diversity;
21652 + priv_ops->ani_control = ar9003_hw_ani_control;
21653 + priv_ops->do_getnf = ar9003_hw_do_getnf;
21654 + priv_ops->loadnf = ar9003_hw_loadnf;
21655 +}
21656 diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
21657 new file mode 100644
21658 index 0000000..e330382
21659 --- /dev/null
21660 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
21661 @@ -0,0 +1,849 @@
21662 +/*
21663 + * Copyright (c) 2002-2010 Atheros Communications, Inc.
21664 + *
21665 + * Permission to use, copy, modify, and/or distribute this software for any
21666 + * purpose with or without fee is hereby granted, provided that the above
21667 + * copyright notice and this permission notice appear in all copies.
21668 + *
21669 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
21670 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
21671 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
21672 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
21673 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
21674 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
21675 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21676 + */
21677 +
21678 +#ifndef AR9003_PHY_H
21679 +#define AR9003_PHY_H
21680 +
21681 +/*
21682 + * Channel Register Map
21683 + */
21684 +#define AR_CHAN_BASE 0x9800
21685 +
21686 +#define AR_PHY_TIMING1 AR_CHAN_BASE + 0x0
21687 +#define AR_PHY_TIMING2 AR_CHAN_BASE + 0x4
21688 +#define AR_PHY_TIMING3 AR_CHAN_BASE + 0x8
21689 +#define AR_PHY_TIMING4 AR_CHAN_BASE + 0xc
21690 +#define AR_PHY_TIMING5 AR_CHAN_BASE + 0x10
21691 +#define AR_PHY_TIMING6 AR_CHAN_BASE + 0x14
21692 +#define AR_PHY_TIMING11 AR_CHAN_BASE + 0x18
21693 +#define AR_PHY_SPUR_REG AR_CHAN_BASE + 0x1c
21694 +#define AR_PHY_RX_IQCAL_CORR_B0 AR_CHAN_BASE + 0xdc
21695 +#define AR_PHY_TX_IQCAL_CONTROL_3 AR_CHAN_BASE + 0xb0
21696 +
21697 +#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
21698 +#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
21699 +
21700 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
21701 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
21702 +
21703 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
21704 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30
21705 +
21706 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
21707 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31
21708 +
21709 +#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
21710 +#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 26
21711 +
21712 +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
21713 +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 17
21714 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
21715 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
21716 +#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
21717 +#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 8
21718 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000
21719 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
21720 +
21721 +#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000
21722 +#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29
21723 +
21724 +#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000
21725 +#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31
21726 +
21727 +#define AR_PHY_FIND_SIG_LOW AR_CHAN_BASE + 0x20
21728 +
21729 +#define AR_PHY_SFCORR AR_CHAN_BASE + 0x24
21730 +#define AR_PHY_SFCORR_LOW AR_CHAN_BASE + 0x28
21731 +#define AR_PHY_SFCORR_EXT AR_CHAN_BASE + 0x2c
21732 +
21733 +#define AR_PHY_EXT_CCA AR_CHAN_BASE + 0x30
21734 +#define AR_PHY_RADAR_0 AR_CHAN_BASE + 0x34
21735 +#define AR_PHY_RADAR_1 AR_CHAN_BASE + 0x38
21736 +#define AR_PHY_RADAR_EXT AR_CHAN_BASE + 0x3c
21737 +#define AR_PHY_MULTICHAIN_CTRL AR_CHAN_BASE + 0x80
21738 +#define AR_PHY_PERCHAIN_CSD AR_CHAN_BASE + 0x84
21739 +
21740 +#define AR_PHY_TX_PHASE_RAMP_0 AR_CHAN_BASE + 0xd0
21741 +#define AR_PHY_ADC_GAIN_DC_CORR_0 AR_CHAN_BASE + 0xd4
21742 +#define AR_PHY_IQ_ADC_MEAS_0_B0 AR_CHAN_BASE + 0xc0
21743 +#define AR_PHY_IQ_ADC_MEAS_1_B0 AR_CHAN_BASE + 0xc4
21744 +#define AR_PHY_IQ_ADC_MEAS_2_B0 AR_CHAN_BASE + 0xc8
21745 +#define AR_PHY_IQ_ADC_MEAS_3_B0 AR_CHAN_BASE + 0xcc
21746 +
21747 +/* The following registers changed position from AR9300 1.0 to AR9300 2.0 */
21748 +#define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10)
21749 +#define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 (AR_CHAN_BASE + 0xd4 - 0x10)
21750 +#define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 (AR_CHAN_BASE + 0xc0 + 0x8)
21751 +#define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 (AR_CHAN_BASE + 0xc4 + 0x8)
21752 +#define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 (AR_CHAN_BASE + 0xc8 + 0x8)
21753 +#define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 (AR_CHAN_BASE + 0xcc + 0x8)
21754 +
21755 +#define AR_PHY_TX_CRC AR_CHAN_BASE + 0xa0
21756 +#define AR_PHY_TST_DAC_CONST AR_CHAN_BASE + 0xa4
21757 +#define AR_PHY_SPUR_REPORT_0 AR_CHAN_BASE + 0xa8
21758 +#define AR_PHY_CHAN_INFO_TAB_0 AR_CHAN_BASE + 0x300
21759 +
21760 +/*
21761 + * Channel Field Definitions
21762 + */
21763 +#define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000
21764 +#define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff
21765 +#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
21766 +#define AR_PHY_TIMING3_DSC_MAN_S 17
21767 +#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
21768 +#define AR_PHY_TIMING3_DSC_EXP_S 13
21769 +#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000
21770 +#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12
21771 +#define AR_PHY_TIMING4_DO_CAL 0x10000
21772 +
21773 +#define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000
21774 +#define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28
21775 +#define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000
21776 +#define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29
21777 +
21778 +#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
21779 +#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30
21780 +#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
21781 +#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31
21782 +
21783 +#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
21784 +#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
21785 +#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
21786 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
21787 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
21788 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
21789 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
21790 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
21791 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
21792 +#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
21793 +#define AR_PHY_SFCORR_M2COUNT_THR_S 0
21794 +#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
21795 +#define AR_PHY_SFCORR_M1_THRESH_S 17
21796 +#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
21797 +#define AR_PHY_SFCORR_M2_THRESH_S 24
21798 +#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
21799 +#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
21800 +#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
21801 +#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
21802 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
21803 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
21804 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
21805 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
21806 +#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
21807 +#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28
21808 +#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
21809 +#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
21810 +#define AR_PHY_EXT_CCA_THRESH62_S 16
21811 +#define AR_PHY_EXT_MINCCA_PWR 0x01FF0000
21812 +#define AR_PHY_EXT_MINCCA_PWR_S 16
21813 +#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
21814 +#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
21815 +#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001
21816 +#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0
21817 +#define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000
21818 +#define AR_PHY_TIMING5_CYCPWR_THR1A_S 16
21819 +#define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16)
21820 +#define AR_PHY_TIMING5_RSSI_THR1A_S 16
21821 +#define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)
21822 +#define AR_PHY_RADAR_0_ENA 0x00000001
21823 +#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
21824 +#define AR_PHY_RADAR_0_INBAND 0x0000003e
21825 +#define AR_PHY_RADAR_0_INBAND_S 1
21826 +#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
21827 +#define AR_PHY_RADAR_0_PRSSI_S 6
21828 +#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
21829 +#define AR_PHY_RADAR_0_HEIGHT_S 12
21830 +#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
21831 +#define AR_PHY_RADAR_0_RRSSI_S 18
21832 +#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
21833 +#define AR_PHY_RADAR_0_FIRPWR_S 24
21834 +#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
21835 +#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
21836 +#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
21837 +#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
21838 +#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
21839 +#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
21840 +#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
21841 +#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
21842 +#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
21843 +#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
21844 +#define AR_PHY_RADAR_1_MAXLEN_S 0
21845 +#define AR_PHY_RADAR_EXT_ENA 0x00004000
21846 +#define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000
21847 +#define AR_PHY_RADAR_DC_PWR_THRESH_S 15
21848 +#define AR_PHY_RADAR_LB_DC_CAP 0x7f800000
21849 +#define AR_PHY_RADAR_LB_DC_CAP_S 23
21850 +#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)
21851 +#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6
21852 +#define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12)
21853 +#define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12
21854 +#define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19
21855 +#define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f
21856 +#define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0
21857 +#define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5
21858 +#define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008
21859 +#define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3
21860 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F
21861 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0
21862 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80
21863 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7
21864 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000
21865 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000
21866 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15
21867 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000
21868 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22
21869 +
21870 +/*
21871 + * MRC Register Map
21872 + */
21873 +#define AR_MRC_BASE 0x9c00
21874 +
21875 +#define AR_PHY_TIMING_3A AR_MRC_BASE + 0x0
21876 +#define AR_PHY_LDPC_CNTL1 AR_MRC_BASE + 0x4
21877 +#define AR_PHY_LDPC_CNTL2 AR_MRC_BASE + 0x8
21878 +#define AR_PHY_PILOT_SPUR_MASK AR_MRC_BASE + 0xc
21879 +#define AR_PHY_CHAN_SPUR_MASK AR_MRC_BASE + 0x10
21880 +#define AR_PHY_SGI_DELTA AR_MRC_BASE + 0x14
21881 +#define AR_PHY_ML_CNTL_1 AR_MRC_BASE + 0x18
21882 +#define AR_PHY_ML_CNTL_2 AR_MRC_BASE + 0x1c
21883 +#define AR_PHY_TST_ADC AR_MRC_BASE + 0x20
21884 +
21885 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0
21886 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5
21887 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F
21888 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0
21889 +
21890 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0
21891 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5
21892 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F
21893 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0
21894 +
21895 +/*
21896 + * MRC Feild Definitions
21897 + */
21898 +#define AR_PHY_SGI_DSC_MAN 0x0007FFF0
21899 +#define AR_PHY_SGI_DSC_MAN_S 4
21900 +#define AR_PHY_SGI_DSC_EXP 0x0000000F
21901 +#define AR_PHY_SGI_DSC_EXP_S 0
21902 +/*
21903 + * BBB Register Map
21904 + */
21905 +#define AR_BBB_BASE 0x9d00
21906 +
21907 +/*
21908 + * AGC Register Map
21909 + */
21910 +#define AR_AGC_BASE 0x9e00
21911 +
21912 +#define AR_PHY_SETTLING AR_AGC_BASE + 0x0
21913 +#define AR_PHY_FORCEMAX_GAINS_0 AR_AGC_BASE + 0x4
21914 +#define AR_PHY_GAINS_MINOFF0 AR_AGC_BASE + 0x8
21915 +#define AR_PHY_DESIRED_SZ AR_AGC_BASE + 0xc
21916 +#define AR_PHY_FIND_SIG AR_AGC_BASE + 0x10
21917 +#define AR_PHY_AGC AR_AGC_BASE + 0x14
21918 +#define AR_PHY_EXT_ATTEN_CTL_0 AR_AGC_BASE + 0x18
21919 +#define AR_PHY_CCA_0 AR_AGC_BASE + 0x1c
21920 +#define AR_PHY_EXT_CCA0 AR_AGC_BASE + 0x20
21921 +#define AR_PHY_RESTART AR_AGC_BASE + 0x24
21922 +#define AR_PHY_MC_GAIN_CTRL AR_AGC_BASE + 0x28
21923 +#define AR_PHY_EXTCHN_PWRTHR1 AR_AGC_BASE + 0x2c
21924 +#define AR_PHY_EXT_CHN_WIN AR_AGC_BASE + 0x30
21925 +#define AR_PHY_20_40_DET_THR AR_AGC_BASE + 0x34
21926 +#define AR_PHY_RIFS_SRCH AR_AGC_BASE + 0x38
21927 +#define AR_PHY_PEAK_DET_CTRL_1 AR_AGC_BASE + 0x3c
21928 +#define AR_PHY_PEAK_DET_CTRL_2 AR_AGC_BASE + 0x40
21929 +#define AR_PHY_RX_GAIN_BOUNDS_1 AR_AGC_BASE + 0x44
21930 +#define AR_PHY_RX_GAIN_BOUNDS_2 AR_AGC_BASE + 0x48
21931 +#define AR_PHY_RSSI_0 AR_AGC_BASE + 0x180
21932 +#define AR_PHY_SPUR_CCK_REP0 AR_AGC_BASE + 0x184
21933 +#define AR_PHY_CCK_DETECT AR_AGC_BASE + 0x1c0
21934 +#define AR_PHY_DAG_CTRLCCK AR_AGC_BASE + 0x1c4
21935 +#define AR_PHY_IQCORR_CTRL_CCK AR_AGC_BASE + 0x1c8
21936 +
21937 +#define AR_PHY_CCK_SPUR_MIT AR_AGC_BASE + 0x1cc
21938 +#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe
21939 +#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1
21940 +#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000
21941 +#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29
21942 +#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001
21943 +#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0
21944 +#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00
21945 +#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9
21946 +
21947 +#define AR_PHY_RX_OCGAIN AR_AGC_BASE + 0x200
21948 +
21949 +#define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110
21950 +#define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115
21951 +#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125
21952 +#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125
21953 +#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
21954 +#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
21955 +
21956 +/*
21957 + * AGC Field Definitions
21958 + */
21959 +#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000
21960 +#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18
21961 +#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00
21962 +#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10
21963 +#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F
21964 +#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0
21965 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000
21966 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17
21967 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000
21968 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12
21969 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0
21970 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6
21971 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F
21972 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0
21973 +#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
21974 +#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
21975 +#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
21976 +#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
21977 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
21978 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
21979 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
21980 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
21981 +#define AR_PHY_SETTLING_SWITCH 0x00003F80
21982 +#define AR_PHY_SETTLING_SWITCH_S 7
21983 +#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
21984 +#define AR_PHY_DESIRED_SZ_ADC_S 0
21985 +#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
21986 +#define AR_PHY_DESIRED_SZ_PGA_S 8
21987 +#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
21988 +#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
21989 +#define AR_PHY_MINCCA_PWR 0x1FF00000
21990 +#define AR_PHY_MINCCA_PWR_S 20
21991 +#define AR_PHY_CCA_THRESH62 0x0007F000
21992 +#define AR_PHY_CCA_THRESH62_S 12
21993 +#define AR9280_PHY_MINCCA_PWR 0x1FF00000
21994 +#define AR9280_PHY_MINCCA_PWR_S 20
21995 +#define AR9280_PHY_CCA_THRESH62 0x000FF000
21996 +#define AR9280_PHY_CCA_THRESH62_S 12
21997 +#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
21998 +#define AR_PHY_EXT_CCA0_THRESH62_S 0
21999 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
22000 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
22001 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
22002 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
22003 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
22004 +
22005 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
22006 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9
22007 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
22008 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
22009 +
22010 +#define AR_PHY_RIFS_INIT_DELAY 0x3ff0000
22011 +#define AR_PHY_AGC_COARSE_LOW 0x00007F80
22012 +#define AR_PHY_AGC_COARSE_LOW_S 7
22013 +#define AR_PHY_AGC_COARSE_HIGH 0x003F8000
22014 +#define AR_PHY_AGC_COARSE_HIGH_S 15
22015 +#define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F
22016 +#define AR_PHY_AGC_COARSE_PWR_CONST_S 0
22017 +#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
22018 +#define AR_PHY_FIND_SIG_FIRSTEP_S 12
22019 +#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
22020 +#define AR_PHY_FIND_SIG_FIRPWR_S 18
22021 +#define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25
22022 +#define AR_PHY_FIND_SIG_RELPWR (0x1f << 6)
22023 +#define AR_PHY_FIND_SIG_RELPWR_S 6
22024 +#define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11
22025 +#define AR_PHY_FIND_SIG_RELSTEP 0x1f
22026 +#define AR_PHY_FIND_SIG_RELSTEP_S 0
22027 +#define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5
22028 +#define AR_PHY_RESTART_DIV_GC 0x001C0000
22029 +#define AR_PHY_RESTART_DIV_GC_S 18
22030 +#define AR_PHY_RESTART_ENA 0x01
22031 +#define AR_PHY_DC_RESTART_DIS 0x40000000
22032 +
22033 +#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000
22034 +#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24
22035 +#define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000
22036 +#define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16
22037 +
22038 +#define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000
22039 +#define AR_PHY_TPC_6_ERROR_EST_MODE_S 24
22040 +
22041 +/*
22042 + * SM Register Map
22043 + */
22044 +#define AR_SM_BASE 0xa200
22045 +
22046 +#define AR_PHY_D2_CHIP_ID AR_SM_BASE + 0x0
22047 +#define AR_PHY_GEN_CTRL AR_SM_BASE + 0x4
22048 +#define AR_PHY_MODE AR_SM_BASE + 0x8
22049 +#define AR_PHY_ACTIVE AR_SM_BASE + 0xc
22050 +#define AR_PHY_SPUR_MASK_A AR_SM_BASE + 0x20
22051 +#define AR_PHY_SPUR_MASK_B AR_SM_BASE + 0x24
22052 +#define AR_PHY_SPECTRAL_SCAN AR_SM_BASE + 0x28
22053 +#define AR_PHY_RADAR_BW_FILTER AR_SM_BASE + 0x2c
22054 +#define AR_PHY_SEARCH_START_DELAY AR_SM_BASE + 0x30
22055 +#define AR_PHY_MAX_RX_LEN AR_SM_BASE + 0x34
22056 +#define AR_PHY_FRAME_CTL AR_SM_BASE + 0x38
22057 +#define AR_PHY_RFBUS_REQ AR_SM_BASE + 0x3c
22058 +#define AR_PHY_RFBUS_GRANT AR_SM_BASE + 0x40
22059 +#define AR_PHY_RIFS AR_SM_BASE + 0x44
22060 +#define AR_PHY_RX_CLR_DELAY AR_SM_BASE + 0x50
22061 +#define AR_PHY_RX_DELAY AR_SM_BASE + 0x54
22062 +
22063 +#define AR_PHY_XPA_TIMING_CTL AR_SM_BASE + 0x64
22064 +#define AR_PHY_MISC_PA_CTL AR_SM_BASE + 0x80
22065 +#define AR_PHY_SWITCH_CHAIN_0 AR_SM_BASE + 0x84
22066 +#define AR_PHY_SWITCH_COM AR_SM_BASE + 0x88
22067 +#define AR_PHY_SWITCH_COM_2 AR_SM_BASE + 0x8c
22068 +#define AR_PHY_RX_CHAINMASK AR_SM_BASE + 0xa0
22069 +#define AR_PHY_CAL_CHAINMASK AR_SM_BASE + 0xc0
22070 +#define AR_PHY_CALMODE AR_SM_BASE + 0xc8
22071 +#define AR_PHY_FCAL_1 AR_SM_BASE + 0xcc
22072 +#define AR_PHY_FCAL_2_0 AR_SM_BASE + 0xd0
22073 +#define AR_PHY_DFT_TONE_CTL_0 AR_SM_BASE + 0xd4
22074 +#define AR_PHY_CL_CAL_CTL AR_SM_BASE + 0xd8
22075 +#define AR_PHY_CL_TAB_0 AR_SM_BASE + 0x100
22076 +#define AR_PHY_SYNTH_CONTROL AR_SM_BASE + 0x140
22077 +#define AR_PHY_ADDAC_CLK_SEL AR_SM_BASE + 0x144
22078 +#define AR_PHY_PLL_CTL AR_SM_BASE + 0x148
22079 +#define AR_PHY_ANALOG_SWAP AR_SM_BASE + 0x14c
22080 +#define AR_PHY_ADDAC_PARA_CTL AR_SM_BASE + 0x150
22081 +#define AR_PHY_XPA_CFG AR_SM_BASE + 0x158
22082 +
22083 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00
22084 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10
22085 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF
22086 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0
22087 +
22088 +#define AR_PHY_TEST AR_SM_BASE + 0x160
22089 +
22090 +#define AR_PHY_TEST_BBB_OBS_SEL 0x780000
22091 +#define AR_PHY_TEST_BBB_OBS_SEL_S 19
22092 +
22093 +#define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23
22094 +#define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)
22095 +
22096 +#define AR_PHY_TEST_CHAIN_SEL 0xC0000000
22097 +#define AR_PHY_TEST_CHAIN_SEL_S 30
22098 +
22099 +#define AR_PHY_TEST_CTL_STATUS AR_SM_BASE + 0x164
22100 +#define AR_PHY_TEST_CTL_TSTDAC_EN 0x1
22101 +#define AR_PHY_TEST_CTL_TSTDAC_EN_S 0
22102 +#define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C
22103 +#define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2
22104 +#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60
22105 +#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5
22106 +#define AR_PHY_TEST_CTL_TSTADC_EN 0x100
22107 +#define AR_PHY_TEST_CTL_TSTADC_EN_S 8
22108 +#define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00
22109 +#define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10
22110 +
22111 +
22112 +#define AR_PHY_TSTDAC AR_SM_BASE + 0x168
22113 +
22114 +#define AR_PHY_CHAN_STATUS AR_SM_BASE + 0x16c
22115 +#define AR_PHY_CHAN_INFO_MEMORY AR_SM_BASE + 0x170
22116 +#define AR_PHY_CHNINFO_NOISEPWR AR_SM_BASE + 0x174
22117 +#define AR_PHY_CHNINFO_GAINDIFF AR_SM_BASE + 0x178
22118 +#define AR_PHY_CHNINFO_FINETIM AR_SM_BASE + 0x17c
22119 +#define AR_PHY_CHAN_INFO_GAIN_0 AR_SM_BASE + 0x180
22120 +#define AR_PHY_SCRAMBLER_SEED AR_SM_BASE + 0x190
22121 +#define AR_PHY_CCK_TX_CTRL AR_SM_BASE + 0x194
22122 +
22123 +#define AR_PHY_HEAVYCLIP_CTL AR_SM_BASE + 0x1a4
22124 +#define AR_PHY_HEAVYCLIP_20 AR_SM_BASE + 0x1a8
22125 +#define AR_PHY_HEAVYCLIP_40 AR_SM_BASE + 0x1ac
22126 +#define AR_PHY_ILLEGAL_TXRATE AR_SM_BASE + 0x1b0
22127 +
22128 +#define AR_PHY_PWRTX_MAX AR_SM_BASE + 0x1f0
22129 +#define AR_PHY_POWER_TX_SUB AR_SM_BASE + 0x1f4
22130 +
22131 +#define AR_PHY_TPC_4_B0 AR_SM_BASE + 0x204
22132 +#define AR_PHY_TPC_5_B0 AR_SM_BASE + 0x208
22133 +#define AR_PHY_TPC_6_B0 AR_SM_BASE + 0x20c
22134 +#define AR_PHY_TPC_11_B0 AR_SM_BASE + 0x220
22135 +#define AR_PHY_TPC_18 AR_SM_BASE + 0x23c
22136 +#define AR_PHY_TPC_19 AR_SM_BASE + 0x240
22137 +
22138 +#define AR_PHY_TX_FORCED_GAIN AR_SM_BASE + 0x258
22139 +
22140 +#define AR_PHY_PDADC_TAB_0 AR_SM_BASE + 0x280
22141 +
22142 +#define AR_PHY_TX_IQCAL_CONTROL_1 AR_SM_BASE + 0x448
22143 +#define AR_PHY_TX_IQCAL_START AR_SM_BASE + 0x440
22144 +#define AR_PHY_TX_IQCAL_STATUS_B0 AR_SM_BASE + 0x48c
22145 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 AR_SM_BASE + 0x450
22146 +
22147 +#define AR_PHY_PANIC_WD_STATUS AR_SM_BASE + 0x5c0
22148 +#define AR_PHY_PANIC_WD_CTL_1 AR_SM_BASE + 0x5c4
22149 +#define AR_PHY_PANIC_WD_CTL_2 AR_SM_BASE + 0x5c8
22150 +#define AR_PHY_BT_CTL AR_SM_BASE + 0x5cc
22151 +#define AR_PHY_ONLY_WARMRESET AR_SM_BASE + 0x5d0
22152 +#define AR_PHY_ONLY_CTL AR_SM_BASE + 0x5d4
22153 +#define AR_PHY_ECO_CTRL AR_SM_BASE + 0x5dc
22154 +#define AR_PHY_BB_THERM_ADC_1 AR_SM_BASE + 0x248
22155 +
22156 +#define AR_PHY_65NM_CH0_SYNTH4 0x1608c
22157 +#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002
22158 +#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1
22159 +#define AR_PHY_65NM_CH0_SYNTH7 0x16098
22160 +#define AR_PHY_65NM_CH0_BIAS1 0x160c0
22161 +#define AR_PHY_65NM_CH0_BIAS2 0x160c4
22162 +#define AR_PHY_65NM_CH0_BIAS4 0x160cc
22163 +#define AR_PHY_65NM_CH0_RXTX4 0x1610c
22164 +#define AR_PHY_65NM_CH0_THERM 0x16290
22165 +
22166 +#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
22167 +#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
22168 +#define AR_PHY_65NM_CH0_THERM_START 0x20000000
22169 +#define AR_PHY_65NM_CH0_THERM_START_S 29
22170 +#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00
22171 +#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8
22172 +
22173 +#define AR_PHY_65NM_CH0_RXTX1 0x16100
22174 +#define AR_PHY_65NM_CH0_RXTX2 0x16104
22175 +#define AR_PHY_65NM_CH1_RXTX1 0x16500
22176 +#define AR_PHY_65NM_CH1_RXTX2 0x16504
22177 +#define AR_PHY_65NM_CH2_RXTX1 0x16900
22178 +#define AR_PHY_65NM_CH2_RXTX2 0x16904
22179 +
22180 +#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000
22181 +#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19
22182 +#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000
22183 +#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22
22184 +#define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000
22185 +#define AR_PHY_LNAGAIN_LONG_SHIFT_S 29
22186 +#define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000
22187 +#define AR_PHY_MXRGAIN_LONG_SHIFT_S 24
22188 +#define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000
22189 +#define AR_PHY_VGAGAIN_LONG_SHIFT_S 26
22190 +#define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001
22191 +#define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0
22192 +#define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002
22193 +#define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1
22194 +
22195 +/*
22196 + * SM Field Definitions
22197 + */
22198 +#define AR_PHY_CL_CAL_ENABLE 0x00000002
22199 +#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
22200 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
22201 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
22202 +
22203 +#define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
22204 +
22205 +#define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000
22206 +#define AR_PHY_FCAL20_CAP_STATUS_0_S 20
22207 +
22208 +#define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */
22209 +#define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */
22210 +#define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */
22211 +#define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */
22212 +#define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */
22213 +#define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
22214 +#define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
22215 +#define AR_PHY_GC_DYN2040_PRI_CH_S 4
22216 +#define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
22217 +#define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */
22218 +#define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
22219 +#define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
22220 +#define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
22221 +#define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */
22222 +#define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */
22223 +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
22224 +
22225 +#define AR_PHY_CALMODE_IQ 0x00000000
22226 +#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
22227 +#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
22228 +#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
22229 +#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
22230 +#define AR_PHY_MODE_OFDM 0x00000000
22231 +#define AR_PHY_MODE_CCK 0x00000001
22232 +#define AR_PHY_MODE_DYNAMIC 0x00000004
22233 +#define AR_PHY_MODE_DYNAMIC_S 2
22234 +#define AR_PHY_MODE_HALF 0x00000020
22235 +#define AR_PHY_MODE_QUARTER 0x00000040
22236 +#define AR_PHY_MAC_CLK_MODE 0x00000080
22237 +#define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
22238 +#define AR_PHY_MODE_SVD_HALF 0x00000200
22239 +#define AR_PHY_ACTIVE_EN 0x00000001
22240 +#define AR_PHY_ACTIVE_DIS 0x00000000
22241 +#define AR_PHY_FORCE_XPA_CFG 0x000000001
22242 +#define AR_PHY_FORCE_XPA_CFG_S 0
22243 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000
22244 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24
22245 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000
22246 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16
22247 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00
22248 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8
22249 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF
22250 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0
22251 +#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
22252 +#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
22253 +#define AR_PHY_TX_END_DATA_START 0x000000FF
22254 +#define AR_PHY_TX_END_DATA_START_S 0
22255 +#define AR_PHY_TX_END_PA_ON 0x0000FF00
22256 +#define AR_PHY_TX_END_PA_ON_S 8
22257 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
22258 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
22259 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
22260 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
22261 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
22262 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
22263 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
22264 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
22265 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
22266 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
22267 +#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
22268 +#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
22269 +#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
22270 +#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
22271 +#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
22272 +#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
22273 +#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
22274 +#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
22275 +#define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e
22276 +#define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
22277 +#define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001
22278 +#define AR_PHY_TXGAIN_FORCE 0x00000001
22279 +#define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00
22280 +#define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10
22281 +#define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000
22282 +#define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14
22283 +#define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000
22284 +#define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22
22285 +#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0
22286 +#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6
22287 +#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e
22288 +#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1
22289 +
22290 +#define AR_PHY_POWER_TX_RATE1 0x9934
22291 +#define AR_PHY_POWER_TX_RATE2 0x9938
22292 +#define AR_PHY_POWER_TX_RATE_MAX 0x993c
22293 +#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
22294 +#define PHY_AGC_CLR 0x10000000
22295 +#define RFSILENT_BB 0x00002000
22296 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF
22297 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800
22298 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
22299 +#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
22300 +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
22301 +#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
22302 +#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001
22303 +#define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0
22304 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002
22305 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1
22306 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0
22307 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
22308 +#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00
22309 +#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
22310 +#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000
22311 +#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
22312 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000
22313 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
22314 +#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
22315 +#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
22316 +#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18
22317 +#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
22318 +#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
22319 +
22320 +#define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
22321 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x00003fff
22322 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0
22323 +
22324 +#define AR_PHY_TPC_18_THERM_CAL_VALUE 0xff
22325 +#define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
22326 +#define AR_PHY_TPC_19_ALPHA_THERM 0xff
22327 +#define AR_PHY_TPC_19_ALPHA_THERM_S 0
22328 +
22329 +#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
22330 +#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
22331 +
22332 +#define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
22333 +#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
22334 +
22335 +/*
22336 + * Channel 1 Register Map
22337 + */
22338 +#define AR_CHAN1_BASE 0xa800
22339 +
22340 +#define AR_PHY_EXT_CCA_1 AR_CHAN1_BASE + 0x30
22341 +#define AR_PHY_TX_PHASE_RAMP_1 AR_CHAN1_BASE + 0xd0
22342 +#define AR_PHY_ADC_GAIN_DC_CORR_1 AR_CHAN1_BASE + 0xd4
22343 +
22344 +#define AR_PHY_SPUR_REPORT_1 AR_CHAN1_BASE + 0xa8
22345 +#define AR_PHY_CHAN_INFO_TAB_1 AR_CHAN1_BASE + 0x300
22346 +#define AR_PHY_RX_IQCAL_CORR_B1 AR_CHAN1_BASE + 0xdc
22347 +
22348 +/*
22349 + * Channel 1 Field Definitions
22350 + */
22351 +#define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
22352 +#define AR_PHY_CH1_EXT_MINCCA_PWR_S 16
22353 +
22354 +/*
22355 + * AGC 1 Register Map
22356 + */
22357 +#define AR_AGC1_BASE 0xae00
22358 +
22359 +#define AR_PHY_FORCEMAX_GAINS_1 AR_AGC1_BASE + 0x4
22360 +#define AR_PHY_EXT_ATTEN_CTL_1 AR_AGC1_BASE + 0x18
22361 +#define AR_PHY_CCA_1 AR_AGC1_BASE + 0x1c
22362 +#define AR_PHY_CCA_CTRL_1 AR_AGC1_BASE + 0x20
22363 +#define AR_PHY_RSSI_1 AR_AGC1_BASE + 0x180
22364 +#define AR_PHY_SPUR_CCK_REP_1 AR_AGC1_BASE + 0x184
22365 +#define AR_PHY_RX_OCGAIN_2 AR_AGC1_BASE + 0x200
22366 +
22367 +/*
22368 + * AGC 1 Field Definitions
22369 + */
22370 +#define AR_PHY_CH1_MINCCA_PWR 0x1FF00000
22371 +#define AR_PHY_CH1_MINCCA_PWR_S 20
22372 +
22373 +/*
22374 + * SM 1 Register Map
22375 + */
22376 +#define AR_SM1_BASE 0xb200
22377 +
22378 +#define AR_PHY_SWITCH_CHAIN_1 AR_SM1_BASE + 0x84
22379 +#define AR_PHY_FCAL_2_1 AR_SM1_BASE + 0xd0
22380 +#define AR_PHY_DFT_TONE_CTL_1 AR_SM1_BASE + 0xd4
22381 +#define AR_PHY_CL_TAB_1 AR_SM1_BASE + 0x100
22382 +#define AR_PHY_CHAN_INFO_GAIN_1 AR_SM1_BASE + 0x180
22383 +#define AR_PHY_TPC_4_B1 AR_SM1_BASE + 0x204
22384 +#define AR_PHY_TPC_5_B1 AR_SM1_BASE + 0x208
22385 +#define AR_PHY_TPC_6_B1 AR_SM1_BASE + 0x20c
22386 +#define AR_PHY_TPC_11_B1 AR_SM1_BASE + 0x220
22387 +#define AR_PHY_PDADC_TAB_1 AR_SM1_BASE + 0x240
22388 +#define AR_PHY_TX_IQCAL_STATUS_B1 AR_SM1_BASE + 0x48c
22389 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1 AR_SM1_BASE + 0x450
22390 +
22391 +/*
22392 + * Channel 2 Register Map
22393 + */
22394 +#define AR_CHAN2_BASE 0xb800
22395 +
22396 +#define AR_PHY_EXT_CCA_2 AR_CHAN2_BASE + 0x30
22397 +#define AR_PHY_TX_PHASE_RAMP_2 AR_CHAN2_BASE + 0xd0
22398 +#define AR_PHY_ADC_GAIN_DC_CORR_2 AR_CHAN2_BASE + 0xd4
22399 +
22400 +#define AR_PHY_SPUR_REPORT_2 AR_CHAN2_BASE + 0xa8
22401 +#define AR_PHY_CHAN_INFO_TAB_2 AR_CHAN2_BASE + 0x300
22402 +#define AR_PHY_RX_IQCAL_CORR_B2 AR_CHAN2_BASE + 0xdc
22403 +
22404 +/*
22405 + * Channel 2 Field Definitions
22406 + */
22407 +#define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000
22408 +#define AR_PHY_CH2_EXT_MINCCA_PWR_S 16
22409 +/*
22410 + * AGC 2 Register Map
22411 + */
22412 +#define AR_AGC2_BASE 0xbe00
22413 +
22414 +#define AR_PHY_FORCEMAX_GAINS_2 AR_AGC2_BASE + 0x4
22415 +#define AR_PHY_EXT_ATTEN_CTL_2 AR_AGC2_BASE + 0x18
22416 +#define AR_PHY_CCA_2 AR_AGC2_BASE + 0x1c
22417 +#define AR_PHY_CCA_CTRL_2 AR_AGC2_BASE + 0x20
22418 +#define AR_PHY_RSSI_2 AR_AGC2_BASE + 0x180
22419 +
22420 +/*
22421 + * AGC 2 Field Definitions
22422 + */
22423 +#define AR_PHY_CH2_MINCCA_PWR 0x1FF00000
22424 +#define AR_PHY_CH2_MINCCA_PWR_S 20
22425 +
22426 +/*
22427 + * SM 2 Register Map
22428 + */
22429 +#define AR_SM2_BASE 0xc200
22430 +
22431 +#define AR_PHY_SWITCH_CHAIN_2 AR_SM2_BASE + 0x84
22432 +#define AR_PHY_FCAL_2_2 AR_SM2_BASE + 0xd0
22433 +#define AR_PHY_DFT_TONE_CTL_2 AR_SM2_BASE + 0xd4
22434 +#define AR_PHY_CL_TAB_2 AR_SM2_BASE + 0x100
22435 +#define AR_PHY_CHAN_INFO_GAIN_2 AR_SM2_BASE + 0x180
22436 +#define AR_PHY_TPC_4_B2 AR_SM2_BASE + 0x204
22437 +#define AR_PHY_TPC_5_B2 AR_SM2_BASE + 0x208
22438 +#define AR_PHY_TPC_6_B2 AR_SM2_BASE + 0x20c
22439 +#define AR_PHY_TPC_11_B2 AR_SM2_BASE + 0x220
22440 +#define AR_PHY_PDADC_TAB_2 AR_SM2_BASE + 0x240
22441 +#define AR_PHY_TX_IQCAL_STATUS_B2 AR_SM2_BASE + 0x48c
22442 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2 AR_SM2_BASE + 0x450
22443 +
22444 +#define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001
22445 +
22446 +/*
22447 + * AGC 3 Register Map
22448 + */
22449 +#define AR_AGC3_BASE 0xce00
22450 +
22451 +#define AR_PHY_RSSI_3 AR_AGC3_BASE + 0x180
22452 +
22453 +/*
22454 + * Misc helper defines
22455 + */
22456 +#define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE)
22457 +
22458 +#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22459 +#define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
22460 +#define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22461 +#define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22462 +
22463 +#define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22464 +#define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22465 +#define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22466 +
22467 +#define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22468 +#define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22469 +#define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22470 +#define AR_PHY_CAL_MEAS_3(_i) (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22471 +#define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
22472 +#define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
22473 +#define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
22474 +#define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
22475 +
22476 +#define AR_PHY_BB_PANIC_NON_IDLE_ENABLE 0x00000001
22477 +#define AR_PHY_BB_PANIC_IDLE_ENABLE 0x00000002
22478 +#define AR_PHY_BB_PANIC_IDLE_MASK 0xFFFF0000
22479 +#define AR_PHY_BB_PANIC_NON_IDLE_MASK 0x0000FFFC
22480 +
22481 +#define AR_PHY_BB_PANIC_RST_ENABLE 0x00000002
22482 +#define AR_PHY_BB_PANIC_IRQ_ENABLE 0x00000004
22483 +#define AR_PHY_BB_PANIC_CNTL2_MASK 0xFFFFFFF9
22484 +
22485 +#define AR_PHY_BB_WD_STATUS 0x00000007
22486 +#define AR_PHY_BB_WD_STATUS_S 0
22487 +#define AR_PHY_BB_WD_DET_HANG 0x00000008
22488 +#define AR_PHY_BB_WD_DET_HANG_S 3
22489 +#define AR_PHY_BB_WD_RADAR_SM 0x000000F0
22490 +#define AR_PHY_BB_WD_RADAR_SM_S 4
22491 +#define AR_PHY_BB_WD_RX_OFDM_SM 0x00000F00
22492 +#define AR_PHY_BB_WD_RX_OFDM_SM_S 8
22493 +#define AR_PHY_BB_WD_RX_CCK_SM 0x0000F000
22494 +#define AR_PHY_BB_WD_RX_CCK_SM_S 12
22495 +#define AR_PHY_BB_WD_TX_OFDM_SM 0x000F0000
22496 +#define AR_PHY_BB_WD_TX_OFDM_SM_S 16
22497 +#define AR_PHY_BB_WD_TX_CCK_SM 0x00F00000
22498 +#define AR_PHY_BB_WD_TX_CCK_SM_S 20
22499 +#define AR_PHY_BB_WD_AGC_SM 0x0F000000
22500 +#define AR_PHY_BB_WD_AGC_SM_S 24
22501 +#define AR_PHY_BB_WD_SRCH_SM 0xF0000000
22502 +#define AR_PHY_BB_WD_SRCH_SM_S 28
22503 +
22504 +#define AR_PHY_BB_WD_STATUS_CLR 0x00000008
22505 +
22506 +void ar9003_hw_modify_chain_masks(struct ath_hw *ah,
22507 + u8 rx_chainmask,
22508 + u8 tx_chainmask);
22509 +
22510 +#endif /* AR9003_PHY_H */
22511 diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
22512 index bdcd257..fbb7dec 100644
22513 --- a/drivers/net/wireless/ath/ath9k/ath9k.h
22514 +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
22515 @@ -114,8 +114,10 @@ enum buffer_type {
22516 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
22517 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
22518
22519 +#define ATH_TXSTATUS_RING_SIZE 64
22520 +
22521 struct ath_descdma {
22522 - struct ath_desc *dd_desc;
22523 + void *dd_desc;
22524 dma_addr_t dd_desc_paddr;
22525 u32 dd_desc_len;
22526 struct ath_buf *dd_bufptr;
22527 @@ -123,7 +125,7 @@ struct ath_descdma {
22528
22529 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
22530 struct list_head *head, const char *name,
22531 - int nbuf, int ndesc);
22532 + int nbuf, int ndesc, bool is_tx);
22533 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
22534 struct list_head *head);
22535
22536 @@ -188,6 +190,7 @@ enum ATH_AGGR_STATUS {
22537 ATH_AGGR_LIMITED,
22538 };
22539
22540 +#define ATH_TXFIFO_DEPTH 8
22541 struct ath_txq {
22542 u32 axq_qnum;
22543 u32 *axq_link;
22544 @@ -197,6 +200,10 @@ struct ath_txq {
22545 bool stopped;
22546 bool axq_tx_inprogress;
22547 struct list_head axq_acq;
22548 + struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
22549 + struct list_head txq_fifo_pending;
22550 + u8 txq_headidx;
22551 + u8 txq_tailidx;
22552 };
22553
22554 #define AGGR_CLEANUP BIT(1)
22555 @@ -223,6 +230,12 @@ struct ath_tx {
22556 struct ath_descdma txdma;
22557 };
22558
22559 +struct ath_rx_edma {
22560 + struct sk_buff_head rx_fifo;
22561 + struct sk_buff_head rx_buffers;
22562 + u32 rx_fifo_hwsize;
22563 +};
22564 +
22565 struct ath_rx {
22566 u8 defant;
22567 u8 rxotherant;
22568 @@ -232,6 +245,8 @@ struct ath_rx {
22569 spinlock_t rxbuflock;
22570 struct list_head rxbuf;
22571 struct ath_descdma rxdma;
22572 + struct ath_buf *rx_bufptr;
22573 + struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
22574 };
22575
22576 int ath_startrecv(struct ath_softc *sc);
22577 @@ -240,7 +255,7 @@ void ath_flushrecv(struct ath_softc *sc);
22578 u32 ath_calcrxfilter(struct ath_softc *sc);
22579 int ath_rx_init(struct ath_softc *sc, int nbufs);
22580 void ath_rx_cleanup(struct ath_softc *sc);
22581 -int ath_rx_tasklet(struct ath_softc *sc, int flush);
22582 +int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
22583 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
22584 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
22585 int ath_tx_setup(struct ath_softc *sc, int haltype);
22586 @@ -258,6 +273,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
22587 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
22588 struct ath_tx_control *txctl);
22589 void ath_tx_tasklet(struct ath_softc *sc);
22590 +void ath_tx_edma_tasklet(struct ath_softc *sc);
22591 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
22592 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
22593 void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
22594 @@ -507,6 +523,8 @@ struct ath_softc {
22595 struct ath_beacon_config cur_beacon_conf;
22596 struct delayed_work tx_complete_work;
22597 struct ath_btcoex btcoex;
22598 +
22599 + struct ath_descdma txsdma;
22600 };
22601
22602 struct ath_wiphy {
22603 diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
22604 index 22375a7..c8a4558 100644
22605 --- a/drivers/net/wireless/ath/ath9k/beacon.c
22606 +++ b/drivers/net/wireless/ath/ath9k/beacon.c
22607 @@ -93,8 +93,6 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
22608 antenna = ((sc->beacon.ast_be_xmit / sc->nbcnvifs) & 1 ? 2 : 1);
22609 }
22610
22611 - ds->ds_data = bf->bf_buf_addr;
22612 -
22613 sband = &sc->sbands[common->hw->conf.channel->band];
22614 rate = sband->bitrates[rateidx].hw_value;
22615 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
22616 @@ -109,7 +107,8 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
22617
22618 /* NB: beacon's BufLen must be a multiple of 4 bytes */
22619 ath9k_hw_filltxdesc(ah, ds, roundup(skb->len, 4),
22620 - true, true, ds);
22621 + true, true, ds, bf->bf_buf_addr,
22622 + sc->beacon.beaconq);
22623
22624 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
22625 series[0].Tries = 1;
22626 diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
22627 index 064f5b5..6982577 100644
22628 --- a/drivers/net/wireless/ath/ath9k/calib.c
22629 +++ b/drivers/net/wireless/ath/ath9k/calib.c
22630 @@ -15,10 +15,12 @@
22631 */
22632
22633 #include "hw.h"
22634 +#include "hw-ops.h"
22635 +
22636 +/* Common calibration code */
22637
22638 /* We can tune this as we go by monitoring really low values */
22639 #define ATH9K_NF_TOO_LOW -60
22640 -#define AR9285_CLCAL_REDO_THRESH 1
22641
22642 /* AR5416 may return very high value (like -31 dBm), in those cases the nf
22643 * is incorrect and we should use the static NF value. Later we can try to
22644 @@ -87,98 +89,9 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
22645 return;
22646 }
22647
22648 -static void ath9k_hw_do_getnf(struct ath_hw *ah,
22649 - int16_t nfarray[NUM_NF_READINGS])
22650 -{
22651 - struct ath_common *common = ath9k_hw_common(ah);
22652 - int16_t nf;
22653 -
22654 - if (AR_SREV_9280_10_OR_LATER(ah))
22655 - nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
22656 - else
22657 - nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
22658 -
22659 - if (nf & 0x100)
22660 - nf = 0 - ((nf ^ 0x1ff) + 1);
22661 - ath_print(common, ATH_DBG_CALIBRATE,
22662 - "NF calibrated [ctl] [chain 0] is %d\n", nf);
22663 -
22664 - if (AR_SREV_9271(ah) && (nf >= -114))
22665 - nf = -116;
22666 -
22667 - nfarray[0] = nf;
22668 -
22669 - if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
22670 - if (AR_SREV_9280_10_OR_LATER(ah))
22671 - nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
22672 - AR9280_PHY_CH1_MINCCA_PWR);
22673 - else
22674 - nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
22675 - AR_PHY_CH1_MINCCA_PWR);
22676 -
22677 - if (nf & 0x100)
22678 - nf = 0 - ((nf ^ 0x1ff) + 1);
22679 - ath_print(common, ATH_DBG_CALIBRATE,
22680 - "NF calibrated [ctl] [chain 1] is %d\n", nf);
22681 - nfarray[1] = nf;
22682 -
22683 - if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
22684 - nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
22685 - AR_PHY_CH2_MINCCA_PWR);
22686 - if (nf & 0x100)
22687 - nf = 0 - ((nf ^ 0x1ff) + 1);
22688 - ath_print(common, ATH_DBG_CALIBRATE,
22689 - "NF calibrated [ctl] [chain 2] is %d\n", nf);
22690 - nfarray[2] = nf;
22691 - }
22692 - }
22693 -
22694 - if (AR_SREV_9280_10_OR_LATER(ah))
22695 - nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
22696 - AR9280_PHY_EXT_MINCCA_PWR);
22697 - else
22698 - nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
22699 - AR_PHY_EXT_MINCCA_PWR);
22700 -
22701 - if (nf & 0x100)
22702 - nf = 0 - ((nf ^ 0x1ff) + 1);
22703 - ath_print(common, ATH_DBG_CALIBRATE,
22704 - "NF calibrated [ext] [chain 0] is %d\n", nf);
22705 -
22706 - if (AR_SREV_9271(ah) && (nf >= -114))
22707 - nf = -116;
22708 -
22709 - nfarray[3] = nf;
22710 -
22711 - if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
22712 - if (AR_SREV_9280_10_OR_LATER(ah))
22713 - nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
22714 - AR9280_PHY_CH1_EXT_MINCCA_PWR);
22715 - else
22716 - nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
22717 - AR_PHY_CH1_EXT_MINCCA_PWR);
22718 -
22719 - if (nf & 0x100)
22720 - nf = 0 - ((nf ^ 0x1ff) + 1);
22721 - ath_print(common, ATH_DBG_CALIBRATE,
22722 - "NF calibrated [ext] [chain 1] is %d\n", nf);
22723 - nfarray[4] = nf;
22724 -
22725 - if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
22726 - nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
22727 - AR_PHY_CH2_EXT_MINCCA_PWR);
22728 - if (nf & 0x100)
22729 - nf = 0 - ((nf ^ 0x1ff) + 1);
22730 - ath_print(common, ATH_DBG_CALIBRATE,
22731 - "NF calibrated [ext] [chain 2] is %d\n", nf);
22732 - nfarray[5] = nf;
22733 - }
22734 - }
22735 -}
22736 -
22737 -static bool getNoiseFloorThresh(struct ath_hw *ah,
22738 - enum ieee80211_band band,
22739 - int16_t *nft)
22740 +static bool ath9k_hw_get_nf_thresh(struct ath_hw *ah,
22741 + enum ieee80211_band band,
22742 + int16_t *nft)
22743 {
22744 switch (band) {
22745 case IEEE80211_BAND_5GHZ:
22746 @@ -195,44 +108,8 @@ static bool getNoiseFloorThresh(struct ath_hw *ah,
22747 return true;
22748 }
22749
22750 -static void ath9k_hw_setup_calibration(struct ath_hw *ah,
22751 - struct ath9k_cal_list *currCal)
22752 -{
22753 - struct ath_common *common = ath9k_hw_common(ah);
22754 -
22755 - REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
22756 - AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
22757 - currCal->calData->calCountMax);
22758 -
22759 - switch (currCal->calData->calType) {
22760 - case IQ_MISMATCH_CAL:
22761 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
22762 - ath_print(common, ATH_DBG_CALIBRATE,
22763 - "starting IQ Mismatch Calibration\n");
22764 - break;
22765 - case ADC_GAIN_CAL:
22766 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
22767 - ath_print(common, ATH_DBG_CALIBRATE,
22768 - "starting ADC Gain Calibration\n");
22769 - break;
22770 - case ADC_DC_CAL:
22771 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
22772 - ath_print(common, ATH_DBG_CALIBRATE,
22773 - "starting ADC DC Calibration\n");
22774 - break;
22775 - case ADC_DC_INIT_CAL:
22776 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
22777 - ath_print(common, ATH_DBG_CALIBRATE,
22778 - "starting Init ADC DC Calibration\n");
22779 - break;
22780 - }
22781 -
22782 - REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
22783 - AR_PHY_TIMING_CTRL4_DO_CAL);
22784 -}
22785 -
22786 -static void ath9k_hw_reset_calibration(struct ath_hw *ah,
22787 - struct ath9k_cal_list *currCal)
22788 +void ath9k_hw_reset_calibration(struct ath_hw *ah,
22789 + struct ath9k_cal_list *currCal)
22790 {
22791 int i;
22792
22793 @@ -250,324 +127,6 @@ static void ath9k_hw_reset_calibration(struct ath_hw *ah,
22794 ah->cal_samples = 0;
22795 }
22796
22797 -static bool ath9k_hw_per_calibration(struct ath_hw *ah,
22798 - struct ath9k_channel *ichan,
22799 - u8 rxchainmask,
22800 - struct ath9k_cal_list *currCal)
22801 -{
22802 - bool iscaldone = false;
22803 -
22804 - if (currCal->calState == CAL_RUNNING) {
22805 - if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
22806 - AR_PHY_TIMING_CTRL4_DO_CAL)) {
22807 -
22808 - currCal->calData->calCollect(ah);
22809 - ah->cal_samples++;
22810 -
22811 - if (ah->cal_samples >= currCal->calData->calNumSamples) {
22812 - int i, numChains = 0;
22813 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
22814 - if (rxchainmask & (1 << i))
22815 - numChains++;
22816 - }
22817 -
22818 - currCal->calData->calPostProc(ah, numChains);
22819 - ichan->CalValid |= currCal->calData->calType;
22820 - currCal->calState = CAL_DONE;
22821 - iscaldone = true;
22822 - } else {
22823 - ath9k_hw_setup_calibration(ah, currCal);
22824 - }
22825 - }
22826 - } else if (!(ichan->CalValid & currCal->calData->calType)) {
22827 - ath9k_hw_reset_calibration(ah, currCal);
22828 - }
22829 -
22830 - return iscaldone;
22831 -}
22832 -
22833 -/* Assumes you are talking about the currently configured channel */
22834 -static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
22835 - enum ath9k_cal_types calType)
22836 -{
22837 - struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
22838 -
22839 - switch (calType & ah->supp_cals) {
22840 - case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
22841 - return true;
22842 - case ADC_GAIN_CAL:
22843 - case ADC_DC_CAL:
22844 - if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
22845 - conf_is_ht20(conf)))
22846 - return true;
22847 - break;
22848 - }
22849 - return false;
22850 -}
22851 -
22852 -static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
22853 -{
22854 - int i;
22855 -
22856 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
22857 - ah->totalPowerMeasI[i] +=
22858 - REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
22859 - ah->totalPowerMeasQ[i] +=
22860 - REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
22861 - ah->totalIqCorrMeas[i] +=
22862 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
22863 - ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
22864 - "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
22865 - ah->cal_samples, i, ah->totalPowerMeasI[i],
22866 - ah->totalPowerMeasQ[i],
22867 - ah->totalIqCorrMeas[i]);
22868 - }
22869 -}
22870 -
22871 -static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
22872 -{
22873 - int i;
22874 -
22875 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
22876 - ah->totalAdcIOddPhase[i] +=
22877 - REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
22878 - ah->totalAdcIEvenPhase[i] +=
22879 - REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
22880 - ah->totalAdcQOddPhase[i] +=
22881 - REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
22882 - ah->totalAdcQEvenPhase[i] +=
22883 - REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
22884 -
22885 - ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
22886 - "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
22887 - "oddq=0x%08x; evenq=0x%08x;\n",
22888 - ah->cal_samples, i,
22889 - ah->totalAdcIOddPhase[i],
22890 - ah->totalAdcIEvenPhase[i],
22891 - ah->totalAdcQOddPhase[i],
22892 - ah->totalAdcQEvenPhase[i]);
22893 - }
22894 -}
22895 -
22896 -static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
22897 -{
22898 - int i;
22899 -
22900 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
22901 - ah->totalAdcDcOffsetIOddPhase[i] +=
22902 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
22903 - ah->totalAdcDcOffsetIEvenPhase[i] +=
22904 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
22905 - ah->totalAdcDcOffsetQOddPhase[i] +=
22906 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
22907 - ah->totalAdcDcOffsetQEvenPhase[i] +=
22908 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
22909 -
22910 - ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
22911 - "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
22912 - "oddq=0x%08x; evenq=0x%08x;\n",
22913 - ah->cal_samples, i,
22914 - ah->totalAdcDcOffsetIOddPhase[i],
22915 - ah->totalAdcDcOffsetIEvenPhase[i],
22916 - ah->totalAdcDcOffsetQOddPhase[i],
22917 - ah->totalAdcDcOffsetQEvenPhase[i]);
22918 - }
22919 -}
22920 -
22921 -static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
22922 -{
22923 - struct ath_common *common = ath9k_hw_common(ah);
22924 - u32 powerMeasQ, powerMeasI, iqCorrMeas;
22925 - u32 qCoffDenom, iCoffDenom;
22926 - int32_t qCoff, iCoff;
22927 - int iqCorrNeg, i;
22928 -
22929 - for (i = 0; i < numChains; i++) {
22930 - powerMeasI = ah->totalPowerMeasI[i];
22931 - powerMeasQ = ah->totalPowerMeasQ[i];
22932 - iqCorrMeas = ah->totalIqCorrMeas[i];
22933 -
22934 - ath_print(common, ATH_DBG_CALIBRATE,
22935 - "Starting IQ Cal and Correction for Chain %d\n",
22936 - i);
22937 -
22938 - ath_print(common, ATH_DBG_CALIBRATE,
22939 - "Orignal: Chn %diq_corr_meas = 0x%08x\n",
22940 - i, ah->totalIqCorrMeas[i]);
22941 -
22942 - iqCorrNeg = 0;
22943 -
22944 - if (iqCorrMeas > 0x80000000) {
22945 - iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
22946 - iqCorrNeg = 1;
22947 - }
22948 -
22949 - ath_print(common, ATH_DBG_CALIBRATE,
22950 - "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
22951 - ath_print(common, ATH_DBG_CALIBRATE,
22952 - "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
22953 - ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
22954 - iqCorrNeg);
22955 -
22956 - iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
22957 - qCoffDenom = powerMeasQ / 64;
22958 -
22959 - if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
22960 - (qCoffDenom != 0)) {
22961 - iCoff = iqCorrMeas / iCoffDenom;
22962 - qCoff = powerMeasI / qCoffDenom - 64;
22963 - ath_print(common, ATH_DBG_CALIBRATE,
22964 - "Chn %d iCoff = 0x%08x\n", i, iCoff);
22965 - ath_print(common, ATH_DBG_CALIBRATE,
22966 - "Chn %d qCoff = 0x%08x\n", i, qCoff);
22967 -
22968 - iCoff = iCoff & 0x3f;
22969 - ath_print(common, ATH_DBG_CALIBRATE,
22970 - "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
22971 - if (iqCorrNeg == 0x0)
22972 - iCoff = 0x40 - iCoff;
22973 -
22974 - if (qCoff > 15)
22975 - qCoff = 15;
22976 - else if (qCoff <= -16)
22977 - qCoff = 16;
22978 -
22979 - ath_print(common, ATH_DBG_CALIBRATE,
22980 - "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
22981 - i, iCoff, qCoff);
22982 -
22983 - REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
22984 - AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
22985 - iCoff);
22986 - REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
22987 - AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
22988 - qCoff);
22989 - ath_print(common, ATH_DBG_CALIBRATE,
22990 - "IQ Cal and Correction done for Chain %d\n",
22991 - i);
22992 - }
22993 - }
22994 -
22995 - REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
22996 - AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
22997 -}
22998 -
22999 -static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
23000 -{
23001 - struct ath_common *common = ath9k_hw_common(ah);
23002 - u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
23003 - u32 qGainMismatch, iGainMismatch, val, i;
23004 -
23005 - for (i = 0; i < numChains; i++) {
23006 - iOddMeasOffset = ah->totalAdcIOddPhase[i];
23007 - iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
23008 - qOddMeasOffset = ah->totalAdcQOddPhase[i];
23009 - qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
23010 -
23011 - ath_print(common, ATH_DBG_CALIBRATE,
23012 - "Starting ADC Gain Cal for Chain %d\n", i);
23013 -
23014 - ath_print(common, ATH_DBG_CALIBRATE,
23015 - "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
23016 - iOddMeasOffset);
23017 - ath_print(common, ATH_DBG_CALIBRATE,
23018 - "Chn %d pwr_meas_even_i = 0x%08x\n", i,
23019 - iEvenMeasOffset);
23020 - ath_print(common, ATH_DBG_CALIBRATE,
23021 - "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
23022 - qOddMeasOffset);
23023 - ath_print(common, ATH_DBG_CALIBRATE,
23024 - "Chn %d pwr_meas_even_q = 0x%08x\n", i,
23025 - qEvenMeasOffset);
23026 -
23027 - if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
23028 - iGainMismatch =
23029 - ((iEvenMeasOffset * 32) /
23030 - iOddMeasOffset) & 0x3f;
23031 - qGainMismatch =
23032 - ((qOddMeasOffset * 32) /
23033 - qEvenMeasOffset) & 0x3f;
23034 -
23035 - ath_print(common, ATH_DBG_CALIBRATE,
23036 - "Chn %d gain_mismatch_i = 0x%08x\n", i,
23037 - iGainMismatch);
23038 - ath_print(common, ATH_DBG_CALIBRATE,
23039 - "Chn %d gain_mismatch_q = 0x%08x\n", i,
23040 - qGainMismatch);
23041 -
23042 - val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
23043 - val &= 0xfffff000;
23044 - val |= (qGainMismatch) | (iGainMismatch << 6);
23045 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
23046 -
23047 - ath_print(common, ATH_DBG_CALIBRATE,
23048 - "ADC Gain Cal done for Chain %d\n", i);
23049 - }
23050 - }
23051 -
23052 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
23053 - REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
23054 - AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
23055 -}
23056 -
23057 -static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
23058 -{
23059 - struct ath_common *common = ath9k_hw_common(ah);
23060 - u32 iOddMeasOffset, iEvenMeasOffset, val, i;
23061 - int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
23062 - const struct ath9k_percal_data *calData =
23063 - ah->cal_list_curr->calData;
23064 - u32 numSamples =
23065 - (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
23066 -
23067 - for (i = 0; i < numChains; i++) {
23068 - iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
23069 - iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
23070 - qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
23071 - qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
23072 -
23073 - ath_print(common, ATH_DBG_CALIBRATE,
23074 - "Starting ADC DC Offset Cal for Chain %d\n", i);
23075 -
23076 - ath_print(common, ATH_DBG_CALIBRATE,
23077 - "Chn %d pwr_meas_odd_i = %d\n", i,
23078 - iOddMeasOffset);
23079 - ath_print(common, ATH_DBG_CALIBRATE,
23080 - "Chn %d pwr_meas_even_i = %d\n", i,
23081 - iEvenMeasOffset);
23082 - ath_print(common, ATH_DBG_CALIBRATE,
23083 - "Chn %d pwr_meas_odd_q = %d\n", i,
23084 - qOddMeasOffset);
23085 - ath_print(common, ATH_DBG_CALIBRATE,
23086 - "Chn %d pwr_meas_even_q = %d\n", i,
23087 - qEvenMeasOffset);
23088 -
23089 - iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
23090 - numSamples) & 0x1ff;
23091 - qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
23092 - numSamples) & 0x1ff;
23093 -
23094 - ath_print(common, ATH_DBG_CALIBRATE,
23095 - "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
23096 - iDcMismatch);
23097 - ath_print(common, ATH_DBG_CALIBRATE,
23098 - "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
23099 - qDcMismatch);
23100 -
23101 - val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
23102 - val &= 0xc0000fff;
23103 - val |= (qDcMismatch << 12) | (iDcMismatch << 21);
23104 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
23105 -
23106 - ath_print(common, ATH_DBG_CALIBRATE,
23107 - "ADC DC Offset Cal done for Chain %d\n", i);
23108 - }
23109 -
23110 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
23111 - REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
23112 - AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
23113 -}
23114 -
23115 /* This is done for the currently configured channel */
23116 bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
23117 {
23118 @@ -614,72 +173,6 @@ void ath9k_hw_start_nfcal(struct ath_hw *ah)
23119 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
23120 }
23121
23122 -void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
23123 -{
23124 - struct ath9k_nfcal_hist *h;
23125 - int i, j;
23126 - int32_t val;
23127 - const u32 ar5416_cca_regs[6] = {
23128 - AR_PHY_CCA,
23129 - AR_PHY_CH1_CCA,
23130 - AR_PHY_CH2_CCA,
23131 - AR_PHY_EXT_CCA,
23132 - AR_PHY_CH1_EXT_CCA,
23133 - AR_PHY_CH2_EXT_CCA
23134 - };
23135 - u8 chainmask, rx_chain_status;
23136 -
23137 - rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
23138 - if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
23139 - chainmask = 0x9;
23140 - else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
23141 - if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
23142 - chainmask = 0x1B;
23143 - else
23144 - chainmask = 0x09;
23145 - } else {
23146 - if (rx_chain_status & 0x4)
23147 - chainmask = 0x3F;
23148 - else if (rx_chain_status & 0x2)
23149 - chainmask = 0x1B;
23150 - else
23151 - chainmask = 0x09;
23152 - }
23153 -
23154 - h = ah->nfCalHist;
23155 -
23156 - for (i = 0; i < NUM_NF_READINGS; i++) {
23157 - if (chainmask & (1 << i)) {
23158 - val = REG_READ(ah, ar5416_cca_regs[i]);
23159 - val &= 0xFFFFFE00;
23160 - val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
23161 - REG_WRITE(ah, ar5416_cca_regs[i], val);
23162 - }
23163 - }
23164 -
23165 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
23166 - AR_PHY_AGC_CONTROL_ENABLE_NF);
23167 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
23168 - AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
23169 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
23170 -
23171 - for (j = 0; j < 5; j++) {
23172 - if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
23173 - AR_PHY_AGC_CONTROL_NF) == 0)
23174 - break;
23175 - udelay(50);
23176 - }
23177 -
23178 - for (i = 0; i < NUM_NF_READINGS; i++) {
23179 - if (chainmask & (1 << i)) {
23180 - val = REG_READ(ah, ar5416_cca_regs[i]);
23181 - val &= 0xFFFFFE00;
23182 - val |= (((u32) (-50) << 1) & 0x1ff);
23183 - REG_WRITE(ah, ar5416_cca_regs[i], val);
23184 - }
23185 - }
23186 -}
23187 -
23188 int16_t ath9k_hw_getnf(struct ath_hw *ah,
23189 struct ath9k_channel *chan)
23190 {
23191 @@ -699,7 +192,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
23192 } else {
23193 ath9k_hw_do_getnf(ah, nfarray);
23194 nf = nfarray[0];
23195 - if (getNoiseFloorThresh(ah, c->band, &nfThresh)
23196 + if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
23197 && nf > nfThresh) {
23198 ath_print(common, ATH_DBG_CALIBRATE,
23199 "noise floor failed detected; "
23200 @@ -757,567 +250,3 @@ s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
23201 return nf;
23202 }
23203 EXPORT_SYMBOL(ath9k_hw_getchan_noise);
23204 -
23205 -static void ath9k_olc_temp_compensation_9287(struct ath_hw *ah)
23206 -{
23207 - u32 rddata;
23208 - int32_t delta, currPDADC, slope;
23209 -
23210 - rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
23211 - currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
23212 -
23213 - if (ah->initPDADC == 0 || currPDADC == 0) {
23214 - /*
23215 - * Zero value indicates that no frames have been transmitted yet,
23216 - * can't do temperature compensation until frames are transmitted.
23217 - */
23218 - return;
23219 - } else {
23220 - slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
23221 -
23222 - if (slope == 0) { /* to avoid divide by zero case */
23223 - delta = 0;
23224 - } else {
23225 - delta = ((currPDADC - ah->initPDADC)*4) / slope;
23226 - }
23227 - REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
23228 - AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
23229 - REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
23230 - AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
23231 - }
23232 -}
23233 -
23234 -static void ath9k_olc_temp_compensation(struct ath_hw *ah)
23235 -{
23236 - u32 rddata, i;
23237 - int delta, currPDADC, regval;
23238 -
23239 - if (OLC_FOR_AR9287_10_LATER) {
23240 - ath9k_olc_temp_compensation_9287(ah);
23241 - } else {
23242 - rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
23243 - currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
23244 -
23245 - if (ah->initPDADC == 0 || currPDADC == 0) {
23246 - return;
23247 - } else {
23248 - if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
23249 - delta = (currPDADC - ah->initPDADC + 4) / 8;
23250 - else
23251 - delta = (currPDADC - ah->initPDADC + 5) / 10;
23252 -
23253 - if (delta != ah->PDADCdelta) {
23254 - ah->PDADCdelta = delta;
23255 - for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
23256 - regval = ah->originalGain[i] - delta;
23257 - if (regval < 0)
23258 - regval = 0;
23259 -
23260 - REG_RMW_FIELD(ah,
23261 - AR_PHY_TX_GAIN_TBL1 + i * 4,
23262 - AR_PHY_TX_GAIN, regval);
23263 - }
23264 - }
23265 - }
23266 - }
23267 -}
23268 -
23269 -static void ath9k_hw_9271_pa_cal(struct ath_hw *ah, bool is_reset)
23270 -{
23271 - u32 regVal;
23272 - unsigned int i;
23273 - u32 regList [][2] = {
23274 - { 0x786c, 0 },
23275 - { 0x7854, 0 },
23276 - { 0x7820, 0 },
23277 - { 0x7824, 0 },
23278 - { 0x7868, 0 },
23279 - { 0x783c, 0 },
23280 - { 0x7838, 0 } ,
23281 - { 0x7828, 0 } ,
23282 - };
23283 -
23284 - for (i = 0; i < ARRAY_SIZE(regList); i++)
23285 - regList[i][1] = REG_READ(ah, regList[i][0]);
23286 -
23287 - regVal = REG_READ(ah, 0x7834);
23288 - regVal &= (~(0x1));
23289 - REG_WRITE(ah, 0x7834, regVal);
23290 - regVal = REG_READ(ah, 0x9808);
23291 - regVal |= (0x1 << 27);
23292 - REG_WRITE(ah, 0x9808, regVal);
23293 -
23294 - /* 786c,b23,1, pwddac=1 */
23295 - REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
23296 - /* 7854, b5,1, pdrxtxbb=1 */
23297 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
23298 - /* 7854, b7,1, pdv2i=1 */
23299 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
23300 - /* 7854, b8,1, pddacinterface=1 */
23301 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
23302 - /* 7824,b12,0, offcal=0 */
23303 - REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
23304 - /* 7838, b1,0, pwddb=0 */
23305 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
23306 - /* 7820,b11,0, enpacal=0 */
23307 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
23308 - /* 7820,b25,1, pdpadrv1=0 */
23309 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
23310 - /* 7820,b24,0, pdpadrv2=0 */
23311 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0);
23312 - /* 7820,b23,0, pdpaout=0 */
23313 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
23314 - /* 783c,b14-16,7, padrvgn2tab_0=7 */
23315 - REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
23316 - /*
23317 - * 7838,b29-31,0, padrvgn1tab_0=0
23318 - * does not matter since we turn it off
23319 - */
23320 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
23321 -
23322 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
23323 -
23324 - /* Set:
23325 - * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
23326 - * txon=1,paon=1,oscon=1,synthon_force=1
23327 - */
23328 - REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
23329 - udelay(30);
23330 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
23331 -
23332 - /* find off_6_1; */
23333 - for (i = 6; i > 0; i--) {
23334 - regVal = REG_READ(ah, 0x7834);
23335 - regVal |= (1 << (20 + i));
23336 - REG_WRITE(ah, 0x7834, regVal);
23337 - udelay(1);
23338 - //regVal = REG_READ(ah, 0x7834);
23339 - regVal &= (~(0x1 << (20 + i)));
23340 - regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
23341 - << (20 + i));
23342 - REG_WRITE(ah, 0x7834, regVal);
23343 - }
23344 -
23345 - regVal = (regVal >>20) & 0x7f;
23346 -
23347 - /* Update PA cal info */
23348 - if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
23349 - if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
23350 - ah->pacal_info.max_skipcount =
23351 - 2 * ah->pacal_info.max_skipcount;
23352 - ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
23353 - } else {
23354 - ah->pacal_info.max_skipcount = 1;
23355 - ah->pacal_info.skipcount = 0;
23356 - ah->pacal_info.prev_offset = regVal;
23357 - }
23358 -
23359 - regVal = REG_READ(ah, 0x7834);
23360 - regVal |= 0x1;
23361 - REG_WRITE(ah, 0x7834, regVal);
23362 - regVal = REG_READ(ah, 0x9808);
23363 - regVal &= (~(0x1 << 27));
23364 - REG_WRITE(ah, 0x9808, regVal);
23365 -
23366 - for (i = 0; i < ARRAY_SIZE(regList); i++)
23367 - REG_WRITE(ah, regList[i][0], regList[i][1]);
23368 -}
23369 -
23370 -static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
23371 -{
23372 - struct ath_common *common = ath9k_hw_common(ah);
23373 - u32 regVal;
23374 - int i, offset, offs_6_1, offs_0;
23375 - u32 ccomp_org, reg_field;
23376 - u32 regList[][2] = {
23377 - { 0x786c, 0 },
23378 - { 0x7854, 0 },
23379 - { 0x7820, 0 },
23380 - { 0x7824, 0 },
23381 - { 0x7868, 0 },
23382 - { 0x783c, 0 },
23383 - { 0x7838, 0 },
23384 - };
23385 -
23386 - ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
23387 -
23388 - /* PA CAL is not needed for high power solution */
23389 - if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
23390 - AR5416_EEP_TXGAIN_HIGH_POWER)
23391 - return;
23392 -
23393 - if (AR_SREV_9285_11(ah)) {
23394 - REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
23395 - udelay(10);
23396 - }
23397 -
23398 - for (i = 0; i < ARRAY_SIZE(regList); i++)
23399 - regList[i][1] = REG_READ(ah, regList[i][0]);
23400 -
23401 - regVal = REG_READ(ah, 0x7834);
23402 - regVal &= (~(0x1));
23403 - REG_WRITE(ah, 0x7834, regVal);
23404 - regVal = REG_READ(ah, 0x9808);
23405 - regVal |= (0x1 << 27);
23406 - REG_WRITE(ah, 0x9808, regVal);
23407 -
23408 - REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
23409 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
23410 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
23411 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
23412 - REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
23413 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
23414 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
23415 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
23416 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
23417 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
23418 - REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
23419 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
23420 - ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
23421 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
23422 -
23423 - REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
23424 - udelay(30);
23425 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
23426 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
23427 -
23428 - for (i = 6; i > 0; i--) {
23429 - regVal = REG_READ(ah, 0x7834);
23430 - regVal |= (1 << (19 + i));
23431 - REG_WRITE(ah, 0x7834, regVal);
23432 - udelay(1);
23433 - regVal = REG_READ(ah, 0x7834);
23434 - regVal &= (~(0x1 << (19 + i)));
23435 - reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
23436 - regVal |= (reg_field << (19 + i));
23437 - REG_WRITE(ah, 0x7834, regVal);
23438 - }
23439 -
23440 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
23441 - udelay(1);
23442 - reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
23443 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
23444 - offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
23445 - offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
23446 -
23447 - offset = (offs_6_1<<1) | offs_0;
23448 - offset = offset - 0;
23449 - offs_6_1 = offset>>1;
23450 - offs_0 = offset & 1;
23451 -
23452 - if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
23453 - if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
23454 - ah->pacal_info.max_skipcount =
23455 - 2 * ah->pacal_info.max_skipcount;
23456 - ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
23457 - } else {
23458 - ah->pacal_info.max_skipcount = 1;
23459 - ah->pacal_info.skipcount = 0;
23460 - ah->pacal_info.prev_offset = offset;
23461 - }
23462 -
23463 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
23464 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
23465 -
23466 - regVal = REG_READ(ah, 0x7834);
23467 - regVal |= 0x1;
23468 - REG_WRITE(ah, 0x7834, regVal);
23469 - regVal = REG_READ(ah, 0x9808);
23470 - regVal &= (~(0x1 << 27));
23471 - REG_WRITE(ah, 0x9808, regVal);
23472 -
23473 - for (i = 0; i < ARRAY_SIZE(regList); i++)
23474 - REG_WRITE(ah, regList[i][0], regList[i][1]);
23475 -
23476 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
23477 -
23478 - if (AR_SREV_9285_11(ah))
23479 - REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
23480 -
23481 -}
23482 -
23483 -bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
23484 - u8 rxchainmask, bool longcal)
23485 -{
23486 - bool iscaldone = true;
23487 - struct ath9k_cal_list *currCal = ah->cal_list_curr;
23488 -
23489 - if (currCal &&
23490 - (currCal->calState == CAL_RUNNING ||
23491 - currCal->calState == CAL_WAITING)) {
23492 - iscaldone = ath9k_hw_per_calibration(ah, chan,
23493 - rxchainmask, currCal);
23494 - if (iscaldone) {
23495 - ah->cal_list_curr = currCal = currCal->calNext;
23496 -
23497 - if (currCal->calState == CAL_WAITING) {
23498 - iscaldone = false;
23499 - ath9k_hw_reset_calibration(ah, currCal);
23500 - }
23501 - }
23502 - }
23503 -
23504 - /* Do NF cal only at longer intervals */
23505 - if (longcal) {
23506 - /* Do periodic PAOffset Cal */
23507 - if (AR_SREV_9271(ah)) {
23508 - if (!ah->pacal_info.skipcount)
23509 - ath9k_hw_9271_pa_cal(ah, false);
23510 - else
23511 - ah->pacal_info.skipcount--;
23512 - } else if (AR_SREV_9285_11_OR_LATER(ah)) {
23513 - if (!ah->pacal_info.skipcount)
23514 - ath9k_hw_9285_pa_cal(ah, false);
23515 - else
23516 - ah->pacal_info.skipcount--;
23517 - }
23518 -
23519 - if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER)
23520 - ath9k_olc_temp_compensation(ah);
23521 -
23522 - /* Get the value from the previous NF cal and update history buffer */
23523 - ath9k_hw_getnf(ah, chan);
23524 -
23525 - /*
23526 - * Load the NF from history buffer of the current channel.
23527 - * NF is slow time-variant, so it is OK to use a historical value.
23528 - */
23529 - ath9k_hw_loadnf(ah, ah->curchan);
23530 -
23531 - ath9k_hw_start_nfcal(ah);
23532 - }
23533 -
23534 - return iscaldone;
23535 -}
23536 -EXPORT_SYMBOL(ath9k_hw_calibrate);
23537 -
23538 -/* Carrier leakage Calibration fix */
23539 -static bool ar9285_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
23540 -{
23541 - struct ath_common *common = ath9k_hw_common(ah);
23542 -
23543 - REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
23544 - if (IS_CHAN_HT20(chan)) {
23545 - REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
23546 - REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
23547 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
23548 - AR_PHY_AGC_CONTROL_FLTR_CAL);
23549 - REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
23550 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
23551 - if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
23552 - AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
23553 - ath_print(common, ATH_DBG_CALIBRATE, "offset "
23554 - "calibration failed to complete in "
23555 - "1ms; noisy ??\n");
23556 - return false;
23557 - }
23558 - REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
23559 - REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
23560 - REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
23561 - }
23562 - REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
23563 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
23564 - REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
23565 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
23566 - if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
23567 - 0, AH_WAIT_TIMEOUT)) {
23568 - ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
23569 - "failed to complete in 1ms; noisy ??\n");
23570 - return false;
23571 - }
23572 -
23573 - REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
23574 - REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
23575 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
23576 -
23577 - return true;
23578 -}
23579 -
23580 -static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
23581 -{
23582 - int i;
23583 - u_int32_t txgain_max;
23584 - u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
23585 - u_int32_t reg_clc_I0, reg_clc_Q0;
23586 - u_int32_t i0_num = 0;
23587 - u_int32_t q0_num = 0;
23588 - u_int32_t total_num = 0;
23589 - u_int32_t reg_rf2g5_org;
23590 - bool retv = true;
23591 -
23592 - if (!(ar9285_cl_cal(ah, chan)))
23593 - return false;
23594 -
23595 - txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
23596 - AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
23597 -
23598 - for (i = 0; i < (txgain_max+1); i++) {
23599 - clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
23600 - AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
23601 - if (!(gain_mask & (1 << clc_gain))) {
23602 - gain_mask |= (1 << clc_gain);
23603 - clc_num++;
23604 - }
23605 - }
23606 -
23607 - for (i = 0; i < clc_num; i++) {
23608 - reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
23609 - & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
23610 - reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
23611 - & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
23612 - if (reg_clc_I0 == 0)
23613 - i0_num++;
23614 -
23615 - if (reg_clc_Q0 == 0)
23616 - q0_num++;
23617 - }
23618 - total_num = i0_num + q0_num;
23619 - if (total_num > AR9285_CLCAL_REDO_THRESH) {
23620 - reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
23621 - if (AR_SREV_9285E_20(ah)) {
23622 - REG_WRITE(ah, AR9285_RF2G5,
23623 - (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
23624 - AR9285_RF2G5_IC50TX_XE_SET);
23625 - } else {
23626 - REG_WRITE(ah, AR9285_RF2G5,
23627 - (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
23628 - AR9285_RF2G5_IC50TX_SET);
23629 - }
23630 - retv = ar9285_cl_cal(ah, chan);
23631 - REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
23632 - }
23633 - return retv;
23634 -}
23635 -
23636 -bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
23637 -{
23638 - struct ath_common *common = ath9k_hw_common(ah);
23639 -
23640 - if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
23641 - if (!ar9285_clc(ah, chan))
23642 - return false;
23643 - } else {
23644 - if (AR_SREV_9280_10_OR_LATER(ah)) {
23645 - if (!AR_SREV_9287_10_OR_LATER(ah))
23646 - REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
23647 - AR_PHY_ADC_CTL_OFF_PWDADC);
23648 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
23649 - AR_PHY_AGC_CONTROL_FLTR_CAL);
23650 - }
23651 -
23652 - /* Calibrate the AGC */
23653 - REG_WRITE(ah, AR_PHY_AGC_CONTROL,
23654 - REG_READ(ah, AR_PHY_AGC_CONTROL) |
23655 - AR_PHY_AGC_CONTROL_CAL);
23656 -
23657 - /* Poll for offset calibration complete */
23658 - if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
23659 - 0, AH_WAIT_TIMEOUT)) {
23660 - ath_print(common, ATH_DBG_CALIBRATE,
23661 - "offset calibration failed to "
23662 - "complete in 1ms; noisy environment?\n");
23663 - return false;
23664 - }
23665 -
23666 - if (AR_SREV_9280_10_OR_LATER(ah)) {
23667 - if (!AR_SREV_9287_10_OR_LATER(ah))
23668 - REG_SET_BIT(ah, AR_PHY_ADC_CTL,
23669 - AR_PHY_ADC_CTL_OFF_PWDADC);
23670 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
23671 - AR_PHY_AGC_CONTROL_FLTR_CAL);
23672 - }
23673 - }
23674 -
23675 - /* Do PA Calibration */
23676 - if (AR_SREV_9271(ah))
23677 - ath9k_hw_9271_pa_cal(ah, true);
23678 - else if (AR_SREV_9285_11_OR_LATER(ah))
23679 - ath9k_hw_9285_pa_cal(ah, true);
23680 -
23681 - /* Do NF Calibration after DC offset and other calibrations */
23682 - REG_WRITE(ah, AR_PHY_AGC_CONTROL,
23683 - REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
23684 -
23685 - ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
23686 -
23687 - /* Enable IQ, ADC Gain and ADC DC offset CALs */
23688 - if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
23689 - if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
23690 - INIT_CAL(&ah->adcgain_caldata);
23691 - INSERT_CAL(ah, &ah->adcgain_caldata);
23692 - ath_print(common, ATH_DBG_CALIBRATE,
23693 - "enabling ADC Gain Calibration.\n");
23694 - }
23695 - if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
23696 - INIT_CAL(&ah->adcdc_caldata);
23697 - INSERT_CAL(ah, &ah->adcdc_caldata);
23698 - ath_print(common, ATH_DBG_CALIBRATE,
23699 - "enabling ADC DC Calibration.\n");
23700 - }
23701 - if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
23702 - INIT_CAL(&ah->iq_caldata);
23703 - INSERT_CAL(ah, &ah->iq_caldata);
23704 - ath_print(common, ATH_DBG_CALIBRATE,
23705 - "enabling IQ Calibration.\n");
23706 - }
23707 -
23708 - ah->cal_list_curr = ah->cal_list;
23709 -
23710 - if (ah->cal_list_curr)
23711 - ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
23712 - }
23713 -
23714 - chan->CalValid = 0;
23715 -
23716 - return true;
23717 -}
23718 -
23719 -const struct ath9k_percal_data iq_cal_multi_sample = {
23720 - IQ_MISMATCH_CAL,
23721 - MAX_CAL_SAMPLES,
23722 - PER_MIN_LOG_COUNT,
23723 - ath9k_hw_iqcal_collect,
23724 - ath9k_hw_iqcalibrate
23725 -};
23726 -const struct ath9k_percal_data iq_cal_single_sample = {
23727 - IQ_MISMATCH_CAL,
23728 - MIN_CAL_SAMPLES,
23729 - PER_MAX_LOG_COUNT,
23730 - ath9k_hw_iqcal_collect,
23731 - ath9k_hw_iqcalibrate
23732 -};
23733 -const struct ath9k_percal_data adc_gain_cal_multi_sample = {
23734 - ADC_GAIN_CAL,
23735 - MAX_CAL_SAMPLES,
23736 - PER_MIN_LOG_COUNT,
23737 - ath9k_hw_adc_gaincal_collect,
23738 - ath9k_hw_adc_gaincal_calibrate
23739 -};
23740 -const struct ath9k_percal_data adc_gain_cal_single_sample = {
23741 - ADC_GAIN_CAL,
23742 - MIN_CAL_SAMPLES,
23743 - PER_MAX_LOG_COUNT,
23744 - ath9k_hw_adc_gaincal_collect,
23745 - ath9k_hw_adc_gaincal_calibrate
23746 -};
23747 -const struct ath9k_percal_data adc_dc_cal_multi_sample = {
23748 - ADC_DC_CAL,
23749 - MAX_CAL_SAMPLES,
23750 - PER_MIN_LOG_COUNT,
23751 - ath9k_hw_adc_dccal_collect,
23752 - ath9k_hw_adc_dccal_calibrate
23753 -};
23754 -const struct ath9k_percal_data adc_dc_cal_single_sample = {
23755 - ADC_DC_CAL,
23756 - MIN_CAL_SAMPLES,
23757 - PER_MAX_LOG_COUNT,
23758 - ath9k_hw_adc_dccal_collect,
23759 - ath9k_hw_adc_dccal_calibrate
23760 -};
23761 -const struct ath9k_percal_data adc_init_dc_cal = {
23762 - ADC_DC_INIT_CAL,
23763 - MIN_CAL_SAMPLES,
23764 - INIT_LOG_COUNT,
23765 - ath9k_hw_adc_dccal_collect,
23766 - ath9k_hw_adc_dccal_calibrate
23767 -};
23768 diff --git a/drivers/net/wireless/ath/ath9k/calib.h b/drivers/net/wireless/ath/ath9k/calib.h
23769 index b2c873e..24538bd 100644
23770 --- a/drivers/net/wireless/ath/ath9k/calib.h
23771 +++ b/drivers/net/wireless/ath/ath9k/calib.h
23772 @@ -19,14 +19,6 @@
23773
23774 #include "hw.h"
23775
23776 -extern const struct ath9k_percal_data iq_cal_multi_sample;
23777 -extern const struct ath9k_percal_data iq_cal_single_sample;
23778 -extern const struct ath9k_percal_data adc_gain_cal_multi_sample;
23779 -extern const struct ath9k_percal_data adc_gain_cal_single_sample;
23780 -extern const struct ath9k_percal_data adc_dc_cal_multi_sample;
23781 -extern const struct ath9k_percal_data adc_dc_cal_single_sample;
23782 -extern const struct ath9k_percal_data adc_init_dc_cal;
23783 -
23784 #define AR_PHY_CCA_MAX_AR5416_GOOD_VALUE -85
23785 #define AR_PHY_CCA_MAX_AR9280_GOOD_VALUE -112
23786 #define AR_PHY_CCA_MAX_AR9285_GOOD_VALUE -118
23787 @@ -76,7 +68,8 @@ enum ath9k_cal_types {
23788 ADC_DC_INIT_CAL = 0x1,
23789 ADC_GAIN_CAL = 0x2,
23790 ADC_DC_CAL = 0x4,
23791 - IQ_MISMATCH_CAL = 0x8
23792 + IQ_MISMATCH_CAL = 0x8,
23793 + TEMP_COMP_CAL = 0x10,
23794 };
23795
23796 enum ath9k_cal_state {
23797 @@ -122,14 +115,12 @@ struct ath9k_pacal_info{
23798
23799 bool ath9k_hw_reset_calvalid(struct ath_hw *ah);
23800 void ath9k_hw_start_nfcal(struct ath_hw *ah);
23801 -void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan);
23802 int16_t ath9k_hw_getnf(struct ath_hw *ah,
23803 struct ath9k_channel *chan);
23804 void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah);
23805 s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan);
23806 -bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
23807 - u8 rxchainmask, bool longcal);
23808 -bool ath9k_hw_init_cal(struct ath_hw *ah,
23809 - struct ath9k_channel *chan);
23810 +void ath9k_hw_reset_calibration(struct ath_hw *ah,
23811 + struct ath9k_cal_list *currCal);
23812 +
23813
23814 #endif /* CALIB_H */
23815 diff --git a/drivers/net/wireless/ath/ath9k/common.h b/drivers/net/wireless/ath/ath9k/common.h
23816 index 72a835d..e08f7e5 100644
23817 --- a/drivers/net/wireless/ath/ath9k/common.h
23818 +++ b/drivers/net/wireless/ath/ath9k/common.h
23819 @@ -20,6 +20,7 @@
23820 #include "../debug.h"
23821
23822 #include "hw.h"
23823 +#include "hw-ops.h"
23824
23825 /* Common header for Atheros 802.11n base driver cores */
23826
23827 @@ -76,11 +77,12 @@ struct ath_buf {
23828 an aggregate) */
23829 struct ath_buf *bf_next; /* next subframe in the aggregate */
23830 struct sk_buff *bf_mpdu; /* enclosing frame structure */
23831 - struct ath_desc *bf_desc; /* virtual addr of desc */
23832 + void *bf_desc; /* virtual addr of desc */
23833 dma_addr_t bf_daddr; /* physical addr of desc */
23834 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
23835 bool bf_stale;
23836 bool bf_isnullfunc;
23837 + bool bf_tx_aborted;
23838 u16 bf_flags;
23839 struct ath_buf_state bf_state;
23840 dma_addr_t bf_dmacontext;
23841 diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
23842 index b22d465..008ade2 100644
23843 --- a/drivers/net/wireless/ath/ath9k/debug.c
23844 +++ b/drivers/net/wireless/ath/ath9k/debug.c
23845 @@ -181,6 +181,10 @@ void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status)
23846 sc->debug.stats.istats.total++;
23847 if (status & ATH9K_INT_RX)
23848 sc->debug.stats.istats.rxok++;
23849 + if (status & ATH9K_INT_RXLP)
23850 + sc->debug.stats.istats.rxlp++;
23851 + if (status & ATH9K_INT_RXHP)
23852 + sc->debug.stats.istats.rxhp++;
23853 if (status & ATH9K_INT_RXEOL)
23854 sc->debug.stats.istats.rxeol++;
23855 if (status & ATH9K_INT_RXORN)
23856 @@ -225,6 +229,10 @@ static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
23857 len += snprintf(buf + len, sizeof(buf) - len,
23858 "%8s: %10u\n", "RX", sc->debug.stats.istats.rxok);
23859 len += snprintf(buf + len, sizeof(buf) - len,
23860 + "%8s: %10u\n", "RXLP", sc->debug.stats.istats.rxlp);
23861 + len += snprintf(buf + len, sizeof(buf) - len,
23862 + "%8s: %10u\n", "RXHP", sc->debug.stats.istats.rxhp);
23863 + len += snprintf(buf + len, sizeof(buf) - len,
23864 "%8s: %10u\n", "RXEOL", sc->debug.stats.istats.rxeol);
23865 len += snprintf(buf + len, sizeof(buf) - len,
23866 "%8s: %10u\n", "RXORN", sc->debug.stats.istats.rxorn);
23867 diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
23868 index b2af9de..c545960 100644
23869 --- a/drivers/net/wireless/ath/ath9k/debug.h
23870 +++ b/drivers/net/wireless/ath/ath9k/debug.h
23871 @@ -35,6 +35,8 @@ struct ath_buf;
23872 * struct ath_interrupt_stats - Contains statistics about interrupts
23873 * @total: Total no. of interrupts generated so far
23874 * @rxok: RX with no errors
23875 + * @rxlp: RX with low priority RX
23876 + * @rxhp: RX with high priority, uapsd only
23877 * @rxeol: RX with no more RXDESC available
23878 * @rxorn: RX FIFO overrun
23879 * @txok: TX completed at the requested rate
23880 @@ -55,6 +57,8 @@ struct ath_buf;
23881 struct ath_interrupt_stats {
23882 u32 total;
23883 u32 rxok;
23884 + u32 rxlp;
23885 + u32 rxhp;
23886 u32 rxeol;
23887 u32 rxorn;
23888 u32 txok;
23889 diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
23890 index dacaae9..bd9dff3 100644
23891 --- a/drivers/net/wireless/ath/ath9k/eeprom.c
23892 +++ b/drivers/net/wireless/ath/ath9k/eeprom.c
23893 @@ -256,14 +256,13 @@ int ath9k_hw_eeprom_init(struct ath_hw *ah)
23894 {
23895 int status;
23896
23897 - if (AR_SREV_9287(ah)) {
23898 - ah->eep_map = EEP_MAP_AR9287;
23899 - ah->eep_ops = &eep_AR9287_ops;
23900 + if (AR_SREV_9300_20_OR_LATER(ah))
23901 + ah->eep_ops = &eep_ar9300_ops;
23902 + else if (AR_SREV_9287(ah)) {
23903 + ah->eep_ops = &eep_ar9287_ops;
23904 } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
23905 - ah->eep_map = EEP_MAP_4KBITS;
23906 ah->eep_ops = &eep_4k_ops;
23907 } else {
23908 - ah->eep_map = EEP_MAP_DEFAULT;
23909 ah->eep_ops = &eep_def_ops;
23910 }
23911
23912 diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
23913 index 2f2993b..fb9c8c9 100644
23914 --- a/drivers/net/wireless/ath/ath9k/eeprom.h
23915 +++ b/drivers/net/wireless/ath/ath9k/eeprom.h
23916 @@ -19,6 +19,7 @@
23917
23918 #include "../ath.h"
23919 #include <net/cfg80211.h>
23920 +#include "ar9003_eeprom.h"
23921
23922 #define AH_USE_EEPROM 0x1
23923
23924 @@ -93,7 +94,6 @@
23925 */
23926 #define AR9285_RDEXT_DEFAULT 0x1F
23927
23928 -#define AR_EEPROM_MAC(i) (0x1d+(i))
23929 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
23930 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
23931 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
23932 @@ -155,6 +155,7 @@
23933 #define AR5416_BCHAN_UNUSED 0xFF
23934 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
23935 #define AR5416_MAX_CHAINS 3
23936 +#define AR9300_MAX_CHAINS 3
23937 #define AR5416_PWR_TABLE_OFFSET_DB -5
23938
23939 /* Rx gain type values */
23940 @@ -249,16 +250,20 @@ enum eeprom_param {
23941 EEP_MINOR_REV,
23942 EEP_TX_MASK,
23943 EEP_RX_MASK,
23944 + EEP_FSTCLK_5G,
23945 EEP_RXGAIN_TYPE,
23946 - EEP_TXGAIN_TYPE,
23947 EEP_OL_PWRCTRL,
23948 + EEP_TXGAIN_TYPE,
23949 EEP_RC_CHAIN_MASK,
23950 EEP_DAC_HPWR_5G,
23951 EEP_FRAC_N_5G,
23952 EEP_DEV_TYPE,
23953 EEP_TEMPSENSE_SLOPE,
23954 EEP_TEMPSENSE_SLOPE_PAL_ON,
23955 - EEP_PWR_TABLE_OFFSET
23956 + EEP_PWR_TABLE_OFFSET,
23957 + EEP_DRIVE_STRENGTH,
23958 + EEP_INTERNAL_REGULATOR,
23959 + EEP_SWREG
23960 };
23961
23962 enum ar5416_rates {
23963 @@ -656,13 +661,6 @@ struct ath9k_country_entry {
23964 u8 iso[3];
23965 };
23966
23967 -enum ath9k_eep_map {
23968 - EEP_MAP_DEFAULT = 0x0,
23969 - EEP_MAP_4KBITS,
23970 - EEP_MAP_AR9287,
23971 - EEP_MAP_MAX
23972 -};
23973 -
23974 struct eeprom_ops {
23975 int (*check_eeprom)(struct ath_hw *hw);
23976 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
23977 @@ -713,6 +711,8 @@ int ath9k_hw_eeprom_init(struct ath_hw *ah);
23978
23979 extern const struct eeprom_ops eep_def_ops;
23980 extern const struct eeprom_ops eep_4k_ops;
23981 -extern const struct eeprom_ops eep_AR9287_ops;
23982 +extern const struct eeprom_ops eep_ar9287_ops;
23983 +extern const struct eeprom_ops eep_ar9287_ops;
23984 +extern const struct eeprom_ops eep_ar9300_ops;
23985
23986 #endif /* EEPROM_H */
23987 diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
23988 index 0354fe5..2384a9f 100644
23989 --- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
23990 +++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
23991 @@ -15,6 +15,7 @@
23992 */
23993
23994 #include "hw.h"
23995 +#include "ar9002_phy.h"
23996
23997 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
23998 {
23999 @@ -182,11 +183,11 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
24000 switch (param) {
24001 case EEP_NFTHRESH_2:
24002 return pModal->noiseFloorThreshCh[0];
24003 - case AR_EEPROM_MAC(0):
24004 + case EEP_MAC_LSW:
24005 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
24006 - case AR_EEPROM_MAC(1):
24007 + case EEP_MAC_MID:
24008 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
24009 - case AR_EEPROM_MAC(2):
24010 + case EEP_MAC_MSW:
24011 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
24012 case EEP_REG_0:
24013 return pBase->regDmn[0];
24014 diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
24015 index d8ca94c..b471db5 100644
24016 --- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
24017 +++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
24018 @@ -15,6 +15,7 @@
24019 */
24020
24021 #include "hw.h"
24022 +#include "ar9002_phy.h"
24023
24024 static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
24025 {
24026 @@ -172,11 +173,11 @@ static u32 ath9k_hw_AR9287_get_eeprom(struct ath_hw *ah,
24027 switch (param) {
24028 case EEP_NFTHRESH_2:
24029 return pModal->noiseFloorThreshCh[0];
24030 - case AR_EEPROM_MAC(0):
24031 + case EEP_MAC_LSW:
24032 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
24033 - case AR_EEPROM_MAC(1):
24034 + case EEP_MAC_MID:
24035 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
24036 - case AR_EEPROM_MAC(2):
24037 + case EEP_MAC_MSW:
24038 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
24039 case EEP_REG_0:
24040 return pBase->regDmn[0];
24041 @@ -1169,7 +1170,7 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
24042 #undef EEP_MAP9287_SPURCHAN
24043 }
24044
24045 -const struct eeprom_ops eep_AR9287_ops = {
24046 +const struct eeprom_ops eep_ar9287_ops = {
24047 .check_eeprom = ath9k_hw_AR9287_check_eeprom,
24048 .get_eeprom = ath9k_hw_AR9287_get_eeprom,
24049 .fill_eeprom = ath9k_hw_AR9287_fill_eeprom,
24050 diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
24051 index 404a034..3d1b86b 100644
24052 --- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
24053 +++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
24054 @@ -15,6 +15,7 @@
24055 */
24056
24057 #include "hw.h"
24058 +#include "ar9002_phy.h"
24059
24060 static void ath9k_get_txgain_index(struct ath_hw *ah,
24061 struct ath9k_channel *chan,
24062 @@ -237,11 +238,11 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
24063 return pModal[0].noiseFloorThreshCh[0];
24064 case EEP_NFTHRESH_2:
24065 return pModal[1].noiseFloorThreshCh[0];
24066 - case AR_EEPROM_MAC(0):
24067 + case EEP_MAC_LSW:
24068 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
24069 - case AR_EEPROM_MAC(1):
24070 + case EEP_MAC_MID:
24071 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
24072 - case AR_EEPROM_MAC(2):
24073 + case EEP_MAC_MSW:
24074 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
24075 case EEP_REG_0:
24076 return pBase->regDmn[0];
24077 diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h
24078 new file mode 100644
24079 index 0000000..8463cb2
24080 --- /dev/null
24081 +++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
24082 @@ -0,0 +1,284 @@
24083 +/*
24084 + * Copyright (c) 2010 Atheros Communications Inc.
24085 + *
24086 + * Permission to use, copy, modify, and/or distribute this software for any
24087 + * purpose with or without fee is hereby granted, provided that the above
24088 + * copyright notice and this permission notice appear in all copies.
24089 + *
24090 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
24091 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
24092 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
24093 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
24094 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
24095 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
24096 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24097 + */
24098 +
24099 +#ifndef ATH9K_HW_OPS_H
24100 +#define ATH9K_HW_OPS_H
24101 +
24102 +#include "hw.h"
24103 +
24104 +/* Hardware core and driver accessible callbacks */
24105 +
24106 +static inline void ath9k_hw_configpcipowersave(struct ath_hw *ah,
24107 + int restore,
24108 + int power_off)
24109 +{
24110 + ath9k_hw_ops(ah)->config_pci_powersave(ah, restore, power_off);
24111 +}
24112 +
24113 +static inline void ath9k_hw_rxena(struct ath_hw *ah)
24114 +{
24115 + ath9k_hw_ops(ah)->rx_enable(ah);
24116 +}
24117 +
24118 +static inline void ath9k_hw_set_desc_link(struct ath_hw *ah, void *ds,
24119 + u32 link)
24120 +{
24121 + ath9k_hw_ops(ah)->set_desc_link(ds, link);
24122 +}
24123 +
24124 +static inline void ath9k_hw_get_desc_link(struct ath_hw *ah, void *ds,
24125 + u32 **link)
24126 +{
24127 + ath9k_hw_ops(ah)->get_desc_link(ds, link);
24128 +}
24129 +static inline bool ath9k_hw_calibrate(struct ath_hw *ah,
24130 + struct ath9k_channel *chan,
24131 + u8 rxchainmask,
24132 + bool longcal)
24133 +{
24134 + return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal);
24135 +}
24136 +
24137 +static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
24138 +{
24139 + return ath9k_hw_ops(ah)->get_isr(ah, masked);
24140 +}
24141 +
24142 +static inline void ath9k_hw_filltxdesc(struct ath_hw *ah, void *ds, u32 seglen,
24143 + bool is_firstseg, bool is_lastseg,
24144 + const void *ds0, dma_addr_t buf_addr,
24145 + unsigned int qcu)
24146 +{
24147 + ath9k_hw_ops(ah)->fill_txdesc(ah, ds, seglen, is_firstseg, is_lastseg,
24148 + ds0, buf_addr, qcu);
24149 +}
24150 +
24151 +static inline void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
24152 +{
24153 + ath9k_hw_ops(ah)->clear_txdesc(ah, ds);
24154 +}
24155 +
24156 +static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds,
24157 + struct ath_tx_status *ts)
24158 +{
24159 + return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts);
24160 +}
24161 +
24162 +static inline void ath9k_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
24163 + u32 pktLen, enum ath9k_pkt_type type,
24164 + u32 txPower, u32 keyIx,
24165 + enum ath9k_key_type keyType,
24166 + u32 flags)
24167 +{
24168 + ath9k_hw_ops(ah)->set11n_txdesc(ah, ds, pktLen, type, txPower, keyIx,
24169 + keyType, flags);
24170 +}
24171 +
24172 +static inline void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
24173 + void *lastds,
24174 + u32 durUpdateEn, u32 rtsctsRate,
24175 + u32 rtsctsDuration,
24176 + struct ath9k_11n_rate_series series[],
24177 + u32 nseries, u32 flags)
24178 +{
24179 + ath9k_hw_ops(ah)->set11n_ratescenario(ah, ds, lastds, durUpdateEn,
24180 + rtsctsRate, rtsctsDuration, series,
24181 + nseries, flags);
24182 +}
24183 +
24184 +static inline void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
24185 + u32 aggrLen)
24186 +{
24187 + ath9k_hw_ops(ah)->set11n_aggr_first(ah, ds, aggrLen);
24188 +}
24189 +
24190 +static inline void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
24191 + u32 numDelims)
24192 +{
24193 + ath9k_hw_ops(ah)->set11n_aggr_middle(ah, ds, numDelims);
24194 +}
24195 +
24196 +static inline void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
24197 +{
24198 + ath9k_hw_ops(ah)->set11n_aggr_last(ah, ds);
24199 +}
24200 +
24201 +static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
24202 +{
24203 + ath9k_hw_ops(ah)->clr11n_aggr(ah, ds);
24204 +}
24205 +
24206 +static inline void ath9k_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
24207 + u32 burstDuration)
24208 +{
24209 + ath9k_hw_ops(ah)->set11n_burstduration(ah, ds, burstDuration);
24210 +}
24211 +
24212 +static inline void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
24213 + u32 vmf)
24214 +{
24215 + ath9k_hw_ops(ah)->set11n_virtualmorefrag(ah, ds, vmf);
24216 +}
24217 +
24218 +/* Private hardware call ops */
24219 +
24220 +/* PHY ops */
24221 +
24222 +static inline int ath9k_hw_rf_set_freq(struct ath_hw *ah,
24223 + struct ath9k_channel *chan)
24224 +{
24225 + return ath9k_hw_private_ops(ah)->rf_set_freq(ah, chan);
24226 +}
24227 +
24228 +static inline void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah,
24229 + struct ath9k_channel *chan)
24230 +{
24231 + ath9k_hw_private_ops(ah)->spur_mitigate_freq(ah, chan);
24232 +}
24233 +
24234 +static inline int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
24235 +{
24236 + if (!ath9k_hw_private_ops(ah)->rf_alloc_ext_banks)
24237 + return 0;
24238 +
24239 + return ath9k_hw_private_ops(ah)->rf_alloc_ext_banks(ah);
24240 +}
24241 +
24242 +static inline void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
24243 +{
24244 + if (!ath9k_hw_private_ops(ah)->rf_free_ext_banks)
24245 + return;
24246 +
24247 + ath9k_hw_private_ops(ah)->rf_free_ext_banks(ah);
24248 +}
24249 +
24250 +static inline bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
24251 + struct ath9k_channel *chan,
24252 + u16 modesIndex)
24253 +{
24254 + if (!ath9k_hw_private_ops(ah)->set_rf_regs)
24255 + return true;
24256 +
24257 + return ath9k_hw_private_ops(ah)->set_rf_regs(ah, chan, modesIndex);
24258 +}
24259 +
24260 +static inline void ath9k_hw_init_bb(struct ath_hw *ah,
24261 + struct ath9k_channel *chan)
24262 +{
24263 + return ath9k_hw_private_ops(ah)->init_bb(ah, chan);
24264 +}
24265 +
24266 +static inline void ath9k_hw_set_channel_regs(struct ath_hw *ah,
24267 + struct ath9k_channel *chan)
24268 +{
24269 + return ath9k_hw_private_ops(ah)->set_channel_regs(ah, chan);
24270 +}
24271 +
24272 +static inline int ath9k_hw_process_ini(struct ath_hw *ah,
24273 + struct ath9k_channel *chan)
24274 +{
24275 + return ath9k_hw_private_ops(ah)->process_ini(ah, chan);
24276 +}
24277 +
24278 +static inline void ath9k_olc_init(struct ath_hw *ah)
24279 +{
24280 + if (!ath9k_hw_private_ops(ah)->olc_init)
24281 + return;
24282 +
24283 + return ath9k_hw_private_ops(ah)->olc_init(ah);
24284 +}
24285 +
24286 +static inline void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
24287 +{
24288 + return ath9k_hw_private_ops(ah)->set_rfmode(ah, chan);
24289 +}
24290 +
24291 +static inline void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
24292 +{
24293 + return ath9k_hw_private_ops(ah)->mark_phy_inactive(ah);
24294 +}
24295 +
24296 +static inline void ath9k_hw_set_delta_slope(struct ath_hw *ah,
24297 + struct ath9k_channel *chan)
24298 +{
24299 + return ath9k_hw_private_ops(ah)->set_delta_slope(ah, chan);
24300 +}
24301 +
24302 +static inline bool ath9k_hw_rfbus_req(struct ath_hw *ah)
24303 +{
24304 + return ath9k_hw_private_ops(ah)->rfbus_req(ah);
24305 +}
24306 +
24307 +static inline void ath9k_hw_rfbus_done(struct ath_hw *ah)
24308 +{
24309 + return ath9k_hw_private_ops(ah)->rfbus_done(ah);
24310 +}
24311 +
24312 +static inline void ath9k_enable_rfkill(struct ath_hw *ah)
24313 +{
24314 + return ath9k_hw_private_ops(ah)->enable_rfkill(ah);
24315 +}
24316 +
24317 +static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah)
24318 +{
24319 + if (!ath9k_hw_private_ops(ah)->restore_chainmask)
24320 + return;
24321 +
24322 + return ath9k_hw_private_ops(ah)->restore_chainmask(ah);
24323 +}
24324 +
24325 +static inline void ath9k_hw_set_diversity(struct ath_hw *ah, bool value)
24326 +{
24327 + return ath9k_hw_private_ops(ah)->set_diversity(ah, value);
24328 +}
24329 +
24330 +static inline bool ath9k_hw_ani_control(struct ath_hw *ah,
24331 + enum ath9k_ani_cmd cmd, int param)
24332 +{
24333 + return ath9k_hw_private_ops(ah)->ani_control(ah, cmd, param);
24334 +}
24335 +
24336 +static inline void ath9k_hw_do_getnf(struct ath_hw *ah,
24337 + int16_t nfarray[NUM_NF_READINGS])
24338 +{
24339 + ath9k_hw_private_ops(ah)->do_getnf(ah, nfarray);
24340 +}
24341 +
24342 +static inline void ath9k_hw_loadnf(struct ath_hw *ah,
24343 + struct ath9k_channel *chan)
24344 +{
24345 + ath9k_hw_private_ops(ah)->loadnf(ah, chan);
24346 +}
24347 +
24348 +static inline bool ath9k_hw_init_cal(struct ath_hw *ah,
24349 + struct ath9k_channel *chan)
24350 +{
24351 + return ath9k_hw_private_ops(ah)->init_cal(ah, chan);
24352 +}
24353 +
24354 +static inline void ath9k_hw_setup_calibration(struct ath_hw *ah,
24355 + struct ath9k_cal_list *currCal)
24356 +{
24357 + ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal);
24358 +}
24359 +
24360 +static inline bool ath9k_hw_iscal_supported(struct ath_hw *ah,
24361 + enum ath9k_cal_types calType)
24362 +{
24363 + return ath9k_hw_private_ops(ah)->iscal_supported(ah, calType);
24364 +}
24365 +
24366 +#endif /* ATH9K_HW_OPS_H */
24367 diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
24368 index 3b9f4c1..11ccb54 100644
24369 --- a/drivers/net/wireless/ath/ath9k/hw.c
24370 +++ b/drivers/net/wireless/ath/ath9k/hw.c
24371 @@ -1,5 +1,5 @@
24372 /*
24373 - * Copyright (c) 2008-2009 Atheros Communications Inc.
24374 + * Copyright (c) 2008-2010 Atheros Communications Inc.
24375 *
24376 * Permission to use, copy, modify, and/or distribute this software for any
24377 * purpose with or without fee is hereby granted, provided that the above
24378 @@ -14,19 +14,17 @@
24379 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24380 */
24381
24382 -#include <linux/io.h>
24383 #include <asm/unaligned.h>
24384
24385 #include "hw.h"
24386 +#include "hw-ops.h"
24387 #include "rc.h"
24388 -#include "initvals.h"
24389
24390 #define ATH9K_CLOCK_RATE_CCK 22
24391 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
24392 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
24393
24394 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
24395 -static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
24396
24397 MODULE_AUTHOR("Atheros Communications");
24398 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
24399 @@ -45,6 +43,37 @@ static void __exit ath9k_exit(void)
24400 }
24401 module_exit(ath9k_exit);
24402
24403 +/* Private hardware callbacks */
24404 +
24405 +static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
24406 +{
24407 + ath9k_hw_private_ops(ah)->init_cal_settings(ah);
24408 +}
24409 +
24410 +static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
24411 +{
24412 + ath9k_hw_private_ops(ah)->init_mode_regs(ah);
24413 +}
24414 +
24415 +static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
24416 +{
24417 + return ath9k_hw_private_ops(ah)->macversion_supported(ah->hw_version.macVersion);
24418 +}
24419 +
24420 +static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
24421 + struct ath9k_channel *chan)
24422 +{
24423 + return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
24424 +}
24425 +
24426 +static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
24427 +{
24428 + if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
24429 + return;
24430 +
24431 + ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
24432 +}
24433 +
24434 /********************/
24435 /* Helper Functions */
24436 /********************/
24437 @@ -232,21 +261,6 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
24438 }
24439 }
24440
24441 -static int ath9k_hw_get_radiorev(struct ath_hw *ah)
24442 -{
24443 - u32 val;
24444 - int i;
24445 -
24446 - REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
24447 -
24448 - for (i = 0; i < 8; i++)
24449 - REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
24450 - val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
24451 - val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
24452 -
24453 - return ath9k_hw_reverse_bits(val, 8);
24454 -}
24455 -
24456 /************************************/
24457 /* HW Attach, Detach, Init Routines */
24458 /************************************/
24459 @@ -269,18 +283,25 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
24460 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
24461 }
24462
24463 +/* This should work for all families including legacy */
24464 static bool ath9k_hw_chip_test(struct ath_hw *ah)
24465 {
24466 struct ath_common *common = ath9k_hw_common(ah);
24467 - u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
24468 + u32 regAddr[2] = { AR_STA_ID0 };
24469 u32 regHold[2];
24470 u32 patternData[4] = { 0x55555555,
24471 0xaaaaaaaa,
24472 0x66666666,
24473 0x99999999 };
24474 - int i, j;
24475 + int i, j, loop_max;
24476 +
24477 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
24478 + loop_max = 2;
24479 + regAddr[1] = AR_PHY_BASE + (8 << 2);
24480 + } else
24481 + loop_max = 1;
24482
24483 - for (i = 0; i < 2; i++) {
24484 + for (i = 0; i < loop_max; i++) {
24485 u32 addr = regAddr[i];
24486 u32 wrData, rdData;
24487
24488 @@ -349,6 +370,9 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
24489
24490 ah->config.rx_intr_mitigation = true;
24491
24492 + if (AR_SREV_9300_20_OR_LATER(ah))
24493 + ah->config.tx_intr_mitigation = true;
24494 +
24495 /*
24496 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
24497 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
24498 @@ -368,7 +392,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
24499 if (num_possible_cpus() > 1)
24500 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
24501 }
24502 -EXPORT_SYMBOL(ath9k_hw_init);
24503
24504 static void ath9k_hw_init_defaults(struct ath_hw *ah)
24505 {
24506 @@ -396,44 +419,17 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
24507 ah->power_mode = ATH9K_PM_UNDEFINED;
24508 }
24509
24510 -static int ath9k_hw_rf_claim(struct ath_hw *ah)
24511 -{
24512 - u32 val;
24513 -
24514 - REG_WRITE(ah, AR_PHY(0), 0x00000007);
24515 -
24516 - val = ath9k_hw_get_radiorev(ah);
24517 - switch (val & AR_RADIO_SREV_MAJOR) {
24518 - case 0:
24519 - val = AR_RAD5133_SREV_MAJOR;
24520 - break;
24521 - case AR_RAD5133_SREV_MAJOR:
24522 - case AR_RAD5122_SREV_MAJOR:
24523 - case AR_RAD2133_SREV_MAJOR:
24524 - case AR_RAD2122_SREV_MAJOR:
24525 - break;
24526 - default:
24527 - ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
24528 - "Radio Chip Rev 0x%02X not supported\n",
24529 - val & AR_RADIO_SREV_MAJOR);
24530 - return -EOPNOTSUPP;
24531 - }
24532 -
24533 - ah->hw_version.analog5GhzRev = val;
24534 -
24535 - return 0;
24536 -}
24537 -
24538 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
24539 {
24540 struct ath_common *common = ath9k_hw_common(ah);
24541 u32 sum;
24542 int i;
24543 u16 eeval;
24544 + u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
24545
24546 sum = 0;
24547 for (i = 0; i < 3; i++) {
24548 - eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
24549 + eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
24550 sum += eeval;
24551 common->macaddr[2 * i] = eeval >> 8;
24552 common->macaddr[2 * i + 1] = eeval & 0xff;
24553 @@ -444,54 +440,6 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
24554 return 0;
24555 }
24556
24557 -static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
24558 -{
24559 - u32 rxgain_type;
24560 -
24561 - if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
24562 - rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
24563 -
24564 - if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
24565 - INIT_INI_ARRAY(&ah->iniModesRxGain,
24566 - ar9280Modes_backoff_13db_rxgain_9280_2,
24567 - ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
24568 - else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
24569 - INIT_INI_ARRAY(&ah->iniModesRxGain,
24570 - ar9280Modes_backoff_23db_rxgain_9280_2,
24571 - ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
24572 - else
24573 - INIT_INI_ARRAY(&ah->iniModesRxGain,
24574 - ar9280Modes_original_rxgain_9280_2,
24575 - ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
24576 - } else {
24577 - INIT_INI_ARRAY(&ah->iniModesRxGain,
24578 - ar9280Modes_original_rxgain_9280_2,
24579 - ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
24580 - }
24581 -}
24582 -
24583 -static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
24584 -{
24585 - u32 txgain_type;
24586 -
24587 - if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
24588 - txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
24589 -
24590 - if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
24591 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24592 - ar9280Modes_high_power_tx_gain_9280_2,
24593 - ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
24594 - else
24595 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24596 - ar9280Modes_original_tx_gain_9280_2,
24597 - ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
24598 - } else {
24599 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24600 - ar9280Modes_original_tx_gain_9280_2,
24601 - ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
24602 - }
24603 -}
24604 -
24605 static int ath9k_hw_post_init(struct ath_hw *ah)
24606 {
24607 int ecode;
24608 @@ -501,9 +449,11 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
24609 return -ENODEV;
24610 }
24611
24612 - ecode = ath9k_hw_rf_claim(ah);
24613 - if (ecode != 0)
24614 - return ecode;
24615 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
24616 + ecode = ar9002_hw_rf_claim(ah);
24617 + if (ecode != 0)
24618 + return ecode;
24619 + }
24620
24621 ecode = ath9k_hw_eeprom_init(ah);
24622 if (ecode != 0)
24623 @@ -514,14 +464,12 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
24624 ah->eep_ops->get_eeprom_ver(ah),
24625 ah->eep_ops->get_eeprom_rev(ah));
24626
24627 - if (!AR_SREV_9280_10_OR_LATER(ah)) {
24628 - ecode = ath9k_hw_rf_alloc_ext_banks(ah);
24629 - if (ecode) {
24630 - ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
24631 - "Failed allocating banks for "
24632 - "external radio\n");
24633 - return ecode;
24634 - }
24635 + ecode = ath9k_hw_rf_alloc_ext_banks(ah);
24636 + if (ecode) {
24637 + ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
24638 + "Failed allocating banks for "
24639 + "external radio\n");
24640 + return ecode;
24641 }
24642
24643 if (!AR_SREV_9100(ah)) {
24644 @@ -532,351 +480,31 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
24645 return 0;
24646 }
24647
24648 -static bool ath9k_hw_devid_supported(u16 devid)
24649 -{
24650 - switch (devid) {
24651 - case AR5416_DEVID_PCI:
24652 - case AR5416_DEVID_PCIE:
24653 - case AR5416_AR9100_DEVID:
24654 - case AR9160_DEVID_PCI:
24655 - case AR9280_DEVID_PCI:
24656 - case AR9280_DEVID_PCIE:
24657 - case AR9285_DEVID_PCIE:
24658 - case AR5416_DEVID_AR9287_PCI:
24659 - case AR5416_DEVID_AR9287_PCIE:
24660 - case AR2427_DEVID_PCIE:
24661 - return true;
24662 - default:
24663 - break;
24664 - }
24665 - return false;
24666 -}
24667 -
24668 -static bool ath9k_hw_macversion_supported(u32 macversion)
24669 -{
24670 - switch (macversion) {
24671 - case AR_SREV_VERSION_5416_PCI:
24672 - case AR_SREV_VERSION_5416_PCIE:
24673 - case AR_SREV_VERSION_9160:
24674 - case AR_SREV_VERSION_9100:
24675 - case AR_SREV_VERSION_9280:
24676 - case AR_SREV_VERSION_9285:
24677 - case AR_SREV_VERSION_9287:
24678 - case AR_SREV_VERSION_9271:
24679 - return true;
24680 - default:
24681 - break;
24682 - }
24683 - return false;
24684 -}
24685 -
24686 -static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
24687 -{
24688 - if (AR_SREV_9160_10_OR_LATER(ah)) {
24689 - if (AR_SREV_9280_10_OR_LATER(ah)) {
24690 - ah->iq_caldata.calData = &iq_cal_single_sample;
24691 - ah->adcgain_caldata.calData =
24692 - &adc_gain_cal_single_sample;
24693 - ah->adcdc_caldata.calData =
24694 - &adc_dc_cal_single_sample;
24695 - ah->adcdc_calinitdata.calData =
24696 - &adc_init_dc_cal;
24697 - } else {
24698 - ah->iq_caldata.calData = &iq_cal_multi_sample;
24699 - ah->adcgain_caldata.calData =
24700 - &adc_gain_cal_multi_sample;
24701 - ah->adcdc_caldata.calData =
24702 - &adc_dc_cal_multi_sample;
24703 - ah->adcdc_calinitdata.calData =
24704 - &adc_init_dc_cal;
24705 - }
24706 - ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
24707 - }
24708 -}
24709 -
24710 -static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
24711 -{
24712 - if (AR_SREV_9271(ah)) {
24713 - INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
24714 - ARRAY_SIZE(ar9271Modes_9271), 6);
24715 - INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
24716 - ARRAY_SIZE(ar9271Common_9271), 2);
24717 - INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
24718 - ar9271Common_normal_cck_fir_coeff_9271,
24719 - ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
24720 - INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
24721 - ar9271Common_japan_2484_cck_fir_coeff_9271,
24722 - ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
24723 - INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
24724 - ar9271Modes_9271_1_0_only,
24725 - ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
24726 - INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
24727 - ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
24728 - INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
24729 - ar9271Modes_high_power_tx_gain_9271,
24730 - ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
24731 - INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
24732 - ar9271Modes_normal_power_tx_gain_9271,
24733 - ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
24734 - return;
24735 - }
24736 -
24737 - if (AR_SREV_9287_11_OR_LATER(ah)) {
24738 - INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
24739 - ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
24740 - INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
24741 - ARRAY_SIZE(ar9287Common_9287_1_1), 2);
24742 - if (ah->config.pcie_clock_req)
24743 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24744 - ar9287PciePhy_clkreq_off_L1_9287_1_1,
24745 - ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
24746 - else
24747 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24748 - ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
24749 - ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
24750 - 2);
24751 - } else if (AR_SREV_9287_10_OR_LATER(ah)) {
24752 - INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
24753 - ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
24754 - INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
24755 - ARRAY_SIZE(ar9287Common_9287_1_0), 2);
24756 -
24757 - if (ah->config.pcie_clock_req)
24758 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24759 - ar9287PciePhy_clkreq_off_L1_9287_1_0,
24760 - ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
24761 - else
24762 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24763 - ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
24764 - ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
24765 - 2);
24766 - } else if (AR_SREV_9285_12_OR_LATER(ah)) {
24767 -
24768 -
24769 - INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
24770 - ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
24771 - INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
24772 - ARRAY_SIZE(ar9285Common_9285_1_2), 2);
24773 -
24774 - if (ah->config.pcie_clock_req) {
24775 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24776 - ar9285PciePhy_clkreq_off_L1_9285_1_2,
24777 - ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
24778 - } else {
24779 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24780 - ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
24781 - ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
24782 - 2);
24783 - }
24784 - } else if (AR_SREV_9285_10_OR_LATER(ah)) {
24785 - INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
24786 - ARRAY_SIZE(ar9285Modes_9285), 6);
24787 - INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
24788 - ARRAY_SIZE(ar9285Common_9285), 2);
24789 -
24790 - if (ah->config.pcie_clock_req) {
24791 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24792 - ar9285PciePhy_clkreq_off_L1_9285,
24793 - ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
24794 - } else {
24795 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24796 - ar9285PciePhy_clkreq_always_on_L1_9285,
24797 - ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
24798 - }
24799 - } else if (AR_SREV_9280_20_OR_LATER(ah)) {
24800 - INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
24801 - ARRAY_SIZE(ar9280Modes_9280_2), 6);
24802 - INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
24803 - ARRAY_SIZE(ar9280Common_9280_2), 2);
24804 -
24805 - if (ah->config.pcie_clock_req) {
24806 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24807 - ar9280PciePhy_clkreq_off_L1_9280,
24808 - ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
24809 - } else {
24810 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24811 - ar9280PciePhy_clkreq_always_on_L1_9280,
24812 - ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
24813 - }
24814 - INIT_INI_ARRAY(&ah->iniModesAdditional,
24815 - ar9280Modes_fast_clock_9280_2,
24816 - ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
24817 - } else if (AR_SREV_9280_10_OR_LATER(ah)) {
24818 - INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
24819 - ARRAY_SIZE(ar9280Modes_9280), 6);
24820 - INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
24821 - ARRAY_SIZE(ar9280Common_9280), 2);
24822 - } else if (AR_SREV_9160_10_OR_LATER(ah)) {
24823 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
24824 - ARRAY_SIZE(ar5416Modes_9160), 6);
24825 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
24826 - ARRAY_SIZE(ar5416Common_9160), 2);
24827 - INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
24828 - ARRAY_SIZE(ar5416Bank0_9160), 2);
24829 - INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
24830 - ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
24831 - INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
24832 - ARRAY_SIZE(ar5416Bank1_9160), 2);
24833 - INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
24834 - ARRAY_SIZE(ar5416Bank2_9160), 2);
24835 - INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
24836 - ARRAY_SIZE(ar5416Bank3_9160), 3);
24837 - INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
24838 - ARRAY_SIZE(ar5416Bank6_9160), 3);
24839 - INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
24840 - ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
24841 - INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
24842 - ARRAY_SIZE(ar5416Bank7_9160), 2);
24843 - if (AR_SREV_9160_11(ah)) {
24844 - INIT_INI_ARRAY(&ah->iniAddac,
24845 - ar5416Addac_91601_1,
24846 - ARRAY_SIZE(ar5416Addac_91601_1), 2);
24847 - } else {
24848 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
24849 - ARRAY_SIZE(ar5416Addac_9160), 2);
24850 - }
24851 - } else if (AR_SREV_9100_OR_LATER(ah)) {
24852 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
24853 - ARRAY_SIZE(ar5416Modes_9100), 6);
24854 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
24855 - ARRAY_SIZE(ar5416Common_9100), 2);
24856 - INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
24857 - ARRAY_SIZE(ar5416Bank0_9100), 2);
24858 - INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
24859 - ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
24860 - INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
24861 - ARRAY_SIZE(ar5416Bank1_9100), 2);
24862 - INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
24863 - ARRAY_SIZE(ar5416Bank2_9100), 2);
24864 - INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
24865 - ARRAY_SIZE(ar5416Bank3_9100), 3);
24866 - INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
24867 - ARRAY_SIZE(ar5416Bank6_9100), 3);
24868 - INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
24869 - ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
24870 - INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
24871 - ARRAY_SIZE(ar5416Bank7_9100), 2);
24872 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
24873 - ARRAY_SIZE(ar5416Addac_9100), 2);
24874 - } else {
24875 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
24876 - ARRAY_SIZE(ar5416Modes), 6);
24877 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
24878 - ARRAY_SIZE(ar5416Common), 2);
24879 - INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
24880 - ARRAY_SIZE(ar5416Bank0), 2);
24881 - INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
24882 - ARRAY_SIZE(ar5416BB_RfGain), 3);
24883 - INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
24884 - ARRAY_SIZE(ar5416Bank1), 2);
24885 - INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
24886 - ARRAY_SIZE(ar5416Bank2), 2);
24887 - INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
24888 - ARRAY_SIZE(ar5416Bank3), 3);
24889 - INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
24890 - ARRAY_SIZE(ar5416Bank6), 3);
24891 - INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
24892 - ARRAY_SIZE(ar5416Bank6TPC), 3);
24893 - INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
24894 - ARRAY_SIZE(ar5416Bank7), 2);
24895 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
24896 - ARRAY_SIZE(ar5416Addac), 2);
24897 - }
24898 -}
24899 -
24900 -static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
24901 +static void ath9k_hw_attach_ops(struct ath_hw *ah)
24902 {
24903 - if (AR_SREV_9287_11_OR_LATER(ah))
24904 - INIT_INI_ARRAY(&ah->iniModesRxGain,
24905 - ar9287Modes_rx_gain_9287_1_1,
24906 - ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
24907 - else if (AR_SREV_9287_10(ah))
24908 - INIT_INI_ARRAY(&ah->iniModesRxGain,
24909 - ar9287Modes_rx_gain_9287_1_0,
24910 - ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
24911 - else if (AR_SREV_9280_20(ah))
24912 - ath9k_hw_init_rxgain_ini(ah);
24913 -
24914 - if (AR_SREV_9287_11_OR_LATER(ah)) {
24915 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24916 - ar9287Modes_tx_gain_9287_1_1,
24917 - ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
24918 - } else if (AR_SREV_9287_10(ah)) {
24919 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24920 - ar9287Modes_tx_gain_9287_1_0,
24921 - ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
24922 - } else if (AR_SREV_9280_20(ah)) {
24923 - ath9k_hw_init_txgain_ini(ah);
24924 - } else if (AR_SREV_9285_12_OR_LATER(ah)) {
24925 - u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
24926 -
24927 - /* txgain table */
24928 - if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
24929 - if (AR_SREV_9285E_20(ah)) {
24930 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24931 - ar9285Modes_XE2_0_high_power,
24932 - ARRAY_SIZE(
24933 - ar9285Modes_XE2_0_high_power), 6);
24934 - } else {
24935 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24936 - ar9285Modes_high_power_tx_gain_9285_1_2,
24937 - ARRAY_SIZE(
24938 - ar9285Modes_high_power_tx_gain_9285_1_2), 6);
24939 - }
24940 - } else {
24941 - if (AR_SREV_9285E_20(ah)) {
24942 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24943 - ar9285Modes_XE2_0_normal_power,
24944 - ARRAY_SIZE(
24945 - ar9285Modes_XE2_0_normal_power), 6);
24946 - } else {
24947 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24948 - ar9285Modes_original_tx_gain_9285_1_2,
24949 - ARRAY_SIZE(
24950 - ar9285Modes_original_tx_gain_9285_1_2), 6);
24951 - }
24952 - }
24953 - }
24954 -}
24955 -
24956 -static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
24957 -{
24958 - struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
24959 - struct ath_common *common = ath9k_hw_common(ah);
24960 -
24961 - ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
24962 - (ah->eep_map != EEP_MAP_4KBITS) &&
24963 - ((pBase->version & 0xff) > 0x0a) &&
24964 - (pBase->pwdclkind == 0);
24965 -
24966 - if (ah->need_an_top2_fixup)
24967 - ath_print(common, ATH_DBG_EEPROM,
24968 - "needs fixup for AR_AN_TOP2 register\n");
24969 + if (AR_SREV_9300_20_OR_LATER(ah))
24970 + ar9003_hw_attach_ops(ah);
24971 + else
24972 + ar9002_hw_attach_ops(ah);
24973 }
24974
24975 -int ath9k_hw_init(struct ath_hw *ah)
24976 +/* Called for all hardware families */
24977 +static int __ath9k_hw_init(struct ath_hw *ah)
24978 {
24979 struct ath_common *common = ath9k_hw_common(ah);
24980 int r = 0;
24981
24982 - if (common->bus_ops->ath_bus_type != ATH_USB) {
24983 - if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
24984 - ath_print(common, ATH_DBG_FATAL,
24985 - "Unsupported device ID: 0x%0x\n",
24986 - ah->hw_version.devid);
24987 - return -EOPNOTSUPP;
24988 - }
24989 - }
24990 -
24991 - ath9k_hw_init_defaults(ah);
24992 - ath9k_hw_init_config(ah);
24993 -
24994 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
24995 ath_print(common, ATH_DBG_FATAL,
24996 "Couldn't reset chip\n");
24997 return -EIO;
24998 }
24999
25000 + ath9k_hw_init_defaults(ah);
25001 + ath9k_hw_init_config(ah);
25002 +
25003 + ath9k_hw_attach_ops(ah);
25004 +
25005 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
25006 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
25007 return -EIO;
25008 @@ -901,7 +529,7 @@ int ath9k_hw_init(struct ath_hw *ah)
25009 else
25010 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
25011
25012 - if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
25013 + if (!ath9k_hw_macversion_supported(ah)) {
25014 ath_print(common, ATH_DBG_FATAL,
25015 "Mac Chip Rev 0x%02x.%x is not supported by "
25016 "this driver\n", ah->hw_version.macVersion,
25017 @@ -909,28 +537,15 @@ int ath9k_hw_init(struct ath_hw *ah)
25018 return -EOPNOTSUPP;
25019 }
25020
25021 - if (AR_SREV_9100(ah)) {
25022 - ah->iq_caldata.calData = &iq_cal_multi_sample;
25023 - ah->supp_cals = IQ_MISMATCH_CAL;
25024 - ah->is_pciexpress = false;
25025 - }
25026 -
25027 - if (AR_SREV_9271(ah))
25028 + if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
25029 ah->is_pciexpress = false;
25030
25031 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
25032 -
25033 ath9k_hw_init_cal_settings(ah);
25034
25035 ah->ani_function = ATH9K_ANI_ALL;
25036 - if (AR_SREV_9280_10_OR_LATER(ah)) {
25037 + if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
25038 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
25039 - ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
25040 - ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
25041 - } else {
25042 - ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
25043 - ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
25044 - }
25045
25046 ath9k_hw_init_mode_regs(ah);
25047
25048 @@ -939,15 +554,8 @@ int ath9k_hw_init(struct ath_hw *ah)
25049 else
25050 ath9k_hw_disablepcie(ah);
25051
25052 - /* Support for Japan ch.14 (2484) spread */
25053 - if (AR_SREV_9287_11_OR_LATER(ah)) {
25054 - INIT_INI_ARRAY(&ah->iniCckfirNormal,
25055 - ar9287Common_normal_cck_fir_coeff_92871_1,
25056 - ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
25057 - INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
25058 - ar9287Common_japan_2484_cck_fir_coeff_92871_1,
25059 - ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
25060 - }
25061 + if (!AR_SREV_9300_20_OR_LATER(ah))
25062 + ar9002_hw_cck_chan14_spread(ah);
25063
25064 r = ath9k_hw_post_init(ah);
25065 if (r)
25066 @@ -958,8 +566,6 @@ int ath9k_hw_init(struct ath_hw *ah)
25067 if (r)
25068 return r;
25069
25070 - ath9k_hw_init_eeprom_fix(ah);
25071 -
25072 r = ath9k_hw_init_macaddr(ah);
25073 if (r) {
25074 ath_print(common, ATH_DBG_FATAL,
25075 @@ -972,6 +578,9 @@ int ath9k_hw_init(struct ath_hw *ah)
25076 else
25077 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
25078
25079 + if (AR_SREV_9300_20_OR_LATER(ah))
25080 + ar9003_hw_set_nf_limits(ah);
25081 +
25082 ath9k_init_nfcal_hist_buffer(ah);
25083
25084 common->state = ATH_HW_INITIALIZED;
25085 @@ -979,21 +588,45 @@ int ath9k_hw_init(struct ath_hw *ah)
25086 return 0;
25087 }
25088
25089 -static void ath9k_hw_init_bb(struct ath_hw *ah,
25090 - struct ath9k_channel *chan)
25091 +int ath9k_hw_init(struct ath_hw *ah)
25092 {
25093 - u32 synthDelay;
25094 + int ret;
25095 + struct ath_common *common = ath9k_hw_common(ah);
25096
25097 - synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
25098 - if (IS_CHAN_B(chan))
25099 - synthDelay = (4 * synthDelay) / 22;
25100 - else
25101 - synthDelay /= 10;
25102 + /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
25103 + switch (ah->hw_version.devid) {
25104 + case AR5416_DEVID_PCI:
25105 + case AR5416_DEVID_PCIE:
25106 + case AR5416_AR9100_DEVID:
25107 + case AR9160_DEVID_PCI:
25108 + case AR9280_DEVID_PCI:
25109 + case AR9280_DEVID_PCIE:
25110 + case AR9285_DEVID_PCIE:
25111 + case AR9287_DEVID_PCI:
25112 + case AR9287_DEVID_PCIE:
25113 + case AR2427_DEVID_PCIE:
25114 + case AR9300_DEVID_PCIE:
25115 + break;
25116 + default:
25117 + if (common->bus_ops->ath_bus_type == ATH_USB)
25118 + break;
25119 + ath_print(common, ATH_DBG_FATAL,
25120 + "Hardware device ID 0x%04x not supported\n",
25121 + ah->hw_version.devid);
25122 + return -EOPNOTSUPP;
25123 + }
25124
25125 - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
25126 + ret = __ath9k_hw_init(ah);
25127 + if (ret) {
25128 + ath_print(common, ATH_DBG_FATAL,
25129 + "Unable to initialize hardware; "
25130 + "initialization status: %d\n", ret);
25131 + return ret;
25132 + }
25133
25134 - udelay(synthDelay + BASE_ACTIVATE_DELAY);
25135 + return 0;
25136 }
25137 +EXPORT_SYMBOL(ath9k_hw_init);
25138
25139 static void ath9k_hw_init_qos(struct ath_hw *ah)
25140 {
25141 @@ -1015,64 +648,8 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
25142 static void ath9k_hw_init_pll(struct ath_hw *ah,
25143 struct ath9k_channel *chan)
25144 {
25145 - u32 pll;
25146 -
25147 - if (AR_SREV_9100(ah)) {
25148 - if (chan && IS_CHAN_5GHZ(chan))
25149 - pll = 0x1450;
25150 - else
25151 - pll = 0x1458;
25152 - } else {
25153 - if (AR_SREV_9280_10_OR_LATER(ah)) {
25154 - pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
25155 -
25156 - if (chan && IS_CHAN_HALF_RATE(chan))
25157 - pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
25158 - else if (chan && IS_CHAN_QUARTER_RATE(chan))
25159 - pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
25160 -
25161 - if (chan && IS_CHAN_5GHZ(chan)) {
25162 - pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
25163 -
25164 -
25165 - if (AR_SREV_9280_20(ah)) {
25166 - if (((chan->channel % 20) == 0)
25167 - || ((chan->channel % 10) == 0))
25168 - pll = 0x2850;
25169 - else
25170 - pll = 0x142c;
25171 - }
25172 - } else {
25173 - pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
25174 - }
25175 -
25176 - } else if (AR_SREV_9160_10_OR_LATER(ah)) {
25177 -
25178 - pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
25179 + u32 pll = ath9k_hw_compute_pll_control(ah, chan);
25180
25181 - if (chan && IS_CHAN_HALF_RATE(chan))
25182 - pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
25183 - else if (chan && IS_CHAN_QUARTER_RATE(chan))
25184 - pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
25185 -
25186 - if (chan && IS_CHAN_5GHZ(chan))
25187 - pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
25188 - else
25189 - pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
25190 - } else {
25191 - pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
25192 -
25193 - if (chan && IS_CHAN_HALF_RATE(chan))
25194 - pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
25195 - else if (chan && IS_CHAN_QUARTER_RATE(chan))
25196 - pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
25197 -
25198 - if (chan && IS_CHAN_5GHZ(chan))
25199 - pll |= SM(0xa, AR_RTC_PLL_DIV);
25200 - else
25201 - pll |= SM(0xb, AR_RTC_PLL_DIV);
25202 - }
25203 - }
25204 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
25205
25206 /* Switch the core clock for ar9271 to 117Mhz */
25207 @@ -1086,43 +663,6 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
25208 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
25209 }
25210
25211 -static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
25212 -{
25213 - int rx_chainmask, tx_chainmask;
25214 -
25215 - rx_chainmask = ah->rxchainmask;
25216 - tx_chainmask = ah->txchainmask;
25217 -
25218 - switch (rx_chainmask) {
25219 - case 0x5:
25220 - REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
25221 - AR_PHY_SWAP_ALT_CHAIN);
25222 - case 0x3:
25223 - if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
25224 - REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
25225 - REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
25226 - break;
25227 - }
25228 - case 0x1:
25229 - case 0x2:
25230 - case 0x7:
25231 - REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
25232 - REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
25233 - break;
25234 - default:
25235 - break;
25236 - }
25237 -
25238 - REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
25239 - if (tx_chainmask == 0x5) {
25240 - REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
25241 - AR_PHY_SWAP_ALT_CHAIN);
25242 - }
25243 - if (AR_SREV_9100(ah))
25244 - REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
25245 - REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
25246 -}
25247 -
25248 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
25249 enum nl80211_iftype opmode)
25250 {
25251 @@ -1132,12 +672,24 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
25252 AR_IMR_RXORN |
25253 AR_IMR_BCNMISC;
25254
25255 - if (ah->config.rx_intr_mitigation)
25256 - imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
25257 - else
25258 - imr_reg |= AR_IMR_RXOK;
25259 + if (AR_SREV_9300_20_OR_LATER(ah)) {
25260 + imr_reg |= AR_IMR_RXOK_HP;
25261 + if (ah->config.rx_intr_mitigation)
25262 + imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
25263 + else
25264 + imr_reg |= AR_IMR_RXOK_LP;
25265 +
25266 + } else {
25267 + if (ah->config.rx_intr_mitigation)
25268 + imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
25269 + else
25270 + imr_reg |= AR_IMR_RXOK;
25271 + }
25272
25273 - imr_reg |= AR_IMR_TXOK;
25274 + if (ah->config.tx_intr_mitigation)
25275 + imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
25276 + else
25277 + imr_reg |= AR_IMR_TXOK;
25278
25279 if (opmode == NL80211_IFTYPE_AP)
25280 imr_reg |= AR_IMR_MIB;
25281 @@ -1151,6 +703,13 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
25282 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
25283 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
25284 }
25285 +
25286 + if (AR_SREV_9300_20_OR_LATER(ah)) {
25287 + REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
25288 + REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
25289 + REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
25290 + REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
25291 + }
25292 }
25293
25294 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
25295 @@ -1242,8 +801,7 @@ void ath9k_hw_deinit(struct ath_hw *ah)
25296 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
25297
25298 free_hw:
25299 - if (!AR_SREV_9280_10_OR_LATER(ah))
25300 - ath9k_hw_rf_free_ext_banks(ah);
25301 + ath9k_hw_rf_free_ext_banks(ah);
25302 }
25303 EXPORT_SYMBOL(ath9k_hw_deinit);
25304
25305 @@ -1251,73 +809,7 @@ EXPORT_SYMBOL(ath9k_hw_deinit);
25306 /* INI */
25307 /*******/
25308
25309 -static void ath9k_hw_override_ini(struct ath_hw *ah,
25310 - struct ath9k_channel *chan)
25311 -{
25312 - u32 val;
25313 -
25314 - /*
25315 - * Set the RX_ABORT and RX_DIS and clear if off only after
25316 - * RXE is set for MAC. This prevents frames with corrupted
25317 - * descriptor status.
25318 - */
25319 - REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
25320 -
25321 - if (AR_SREV_9280_10_OR_LATER(ah)) {
25322 - val = REG_READ(ah, AR_PCU_MISC_MODE2);
25323 -
25324 - if (!AR_SREV_9271(ah))
25325 - val &= ~AR_PCU_MISC_MODE2_HWWAR1;
25326 -
25327 - if (AR_SREV_9287_10_OR_LATER(ah))
25328 - val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
25329 -
25330 - REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
25331 - }
25332 -
25333 - if (!AR_SREV_5416_20_OR_LATER(ah) ||
25334 - AR_SREV_9280_10_OR_LATER(ah))
25335 - return;
25336 - /*
25337 - * Disable BB clock gating
25338 - * Necessary to avoid issues on AR5416 2.0
25339 - */
25340 - REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
25341 -
25342 - /*
25343 - * Disable RIFS search on some chips to avoid baseband
25344 - * hang issues.
25345 - */
25346 - if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
25347 - val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
25348 - val &= ~AR_PHY_RIFS_INIT_DELAY;
25349 - REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
25350 - }
25351 -}
25352 -
25353 -static void ath9k_olc_init(struct ath_hw *ah)
25354 -{
25355 - u32 i;
25356 -
25357 - if (OLC_FOR_AR9287_10_LATER) {
25358 - REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
25359 - AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
25360 - ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
25361 - AR9287_AN_TXPC0_TXPCMODE,
25362 - AR9287_AN_TXPC0_TXPCMODE_S,
25363 - AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
25364 - udelay(100);
25365 - } else {
25366 - for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
25367 - ah->originalGain[i] =
25368 - MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
25369 - AR_PHY_TX_GAIN);
25370 - ah->PDADCdelta = 0;
25371 - }
25372 -}
25373 -
25374 -static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
25375 - struct ath9k_channel *chan)
25376 +u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
25377 {
25378 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
25379
25380 @@ -1331,193 +823,22 @@ static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
25381 return ctl;
25382 }
25383
25384 -static int ath9k_hw_process_ini(struct ath_hw *ah,
25385 - struct ath9k_channel *chan)
25386 -{
25387 - struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
25388 - int i, regWrites = 0;
25389 - struct ieee80211_channel *channel = chan->chan;
25390 - u32 modesIndex, freqIndex;
25391 -
25392 - switch (chan->chanmode) {
25393 - case CHANNEL_A:
25394 - case CHANNEL_A_HT20:
25395 - modesIndex = 1;
25396 - freqIndex = 1;
25397 - break;
25398 - case CHANNEL_A_HT40PLUS:
25399 - case CHANNEL_A_HT40MINUS:
25400 - modesIndex = 2;
25401 - freqIndex = 1;
25402 - break;
25403 - case CHANNEL_G:
25404 - case CHANNEL_G_HT20:
25405 - case CHANNEL_B:
25406 - modesIndex = 4;
25407 - freqIndex = 2;
25408 - break;
25409 - case CHANNEL_G_HT40PLUS:
25410 - case CHANNEL_G_HT40MINUS:
25411 - modesIndex = 3;
25412 - freqIndex = 2;
25413 - break;
25414 -
25415 - default:
25416 - return -EINVAL;
25417 - }
25418 -
25419 - /* Set correct baseband to analog shift setting to access analog chips */
25420 - REG_WRITE(ah, AR_PHY(0), 0x00000007);
25421 -
25422 - /* Write ADDAC shifts */
25423 - REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
25424 - ah->eep_ops->set_addac(ah, chan);
25425 -
25426 - if (AR_SREV_5416_22_OR_LATER(ah)) {
25427 - REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
25428 - } else {
25429 - struct ar5416IniArray temp;
25430 - u32 addacSize =
25431 - sizeof(u32) * ah->iniAddac.ia_rows *
25432 - ah->iniAddac.ia_columns;
25433 -
25434 - /* For AR5416 2.0/2.1 */
25435 - memcpy(ah->addac5416_21,
25436 - ah->iniAddac.ia_array, addacSize);
25437 -
25438 - /* override CLKDRV value at [row, column] = [31, 1] */
25439 - (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
25440 -
25441 - temp.ia_array = ah->addac5416_21;
25442 - temp.ia_columns = ah->iniAddac.ia_columns;
25443 - temp.ia_rows = ah->iniAddac.ia_rows;
25444 - REG_WRITE_ARRAY(&temp, 1, regWrites);
25445 - }
25446 -
25447 - REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
25448 -
25449 - for (i = 0; i < ah->iniModes.ia_rows; i++) {
25450 - u32 reg = INI_RA(&ah->iniModes, i, 0);
25451 - u32 val = INI_RA(&ah->iniModes, i, modesIndex);
25452 -
25453 - if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
25454 - val &= ~AR_AN_TOP2_PWDCLKIND;
25455 -
25456 - REG_WRITE(ah, reg, val);
25457 -
25458 - if (reg >= 0x7800 && reg < 0x78a0
25459 - && ah->config.analog_shiftreg) {
25460 - udelay(100);
25461 - }
25462 -
25463 - DO_DELAY(regWrites);
25464 - }
25465 -
25466 - if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
25467 - REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
25468 -
25469 - if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
25470 - AR_SREV_9287_10_OR_LATER(ah))
25471 - REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
25472 -
25473 - if (AR_SREV_9271_10(ah))
25474 - REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
25475 - modesIndex, regWrites);
25476 -
25477 - /* Write common array parameters */
25478 - for (i = 0; i < ah->iniCommon.ia_rows; i++) {
25479 - u32 reg = INI_RA(&ah->iniCommon, i, 0);
25480 - u32 val = INI_RA(&ah->iniCommon, i, 1);
25481 -
25482 - REG_WRITE(ah, reg, val);
25483 -
25484 - if (reg >= 0x7800 && reg < 0x78a0
25485 - && ah->config.analog_shiftreg) {
25486 - udelay(100);
25487 - }
25488 -
25489 - DO_DELAY(regWrites);
25490 - }
25491 -
25492 - if (AR_SREV_9271(ah)) {
25493 - if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
25494 - REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
25495 - modesIndex, regWrites);
25496 - else
25497 - REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
25498 - modesIndex, regWrites);
25499 - }
25500 -
25501 - ath9k_hw_write_regs(ah, freqIndex, regWrites);
25502 -
25503 - if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
25504 - REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
25505 - regWrites);
25506 - }
25507 -
25508 - ath9k_hw_override_ini(ah, chan);
25509 - ath9k_hw_set_regs(ah, chan);
25510 - ath9k_hw_init_chain_masks(ah);
25511 -
25512 - if (OLC_FOR_AR9280_20_LATER)
25513 - ath9k_olc_init(ah);
25514 -
25515 - /* Set TX power */
25516 - ah->eep_ops->set_txpower(ah, chan,
25517 - ath9k_regd_get_ctl(regulatory, chan),
25518 - channel->max_antenna_gain * 2,
25519 - channel->max_power * 2,
25520 - min((u32) MAX_RATE_POWER,
25521 - (u32) regulatory->power_limit));
25522 -
25523 - /* Write analog registers */
25524 - if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
25525 - ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
25526 - "ar5416SetRfRegs failed\n");
25527 - return -EIO;
25528 - }
25529 -
25530 - return 0;
25531 -}
25532 -
25533 /****************************************/
25534 /* Reset and Channel Switching Routines */
25535 /****************************************/
25536
25537 -static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
25538 -{
25539 - u32 rfMode = 0;
25540 -
25541 - if (chan == NULL)
25542 - return;
25543 -
25544 - rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
25545 - ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
25546 -
25547 - if (!AR_SREV_9280_10_OR_LATER(ah))
25548 - rfMode |= (IS_CHAN_5GHZ(chan)) ?
25549 - AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
25550 -
25551 - if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
25552 - rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
25553 -
25554 - REG_WRITE(ah, AR_PHY_MODE, rfMode);
25555 -}
25556 -
25557 -static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
25558 -{
25559 - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
25560 -}
25561 -
25562 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
25563 {
25564 + struct ath_common *common = ath9k_hw_common(ah);
25565 u32 regval;
25566
25567 /*
25568 * set AHB_MODE not to do cacheline prefetches
25569 */
25570 - regval = REG_READ(ah, AR_AHB_MODE);
25571 - REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
25572 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
25573 + regval = REG_READ(ah, AR_AHB_MODE);
25574 + REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
25575 + }
25576
25577 /*
25578 * let mac dma reads be in 128 byte chunks
25579 @@ -1530,7 +851,8 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
25580 * The initial value depends on whether aggregation is enabled, and is
25581 * adjusted whenever underruns are detected.
25582 */
25583 - REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
25584 + if (!AR_SREV_9300_20_OR_LATER(ah))
25585 + REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
25586
25587 /*
25588 * let mac dma writes be in 128 byte chunks
25589 @@ -1543,6 +865,14 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
25590 */
25591 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
25592
25593 + if (AR_SREV_9300_20_OR_LATER(ah)) {
25594 + REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
25595 + REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
25596 +
25597 + ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
25598 + ah->caps.rx_status_len);
25599 + }
25600 +
25601 /*
25602 * reduce the number of usable entries in PCU TXBUF to avoid
25603 * wrap around issues.
25604 @@ -1558,6 +888,9 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
25605 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
25606 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
25607 }
25608 +
25609 + if (AR_SREV_9300_20_OR_LATER(ah))
25610 + ath9k_hw_reset_txstatus_ring(ah);
25611 }
25612
25613 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
25614 @@ -1585,10 +918,8 @@ static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
25615 }
25616 }
25617
25618 -static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
25619 - u32 coef_scaled,
25620 - u32 *coef_mantissa,
25621 - u32 *coef_exponent)
25622 +void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
25623 + u32 *coef_mantissa, u32 *coef_exponent)
25624 {
25625 u32 coef_exp, coef_man;
25626
25627 @@ -1604,40 +935,6 @@ static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
25628 *coef_exponent = coef_exp - 16;
25629 }
25630
25631 -static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
25632 - struct ath9k_channel *chan)
25633 -{
25634 - u32 coef_scaled, ds_coef_exp, ds_coef_man;
25635 - u32 clockMhzScaled = 0x64000000;
25636 - struct chan_centers centers;
25637 -
25638 - if (IS_CHAN_HALF_RATE(chan))
25639 - clockMhzScaled = clockMhzScaled >> 1;
25640 - else if (IS_CHAN_QUARTER_RATE(chan))
25641 - clockMhzScaled = clockMhzScaled >> 2;
25642 -
25643 - ath9k_hw_get_channel_centers(ah, chan, &centers);
25644 - coef_scaled = clockMhzScaled / centers.synth_center;
25645 -
25646 - ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
25647 - &ds_coef_exp);
25648 -
25649 - REG_RMW_FIELD(ah, AR_PHY_TIMING3,
25650 - AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
25651 - REG_RMW_FIELD(ah, AR_PHY_TIMING3,
25652 - AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
25653 -
25654 - coef_scaled = (9 * coef_scaled) / 10;
25655 -
25656 - ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
25657 - &ds_coef_exp);
25658 -
25659 - REG_RMW_FIELD(ah, AR_PHY_HALFGI,
25660 - AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
25661 - REG_RMW_FIELD(ah, AR_PHY_HALFGI,
25662 - AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
25663 -}
25664 -
25665 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
25666 {
25667 u32 rst_flags;
25668 @@ -1658,15 +955,21 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
25669 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
25670 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
25671 } else {
25672 +
25673 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
25674 if (tmpReg &
25675 (AR_INTR_SYNC_LOCAL_TIMEOUT |
25676 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
25677 + u32 val;
25678 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
25679 - REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
25680 - } else {
25681 +
25682 + val = AR_RC_HOSTIF;
25683 + if (!AR_SREV_9300_20_OR_LATER(ah))
25684 + val |= AR_RC_AHB;
25685 + REG_WRITE(ah, AR_RC, val);
25686 +
25687 + } else if (!AR_SREV_9300_20_OR_LATER(ah))
25688 REG_WRITE(ah, AR_RC, AR_RC_AHB);
25689 - }
25690
25691 rst_flags = AR_RTC_RC_MAC_WARM;
25692 if (type == ATH9K_RESET_COLD)
25693 @@ -1697,13 +1000,15 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
25694 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
25695 AR_RTC_FORCE_WAKE_ON_INT);
25696
25697 - if (!AR_SREV_9100(ah))
25698 + if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
25699 REG_WRITE(ah, AR_RC, AR_RC_AHB);
25700
25701 REG_WRITE(ah, AR_RTC_RESET, 0);
25702 - udelay(2);
25703
25704 - if (!AR_SREV_9100(ah))
25705 + if (!AR_SREV_9300_20_OR_LATER(ah))
25706 + udelay(2);
25707 +
25708 + if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
25709 REG_WRITE(ah, AR_RC, 0);
25710
25711 REG_WRITE(ah, AR_RTC_RESET, 1);
25712 @@ -1739,34 +1044,6 @@ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
25713 }
25714 }
25715
25716 -static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
25717 -{
25718 - u32 phymode;
25719 - u32 enableDacFifo = 0;
25720 -
25721 - if (AR_SREV_9285_10_OR_LATER(ah))
25722 - enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
25723 - AR_PHY_FC_ENABLE_DAC_FIFO);
25724 -
25725 - phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
25726 - | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
25727 -
25728 - if (IS_CHAN_HT40(chan)) {
25729 - phymode |= AR_PHY_FC_DYN2040_EN;
25730 -
25731 - if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
25732 - (chan->chanmode == CHANNEL_G_HT40PLUS))
25733 - phymode |= AR_PHY_FC_DYN2040_PRI_CH;
25734 -
25735 - }
25736 - REG_WRITE(ah, AR_PHY_TURBO, phymode);
25737 -
25738 - ath9k_hw_set11nmac2040(ah);
25739 -
25740 - REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
25741 - REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
25742 -}
25743 -
25744 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
25745 struct ath9k_channel *chan)
25746 {
25747 @@ -1792,7 +1069,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
25748 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
25749 struct ath_common *common = ath9k_hw_common(ah);
25750 struct ieee80211_channel *channel = chan->chan;
25751 - u32 synthDelay, qnum;
25752 + u32 qnum;
25753 int r;
25754
25755 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
25756 @@ -1804,17 +1081,15 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
25757 }
25758 }
25759
25760 - REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
25761 - if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
25762 - AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
25763 + if (!ath9k_hw_rfbus_req(ah)) {
25764 ath_print(common, ATH_DBG_FATAL,
25765 "Could not kill baseband RX\n");
25766 return false;
25767 }
25768
25769 - ath9k_hw_set_regs(ah, chan);
25770 + ath9k_hw_set_channel_regs(ah, chan);
25771
25772 - r = ah->ath9k_hw_rf_set_freq(ah, chan);
25773 + r = ath9k_hw_rf_set_freq(ah, chan);
25774 if (r) {
25775 ath_print(common, ATH_DBG_FATAL,
25776 "Failed to set channel\n");
25777 @@ -1828,20 +1103,12 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
25778 min((u32) MAX_RATE_POWER,
25779 (u32) regulatory->power_limit));
25780
25781 - synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
25782 - if (IS_CHAN_B(chan))
25783 - synthDelay = (4 * synthDelay) / 22;
25784 - else
25785 - synthDelay /= 10;
25786 -
25787 - udelay(synthDelay + BASE_ACTIVATE_DELAY);
25788 -
25789 - REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
25790 + ath9k_hw_rfbus_done(ah);
25791
25792 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
25793 ath9k_hw_set_delta_slope(ah, chan);
25794
25795 - ah->ath9k_hw_spur_mitigate_freq(ah, chan);
25796 + ath9k_hw_spur_mitigate_freq(ah, chan);
25797
25798 if (!chan->oneTimeCalsDone)
25799 chan->oneTimeCalsDone = true;
25800 @@ -1849,18 +1116,6 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
25801 return true;
25802 }
25803
25804 -static void ath9k_enable_rfkill(struct ath_hw *ah)
25805 -{
25806 - REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
25807 - AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
25808 -
25809 - REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
25810 - AR_GPIO_INPUT_MUX2_RFSILENT);
25811 -
25812 - ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
25813 - REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
25814 -}
25815 -
25816 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
25817 bool bChannelChange)
25818 {
25819 @@ -1870,11 +1125,18 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
25820 u32 saveDefAntenna;
25821 u32 macStaId1;
25822 u64 tsf = 0;
25823 - int i, rx_chainmask, r;
25824 + int i, r;
25825
25826 ah->txchainmask = common->tx_chainmask;
25827 ah->rxchainmask = common->rx_chainmask;
25828
25829 + if (!ah->chip_fullsleep) {
25830 + ath9k_hw_abortpcurecv(ah);
25831 + if (!ath9k_hw_stopdmarecv(ah))
25832 + ath_print(common, ATH_DBG_XMIT,
25833 + "Failed to stop receive dma\n");
25834 + }
25835 +
25836 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
25837 return -EIO;
25838
25839 @@ -1939,19 +1201,14 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
25840 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
25841 ath9k_hw_settsf64(ah, tsf);
25842
25843 + if (AR_SREV_9300_20_OR_LATER(ah))
25844 + ar9003_hw_attach_mac_ops(ah);
25845 + else
25846 + ar9002_hw_attach_mac_ops(ah);
25847 +
25848 if (AR_SREV_9280_10_OR_LATER(ah))
25849 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
25850
25851 - if (AR_SREV_9287_12_OR_LATER(ah)) {
25852 - /* Enable ASYNC FIFO */
25853 - REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
25854 - AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
25855 - REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
25856 - REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
25857 - AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
25858 - REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
25859 - AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
25860 - }
25861 r = ath9k_hw_process_ini(ah, chan);
25862 if (r)
25863 return r;
25864 @@ -1976,7 +1233,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
25865 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
25866 ath9k_hw_set_delta_slope(ah, chan);
25867
25868 - ah->ath9k_hw_spur_mitigate_freq(ah, chan);
25869 + ath9k_hw_spur_mitigate_freq(ah, chan);
25870 ah->eep_ops->set_board_values(ah, chan);
25871
25872 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
25873 @@ -1998,7 +1255,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
25874
25875 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
25876
25877 - r = ah->ath9k_hw_rf_set_freq(ah, chan);
25878 + r = ath9k_hw_rf_set_freq(ah, chan);
25879 if (r)
25880 return r;
25881
25882 @@ -2017,25 +1274,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
25883
25884 ath9k_hw_init_global_settings(ah);
25885
25886 - if (AR_SREV_9287_12_OR_LATER(ah)) {
25887 - REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
25888 - AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
25889 - REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
25890 - AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
25891 - REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
25892 - AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
25893 -
25894 - REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
25895 - REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
25896 -
25897 - REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
25898 - AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
25899 - REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
25900 - AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
25901 - }
25902 - if (AR_SREV_9287_12_OR_LATER(ah)) {
25903 - REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
25904 - AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
25905 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
25906 + ar9002_hw_enable_async_fifo(ah);
25907 + ar9002_hw_enable_wep_aggregation(ah);
25908 }
25909
25910 REG_WRITE(ah, AR_STA_ID1,
25911 @@ -2050,17 +1291,17 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
25912 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
25913 }
25914
25915 + if (ah->config.tx_intr_mitigation) {
25916 + REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
25917 + REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
25918 + }
25919 +
25920 ath9k_hw_init_bb(ah, chan);
25921
25922 if (!ath9k_hw_init_cal(ah, chan))
25923 return -EIO;
25924
25925 - rx_chainmask = ah->rxchainmask;
25926 - if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
25927 - REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
25928 - REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
25929 - }
25930 -
25931 + ath9k_hw_restore_chainmask(ah);
25932 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
25933
25934 /*
25935 @@ -2092,6 +1333,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
25936 if (ah->btcoex_hw.enabled)
25937 ath9k_hw_btcoex_enable(ah);
25938
25939 + if (AR_SREV_9300_20_OR_LATER(ah)) {
25940 + ath9k_hw_loadnf(ah, curchan);
25941 + ath9k_hw_start_nfcal(ah);
25942 + }
25943 +
25944 return 0;
25945 }
25946 EXPORT_SYMBOL(ath9k_hw_reset);
25947 @@ -2378,21 +1624,31 @@ EXPORT_SYMBOL(ath9k_hw_keyisvalid);
25948 /* Power Management (Chipset) */
25949 /******************************/
25950
25951 +/*
25952 + * Notify Power Mgt is disabled in self-generated frames.
25953 + * If requested, force chip to sleep.
25954 + */
25955 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
25956 {
25957 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
25958 if (setChip) {
25959 + /* Clear the RTC force wake bit to allow the mac to go to sleep */
25960 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
25961 AR_RTC_FORCE_WAKE_EN);
25962 - if (!AR_SREV_9100(ah))
25963 + if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
25964 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
25965 -
25966 + /* Shutdown chip. Active low */
25967 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
25968 REG_CLR_BIT(ah, (AR_RTC_RESET),
25969 AR_RTC_RESET_EN);
25970 }
25971 }
25972
25973 +/*
25974 + * Notify Power Management is enabled in self-generating
25975 + * frames. If request, set power mode of chip to
25976 + * auto/normal. Duration in units of 128us (1/8 TU).
25977 + */
25978 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
25979 {
25980 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
25981 @@ -2400,9 +1656,14 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
25982 struct ath9k_hw_capabilities *pCap = &ah->caps;
25983
25984 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
25985 + /* Set WakeOnInterrupt bit; clear ForceWake bit */
25986 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
25987 AR_RTC_FORCE_WAKE_ON_INT);
25988 } else {
25989 + /*
25990 + * Clear the RTC force wake bit to allow the
25991 + * mac to go to sleep.
25992 + */
25993 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
25994 AR_RTC_FORCE_WAKE_EN);
25995 }
25996 @@ -2421,7 +1682,8 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
25997 ATH9K_RESET_POWER_ON) != true) {
25998 return false;
25999 }
26000 - ath9k_hw_init_pll(ah, NULL);
26001 + if (!AR_SREV_9300_20_OR_LATER(ah))
26002 + ath9k_hw_init_pll(ah, NULL);
26003 }
26004 if (AR_SREV_9100(ah))
26005 REG_SET_BIT(ah, AR_RTC_RESET,
26006 @@ -2491,420 +1753,6 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
26007 }
26008 EXPORT_SYMBOL(ath9k_hw_setpower);
26009
26010 -/*
26011 - * Helper for ASPM support.
26012 - *
26013 - * Disable PLL when in L0s as well as receiver clock when in L1.
26014 - * This power saving option must be enabled through the SerDes.
26015 - *
26016 - * Programming the SerDes must go through the same 288 bit serial shift
26017 - * register as the other analog registers. Hence the 9 writes.
26018 - */
26019 -void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
26020 -{
26021 - u8 i;
26022 - u32 val;
26023 -
26024 - if (ah->is_pciexpress != true)
26025 - return;
26026 -
26027 - /* Do not touch SerDes registers */
26028 - if (ah->config.pcie_powersave_enable == 2)
26029 - return;
26030 -
26031 - /* Nothing to do on restore for 11N */
26032 - if (!restore) {
26033 - if (AR_SREV_9280_20_OR_LATER(ah)) {
26034 - /*
26035 - * AR9280 2.0 or later chips use SerDes values from the
26036 - * initvals.h initialized depending on chipset during
26037 - * ath9k_hw_init()
26038 - */
26039 - for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
26040 - REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
26041 - INI_RA(&ah->iniPcieSerdes, i, 1));
26042 - }
26043 - } else if (AR_SREV_9280(ah) &&
26044 - (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
26045 - REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
26046 - REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
26047 -
26048 - /* RX shut off when elecidle is asserted */
26049 - REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
26050 - REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
26051 - REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
26052 -
26053 - /* Shut off CLKREQ active in L1 */
26054 - if (ah->config.pcie_clock_req)
26055 - REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
26056 - else
26057 - REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
26058 -
26059 - REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
26060 - REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
26061 - REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
26062 -
26063 - /* Load the new settings */
26064 - REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
26065 -
26066 - } else {
26067 - REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
26068 - REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
26069 -
26070 - /* RX shut off when elecidle is asserted */
26071 - REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
26072 - REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
26073 - REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
26074 -
26075 - /*
26076 - * Ignore ah->ah_config.pcie_clock_req setting for
26077 - * pre-AR9280 11n
26078 - */
26079 - REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
26080 -
26081 - REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
26082 - REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
26083 - REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
26084 -
26085 - /* Load the new settings */
26086 - REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
26087 - }
26088 -
26089 - udelay(1000);
26090 -
26091 - /* set bit 19 to allow forcing of pcie core into L1 state */
26092 - REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
26093 -
26094 - /* Several PCIe massages to ensure proper behaviour */
26095 - if (ah->config.pcie_waen) {
26096 - val = ah->config.pcie_waen;
26097 - if (!power_off)
26098 - val &= (~AR_WA_D3_L1_DISABLE);
26099 - } else {
26100 - if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
26101 - AR_SREV_9287(ah)) {
26102 - val = AR9285_WA_DEFAULT;
26103 - if (!power_off)
26104 - val &= (~AR_WA_D3_L1_DISABLE);
26105 - } else if (AR_SREV_9280(ah)) {
26106 - /*
26107 - * On AR9280 chips bit 22 of 0x4004 needs to be
26108 - * set otherwise card may disappear.
26109 - */
26110 - val = AR9280_WA_DEFAULT;
26111 - if (!power_off)
26112 - val &= (~AR_WA_D3_L1_DISABLE);
26113 - } else
26114 - val = AR_WA_DEFAULT;
26115 - }
26116 -
26117 - REG_WRITE(ah, AR_WA, val);
26118 - }
26119 -
26120 - if (power_off) {
26121 - /*
26122 - * Set PCIe workaround bits
26123 - * bit 14 in WA register (disable L1) should only
26124 - * be set when device enters D3 and be cleared
26125 - * when device comes back to D0.
26126 - */
26127 - if (ah->config.pcie_waen) {
26128 - if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
26129 - REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
26130 - } else {
26131 - if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
26132 - AR_SREV_9287(ah)) &&
26133 - (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
26134 - (AR_SREV_9280(ah) &&
26135 - (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
26136 - REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
26137 - }
26138 - }
26139 - }
26140 -}
26141 -EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
26142 -
26143 -/**********************/
26144 -/* Interrupt Handling */
26145 -/**********************/
26146 -
26147 -bool ath9k_hw_intrpend(struct ath_hw *ah)
26148 -{
26149 - u32 host_isr;
26150 -
26151 - if (AR_SREV_9100(ah))
26152 - return true;
26153 -
26154 - host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
26155 - if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
26156 - return true;
26157 -
26158 - host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
26159 - if ((host_isr & AR_INTR_SYNC_DEFAULT)
26160 - && (host_isr != AR_INTR_SPURIOUS))
26161 - return true;
26162 -
26163 - return false;
26164 -}
26165 -EXPORT_SYMBOL(ath9k_hw_intrpend);
26166 -
26167 -bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
26168 -{
26169 - u32 isr = 0;
26170 - u32 mask2 = 0;
26171 - struct ath9k_hw_capabilities *pCap = &ah->caps;
26172 - u32 sync_cause = 0;
26173 - bool fatal_int = false;
26174 - struct ath_common *common = ath9k_hw_common(ah);
26175 -
26176 - if (!AR_SREV_9100(ah)) {
26177 - if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
26178 - if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
26179 - == AR_RTC_STATUS_ON) {
26180 - isr = REG_READ(ah, AR_ISR);
26181 - }
26182 - }
26183 -
26184 - sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
26185 - AR_INTR_SYNC_DEFAULT;
26186 -
26187 - *masked = 0;
26188 -
26189 - if (!isr && !sync_cause)
26190 - return false;
26191 - } else {
26192 - *masked = 0;
26193 - isr = REG_READ(ah, AR_ISR);
26194 - }
26195 -
26196 - if (isr) {
26197 - if (isr & AR_ISR_BCNMISC) {
26198 - u32 isr2;
26199 - isr2 = REG_READ(ah, AR_ISR_S2);
26200 - if (isr2 & AR_ISR_S2_TIM)
26201 - mask2 |= ATH9K_INT_TIM;
26202 - if (isr2 & AR_ISR_S2_DTIM)
26203 - mask2 |= ATH9K_INT_DTIM;
26204 - if (isr2 & AR_ISR_S2_DTIMSYNC)
26205 - mask2 |= ATH9K_INT_DTIMSYNC;
26206 - if (isr2 & (AR_ISR_S2_CABEND))
26207 - mask2 |= ATH9K_INT_CABEND;
26208 - if (isr2 & AR_ISR_S2_GTT)
26209 - mask2 |= ATH9K_INT_GTT;
26210 - if (isr2 & AR_ISR_S2_CST)
26211 - mask2 |= ATH9K_INT_CST;
26212 - if (isr2 & AR_ISR_S2_TSFOOR)
26213 - mask2 |= ATH9K_INT_TSFOOR;
26214 - }
26215 -
26216 - isr = REG_READ(ah, AR_ISR_RAC);
26217 - if (isr == 0xffffffff) {
26218 - *masked = 0;
26219 - return false;
26220 - }
26221 -
26222 - *masked = isr & ATH9K_INT_COMMON;
26223 -
26224 - if (ah->config.rx_intr_mitigation) {
26225 - if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
26226 - *masked |= ATH9K_INT_RX;
26227 - }
26228 -
26229 - if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
26230 - *masked |= ATH9K_INT_RX;
26231 - if (isr &
26232 - (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
26233 - AR_ISR_TXEOL)) {
26234 - u32 s0_s, s1_s;
26235 -
26236 - *masked |= ATH9K_INT_TX;
26237 -
26238 - s0_s = REG_READ(ah, AR_ISR_S0_S);
26239 - ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
26240 - ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
26241 -
26242 - s1_s = REG_READ(ah, AR_ISR_S1_S);
26243 - ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
26244 - ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
26245 - }
26246 -
26247 - if (isr & AR_ISR_RXORN) {
26248 - ath_print(common, ATH_DBG_INTERRUPT,
26249 - "receive FIFO overrun interrupt\n");
26250 - }
26251 -
26252 - if (!AR_SREV_9100(ah)) {
26253 - if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
26254 - u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
26255 - if (isr5 & AR_ISR_S5_TIM_TIMER)
26256 - *masked |= ATH9K_INT_TIM_TIMER;
26257 - }
26258 - }
26259 -
26260 - *masked |= mask2;
26261 - }
26262 -
26263 - if (AR_SREV_9100(ah))
26264 - return true;
26265 -
26266 - if (isr & AR_ISR_GENTMR) {
26267 - u32 s5_s;
26268 -
26269 - s5_s = REG_READ(ah, AR_ISR_S5_S);
26270 - if (isr & AR_ISR_GENTMR) {
26271 - ah->intr_gen_timer_trigger =
26272 - MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
26273 -
26274 - ah->intr_gen_timer_thresh =
26275 - MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
26276 -
26277 - if (ah->intr_gen_timer_trigger)
26278 - *masked |= ATH9K_INT_GENTIMER;
26279 -
26280 - }
26281 - }
26282 -
26283 - if (sync_cause) {
26284 - fatal_int =
26285 - (sync_cause &
26286 - (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
26287 - ? true : false;
26288 -
26289 - if (fatal_int) {
26290 - if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
26291 - ath_print(common, ATH_DBG_ANY,
26292 - "received PCI FATAL interrupt\n");
26293 - }
26294 - if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
26295 - ath_print(common, ATH_DBG_ANY,
26296 - "received PCI PERR interrupt\n");
26297 - }
26298 - *masked |= ATH9K_INT_FATAL;
26299 - }
26300 - if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
26301 - ath_print(common, ATH_DBG_INTERRUPT,
26302 - "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
26303 - REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
26304 - REG_WRITE(ah, AR_RC, 0);
26305 - *masked |= ATH9K_INT_FATAL;
26306 - }
26307 - if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
26308 - ath_print(common, ATH_DBG_INTERRUPT,
26309 - "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
26310 - }
26311 -
26312 - REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
26313 - (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
26314 - }
26315 -
26316 - return true;
26317 -}
26318 -EXPORT_SYMBOL(ath9k_hw_getisr);
26319 -
26320 -enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
26321 -{
26322 - enum ath9k_int omask = ah->imask;
26323 - u32 mask, mask2;
26324 - struct ath9k_hw_capabilities *pCap = &ah->caps;
26325 - struct ath_common *common = ath9k_hw_common(ah);
26326 -
26327 - ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
26328 -
26329 - if (omask & ATH9K_INT_GLOBAL) {
26330 - ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
26331 - REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
26332 - (void) REG_READ(ah, AR_IER);
26333 - if (!AR_SREV_9100(ah)) {
26334 - REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
26335 - (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
26336 -
26337 - REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
26338 - (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
26339 - }
26340 - }
26341 -
26342 - mask = ints & ATH9K_INT_COMMON;
26343 - mask2 = 0;
26344 -
26345 - if (ints & ATH9K_INT_TX) {
26346 - if (ah->txok_interrupt_mask)
26347 - mask |= AR_IMR_TXOK;
26348 - if (ah->txdesc_interrupt_mask)
26349 - mask |= AR_IMR_TXDESC;
26350 - if (ah->txerr_interrupt_mask)
26351 - mask |= AR_IMR_TXERR;
26352 - if (ah->txeol_interrupt_mask)
26353 - mask |= AR_IMR_TXEOL;
26354 - }
26355 - if (ints & ATH9K_INT_RX) {
26356 - mask |= AR_IMR_RXERR;
26357 - if (ah->config.rx_intr_mitigation)
26358 - mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
26359 - else
26360 - mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
26361 - if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
26362 - mask |= AR_IMR_GENTMR;
26363 - }
26364 -
26365 - if (ints & (ATH9K_INT_BMISC)) {
26366 - mask |= AR_IMR_BCNMISC;
26367 - if (ints & ATH9K_INT_TIM)
26368 - mask2 |= AR_IMR_S2_TIM;
26369 - if (ints & ATH9K_INT_DTIM)
26370 - mask2 |= AR_IMR_S2_DTIM;
26371 - if (ints & ATH9K_INT_DTIMSYNC)
26372 - mask2 |= AR_IMR_S2_DTIMSYNC;
26373 - if (ints & ATH9K_INT_CABEND)
26374 - mask2 |= AR_IMR_S2_CABEND;
26375 - if (ints & ATH9K_INT_TSFOOR)
26376 - mask2 |= AR_IMR_S2_TSFOOR;
26377 - }
26378 -
26379 - if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
26380 - mask |= AR_IMR_BCNMISC;
26381 - if (ints & ATH9K_INT_GTT)
26382 - mask2 |= AR_IMR_S2_GTT;
26383 - if (ints & ATH9K_INT_CST)
26384 - mask2 |= AR_IMR_S2_CST;
26385 - }
26386 -
26387 - ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
26388 - REG_WRITE(ah, AR_IMR, mask);
26389 - ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
26390 - AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
26391 - AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
26392 - ah->imrs2_reg |= mask2;
26393 - REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
26394 -
26395 - if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
26396 - if (ints & ATH9K_INT_TIM_TIMER)
26397 - REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
26398 - else
26399 - REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
26400 - }
26401 -
26402 - if (ints & ATH9K_INT_GLOBAL) {
26403 - ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
26404 - REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
26405 - if (!AR_SREV_9100(ah)) {
26406 - REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
26407 - AR_INTR_MAC_IRQ);
26408 - REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
26409 -
26410 -
26411 - REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
26412 - AR_INTR_SYNC_DEFAULT);
26413 - REG_WRITE(ah, AR_INTR_SYNC_MASK,
26414 - AR_INTR_SYNC_DEFAULT);
26415 - }
26416 - ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
26417 - REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
26418 - }
26419 -
26420 - return omask;
26421 -}
26422 -EXPORT_SYMBOL(ath9k_hw_set_interrupts);
26423 -
26424 /*******************/
26425 /* Beacon Handling */
26426 /*******************/
26427 @@ -3240,6 +2088,24 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
26428 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
26429 }
26430
26431 + if (AR_SREV_9300_20_OR_LATER(ah)) {
26432 + pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC;
26433 + pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
26434 + if (AR_SREV_9300_20_OR_LATER(ah))
26435 + pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
26436 + else
26437 + pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH_AR9300_10;
26438 +
26439 + pCap->rx_status_len = sizeof(struct ar9003_rxs);
26440 + pCap->tx_desc_len = sizeof(struct ar9003_txc);
26441 + pCap->txs_len = sizeof(struct ar9003_txs);
26442 + } else {
26443 + pCap->tx_desc_len = sizeof(struct ath_desc);
26444 + }
26445 +
26446 + if (AR_SREV_9300_20_OR_LATER(ah))
26447 + pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
26448 +
26449 return 0;
26450 }
26451
26452 @@ -3272,10 +2138,6 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
26453 case ATH9K_CAP_TKIP_SPLIT:
26454 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
26455 false : true;
26456 - case ATH9K_CAP_DIVERSITY:
26457 - return (REG_READ(ah, AR_PHY_CCK_DETECT) &
26458 - AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
26459 - true : false;
26460 case ATH9K_CAP_MCAST_KEYSRCH:
26461 switch (capability) {
26462 case 0:
26463 @@ -3318,8 +2180,6 @@ EXPORT_SYMBOL(ath9k_hw_getcapability);
26464 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
26465 u32 capability, u32 setting, int *status)
26466 {
26467 - u32 v;
26468 -
26469 switch (type) {
26470 case ATH9K_CAP_TKIP_MIC:
26471 if (setting)
26472 @@ -3329,14 +2189,6 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
26473 ah->sta_id1_defaults &=
26474 ~AR_STA_ID1_CRPT_MIC_ENABLE;
26475 return true;
26476 - case ATH9K_CAP_DIVERSITY:
26477 - v = REG_READ(ah, AR_PHY_CCK_DETECT);
26478 - if (setting)
26479 - v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
26480 - else
26481 - v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
26482 - REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
26483 - return true;
26484 case ATH9K_CAP_MCAST_KEYSRCH:
26485 if (setting)
26486 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
26487 @@ -3404,7 +2256,9 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
26488 if (gpio >= ah->caps.num_gpio_pins)
26489 return 0xffffffff;
26490
26491 - if (AR_SREV_9271(ah))
26492 + if (AR_SREV_9300_20_OR_LATER(ah))
26493 + return MS_REG_READ(AR9300, gpio) != 0;
26494 + else if (AR_SREV_9271(ah))
26495 return MS_REG_READ(AR9271, gpio) != 0;
26496 else if (AR_SREV_9287_10_OR_LATER(ah))
26497 return MS_REG_READ(AR9287, gpio) != 0;
26498 @@ -3846,6 +2700,7 @@ static struct {
26499 { AR_SREV_VERSION_9285, "9285" },
26500 { AR_SREV_VERSION_9287, "9287" },
26501 { AR_SREV_VERSION_9271, "9271" },
26502 + { AR_SREV_VERSION_9300, "9300" },
26503 };
26504
26505 /* For devices with external radios */
26506 diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
26507 index f4821cf..43a1a44 100644
26508 --- a/drivers/net/wireless/ath/ath9k/hw.h
26509 +++ b/drivers/net/wireless/ath/ath9k/hw.h
26510 @@ -1,5 +1,5 @@
26511 /*
26512 - * Copyright (c) 2008-2009 Atheros Communications Inc.
26513 + * Copyright (c) 2008-2010 Atheros Communications Inc.
26514 *
26515 * Permission to use, copy, modify, and/or distribute this software for any
26516 * purpose with or without fee is hereby granted, provided that the above
26517 @@ -28,6 +28,7 @@
26518 #include "reg.h"
26519 #include "phy.h"
26520 #include "btcoex.h"
26521 +#include "ar9003_mac.h"
26522
26523 #include "../regd.h"
26524 #include "../debug.h"
26525 @@ -41,6 +42,9 @@
26526 #define AR9280_DEVID_PCIE 0x002a
26527 #define AR9285_DEVID_PCIE 0x002b
26528 #define AR2427_DEVID_PCIE 0x002c
26529 +#define AR9287_DEVID_PCI 0x002d
26530 +#define AR9287_DEVID_PCIE 0x002e
26531 +#define AR9300_DEVID_PCIE 0x0030
26532
26533 #define AR5416_AR9100_DEVID 0x000b
26534
26535 @@ -48,9 +52,6 @@
26536 #define AR_SUBVENDOR_ID_NEW_A 0x7065
26537 #define AR5416_MAGIC 0x19641014
26538
26539 -#define AR5416_DEVID_AR9287_PCI 0x002D
26540 -#define AR5416_DEVID_AR9287_PCIE 0x002E
26541 -
26542 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
26543 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
26544 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
26545 @@ -75,6 +76,8 @@
26546 #define REG_RMW_FIELD(_a, _r, _f, _v) \
26547 REG_WRITE(_a, _r, \
26548 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
26549 +#define REG_READ_FIELD(_a, _r, _f) \
26550 + (((REG_READ(_a, _r) & _f) >> _f##_S))
26551 #define REG_SET_BIT(_a, _r, _f) \
26552 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
26553 #define REG_CLR_BIT(_a, _r, _f) \
26554 @@ -135,6 +138,17 @@
26555
26556 #define TU_TO_USEC(_tu) ((_tu) << 10)
26557
26558 +#define ATH9K_HW_RX_HP_QDEPTH 16
26559 +#define ATH9K_HW_RX_LP_QDEPTH_AR9300_10 64
26560 +#define ATH9K_HW_RX_LP_QDEPTH 128
26561 +
26562 +enum ath_ini_subsys {
26563 + ATH_INI_PRE = 0,
26564 + ATH_INI_CORE,
26565 + ATH_INI_POST,
26566 + ATH_INI_NUM_SPLIT,
26567 +};
26568 +
26569 enum wireless_mode {
26570 ATH9K_MODE_11A = 0,
26571 ATH9K_MODE_11G,
26572 @@ -165,13 +179,15 @@ enum ath9k_hw_caps {
26573 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
26574 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
26575 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
26576 + ATH9K_HW_CAP_EDMA = BIT(17),
26577 + ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18),
26578 + ATH9K_HW_CAP_LDPC = BIT(19),
26579 };
26580
26581 enum ath9k_capability_type {
26582 ATH9K_CAP_CIPHER = 0,
26583 ATH9K_CAP_TKIP_MIC,
26584 ATH9K_CAP_TKIP_SPLIT,
26585 - ATH9K_CAP_DIVERSITY,
26586 ATH9K_CAP_TXPOW,
26587 ATH9K_CAP_MCAST_KEYSRCH,
26588 ATH9K_CAP_DS
26589 @@ -192,6 +208,11 @@ struct ath9k_hw_capabilities {
26590 u8 num_gpio_pins;
26591 u8 num_antcfg_2ghz;
26592 u8 num_antcfg_5ghz;
26593 + u8 rx_hp_qdepth;
26594 + u8 rx_lp_qdepth;
26595 + u8 rx_status_len;
26596 + u8 tx_desc_len;
26597 + u8 txs_len;
26598 };
26599
26600 struct ath9k_ops_config {
26601 @@ -212,6 +233,7 @@ struct ath9k_ops_config {
26602 u32 enable_ani;
26603 int serialize_regmode;
26604 bool rx_intr_mitigation;
26605 + bool tx_intr_mitigation;
26606 #define SPUR_DISABLE 0
26607 #define SPUR_ENABLE_IOCTL 1
26608 #define SPUR_ENABLE_EEPROM 2
26609 @@ -231,6 +253,8 @@ struct ath9k_ops_config {
26610 enum ath9k_int {
26611 ATH9K_INT_RX = 0x00000001,
26612 ATH9K_INT_RXDESC = 0x00000002,
26613 + ATH9K_INT_RXHP = 0x00000001,
26614 + ATH9K_INT_RXLP = 0x00000002,
26615 ATH9K_INT_RXNOFRM = 0x00000008,
26616 ATH9K_INT_RXEOL = 0x00000010,
26617 ATH9K_INT_RXORN = 0x00000020,
26618 @@ -440,6 +464,125 @@ struct ath_gen_timer_table {
26619 } timer_mask;
26620 };
26621
26622 +/**
26623 + * struct ath_hw_private_ops - callbacks used internally by hardware code
26624 + *
26625 + * This structure contains private callbacks designed to only be used internally
26626 + * by the hardware core.
26627 + *
26628 + * @init_cal_settings: setup types of calibrations supported
26629 + * @init_cal: starts actual calibration
26630 + *
26631 + * @init_mode_regs: Initializes mode registers
26632 + * @init_mode_gain_regs: Initialize TX/RX gain registers
26633 + * @macversion_supported: If this specific mac revision is supported
26634 + *
26635 + * @rf_set_freq: change frequency
26636 + * @spur_mitigate_freq: spur mitigation
26637 + * @rf_alloc_ext_banks:
26638 + * @rf_free_ext_banks:
26639 + * @set_rf_regs:
26640 + * @compute_pll_control: compute the PLL control value to use for
26641 + * AR_RTC_PLL_CONTROL for a given channel
26642 + * @setup_calibration: set up calibration
26643 + * @iscal_supported: used to query if a type of calibration is supported
26644 + * @loadnf: load noise floor read from each chain on the CCA registers
26645 + */
26646 +struct ath_hw_private_ops {
26647 + /* Calibration ops */
26648 + void (*init_cal_settings)(struct ath_hw *ah);
26649 + bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
26650 +
26651 + void (*init_mode_regs)(struct ath_hw *ah);
26652 + void (*init_mode_gain_regs)(struct ath_hw *ah);
26653 + bool (*macversion_supported)(u32 macversion);
26654 + void (*setup_calibration)(struct ath_hw *ah,
26655 + struct ath9k_cal_list *currCal);
26656 + bool (*iscal_supported)(struct ath_hw *ah,
26657 + enum ath9k_cal_types calType);
26658 +
26659 + /* PHY ops */
26660 + int (*rf_set_freq)(struct ath_hw *ah,
26661 + struct ath9k_channel *chan);
26662 + void (*spur_mitigate_freq)(struct ath_hw *ah,
26663 + struct ath9k_channel *chan);
26664 + int (*rf_alloc_ext_banks)(struct ath_hw *ah);
26665 + void (*rf_free_ext_banks)(struct ath_hw *ah);
26666 + bool (*set_rf_regs)(struct ath_hw *ah,
26667 + struct ath9k_channel *chan,
26668 + u16 modesIndex);
26669 + void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
26670 + void (*init_bb)(struct ath_hw *ah,
26671 + struct ath9k_channel *chan);
26672 + int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
26673 + void (*olc_init)(struct ath_hw *ah);
26674 + void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
26675 + void (*mark_phy_inactive)(struct ath_hw *ah);
26676 + void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
26677 + bool (*rfbus_req)(struct ath_hw *ah);
26678 + void (*rfbus_done)(struct ath_hw *ah);
26679 + void (*enable_rfkill)(struct ath_hw *ah);
26680 + void (*restore_chainmask)(struct ath_hw *ah);
26681 + void (*set_diversity)(struct ath_hw *ah, bool value);
26682 + u32 (*compute_pll_control)(struct ath_hw *ah,
26683 + struct ath9k_channel *chan);
26684 + bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
26685 + int param);
26686 + void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
26687 + void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
26688 +};
26689 +
26690 +/**
26691 + * struct ath_hw_ops - callbacks used by hardware code and driver code
26692 + *
26693 + * This structure contains callbacks designed to to be used internally by
26694 + * hardware code and also by the lower level driver.
26695 + *
26696 + * @config_pci_powersave:
26697 + * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
26698 + */
26699 +struct ath_hw_ops {
26700 + void (*config_pci_powersave)(struct ath_hw *ah,
26701 + int restore,
26702 + int power_off);
26703 + void (*rx_enable)(struct ath_hw *ah);
26704 + void (*set_desc_link)(void *ds, u32 link);
26705 + void (*get_desc_link)(void *ds, u32 **link);
26706 + bool (*calibrate)(struct ath_hw *ah,
26707 + struct ath9k_channel *chan,
26708 + u8 rxchainmask,
26709 + bool longcal);
26710 + bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
26711 + void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
26712 + bool is_firstseg, bool is_is_lastseg,
26713 + const void *ds0, dma_addr_t buf_addr,
26714 + unsigned int qcu);
26715 + void (*clear_txdesc)(struct ath_hw *ah, void *ds);
26716 + int (*proc_txdesc)(struct ath_hw *ah, void *ds,
26717 + struct ath_tx_status *ts);
26718 + void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
26719 + u32 pktLen, enum ath9k_pkt_type type,
26720 + u32 txPower, u32 keyIx,
26721 + enum ath9k_key_type keyType,
26722 + u32 flags);
26723 + void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
26724 + void *lastds,
26725 + u32 durUpdateEn, u32 rtsctsRate,
26726 + u32 rtsctsDuration,
26727 + struct ath9k_11n_rate_series series[],
26728 + u32 nseries, u32 flags);
26729 + void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
26730 + u32 aggrLen);
26731 + void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
26732 + u32 numDelims);
26733 + void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
26734 + void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
26735 + void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
26736 + u32 burstDuration);
26737 + void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
26738 + u32 vmf);
26739 +};
26740 +
26741 struct ath_hw {
26742 struct ieee80211_hw *hw;
26743 struct ath_common common;
26744 @@ -453,14 +596,18 @@ struct ath_hw {
26745 struct ar5416_eeprom_def def;
26746 struct ar5416_eeprom_4k map4k;
26747 struct ar9287_eeprom map9287;
26748 + struct ar9300_eeprom ar9300_eep;
26749 } eeprom;
26750 const struct eeprom_ops *eep_ops;
26751 - enum ath9k_eep_map eep_map;
26752
26753 bool sw_mgmt_crypto;
26754 bool is_pciexpress;
26755 bool need_an_top2_fixup;
26756 u16 tx_trig_level;
26757 + s16 nf_2g_max;
26758 + s16 nf_2g_min;
26759 + s16 nf_5g_max;
26760 + s16 nf_5g_min;
26761 u16 rfsilent;
26762 u32 rfkill_gpio;
26763 u32 rfkill_polarity;
26764 @@ -493,6 +640,7 @@ struct ath_hw {
26765 struct ath9k_cal_list adcgain_caldata;
26766 struct ath9k_cal_list adcdc_calinitdata;
26767 struct ath9k_cal_list adcdc_caldata;
26768 + struct ath9k_cal_list tempCompCalData;
26769 struct ath9k_cal_list *cal_list;
26770 struct ath9k_cal_list *cal_list_last;
26771 struct ath9k_cal_list *cal_list_curr;
26772 @@ -533,12 +681,10 @@ struct ath_hw {
26773 DONT_USE_32KHZ,
26774 } enable_32kHz_clock;
26775
26776 - /* Callback for radio frequency change */
26777 - int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan);
26778 -
26779 - /* Callback for baseband spur frequency */
26780 - void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
26781 - struct ath9k_channel *chan);
26782 + /* Private to hardware code */
26783 + struct ath_hw_private_ops private_ops;
26784 + /* Accessed by the lower level driver */
26785 + struct ath_hw_ops ops;
26786
26787 /* Used to program the radio on non single-chip devices */
26788 u32 *analogBank0Data;
26789 @@ -592,6 +738,7 @@ struct ath_hw {
26790 struct ar5416IniArray iniBank7;
26791 struct ar5416IniArray iniAddac;
26792 struct ar5416IniArray iniPcieSerdes;
26793 + struct ar5416IniArray iniPcieSerdesLowPower;
26794 struct ar5416IniArray iniModesAdditional;
26795 struct ar5416IniArray iniModesRxGain;
26796 struct ar5416IniArray iniModesTxGain;
26797 @@ -604,9 +751,21 @@ struct ath_hw {
26798 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
26799 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
26800
26801 + struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
26802 + struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
26803 + struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
26804 + struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
26805 +
26806 u32 intr_gen_timer_trigger;
26807 u32 intr_gen_timer_thresh;
26808 struct ath_gen_timer_table hw_gen_timers;
26809 +
26810 + struct ar9003_txs *ts_ring;
26811 + void *ts_start;
26812 + u32 ts_paddr_start;
26813 + u32 ts_paddr_end;
26814 + u16 ts_tail;
26815 + u8 ts_size;
26816 };
26817
26818 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
26819 @@ -619,6 +778,16 @@ static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
26820 return &(ath9k_hw_common(ah)->regulatory);
26821 }
26822
26823 +static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
26824 +{
26825 + return &ah->private_ops;
26826 +}
26827 +
26828 +static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
26829 +{
26830 + return &ah->ops;
26831 +}
26832 +
26833 /* Initialization, Detach, Reset */
26834 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
26835 void ath9k_hw_deinit(struct ath_hw *ah);
26836 @@ -630,6 +799,7 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
26837 u32 capability, u32 *result);
26838 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
26839 u32 capability, u32 setting, int *status);
26840 +u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
26841
26842 /* Key Cache Management */
26843 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
26844 @@ -681,13 +851,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
26845
26846 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
26847
26848 -void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
26849 -
26850 -/* Interrupt Handling */
26851 -bool ath9k_hw_intrpend(struct ath_hw *ah);
26852 -bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
26853 -enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
26854 -
26855 /* Generic hw timer primitives */
26856 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
26857 void (*trigger)(void *),
26858 @@ -709,6 +872,36 @@ void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
26859 /* HTC */
26860 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
26861
26862 +/* PHY */
26863 +void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
26864 + u32 *coef_mantissa, u32 *coef_exponent);
26865 +
26866 +/*
26867 + * Code Specific to AR5008, AR9001 or AR9002,
26868 + * we stuff these here to avoid callbacks for AR9003.
26869 + */
26870 +void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
26871 +int ar9002_hw_rf_claim(struct ath_hw *ah);
26872 +void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
26873 +void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
26874 +
26875 +/*
26876 + * Code specifric to AR9003, we stuff these here to avoid callbacks
26877 + * for older families
26878 + */
26879 +void ar9003_hw_set_nf_limits(struct ath_hw *ah);
26880 +
26881 +/* Hardware family op attach helpers */
26882 +void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
26883 +void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
26884 +void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
26885 +
26886 +void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
26887 +void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
26888 +
26889 +void ar9002_hw_attach_ops(struct ath_hw *ah);
26890 +void ar9003_hw_attach_ops(struct ath_hw *ah);
26891 +
26892 #define ATH_PCIE_CAP_LINK_CTRL 0x70
26893 #define ATH_PCIE_CAP_LINK_L0S 1
26894 #define ATH_PCIE_CAP_LINK_L1 2
26895 diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
26896 index 6063f54..5adc2e3 100644
26897 --- a/drivers/net/wireless/ath/ath9k/init.c
26898 +++ b/drivers/net/wireless/ath/ath9k/init.c
26899 @@ -189,6 +189,9 @@ static void setup_ht_cap(struct ath_softc *sc,
26900 IEEE80211_HT_CAP_SGI_40 |
26901 IEEE80211_HT_CAP_DSSSCCK40;
26902
26903 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
26904 + ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
26905 +
26906 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
26907 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
26908
26909 @@ -233,31 +236,37 @@ static int ath9k_reg_notifier(struct wiphy *wiphy,
26910 */
26911 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
26912 struct list_head *head, const char *name,
26913 - int nbuf, int ndesc)
26914 + int nbuf, int ndesc, bool is_tx)
26915 {
26916 #define DS2PHYS(_dd, _ds) \
26917 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
26918 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
26919 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
26920 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
26921 - struct ath_desc *ds;
26922 + u8 *ds;
26923 struct ath_buf *bf;
26924 - int i, bsize, error;
26925 + int i, bsize, error, desc_len;
26926
26927 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
26928 name, nbuf, ndesc);
26929
26930 INIT_LIST_HEAD(head);
26931 +
26932 + if (is_tx)
26933 + desc_len = sc->sc_ah->caps.tx_desc_len;
26934 + else
26935 + desc_len = sizeof(struct ath_desc);
26936 +
26937 /* ath_desc must be a multiple of DWORDs */
26938 - if ((sizeof(struct ath_desc) % 4) != 0) {
26939 + if ((desc_len % 4) != 0) {
26940 ath_print(common, ATH_DBG_FATAL,
26941 "ath_desc not DWORD aligned\n");
26942 - BUG_ON((sizeof(struct ath_desc) % 4) != 0);
26943 + BUG_ON((desc_len % 4) != 0);
26944 error = -ENOMEM;
26945 goto fail;
26946 }
26947
26948 - dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
26949 + dd->dd_desc_len = desc_len * nbuf * ndesc;
26950
26951 /*
26952 * Need additional DMA memory because we can't use
26953 @@ -270,7 +279,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
26954 u32 dma_len;
26955
26956 while (ndesc_skipped) {
26957 - dma_len = ndesc_skipped * sizeof(struct ath_desc);
26958 + dma_len = ndesc_skipped * desc_len;
26959 dd->dd_desc_len += dma_len;
26960
26961 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
26962 @@ -284,7 +293,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
26963 error = -ENOMEM;
26964 goto fail;
26965 }
26966 - ds = dd->dd_desc;
26967 + ds = (u8 *) dd->dd_desc;
26968 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
26969 name, ds, (u32) dd->dd_desc_len,
26970 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
26971 @@ -298,7 +307,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
26972 }
26973 dd->dd_bufptr = bf;
26974
26975 - for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
26976 + for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
26977 bf->bf_desc = ds;
26978 bf->bf_daddr = DS2PHYS(dd, ds);
26979
26980 @@ -314,7 +323,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
26981 ((caddr_t) dd->dd_desc +
26982 dd->dd_desc_len));
26983
26984 - ds += ndesc;
26985 + ds += (desc_len * ndesc);
26986 bf->bf_desc = ds;
26987 bf->bf_daddr = DS2PHYS(dd, ds);
26988 }
26989 @@ -512,7 +521,7 @@ static void ath9k_init_misc(struct ath_softc *sc)
26990 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
26991 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
26992
26993 - ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
26994 + ath9k_hw_set_diversity(sc->sc_ah, true);
26995 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
26996
26997 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
26998 @@ -566,13 +575,10 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
26999 ath_read_cachesize(common, &csz);
27000 common->cachelsz = csz << 2; /* convert to bytes */
27001
27002 + /* Initializes the hardware for all supported chipsets */
27003 ret = ath9k_hw_init(ah);
27004 - if (ret) {
27005 - ath_print(common, ATH_DBG_FATAL,
27006 - "Unable to initialize hardware; "
27007 - "initialization status: %d\n", ret);
27008 + if (ret)
27009 goto err_hw;
27010 - }
27011
27012 ret = ath9k_init_debug(ah);
27013 if (ret) {
27014 diff --git a/drivers/net/wireless/ath/ath9k/initvals.h b/drivers/net/wireless/ath/ath9k/initvals.h
27015 deleted file mode 100644
27016 index 455e9d3..0000000
27017 --- a/drivers/net/wireless/ath/ath9k/initvals.h
27018 +++ /dev/null
27019 @@ -1,7200 +0,0 @@
27020 -/*
27021 - * Copyright (c) 2008-2009 Atheros Communications Inc.
27022 - *
27023 - * Permission to use, copy, modify, and/or distribute this software for any
27024 - * purpose with or without fee is hereby granted, provided that the above
27025 - * copyright notice and this permission notice appear in all copies.
27026 - *
27027 - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
27028 - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
27029 - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
27030 - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
27031 - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
27032 - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
27033 - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
27034 - */
27035 -
27036 -static const u32 ar5416Modes[][6] = {
27037 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
27038 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
27039 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
27040 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
27041 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
27042 - { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
27043 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
27044 - { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
27045 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
27046 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
27047 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
27048 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
27049 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
27050 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
27051 - { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
27052 - { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
27053 - { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
27054 - { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
27055 - { 0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de, 0x6c48b0de },
27056 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
27057 - { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
27058 - { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 },
27059 - { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
27060 - { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 },
27061 - { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
27062 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
27063 - { 0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134, 0x00000134 },
27064 - { 0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b },
27065 - { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
27066 - { 0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
27067 - { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
27068 - { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
27069 - { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 },
27070 - { 0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 },
27071 - { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
27072 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
27073 - { 0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c },
27074 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
27075 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
27076 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27077 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27078 - { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
27079 - { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
27080 - { 0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
27081 - { 0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
27082 - { 0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
27083 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
27084 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
27085 - { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
27086 - { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
27087 - { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
27088 - { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
27089 - { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
27090 - { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
27091 - { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
27092 - { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
27093 - { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
27094 - { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
27095 - { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
27096 - { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
27097 - { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27098 - { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27099 - { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27100 -};
27101 -
27102 -static const u32 ar5416Common[][2] = {
27103 - { 0x0000000c, 0x00000000 },
27104 - { 0x00000030, 0x00020015 },
27105 - { 0x00000034, 0x00000005 },
27106 - { 0x00000040, 0x00000000 },
27107 - { 0x00000044, 0x00000008 },
27108 - { 0x00000048, 0x00000008 },
27109 - { 0x0000004c, 0x00000010 },
27110 - { 0x00000050, 0x00000000 },
27111 - { 0x00000054, 0x0000001f },
27112 - { 0x00000800, 0x00000000 },
27113 - { 0x00000804, 0x00000000 },
27114 - { 0x00000808, 0x00000000 },
27115 - { 0x0000080c, 0x00000000 },
27116 - { 0x00000810, 0x00000000 },
27117 - { 0x00000814, 0x00000000 },
27118 - { 0x00000818, 0x00000000 },
27119 - { 0x0000081c, 0x00000000 },
27120 - { 0x00000820, 0x00000000 },
27121 - { 0x00000824, 0x00000000 },
27122 - { 0x00001040, 0x002ffc0f },
27123 - { 0x00001044, 0x002ffc0f },
27124 - { 0x00001048, 0x002ffc0f },
27125 - { 0x0000104c, 0x002ffc0f },
27126 - { 0x00001050, 0x002ffc0f },
27127 - { 0x00001054, 0x002ffc0f },
27128 - { 0x00001058, 0x002ffc0f },
27129 - { 0x0000105c, 0x002ffc0f },
27130 - { 0x00001060, 0x002ffc0f },
27131 - { 0x00001064, 0x002ffc0f },
27132 - { 0x00001230, 0x00000000 },
27133 - { 0x00001270, 0x00000000 },
27134 - { 0x00001038, 0x00000000 },
27135 - { 0x00001078, 0x00000000 },
27136 - { 0x000010b8, 0x00000000 },
27137 - { 0x000010f8, 0x00000000 },
27138 - { 0x00001138, 0x00000000 },
27139 - { 0x00001178, 0x00000000 },
27140 - { 0x000011b8, 0x00000000 },
27141 - { 0x000011f8, 0x00000000 },
27142 - { 0x00001238, 0x00000000 },
27143 - { 0x00001278, 0x00000000 },
27144 - { 0x000012b8, 0x00000000 },
27145 - { 0x000012f8, 0x00000000 },
27146 - { 0x00001338, 0x00000000 },
27147 - { 0x00001378, 0x00000000 },
27148 - { 0x000013b8, 0x00000000 },
27149 - { 0x000013f8, 0x00000000 },
27150 - { 0x00001438, 0x00000000 },
27151 - { 0x00001478, 0x00000000 },
27152 - { 0x000014b8, 0x00000000 },
27153 - { 0x000014f8, 0x00000000 },
27154 - { 0x00001538, 0x00000000 },
27155 - { 0x00001578, 0x00000000 },
27156 - { 0x000015b8, 0x00000000 },
27157 - { 0x000015f8, 0x00000000 },
27158 - { 0x00001638, 0x00000000 },
27159 - { 0x00001678, 0x00000000 },
27160 - { 0x000016b8, 0x00000000 },
27161 - { 0x000016f8, 0x00000000 },
27162 - { 0x00001738, 0x00000000 },
27163 - { 0x00001778, 0x00000000 },
27164 - { 0x000017b8, 0x00000000 },
27165 - { 0x000017f8, 0x00000000 },
27166 - { 0x0000103c, 0x00000000 },
27167 - { 0x0000107c, 0x00000000 },
27168 - { 0x000010bc, 0x00000000 },
27169 - { 0x000010fc, 0x00000000 },
27170 - { 0x0000113c, 0x00000000 },
27171 - { 0x0000117c, 0x00000000 },
27172 - { 0x000011bc, 0x00000000 },
27173 - { 0x000011fc, 0x00000000 },
27174 - { 0x0000123c, 0x00000000 },
27175 - { 0x0000127c, 0x00000000 },
27176 - { 0x000012bc, 0x00000000 },
27177 - { 0x000012fc, 0x00000000 },
27178 - { 0x0000133c, 0x00000000 },
27179 - { 0x0000137c, 0x00000000 },
27180 - { 0x000013bc, 0x00000000 },
27181 - { 0x000013fc, 0x00000000 },
27182 - { 0x0000143c, 0x00000000 },
27183 - { 0x0000147c, 0x00000000 },
27184 - { 0x00004030, 0x00000002 },
27185 - { 0x0000403c, 0x00000002 },
27186 - { 0x00007010, 0x00000000 },
27187 - { 0x00007038, 0x000004c2 },
27188 - { 0x00008004, 0x00000000 },
27189 - { 0x00008008, 0x00000000 },
27190 - { 0x0000800c, 0x00000000 },
27191 - { 0x00008018, 0x00000700 },
27192 - { 0x00008020, 0x00000000 },
27193 - { 0x00008038, 0x00000000 },
27194 - { 0x0000803c, 0x00000000 },
27195 - { 0x00008048, 0x40000000 },
27196 - { 0x00008054, 0x00000000 },
27197 - { 0x00008058, 0x00000000 },
27198 - { 0x0000805c, 0x000fc78f },
27199 - { 0x00008060, 0x0000000f },
27200 - { 0x00008064, 0x00000000 },
27201 - { 0x000080c0, 0x2a82301a },
27202 - { 0x000080c4, 0x05dc01e0 },
27203 - { 0x000080c8, 0x1f402710 },
27204 - { 0x000080cc, 0x01f40000 },
27205 - { 0x000080d0, 0x00001e00 },
27206 - { 0x000080d4, 0x00000000 },
27207 - { 0x000080d8, 0x00400000 },
27208 - { 0x000080e0, 0xffffffff },
27209 - { 0x000080e4, 0x0000ffff },
27210 - { 0x000080e8, 0x003f3f3f },
27211 - { 0x000080ec, 0x00000000 },
27212 - { 0x000080f0, 0x00000000 },
27213 - { 0x000080f4, 0x00000000 },
27214 - { 0x000080f8, 0x00000000 },
27215 - { 0x000080fc, 0x00020000 },
27216 - { 0x00008100, 0x00020000 },
27217 - { 0x00008104, 0x00000001 },
27218 - { 0x00008108, 0x00000052 },
27219 - { 0x0000810c, 0x00000000 },
27220 - { 0x00008110, 0x00000168 },
27221 - { 0x00008118, 0x000100aa },
27222 - { 0x0000811c, 0x00003210 },
27223 - { 0x00008124, 0x00000000 },
27224 - { 0x00008128, 0x00000000 },
27225 - { 0x0000812c, 0x00000000 },
27226 - { 0x00008130, 0x00000000 },
27227 - { 0x00008134, 0x00000000 },
27228 - { 0x00008138, 0x00000000 },
27229 - { 0x0000813c, 0x00000000 },
27230 - { 0x00008144, 0xffffffff },
27231 - { 0x00008168, 0x00000000 },
27232 - { 0x0000816c, 0x00000000 },
27233 - { 0x00008170, 0x32143320 },
27234 - { 0x00008174, 0xfaa4fa50 },
27235 - { 0x00008178, 0x00000100 },
27236 - { 0x0000817c, 0x00000000 },
27237 - { 0x000081c4, 0x00000000 },
27238 - { 0x000081ec, 0x00000000 },
27239 - { 0x000081f0, 0x00000000 },
27240 - { 0x000081f4, 0x00000000 },
27241 - { 0x000081f8, 0x00000000 },
27242 - { 0x000081fc, 0x00000000 },
27243 - { 0x00008200, 0x00000000 },
27244 - { 0x00008204, 0x00000000 },
27245 - { 0x00008208, 0x00000000 },
27246 - { 0x0000820c, 0x00000000 },
27247 - { 0x00008210, 0x00000000 },
27248 - { 0x00008214, 0x00000000 },
27249 - { 0x00008218, 0x00000000 },
27250 - { 0x0000821c, 0x00000000 },
27251 - { 0x00008220, 0x00000000 },
27252 - { 0x00008224, 0x00000000 },
27253 - { 0x00008228, 0x00000000 },
27254 - { 0x0000822c, 0x00000000 },
27255 - { 0x00008230, 0x00000000 },
27256 - { 0x00008234, 0x00000000 },
27257 - { 0x00008238, 0x00000000 },
27258 - { 0x0000823c, 0x00000000 },
27259 - { 0x00008240, 0x00100000 },
27260 - { 0x00008244, 0x0010f400 },
27261 - { 0x00008248, 0x00000100 },
27262 - { 0x0000824c, 0x0001e800 },
27263 - { 0x00008250, 0x00000000 },
27264 - { 0x00008254, 0x00000000 },
27265 - { 0x00008258, 0x00000000 },
27266 - { 0x0000825c, 0x400000ff },
27267 - { 0x00008260, 0x00080922 },
27268 - { 0x00008264, 0xa8000010 },
27269 - { 0x00008270, 0x00000000 },
27270 - { 0x00008274, 0x40000000 },
27271 - { 0x00008278, 0x003e4180 },
27272 - { 0x0000827c, 0x00000000 },
27273 - { 0x00008284, 0x0000002c },
27274 - { 0x00008288, 0x0000002c },
27275 - { 0x0000828c, 0x00000000 },
27276 - { 0x00008294, 0x00000000 },
27277 - { 0x00008298, 0x00000000 },
27278 - { 0x00008300, 0x00000000 },
27279 - { 0x00008304, 0x00000000 },
27280 - { 0x00008308, 0x00000000 },
27281 - { 0x0000830c, 0x00000000 },
27282 - { 0x00008310, 0x00000000 },
27283 - { 0x00008314, 0x00000000 },
27284 - { 0x00008318, 0x00000000 },
27285 - { 0x00008328, 0x00000000 },
27286 - { 0x0000832c, 0x00000007 },
27287 - { 0x00008330, 0x00000302 },
27288 - { 0x00008334, 0x00000e00 },
27289 - { 0x00008338, 0x00070000 },
27290 - { 0x0000833c, 0x00000000 },
27291 - { 0x00008340, 0x000107ff },
27292 - { 0x00009808, 0x00000000 },
27293 - { 0x0000980c, 0xad848e19 },
27294 - { 0x00009810, 0x7d14e000 },
27295 - { 0x00009814, 0x9c0a9f6b },
27296 - { 0x0000981c, 0x00000000 },
27297 - { 0x0000982c, 0x0000a000 },
27298 - { 0x00009830, 0x00000000 },
27299 - { 0x0000983c, 0x00200400 },
27300 - { 0x00009840, 0x206a002e },
27301 - { 0x0000984c, 0x1284233c },
27302 - { 0x00009854, 0x00000859 },
27303 - { 0x00009900, 0x00000000 },
27304 - { 0x00009904, 0x00000000 },
27305 - { 0x00009908, 0x00000000 },
27306 - { 0x0000990c, 0x00000000 },
27307 - { 0x0000991c, 0x10000fff },
27308 - { 0x00009920, 0x05100000 },
27309 - { 0x0000a920, 0x05100000 },
27310 - { 0x0000b920, 0x05100000 },
27311 - { 0x00009928, 0x00000001 },
27312 - { 0x0000992c, 0x00000004 },
27313 - { 0x00009934, 0x1e1f2022 },
27314 - { 0x00009938, 0x0a0b0c0d },
27315 - { 0x0000993c, 0x00000000 },
27316 - { 0x00009948, 0x9280b212 },
27317 - { 0x0000994c, 0x00020028 },
27318 - { 0x00009954, 0x5d50e188 },
27319 - { 0x00009958, 0x00081fff },
27320 - { 0x0000c95c, 0x004b6a8e },
27321 - { 0x0000c968, 0x000003ce },
27322 - { 0x00009970, 0x190fb515 },
27323 - { 0x00009974, 0x00000000 },
27324 - { 0x00009978, 0x00000001 },
27325 - { 0x0000997c, 0x00000000 },
27326 - { 0x00009980, 0x00000000 },
27327 - { 0x00009984, 0x00000000 },
27328 - { 0x00009988, 0x00000000 },
27329 - { 0x0000998c, 0x00000000 },
27330 - { 0x00009990, 0x00000000 },
27331 - { 0x00009994, 0x00000000 },
27332 - { 0x00009998, 0x00000000 },
27333 - { 0x0000999c, 0x00000000 },
27334 - { 0x000099a0, 0x00000000 },
27335 - { 0x000099a4, 0x00000001 },
27336 - { 0x000099a8, 0x001fff00 },
27337 - { 0x000099ac, 0x00000000 },
27338 - { 0x000099b0, 0x03051000 },
27339 - { 0x000099dc, 0x00000000 },
27340 - { 0x000099e0, 0x00000200 },
27341 - { 0x000099e4, 0xaaaaaaaa },
27342 - { 0x000099e8, 0x3c466478 },
27343 - { 0x000099ec, 0x000000aa },
27344 - { 0x000099fc, 0x00001042 },
27345 - { 0x00009b00, 0x00000000 },
27346 - { 0x00009b04, 0x00000001 },
27347 - { 0x00009b08, 0x00000002 },
27348 - { 0x00009b0c, 0x00000003 },
27349 - { 0x00009b10, 0x00000004 },
27350 - { 0x00009b14, 0x00000005 },
27351 - { 0x00009b18, 0x00000008 },
27352 - { 0x00009b1c, 0x00000009 },
27353 - { 0x00009b20, 0x0000000a },
27354 - { 0x00009b24, 0x0000000b },
27355 - { 0x00009b28, 0x0000000c },
27356 - { 0x00009b2c, 0x0000000d },
27357 - { 0x00009b30, 0x00000010 },
27358 - { 0x00009b34, 0x00000011 },
27359 - { 0x00009b38, 0x00000012 },
27360 - { 0x00009b3c, 0x00000013 },
27361 - { 0x00009b40, 0x00000014 },
27362 - { 0x00009b44, 0x00000015 },
27363 - { 0x00009b48, 0x00000018 },
27364 - { 0x00009b4c, 0x00000019 },
27365 - { 0x00009b50, 0x0000001a },
27366 - { 0x00009b54, 0x0000001b },
27367 - { 0x00009b58, 0x0000001c },
27368 - { 0x00009b5c, 0x0000001d },
27369 - { 0x00009b60, 0x00000020 },
27370 - { 0x00009b64, 0x00000021 },
27371 - { 0x00009b68, 0x00000022 },
27372 - { 0x00009b6c, 0x00000023 },
27373 - { 0x00009b70, 0x00000024 },
27374 - { 0x00009b74, 0x00000025 },
27375 - { 0x00009b78, 0x00000028 },
27376 - { 0x00009b7c, 0x00000029 },
27377 - { 0x00009b80, 0x0000002a },
27378 - { 0x00009b84, 0x0000002b },
27379 - { 0x00009b88, 0x0000002c },
27380 - { 0x00009b8c, 0x0000002d },
27381 - { 0x00009b90, 0x00000030 },
27382 - { 0x00009b94, 0x00000031 },
27383 - { 0x00009b98, 0x00000032 },
27384 - { 0x00009b9c, 0x00000033 },
27385 - { 0x00009ba0, 0x00000034 },
27386 - { 0x00009ba4, 0x00000035 },
27387 - { 0x00009ba8, 0x00000035 },
27388 - { 0x00009bac, 0x00000035 },
27389 - { 0x00009bb0, 0x00000035 },
27390 - { 0x00009bb4, 0x00000035 },
27391 - { 0x00009bb8, 0x00000035 },
27392 - { 0x00009bbc, 0x00000035 },
27393 - { 0x00009bc0, 0x00000035 },
27394 - { 0x00009bc4, 0x00000035 },
27395 - { 0x00009bc8, 0x00000035 },
27396 - { 0x00009bcc, 0x00000035 },
27397 - { 0x00009bd0, 0x00000035 },
27398 - { 0x00009bd4, 0x00000035 },
27399 - { 0x00009bd8, 0x00000035 },
27400 - { 0x00009bdc, 0x00000035 },
27401 - { 0x00009be0, 0x00000035 },
27402 - { 0x00009be4, 0x00000035 },
27403 - { 0x00009be8, 0x00000035 },
27404 - { 0x00009bec, 0x00000035 },
27405 - { 0x00009bf0, 0x00000035 },
27406 - { 0x00009bf4, 0x00000035 },
27407 - { 0x00009bf8, 0x00000010 },
27408 - { 0x00009bfc, 0x0000001a },
27409 - { 0x0000a210, 0x40806333 },
27410 - { 0x0000a214, 0x00106c10 },
27411 - { 0x0000a218, 0x009c4060 },
27412 - { 0x0000a220, 0x018830c6 },
27413 - { 0x0000a224, 0x00000400 },
27414 - { 0x0000a228, 0x00000bb5 },
27415 - { 0x0000a22c, 0x00000011 },
27416 - { 0x0000a234, 0x20202020 },
27417 - { 0x0000a238, 0x20202020 },
27418 - { 0x0000a23c, 0x13c889af },
27419 - { 0x0000a240, 0x38490a20 },
27420 - { 0x0000a244, 0x00007bb6 },
27421 - { 0x0000a248, 0x0fff3ffc },
27422 - { 0x0000a24c, 0x00000001 },
27423 - { 0x0000a250, 0x0000a000 },
27424 - { 0x0000a254, 0x00000000 },
27425 - { 0x0000a258, 0x0cc75380 },
27426 - { 0x0000a25c, 0x0f0f0f01 },
27427 - { 0x0000a260, 0xdfa91f01 },
27428 - { 0x0000a268, 0x00000000 },
27429 - { 0x0000a26c, 0x0e79e5c6 },
27430 - { 0x0000b26c, 0x0e79e5c6 },
27431 - { 0x0000c26c, 0x0e79e5c6 },
27432 - { 0x0000d270, 0x00820820 },
27433 - { 0x0000a278, 0x1ce739ce },
27434 - { 0x0000a27c, 0x051701ce },
27435 - { 0x0000a338, 0x00000000 },
27436 - { 0x0000a33c, 0x00000000 },
27437 - { 0x0000a340, 0x00000000 },
27438 - { 0x0000a344, 0x00000000 },
27439 - { 0x0000a348, 0x3fffffff },
27440 - { 0x0000a34c, 0x3fffffff },
27441 - { 0x0000a350, 0x3fffffff },
27442 - { 0x0000a354, 0x0003ffff },
27443 - { 0x0000a358, 0x79a8aa1f },
27444 - { 0x0000d35c, 0x07ffffef },
27445 - { 0x0000d360, 0x0fffffe7 },
27446 - { 0x0000d364, 0x17ffffe5 },
27447 - { 0x0000d368, 0x1fffffe4 },
27448 - { 0x0000d36c, 0x37ffffe3 },
27449 - { 0x0000d370, 0x3fffffe3 },
27450 - { 0x0000d374, 0x57ffffe3 },
27451 - { 0x0000d378, 0x5fffffe2 },
27452 - { 0x0000d37c, 0x7fffffe2 },
27453 - { 0x0000d380, 0x7f3c7bba },
27454 - { 0x0000d384, 0xf3307ff0 },
27455 - { 0x0000a388, 0x08000000 },
27456 - { 0x0000a38c, 0x20202020 },
27457 - { 0x0000a390, 0x20202020 },
27458 - { 0x0000a394, 0x1ce739ce },
27459 - { 0x0000a398, 0x000001ce },
27460 - { 0x0000a39c, 0x00000001 },
27461 - { 0x0000a3a0, 0x00000000 },
27462 - { 0x0000a3a4, 0x00000000 },
27463 - { 0x0000a3a8, 0x00000000 },
27464 - { 0x0000a3ac, 0x00000000 },
27465 - { 0x0000a3b0, 0x00000000 },
27466 - { 0x0000a3b4, 0x00000000 },
27467 - { 0x0000a3b8, 0x00000000 },
27468 - { 0x0000a3bc, 0x00000000 },
27469 - { 0x0000a3c0, 0x00000000 },
27470 - { 0x0000a3c4, 0x00000000 },
27471 - { 0x0000a3c8, 0x00000246 },
27472 - { 0x0000a3cc, 0x20202020 },
27473 - { 0x0000a3d0, 0x20202020 },
27474 - { 0x0000a3d4, 0x20202020 },
27475 - { 0x0000a3dc, 0x1ce739ce },
27476 - { 0x0000a3e0, 0x000001ce },
27477 -};
27478 -
27479 -static const u32 ar5416Bank0[][2] = {
27480 - { 0x000098b0, 0x1e5795e5 },
27481 - { 0x000098e0, 0x02008020 },
27482 -};
27483 -
27484 -static const u32 ar5416BB_RfGain[][3] = {
27485 - { 0x00009a00, 0x00000000, 0x00000000 },
27486 - { 0x00009a04, 0x00000040, 0x00000040 },
27487 - { 0x00009a08, 0x00000080, 0x00000080 },
27488 - { 0x00009a0c, 0x000001a1, 0x00000141 },
27489 - { 0x00009a10, 0x000001e1, 0x00000181 },
27490 - { 0x00009a14, 0x00000021, 0x000001c1 },
27491 - { 0x00009a18, 0x00000061, 0x00000001 },
27492 - { 0x00009a1c, 0x00000168, 0x00000041 },
27493 - { 0x00009a20, 0x000001a8, 0x000001a8 },
27494 - { 0x00009a24, 0x000001e8, 0x000001e8 },
27495 - { 0x00009a28, 0x00000028, 0x00000028 },
27496 - { 0x00009a2c, 0x00000068, 0x00000068 },
27497 - { 0x00009a30, 0x00000189, 0x000000a8 },
27498 - { 0x00009a34, 0x000001c9, 0x00000169 },
27499 - { 0x00009a38, 0x00000009, 0x000001a9 },
27500 - { 0x00009a3c, 0x00000049, 0x000001e9 },
27501 - { 0x00009a40, 0x00000089, 0x00000029 },
27502 - { 0x00009a44, 0x00000170, 0x00000069 },
27503 - { 0x00009a48, 0x000001b0, 0x00000190 },
27504 - { 0x00009a4c, 0x000001f0, 0x000001d0 },
27505 - { 0x00009a50, 0x00000030, 0x00000010 },
27506 - { 0x00009a54, 0x00000070, 0x00000050 },
27507 - { 0x00009a58, 0x00000191, 0x00000090 },
27508 - { 0x00009a5c, 0x000001d1, 0x00000151 },
27509 - { 0x00009a60, 0x00000011, 0x00000191 },
27510 - { 0x00009a64, 0x00000051, 0x000001d1 },
27511 - { 0x00009a68, 0x00000091, 0x00000011 },
27512 - { 0x00009a6c, 0x000001b8, 0x00000051 },
27513 - { 0x00009a70, 0x000001f8, 0x00000198 },
27514 - { 0x00009a74, 0x00000038, 0x000001d8 },
27515 - { 0x00009a78, 0x00000078, 0x00000018 },
27516 - { 0x00009a7c, 0x00000199, 0x00000058 },
27517 - { 0x00009a80, 0x000001d9, 0x00000098 },
27518 - { 0x00009a84, 0x00000019, 0x00000159 },
27519 - { 0x00009a88, 0x00000059, 0x00000199 },
27520 - { 0x00009a8c, 0x00000099, 0x000001d9 },
27521 - { 0x00009a90, 0x000000d9, 0x00000019 },
27522 - { 0x00009a94, 0x000000f9, 0x00000059 },
27523 - { 0x00009a98, 0x000000f9, 0x00000099 },
27524 - { 0x00009a9c, 0x000000f9, 0x000000d9 },
27525 - { 0x00009aa0, 0x000000f9, 0x000000f9 },
27526 - { 0x00009aa4, 0x000000f9, 0x000000f9 },
27527 - { 0x00009aa8, 0x000000f9, 0x000000f9 },
27528 - { 0x00009aac, 0x000000f9, 0x000000f9 },
27529 - { 0x00009ab0, 0x000000f9, 0x000000f9 },
27530 - { 0x00009ab4, 0x000000f9, 0x000000f9 },
27531 - { 0x00009ab8, 0x000000f9, 0x000000f9 },
27532 - { 0x00009abc, 0x000000f9, 0x000000f9 },
27533 - { 0x00009ac0, 0x000000f9, 0x000000f9 },
27534 - { 0x00009ac4, 0x000000f9, 0x000000f9 },
27535 - { 0x00009ac8, 0x000000f9, 0x000000f9 },
27536 - { 0x00009acc, 0x000000f9, 0x000000f9 },
27537 - { 0x00009ad0, 0x000000f9, 0x000000f9 },
27538 - { 0x00009ad4, 0x000000f9, 0x000000f9 },
27539 - { 0x00009ad8, 0x000000f9, 0x000000f9 },
27540 - { 0x00009adc, 0x000000f9, 0x000000f9 },
27541 - { 0x00009ae0, 0x000000f9, 0x000000f9 },
27542 - { 0x00009ae4, 0x000000f9, 0x000000f9 },
27543 - { 0x00009ae8, 0x000000f9, 0x000000f9 },
27544 - { 0x00009aec, 0x000000f9, 0x000000f9 },
27545 - { 0x00009af0, 0x000000f9, 0x000000f9 },
27546 - { 0x00009af4, 0x000000f9, 0x000000f9 },
27547 - { 0x00009af8, 0x000000f9, 0x000000f9 },
27548 - { 0x00009afc, 0x000000f9, 0x000000f9 },
27549 -};
27550 -
27551 -static const u32 ar5416Bank1[][2] = {
27552 - { 0x000098b0, 0x02108421 },
27553 - { 0x000098ec, 0x00000008 },
27554 -};
27555 -
27556 -static const u32 ar5416Bank2[][2] = {
27557 - { 0x000098b0, 0x0e73ff17 },
27558 - { 0x000098e0, 0x00000420 },
27559 -};
27560 -
27561 -static const u32 ar5416Bank3[][3] = {
27562 - { 0x000098f0, 0x01400018, 0x01c00018 },
27563 -};
27564 -
27565 -static const u32 ar5416Bank6[][3] = {
27566 -
27567 - { 0x0000989c, 0x00000000, 0x00000000 },
27568 - { 0x0000989c, 0x00000000, 0x00000000 },
27569 - { 0x0000989c, 0x00000000, 0x00000000 },
27570 - { 0x0000989c, 0x00e00000, 0x00e00000 },
27571 - { 0x0000989c, 0x005e0000, 0x005e0000 },
27572 - { 0x0000989c, 0x00120000, 0x00120000 },
27573 - { 0x0000989c, 0x00620000, 0x00620000 },
27574 - { 0x0000989c, 0x00020000, 0x00020000 },
27575 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27576 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27577 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27578 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
27579 - { 0x0000989c, 0x005f0000, 0x005f0000 },
27580 - { 0x0000989c, 0x00870000, 0x00870000 },
27581 - { 0x0000989c, 0x00f90000, 0x00f90000 },
27582 - { 0x0000989c, 0x007b0000, 0x007b0000 },
27583 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27584 - { 0x0000989c, 0x00f50000, 0x00f50000 },
27585 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
27586 - { 0x0000989c, 0x00110000, 0x00110000 },
27587 - { 0x0000989c, 0x006100a8, 0x006100a8 },
27588 - { 0x0000989c, 0x004210a2, 0x004210a2 },
27589 - { 0x0000989c, 0x0014008f, 0x0014008f },
27590 - { 0x0000989c, 0x00c40003, 0x00c40003 },
27591 - { 0x0000989c, 0x003000f2, 0x003000f2 },
27592 - { 0x0000989c, 0x00440016, 0x00440016 },
27593 - { 0x0000989c, 0x00410040, 0x00410040 },
27594 - { 0x0000989c, 0x0001805e, 0x0001805e },
27595 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
27596 - { 0x0000989c, 0x000000f1, 0x000000f1 },
27597 - { 0x0000989c, 0x00002081, 0x00002081 },
27598 - { 0x0000989c, 0x000000d4, 0x000000d4 },
27599 - { 0x000098d0, 0x0000000f, 0x0010000f },
27600 -};
27601 -
27602 -static const u32 ar5416Bank6TPC[][3] = {
27603 - { 0x0000989c, 0x00000000, 0x00000000 },
27604 - { 0x0000989c, 0x00000000, 0x00000000 },
27605 - { 0x0000989c, 0x00000000, 0x00000000 },
27606 - { 0x0000989c, 0x00e00000, 0x00e00000 },
27607 - { 0x0000989c, 0x005e0000, 0x005e0000 },
27608 - { 0x0000989c, 0x00120000, 0x00120000 },
27609 - { 0x0000989c, 0x00620000, 0x00620000 },
27610 - { 0x0000989c, 0x00020000, 0x00020000 },
27611 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27612 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27613 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27614 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
27615 - { 0x0000989c, 0x005f0000, 0x005f0000 },
27616 - { 0x0000989c, 0x00870000, 0x00870000 },
27617 - { 0x0000989c, 0x00f90000, 0x00f90000 },
27618 - { 0x0000989c, 0x007b0000, 0x007b0000 },
27619 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27620 - { 0x0000989c, 0x00f50000, 0x00f50000 },
27621 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
27622 - { 0x0000989c, 0x00110000, 0x00110000 },
27623 - { 0x0000989c, 0x006100a8, 0x006100a8 },
27624 - { 0x0000989c, 0x00423022, 0x00423022 },
27625 - { 0x0000989c, 0x201400df, 0x201400df },
27626 - { 0x0000989c, 0x00c40002, 0x00c40002 },
27627 - { 0x0000989c, 0x003000f2, 0x003000f2 },
27628 - { 0x0000989c, 0x00440016, 0x00440016 },
27629 - { 0x0000989c, 0x00410040, 0x00410040 },
27630 - { 0x0000989c, 0x0001805e, 0x0001805e },
27631 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
27632 - { 0x0000989c, 0x000000e1, 0x000000e1 },
27633 - { 0x0000989c, 0x00007081, 0x00007081 },
27634 - { 0x0000989c, 0x000000d4, 0x000000d4 },
27635 - { 0x000098d0, 0x0000000f, 0x0010000f },
27636 -};
27637 -
27638 -static const u32 ar5416Bank7[][2] = {
27639 - { 0x0000989c, 0x00000500 },
27640 - { 0x0000989c, 0x00000800 },
27641 - { 0x000098cc, 0x0000000e },
27642 -};
27643 -
27644 -static const u32 ar5416Addac[][2] = {
27645 - {0x0000989c, 0x00000000 },
27646 - {0x0000989c, 0x00000003 },
27647 - {0x0000989c, 0x00000000 },
27648 - {0x0000989c, 0x0000000c },
27649 - {0x0000989c, 0x00000000 },
27650 - {0x0000989c, 0x00000030 },
27651 - {0x0000989c, 0x00000000 },
27652 - {0x0000989c, 0x00000000 },
27653 - {0x0000989c, 0x00000000 },
27654 - {0x0000989c, 0x00000000 },
27655 - {0x0000989c, 0x00000000 },
27656 - {0x0000989c, 0x00000000 },
27657 - {0x0000989c, 0x00000000 },
27658 - {0x0000989c, 0x00000000 },
27659 - {0x0000989c, 0x00000000 },
27660 - {0x0000989c, 0x00000000 },
27661 - {0x0000989c, 0x00000000 },
27662 - {0x0000989c, 0x00000000 },
27663 - {0x0000989c, 0x00000060 },
27664 - {0x0000989c, 0x00000000 },
27665 - {0x0000989c, 0x00000000 },
27666 - {0x0000989c, 0x00000000 },
27667 - {0x0000989c, 0x00000000 },
27668 - {0x0000989c, 0x00000000 },
27669 - {0x0000989c, 0x00000000 },
27670 - {0x0000989c, 0x00000000 },
27671 - {0x0000989c, 0x00000000 },
27672 - {0x0000989c, 0x00000000 },
27673 - {0x0000989c, 0x00000000 },
27674 - {0x0000989c, 0x00000000 },
27675 - {0x0000989c, 0x00000000 },
27676 - {0x0000989c, 0x00000058 },
27677 - {0x0000989c, 0x00000000 },
27678 - {0x0000989c, 0x00000000 },
27679 - {0x0000989c, 0x00000000 },
27680 - {0x0000989c, 0x00000000 },
27681 - {0x000098cc, 0x00000000 },
27682 -};
27683 -
27684 -static const u32 ar5416Modes_9100[][6] = {
27685 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
27686 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
27687 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
27688 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
27689 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
27690 - { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
27691 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
27692 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
27693 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
27694 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
27695 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
27696 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
27697 - { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
27698 - { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
27699 - { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
27700 - { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
27701 - { 0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2, 0x6d48b0e2 },
27702 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec86d2e, 0x7ec84d2e, 0x7ec82d2e },
27703 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
27704 - { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
27705 - { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
27706 - { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
27707 - { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
27708 - { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
27709 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
27710 - { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a11, 0xd00a8a0d, 0xd00a8a0d },
27711 - { 0x00009940, 0x00754604, 0x00754604, 0xfff81204, 0xfff81204, 0xfff81204 },
27712 - { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },
27713 - { 0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e, 0xe250a51e },
27714 - { 0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff, 0x3388ffff },
27715 -#ifdef TB243
27716 - { 0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
27717 - { 0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
27718 - { 0x0000b960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
27719 - { 0x00009964, 0x00000000, 0x00000000, 0x00002210, 0x00002210, 0x00001120 },
27720 -#else
27721 - { 0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
27722 - { 0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
27723 - { 0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
27724 - { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
27725 -#endif
27726 - { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00, 0x001a0c00 },
27727 - { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
27728 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
27729 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
27730 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
27731 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
27732 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27733 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27734 - { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
27735 - { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
27736 - { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
27737 - { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
27738 - { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
27739 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
27740 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
27741 - { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
27742 - { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
27743 - { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
27744 - { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
27745 - { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
27746 - { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
27747 - { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
27748 - { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
27749 - { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
27750 - { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
27751 - { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
27752 - { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
27753 - { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27754 - { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27755 - { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27756 -};
27757 -
27758 -static const u32 ar5416Common_9100[][2] = {
27759 - { 0x0000000c, 0x00000000 },
27760 - { 0x00000030, 0x00020015 },
27761 - { 0x00000034, 0x00000005 },
27762 - { 0x00000040, 0x00000000 },
27763 - { 0x00000044, 0x00000008 },
27764 - { 0x00000048, 0x00000008 },
27765 - { 0x0000004c, 0x00000010 },
27766 - { 0x00000050, 0x00000000 },
27767 - { 0x00000054, 0x0000001f },
27768 - { 0x00000800, 0x00000000 },
27769 - { 0x00000804, 0x00000000 },
27770 - { 0x00000808, 0x00000000 },
27771 - { 0x0000080c, 0x00000000 },
27772 - { 0x00000810, 0x00000000 },
27773 - { 0x00000814, 0x00000000 },
27774 - { 0x00000818, 0x00000000 },
27775 - { 0x0000081c, 0x00000000 },
27776 - { 0x00000820, 0x00000000 },
27777 - { 0x00000824, 0x00000000 },
27778 - { 0x00001040, 0x002ffc0f },
27779 - { 0x00001044, 0x002ffc0f },
27780 - { 0x00001048, 0x002ffc0f },
27781 - { 0x0000104c, 0x002ffc0f },
27782 - { 0x00001050, 0x002ffc0f },
27783 - { 0x00001054, 0x002ffc0f },
27784 - { 0x00001058, 0x002ffc0f },
27785 - { 0x0000105c, 0x002ffc0f },
27786 - { 0x00001060, 0x002ffc0f },
27787 - { 0x00001064, 0x002ffc0f },
27788 - { 0x00001230, 0x00000000 },
27789 - { 0x00001270, 0x00000000 },
27790 - { 0x00001038, 0x00000000 },
27791 - { 0x00001078, 0x00000000 },
27792 - { 0x000010b8, 0x00000000 },
27793 - { 0x000010f8, 0x00000000 },
27794 - { 0x00001138, 0x00000000 },
27795 - { 0x00001178, 0x00000000 },
27796 - { 0x000011b8, 0x00000000 },
27797 - { 0x000011f8, 0x00000000 },
27798 - { 0x00001238, 0x00000000 },
27799 - { 0x00001278, 0x00000000 },
27800 - { 0x000012b8, 0x00000000 },
27801 - { 0x000012f8, 0x00000000 },
27802 - { 0x00001338, 0x00000000 },
27803 - { 0x00001378, 0x00000000 },
27804 - { 0x000013b8, 0x00000000 },
27805 - { 0x000013f8, 0x00000000 },
27806 - { 0x00001438, 0x00000000 },
27807 - { 0x00001478, 0x00000000 },
27808 - { 0x000014b8, 0x00000000 },
27809 - { 0x000014f8, 0x00000000 },
27810 - { 0x00001538, 0x00000000 },
27811 - { 0x00001578, 0x00000000 },
27812 - { 0x000015b8, 0x00000000 },
27813 - { 0x000015f8, 0x00000000 },
27814 - { 0x00001638, 0x00000000 },
27815 - { 0x00001678, 0x00000000 },
27816 - { 0x000016b8, 0x00000000 },
27817 - { 0x000016f8, 0x00000000 },
27818 - { 0x00001738, 0x00000000 },
27819 - { 0x00001778, 0x00000000 },
27820 - { 0x000017b8, 0x00000000 },
27821 - { 0x000017f8, 0x00000000 },
27822 - { 0x0000103c, 0x00000000 },
27823 - { 0x0000107c, 0x00000000 },
27824 - { 0x000010bc, 0x00000000 },
27825 - { 0x000010fc, 0x00000000 },
27826 - { 0x0000113c, 0x00000000 },
27827 - { 0x0000117c, 0x00000000 },
27828 - { 0x000011bc, 0x00000000 },
27829 - { 0x000011fc, 0x00000000 },
27830 - { 0x0000123c, 0x00000000 },
27831 - { 0x0000127c, 0x00000000 },
27832 - { 0x000012bc, 0x00000000 },
27833 - { 0x000012fc, 0x00000000 },
27834 - { 0x0000133c, 0x00000000 },
27835 - { 0x0000137c, 0x00000000 },
27836 - { 0x000013bc, 0x00000000 },
27837 - { 0x000013fc, 0x00000000 },
27838 - { 0x0000143c, 0x00000000 },
27839 - { 0x0000147c, 0x00000000 },
27840 - { 0x00020010, 0x00000003 },
27841 - { 0x00020038, 0x000004c2 },
27842 - { 0x00008004, 0x00000000 },
27843 - { 0x00008008, 0x00000000 },
27844 - { 0x0000800c, 0x00000000 },
27845 - { 0x00008018, 0x00000700 },
27846 - { 0x00008020, 0x00000000 },
27847 - { 0x00008038, 0x00000000 },
27848 - { 0x0000803c, 0x00000000 },
27849 - { 0x00008048, 0x40000000 },
27850 - { 0x00008054, 0x00004000 },
27851 - { 0x00008058, 0x00000000 },
27852 - { 0x0000805c, 0x000fc78f },
27853 - { 0x00008060, 0x0000000f },
27854 - { 0x00008064, 0x00000000 },
27855 - { 0x000080c0, 0x2a82301a },
27856 - { 0x000080c4, 0x05dc01e0 },
27857 - { 0x000080c8, 0x1f402710 },
27858 - { 0x000080cc, 0x01f40000 },
27859 - { 0x000080d0, 0x00001e00 },
27860 - { 0x000080d4, 0x00000000 },
27861 - { 0x000080d8, 0x00400000 },
27862 - { 0x000080e0, 0xffffffff },
27863 - { 0x000080e4, 0x0000ffff },
27864 - { 0x000080e8, 0x003f3f3f },
27865 - { 0x000080ec, 0x00000000 },
27866 - { 0x000080f0, 0x00000000 },
27867 - { 0x000080f4, 0x00000000 },
27868 - { 0x000080f8, 0x00000000 },
27869 - { 0x000080fc, 0x00020000 },
27870 - { 0x00008100, 0x00020000 },
27871 - { 0x00008104, 0x00000001 },
27872 - { 0x00008108, 0x00000052 },
27873 - { 0x0000810c, 0x00000000 },
27874 - { 0x00008110, 0x00000168 },
27875 - { 0x00008118, 0x000100aa },
27876 - { 0x0000811c, 0x00003210 },
27877 - { 0x00008120, 0x08f04800 },
27878 - { 0x00008124, 0x00000000 },
27879 - { 0x00008128, 0x00000000 },
27880 - { 0x0000812c, 0x00000000 },
27881 - { 0x00008130, 0x00000000 },
27882 - { 0x00008134, 0x00000000 },
27883 - { 0x00008138, 0x00000000 },
27884 - { 0x0000813c, 0x00000000 },
27885 - { 0x00008144, 0x00000000 },
27886 - { 0x00008168, 0x00000000 },
27887 - { 0x0000816c, 0x00000000 },
27888 - { 0x00008170, 0x32143320 },
27889 - { 0x00008174, 0xfaa4fa50 },
27890 - { 0x00008178, 0x00000100 },
27891 - { 0x0000817c, 0x00000000 },
27892 - { 0x000081c4, 0x00000000 },
27893 - { 0x000081d0, 0x00003210 },
27894 - { 0x000081ec, 0x00000000 },
27895 - { 0x000081f0, 0x00000000 },
27896 - { 0x000081f4, 0x00000000 },
27897 - { 0x000081f8, 0x00000000 },
27898 - { 0x000081fc, 0x00000000 },
27899 - { 0x00008200, 0x00000000 },
27900 - { 0x00008204, 0x00000000 },
27901 - { 0x00008208, 0x00000000 },
27902 - { 0x0000820c, 0x00000000 },
27903 - { 0x00008210, 0x00000000 },
27904 - { 0x00008214, 0x00000000 },
27905 - { 0x00008218, 0x00000000 },
27906 - { 0x0000821c, 0x00000000 },
27907 - { 0x00008220, 0x00000000 },
27908 - { 0x00008224, 0x00000000 },
27909 - { 0x00008228, 0x00000000 },
27910 - { 0x0000822c, 0x00000000 },
27911 - { 0x00008230, 0x00000000 },
27912 - { 0x00008234, 0x00000000 },
27913 - { 0x00008238, 0x00000000 },
27914 - { 0x0000823c, 0x00000000 },
27915 - { 0x00008240, 0x00100000 },
27916 - { 0x00008244, 0x0010f400 },
27917 - { 0x00008248, 0x00000100 },
27918 - { 0x0000824c, 0x0001e800 },
27919 - { 0x00008250, 0x00000000 },
27920 - { 0x00008254, 0x00000000 },
27921 - { 0x00008258, 0x00000000 },
27922 - { 0x0000825c, 0x400000ff },
27923 - { 0x00008260, 0x00080922 },
27924 - { 0x00008270, 0x00000000 },
27925 - { 0x00008274, 0x40000000 },
27926 - { 0x00008278, 0x003e4180 },
27927 - { 0x0000827c, 0x00000000 },
27928 - { 0x00008284, 0x0000002c },
27929 - { 0x00008288, 0x0000002c },
27930 - { 0x0000828c, 0x00000000 },
27931 - { 0x00008294, 0x00000000 },
27932 - { 0x00008298, 0x00000000 },
27933 - { 0x00008300, 0x00000000 },
27934 - { 0x00008304, 0x00000000 },
27935 - { 0x00008308, 0x00000000 },
27936 - { 0x0000830c, 0x00000000 },
27937 - { 0x00008310, 0x00000000 },
27938 - { 0x00008314, 0x00000000 },
27939 - { 0x00008318, 0x00000000 },
27940 - { 0x00008328, 0x00000000 },
27941 - { 0x0000832c, 0x00000007 },
27942 - { 0x00008330, 0x00000302 },
27943 - { 0x00008334, 0x00000e00 },
27944 - { 0x00008338, 0x00000000 },
27945 - { 0x0000833c, 0x00000000 },
27946 - { 0x00008340, 0x000107ff },
27947 - { 0x00009808, 0x00000000 },
27948 - { 0x0000980c, 0xad848e19 },
27949 - { 0x00009810, 0x7d14e000 },
27950 - { 0x00009814, 0x9c0a9f6b },
27951 - { 0x0000981c, 0x00000000 },
27952 - { 0x0000982c, 0x0000a000 },
27953 - { 0x00009830, 0x00000000 },
27954 - { 0x0000983c, 0x00200400 },
27955 - { 0x00009840, 0x206a01ae },
27956 - { 0x0000984c, 0x1284233c },
27957 - { 0x00009854, 0x00000859 },
27958 - { 0x00009900, 0x00000000 },
27959 - { 0x00009904, 0x00000000 },
27960 - { 0x00009908, 0x00000000 },
27961 - { 0x0000990c, 0x00000000 },
27962 - { 0x0000991c, 0x10000fff },
27963 - { 0x00009920, 0x05100000 },
27964 - { 0x0000a920, 0x05100000 },
27965 - { 0x0000b920, 0x05100000 },
27966 - { 0x00009928, 0x00000001 },
27967 - { 0x0000992c, 0x00000004 },
27968 - { 0x00009934, 0x1e1f2022 },
27969 - { 0x00009938, 0x0a0b0c0d },
27970 - { 0x0000993c, 0x00000000 },
27971 - { 0x00009948, 0x9280b212 },
27972 - { 0x0000994c, 0x00020028 },
27973 - { 0x0000c95c, 0x004b6a8e },
27974 - { 0x0000c968, 0x000003ce },
27975 - { 0x00009970, 0x190fb515 },
27976 - { 0x00009974, 0x00000000 },
27977 - { 0x00009978, 0x00000001 },
27978 - { 0x0000997c, 0x00000000 },
27979 - { 0x00009980, 0x00000000 },
27980 - { 0x00009984, 0x00000000 },
27981 - { 0x00009988, 0x00000000 },
27982 - { 0x0000998c, 0x00000000 },
27983 - { 0x00009990, 0x00000000 },
27984 - { 0x00009994, 0x00000000 },
27985 - { 0x00009998, 0x00000000 },
27986 - { 0x0000999c, 0x00000000 },
27987 - { 0x000099a0, 0x00000000 },
27988 - { 0x000099a4, 0x00000001 },
27989 - { 0x000099a8, 0x201fff00 },
27990 - { 0x000099ac, 0x006f0000 },
27991 - { 0x000099b0, 0x03051000 },
27992 - { 0x000099dc, 0x00000000 },
27993 - { 0x000099e0, 0x00000200 },
27994 - { 0x000099e4, 0xaaaaaaaa },
27995 - { 0x000099e8, 0x3c466478 },
27996 - { 0x000099ec, 0x0cc80caa },
27997 - { 0x000099fc, 0x00001042 },
27998 - { 0x00009b00, 0x00000000 },
27999 - { 0x00009b04, 0x00000001 },
28000 - { 0x00009b08, 0x00000002 },
28001 - { 0x00009b0c, 0x00000003 },
28002 - { 0x00009b10, 0x00000004 },
28003 - { 0x00009b14, 0x00000005 },
28004 - { 0x00009b18, 0x00000008 },
28005 - { 0x00009b1c, 0x00000009 },
28006 - { 0x00009b20, 0x0000000a },
28007 - { 0x00009b24, 0x0000000b },
28008 - { 0x00009b28, 0x0000000c },
28009 - { 0x00009b2c, 0x0000000d },
28010 - { 0x00009b30, 0x00000010 },
28011 - { 0x00009b34, 0x00000011 },
28012 - { 0x00009b38, 0x00000012 },
28013 - { 0x00009b3c, 0x00000013 },
28014 - { 0x00009b40, 0x00000014 },
28015 - { 0x00009b44, 0x00000015 },
28016 - { 0x00009b48, 0x00000018 },
28017 - { 0x00009b4c, 0x00000019 },
28018 - { 0x00009b50, 0x0000001a },
28019 - { 0x00009b54, 0x0000001b },
28020 - { 0x00009b58, 0x0000001c },
28021 - { 0x00009b5c, 0x0000001d },
28022 - { 0x00009b60, 0x00000020 },
28023 - { 0x00009b64, 0x00000021 },
28024 - { 0x00009b68, 0x00000022 },
28025 - { 0x00009b6c, 0x00000023 },
28026 - { 0x00009b70, 0x00000024 },
28027 - { 0x00009b74, 0x00000025 },
28028 - { 0x00009b78, 0x00000028 },
28029 - { 0x00009b7c, 0x00000029 },
28030 - { 0x00009b80, 0x0000002a },
28031 - { 0x00009b84, 0x0000002b },
28032 - { 0x00009b88, 0x0000002c },
28033 - { 0x00009b8c, 0x0000002d },
28034 - { 0x00009b90, 0x00000030 },
28035 - { 0x00009b94, 0x00000031 },
28036 - { 0x00009b98, 0x00000032 },
28037 - { 0x00009b9c, 0x00000033 },
28038 - { 0x00009ba0, 0x00000034 },
28039 - { 0x00009ba4, 0x00000035 },
28040 - { 0x00009ba8, 0x00000035 },
28041 - { 0x00009bac, 0x00000035 },
28042 - { 0x00009bb0, 0x00000035 },
28043 - { 0x00009bb4, 0x00000035 },
28044 - { 0x00009bb8, 0x00000035 },
28045 - { 0x00009bbc, 0x00000035 },
28046 - { 0x00009bc0, 0x00000035 },
28047 - { 0x00009bc4, 0x00000035 },
28048 - { 0x00009bc8, 0x00000035 },
28049 - { 0x00009bcc, 0x00000035 },
28050 - { 0x00009bd0, 0x00000035 },
28051 - { 0x00009bd4, 0x00000035 },
28052 - { 0x00009bd8, 0x00000035 },
28053 - { 0x00009bdc, 0x00000035 },
28054 - { 0x00009be0, 0x00000035 },
28055 - { 0x00009be4, 0x00000035 },
28056 - { 0x00009be8, 0x00000035 },
28057 - { 0x00009bec, 0x00000035 },
28058 - { 0x00009bf0, 0x00000035 },
28059 - { 0x00009bf4, 0x00000035 },
28060 - { 0x00009bf8, 0x00000010 },
28061 - { 0x00009bfc, 0x0000001a },
28062 - { 0x0000a210, 0x40806333 },
28063 - { 0x0000a214, 0x00106c10 },
28064 - { 0x0000a218, 0x009c4060 },
28065 - { 0x0000a220, 0x018830c6 },
28066 - { 0x0000a224, 0x00000400 },
28067 - { 0x0000a228, 0x001a0bb5 },
28068 - { 0x0000a22c, 0x00000000 },
28069 - { 0x0000a234, 0x20202020 },
28070 - { 0x0000a238, 0x20202020 },
28071 - { 0x0000a23c, 0x13c889ae },
28072 - { 0x0000a240, 0x38490a20 },
28073 - { 0x0000a244, 0x00007bb6 },
28074 - { 0x0000a248, 0x0fff3ffc },
28075 - { 0x0000a24c, 0x00000001 },
28076 - { 0x0000a250, 0x0000a000 },
28077 - { 0x0000a254, 0x00000000 },
28078 - { 0x0000a258, 0x0cc75380 },
28079 - { 0x0000a25c, 0x0f0f0f01 },
28080 - { 0x0000a260, 0xdfa91f01 },
28081 - { 0x0000a268, 0x00000001 },
28082 - { 0x0000a26c, 0x0ebae9c6 },
28083 - { 0x0000b26c, 0x0ebae9c6 },
28084 - { 0x0000c26c, 0x0ebae9c6 },
28085 - { 0x0000d270, 0x00820820 },
28086 - { 0x0000a278, 0x1ce739ce },
28087 - { 0x0000a27c, 0x050701ce },
28088 - { 0x0000a338, 0x00000000 },
28089 - { 0x0000a33c, 0x00000000 },
28090 - { 0x0000a340, 0x00000000 },
28091 - { 0x0000a344, 0x00000000 },
28092 - { 0x0000a348, 0x3fffffff },
28093 - { 0x0000a34c, 0x3fffffff },
28094 - { 0x0000a350, 0x3fffffff },
28095 - { 0x0000a354, 0x0003ffff },
28096 - { 0x0000a358, 0x79a8aa33 },
28097 - { 0x0000d35c, 0x07ffffef },
28098 - { 0x0000d360, 0x0fffffe7 },
28099 - { 0x0000d364, 0x17ffffe5 },
28100 - { 0x0000d368, 0x1fffffe4 },
28101 - { 0x0000d36c, 0x37ffffe3 },
28102 - { 0x0000d370, 0x3fffffe3 },
28103 - { 0x0000d374, 0x57ffffe3 },
28104 - { 0x0000d378, 0x5fffffe2 },
28105 - { 0x0000d37c, 0x7fffffe2 },
28106 - { 0x0000d380, 0x7f3c7bba },
28107 - { 0x0000d384, 0xf3307ff0 },
28108 - { 0x0000a388, 0x0c000000 },
28109 - { 0x0000a38c, 0x20202020 },
28110 - { 0x0000a390, 0x20202020 },
28111 - { 0x0000a394, 0x1ce739ce },
28112 - { 0x0000a398, 0x000001ce },
28113 - { 0x0000a39c, 0x00000001 },
28114 - { 0x0000a3a0, 0x00000000 },
28115 - { 0x0000a3a4, 0x00000000 },
28116 - { 0x0000a3a8, 0x00000000 },
28117 - { 0x0000a3ac, 0x00000000 },
28118 - { 0x0000a3b0, 0x00000000 },
28119 - { 0x0000a3b4, 0x00000000 },
28120 - { 0x0000a3b8, 0x00000000 },
28121 - { 0x0000a3bc, 0x00000000 },
28122 - { 0x0000a3c0, 0x00000000 },
28123 - { 0x0000a3c4, 0x00000000 },
28124 - { 0x0000a3c8, 0x00000246 },
28125 - { 0x0000a3cc, 0x20202020 },
28126 - { 0x0000a3d0, 0x20202020 },
28127 - { 0x0000a3d4, 0x20202020 },
28128 - { 0x0000a3dc, 0x1ce739ce },
28129 - { 0x0000a3e0, 0x000001ce },
28130 -};
28131 -
28132 -static const u32 ar5416Bank0_9100[][2] = {
28133 - { 0x000098b0, 0x1e5795e5 },
28134 - { 0x000098e0, 0x02008020 },
28135 -};
28136 -
28137 -static const u32 ar5416BB_RfGain_9100[][3] = {
28138 - { 0x00009a00, 0x00000000, 0x00000000 },
28139 - { 0x00009a04, 0x00000040, 0x00000040 },
28140 - { 0x00009a08, 0x00000080, 0x00000080 },
28141 - { 0x00009a0c, 0x000001a1, 0x00000141 },
28142 - { 0x00009a10, 0x000001e1, 0x00000181 },
28143 - { 0x00009a14, 0x00000021, 0x000001c1 },
28144 - { 0x00009a18, 0x00000061, 0x00000001 },
28145 - { 0x00009a1c, 0x00000168, 0x00000041 },
28146 - { 0x00009a20, 0x000001a8, 0x000001a8 },
28147 - { 0x00009a24, 0x000001e8, 0x000001e8 },
28148 - { 0x00009a28, 0x00000028, 0x00000028 },
28149 - { 0x00009a2c, 0x00000068, 0x00000068 },
28150 - { 0x00009a30, 0x00000189, 0x000000a8 },
28151 - { 0x00009a34, 0x000001c9, 0x00000169 },
28152 - { 0x00009a38, 0x00000009, 0x000001a9 },
28153 - { 0x00009a3c, 0x00000049, 0x000001e9 },
28154 - { 0x00009a40, 0x00000089, 0x00000029 },
28155 - { 0x00009a44, 0x00000170, 0x00000069 },
28156 - { 0x00009a48, 0x000001b0, 0x00000190 },
28157 - { 0x00009a4c, 0x000001f0, 0x000001d0 },
28158 - { 0x00009a50, 0x00000030, 0x00000010 },
28159 - { 0x00009a54, 0x00000070, 0x00000050 },
28160 - { 0x00009a58, 0x00000191, 0x00000090 },
28161 - { 0x00009a5c, 0x000001d1, 0x00000151 },
28162 - { 0x00009a60, 0x00000011, 0x00000191 },
28163 - { 0x00009a64, 0x00000051, 0x000001d1 },
28164 - { 0x00009a68, 0x00000091, 0x00000011 },
28165 - { 0x00009a6c, 0x000001b8, 0x00000051 },
28166 - { 0x00009a70, 0x000001f8, 0x00000198 },
28167 - { 0x00009a74, 0x00000038, 0x000001d8 },
28168 - { 0x00009a78, 0x00000078, 0x00000018 },
28169 - { 0x00009a7c, 0x00000199, 0x00000058 },
28170 - { 0x00009a80, 0x000001d9, 0x00000098 },
28171 - { 0x00009a84, 0x00000019, 0x00000159 },
28172 - { 0x00009a88, 0x00000059, 0x00000199 },
28173 - { 0x00009a8c, 0x00000099, 0x000001d9 },
28174 - { 0x00009a90, 0x000000d9, 0x00000019 },
28175 - { 0x00009a94, 0x000000f9, 0x00000059 },
28176 - { 0x00009a98, 0x000000f9, 0x00000099 },
28177 - { 0x00009a9c, 0x000000f9, 0x000000d9 },
28178 - { 0x00009aa0, 0x000000f9, 0x000000f9 },
28179 - { 0x00009aa4, 0x000000f9, 0x000000f9 },
28180 - { 0x00009aa8, 0x000000f9, 0x000000f9 },
28181 - { 0x00009aac, 0x000000f9, 0x000000f9 },
28182 - { 0x00009ab0, 0x000000f9, 0x000000f9 },
28183 - { 0x00009ab4, 0x000000f9, 0x000000f9 },
28184 - { 0x00009ab8, 0x000000f9, 0x000000f9 },
28185 - { 0x00009abc, 0x000000f9, 0x000000f9 },
28186 - { 0x00009ac0, 0x000000f9, 0x000000f9 },
28187 - { 0x00009ac4, 0x000000f9, 0x000000f9 },
28188 - { 0x00009ac8, 0x000000f9, 0x000000f9 },
28189 - { 0x00009acc, 0x000000f9, 0x000000f9 },
28190 - { 0x00009ad0, 0x000000f9, 0x000000f9 },
28191 - { 0x00009ad4, 0x000000f9, 0x000000f9 },
28192 - { 0x00009ad8, 0x000000f9, 0x000000f9 },
28193 - { 0x00009adc, 0x000000f9, 0x000000f9 },
28194 - { 0x00009ae0, 0x000000f9, 0x000000f9 },
28195 - { 0x00009ae4, 0x000000f9, 0x000000f9 },
28196 - { 0x00009ae8, 0x000000f9, 0x000000f9 },
28197 - { 0x00009aec, 0x000000f9, 0x000000f9 },
28198 - { 0x00009af0, 0x000000f9, 0x000000f9 },
28199 - { 0x00009af4, 0x000000f9, 0x000000f9 },
28200 - { 0x00009af8, 0x000000f9, 0x000000f9 },
28201 - { 0x00009afc, 0x000000f9, 0x000000f9 },
28202 -};
28203 -
28204 -static const u32 ar5416Bank1_9100[][2] = {
28205 - { 0x000098b0, 0x02108421},
28206 - { 0x000098ec, 0x00000008},
28207 -};
28208 -
28209 -static const u32 ar5416Bank2_9100[][2] = {
28210 - { 0x000098b0, 0x0e73ff17},
28211 - { 0x000098e0, 0x00000420},
28212 -};
28213 -
28214 -static const u32 ar5416Bank3_9100[][3] = {
28215 - { 0x000098f0, 0x01400018, 0x01c00018 },
28216 -};
28217 -
28218 -static const u32 ar5416Bank6_9100[][3] = {
28219 -
28220 - { 0x0000989c, 0x00000000, 0x00000000 },
28221 - { 0x0000989c, 0x00000000, 0x00000000 },
28222 - { 0x0000989c, 0x00000000, 0x00000000 },
28223 - { 0x0000989c, 0x00e00000, 0x00e00000 },
28224 - { 0x0000989c, 0x005e0000, 0x005e0000 },
28225 - { 0x0000989c, 0x00120000, 0x00120000 },
28226 - { 0x0000989c, 0x00620000, 0x00620000 },
28227 - { 0x0000989c, 0x00020000, 0x00020000 },
28228 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28229 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28230 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28231 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28232 - { 0x0000989c, 0x005f0000, 0x005f0000 },
28233 - { 0x0000989c, 0x00870000, 0x00870000 },
28234 - { 0x0000989c, 0x00f90000, 0x00f90000 },
28235 - { 0x0000989c, 0x007b0000, 0x007b0000 },
28236 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28237 - { 0x0000989c, 0x00f50000, 0x00f50000 },
28238 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
28239 - { 0x0000989c, 0x00110000, 0x00110000 },
28240 - { 0x0000989c, 0x006100a8, 0x006100a8 },
28241 - { 0x0000989c, 0x004210a2, 0x004210a2 },
28242 - { 0x0000989c, 0x0014000f, 0x0014000f },
28243 - { 0x0000989c, 0x00c40002, 0x00c40002 },
28244 - { 0x0000989c, 0x003000f2, 0x003000f2 },
28245 - { 0x0000989c, 0x00440016, 0x00440016 },
28246 - { 0x0000989c, 0x00410040, 0x00410040 },
28247 - { 0x0000989c, 0x000180d6, 0x000180d6 },
28248 - { 0x0000989c, 0x0000c0aa, 0x0000c0aa },
28249 - { 0x0000989c, 0x000000b1, 0x000000b1 },
28250 - { 0x0000989c, 0x00002000, 0x00002000 },
28251 - { 0x0000989c, 0x000000d4, 0x000000d4 },
28252 - { 0x000098d0, 0x0000000f, 0x0010000f },
28253 -};
28254 -
28255 -
28256 -static const u32 ar5416Bank6TPC_9100[][3] = {
28257 -
28258 - { 0x0000989c, 0x00000000, 0x00000000 },
28259 - { 0x0000989c, 0x00000000, 0x00000000 },
28260 - { 0x0000989c, 0x00000000, 0x00000000 },
28261 - { 0x0000989c, 0x00e00000, 0x00e00000 },
28262 - { 0x0000989c, 0x005e0000, 0x005e0000 },
28263 - { 0x0000989c, 0x00120000, 0x00120000 },
28264 - { 0x0000989c, 0x00620000, 0x00620000 },
28265 - { 0x0000989c, 0x00020000, 0x00020000 },
28266 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28267 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28268 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28269 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
28270 - { 0x0000989c, 0x005f0000, 0x005f0000 },
28271 - { 0x0000989c, 0x00870000, 0x00870000 },
28272 - { 0x0000989c, 0x00f90000, 0x00f90000 },
28273 - { 0x0000989c, 0x007b0000, 0x007b0000 },
28274 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28275 - { 0x0000989c, 0x00f50000, 0x00f50000 },
28276 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
28277 - { 0x0000989c, 0x00110000, 0x00110000 },
28278 - { 0x0000989c, 0x006100a8, 0x006100a8 },
28279 - { 0x0000989c, 0x00423022, 0x00423022 },
28280 - { 0x0000989c, 0x2014008f, 0x2014008f },
28281 - { 0x0000989c, 0x00c40002, 0x00c40002 },
28282 - { 0x0000989c, 0x003000f2, 0x003000f2 },
28283 - { 0x0000989c, 0x00440016, 0x00440016 },
28284 - { 0x0000989c, 0x00410040, 0x00410040 },
28285 - { 0x0000989c, 0x0001805e, 0x0001805e },
28286 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
28287 - { 0x0000989c, 0x000000e1, 0x000000e1 },
28288 - { 0x0000989c, 0x00007080, 0x00007080 },
28289 - { 0x0000989c, 0x000000d4, 0x000000d4 },
28290 - { 0x000098d0, 0x0000000f, 0x0010000f },
28291 -};
28292 -
28293 -static const u32 ar5416Bank7_9100[][2] = {
28294 - { 0x0000989c, 0x00000500 },
28295 - { 0x0000989c, 0x00000800 },
28296 - { 0x000098cc, 0x0000000e },
28297 -};
28298 -
28299 -static const u32 ar5416Addac_9100[][2] = {
28300 - {0x0000989c, 0x00000000 },
28301 - {0x0000989c, 0x00000000 },
28302 - {0x0000989c, 0x00000000 },
28303 - {0x0000989c, 0x00000000 },
28304 - {0x0000989c, 0x00000000 },
28305 - {0x0000989c, 0x00000000 },
28306 - {0x0000989c, 0x00000000 },
28307 - {0x0000989c, 0x00000010 },
28308 - {0x0000989c, 0x00000000 },
28309 - {0x0000989c, 0x00000000 },
28310 - {0x0000989c, 0x00000000 },
28311 - {0x0000989c, 0x00000000 },
28312 - {0x0000989c, 0x00000000 },
28313 - {0x0000989c, 0x00000000 },
28314 - {0x0000989c, 0x00000000 },
28315 - {0x0000989c, 0x00000000 },
28316 - {0x0000989c, 0x00000000 },
28317 - {0x0000989c, 0x00000000 },
28318 - {0x0000989c, 0x00000000 },
28319 - {0x0000989c, 0x00000000 },
28320 - {0x0000989c, 0x00000000 },
28321 - {0x0000989c, 0x000000c0 },
28322 - {0x0000989c, 0x00000015 },
28323 - {0x0000989c, 0x00000000 },
28324 - {0x0000989c, 0x00000000 },
28325 - {0x0000989c, 0x00000000 },
28326 - {0x0000989c, 0x00000000 },
28327 - {0x0000989c, 0x00000000 },
28328 - {0x0000989c, 0x00000000 },
28329 - {0x0000989c, 0x00000000 },
28330 - {0x0000989c, 0x00000000 },
28331 - {0x000098cc, 0x00000000 },
28332 -};
28333 -
28334 -static const u32 ar5416Modes_9160[][6] = {
28335 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
28336 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
28337 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
28338 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
28339 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
28340 - { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
28341 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
28342 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
28343 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
28344 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
28345 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
28346 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
28347 - { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
28348 - { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
28349 - { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
28350 - { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
28351 - { 0x00009850, 0x6c48b4e2, 0x6c48b4e2, 0x6c48b0e2, 0x6c48b0e2, 0x6c48b0e2 },
28352 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
28353 - { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e },
28354 - { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
28355 - { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
28356 - { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
28357 - { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
28358 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
28359 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
28360 - { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
28361 - { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
28362 - { 0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
28363 - { 0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
28364 - { 0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
28365 - { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
28366 - { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
28367 - { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00, 0x001a0c00 },
28368 - { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
28369 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
28370 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
28371 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
28372 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
28373 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28374 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28375 - { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
28376 - { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
28377 - { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
28378 - { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
28379 - { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
28380 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
28381 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
28382 - { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
28383 - { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
28384 - { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
28385 - { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
28386 - { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
28387 - { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
28388 - { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
28389 - { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
28390 - { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
28391 - { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
28392 - { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
28393 - { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
28394 - { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28395 - { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28396 - { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28397 -};
28398 -
28399 -static const u32 ar5416Common_9160[][2] = {
28400 - { 0x0000000c, 0x00000000 },
28401 - { 0x00000030, 0x00020015 },
28402 - { 0x00000034, 0x00000005 },
28403 - { 0x00000040, 0x00000000 },
28404 - { 0x00000044, 0x00000008 },
28405 - { 0x00000048, 0x00000008 },
28406 - { 0x0000004c, 0x00000010 },
28407 - { 0x00000050, 0x00000000 },
28408 - { 0x00000054, 0x0000001f },
28409 - { 0x00000800, 0x00000000 },
28410 - { 0x00000804, 0x00000000 },
28411 - { 0x00000808, 0x00000000 },
28412 - { 0x0000080c, 0x00000000 },
28413 - { 0x00000810, 0x00000000 },
28414 - { 0x00000814, 0x00000000 },
28415 - { 0x00000818, 0x00000000 },
28416 - { 0x0000081c, 0x00000000 },
28417 - { 0x00000820, 0x00000000 },
28418 - { 0x00000824, 0x00000000 },
28419 - { 0x00001040, 0x002ffc0f },
28420 - { 0x00001044, 0x002ffc0f },
28421 - { 0x00001048, 0x002ffc0f },
28422 - { 0x0000104c, 0x002ffc0f },
28423 - { 0x00001050, 0x002ffc0f },
28424 - { 0x00001054, 0x002ffc0f },
28425 - { 0x00001058, 0x002ffc0f },
28426 - { 0x0000105c, 0x002ffc0f },
28427 - { 0x00001060, 0x002ffc0f },
28428 - { 0x00001064, 0x002ffc0f },
28429 - { 0x00001230, 0x00000000 },
28430 - { 0x00001270, 0x00000000 },
28431 - { 0x00001038, 0x00000000 },
28432 - { 0x00001078, 0x00000000 },
28433 - { 0x000010b8, 0x00000000 },
28434 - { 0x000010f8, 0x00000000 },
28435 - { 0x00001138, 0x00000000 },
28436 - { 0x00001178, 0x00000000 },
28437 - { 0x000011b8, 0x00000000 },
28438 - { 0x000011f8, 0x00000000 },
28439 - { 0x00001238, 0x00000000 },
28440 - { 0x00001278, 0x00000000 },
28441 - { 0x000012b8, 0x00000000 },
28442 - { 0x000012f8, 0x00000000 },
28443 - { 0x00001338, 0x00000000 },
28444 - { 0x00001378, 0x00000000 },
28445 - { 0x000013b8, 0x00000000 },
28446 - { 0x000013f8, 0x00000000 },
28447 - { 0x00001438, 0x00000000 },
28448 - { 0x00001478, 0x00000000 },
28449 - { 0x000014b8, 0x00000000 },
28450 - { 0x000014f8, 0x00000000 },
28451 - { 0x00001538, 0x00000000 },
28452 - { 0x00001578, 0x00000000 },
28453 - { 0x000015b8, 0x00000000 },
28454 - { 0x000015f8, 0x00000000 },
28455 - { 0x00001638, 0x00000000 },
28456 - { 0x00001678, 0x00000000 },
28457 - { 0x000016b8, 0x00000000 },
28458 - { 0x000016f8, 0x00000000 },
28459 - { 0x00001738, 0x00000000 },
28460 - { 0x00001778, 0x00000000 },
28461 - { 0x000017b8, 0x00000000 },
28462 - { 0x000017f8, 0x00000000 },
28463 - { 0x0000103c, 0x00000000 },
28464 - { 0x0000107c, 0x00000000 },
28465 - { 0x000010bc, 0x00000000 },
28466 - { 0x000010fc, 0x00000000 },
28467 - { 0x0000113c, 0x00000000 },
28468 - { 0x0000117c, 0x00000000 },
28469 - { 0x000011bc, 0x00000000 },
28470 - { 0x000011fc, 0x00000000 },
28471 - { 0x0000123c, 0x00000000 },
28472 - { 0x0000127c, 0x00000000 },
28473 - { 0x000012bc, 0x00000000 },
28474 - { 0x000012fc, 0x00000000 },
28475 - { 0x0000133c, 0x00000000 },
28476 - { 0x0000137c, 0x00000000 },
28477 - { 0x000013bc, 0x00000000 },
28478 - { 0x000013fc, 0x00000000 },
28479 - { 0x0000143c, 0x00000000 },
28480 - { 0x0000147c, 0x00000000 },
28481 - { 0x00004030, 0x00000002 },
28482 - { 0x0000403c, 0x00000002 },
28483 - { 0x00007010, 0x00000020 },
28484 - { 0x00007038, 0x000004c2 },
28485 - { 0x00008004, 0x00000000 },
28486 - { 0x00008008, 0x00000000 },
28487 - { 0x0000800c, 0x00000000 },
28488 - { 0x00008018, 0x00000700 },
28489 - { 0x00008020, 0x00000000 },
28490 - { 0x00008038, 0x00000000 },
28491 - { 0x0000803c, 0x00000000 },
28492 - { 0x00008048, 0x40000000 },
28493 - { 0x00008054, 0x00000000 },
28494 - { 0x00008058, 0x00000000 },
28495 - { 0x0000805c, 0x000fc78f },
28496 - { 0x00008060, 0x0000000f },
28497 - { 0x00008064, 0x00000000 },
28498 - { 0x000080c0, 0x2a82301a },
28499 - { 0x000080c4, 0x05dc01e0 },
28500 - { 0x000080c8, 0x1f402710 },
28501 - { 0x000080cc, 0x01f40000 },
28502 - { 0x000080d0, 0x00001e00 },
28503 - { 0x000080d4, 0x00000000 },
28504 - { 0x000080d8, 0x00400000 },
28505 - { 0x000080e0, 0xffffffff },
28506 - { 0x000080e4, 0x0000ffff },
28507 - { 0x000080e8, 0x003f3f3f },
28508 - { 0x000080ec, 0x00000000 },
28509 - { 0x000080f0, 0x00000000 },
28510 - { 0x000080f4, 0x00000000 },
28511 - { 0x000080f8, 0x00000000 },
28512 - { 0x000080fc, 0x00020000 },
28513 - { 0x00008100, 0x00020000 },
28514 - { 0x00008104, 0x00000001 },
28515 - { 0x00008108, 0x00000052 },
28516 - { 0x0000810c, 0x00000000 },
28517 - { 0x00008110, 0x00000168 },
28518 - { 0x00008118, 0x000100aa },
28519 - { 0x0000811c, 0x00003210 },
28520 - { 0x00008120, 0x08f04800 },
28521 - { 0x00008124, 0x00000000 },
28522 - { 0x00008128, 0x00000000 },
28523 - { 0x0000812c, 0x00000000 },
28524 - { 0x00008130, 0x00000000 },
28525 - { 0x00008134, 0x00000000 },
28526 - { 0x00008138, 0x00000000 },
28527 - { 0x0000813c, 0x00000000 },
28528 - { 0x00008144, 0xffffffff },
28529 - { 0x00008168, 0x00000000 },
28530 - { 0x0000816c, 0x00000000 },
28531 - { 0x00008170, 0x32143320 },
28532 - { 0x00008174, 0xfaa4fa50 },
28533 - { 0x00008178, 0x00000100 },
28534 - { 0x0000817c, 0x00000000 },
28535 - { 0x000081c4, 0x00000000 },
28536 - { 0x000081d0, 0x00003210 },
28537 - { 0x000081ec, 0x00000000 },
28538 - { 0x000081f0, 0x00000000 },
28539 - { 0x000081f4, 0x00000000 },
28540 - { 0x000081f8, 0x00000000 },
28541 - { 0x000081fc, 0x00000000 },
28542 - { 0x00008200, 0x00000000 },
28543 - { 0x00008204, 0x00000000 },
28544 - { 0x00008208, 0x00000000 },
28545 - { 0x0000820c, 0x00000000 },
28546 - { 0x00008210, 0x00000000 },
28547 - { 0x00008214, 0x00000000 },
28548 - { 0x00008218, 0x00000000 },
28549 - { 0x0000821c, 0x00000000 },
28550 - { 0x00008220, 0x00000000 },
28551 - { 0x00008224, 0x00000000 },
28552 - { 0x00008228, 0x00000000 },
28553 - { 0x0000822c, 0x00000000 },
28554 - { 0x00008230, 0x00000000 },
28555 - { 0x00008234, 0x00000000 },
28556 - { 0x00008238, 0x00000000 },
28557 - { 0x0000823c, 0x00000000 },
28558 - { 0x00008240, 0x00100000 },
28559 - { 0x00008244, 0x0010f400 },
28560 - { 0x00008248, 0x00000100 },
28561 - { 0x0000824c, 0x0001e800 },
28562 - { 0x00008250, 0x00000000 },
28563 - { 0x00008254, 0x00000000 },
28564 - { 0x00008258, 0x00000000 },
28565 - { 0x0000825c, 0x400000ff },
28566 - { 0x00008260, 0x00080922 },
28567 - { 0x00008270, 0x00000000 },
28568 - { 0x00008274, 0x40000000 },
28569 - { 0x00008278, 0x003e4180 },
28570 - { 0x0000827c, 0x00000000 },
28571 - { 0x00008284, 0x0000002c },
28572 - { 0x00008288, 0x0000002c },
28573 - { 0x0000828c, 0x00000000 },
28574 - { 0x00008294, 0x00000000 },
28575 - { 0x00008298, 0x00000000 },
28576 - { 0x00008300, 0x00000000 },
28577 - { 0x00008304, 0x00000000 },
28578 - { 0x00008308, 0x00000000 },
28579 - { 0x0000830c, 0x00000000 },
28580 - { 0x00008310, 0x00000000 },
28581 - { 0x00008314, 0x00000000 },
28582 - { 0x00008318, 0x00000000 },
28583 - { 0x00008328, 0x00000000 },
28584 - { 0x0000832c, 0x00000007 },
28585 - { 0x00008330, 0x00000302 },
28586 - { 0x00008334, 0x00000e00 },
28587 - { 0x00008338, 0x00ff0000 },
28588 - { 0x0000833c, 0x00000000 },
28589 - { 0x00008340, 0x000107ff },
28590 - { 0x00009808, 0x00000000 },
28591 - { 0x0000980c, 0xad848e19 },
28592 - { 0x00009810, 0x7d14e000 },
28593 - { 0x00009814, 0x9c0a9f6b },
28594 - { 0x0000981c, 0x00000000 },
28595 - { 0x0000982c, 0x0000a000 },
28596 - { 0x00009830, 0x00000000 },
28597 - { 0x0000983c, 0x00200400 },
28598 - { 0x00009840, 0x206a01ae },
28599 - { 0x0000984c, 0x1284233c },
28600 - { 0x00009854, 0x00000859 },
28601 - { 0x00009900, 0x00000000 },
28602 - { 0x00009904, 0x00000000 },
28603 - { 0x00009908, 0x00000000 },
28604 - { 0x0000990c, 0x00000000 },
28605 - { 0x0000991c, 0x10000fff },
28606 - { 0x00009920, 0x05100000 },
28607 - { 0x0000a920, 0x05100000 },
28608 - { 0x0000b920, 0x05100000 },
28609 - { 0x00009928, 0x00000001 },
28610 - { 0x0000992c, 0x00000004 },
28611 - { 0x00009934, 0x1e1f2022 },
28612 - { 0x00009938, 0x0a0b0c0d },
28613 - { 0x0000993c, 0x00000000 },
28614 - { 0x00009948, 0x9280b212 },
28615 - { 0x0000994c, 0x00020028 },
28616 - { 0x00009954, 0x5f3ca3de },
28617 - { 0x00009958, 0x2108ecff },
28618 - { 0x00009940, 0x00750604 },
28619 - { 0x0000c95c, 0x004b6a8e },
28620 - { 0x00009970, 0x190fb515 },
28621 - { 0x00009974, 0x00000000 },
28622 - { 0x00009978, 0x00000001 },
28623 - { 0x0000997c, 0x00000000 },
28624 - { 0x00009980, 0x00000000 },
28625 - { 0x00009984, 0x00000000 },
28626 - { 0x00009988, 0x00000000 },
28627 - { 0x0000998c, 0x00000000 },
28628 - { 0x00009990, 0x00000000 },
28629 - { 0x00009994, 0x00000000 },
28630 - { 0x00009998, 0x00000000 },
28631 - { 0x0000999c, 0x00000000 },
28632 - { 0x000099a0, 0x00000000 },
28633 - { 0x000099a4, 0x00000001 },
28634 - { 0x000099a8, 0x201fff00 },
28635 - { 0x000099ac, 0x006f0000 },
28636 - { 0x000099b0, 0x03051000 },
28637 - { 0x000099dc, 0x00000000 },
28638 - { 0x000099e0, 0x00000200 },
28639 - { 0x000099e4, 0xaaaaaaaa },
28640 - { 0x000099e8, 0x3c466478 },
28641 - { 0x000099ec, 0x0cc80caa },
28642 - { 0x000099fc, 0x00001042 },
28643 - { 0x00009b00, 0x00000000 },
28644 - { 0x00009b04, 0x00000001 },
28645 - { 0x00009b08, 0x00000002 },
28646 - { 0x00009b0c, 0x00000003 },
28647 - { 0x00009b10, 0x00000004 },
28648 - { 0x00009b14, 0x00000005 },
28649 - { 0x00009b18, 0x00000008 },
28650 - { 0x00009b1c, 0x00000009 },
28651 - { 0x00009b20, 0x0000000a },
28652 - { 0x00009b24, 0x0000000b },
28653 - { 0x00009b28, 0x0000000c },
28654 - { 0x00009b2c, 0x0000000d },
28655 - { 0x00009b30, 0x00000010 },
28656 - { 0x00009b34, 0x00000011 },
28657 - { 0x00009b38, 0x00000012 },
28658 - { 0x00009b3c, 0x00000013 },
28659 - { 0x00009b40, 0x00000014 },
28660 - { 0x00009b44, 0x00000015 },
28661 - { 0x00009b48, 0x00000018 },
28662 - { 0x00009b4c, 0x00000019 },
28663 - { 0x00009b50, 0x0000001a },
28664 - { 0x00009b54, 0x0000001b },
28665 - { 0x00009b58, 0x0000001c },
28666 - { 0x00009b5c, 0x0000001d },
28667 - { 0x00009b60, 0x00000020 },
28668 - { 0x00009b64, 0x00000021 },
28669 - { 0x00009b68, 0x00000022 },
28670 - { 0x00009b6c, 0x00000023 },
28671 - { 0x00009b70, 0x00000024 },
28672 - { 0x00009b74, 0x00000025 },
28673 - { 0x00009b78, 0x00000028 },
28674 - { 0x00009b7c, 0x00000029 },
28675 - { 0x00009b80, 0x0000002a },
28676 - { 0x00009b84, 0x0000002b },
28677 - { 0x00009b88, 0x0000002c },
28678 - { 0x00009b8c, 0x0000002d },
28679 - { 0x00009b90, 0x00000030 },
28680 - { 0x00009b94, 0x00000031 },
28681 - { 0x00009b98, 0x00000032 },
28682 - { 0x00009b9c, 0x00000033 },
28683 - { 0x00009ba0, 0x00000034 },
28684 - { 0x00009ba4, 0x00000035 },
28685 - { 0x00009ba8, 0x00000035 },
28686 - { 0x00009bac, 0x00000035 },
28687 - { 0x00009bb0, 0x00000035 },
28688 - { 0x00009bb4, 0x00000035 },
28689 - { 0x00009bb8, 0x00000035 },
28690 - { 0x00009bbc, 0x00000035 },
28691 - { 0x00009bc0, 0x00000035 },
28692 - { 0x00009bc4, 0x00000035 },
28693 - { 0x00009bc8, 0x00000035 },
28694 - { 0x00009bcc, 0x00000035 },
28695 - { 0x00009bd0, 0x00000035 },
28696 - { 0x00009bd4, 0x00000035 },
28697 - { 0x00009bd8, 0x00000035 },
28698 - { 0x00009bdc, 0x00000035 },
28699 - { 0x00009be0, 0x00000035 },
28700 - { 0x00009be4, 0x00000035 },
28701 - { 0x00009be8, 0x00000035 },
28702 - { 0x00009bec, 0x00000035 },
28703 - { 0x00009bf0, 0x00000035 },
28704 - { 0x00009bf4, 0x00000035 },
28705 - { 0x00009bf8, 0x00000010 },
28706 - { 0x00009bfc, 0x0000001a },
28707 - { 0x0000a210, 0x40806333 },
28708 - { 0x0000a214, 0x00106c10 },
28709 - { 0x0000a218, 0x009c4060 },
28710 - { 0x0000a220, 0x018830c6 },
28711 - { 0x0000a224, 0x00000400 },
28712 - { 0x0000a228, 0x001a0bb5 },
28713 - { 0x0000a22c, 0x00000000 },
28714 - { 0x0000a234, 0x20202020 },
28715 - { 0x0000a238, 0x20202020 },
28716 - { 0x0000a23c, 0x13c889af },
28717 - { 0x0000a240, 0x38490a20 },
28718 - { 0x0000a244, 0x00007bb6 },
28719 - { 0x0000a248, 0x0fff3ffc },
28720 - { 0x0000a24c, 0x00000001 },
28721 - { 0x0000a250, 0x0000e000 },
28722 - { 0x0000a254, 0x00000000 },
28723 - { 0x0000a258, 0x0cc75380 },
28724 - { 0x0000a25c, 0x0f0f0f01 },
28725 - { 0x0000a260, 0xdfa91f01 },
28726 - { 0x0000a268, 0x00000001 },
28727 - { 0x0000a26c, 0x0ebae9c6 },
28728 - { 0x0000b26c, 0x0ebae9c6 },
28729 - { 0x0000c26c, 0x0ebae9c6 },
28730 - { 0x0000d270, 0x00820820 },
28731 - { 0x0000a278, 0x1ce739ce },
28732 - { 0x0000a27c, 0x050701ce },
28733 - { 0x0000a338, 0x00000000 },
28734 - { 0x0000a33c, 0x00000000 },
28735 - { 0x0000a340, 0x00000000 },
28736 - { 0x0000a344, 0x00000000 },
28737 - { 0x0000a348, 0x3fffffff },
28738 - { 0x0000a34c, 0x3fffffff },
28739 - { 0x0000a350, 0x3fffffff },
28740 - { 0x0000a354, 0x0003ffff },
28741 - { 0x0000a358, 0x79bfaa03 },
28742 - { 0x0000d35c, 0x07ffffef },
28743 - { 0x0000d360, 0x0fffffe7 },
28744 - { 0x0000d364, 0x17ffffe5 },
28745 - { 0x0000d368, 0x1fffffe4 },
28746 - { 0x0000d36c, 0x37ffffe3 },
28747 - { 0x0000d370, 0x3fffffe3 },
28748 - { 0x0000d374, 0x57ffffe3 },
28749 - { 0x0000d378, 0x5fffffe2 },
28750 - { 0x0000d37c, 0x7fffffe2 },
28751 - { 0x0000d380, 0x7f3c7bba },
28752 - { 0x0000d384, 0xf3307ff0 },
28753 - { 0x0000a388, 0x0c000000 },
28754 - { 0x0000a38c, 0x20202020 },
28755 - { 0x0000a390, 0x20202020 },
28756 - { 0x0000a394, 0x1ce739ce },
28757 - { 0x0000a398, 0x000001ce },
28758 - { 0x0000a39c, 0x00000001 },
28759 - { 0x0000a3a0, 0x00000000 },
28760 - { 0x0000a3a4, 0x00000000 },
28761 - { 0x0000a3a8, 0x00000000 },
28762 - { 0x0000a3ac, 0x00000000 },
28763 - { 0x0000a3b0, 0x00000000 },
28764 - { 0x0000a3b4, 0x00000000 },
28765 - { 0x0000a3b8, 0x00000000 },
28766 - { 0x0000a3bc, 0x00000000 },
28767 - { 0x0000a3c0, 0x00000000 },
28768 - { 0x0000a3c4, 0x00000000 },
28769 - { 0x0000a3c8, 0x00000246 },
28770 - { 0x0000a3cc, 0x20202020 },
28771 - { 0x0000a3d0, 0x20202020 },
28772 - { 0x0000a3d4, 0x20202020 },
28773 - { 0x0000a3dc, 0x1ce739ce },
28774 - { 0x0000a3e0, 0x000001ce },
28775 -};
28776 -
28777 -static const u32 ar5416Bank0_9160[][2] = {
28778 - { 0x000098b0, 0x1e5795e5 },
28779 - { 0x000098e0, 0x02008020 },
28780 -};
28781 -
28782 -static const u32 ar5416BB_RfGain_9160[][3] = {
28783 - { 0x00009a00, 0x00000000, 0x00000000 },
28784 - { 0x00009a04, 0x00000040, 0x00000040 },
28785 - { 0x00009a08, 0x00000080, 0x00000080 },
28786 - { 0x00009a0c, 0x000001a1, 0x00000141 },
28787 - { 0x00009a10, 0x000001e1, 0x00000181 },
28788 - { 0x00009a14, 0x00000021, 0x000001c1 },
28789 - { 0x00009a18, 0x00000061, 0x00000001 },
28790 - { 0x00009a1c, 0x00000168, 0x00000041 },
28791 - { 0x00009a20, 0x000001a8, 0x000001a8 },
28792 - { 0x00009a24, 0x000001e8, 0x000001e8 },
28793 - { 0x00009a28, 0x00000028, 0x00000028 },
28794 - { 0x00009a2c, 0x00000068, 0x00000068 },
28795 - { 0x00009a30, 0x00000189, 0x000000a8 },
28796 - { 0x00009a34, 0x000001c9, 0x00000169 },
28797 - { 0x00009a38, 0x00000009, 0x000001a9 },
28798 - { 0x00009a3c, 0x00000049, 0x000001e9 },
28799 - { 0x00009a40, 0x00000089, 0x00000029 },
28800 - { 0x00009a44, 0x00000170, 0x00000069 },
28801 - { 0x00009a48, 0x000001b0, 0x00000190 },
28802 - { 0x00009a4c, 0x000001f0, 0x000001d0 },
28803 - { 0x00009a50, 0x00000030, 0x00000010 },
28804 - { 0x00009a54, 0x00000070, 0x00000050 },
28805 - { 0x00009a58, 0x00000191, 0x00000090 },
28806 - { 0x00009a5c, 0x000001d1, 0x00000151 },
28807 - { 0x00009a60, 0x00000011, 0x00000191 },
28808 - { 0x00009a64, 0x00000051, 0x000001d1 },
28809 - { 0x00009a68, 0x00000091, 0x00000011 },
28810 - { 0x00009a6c, 0x000001b8, 0x00000051 },
28811 - { 0x00009a70, 0x000001f8, 0x00000198 },
28812 - { 0x00009a74, 0x00000038, 0x000001d8 },
28813 - { 0x00009a78, 0x00000078, 0x00000018 },
28814 - { 0x00009a7c, 0x00000199, 0x00000058 },
28815 - { 0x00009a80, 0x000001d9, 0x00000098 },
28816 - { 0x00009a84, 0x00000019, 0x00000159 },
28817 - { 0x00009a88, 0x00000059, 0x00000199 },
28818 - { 0x00009a8c, 0x00000099, 0x000001d9 },
28819 - { 0x00009a90, 0x000000d9, 0x00000019 },
28820 - { 0x00009a94, 0x000000f9, 0x00000059 },
28821 - { 0x00009a98, 0x000000f9, 0x00000099 },
28822 - { 0x00009a9c, 0x000000f9, 0x000000d9 },
28823 - { 0x00009aa0, 0x000000f9, 0x000000f9 },
28824 - { 0x00009aa4, 0x000000f9, 0x000000f9 },
28825 - { 0x00009aa8, 0x000000f9, 0x000000f9 },
28826 - { 0x00009aac, 0x000000f9, 0x000000f9 },
28827 - { 0x00009ab0, 0x000000f9, 0x000000f9 },
28828 - { 0x00009ab4, 0x000000f9, 0x000000f9 },
28829 - { 0x00009ab8, 0x000000f9, 0x000000f9 },
28830 - { 0x00009abc, 0x000000f9, 0x000000f9 },
28831 - { 0x00009ac0, 0x000000f9, 0x000000f9 },
28832 - { 0x00009ac4, 0x000000f9, 0x000000f9 },
28833 - { 0x00009ac8, 0x000000f9, 0x000000f9 },
28834 - { 0x00009acc, 0x000000f9, 0x000000f9 },
28835 - { 0x00009ad0, 0x000000f9, 0x000000f9 },
28836 - { 0x00009ad4, 0x000000f9, 0x000000f9 },
28837 - { 0x00009ad8, 0x000000f9, 0x000000f9 },
28838 - { 0x00009adc, 0x000000f9, 0x000000f9 },
28839 - { 0x00009ae0, 0x000000f9, 0x000000f9 },
28840 - { 0x00009ae4, 0x000000f9, 0x000000f9 },
28841 - { 0x00009ae8, 0x000000f9, 0x000000f9 },
28842 - { 0x00009aec, 0x000000f9, 0x000000f9 },
28843 - { 0x00009af0, 0x000000f9, 0x000000f9 },
28844 - { 0x00009af4, 0x000000f9, 0x000000f9 },
28845 - { 0x00009af8, 0x000000f9, 0x000000f9 },
28846 - { 0x00009afc, 0x000000f9, 0x000000f9 },
28847 -};
28848 -
28849 -static const u32 ar5416Bank1_9160[][2] = {
28850 - { 0x000098b0, 0x02108421 },
28851 - { 0x000098ec, 0x00000008 },
28852 -};
28853 -
28854 -static const u32 ar5416Bank2_9160[][2] = {
28855 - { 0x000098b0, 0x0e73ff17 },
28856 - { 0x000098e0, 0x00000420 },
28857 -};
28858 -
28859 -static const u32 ar5416Bank3_9160[][3] = {
28860 - { 0x000098f0, 0x01400018, 0x01c00018 },
28861 -};
28862 -
28863 -static const u32 ar5416Bank6_9160[][3] = {
28864 - { 0x0000989c, 0x00000000, 0x00000000 },
28865 - { 0x0000989c, 0x00000000, 0x00000000 },
28866 - { 0x0000989c, 0x00000000, 0x00000000 },
28867 - { 0x0000989c, 0x00e00000, 0x00e00000 },
28868 - { 0x0000989c, 0x005e0000, 0x005e0000 },
28869 - { 0x0000989c, 0x00120000, 0x00120000 },
28870 - { 0x0000989c, 0x00620000, 0x00620000 },
28871 - { 0x0000989c, 0x00020000, 0x00020000 },
28872 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28873 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28874 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28875 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
28876 - { 0x0000989c, 0x005f0000, 0x005f0000 },
28877 - { 0x0000989c, 0x00870000, 0x00870000 },
28878 - { 0x0000989c, 0x00f90000, 0x00f90000 },
28879 - { 0x0000989c, 0x007b0000, 0x007b0000 },
28880 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28881 - { 0x0000989c, 0x00f50000, 0x00f50000 },
28882 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
28883 - { 0x0000989c, 0x00110000, 0x00110000 },
28884 - { 0x0000989c, 0x006100a8, 0x006100a8 },
28885 - { 0x0000989c, 0x004210a2, 0x004210a2 },
28886 - { 0x0000989c, 0x0014008f, 0x0014008f },
28887 - { 0x0000989c, 0x00c40003, 0x00c40003 },
28888 - { 0x0000989c, 0x003000f2, 0x003000f2 },
28889 - { 0x0000989c, 0x00440016, 0x00440016 },
28890 - { 0x0000989c, 0x00410040, 0x00410040 },
28891 - { 0x0000989c, 0x0001805e, 0x0001805e },
28892 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
28893 - { 0x0000989c, 0x000000f1, 0x000000f1 },
28894 - { 0x0000989c, 0x00002081, 0x00002081 },
28895 - { 0x0000989c, 0x000000d4, 0x000000d4 },
28896 - { 0x000098d0, 0x0000000f, 0x0010000f },
28897 -};
28898 -
28899 -static const u32 ar5416Bank6TPC_9160[][3] = {
28900 - { 0x0000989c, 0x00000000, 0x00000000 },
28901 - { 0x0000989c, 0x00000000, 0x00000000 },
28902 - { 0x0000989c, 0x00000000, 0x00000000 },
28903 - { 0x0000989c, 0x00e00000, 0x00e00000 },
28904 - { 0x0000989c, 0x005e0000, 0x005e0000 },
28905 - { 0x0000989c, 0x00120000, 0x00120000 },
28906 - { 0x0000989c, 0x00620000, 0x00620000 },
28907 - { 0x0000989c, 0x00020000, 0x00020000 },
28908 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28909 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28910 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28911 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
28912 - { 0x0000989c, 0x005f0000, 0x005f0000 },
28913 - { 0x0000989c, 0x00870000, 0x00870000 },
28914 - { 0x0000989c, 0x00f90000, 0x00f90000 },
28915 - { 0x0000989c, 0x007b0000, 0x007b0000 },
28916 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28917 - { 0x0000989c, 0x00f50000, 0x00f50000 },
28918 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
28919 - { 0x0000989c, 0x00110000, 0x00110000 },
28920 - { 0x0000989c, 0x006100a8, 0x006100a8 },
28921 - { 0x0000989c, 0x00423022, 0x00423022 },
28922 - { 0x0000989c, 0x2014008f, 0x2014008f },
28923 - { 0x0000989c, 0x00c40002, 0x00c40002 },
28924 - { 0x0000989c, 0x003000f2, 0x003000f2 },
28925 - { 0x0000989c, 0x00440016, 0x00440016 },
28926 - { 0x0000989c, 0x00410040, 0x00410040 },
28927 - { 0x0000989c, 0x0001805e, 0x0001805e },
28928 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
28929 - { 0x0000989c, 0x000000e1, 0x000000e1 },
28930 - { 0x0000989c, 0x00007080, 0x00007080 },
28931 - { 0x0000989c, 0x000000d4, 0x000000d4 },
28932 - { 0x000098d0, 0x0000000f, 0x0010000f },
28933 -};
28934 -
28935 -static const u32 ar5416Bank7_9160[][2] = {
28936 - { 0x0000989c, 0x00000500 },
28937 - { 0x0000989c, 0x00000800 },
28938 - { 0x000098cc, 0x0000000e },
28939 -};
28940 -
28941 -static u32 ar5416Addac_9160[][2] = {
28942 - {0x0000989c, 0x00000000 },
28943 - {0x0000989c, 0x00000000 },
28944 - {0x0000989c, 0x00000000 },
28945 - {0x0000989c, 0x00000000 },
28946 - {0x0000989c, 0x00000000 },
28947 - {0x0000989c, 0x00000000 },
28948 - {0x0000989c, 0x000000c0 },
28949 - {0x0000989c, 0x00000018 },
28950 - {0x0000989c, 0x00000004 },
28951 - {0x0000989c, 0x00000000 },
28952 - {0x0000989c, 0x00000000 },
28953 - {0x0000989c, 0x00000000 },
28954 - {0x0000989c, 0x00000000 },
28955 - {0x0000989c, 0x00000000 },
28956 - {0x0000989c, 0x00000000 },
28957 - {0x0000989c, 0x00000000 },
28958 - {0x0000989c, 0x00000000 },
28959 - {0x0000989c, 0x00000000 },
28960 - {0x0000989c, 0x00000000 },
28961 - {0x0000989c, 0x00000000 },
28962 - {0x0000989c, 0x00000000 },
28963 - {0x0000989c, 0x000000c0 },
28964 - {0x0000989c, 0x00000019 },
28965 - {0x0000989c, 0x00000004 },
28966 - {0x0000989c, 0x00000000 },
28967 - {0x0000989c, 0x00000000 },
28968 - {0x0000989c, 0x00000000 },
28969 - {0x0000989c, 0x00000004 },
28970 - {0x0000989c, 0x00000003 },
28971 - {0x0000989c, 0x00000008 },
28972 - {0x0000989c, 0x00000000 },
28973 - {0x000098cc, 0x00000000 },
28974 -};
28975 -
28976 -static u32 ar5416Addac_91601_1[][2] = {
28977 - {0x0000989c, 0x00000000 },
28978 - {0x0000989c, 0x00000000 },
28979 - {0x0000989c, 0x00000000 },
28980 - {0x0000989c, 0x00000000 },
28981 - {0x0000989c, 0x00000000 },
28982 - {0x0000989c, 0x00000000 },
28983 - {0x0000989c, 0x000000c0 },
28984 - {0x0000989c, 0x00000018 },
28985 - {0x0000989c, 0x00000004 },
28986 - {0x0000989c, 0x00000000 },
28987 - {0x0000989c, 0x00000000 },
28988 - {0x0000989c, 0x00000000 },
28989 - {0x0000989c, 0x00000000 },
28990 - {0x0000989c, 0x00000000 },
28991 - {0x0000989c, 0x00000000 },
28992 - {0x0000989c, 0x00000000 },
28993 - {0x0000989c, 0x00000000 },
28994 - {0x0000989c, 0x00000000 },
28995 - {0x0000989c, 0x00000000 },
28996 - {0x0000989c, 0x00000000 },
28997 - {0x0000989c, 0x00000000 },
28998 - {0x0000989c, 0x000000c0 },
28999 - {0x0000989c, 0x00000019 },
29000 - {0x0000989c, 0x00000004 },
29001 - {0x0000989c, 0x00000000 },
29002 - {0x0000989c, 0x00000000 },
29003 - {0x0000989c, 0x00000000 },
29004 - {0x0000989c, 0x00000000 },
29005 - {0x0000989c, 0x00000000 },
29006 - {0x0000989c, 0x00000000 },
29007 - {0x0000989c, 0x00000000 },
29008 - {0x000098cc, 0x00000000 },
29009 -};
29010 -
29011 -/* XXX 9280 1 */
29012 -static const u32 ar9280Modes_9280[][6] = {
29013 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
29014 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
29015 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
29016 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
29017 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801080, 0x08400840, 0x06e006e0 },
29018 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
29019 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
29020 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
29021 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
29022 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
29023 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
29024 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
29025 - { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
29026 - { 0x00009848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 },
29027 - { 0x0000a848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 },
29028 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
29029 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
29030 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
29031 - { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d20, 0x00049d20, 0x00049d18 },
29032 - { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
29033 - { 0x00009868, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190 },
29034 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
29035 - { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
29036 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
29037 - { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
29038 - { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010 },
29039 - { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
29040 - { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
29041 - { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
29042 - { 0x0000c9b8, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a },
29043 - { 0x0000c9bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
29044 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
29045 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
29046 - { 0x000099c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c },
29047 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
29048 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
29049 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29050 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29051 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000214, 0x00000214, 0x00000214 },
29052 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000218, 0x00000218, 0x00000218 },
29053 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000224, 0x00000224, 0x00000224 },
29054 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000228, 0x00000228, 0x00000228 },
29055 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000022c, 0x0000022c, 0x0000022c },
29056 - { 0x00009a14, 0x00008200, 0x00008200, 0x00000230, 0x00000230, 0x00000230 },
29057 - { 0x00009a18, 0x00008204, 0x00008204, 0x000002a4, 0x000002a4, 0x000002a4 },
29058 - { 0x00009a1c, 0x00008208, 0x00008208, 0x000002a8, 0x000002a8, 0x000002a8 },
29059 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x000002ac, 0x000002ac, 0x000002ac },
29060 - { 0x00009a24, 0x00008210, 0x00008210, 0x000002b0, 0x000002b0, 0x000002b0 },
29061 - { 0x00009a28, 0x00008214, 0x00008214, 0x000002b4, 0x000002b4, 0x000002b4 },
29062 - { 0x00009a2c, 0x00008280, 0x00008280, 0x000002b8, 0x000002b8, 0x000002b8 },
29063 - { 0x00009a30, 0x00008284, 0x00008284, 0x00000390, 0x00000390, 0x00000390 },
29064 - { 0x00009a34, 0x00008288, 0x00008288, 0x00000394, 0x00000394, 0x00000394 },
29065 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00000398, 0x00000398, 0x00000398 },
29066 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00000334, 0x00000334, 0x00000334 },
29067 - { 0x00009a40, 0x00008300, 0x00008300, 0x00000338, 0x00000338, 0x00000338 },
29068 - { 0x00009a44, 0x00008304, 0x00008304, 0x000003ac, 0x000003ac, 0x000003ac },
29069 - { 0x00009a48, 0x00008308, 0x00008308, 0x000003b0, 0x000003b0, 0x000003b0 },
29070 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x000003b4, 0x000003b4, 0x000003b4 },
29071 - { 0x00009a50, 0x00008310, 0x00008310, 0x000003b8, 0x000003b8, 0x000003b8 },
29072 - { 0x00009a54, 0x00008314, 0x00008314, 0x000003a5, 0x000003a5, 0x000003a5 },
29073 - { 0x00009a58, 0x00008380, 0x00008380, 0x000003a9, 0x000003a9, 0x000003a9 },
29074 - { 0x00009a5c, 0x00008384, 0x00008384, 0x000003ad, 0x000003ad, 0x000003ad },
29075 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
29076 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
29077 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
29078 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
29079 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
29080 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
29081 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
29082 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
29083 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
29084 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
29085 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
29086 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
29087 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
29088 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
29089 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
29090 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
29091 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
29092 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
29093 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
29094 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
29095 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
29096 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
29097 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
29098 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
29099 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
29100 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
29101 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
29102 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
29103 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
29104 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
29105 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
29106 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
29107 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
29108 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
29109 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c },
29110 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 },
29111 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 },
29112 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 },
29113 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 },
29114 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 },
29115 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 },
29116 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 },
29117 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 },
29118 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 },
29119 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 },
29120 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 },
29121 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 },
29122 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c },
29123 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 },
29124 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 },
29125 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 },
29126 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 },
29127 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 },
29128 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 },
29129 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 },
29130 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 },
29131 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad },
29132 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 },
29133 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 },
29134 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 },
29135 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 },
29136 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 },
29137 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 },
29138 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 },
29139 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 },
29140 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 },
29141 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca },
29142 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce },
29143 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 },
29144 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 },
29145 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 },
29146 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 },
29147 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb },
29148 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf },
29149 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 },
29150 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db },
29151 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db },
29152 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db },
29153 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29154 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29155 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29156 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29157 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29158 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29159 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29160 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29161 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29162 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29163 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29164 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29165 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29166 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29167 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29168 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29169 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29170 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29171 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29172 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29173 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29174 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29175 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29176 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29177 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29178 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29179 - { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 },
29180 - { 0x0000a208, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788 },
29181 - { 0x0000a20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 },
29182 - { 0x0000b20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 },
29183 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
29184 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
29185 - { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
29186 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29187 - { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
29188 - { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
29189 - { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b },
29190 - { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 },
29191 - { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 },
29192 - { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a },
29193 - { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 },
29194 - { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
29195 - { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b },
29196 - { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 },
29197 - { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 },
29198 - { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a },
29199 - { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 },
29200 - { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b },
29201 - { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 },
29202 - { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 },
29203 - { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a },
29204 - { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 },
29205 - { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a },
29206 - { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 },
29207 - { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 },
29208 - { 0x0000784c, 0x0e4f048c, 0x0e4f048c, 0x0e4d048c, 0x0e4d048c, 0x0e4d048c },
29209 - { 0x00007854, 0x12031828, 0x12031828, 0x12035828, 0x12035828, 0x12035828 },
29210 - { 0x00007870, 0x807ec400, 0x807ec400, 0x807ec000, 0x807ec000, 0x807ec000 },
29211 - { 0x0000788c, 0x00010000, 0x00010000, 0x00110000, 0x00110000, 0x00110000 },
29212 -};
29213 -
29214 -static const u32 ar9280Common_9280[][2] = {
29215 - { 0x0000000c, 0x00000000 },
29216 - { 0x00000030, 0x00020015 },
29217 - { 0x00000034, 0x00000005 },
29218 - { 0x00000040, 0x00000000 },
29219 - { 0x00000044, 0x00000008 },
29220 - { 0x00000048, 0x00000008 },
29221 - { 0x0000004c, 0x00000010 },
29222 - { 0x00000050, 0x00000000 },
29223 - { 0x00000054, 0x0000001f },
29224 - { 0x00000800, 0x00000000 },
29225 - { 0x00000804, 0x00000000 },
29226 - { 0x00000808, 0x00000000 },
29227 - { 0x0000080c, 0x00000000 },
29228 - { 0x00000810, 0x00000000 },
29229 - { 0x00000814, 0x00000000 },
29230 - { 0x00000818, 0x00000000 },
29231 - { 0x0000081c, 0x00000000 },
29232 - { 0x00000820, 0x00000000 },
29233 - { 0x00000824, 0x00000000 },
29234 - { 0x00001040, 0x002ffc0f },
29235 - { 0x00001044, 0x002ffc0f },
29236 - { 0x00001048, 0x002ffc0f },
29237 - { 0x0000104c, 0x002ffc0f },
29238 - { 0x00001050, 0x002ffc0f },
29239 - { 0x00001054, 0x002ffc0f },
29240 - { 0x00001058, 0x002ffc0f },
29241 - { 0x0000105c, 0x002ffc0f },
29242 - { 0x00001060, 0x002ffc0f },
29243 - { 0x00001064, 0x002ffc0f },
29244 - { 0x00001230, 0x00000000 },
29245 - { 0x00001270, 0x00000000 },
29246 - { 0x00001038, 0x00000000 },
29247 - { 0x00001078, 0x00000000 },
29248 - { 0x000010b8, 0x00000000 },
29249 - { 0x000010f8, 0x00000000 },
29250 - { 0x00001138, 0x00000000 },
29251 - { 0x00001178, 0x00000000 },
29252 - { 0x000011b8, 0x00000000 },
29253 - { 0x000011f8, 0x00000000 },
29254 - { 0x00001238, 0x00000000 },
29255 - { 0x00001278, 0x00000000 },
29256 - { 0x000012b8, 0x00000000 },
29257 - { 0x000012f8, 0x00000000 },
29258 - { 0x00001338, 0x00000000 },
29259 - { 0x00001378, 0x00000000 },
29260 - { 0x000013b8, 0x00000000 },
29261 - { 0x000013f8, 0x00000000 },
29262 - { 0x00001438, 0x00000000 },
29263 - { 0x00001478, 0x00000000 },
29264 - { 0x000014b8, 0x00000000 },
29265 - { 0x000014f8, 0x00000000 },
29266 - { 0x00001538, 0x00000000 },
29267 - { 0x00001578, 0x00000000 },
29268 - { 0x000015b8, 0x00000000 },
29269 - { 0x000015f8, 0x00000000 },
29270 - { 0x00001638, 0x00000000 },
29271 - { 0x00001678, 0x00000000 },
29272 - { 0x000016b8, 0x00000000 },
29273 - { 0x000016f8, 0x00000000 },
29274 - { 0x00001738, 0x00000000 },
29275 - { 0x00001778, 0x00000000 },
29276 - { 0x000017b8, 0x00000000 },
29277 - { 0x000017f8, 0x00000000 },
29278 - { 0x0000103c, 0x00000000 },
29279 - { 0x0000107c, 0x00000000 },
29280 - { 0x000010bc, 0x00000000 },
29281 - { 0x000010fc, 0x00000000 },
29282 - { 0x0000113c, 0x00000000 },
29283 - { 0x0000117c, 0x00000000 },
29284 - { 0x000011bc, 0x00000000 },
29285 - { 0x000011fc, 0x00000000 },
29286 - { 0x0000123c, 0x00000000 },
29287 - { 0x0000127c, 0x00000000 },
29288 - { 0x000012bc, 0x00000000 },
29289 - { 0x000012fc, 0x00000000 },
29290 - { 0x0000133c, 0x00000000 },
29291 - { 0x0000137c, 0x00000000 },
29292 - { 0x000013bc, 0x00000000 },
29293 - { 0x000013fc, 0x00000000 },
29294 - { 0x0000143c, 0x00000000 },
29295 - { 0x0000147c, 0x00000000 },
29296 - { 0x00004030, 0x00000002 },
29297 - { 0x0000403c, 0x00000002 },
29298 - { 0x00004024, 0x0000001f },
29299 - { 0x00007010, 0x00000033 },
29300 - { 0x00007038, 0x000004c2 },
29301 - { 0x00008004, 0x00000000 },
29302 - { 0x00008008, 0x00000000 },
29303 - { 0x0000800c, 0x00000000 },
29304 - { 0x00008018, 0x00000700 },
29305 - { 0x00008020, 0x00000000 },
29306 - { 0x00008038, 0x00000000 },
29307 - { 0x0000803c, 0x00000000 },
29308 - { 0x00008048, 0x40000000 },
29309 - { 0x00008054, 0x00000000 },
29310 - { 0x00008058, 0x00000000 },
29311 - { 0x0000805c, 0x000fc78f },
29312 - { 0x00008060, 0x0000000f },
29313 - { 0x00008064, 0x00000000 },
29314 - { 0x00008070, 0x00000000 },
29315 - { 0x000080c0, 0x2a82301a },
29316 - { 0x000080c4, 0x05dc01e0 },
29317 - { 0x000080c8, 0x1f402710 },
29318 - { 0x000080cc, 0x01f40000 },
29319 - { 0x000080d0, 0x00001e00 },
29320 - { 0x000080d4, 0x00000000 },
29321 - { 0x000080d8, 0x00400000 },
29322 - { 0x000080e0, 0xffffffff },
29323 - { 0x000080e4, 0x0000ffff },
29324 - { 0x000080e8, 0x003f3f3f },
29325 - { 0x000080ec, 0x00000000 },
29326 - { 0x000080f0, 0x00000000 },
29327 - { 0x000080f4, 0x00000000 },
29328 - { 0x000080f8, 0x00000000 },
29329 - { 0x000080fc, 0x00020000 },
29330 - { 0x00008100, 0x00020000 },
29331 - { 0x00008104, 0x00000001 },
29332 - { 0x00008108, 0x00000052 },
29333 - { 0x0000810c, 0x00000000 },
29334 - { 0x00008110, 0x00000168 },
29335 - { 0x00008118, 0x000100aa },
29336 - { 0x0000811c, 0x00003210 },
29337 - { 0x00008120, 0x08f04800 },
29338 - { 0x00008124, 0x00000000 },
29339 - { 0x00008128, 0x00000000 },
29340 - { 0x0000812c, 0x00000000 },
29341 - { 0x00008130, 0x00000000 },
29342 - { 0x00008134, 0x00000000 },
29343 - { 0x00008138, 0x00000000 },
29344 - { 0x0000813c, 0x00000000 },
29345 - { 0x00008144, 0x00000000 },
29346 - { 0x00008168, 0x00000000 },
29347 - { 0x0000816c, 0x00000000 },
29348 - { 0x00008170, 0x32143320 },
29349 - { 0x00008174, 0xfaa4fa50 },
29350 - { 0x00008178, 0x00000100 },
29351 - { 0x0000817c, 0x00000000 },
29352 - { 0x000081c4, 0x00000000 },
29353 - { 0x000081d0, 0x00003210 },
29354 - { 0x000081ec, 0x00000000 },
29355 - { 0x000081f0, 0x00000000 },
29356 - { 0x000081f4, 0x00000000 },
29357 - { 0x000081f8, 0x00000000 },
29358 - { 0x000081fc, 0x00000000 },
29359 - { 0x00008200, 0x00000000 },
29360 - { 0x00008204, 0x00000000 },
29361 - { 0x00008208, 0x00000000 },
29362 - { 0x0000820c, 0x00000000 },
29363 - { 0x00008210, 0x00000000 },
29364 - { 0x00008214, 0x00000000 },
29365 - { 0x00008218, 0x00000000 },
29366 - { 0x0000821c, 0x00000000 },
29367 - { 0x00008220, 0x00000000 },
29368 - { 0x00008224, 0x00000000 },
29369 - { 0x00008228, 0x00000000 },
29370 - { 0x0000822c, 0x00000000 },
29371 - { 0x00008230, 0x00000000 },
29372 - { 0x00008234, 0x00000000 },
29373 - { 0x00008238, 0x00000000 },
29374 - { 0x0000823c, 0x00000000 },
29375 - { 0x00008240, 0x00100000 },
29376 - { 0x00008244, 0x0010f400 },
29377 - { 0x00008248, 0x00000100 },
29378 - { 0x0000824c, 0x0001e800 },
29379 - { 0x00008250, 0x00000000 },
29380 - { 0x00008254, 0x00000000 },
29381 - { 0x00008258, 0x00000000 },
29382 - { 0x0000825c, 0x400000ff },
29383 - { 0x00008260, 0x00080922 },
29384 - { 0x00008270, 0x00000000 },
29385 - { 0x00008274, 0x40000000 },
29386 - { 0x00008278, 0x003e4180 },
29387 - { 0x0000827c, 0x00000000 },
29388 - { 0x00008284, 0x0000002c },
29389 - { 0x00008288, 0x0000002c },
29390 - { 0x0000828c, 0x00000000 },
29391 - { 0x00008294, 0x00000000 },
29392 - { 0x00008298, 0x00000000 },
29393 - { 0x00008300, 0x00000000 },
29394 - { 0x00008304, 0x00000000 },
29395 - { 0x00008308, 0x00000000 },
29396 - { 0x0000830c, 0x00000000 },
29397 - { 0x00008310, 0x00000000 },
29398 - { 0x00008314, 0x00000000 },
29399 - { 0x00008318, 0x00000000 },
29400 - { 0x00008328, 0x00000000 },
29401 - { 0x0000832c, 0x00000007 },
29402 - { 0x00008330, 0x00000302 },
29403 - { 0x00008334, 0x00000e00 },
29404 - { 0x00008338, 0x00000000 },
29405 - { 0x0000833c, 0x00000000 },
29406 - { 0x00008340, 0x000107ff },
29407 - { 0x00008344, 0x00000000 },
29408 - { 0x00009808, 0x00000000 },
29409 - { 0x0000980c, 0xaf268e30 },
29410 - { 0x00009810, 0xfd14e000 },
29411 - { 0x00009814, 0x9c0a9f6b },
29412 - { 0x0000981c, 0x00000000 },
29413 - { 0x0000982c, 0x0000a000 },
29414 - { 0x00009830, 0x00000000 },
29415 - { 0x0000983c, 0x00200400 },
29416 - { 0x00009840, 0x206a01ae },
29417 - { 0x0000984c, 0x0040233c },
29418 - { 0x0000a84c, 0x0040233c },
29419 - { 0x00009854, 0x00000044 },
29420 - { 0x00009900, 0x00000000 },
29421 - { 0x00009904, 0x00000000 },
29422 - { 0x00009908, 0x00000000 },
29423 - { 0x0000990c, 0x00000000 },
29424 - { 0x0000991c, 0x10000fff },
29425 - { 0x00009920, 0x04900000 },
29426 - { 0x0000a920, 0x04900000 },
29427 - { 0x00009928, 0x00000001 },
29428 - { 0x0000992c, 0x00000004 },
29429 - { 0x00009934, 0x1e1f2022 },
29430 - { 0x00009938, 0x0a0b0c0d },
29431 - { 0x0000993c, 0x00000000 },
29432 - { 0x00009948, 0x9280c00a },
29433 - { 0x0000994c, 0x00020028 },
29434 - { 0x00009954, 0xe250a51e },
29435 - { 0x00009958, 0x3388ffff },
29436 - { 0x00009940, 0x00781204 },
29437 - { 0x0000c95c, 0x004b6a8e },
29438 - { 0x0000c968, 0x000003ce },
29439 - { 0x00009970, 0x190fb514 },
29440 - { 0x00009974, 0x00000000 },
29441 - { 0x00009978, 0x00000001 },
29442 - { 0x0000997c, 0x00000000 },
29443 - { 0x00009980, 0x00000000 },
29444 - { 0x00009984, 0x00000000 },
29445 - { 0x00009988, 0x00000000 },
29446 - { 0x0000998c, 0x00000000 },
29447 - { 0x00009990, 0x00000000 },
29448 - { 0x00009994, 0x00000000 },
29449 - { 0x00009998, 0x00000000 },
29450 - { 0x0000999c, 0x00000000 },
29451 - { 0x000099a0, 0x00000000 },
29452 - { 0x000099a4, 0x00000001 },
29453 - { 0x000099a8, 0x201fff00 },
29454 - { 0x000099ac, 0x006f00c4 },
29455 - { 0x000099b0, 0x03051000 },
29456 - { 0x000099b4, 0x00000820 },
29457 - { 0x000099dc, 0x00000000 },
29458 - { 0x000099e0, 0x00000000 },
29459 - { 0x000099e4, 0xaaaaaaaa },
29460 - { 0x000099e8, 0x3c466478 },
29461 - { 0x000099ec, 0x0cc80caa },
29462 - { 0x000099fc, 0x00001042 },
29463 - { 0x0000a210, 0x4080a333 },
29464 - { 0x0000a214, 0x40206c10 },
29465 - { 0x0000a218, 0x009c4060 },
29466 - { 0x0000a220, 0x01834061 },
29467 - { 0x0000a224, 0x00000400 },
29468 - { 0x0000a228, 0x000003b5 },
29469 - { 0x0000a22c, 0x23277200 },
29470 - { 0x0000a234, 0x20202020 },
29471 - { 0x0000a238, 0x20202020 },
29472 - { 0x0000a23c, 0x13c889af },
29473 - { 0x0000a240, 0x38490a20 },
29474 - { 0x0000a244, 0x00007bb6 },
29475 - { 0x0000a248, 0x0fff3ffc },
29476 - { 0x0000a24c, 0x00000001 },
29477 - { 0x0000a250, 0x001da000 },
29478 - { 0x0000a254, 0x00000000 },
29479 - { 0x0000a258, 0x0cdbd380 },
29480 - { 0x0000a25c, 0x0f0f0f01 },
29481 - { 0x0000a260, 0xdfa91f01 },
29482 - { 0x0000a268, 0x00000000 },
29483 - { 0x0000a26c, 0x0ebae9c6 },
29484 - { 0x0000b26c, 0x0ebae9c6 },
29485 - { 0x0000d270, 0x00820820 },
29486 - { 0x0000a278, 0x1ce739ce },
29487 - { 0x0000a27c, 0x050701ce },
29488 - { 0x0000a358, 0x7999aa0f },
29489 - { 0x0000d35c, 0x07ffffef },
29490 - { 0x0000d360, 0x0fffffe7 },
29491 - { 0x0000d364, 0x17ffffe5 },
29492 - { 0x0000d368, 0x1fffffe4 },
29493 - { 0x0000d36c, 0x37ffffe3 },
29494 - { 0x0000d370, 0x3fffffe3 },
29495 - { 0x0000d374, 0x57ffffe3 },
29496 - { 0x0000d378, 0x5fffffe2 },
29497 - { 0x0000d37c, 0x7fffffe2 },
29498 - { 0x0000d380, 0x7f3c7bba },
29499 - { 0x0000d384, 0xf3307ff0 },
29500 - { 0x0000a388, 0x0c000000 },
29501 - { 0x0000a38c, 0x20202020 },
29502 - { 0x0000a390, 0x20202020 },
29503 - { 0x0000a394, 0x1ce739ce },
29504 - { 0x0000a398, 0x000001ce },
29505 - { 0x0000a39c, 0x00000001 },
29506 - { 0x0000a3a0, 0x00000000 },
29507 - { 0x0000a3a4, 0x00000000 },
29508 - { 0x0000a3a8, 0x00000000 },
29509 - { 0x0000a3ac, 0x00000000 },
29510 - { 0x0000a3b0, 0x00000000 },
29511 - { 0x0000a3b4, 0x00000000 },
29512 - { 0x0000a3b8, 0x00000000 },
29513 - { 0x0000a3bc, 0x00000000 },
29514 - { 0x0000a3c0, 0x00000000 },
29515 - { 0x0000a3c4, 0x00000000 },
29516 - { 0x0000a3c8, 0x00000246 },
29517 - { 0x0000a3cc, 0x20202020 },
29518 - { 0x0000a3d0, 0x20202020 },
29519 - { 0x0000a3d4, 0x20202020 },
29520 - { 0x0000a3dc, 0x1ce739ce },
29521 - { 0x0000a3e0, 0x000001ce },
29522 - { 0x0000a3e4, 0x00000000 },
29523 - { 0x0000a3e8, 0x18c43433 },
29524 - { 0x0000a3ec, 0x00f38081 },
29525 - { 0x00007800, 0x00040000 },
29526 - { 0x00007804, 0xdb005012 },
29527 - { 0x00007808, 0x04924914 },
29528 - { 0x0000780c, 0x21084210 },
29529 - { 0x00007810, 0x6d801300 },
29530 - { 0x00007814, 0x0019beff },
29531 - { 0x00007818, 0x07e40000 },
29532 - { 0x0000781c, 0x00492000 },
29533 - { 0x00007820, 0x92492480 },
29534 - { 0x00007824, 0x00040000 },
29535 - { 0x00007828, 0xdb005012 },
29536 - { 0x0000782c, 0x04924914 },
29537 - { 0x00007830, 0x21084210 },
29538 - { 0x00007834, 0x6d801300 },
29539 - { 0x00007838, 0x0019beff },
29540 - { 0x0000783c, 0x07e40000 },
29541 - { 0x00007840, 0x00492000 },
29542 - { 0x00007844, 0x92492480 },
29543 - { 0x00007848, 0x00120000 },
29544 - { 0x00007850, 0x54214514 },
29545 - { 0x00007858, 0x92592692 },
29546 - { 0x00007860, 0x52802000 },
29547 - { 0x00007864, 0x0a8e370e },
29548 - { 0x00007868, 0xc0102850 },
29549 - { 0x0000786c, 0x812d4000 },
29550 - { 0x00007874, 0x001b6db0 },
29551 - { 0x00007878, 0x00376b63 },
29552 - { 0x0000787c, 0x06db6db6 },
29553 - { 0x00007880, 0x006d8000 },
29554 - { 0x00007884, 0xffeffffe },
29555 - { 0x00007888, 0xffeffffe },
29556 - { 0x00007890, 0x00060aeb },
29557 - { 0x00007894, 0x5a108000 },
29558 - { 0x00007898, 0x2a850160 },
29559 -};
29560 -
29561 -/* XXX 9280 2 */
29562 -static const u32 ar9280Modes_9280_2[][6] = {
29563 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
29564 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
29565 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
29566 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
29567 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
29568 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
29569 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
29570 - { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
29571 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
29572 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
29573 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
29574 - { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
29575 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
29576 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
29577 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
29578 - { 0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e, 0x206a012e },
29579 - { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
29580 - { 0x00009850, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
29581 - { 0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
29582 - { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
29583 - { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
29584 - { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
29585 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
29586 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
29587 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
29588 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000268, 0x0000000b, 0x00000016 },
29589 - { 0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
29590 - { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010 },
29591 - { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
29592 - { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
29593 - { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
29594 - { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
29595 - { 0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c },
29596 - { 0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00, 0x00000c00 },
29597 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
29598 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
29599 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
29600 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
29601 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
29602 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29603 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29604 - { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 },
29605 - { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
29606 - { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
29607 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
29608 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
29609 - { 0x0000a23c, 0x13c88000, 0x13c88000, 0x13c88001, 0x13c88000, 0x13c88000 },
29610 - { 0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000, 0x0004a000 },
29611 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
29612 - { 0x0000a388, 0x0c000000, 0x0c000000, 0x08000000, 0x0c000000, 0x0c000000 },
29613 - { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29614 - { 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 },
29615 -};
29616 -
29617 -static const u32 ar9280Common_9280_2[][2] = {
29618 - { 0x0000000c, 0x00000000 },
29619 - { 0x00000030, 0x00020015 },
29620 - { 0x00000034, 0x00000005 },
29621 - { 0x00000040, 0x00000000 },
29622 - { 0x00000044, 0x00000008 },
29623 - { 0x00000048, 0x00000008 },
29624 - { 0x0000004c, 0x00000010 },
29625 - { 0x00000050, 0x00000000 },
29626 - { 0x00000054, 0x0000001f },
29627 - { 0x00000800, 0x00000000 },
29628 - { 0x00000804, 0x00000000 },
29629 - { 0x00000808, 0x00000000 },
29630 - { 0x0000080c, 0x00000000 },
29631 - { 0x00000810, 0x00000000 },
29632 - { 0x00000814, 0x00000000 },
29633 - { 0x00000818, 0x00000000 },
29634 - { 0x0000081c, 0x00000000 },
29635 - { 0x00000820, 0x00000000 },
29636 - { 0x00000824, 0x00000000 },
29637 - { 0x00001040, 0x002ffc0f },
29638 - { 0x00001044, 0x002ffc0f },
29639 - { 0x00001048, 0x002ffc0f },
29640 - { 0x0000104c, 0x002ffc0f },
29641 - { 0x00001050, 0x002ffc0f },
29642 - { 0x00001054, 0x002ffc0f },
29643 - { 0x00001058, 0x002ffc0f },
29644 - { 0x0000105c, 0x002ffc0f },
29645 - { 0x00001060, 0x002ffc0f },
29646 - { 0x00001064, 0x002ffc0f },
29647 - { 0x00001230, 0x00000000 },
29648 - { 0x00001270, 0x00000000 },
29649 - { 0x00001038, 0x00000000 },
29650 - { 0x00001078, 0x00000000 },
29651 - { 0x000010b8, 0x00000000 },
29652 - { 0x000010f8, 0x00000000 },
29653 - { 0x00001138, 0x00000000 },
29654 - { 0x00001178, 0x00000000 },
29655 - { 0x000011b8, 0x00000000 },
29656 - { 0x000011f8, 0x00000000 },
29657 - { 0x00001238, 0x00000000 },
29658 - { 0x00001278, 0x00000000 },
29659 - { 0x000012b8, 0x00000000 },
29660 - { 0x000012f8, 0x00000000 },
29661 - { 0x00001338, 0x00000000 },
29662 - { 0x00001378, 0x00000000 },
29663 - { 0x000013b8, 0x00000000 },
29664 - { 0x000013f8, 0x00000000 },
29665 - { 0x00001438, 0x00000000 },
29666 - { 0x00001478, 0x00000000 },
29667 - { 0x000014b8, 0x00000000 },
29668 - { 0x000014f8, 0x00000000 },
29669 - { 0x00001538, 0x00000000 },
29670 - { 0x00001578, 0x00000000 },
29671 - { 0x000015b8, 0x00000000 },
29672 - { 0x000015f8, 0x00000000 },
29673 - { 0x00001638, 0x00000000 },
29674 - { 0x00001678, 0x00000000 },
29675 - { 0x000016b8, 0x00000000 },
29676 - { 0x000016f8, 0x00000000 },
29677 - { 0x00001738, 0x00000000 },
29678 - { 0x00001778, 0x00000000 },
29679 - { 0x000017b8, 0x00000000 },
29680 - { 0x000017f8, 0x00000000 },
29681 - { 0x0000103c, 0x00000000 },
29682 - { 0x0000107c, 0x00000000 },
29683 - { 0x000010bc, 0x00000000 },
29684 - { 0x000010fc, 0x00000000 },
29685 - { 0x0000113c, 0x00000000 },
29686 - { 0x0000117c, 0x00000000 },
29687 - { 0x000011bc, 0x00000000 },
29688 - { 0x000011fc, 0x00000000 },
29689 - { 0x0000123c, 0x00000000 },
29690 - { 0x0000127c, 0x00000000 },
29691 - { 0x000012bc, 0x00000000 },
29692 - { 0x000012fc, 0x00000000 },
29693 - { 0x0000133c, 0x00000000 },
29694 - { 0x0000137c, 0x00000000 },
29695 - { 0x000013bc, 0x00000000 },
29696 - { 0x000013fc, 0x00000000 },
29697 - { 0x0000143c, 0x00000000 },
29698 - { 0x0000147c, 0x00000000 },
29699 - { 0x00004030, 0x00000002 },
29700 - { 0x0000403c, 0x00000002 },
29701 - { 0x00004024, 0x0000001f },
29702 - { 0x00004060, 0x00000000 },
29703 - { 0x00004064, 0x00000000 },
29704 - { 0x00007010, 0x00000033 },
29705 - { 0x00007034, 0x00000002 },
29706 - { 0x00007038, 0x000004c2 },
29707 - { 0x00008004, 0x00000000 },
29708 - { 0x00008008, 0x00000000 },
29709 - { 0x0000800c, 0x00000000 },
29710 - { 0x00008018, 0x00000700 },
29711 - { 0x00008020, 0x00000000 },
29712 - { 0x00008038, 0x00000000 },
29713 - { 0x0000803c, 0x00000000 },
29714 - { 0x00008048, 0x40000000 },
29715 - { 0x00008054, 0x00000000 },
29716 - { 0x00008058, 0x00000000 },
29717 - { 0x0000805c, 0x000fc78f },
29718 - { 0x00008060, 0x0000000f },
29719 - { 0x00008064, 0x00000000 },
29720 - { 0x00008070, 0x00000000 },
29721 - { 0x000080c0, 0x2a80001a },
29722 - { 0x000080c4, 0x05dc01e0 },
29723 - { 0x000080c8, 0x1f402710 },
29724 - { 0x000080cc, 0x01f40000 },
29725 - { 0x000080d0, 0x00001e00 },
29726 - { 0x000080d4, 0x00000000 },
29727 - { 0x000080d8, 0x00400000 },
29728 - { 0x000080e0, 0xffffffff },
29729 - { 0x000080e4, 0x0000ffff },
29730 - { 0x000080e8, 0x003f3f3f },
29731 - { 0x000080ec, 0x00000000 },
29732 - { 0x000080f0, 0x00000000 },
29733 - { 0x000080f4, 0x00000000 },
29734 - { 0x000080f8, 0x00000000 },
29735 - { 0x000080fc, 0x00020000 },
29736 - { 0x00008100, 0x00020000 },
29737 - { 0x00008104, 0x00000001 },
29738 - { 0x00008108, 0x00000052 },
29739 - { 0x0000810c, 0x00000000 },
29740 - { 0x00008110, 0x00000168 },
29741 - { 0x00008118, 0x000100aa },
29742 - { 0x0000811c, 0x00003210 },
29743 - { 0x00008124, 0x00000000 },
29744 - { 0x00008128, 0x00000000 },
29745 - { 0x0000812c, 0x00000000 },
29746 - { 0x00008130, 0x00000000 },
29747 - { 0x00008134, 0x00000000 },
29748 - { 0x00008138, 0x00000000 },
29749 - { 0x0000813c, 0x00000000 },
29750 - { 0x00008144, 0xffffffff },
29751 - { 0x00008168, 0x00000000 },
29752 - { 0x0000816c, 0x00000000 },
29753 - { 0x00008170, 0x32143320 },
29754 - { 0x00008174, 0xfaa4fa50 },
29755 - { 0x00008178, 0x00000100 },
29756 - { 0x0000817c, 0x00000000 },
29757 - { 0x000081c0, 0x00000000 },
29758 - { 0x000081ec, 0x00000000 },
29759 - { 0x000081f0, 0x00000000 },
29760 - { 0x000081f4, 0x00000000 },
29761 - { 0x000081f8, 0x00000000 },
29762 - { 0x000081fc, 0x00000000 },
29763 - { 0x00008200, 0x00000000 },
29764 - { 0x00008204, 0x00000000 },
29765 - { 0x00008208, 0x00000000 },
29766 - { 0x0000820c, 0x00000000 },
29767 - { 0x00008210, 0x00000000 },
29768 - { 0x00008214, 0x00000000 },
29769 - { 0x00008218, 0x00000000 },
29770 - { 0x0000821c, 0x00000000 },
29771 - { 0x00008220, 0x00000000 },
29772 - { 0x00008224, 0x00000000 },
29773 - { 0x00008228, 0x00000000 },
29774 - { 0x0000822c, 0x00000000 },
29775 - { 0x00008230, 0x00000000 },
29776 - { 0x00008234, 0x00000000 },
29777 - { 0x00008238, 0x00000000 },
29778 - { 0x0000823c, 0x00000000 },
29779 - { 0x00008240, 0x00100000 },
29780 - { 0x00008244, 0x0010f400 },
29781 - { 0x00008248, 0x00000100 },
29782 - { 0x0000824c, 0x0001e800 },
29783 - { 0x00008250, 0x00000000 },
29784 - { 0x00008254, 0x00000000 },
29785 - { 0x00008258, 0x00000000 },
29786 - { 0x0000825c, 0x400000ff },
29787 - { 0x00008260, 0x00080922 },
29788 - { 0x00008264, 0xa8a00010 },
29789 - { 0x00008270, 0x00000000 },
29790 - { 0x00008274, 0x40000000 },
29791 - { 0x00008278, 0x003e4180 },
29792 - { 0x0000827c, 0x00000000 },
29793 - { 0x00008284, 0x0000002c },
29794 - { 0x00008288, 0x0000002c },
29795 - { 0x0000828c, 0x00000000 },
29796 - { 0x00008294, 0x00000000 },
29797 - { 0x00008298, 0x00000000 },
29798 - { 0x0000829c, 0x00000000 },
29799 - { 0x00008300, 0x00000040 },
29800 - { 0x00008314, 0x00000000 },
29801 - { 0x00008328, 0x00000000 },
29802 - { 0x0000832c, 0x00000007 },
29803 - { 0x00008330, 0x00000302 },
29804 - { 0x00008334, 0x00000e00 },
29805 - { 0x00008338, 0x00ff0000 },
29806 - { 0x0000833c, 0x00000000 },
29807 - { 0x00008340, 0x000107ff },
29808 - { 0x00008344, 0x00481043 },
29809 - { 0x00009808, 0x00000000 },
29810 - { 0x0000980c, 0xafa68e30 },
29811 - { 0x00009810, 0xfd14e000 },
29812 - { 0x00009814, 0x9c0a9f6b },
29813 - { 0x0000981c, 0x00000000 },
29814 - { 0x0000982c, 0x0000a000 },
29815 - { 0x00009830, 0x00000000 },
29816 - { 0x0000983c, 0x00200400 },
29817 - { 0x0000984c, 0x0040233c },
29818 - { 0x0000a84c, 0x0040233c },
29819 - { 0x00009854, 0x00000044 },
29820 - { 0x00009900, 0x00000000 },
29821 - { 0x00009904, 0x00000000 },
29822 - { 0x00009908, 0x00000000 },
29823 - { 0x0000990c, 0x00000000 },
29824 - { 0x00009910, 0x01002310 },
29825 - { 0x0000991c, 0x10000fff },
29826 - { 0x00009920, 0x04900000 },
29827 - { 0x0000a920, 0x04900000 },
29828 - { 0x00009928, 0x00000001 },
29829 - { 0x0000992c, 0x00000004 },
29830 - { 0x00009934, 0x1e1f2022 },
29831 - { 0x00009938, 0x0a0b0c0d },
29832 - { 0x0000993c, 0x00000000 },
29833 - { 0x00009948, 0x9280c00a },
29834 - { 0x0000994c, 0x00020028 },
29835 - { 0x00009954, 0x5f3ca3de },
29836 - { 0x00009958, 0x2108ecff },
29837 - { 0x00009940, 0x14750604 },
29838 - { 0x0000c95c, 0x004b6a8e },
29839 - { 0x00009970, 0x190fb515 },
29840 - { 0x00009974, 0x00000000 },
29841 - { 0x00009978, 0x00000001 },
29842 - { 0x0000997c, 0x00000000 },
29843 - { 0x00009980, 0x00000000 },
29844 - { 0x00009984, 0x00000000 },
29845 - { 0x00009988, 0x00000000 },
29846 - { 0x0000998c, 0x00000000 },
29847 - { 0x00009990, 0x00000000 },
29848 - { 0x00009994, 0x00000000 },
29849 - { 0x00009998, 0x00000000 },
29850 - { 0x0000999c, 0x00000000 },
29851 - { 0x000099a0, 0x00000000 },
29852 - { 0x000099a4, 0x00000001 },
29853 - { 0x000099a8, 0x201fff00 },
29854 - { 0x000099ac, 0x006f0000 },
29855 - { 0x000099b0, 0x03051000 },
29856 - { 0x000099b4, 0x00000820 },
29857 - { 0x000099dc, 0x00000000 },
29858 - { 0x000099e0, 0x00000000 },
29859 - { 0x000099e4, 0xaaaaaaaa },
29860 - { 0x000099e8, 0x3c466478 },
29861 - { 0x000099ec, 0x0cc80caa },
29862 - { 0x000099f0, 0x00000000 },
29863 - { 0x000099fc, 0x00001042 },
29864 - { 0x0000a208, 0x803e4788 },
29865 - { 0x0000a210, 0x4080a333 },
29866 - { 0x0000a214, 0x40206c10 },
29867 - { 0x0000a218, 0x009c4060 },
29868 - { 0x0000a220, 0x01834061 },
29869 - { 0x0000a224, 0x00000400 },
29870 - { 0x0000a228, 0x000003b5 },
29871 - { 0x0000a22c, 0x233f7180 },
29872 - { 0x0000a234, 0x20202020 },
29873 - { 0x0000a238, 0x20202020 },
29874 - { 0x0000a240, 0x38490a20 },
29875 - { 0x0000a244, 0x00007bb6 },
29876 - { 0x0000a248, 0x0fff3ffc },
29877 - { 0x0000a24c, 0x00000000 },
29878 - { 0x0000a254, 0x00000000 },
29879 - { 0x0000a258, 0x0cdbd380 },
29880 - { 0x0000a25c, 0x0f0f0f01 },
29881 - { 0x0000a260, 0xdfa91f01 },
29882 - { 0x0000a268, 0x00000000 },
29883 - { 0x0000a26c, 0x0e79e5c6 },
29884 - { 0x0000b26c, 0x0e79e5c6 },
29885 - { 0x0000d270, 0x00820820 },
29886 - { 0x0000a278, 0x1ce739ce },
29887 - { 0x0000d35c, 0x07ffffef },
29888 - { 0x0000d360, 0x0fffffe7 },
29889 - { 0x0000d364, 0x17ffffe5 },
29890 - { 0x0000d368, 0x1fffffe4 },
29891 - { 0x0000d36c, 0x37ffffe3 },
29892 - { 0x0000d370, 0x3fffffe3 },
29893 - { 0x0000d374, 0x57ffffe3 },
29894 - { 0x0000d378, 0x5fffffe2 },
29895 - { 0x0000d37c, 0x7fffffe2 },
29896 - { 0x0000d380, 0x7f3c7bba },
29897 - { 0x0000d384, 0xf3307ff0 },
29898 - { 0x0000a38c, 0x20202020 },
29899 - { 0x0000a390, 0x20202020 },
29900 - { 0x0000a394, 0x1ce739ce },
29901 - { 0x0000a398, 0x000001ce },
29902 - { 0x0000a39c, 0x00000001 },
29903 - { 0x0000a3a0, 0x00000000 },
29904 - { 0x0000a3a4, 0x00000000 },
29905 - { 0x0000a3a8, 0x00000000 },
29906 - { 0x0000a3ac, 0x00000000 },
29907 - { 0x0000a3b0, 0x00000000 },
29908 - { 0x0000a3b4, 0x00000000 },
29909 - { 0x0000a3b8, 0x00000000 },
29910 - { 0x0000a3bc, 0x00000000 },
29911 - { 0x0000a3c0, 0x00000000 },
29912 - { 0x0000a3c4, 0x00000000 },
29913 - { 0x0000a3c8, 0x00000246 },
29914 - { 0x0000a3cc, 0x20202020 },
29915 - { 0x0000a3d0, 0x20202020 },
29916 - { 0x0000a3d4, 0x20202020 },
29917 - { 0x0000a3dc, 0x1ce739ce },
29918 - { 0x0000a3e0, 0x000001ce },
29919 - { 0x0000a3e4, 0x00000000 },
29920 - { 0x0000a3e8, 0x18c43433 },
29921 - { 0x0000a3ec, 0x00f70081 },
29922 - { 0x00007800, 0x00040000 },
29923 - { 0x00007804, 0xdb005012 },
29924 - { 0x00007808, 0x04924914 },
29925 - { 0x0000780c, 0x21084210 },
29926 - { 0x00007810, 0x6d801300 },
29927 - { 0x00007818, 0x07e41000 },
29928 - { 0x00007824, 0x00040000 },
29929 - { 0x00007828, 0xdb005012 },
29930 - { 0x0000782c, 0x04924914 },
29931 - { 0x00007830, 0x21084210 },
29932 - { 0x00007834, 0x6d801300 },
29933 - { 0x0000783c, 0x07e40000 },
29934 - { 0x00007848, 0x00100000 },
29935 - { 0x0000784c, 0x773f0567 },
29936 - { 0x00007850, 0x54214514 },
29937 - { 0x00007854, 0x12035828 },
29938 - { 0x00007858, 0x9259269a },
29939 - { 0x00007860, 0x52802000 },
29940 - { 0x00007864, 0x0a8e370e },
29941 - { 0x00007868, 0xc0102850 },
29942 - { 0x0000786c, 0x812d4000 },
29943 - { 0x00007870, 0x807ec400 },
29944 - { 0x00007874, 0x001b6db0 },
29945 - { 0x00007878, 0x00376b63 },
29946 - { 0x0000787c, 0x06db6db6 },
29947 - { 0x00007880, 0x006d8000 },
29948 - { 0x00007884, 0xffeffffe },
29949 - { 0x00007888, 0xffeffffe },
29950 - { 0x0000788c, 0x00010000 },
29951 - { 0x00007890, 0x02060aeb },
29952 - { 0x00007898, 0x2a850160 },
29953 -};
29954 -
29955 -static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
29956 - { 0x00001030, 0x00000268, 0x000004d0 },
29957 - { 0x00001070, 0x0000018c, 0x00000318 },
29958 - { 0x000010b0, 0x00000fd0, 0x00001fa0 },
29959 - { 0x00008014, 0x044c044c, 0x08980898 },
29960 - { 0x0000801c, 0x148ec02b, 0x148ec057 },
29961 - { 0x00008318, 0x000044c0, 0x00008980 },
29962 - { 0x00009820, 0x02020200, 0x02020200 },
29963 - { 0x00009824, 0x01000f0f, 0x01000f0f },
29964 - { 0x00009828, 0x0b020001, 0x0b020001 },
29965 - { 0x00009834, 0x00000f0f, 0x00000f0f },
29966 - { 0x00009844, 0x03721821, 0x03721821 },
29967 - { 0x00009914, 0x00000898, 0x00001130 },
29968 - { 0x00009918, 0x0000000b, 0x00000016 },
29969 -};
29970 -
29971 -static const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = {
29972 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
29973 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
29974 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
29975 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
29976 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
29977 - { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
29978 - { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
29979 - { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
29980 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
29981 - { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
29982 - { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
29983 - { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
29984 - { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
29985 - { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
29986 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
29987 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
29988 - { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
29989 - { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
29990 - { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
29991 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
29992 - { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
29993 - { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
29994 - { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
29995 - { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
29996 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
29997 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
29998 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
29999 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
30000 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
30001 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
30002 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
30003 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
30004 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
30005 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
30006 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
30007 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
30008 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
30009 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
30010 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
30011 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
30012 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
30013 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
30014 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
30015 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
30016 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
30017 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
30018 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
30019 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
30020 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b10, 0x00008b10, 0x00008b10 },
30021 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b14, 0x00008b14, 0x00008b14 },
30022 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b01, 0x00008b01, 0x00008b01 },
30023 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b05, 0x00008b05, 0x00008b05 },
30024 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b09, 0x00008b09, 0x00008b09 },
30025 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008b0d, 0x00008b0d, 0x00008b0d },
30026 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008b11, 0x00008b11, 0x00008b11 },
30027 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008b15, 0x00008b15, 0x00008b15 },
30028 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008b02, 0x00008b02, 0x00008b02 },
30029 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008b06, 0x00008b06, 0x00008b06 },
30030 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x00008b0a, 0x00008b0a, 0x00008b0a },
30031 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00008b0e, 0x00008b0e, 0x00008b0e },
30032 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00008b12, 0x00008b12, 0x00008b12 },
30033 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00008b16, 0x00008b16, 0x00008b16 },
30034 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00008b03, 0x00008b03, 0x00008b03 },
30035 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x00008b07, 0x00008b07, 0x00008b07 },
30036 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x00008b0b, 0x00008b0b, 0x00008b0b },
30037 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x00008b0f, 0x00008b0f, 0x00008b0f },
30038 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00008b13, 0x00008b13, 0x00008b13 },
30039 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00008b17, 0x00008b17, 0x00008b17 },
30040 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00008b23, 0x00008b23, 0x00008b23 },
30041 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x00008b27, 0x00008b27, 0x00008b27 },
30042 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00008b2b, 0x00008b2b, 0x00008b2b },
30043 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x00008b2f, 0x00008b2f, 0x00008b2f },
30044 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x00008b33, 0x00008b33, 0x00008b33 },
30045 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x00008b37, 0x00008b37, 0x00008b37 },
30046 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x00008b43, 0x00008b43, 0x00008b43 },
30047 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x00008b47, 0x00008b47, 0x00008b47 },
30048 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00008b4b, 0x00008b4b, 0x00008b4b },
30049 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00008b4f, 0x00008b4f, 0x00008b4f },
30050 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00008b53, 0x00008b53, 0x00008b53 },
30051 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00008b57, 0x00008b57, 0x00008b57 },
30052 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30053 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30054 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30055 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30056 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30057 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30058 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30059 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30060 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30061 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30062 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30063 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30064 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30065 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30066 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30067 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30068 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30069 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30070 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30071 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30072 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30073 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30074 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30075 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30076 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30077 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30078 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30079 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30080 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30081 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30082 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30083 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30084 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30085 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30086 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30087 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30088 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30089 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30090 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30091 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30092 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30093 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30094 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30095 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30096 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30097 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30098 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30099 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30100 - { 0x00009848, 0x00001066, 0x00001066, 0x00001050, 0x00001050, 0x00001050 },
30101 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001050, 0x00001050, 0x00001050 },
30102 -};
30103 -
30104 -static const u32 ar9280Modes_original_rxgain_9280_2[][6] = {
30105 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
30106 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
30107 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
30108 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
30109 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
30110 - { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
30111 - { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
30112 - { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
30113 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
30114 - { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
30115 - { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
30116 - { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
30117 - { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
30118 - { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
30119 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
30120 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
30121 - { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
30122 - { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
30123 - { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
30124 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
30125 - { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
30126 - { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
30127 - { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
30128 - { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
30129 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
30130 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
30131 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
30132 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
30133 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
30134 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
30135 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
30136 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
30137 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
30138 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
30139 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
30140 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
30141 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
30142 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
30143 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
30144 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
30145 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
30146 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
30147 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
30148 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
30149 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
30150 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
30151 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
30152 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
30153 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
30154 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
30155 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
30156 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
30157 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
30158 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
30159 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
30160 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
30161 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
30162 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
30163 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c },
30164 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 },
30165 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 },
30166 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 },
30167 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 },
30168 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 },
30169 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 },
30170 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 },
30171 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 },
30172 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 },
30173 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 },
30174 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 },
30175 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 },
30176 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c },
30177 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 },
30178 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 },
30179 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 },
30180 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 },
30181 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 },
30182 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 },
30183 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 },
30184 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 },
30185 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad },
30186 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 },
30187 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 },
30188 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 },
30189 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 },
30190 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 },
30191 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 },
30192 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 },
30193 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 },
30194 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 },
30195 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca },
30196 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce },
30197 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 },
30198 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 },
30199 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 },
30200 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 },
30201 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb },
30202 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf },
30203 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 },
30204 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db },
30205 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db },
30206 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db },
30207 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30208 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30209 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30210 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30211 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30212 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30213 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30214 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30215 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30216 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30217 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30218 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30219 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30220 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30221 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30222 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30223 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30224 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30225 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30226 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30227 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30228 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30229 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30230 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30231 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30232 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30233 - { 0x00009848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 },
30234 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 },
30235 -};
30236 -
30237 -static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
30238 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
30239 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
30240 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
30241 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
30242 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
30243 - { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
30244 - { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
30245 - { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
30246 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
30247 - { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
30248 - { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
30249 - { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
30250 - { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
30251 - { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
30252 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
30253 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
30254 - { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
30255 - { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
30256 - { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
30257 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
30258 - { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
30259 - { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
30260 - { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
30261 - { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
30262 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
30263 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
30264 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
30265 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
30266 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
30267 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
30268 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
30269 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
30270 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
30271 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
30272 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
30273 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
30274 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
30275 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
30276 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
30277 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
30278 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
30279 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
30280 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
30281 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
30282 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
30283 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
30284 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
30285 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
30286 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
30287 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
30288 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
30289 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
30290 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
30291 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
30292 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
30293 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
30294 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
30295 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
30296 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x00009310, 0x00009310, 0x00009310 },
30297 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009314, 0x00009314, 0x00009314 },
30298 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009320, 0x00009320, 0x00009320 },
30299 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009324, 0x00009324, 0x00009324 },
30300 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009328, 0x00009328, 0x00009328 },
30301 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x0000932c, 0x0000932c, 0x0000932c },
30302 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x00009330, 0x00009330, 0x00009330 },
30303 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x00009334, 0x00009334, 0x00009334 },
30304 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009321, 0x00009321, 0x00009321 },
30305 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009325, 0x00009325, 0x00009325 },
30306 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009329, 0x00009329, 0x00009329 },
30307 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x0000932d, 0x0000932d, 0x0000932d },
30308 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009331, 0x00009331, 0x00009331 },
30309 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x00009335, 0x00009335, 0x00009335 },
30310 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x00009322, 0x00009322, 0x00009322 },
30311 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x00009326, 0x00009326, 0x00009326 },
30312 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x0000932a, 0x0000932a, 0x0000932a },
30313 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x0000932e, 0x0000932e, 0x0000932e },
30314 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00009332, 0x00009332, 0x00009332 },
30315 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00009336, 0x00009336, 0x00009336 },
30316 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00009323, 0x00009323, 0x00009323 },
30317 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00009327, 0x00009327, 0x00009327 },
30318 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x0000932b, 0x0000932b, 0x0000932b },
30319 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x0000932f, 0x0000932f, 0x0000932f },
30320 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00009333, 0x00009333, 0x00009333 },
30321 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00009337, 0x00009337, 0x00009337 },
30322 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00009343, 0x00009343, 0x00009343 },
30323 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00009347, 0x00009347, 0x00009347 },
30324 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x0000934b, 0x0000934b, 0x0000934b },
30325 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x0000934f, 0x0000934f, 0x0000934f },
30326 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00009353, 0x00009353, 0x00009353 },
30327 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00009357, 0x00009357, 0x00009357 },
30328 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x0000935b, 0x0000935b, 0x0000935b },
30329 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x0000935b, 0x0000935b, 0x0000935b },
30330 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x0000935b, 0x0000935b, 0x0000935b },
30331 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x0000935b, 0x0000935b, 0x0000935b },
30332 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x0000935b, 0x0000935b, 0x0000935b },
30333 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x0000935b, 0x0000935b, 0x0000935b },
30334 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x0000935b, 0x0000935b, 0x0000935b },
30335 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x0000935b, 0x0000935b, 0x0000935b },
30336 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x0000935b, 0x0000935b, 0x0000935b },
30337 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x0000935b, 0x0000935b, 0x0000935b },
30338 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x0000935b, 0x0000935b, 0x0000935b },
30339 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x0000935b, 0x0000935b, 0x0000935b },
30340 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30341 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30342 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30343 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30344 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30345 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30346 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30347 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30348 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30349 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30350 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30351 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30352 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30353 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30354 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30355 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30356 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30357 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30358 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30359 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30360 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30361 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30362 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30363 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30364 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30365 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30366 - { 0x00009848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a },
30367 - { 0x0000a848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a },
30368 -};
30369 -
30370 -static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
30371 - { 0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
30372 - { 0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce },
30373 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30374 - { 0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002, 0x00004002 },
30375 - { 0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008, 0x00007008 },
30376 - { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000c010, 0x0000c010, 0x0000c010 },
30377 - { 0x0000a310, 0x0000e012, 0x0000e012, 0x00010012, 0x00010012, 0x00010012 },
30378 - { 0x0000a314, 0x00011014, 0x00011014, 0x00013014, 0x00013014, 0x00013014 },
30379 - { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001820a, 0x0001820a, 0x0001820a },
30380 - { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001b211, 0x0001b211, 0x0001b211 },
30381 - { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
30382 - { 0x0000a324, 0x00021092, 0x00021092, 0x00022411, 0x00022411, 0x00022411 },
30383 - { 0x0000a328, 0x0002510a, 0x0002510a, 0x00025413, 0x00025413, 0x00025413 },
30384 - { 0x0000a32c, 0x0002910c, 0x0002910c, 0x00029811, 0x00029811, 0x00029811 },
30385 - { 0x0000a330, 0x0002c18b, 0x0002c18b, 0x0002c813, 0x0002c813, 0x0002c813 },
30386 - { 0x0000a334, 0x0002f1cc, 0x0002f1cc, 0x00030a14, 0x00030a14, 0x00030a14 },
30387 - { 0x0000a338, 0x000321eb, 0x000321eb, 0x00035a50, 0x00035a50, 0x00035a50 },
30388 - { 0x0000a33c, 0x000341ec, 0x000341ec, 0x00039c4c, 0x00039c4c, 0x00039c4c },
30389 - { 0x0000a340, 0x000341ec, 0x000341ec, 0x0003de8a, 0x0003de8a, 0x0003de8a },
30390 - { 0x0000a344, 0x000341ec, 0x000341ec, 0x00042e92, 0x00042e92, 0x00042e92 },
30391 - { 0x0000a348, 0x000341ec, 0x000341ec, 0x00046ed2, 0x00046ed2, 0x00046ed2 },
30392 - { 0x0000a34c, 0x000341ec, 0x000341ec, 0x0004bed5, 0x0004bed5, 0x0004bed5 },
30393 - { 0x0000a350, 0x000341ec, 0x000341ec, 0x0004ff54, 0x0004ff54, 0x0004ff54 },
30394 - { 0x0000a354, 0x000341ec, 0x000341ec, 0x00055fd5, 0x00055fd5, 0x00055fd5 },
30395 - { 0x00007814, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff },
30396 - { 0x00007838, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff },
30397 - { 0x0000781c, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 },
30398 - { 0x00007840, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 },
30399 - { 0x00007820, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
30400 - { 0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
30401 -};
30402 -
30403 -static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
30404 - { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
30405 - { 0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce },
30406 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30407 - { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
30408 - { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
30409 - { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b },
30410 - { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 },
30411 - { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 },
30412 - { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a },
30413 - { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 },
30414 - { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
30415 - { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b },
30416 - { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 },
30417 - { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 },
30418 - { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a },
30419 - { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 },
30420 - { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b },
30421 - { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 },
30422 - { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 },
30423 - { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a },
30424 - { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 },
30425 - { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a },
30426 - { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 },
30427 - { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 },
30428 - { 0x00007814, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff },
30429 - { 0x00007838, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff },
30430 - { 0x0000781c, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 },
30431 - { 0x00007840, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 },
30432 - { 0x00007820, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
30433 - { 0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
30434 -};
30435 -
30436 -static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
30437 - {0x00004040, 0x9248fd00 },
30438 - {0x00004040, 0x24924924 },
30439 - {0x00004040, 0xa8000019 },
30440 - {0x00004040, 0x13160820 },
30441 - {0x00004040, 0xe5980560 },
30442 - {0x00004040, 0xc01dcffc },
30443 - {0x00004040, 0x1aaabe41 },
30444 - {0x00004040, 0xbe105554 },
30445 - {0x00004040, 0x00043007 },
30446 - {0x00004044, 0x00000000 },
30447 -};
30448 -
30449 -static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
30450 - {0x00004040, 0x9248fd00 },
30451 - {0x00004040, 0x24924924 },
30452 - {0x00004040, 0xa8000019 },
30453 - {0x00004040, 0x13160820 },
30454 - {0x00004040, 0xe5980560 },
30455 - {0x00004040, 0xc01dcffd },
30456 - {0x00004040, 0x1aaabe41 },
30457 - {0x00004040, 0xbe105554 },
30458 - {0x00004040, 0x00043007 },
30459 - {0x00004044, 0x00000000 },
30460 -};
30461 -
30462 -/* AR9285 Revsion 10*/
30463 -static const u_int32_t ar9285Modes_9285[][6] = {
30464 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
30465 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
30466 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
30467 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
30468 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
30469 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
30470 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
30471 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
30472 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
30473 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
30474 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
30475 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
30476 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
30477 - { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
30478 - { 0x00009844, 0x0372161e, 0x0372161e, 0x03720020, 0x03720020, 0x037216a0 },
30479 - { 0x00009848, 0x00001066, 0x00001066, 0x0000004e, 0x0000004e, 0x00001059 },
30480 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
30481 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
30482 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3136605e, 0x3136605e, 0x3139605e },
30483 - { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
30484 - { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
30485 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
30486 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
30487 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
30488 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
30489 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
30490 - { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1020, 0xdfbc1020, 0xdfbc1010 },
30491 - { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30492 - { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30493 - { 0x000099b8, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c },
30494 - { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
30495 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
30496 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
30497 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
30498 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
30499 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
30500 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30501 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30502 - { 0x00009a00, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
30503 - { 0x00009a04, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
30504 - { 0x00009a08, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
30505 - { 0x00009a0c, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
30506 - { 0x00009a10, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
30507 - { 0x00009a14, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
30508 - { 0x00009a18, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
30509 - { 0x00009a1c, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
30510 - { 0x00009a20, 0x00000000, 0x00000000, 0x00068114, 0x00068114, 0x00000000 },
30511 - { 0x00009a24, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
30512 - { 0x00009a28, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
30513 - { 0x00009a2c, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
30514 - { 0x00009a30, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
30515 - { 0x00009a34, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
30516 - { 0x00009a38, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
30517 - { 0x00009a3c, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
30518 - { 0x00009a40, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
30519 - { 0x00009a44, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
30520 - { 0x00009a48, 0x00000000, 0x00000000, 0x00068284, 0x00068284, 0x00000000 },
30521 - { 0x00009a4c, 0x00000000, 0x00000000, 0x00068288, 0x00068288, 0x00000000 },
30522 - { 0x00009a50, 0x00000000, 0x00000000, 0x00068220, 0x00068220, 0x00000000 },
30523 - { 0x00009a54, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
30524 - { 0x00009a58, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
30525 - { 0x00009a5c, 0x00000000, 0x00000000, 0x00068304, 0x00068304, 0x00000000 },
30526 - { 0x00009a60, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
30527 - { 0x00009a64, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
30528 - { 0x00009a68, 0x00000000, 0x00000000, 0x00068380, 0x00068380, 0x00000000 },
30529 - { 0x00009a6c, 0x00000000, 0x00000000, 0x00068384, 0x00068384, 0x00000000 },
30530 - { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
30531 - { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
30532 - { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
30533 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
30534 - { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
30535 - { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
30536 - { 0x00009a88, 0x00000000, 0x00000000, 0x00068b04, 0x00068b04, 0x00000000 },
30537 - { 0x00009a8c, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
30538 - { 0x00009a90, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
30539 - { 0x00009a94, 0x00000000, 0x00000000, 0x00068b0c, 0x00068b0c, 0x00000000 },
30540 - { 0x00009a98, 0x00000000, 0x00000000, 0x00068b80, 0x00068b80, 0x00000000 },
30541 - { 0x00009a9c, 0x00000000, 0x00000000, 0x00068b84, 0x00068b84, 0x00000000 },
30542 - { 0x00009aa0, 0x00000000, 0x00000000, 0x00068b88, 0x00068b88, 0x00000000 },
30543 - { 0x00009aa4, 0x00000000, 0x00000000, 0x00068b8c, 0x00068b8c, 0x00000000 },
30544 - { 0x00009aa8, 0x00000000, 0x00000000, 0x000b8b90, 0x000b8b90, 0x00000000 },
30545 - { 0x00009aac, 0x00000000, 0x00000000, 0x000b8f80, 0x000b8f80, 0x00000000 },
30546 - { 0x00009ab0, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
30547 - { 0x00009ab4, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
30548 - { 0x00009ab8, 0x00000000, 0x00000000, 0x000b8f8c, 0x000b8f8c, 0x00000000 },
30549 - { 0x00009abc, 0x00000000, 0x00000000, 0x000b8f90, 0x000b8f90, 0x00000000 },
30550 - { 0x00009ac0, 0x00000000, 0x00000000, 0x000bb30c, 0x000bb30c, 0x00000000 },
30551 - { 0x00009ac4, 0x00000000, 0x00000000, 0x000bb310, 0x000bb310, 0x00000000 },
30552 - { 0x00009ac8, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
30553 - { 0x00009acc, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
30554 - { 0x00009ad0, 0x00000000, 0x00000000, 0x000bb324, 0x000bb324, 0x00000000 },
30555 - { 0x00009ad4, 0x00000000, 0x00000000, 0x000bb704, 0x000bb704, 0x00000000 },
30556 - { 0x00009ad8, 0x00000000, 0x00000000, 0x000f96a4, 0x000f96a4, 0x00000000 },
30557 - { 0x00009adc, 0x00000000, 0x00000000, 0x000f96a8, 0x000f96a8, 0x00000000 },
30558 - { 0x00009ae0, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
30559 - { 0x00009ae4, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
30560 - { 0x00009ae8, 0x00000000, 0x00000000, 0x000f9720, 0x000f9720, 0x00000000 },
30561 - { 0x00009aec, 0x00000000, 0x00000000, 0x000f9724, 0x000f9724, 0x00000000 },
30562 - { 0x00009af0, 0x00000000, 0x00000000, 0x000f9728, 0x000f9728, 0x00000000 },
30563 - { 0x00009af4, 0x00000000, 0x00000000, 0x000f972c, 0x000f972c, 0x00000000 },
30564 - { 0x00009af8, 0x00000000, 0x00000000, 0x000f97a0, 0x000f97a0, 0x00000000 },
30565 - { 0x00009afc, 0x00000000, 0x00000000, 0x000f97a4, 0x000f97a4, 0x00000000 },
30566 - { 0x00009b00, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
30567 - { 0x00009b04, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
30568 - { 0x00009b08, 0x00000000, 0x00000000, 0x000fb7b4, 0x000fb7b4, 0x00000000 },
30569 - { 0x00009b0c, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
30570 - { 0x00009b10, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
30571 - { 0x00009b14, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
30572 - { 0x00009b18, 0x00000000, 0x00000000, 0x000fb7ad, 0x000fb7ad, 0x00000000 },
30573 - { 0x00009b1c, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
30574 - { 0x00009b20, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
30575 - { 0x00009b24, 0x00000000, 0x00000000, 0x000fb7b9, 0x000fb7b9, 0x00000000 },
30576 - { 0x00009b28, 0x00000000, 0x00000000, 0x000fb7c5, 0x000fb7c5, 0x00000000 },
30577 - { 0x00009b2c, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
30578 - { 0x00009b30, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
30579 - { 0x00009b34, 0x00000000, 0x00000000, 0x000fb7d5, 0x000fb7d5, 0x00000000 },
30580 - { 0x00009b38, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
30581 - { 0x00009b3c, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
30582 - { 0x00009b40, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
30583 - { 0x00009b44, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
30584 - { 0x00009b48, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
30585 - { 0x00009b4c, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
30586 - { 0x00009b50, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
30587 - { 0x00009b54, 0x00000000, 0x00000000, 0x000fb7c7, 0x000fb7c7, 0x00000000 },
30588 - { 0x00009b58, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
30589 - { 0x00009b5c, 0x00000000, 0x00000000, 0x000fb7cf, 0x000fb7cf, 0x00000000 },
30590 - { 0x00009b60, 0x00000000, 0x00000000, 0x000fb7d7, 0x000fb7d7, 0x00000000 },
30591 - { 0x00009b64, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30592 - { 0x00009b68, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30593 - { 0x00009b6c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30594 - { 0x00009b70, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30595 - { 0x00009b74, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30596 - { 0x00009b78, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30597 - { 0x00009b7c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30598 - { 0x00009b80, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30599 - { 0x00009b84, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30600 - { 0x00009b88, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30601 - { 0x00009b8c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30602 - { 0x00009b90, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30603 - { 0x00009b94, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30604 - { 0x00009b98, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30605 - { 0x00009b9c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30606 - { 0x00009ba0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30607 - { 0x00009ba4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30608 - { 0x00009ba8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30609 - { 0x00009bac, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30610 - { 0x00009bb0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30611 - { 0x00009bb4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30612 - { 0x00009bb8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30613 - { 0x00009bbc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30614 - { 0x00009bc0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30615 - { 0x00009bc4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30616 - { 0x00009bc8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30617 - { 0x00009bcc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30618 - { 0x00009bd0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30619 - { 0x00009bd4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30620 - { 0x00009bd8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30621 - { 0x00009bdc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30622 - { 0x00009be0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30623 - { 0x00009be4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30624 - { 0x00009be8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30625 - { 0x00009bec, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30626 - { 0x00009bf0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30627 - { 0x00009bf4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30628 - { 0x00009bf8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30629 - { 0x00009bfc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30630 - { 0x0000aa00, 0x00000000, 0x00000000, 0x0006801c, 0x0006801c, 0x00000000 },
30631 - { 0x0000aa04, 0x00000000, 0x00000000, 0x00068080, 0x00068080, 0x00000000 },
30632 - { 0x0000aa08, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
30633 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
30634 - { 0x0000aa10, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
30635 - { 0x0000aa14, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
30636 - { 0x0000aa18, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
30637 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
30638 - { 0x0000aa20, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
30639 - { 0x0000aa24, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
30640 - { 0x0000aa28, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
30641 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
30642 - { 0x0000aa30, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
30643 - { 0x0000aa34, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
30644 - { 0x0000aa38, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
30645 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
30646 - { 0x0000aa40, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
30647 - { 0x0000aa44, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
30648 - { 0x0000aa48, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
30649 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
30650 - { 0x0000aa50, 0x00000000, 0x00000000, 0x000681ac, 0x000681ac, 0x00000000 },
30651 - { 0x0000aa54, 0x00000000, 0x00000000, 0x0006821c, 0x0006821c, 0x00000000 },
30652 - { 0x0000aa58, 0x00000000, 0x00000000, 0x00068224, 0x00068224, 0x00000000 },
30653 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
30654 - { 0x0000aa60, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
30655 - { 0x0000aa64, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
30656 - { 0x0000aa68, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
30657 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x00068310, 0x00068310, 0x00000000 },
30658 - { 0x0000aa70, 0x00000000, 0x00000000, 0x00068788, 0x00068788, 0x00000000 },
30659 - { 0x0000aa74, 0x00000000, 0x00000000, 0x0006878c, 0x0006878c, 0x00000000 },
30660 - { 0x0000aa78, 0x00000000, 0x00000000, 0x00068790, 0x00068790, 0x00000000 },
30661 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x00068794, 0x00068794, 0x00000000 },
30662 - { 0x0000aa80, 0x00000000, 0x00000000, 0x00068798, 0x00068798, 0x00000000 },
30663 - { 0x0000aa84, 0x00000000, 0x00000000, 0x0006879c, 0x0006879c, 0x00000000 },
30664 - { 0x0000aa88, 0x00000000, 0x00000000, 0x00068b89, 0x00068b89, 0x00000000 },
30665 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x00068b8d, 0x00068b8d, 0x00000000 },
30666 - { 0x0000aa90, 0x00000000, 0x00000000, 0x00068b91, 0x00068b91, 0x00000000 },
30667 - { 0x0000aa94, 0x00000000, 0x00000000, 0x00068b95, 0x00068b95, 0x00000000 },
30668 - { 0x0000aa98, 0x00000000, 0x00000000, 0x00068b99, 0x00068b99, 0x00000000 },
30669 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x00068ba5, 0x00068ba5, 0x00000000 },
30670 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x00068ba9, 0x00068ba9, 0x00000000 },
30671 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x00068bad, 0x00068bad, 0x00000000 },
30672 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x000b8b0c, 0x000b8b0c, 0x00000000 },
30673 - { 0x0000aaac, 0x00000000, 0x00000000, 0x000b8f10, 0x000b8f10, 0x00000000 },
30674 - { 0x0000aab0, 0x00000000, 0x00000000, 0x000b8f14, 0x000b8f14, 0x00000000 },
30675 - { 0x0000aab4, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
30676 - { 0x0000aab8, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
30677 - { 0x0000aabc, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
30678 - { 0x0000aac0, 0x00000000, 0x00000000, 0x000bb380, 0x000bb380, 0x00000000 },
30679 - { 0x0000aac4, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
30680 - { 0x0000aac8, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
30681 - { 0x0000aacc, 0x00000000, 0x00000000, 0x000bb38c, 0x000bb38c, 0x00000000 },
30682 - { 0x0000aad0, 0x00000000, 0x00000000, 0x000bb394, 0x000bb394, 0x00000000 },
30683 - { 0x0000aad4, 0x00000000, 0x00000000, 0x000bb798, 0x000bb798, 0x00000000 },
30684 - { 0x0000aad8, 0x00000000, 0x00000000, 0x000f970c, 0x000f970c, 0x00000000 },
30685 - { 0x0000aadc, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
30686 - { 0x0000aae0, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
30687 - { 0x0000aae4, 0x00000000, 0x00000000, 0x000f9718, 0x000f9718, 0x00000000 },
30688 - { 0x0000aae8, 0x00000000, 0x00000000, 0x000f9705, 0x000f9705, 0x00000000 },
30689 - { 0x0000aaec, 0x00000000, 0x00000000, 0x000f9709, 0x000f9709, 0x00000000 },
30690 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x000f970d, 0x000f970d, 0x00000000 },
30691 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x000f9711, 0x000f9711, 0x00000000 },
30692 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x000f9715, 0x000f9715, 0x00000000 },
30693 - { 0x0000aafc, 0x00000000, 0x00000000, 0x000f9719, 0x000f9719, 0x00000000 },
30694 - { 0x0000ab00, 0x00000000, 0x00000000, 0x000fb7a4, 0x000fb7a4, 0x00000000 },
30695 - { 0x0000ab04, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
30696 - { 0x0000ab08, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
30697 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
30698 - { 0x0000ab10, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
30699 - { 0x0000ab14, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
30700 - { 0x0000ab18, 0x00000000, 0x00000000, 0x000fb7bc, 0x000fb7bc, 0x00000000 },
30701 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x000fb7a1, 0x000fb7a1, 0x00000000 },
30702 - { 0x0000ab20, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
30703 - { 0x0000ab24, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
30704 - { 0x0000ab28, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
30705 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
30706 - { 0x0000ab30, 0x00000000, 0x00000000, 0x000fb7bd, 0x000fb7bd, 0x00000000 },
30707 - { 0x0000ab34, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
30708 - { 0x0000ab38, 0x00000000, 0x00000000, 0x000fb7cd, 0x000fb7cd, 0x00000000 },
30709 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
30710 - { 0x0000ab40, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
30711 - { 0x0000ab44, 0x00000000, 0x00000000, 0x000fb7c2, 0x000fb7c2, 0x00000000 },
30712 - { 0x0000ab48, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
30713 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
30714 - { 0x0000ab50, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
30715 - { 0x0000ab54, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
30716 - { 0x0000ab58, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
30717 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
30718 - { 0x0000ab60, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
30719 - { 0x0000ab64, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30720 - { 0x0000ab68, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30721 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30722 - { 0x0000ab70, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30723 - { 0x0000ab74, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30724 - { 0x0000ab78, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30725 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30726 - { 0x0000ab80, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30727 - { 0x0000ab84, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30728 - { 0x0000ab88, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30729 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30730 - { 0x0000ab90, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30731 - { 0x0000ab94, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30732 - { 0x0000ab98, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30733 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30734 - { 0x0000aba0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30735 - { 0x0000aba4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30736 - { 0x0000aba8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30737 - { 0x0000abac, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30738 - { 0x0000abb0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30739 - { 0x0000abb4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30740 - { 0x0000abb8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30741 - { 0x0000abbc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30742 - { 0x0000abc0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30743 - { 0x0000abc4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30744 - { 0x0000abc8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30745 - { 0x0000abcc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30746 - { 0x0000abd0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30747 - { 0x0000abd4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30748 - { 0x0000abd8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30749 - { 0x0000abdc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30750 - { 0x0000abe0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30751 - { 0x0000abe4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30752 - { 0x0000abe8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30753 - { 0x0000abec, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30754 - { 0x0000abf0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30755 - { 0x0000abf4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30756 - { 0x0000abf8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30757 - { 0x0000abfc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30758 - { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
30759 - { 0x0000a20c, 0x00000014, 0x00000014, 0x00000000, 0x00000000, 0x0001f000 },
30760 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
30761 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
30762 - { 0x0000a250, 0x001ff000, 0x001ff000, 0x001ca000, 0x001ca000, 0x001da000 },
30763 - { 0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652, 0x0a82a652 },
30764 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30765 - { 0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
30766 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408, 0x00000000 },
30767 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a, 0x00000000 },
30768 - { 0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818, 0x00000000 },
30769 - { 0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858, 0x00000000 },
30770 - { 0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859, 0x00000000 },
30771 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b, 0x00000000 },
30772 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002c89a, 0x0002c89a, 0x00000000 },
30773 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002e89b, 0x0002e89b, 0x00000000 },
30774 - { 0x0000a328, 0x00000000, 0x00000000, 0x0003089c, 0x0003089c, 0x00000000 },
30775 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0003289d, 0x0003289d, 0x00000000 },
30776 - { 0x0000a330, 0x00000000, 0x00000000, 0x0003489e, 0x0003489e, 0x00000000 },
30777 - { 0x0000a334, 0x00000000, 0x00000000, 0x000388de, 0x000388de, 0x00000000 },
30778 - { 0x0000a338, 0x00000000, 0x00000000, 0x0003b91e, 0x0003b91e, 0x00000000 },
30779 - { 0x0000a33c, 0x00000000, 0x00000000, 0x0003d95e, 0x0003d95e, 0x00000000 },
30780 - { 0x0000a340, 0x00000000, 0x00000000, 0x000419df, 0x000419df, 0x00000000 },
30781 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
30782 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
30783 -};
30784 -
30785 -static const u_int32_t ar9285Common_9285[][2] = {
30786 - { 0x0000000c, 0x00000000 },
30787 - { 0x00000030, 0x00020045 },
30788 - { 0x00000034, 0x00000005 },
30789 - { 0x00000040, 0x00000000 },
30790 - { 0x00000044, 0x00000008 },
30791 - { 0x00000048, 0x00000008 },
30792 - { 0x0000004c, 0x00000010 },
30793 - { 0x00000050, 0x00000000 },
30794 - { 0x00000054, 0x0000001f },
30795 - { 0x00000800, 0x00000000 },
30796 - { 0x00000804, 0x00000000 },
30797 - { 0x00000808, 0x00000000 },
30798 - { 0x0000080c, 0x00000000 },
30799 - { 0x00000810, 0x00000000 },
30800 - { 0x00000814, 0x00000000 },
30801 - { 0x00000818, 0x00000000 },
30802 - { 0x0000081c, 0x00000000 },
30803 - { 0x00000820, 0x00000000 },
30804 - { 0x00000824, 0x00000000 },
30805 - { 0x00001040, 0x002ffc0f },
30806 - { 0x00001044, 0x002ffc0f },
30807 - { 0x00001048, 0x002ffc0f },
30808 - { 0x0000104c, 0x002ffc0f },
30809 - { 0x00001050, 0x002ffc0f },
30810 - { 0x00001054, 0x002ffc0f },
30811 - { 0x00001058, 0x002ffc0f },
30812 - { 0x0000105c, 0x002ffc0f },
30813 - { 0x00001060, 0x002ffc0f },
30814 - { 0x00001064, 0x002ffc0f },
30815 - { 0x00001230, 0x00000000 },
30816 - { 0x00001270, 0x00000000 },
30817 - { 0x00001038, 0x00000000 },
30818 - { 0x00001078, 0x00000000 },
30819 - { 0x000010b8, 0x00000000 },
30820 - { 0x000010f8, 0x00000000 },
30821 - { 0x00001138, 0x00000000 },
30822 - { 0x00001178, 0x00000000 },
30823 - { 0x000011b8, 0x00000000 },
30824 - { 0x000011f8, 0x00000000 },
30825 - { 0x00001238, 0x00000000 },
30826 - { 0x00001278, 0x00000000 },
30827 - { 0x000012b8, 0x00000000 },
30828 - { 0x000012f8, 0x00000000 },
30829 - { 0x00001338, 0x00000000 },
30830 - { 0x00001378, 0x00000000 },
30831 - { 0x000013b8, 0x00000000 },
30832 - { 0x000013f8, 0x00000000 },
30833 - { 0x00001438, 0x00000000 },
30834 - { 0x00001478, 0x00000000 },
30835 - { 0x000014b8, 0x00000000 },
30836 - { 0x000014f8, 0x00000000 },
30837 - { 0x00001538, 0x00000000 },
30838 - { 0x00001578, 0x00000000 },
30839 - { 0x000015b8, 0x00000000 },
30840 - { 0x000015f8, 0x00000000 },
30841 - { 0x00001638, 0x00000000 },
30842 - { 0x00001678, 0x00000000 },
30843 - { 0x000016b8, 0x00000000 },
30844 - { 0x000016f8, 0x00000000 },
30845 - { 0x00001738, 0x00000000 },
30846 - { 0x00001778, 0x00000000 },
30847 - { 0x000017b8, 0x00000000 },
30848 - { 0x000017f8, 0x00000000 },
30849 - { 0x0000103c, 0x00000000 },
30850 - { 0x0000107c, 0x00000000 },
30851 - { 0x000010bc, 0x00000000 },
30852 - { 0x000010fc, 0x00000000 },
30853 - { 0x0000113c, 0x00000000 },
30854 - { 0x0000117c, 0x00000000 },
30855 - { 0x000011bc, 0x00000000 },
30856 - { 0x000011fc, 0x00000000 },
30857 - { 0x0000123c, 0x00000000 },
30858 - { 0x0000127c, 0x00000000 },
30859 - { 0x000012bc, 0x00000000 },
30860 - { 0x000012fc, 0x00000000 },
30861 - { 0x0000133c, 0x00000000 },
30862 - { 0x0000137c, 0x00000000 },
30863 - { 0x000013bc, 0x00000000 },
30864 - { 0x000013fc, 0x00000000 },
30865 - { 0x0000143c, 0x00000000 },
30866 - { 0x0000147c, 0x00000000 },
30867 - { 0x00004030, 0x00000002 },
30868 - { 0x0000403c, 0x00000002 },
30869 - { 0x00004024, 0x0000001f },
30870 - { 0x00004060, 0x00000000 },
30871 - { 0x00004064, 0x00000000 },
30872 - { 0x00007010, 0x00000031 },
30873 - { 0x00007034, 0x00000002 },
30874 - { 0x00007038, 0x000004c2 },
30875 - { 0x00008004, 0x00000000 },
30876 - { 0x00008008, 0x00000000 },
30877 - { 0x0000800c, 0x00000000 },
30878 - { 0x00008018, 0x00000700 },
30879 - { 0x00008020, 0x00000000 },
30880 - { 0x00008038, 0x00000000 },
30881 - { 0x0000803c, 0x00000000 },
30882 - { 0x00008048, 0x00000000 },
30883 - { 0x00008054, 0x00000000 },
30884 - { 0x00008058, 0x00000000 },
30885 - { 0x0000805c, 0x000fc78f },
30886 - { 0x00008060, 0x0000000f },
30887 - { 0x00008064, 0x00000000 },
30888 - { 0x00008070, 0x00000000 },
30889 - { 0x000080c0, 0x2a80001a },
30890 - { 0x000080c4, 0x05dc01e0 },
30891 - { 0x000080c8, 0x1f402710 },
30892 - { 0x000080cc, 0x01f40000 },
30893 - { 0x000080d0, 0x00001e00 },
30894 - { 0x000080d4, 0x00000000 },
30895 - { 0x000080d8, 0x00400000 },
30896 - { 0x000080e0, 0xffffffff },
30897 - { 0x000080e4, 0x0000ffff },
30898 - { 0x000080e8, 0x003f3f3f },
30899 - { 0x000080ec, 0x00000000 },
30900 - { 0x000080f0, 0x00000000 },
30901 - { 0x000080f4, 0x00000000 },
30902 - { 0x000080f8, 0x00000000 },
30903 - { 0x000080fc, 0x00020000 },
30904 - { 0x00008100, 0x00020000 },
30905 - { 0x00008104, 0x00000001 },
30906 - { 0x00008108, 0x00000052 },
30907 - { 0x0000810c, 0x00000000 },
30908 - { 0x00008110, 0x00000168 },
30909 - { 0x00008118, 0x000100aa },
30910 - { 0x0000811c, 0x00003210 },
30911 - { 0x00008120, 0x08f04800 },
30912 - { 0x00008124, 0x00000000 },
30913 - { 0x00008128, 0x00000000 },
30914 - { 0x0000812c, 0x00000000 },
30915 - { 0x00008130, 0x00000000 },
30916 - { 0x00008134, 0x00000000 },
30917 - { 0x00008138, 0x00000000 },
30918 - { 0x0000813c, 0x00000000 },
30919 - { 0x00008144, 0x00000000 },
30920 - { 0x00008168, 0x00000000 },
30921 - { 0x0000816c, 0x00000000 },
30922 - { 0x00008170, 0x32143320 },
30923 - { 0x00008174, 0xfaa4fa50 },
30924 - { 0x00008178, 0x00000100 },
30925 - { 0x0000817c, 0x00000000 },
30926 - { 0x000081c0, 0x00000000 },
30927 - { 0x000081d0, 0x00003210 },
30928 - { 0x000081ec, 0x00000000 },
30929 - { 0x000081f0, 0x00000000 },
30930 - { 0x000081f4, 0x00000000 },
30931 - { 0x000081f8, 0x00000000 },
30932 - { 0x000081fc, 0x00000000 },
30933 - { 0x00008200, 0x00000000 },
30934 - { 0x00008204, 0x00000000 },
30935 - { 0x00008208, 0x00000000 },
30936 - { 0x0000820c, 0x00000000 },
30937 - { 0x00008210, 0x00000000 },
30938 - { 0x00008214, 0x00000000 },
30939 - { 0x00008218, 0x00000000 },
30940 - { 0x0000821c, 0x00000000 },
30941 - { 0x00008220, 0x00000000 },
30942 - { 0x00008224, 0x00000000 },
30943 - { 0x00008228, 0x00000000 },
30944 - { 0x0000822c, 0x00000000 },
30945 - { 0x00008230, 0x00000000 },
30946 - { 0x00008234, 0x00000000 },
30947 - { 0x00008238, 0x00000000 },
30948 - { 0x0000823c, 0x00000000 },
30949 - { 0x00008240, 0x00100000 },
30950 - { 0x00008244, 0x0010f400 },
30951 - { 0x00008248, 0x00000100 },
30952 - { 0x0000824c, 0x0001e800 },
30953 - { 0x00008250, 0x00000000 },
30954 - { 0x00008254, 0x00000000 },
30955 - { 0x00008258, 0x00000000 },
30956 - { 0x0000825c, 0x400000ff },
30957 - { 0x00008260, 0x00080922 },
30958 - { 0x00008264, 0xa8a00010 },
30959 - { 0x00008270, 0x00000000 },
30960 - { 0x00008274, 0x40000000 },
30961 - { 0x00008278, 0x003e4180 },
30962 - { 0x0000827c, 0x00000000 },
30963 - { 0x00008284, 0x0000002c },
30964 - { 0x00008288, 0x0000002c },
30965 - { 0x0000828c, 0x00000000 },
30966 - { 0x00008294, 0x00000000 },
30967 - { 0x00008298, 0x00000000 },
30968 - { 0x0000829c, 0x00000000 },
30969 - { 0x00008300, 0x00000040 },
30970 - { 0x00008314, 0x00000000 },
30971 - { 0x00008328, 0x00000000 },
30972 - { 0x0000832c, 0x00000001 },
30973 - { 0x00008330, 0x00000302 },
30974 - { 0x00008334, 0x00000e00 },
30975 - { 0x00008338, 0x00000000 },
30976 - { 0x0000833c, 0x00000000 },
30977 - { 0x00008340, 0x00010380 },
30978 - { 0x00008344, 0x00481043 },
30979 - { 0x00009808, 0x00000000 },
30980 - { 0x0000980c, 0xafe68e30 },
30981 - { 0x00009810, 0xfd14e000 },
30982 - { 0x00009814, 0x9c0a9f6b },
30983 - { 0x0000981c, 0x00000000 },
30984 - { 0x0000982c, 0x0000a000 },
30985 - { 0x00009830, 0x00000000 },
30986 - { 0x0000983c, 0x00200400 },
30987 - { 0x0000984c, 0x0040233c },
30988 - { 0x00009854, 0x00000044 },
30989 - { 0x00009900, 0x00000000 },
30990 - { 0x00009904, 0x00000000 },
30991 - { 0x00009908, 0x00000000 },
30992 - { 0x0000990c, 0x00000000 },
30993 - { 0x00009910, 0x01002310 },
30994 - { 0x0000991c, 0x10000fff },
30995 - { 0x00009920, 0x04900000 },
30996 - { 0x00009928, 0x00000001 },
30997 - { 0x0000992c, 0x00000004 },
30998 - { 0x00009934, 0x1e1f2022 },
30999 - { 0x00009938, 0x0a0b0c0d },
31000 - { 0x0000993c, 0x00000000 },
31001 - { 0x00009940, 0x14750604 },
31002 - { 0x00009948, 0x9280c00a },
31003 - { 0x0000994c, 0x00020028 },
31004 - { 0x00009954, 0x5f3ca3de },
31005 - { 0x00009958, 0x2108ecff },
31006 - { 0x00009968, 0x000003ce },
31007 - { 0x00009970, 0x1927b515 },
31008 - { 0x00009974, 0x00000000 },
31009 - { 0x00009978, 0x00000001 },
31010 - { 0x0000997c, 0x00000000 },
31011 - { 0x00009980, 0x00000000 },
31012 - { 0x00009984, 0x00000000 },
31013 - { 0x00009988, 0x00000000 },
31014 - { 0x0000998c, 0x00000000 },
31015 - { 0x00009990, 0x00000000 },
31016 - { 0x00009994, 0x00000000 },
31017 - { 0x00009998, 0x00000000 },
31018 - { 0x0000999c, 0x00000000 },
31019 - { 0x000099a0, 0x00000000 },
31020 - { 0x000099a4, 0x00000001 },
31021 - { 0x000099a8, 0x201fff00 },
31022 - { 0x000099ac, 0x2def0a00 },
31023 - { 0x000099b0, 0x03051000 },
31024 - { 0x000099b4, 0x00000820 },
31025 - { 0x000099dc, 0x00000000 },
31026 - { 0x000099e0, 0x00000000 },
31027 - { 0x000099e4, 0xaaaaaaaa },
31028 - { 0x000099e8, 0x3c466478 },
31029 - { 0x000099ec, 0x0cc80caa },
31030 - { 0x000099f0, 0x00000000 },
31031 - { 0x0000a208, 0x803e6788 },
31032 - { 0x0000a210, 0x4080a333 },
31033 - { 0x0000a214, 0x00206c10 },
31034 - { 0x0000a218, 0x009c4060 },
31035 - { 0x0000a220, 0x01834061 },
31036 - { 0x0000a224, 0x00000400 },
31037 - { 0x0000a228, 0x000003b5 },
31038 - { 0x0000a22c, 0x00000000 },
31039 - { 0x0000a234, 0x20202020 },
31040 - { 0x0000a238, 0x20202020 },
31041 - { 0x0000a244, 0x00000000 },
31042 - { 0x0000a248, 0xfffffffc },
31043 - { 0x0000a24c, 0x00000000 },
31044 - { 0x0000a254, 0x00000000 },
31045 - { 0x0000a258, 0x0ccb5380 },
31046 - { 0x0000a25c, 0x15151501 },
31047 - { 0x0000a260, 0xdfa90f01 },
31048 - { 0x0000a268, 0x00000000 },
31049 - { 0x0000a26c, 0x0ebae9e6 },
31050 - { 0x0000d270, 0x0d820820 },
31051 - { 0x0000a278, 0x39ce739c },
31052 - { 0x0000a27c, 0x050e039c },
31053 - { 0x0000d35c, 0x07ffffef },
31054 - { 0x0000d360, 0x0fffffe7 },
31055 - { 0x0000d364, 0x17ffffe5 },
31056 - { 0x0000d368, 0x1fffffe4 },
31057 - { 0x0000d36c, 0x37ffffe3 },
31058 - { 0x0000d370, 0x3fffffe3 },
31059 - { 0x0000d374, 0x57ffffe3 },
31060 - { 0x0000d378, 0x5fffffe2 },
31061 - { 0x0000d37c, 0x7fffffe2 },
31062 - { 0x0000d380, 0x7f3c7bba },
31063 - { 0x0000d384, 0xf3307ff0 },
31064 - { 0x0000a388, 0x0c000000 },
31065 - { 0x0000a38c, 0x20202020 },
31066 - { 0x0000a390, 0x20202020 },
31067 - { 0x0000a394, 0x39ce739c },
31068 - { 0x0000a398, 0x0000039c },
31069 - { 0x0000a39c, 0x00000001 },
31070 - { 0x0000a3a0, 0x00000000 },
31071 - { 0x0000a3a4, 0x00000000 },
31072 - { 0x0000a3a8, 0x00000000 },
31073 - { 0x0000a3ac, 0x00000000 },
31074 - { 0x0000a3b0, 0x00000000 },
31075 - { 0x0000a3b4, 0x00000000 },
31076 - { 0x0000a3b8, 0x00000000 },
31077 - { 0x0000a3bc, 0x00000000 },
31078 - { 0x0000a3c0, 0x00000000 },
31079 - { 0x0000a3c4, 0x00000000 },
31080 - { 0x0000a3cc, 0x20202020 },
31081 - { 0x0000a3d0, 0x20202020 },
31082 - { 0x0000a3d4, 0x20202020 },
31083 - { 0x0000a3dc, 0x39ce739c },
31084 - { 0x0000a3e0, 0x0000039c },
31085 - { 0x0000a3e4, 0x00000000 },
31086 - { 0x0000a3e8, 0x18c43433 },
31087 - { 0x0000a3ec, 0x00f70081 },
31088 - { 0x00007800, 0x00140000 },
31089 - { 0x00007804, 0x0e4548d8 },
31090 - { 0x00007808, 0x54214514 },
31091 - { 0x0000780c, 0x02025820 },
31092 - { 0x00007810, 0x71c0d388 },
31093 - { 0x00007814, 0x924934a8 },
31094 - { 0x0000781c, 0x00000000 },
31095 - { 0x00007820, 0x00000c04 },
31096 - { 0x00007824, 0x00d86fff },
31097 - { 0x00007828, 0x26d2491b },
31098 - { 0x0000782c, 0x6e36d97b },
31099 - { 0x00007830, 0xedb6d96c },
31100 - { 0x00007834, 0x71400086 },
31101 - { 0x00007838, 0xfac68800 },
31102 - { 0x0000783c, 0x0001fffe },
31103 - { 0x00007840, 0xffeb1a20 },
31104 - { 0x00007844, 0x000c0db6 },
31105 - { 0x00007848, 0x6db61b6f },
31106 - { 0x0000784c, 0x6d9b66db },
31107 - { 0x00007850, 0x6d8c6dba },
31108 - { 0x00007854, 0x00040000 },
31109 - { 0x00007858, 0xdb003012 },
31110 - { 0x0000785c, 0x04924914 },
31111 - { 0x00007860, 0x21084210 },
31112 - { 0x00007864, 0xf7d7ffde },
31113 - { 0x00007868, 0xc2034080 },
31114 - { 0x0000786c, 0x48609eb4 },
31115 - { 0x00007870, 0x10142c00 },
31116 -};
31117 -
31118 -static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
31119 - {0x00004040, 0x9248fd00 },
31120 - {0x00004040, 0x24924924 },
31121 - {0x00004040, 0xa8000019 },
31122 - {0x00004040, 0x13160820 },
31123 - {0x00004040, 0xe5980560 },
31124 - {0x00004040, 0xc01dcffd },
31125 - {0x00004040, 0x1aaabe41 },
31126 - {0x00004040, 0xbe105554 },
31127 - {0x00004040, 0x00043007 },
31128 - {0x00004044, 0x00000000 },
31129 -};
31130 -
31131 -static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285[][2] = {
31132 - {0x00004040, 0x9248fd00 },
31133 - {0x00004040, 0x24924924 },
31134 - {0x00004040, 0xa8000019 },
31135 - {0x00004040, 0x13160820 },
31136 - {0x00004040, 0xe5980560 },
31137 - {0x00004040, 0xc01dcffc },
31138 - {0x00004040, 0x1aaabe41 },
31139 - {0x00004040, 0xbe105554 },
31140 - {0x00004040, 0x00043007 },
31141 - {0x00004044, 0x00000000 },
31142 -};
31143 -
31144 -/* AR9285 v1_2 PCI Register Writes. Created: 04/13/09 */
31145 -static const u_int32_t ar9285Modes_9285_1_2[][6] = {
31146 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
31147 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
31148 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
31149 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
31150 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
31151 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
31152 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
31153 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
31154 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
31155 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
31156 - { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
31157 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
31158 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
31159 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
31160 - { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
31161 - { 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
31162 - { 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
31163 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
31164 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
31165 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
31166 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
31167 - { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
31168 - { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
31169 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
31170 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
31171 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
31172 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
31173 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
31174 - { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
31175 - { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31176 - { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31177 - { 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
31178 - { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
31179 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
31180 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
31181 - { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
31182 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
31183 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
31184 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31185 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31186 - { 0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
31187 - { 0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
31188 - { 0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
31189 - { 0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
31190 - { 0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
31191 - { 0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
31192 - { 0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
31193 - { 0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
31194 - { 0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
31195 - { 0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
31196 - { 0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
31197 - { 0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
31198 - { 0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
31199 - { 0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
31200 - { 0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
31201 - { 0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
31202 - { 0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
31203 - { 0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
31204 - { 0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
31205 - { 0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
31206 - { 0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
31207 - { 0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
31208 - { 0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
31209 - { 0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
31210 - { 0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
31211 - { 0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
31212 - { 0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
31213 - { 0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
31214 - { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
31215 - { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
31216 - { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
31217 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
31218 - { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
31219 - { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
31220 - { 0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
31221 - { 0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
31222 - { 0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
31223 - { 0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
31224 - { 0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
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31432 - { 0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31433 - { 0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31434 - { 0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31435 - { 0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31436 - { 0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31437 - { 0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31438 - { 0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31439 - { 0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31440 - { 0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31441 - { 0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31442 - { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
31443 - { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
31444 - { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
31445 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
31446 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
31447 - { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
31448 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
31449 -};
31450 -
31451 -static const u_int32_t ar9285Common_9285_1_2[][2] = {
31452 - { 0x0000000c, 0x00000000 },
31453 - { 0x00000030, 0x00020045 },
31454 - { 0x00000034, 0x00000005 },
31455 - { 0x00000040, 0x00000000 },
31456 - { 0x00000044, 0x00000008 },
31457 - { 0x00000048, 0x00000008 },
31458 - { 0x0000004c, 0x00000010 },
31459 - { 0x00000050, 0x00000000 },
31460 - { 0x00000054, 0x0000001f },
31461 - { 0x00000800, 0x00000000 },
31462 - { 0x00000804, 0x00000000 },
31463 - { 0x00000808, 0x00000000 },
31464 - { 0x0000080c, 0x00000000 },
31465 - { 0x00000810, 0x00000000 },
31466 - { 0x00000814, 0x00000000 },
31467 - { 0x00000818, 0x00000000 },
31468 - { 0x0000081c, 0x00000000 },
31469 - { 0x00000820, 0x00000000 },
31470 - { 0x00000824, 0x00000000 },
31471 - { 0x00001040, 0x002ffc0f },
31472 - { 0x00001044, 0x002ffc0f },
31473 - { 0x00001048, 0x002ffc0f },
31474 - { 0x0000104c, 0x002ffc0f },
31475 - { 0x00001050, 0x002ffc0f },
31476 - { 0x00001054, 0x002ffc0f },
31477 - { 0x00001058, 0x002ffc0f },
31478 - { 0x0000105c, 0x002ffc0f },
31479 - { 0x00001060, 0x002ffc0f },
31480 - { 0x00001064, 0x002ffc0f },
31481 - { 0x00001230, 0x00000000 },
31482 - { 0x00001270, 0x00000000 },
31483 - { 0x00001038, 0x00000000 },
31484 - { 0x00001078, 0x00000000 },
31485 - { 0x000010b8, 0x00000000 },
31486 - { 0x000010f8, 0x00000000 },
31487 - { 0x00001138, 0x00000000 },
31488 - { 0x00001178, 0x00000000 },
31489 - { 0x000011b8, 0x00000000 },
31490 - { 0x000011f8, 0x00000000 },
31491 - { 0x00001238, 0x00000000 },
31492 - { 0x00001278, 0x00000000 },
31493 - { 0x000012b8, 0x00000000 },
31494 - { 0x000012f8, 0x00000000 },
31495 - { 0x00001338, 0x00000000 },
31496 - { 0x00001378, 0x00000000 },
31497 - { 0x000013b8, 0x00000000 },
31498 - { 0x000013f8, 0x00000000 },
31499 - { 0x00001438, 0x00000000 },
31500 - { 0x00001478, 0x00000000 },
31501 - { 0x000014b8, 0x00000000 },
31502 - { 0x000014f8, 0x00000000 },
31503 - { 0x00001538, 0x00000000 },
31504 - { 0x00001578, 0x00000000 },
31505 - { 0x000015b8, 0x00000000 },
31506 - { 0x000015f8, 0x00000000 },
31507 - { 0x00001638, 0x00000000 },
31508 - { 0x00001678, 0x00000000 },
31509 - { 0x000016b8, 0x00000000 },
31510 - { 0x000016f8, 0x00000000 },
31511 - { 0x00001738, 0x00000000 },
31512 - { 0x00001778, 0x00000000 },
31513 - { 0x000017b8, 0x00000000 },
31514 - { 0x000017f8, 0x00000000 },
31515 - { 0x0000103c, 0x00000000 },
31516 - { 0x0000107c, 0x00000000 },
31517 - { 0x000010bc, 0x00000000 },
31518 - { 0x000010fc, 0x00000000 },
31519 - { 0x0000113c, 0x00000000 },
31520 - { 0x0000117c, 0x00000000 },
31521 - { 0x000011bc, 0x00000000 },
31522 - { 0x000011fc, 0x00000000 },
31523 - { 0x0000123c, 0x00000000 },
31524 - { 0x0000127c, 0x00000000 },
31525 - { 0x000012bc, 0x00000000 },
31526 - { 0x000012fc, 0x00000000 },
31527 - { 0x0000133c, 0x00000000 },
31528 - { 0x0000137c, 0x00000000 },
31529 - { 0x000013bc, 0x00000000 },
31530 - { 0x000013fc, 0x00000000 },
31531 - { 0x0000143c, 0x00000000 },
31532 - { 0x0000147c, 0x00000000 },
31533 - { 0x00004030, 0x00000002 },
31534 - { 0x0000403c, 0x00000002 },
31535 - { 0x00004024, 0x0000001f },
31536 - { 0x00004060, 0x00000000 },
31537 - { 0x00004064, 0x00000000 },
31538 - { 0x00007010, 0x00000031 },
31539 - { 0x00007034, 0x00000002 },
31540 - { 0x00007038, 0x000004c2 },
31541 - { 0x00008004, 0x00000000 },
31542 - { 0x00008008, 0x00000000 },
31543 - { 0x0000800c, 0x00000000 },
31544 - { 0x00008018, 0x00000700 },
31545 - { 0x00008020, 0x00000000 },
31546 - { 0x00008038, 0x00000000 },
31547 - { 0x0000803c, 0x00000000 },
31548 - { 0x00008048, 0x00000000 },
31549 - { 0x00008054, 0x00000000 },
31550 - { 0x00008058, 0x00000000 },
31551 - { 0x0000805c, 0x000fc78f },
31552 - { 0x00008060, 0x0000000f },
31553 - { 0x00008064, 0x00000000 },
31554 - { 0x00008070, 0x00000000 },
31555 - { 0x000080c0, 0x2a80001a },
31556 - { 0x000080c4, 0x05dc01e0 },
31557 - { 0x000080c8, 0x1f402710 },
31558 - { 0x000080cc, 0x01f40000 },
31559 - { 0x000080d0, 0x00001e00 },
31560 - { 0x000080d4, 0x00000000 },
31561 - { 0x000080d8, 0x00400000 },
31562 - { 0x000080e0, 0xffffffff },
31563 - { 0x000080e4, 0x0000ffff },
31564 - { 0x000080e8, 0x003f3f3f },
31565 - { 0x000080ec, 0x00000000 },
31566 - { 0x000080f0, 0x00000000 },
31567 - { 0x000080f4, 0x00000000 },
31568 - { 0x000080f8, 0x00000000 },
31569 - { 0x000080fc, 0x00020000 },
31570 - { 0x00008100, 0x00020000 },
31571 - { 0x00008104, 0x00000001 },
31572 - { 0x00008108, 0x00000052 },
31573 - { 0x0000810c, 0x00000000 },
31574 - { 0x00008110, 0x00000168 },
31575 - { 0x00008118, 0x000100aa },
31576 - { 0x0000811c, 0x00003210 },
31577 - { 0x00008120, 0x08f04810 },
31578 - { 0x00008124, 0x00000000 },
31579 - { 0x00008128, 0x00000000 },
31580 - { 0x0000812c, 0x00000000 },
31581 - { 0x00008130, 0x00000000 },
31582 - { 0x00008134, 0x00000000 },
31583 - { 0x00008138, 0x00000000 },
31584 - { 0x0000813c, 0x00000000 },
31585 - { 0x00008144, 0xffffffff },
31586 - { 0x00008168, 0x00000000 },
31587 - { 0x0000816c, 0x00000000 },
31588 - { 0x00008170, 0x32143320 },
31589 - { 0x00008174, 0xfaa4fa50 },
31590 - { 0x00008178, 0x00000100 },
31591 - { 0x0000817c, 0x00000000 },
31592 - { 0x000081c0, 0x00000000 },
31593 - { 0x000081d0, 0x0000320a },
31594 - { 0x000081ec, 0x00000000 },
31595 - { 0x000081f0, 0x00000000 },
31596 - { 0x000081f4, 0x00000000 },
31597 - { 0x000081f8, 0x00000000 },
31598 - { 0x000081fc, 0x00000000 },
31599 - { 0x00008200, 0x00000000 },
31600 - { 0x00008204, 0x00000000 },
31601 - { 0x00008208, 0x00000000 },
31602 - { 0x0000820c, 0x00000000 },
31603 - { 0x00008210, 0x00000000 },
31604 - { 0x00008214, 0x00000000 },
31605 - { 0x00008218, 0x00000000 },
31606 - { 0x0000821c, 0x00000000 },
31607 - { 0x00008220, 0x00000000 },
31608 - { 0x00008224, 0x00000000 },
31609 - { 0x00008228, 0x00000000 },
31610 - { 0x0000822c, 0x00000000 },
31611 - { 0x00008230, 0x00000000 },
31612 - { 0x00008234, 0x00000000 },
31613 - { 0x00008238, 0x00000000 },
31614 - { 0x0000823c, 0x00000000 },
31615 - { 0x00008240, 0x00100000 },
31616 - { 0x00008244, 0x0010f400 },
31617 - { 0x00008248, 0x00000100 },
31618 - { 0x0000824c, 0x0001e800 },
31619 - { 0x00008250, 0x00000000 },
31620 - { 0x00008254, 0x00000000 },
31621 - { 0x00008258, 0x00000000 },
31622 - { 0x0000825c, 0x400000ff },
31623 - { 0x00008260, 0x00080922 },
31624 - { 0x00008264, 0x88a00010 },
31625 - { 0x00008270, 0x00000000 },
31626 - { 0x00008274, 0x40000000 },
31627 - { 0x00008278, 0x003e4180 },
31628 - { 0x0000827c, 0x00000000 },
31629 - { 0x00008284, 0x0000002c },
31630 - { 0x00008288, 0x0000002c },
31631 - { 0x0000828c, 0x00000000 },
31632 - { 0x00008294, 0x00000000 },
31633 - { 0x00008298, 0x00000000 },
31634 - { 0x0000829c, 0x00000000 },
31635 - { 0x00008300, 0x00000040 },
31636 - { 0x00008314, 0x00000000 },
31637 - { 0x00008328, 0x00000000 },
31638 - { 0x0000832c, 0x00000001 },
31639 - { 0x00008330, 0x00000302 },
31640 - { 0x00008334, 0x00000e00 },
31641 - { 0x00008338, 0x00ff0000 },
31642 - { 0x0000833c, 0x00000000 },
31643 - { 0x00008340, 0x00010380 },
31644 - { 0x00008344, 0x00481043 },
31645 - { 0x00009808, 0x00000000 },
31646 - { 0x0000980c, 0xafe68e30 },
31647 - { 0x00009810, 0xfd14e000 },
31648 - { 0x00009814, 0x9c0a9f6b },
31649 - { 0x0000981c, 0x00000000 },
31650 - { 0x0000982c, 0x0000a000 },
31651 - { 0x00009830, 0x00000000 },
31652 - { 0x0000983c, 0x00200400 },
31653 - { 0x0000984c, 0x0040233c },
31654 - { 0x00009854, 0x00000044 },
31655 - { 0x00009900, 0x00000000 },
31656 - { 0x00009904, 0x00000000 },
31657 - { 0x00009908, 0x00000000 },
31658 - { 0x0000990c, 0x00000000 },
31659 - { 0x00009910, 0x01002310 },
31660 - { 0x0000991c, 0x10000fff },
31661 - { 0x00009920, 0x04900000 },
31662 - { 0x00009928, 0x00000001 },
31663 - { 0x0000992c, 0x00000004 },
31664 - { 0x00009934, 0x1e1f2022 },
31665 - { 0x00009938, 0x0a0b0c0d },
31666 - { 0x0000993c, 0x00000000 },
31667 - { 0x00009940, 0x14750604 },
31668 - { 0x00009948, 0x9280c00a },
31669 - { 0x0000994c, 0x00020028 },
31670 - { 0x00009954, 0x5f3ca3de },
31671 - { 0x00009958, 0x2108ecff },
31672 - { 0x00009968, 0x000003ce },
31673 - { 0x00009970, 0x192bb514 },
31674 - { 0x00009974, 0x00000000 },
31675 - { 0x00009978, 0x00000001 },
31676 - { 0x0000997c, 0x00000000 },
31677 - { 0x00009980, 0x00000000 },
31678 - { 0x00009984, 0x00000000 },
31679 - { 0x00009988, 0x00000000 },
31680 - { 0x0000998c, 0x00000000 },
31681 - { 0x00009990, 0x00000000 },
31682 - { 0x00009994, 0x00000000 },
31683 - { 0x00009998, 0x00000000 },
31684 - { 0x0000999c, 0x00000000 },
31685 - { 0x000099a0, 0x00000000 },
31686 - { 0x000099a4, 0x00000001 },
31687 - { 0x000099a8, 0x201fff00 },
31688 - { 0x000099ac, 0x2def0400 },
31689 - { 0x000099b0, 0x03051000 },
31690 - { 0x000099b4, 0x00000820 },
31691 - { 0x000099dc, 0x00000000 },
31692 - { 0x000099e0, 0x00000000 },
31693 - { 0x000099e4, 0xaaaaaaaa },
31694 - { 0x000099e8, 0x3c466478 },
31695 - { 0x000099ec, 0x0cc80caa },
31696 - { 0x000099f0, 0x00000000 },
31697 - { 0x0000a208, 0x803e68c8 },
31698 - { 0x0000a210, 0x4080a333 },
31699 - { 0x0000a214, 0x00206c10 },
31700 - { 0x0000a218, 0x009c4060 },
31701 - { 0x0000a220, 0x01834061 },
31702 - { 0x0000a224, 0x00000400 },
31703 - { 0x0000a228, 0x000003b5 },
31704 - { 0x0000a22c, 0x00000000 },
31705 - { 0x0000a234, 0x20202020 },
31706 - { 0x0000a238, 0x20202020 },
31707 - { 0x0000a244, 0x00000000 },
31708 - { 0x0000a248, 0xfffffffc },
31709 - { 0x0000a24c, 0x00000000 },
31710 - { 0x0000a254, 0x00000000 },
31711 - { 0x0000a258, 0x0ccb5380 },
31712 - { 0x0000a25c, 0x15151501 },
31713 - { 0x0000a260, 0xdfa90f01 },
31714 - { 0x0000a268, 0x00000000 },
31715 - { 0x0000a26c, 0x0ebae9e6 },
31716 - { 0x0000d270, 0x0d820820 },
31717 - { 0x0000d35c, 0x07ffffef },
31718 - { 0x0000d360, 0x0fffffe7 },
31719 - { 0x0000d364, 0x17ffffe5 },
31720 - { 0x0000d368, 0x1fffffe4 },
31721 - { 0x0000d36c, 0x37ffffe3 },
31722 - { 0x0000d370, 0x3fffffe3 },
31723 - { 0x0000d374, 0x57ffffe3 },
31724 - { 0x0000d378, 0x5fffffe2 },
31725 - { 0x0000d37c, 0x7fffffe2 },
31726 - { 0x0000d380, 0x7f3c7bba },
31727 - { 0x0000d384, 0xf3307ff0 },
31728 - { 0x0000a388, 0x0c000000 },
31729 - { 0x0000a38c, 0x20202020 },
31730 - { 0x0000a390, 0x20202020 },
31731 - { 0x0000a39c, 0x00000001 },
31732 - { 0x0000a3a0, 0x00000000 },
31733 - { 0x0000a3a4, 0x00000000 },
31734 - { 0x0000a3a8, 0x00000000 },
31735 - { 0x0000a3ac, 0x00000000 },
31736 - { 0x0000a3b0, 0x00000000 },
31737 - { 0x0000a3b4, 0x00000000 },
31738 - { 0x0000a3b8, 0x00000000 },
31739 - { 0x0000a3bc, 0x00000000 },
31740 - { 0x0000a3c0, 0x00000000 },
31741 - { 0x0000a3c4, 0x00000000 },
31742 - { 0x0000a3cc, 0x20202020 },
31743 - { 0x0000a3d0, 0x20202020 },
31744 - { 0x0000a3d4, 0x20202020 },
31745 - { 0x0000a3e4, 0x00000000 },
31746 - { 0x0000a3e8, 0x18c43433 },
31747 - { 0x0000a3ec, 0x00f70081 },
31748 - { 0x00007800, 0x00140000 },
31749 - { 0x00007804, 0x0e4548d8 },
31750 - { 0x00007808, 0x54214514 },
31751 - { 0x0000780c, 0x02025830 },
31752 - { 0x00007810, 0x71c0d388 },
31753 - { 0x0000781c, 0x00000000 },
31754 - { 0x00007824, 0x00d86fff },
31755 - { 0x0000782c, 0x6e36d97b },
31756 - { 0x00007834, 0x71400087 },
31757 - { 0x00007844, 0x000c0db6 },
31758 - { 0x00007848, 0x6db6246f },
31759 - { 0x0000784c, 0x6d9b66db },
31760 - { 0x00007850, 0x6d8c6dba },
31761 - { 0x00007854, 0x00040000 },
31762 - { 0x00007858, 0xdb003012 },
31763 - { 0x0000785c, 0x04924914 },
31764 - { 0x00007860, 0x21084210 },
31765 - { 0x00007864, 0xf7d7ffde },
31766 - { 0x00007868, 0xc2034080 },
31767 - { 0x00007870, 0x10142c00 },
31768 -};
31769 -
31770 -static const u_int32_t ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
31771 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
31772 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31773 - { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
31774 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
31775 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
31776 - { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
31777 - { 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
31778 - { 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
31779 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
31780 - { 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
31781 - { 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
31782 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
31783 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
31784 - { 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
31785 - { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
31786 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
31787 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
31788 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31789 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31790 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31791 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31792 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31793 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31794 - { 0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8 },
31795 - { 0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b },
31796 - { 0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e },
31797 - { 0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803 },
31798 - { 0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe },
31799 - { 0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20 },
31800 - { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
31801 - { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
31802 - { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
31803 - { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
31804 - { 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
31805 - { 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
31806 - { 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
31807 - { 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
31808 - { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
31809 -};
31810 -
31811 -static const u_int32_t ar9285Modes_original_tx_gain_9285_1_2[][6] = {
31812 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
31813 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31814 - { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
31815 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
31816 - { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
31817 - { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
31818 - { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
31819 - { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
31820 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
31821 - { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
31822 - { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
31823 - { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
31824 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
31825 - { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
31826 - { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
31827 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
31828 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
31829 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31830 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31831 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31832 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31833 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31834 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31835 - { 0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8 },
31836 - { 0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b },
31837 - { 0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e },
31838 - { 0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801 },
31839 - { 0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe },
31840 - { 0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20 },
31841 - { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
31842 - { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
31843 - { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
31844 - { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
31845 - { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
31846 - { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
31847 - { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
31848 - { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
31849 - { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
31850 -};
31851 -
31852 -static const u_int32_t ar9285Modes_XE2_0_normal_power[][6] = {
31853 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31854 - { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
31855 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
31856 - { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
31857 - { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
31858 - { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
31859 - { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
31860 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
31861 - { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
31862 - { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
31863 - { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
31864 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
31865 - { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
31866 - { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
31867 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
31868 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
31869 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31870 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31871 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31872 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31873 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31874 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31875 - { 0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8 },
31876 - { 0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b, 0x4ad2491b },
31877 - { 0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6dbae },
31878 - { 0x00007838, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441 },
31879 - { 0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe },
31880 - { 0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c },
31881 - { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
31882 - { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
31883 - { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
31884 - { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
31885 - { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
31886 - { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
31887 - { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
31888 - { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
31889 - { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
31890 -};
31891 -
31892 -static const u_int32_t ar9285Modes_XE2_0_high_power[][6] = {
31893 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31894 - { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
31895 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
31896 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
31897 - { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
31898 - { 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
31899 - { 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
31900 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
31901 - { 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
31902 - { 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
31903 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
31904 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
31905 - { 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
31906 - { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
31907 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
31908 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
31909 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31910 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31911 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31912 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31913 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31914 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31915 - { 0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8 },
31916 - { 0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b, 0x4ad2491b },
31917 - { 0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e },
31918 - { 0x00007838, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443 },
31919 - { 0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe },
31920 - { 0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c },
31921 - { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
31922 - { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
31923 - { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
31924 - { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
31925 - { 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
31926 - { 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
31927 - { 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
31928 - { 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
31929 - { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
31930 -};
31931 -
31932 -static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
31933 - {0x00004040, 0x9248fd00 },
31934 - {0x00004040, 0x24924924 },
31935 - {0x00004040, 0xa8000019 },
31936 - {0x00004040, 0x13160820 },
31937 - {0x00004040, 0xe5980560 },
31938 - {0x00004040, 0xc01dcffd },
31939 - {0x00004040, 0x1aaabe41 },
31940 - {0x00004040, 0xbe105554 },
31941 - {0x00004040, 0x00043007 },
31942 - {0x00004044, 0x00000000 },
31943 -};
31944 -
31945 -static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
31946 - {0x00004040, 0x9248fd00 },
31947 - {0x00004040, 0x24924924 },
31948 - {0x00004040, 0xa8000019 },
31949 - {0x00004040, 0x13160820 },
31950 - {0x00004040, 0xe5980560 },
31951 - {0x00004040, 0xc01dcffc },
31952 - {0x00004040, 0x1aaabe41 },
31953 - {0x00004040, 0xbe105554 },
31954 - {0x00004040, 0x00043007 },
31955 - {0x00004044, 0x00000000 },
31956 -};
31957 -
31958 -/* AR9287 Revision 10 */
31959 -static const u_int32_t ar9287Modes_9287_1_0[][6] = {
31960 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
31961 - { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 },
31962 - { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 },
31963 - { 0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180 },
31964 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
31965 - { 0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00, 0x06e006e0 },
31966 - { 0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b, 0x0988004f },
31967 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
31968 - { 0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a, 0x0000320a },
31969 - { 0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440, 0x00006880 },
31970 - { 0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300, 0x00000303 },
31971 - { 0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200, 0x02020200 },
31972 - { 0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e, 0x01000e0e },
31973 - { 0x00009828, 0x00000000, 0x00000000, 0x0a020001, 0x0a020001, 0x0a020001 },
31974 - { 0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e, 0x00000e0e },
31975 - { 0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007, 0x00000007 },
31976 - { 0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e, 0x206a012e },
31977 - { 0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0, 0x037216a0 },
31978 - { 0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
31979 - { 0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
31980 - { 0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e, 0x31395d5e },
31981 - { 0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20, 0x00058d18 },
31982 - { 0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
31983 - { 0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
31984 - { 0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881, 0x06903881 },
31985 - { 0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898, 0x000007d0 },
31986 - { 0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b, 0x00000016 },
31987 - { 0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
31988 - { 0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010, 0xefbc1010 },
31989 - { 0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
31990 - { 0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
31991 - { 0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210, 0x00000210 },
31992 - { 0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce, 0x000003ce },
31993 - { 0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c, 0x0000001c },
31994 - { 0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00, 0x00000c00 },
31995 - { 0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
31996 - { 0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444, 0x00000444 },
31997 - { 0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31998 - { 0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31999 - { 0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a, 0x1883800a },
32000 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
32001 - { 0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000, 0x0004a000 },
32002 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
32003 - { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
32004 -};
32005 -
32006 -static const u_int32_t ar9287Common_9287_1_0[][2] = {
32007 - { 0x0000000c, 0x00000000 },
32008 - { 0x00000030, 0x00020015 },
32009 - { 0x00000034, 0x00000005 },
32010 - { 0x00000040, 0x00000000 },
32011 - { 0x00000044, 0x00000008 },
32012 - { 0x00000048, 0x00000008 },
32013 - { 0x0000004c, 0x00000010 },
32014 - { 0x00000050, 0x00000000 },
32015 - { 0x00000054, 0x0000001f },
32016 - { 0x00000800, 0x00000000 },
32017 - { 0x00000804, 0x00000000 },
32018 - { 0x00000808, 0x00000000 },
32019 - { 0x0000080c, 0x00000000 },
32020 - { 0x00000810, 0x00000000 },
32021 - { 0x00000814, 0x00000000 },
32022 - { 0x00000818, 0x00000000 },
32023 - { 0x0000081c, 0x00000000 },
32024 - { 0x00000820, 0x00000000 },
32025 - { 0x00000824, 0x00000000 },
32026 - { 0x00001040, 0x002ffc0f },
32027 - { 0x00001044, 0x002ffc0f },
32028 - { 0x00001048, 0x002ffc0f },
32029 - { 0x0000104c, 0x002ffc0f },
32030 - { 0x00001050, 0x002ffc0f },
32031 - { 0x00001054, 0x002ffc0f },
32032 - { 0x00001058, 0x002ffc0f },
32033 - { 0x0000105c, 0x002ffc0f },
32034 - { 0x00001060, 0x002ffc0f },
32035 - { 0x00001064, 0x002ffc0f },
32036 - { 0x00001230, 0x00000000 },
32037 - { 0x00001270, 0x00000000 },
32038 - { 0x00001038, 0x00000000 },
32039 - { 0x00001078, 0x00000000 },
32040 - { 0x000010b8, 0x00000000 },
32041 - { 0x000010f8, 0x00000000 },
32042 - { 0x00001138, 0x00000000 },
32043 - { 0x00001178, 0x00000000 },
32044 - { 0x000011b8, 0x00000000 },
32045 - { 0x000011f8, 0x00000000 },
32046 - { 0x00001238, 0x00000000 },
32047 - { 0x00001278, 0x00000000 },
32048 - { 0x000012b8, 0x00000000 },
32049 - { 0x000012f8, 0x00000000 },
32050 - { 0x00001338, 0x00000000 },
32051 - { 0x00001378, 0x00000000 },
32052 - { 0x000013b8, 0x00000000 },
32053 - { 0x000013f8, 0x00000000 },
32054 - { 0x00001438, 0x00000000 },
32055 - { 0x00001478, 0x00000000 },
32056 - { 0x000014b8, 0x00000000 },
32057 - { 0x000014f8, 0x00000000 },
32058 - { 0x00001538, 0x00000000 },
32059 - { 0x00001578, 0x00000000 },
32060 - { 0x000015b8, 0x00000000 },
32061 - { 0x000015f8, 0x00000000 },
32062 - { 0x00001638, 0x00000000 },
32063 - { 0x00001678, 0x00000000 },
32064 - { 0x000016b8, 0x00000000 },
32065 - { 0x000016f8, 0x00000000 },
32066 - { 0x00001738, 0x00000000 },
32067 - { 0x00001778, 0x00000000 },
32068 - { 0x000017b8, 0x00000000 },
32069 - { 0x000017f8, 0x00000000 },
32070 - { 0x0000103c, 0x00000000 },
32071 - { 0x0000107c, 0x00000000 },
32072 - { 0x000010bc, 0x00000000 },
32073 - { 0x000010fc, 0x00000000 },
32074 - { 0x0000113c, 0x00000000 },
32075 - { 0x0000117c, 0x00000000 },
32076 - { 0x000011bc, 0x00000000 },
32077 - { 0x000011fc, 0x00000000 },
32078 - { 0x0000123c, 0x00000000 },
32079 - { 0x0000127c, 0x00000000 },
32080 - { 0x000012bc, 0x00000000 },
32081 - { 0x000012fc, 0x00000000 },
32082 - { 0x0000133c, 0x00000000 },
32083 - { 0x0000137c, 0x00000000 },
32084 - { 0x000013bc, 0x00000000 },
32085 - { 0x000013fc, 0x00000000 },
32086 - { 0x0000143c, 0x00000000 },
32087 - { 0x0000147c, 0x00000000 },
32088 - { 0x00004030, 0x00000002 },
32089 - { 0x0000403c, 0x00000002 },
32090 - { 0x00004024, 0x0000001f },
32091 - { 0x00004060, 0x00000000 },
32092 - { 0x00004064, 0x00000000 },
32093 - { 0x00007010, 0x00000033 },
32094 - { 0x00007020, 0x00000000 },
32095 - { 0x00007034, 0x00000002 },
32096 - { 0x00007038, 0x000004c2 },
32097 - { 0x00008004, 0x00000000 },
32098 - { 0x00008008, 0x00000000 },
32099 - { 0x0000800c, 0x00000000 },
32100 - { 0x00008018, 0x00000700 },
32101 - { 0x00008020, 0x00000000 },
32102 - { 0x00008038, 0x00000000 },
32103 - { 0x0000803c, 0x00000000 },
32104 - { 0x00008048, 0x40000000 },
32105 - { 0x00008054, 0x00000000 },
32106 - { 0x00008058, 0x00000000 },
32107 - { 0x0000805c, 0x000fc78f },
32108 - { 0x00008060, 0x0000000f },
32109 - { 0x00008064, 0x00000000 },
32110 - { 0x00008070, 0x00000000 },
32111 - { 0x000080c0, 0x2a80001a },
32112 - { 0x000080c4, 0x05dc01e0 },
32113 - { 0x000080c8, 0x1f402710 },
32114 - { 0x000080cc, 0x01f40000 },
32115 - { 0x000080d0, 0x00001e00 },
32116 - { 0x000080d4, 0x00000000 },
32117 - { 0x000080d8, 0x00400000 },
32118 - { 0x000080e0, 0xffffffff },
32119 - { 0x000080e4, 0x0000ffff },
32120 - { 0x000080e8, 0x003f3f3f },
32121 - { 0x000080ec, 0x00000000 },
32122 - { 0x000080f0, 0x00000000 },
32123 - { 0x000080f4, 0x00000000 },
32124 - { 0x000080f8, 0x00000000 },
32125 - { 0x000080fc, 0x00020000 },
32126 - { 0x00008100, 0x00020000 },
32127 - { 0x00008104, 0x00000001 },
32128 - { 0x00008108, 0x00000052 },
32129 - { 0x0000810c, 0x00000000 },
32130 - { 0x00008110, 0x00000168 },
32131 - { 0x00008118, 0x000100aa },
32132 - { 0x0000811c, 0x00003210 },
32133 - { 0x00008124, 0x00000000 },
32134 - { 0x00008128, 0x00000000 },
32135 - { 0x0000812c, 0x00000000 },
32136 - { 0x00008130, 0x00000000 },
32137 - { 0x00008134, 0x00000000 },
32138 - { 0x00008138, 0x00000000 },
32139 - { 0x0000813c, 0x00000000 },
32140 - { 0x00008144, 0xffffffff },
32141 - { 0x00008168, 0x00000000 },
32142 - { 0x0000816c, 0x00000000 },
32143 - { 0x00008170, 0x18487320 },
32144 - { 0x00008174, 0xfaa4fa50 },
32145 - { 0x00008178, 0x00000100 },
32146 - { 0x0000817c, 0x00000000 },
32147 - { 0x000081c0, 0x00000000 },
32148 - { 0x000081c4, 0x00000000 },
32149 - { 0x000081d4, 0x00000000 },
32150 - { 0x000081ec, 0x00000000 },
32151 - { 0x000081f0, 0x00000000 },
32152 - { 0x000081f4, 0x00000000 },
32153 - { 0x000081f8, 0x00000000 },
32154 - { 0x000081fc, 0x00000000 },
32155 - { 0x00008200, 0x00000000 },
32156 - { 0x00008204, 0x00000000 },
32157 - { 0x00008208, 0x00000000 },
32158 - { 0x0000820c, 0x00000000 },
32159 - { 0x00008210, 0x00000000 },
32160 - { 0x00008214, 0x00000000 },
32161 - { 0x00008218, 0x00000000 },
32162 - { 0x0000821c, 0x00000000 },
32163 - { 0x00008220, 0x00000000 },
32164 - { 0x00008224, 0x00000000 },
32165 - { 0x00008228, 0x00000000 },
32166 - { 0x0000822c, 0x00000000 },
32167 - { 0x00008230, 0x00000000 },
32168 - { 0x00008234, 0x00000000 },
32169 - { 0x00008238, 0x00000000 },
32170 - { 0x0000823c, 0x00000000 },
32171 - { 0x00008240, 0x00100000 },
32172 - { 0x00008244, 0x0010f400 },
32173 - { 0x00008248, 0x00000100 },
32174 - { 0x0000824c, 0x0001e800 },
32175 - { 0x00008250, 0x00000000 },
32176 - { 0x00008254, 0x00000000 },
32177 - { 0x00008258, 0x00000000 },
32178 - { 0x0000825c, 0x400000ff },
32179 - { 0x00008260, 0x00080922 },
32180 - { 0x00008264, 0xa8a00010 },
32181 - { 0x00008270, 0x00000000 },
32182 - { 0x00008274, 0x40000000 },
32183 - { 0x00008278, 0x003e4180 },
32184 - { 0x0000827c, 0x00000000 },
32185 - { 0x00008284, 0x0000002c },
32186 - { 0x00008288, 0x0000002c },
32187 - { 0x0000828c, 0x000000ff },
32188 - { 0x00008294, 0x00000000 },
32189 - { 0x00008298, 0x00000000 },
32190 - { 0x0000829c, 0x00000000 },
32191 - { 0x00008300, 0x00000040 },
32192 - { 0x00008314, 0x00000000 },
32193 - { 0x00008328, 0x00000000 },
32194 - { 0x0000832c, 0x00000007 },
32195 - { 0x00008330, 0x00000302 },
32196 - { 0x00008334, 0x00000e00 },
32197 - { 0x00008338, 0x00ff0000 },
32198 - { 0x0000833c, 0x00000000 },
32199 - { 0x00008340, 0x000107ff },
32200 - { 0x00008344, 0x01c81043 },
32201 - { 0x00008360, 0xffffffff },
32202 - { 0x00008364, 0xffffffff },
32203 - { 0x00008368, 0x00000000 },
32204 - { 0x00008370, 0x00000000 },
32205 - { 0x00008374, 0x000000ff },
32206 - { 0x00008378, 0x00000000 },
32207 - { 0x0000837c, 0x00000000 },
32208 - { 0x00008380, 0xffffffff },
32209 - { 0x00008384, 0xffffffff },
32210 - { 0x00008390, 0x0fffffff },
32211 - { 0x00008394, 0x0fffffff },
32212 - { 0x00008398, 0x00000000 },
32213 - { 0x0000839c, 0x00000000 },
32214 - { 0x000083a0, 0x00000000 },
32215 - { 0x00009808, 0x00000000 },
32216 - { 0x0000980c, 0xafe68e30 },
32217 - { 0x00009810, 0xfd14e000 },
32218 - { 0x00009814, 0x9c0a9f6b },
32219 - { 0x0000981c, 0x00000000 },
32220 - { 0x0000982c, 0x0000a000 },
32221 - { 0x00009830, 0x00000000 },
32222 - { 0x0000983c, 0x00200400 },
32223 - { 0x0000984c, 0x0040233c },
32224 - { 0x0000a84c, 0x0040233c },
32225 - { 0x00009854, 0x00000044 },
32226 - { 0x00009900, 0x00000000 },
32227 - { 0x00009904, 0x00000000 },
32228 - { 0x00009908, 0x00000000 },
32229 - { 0x0000990c, 0x00000000 },
32230 - { 0x00009910, 0x10002310 },
32231 - { 0x0000991c, 0x10000fff },
32232 - { 0x00009920, 0x04900000 },
32233 - { 0x0000a920, 0x04900000 },
32234 - { 0x00009928, 0x00000001 },
32235 - { 0x0000992c, 0x00000004 },
32236 - { 0x00009930, 0x00000000 },
32237 - { 0x0000a930, 0x00000000 },
32238 - { 0x00009934, 0x1e1f2022 },
32239 - { 0x00009938, 0x0a0b0c0d },
32240 - { 0x0000993c, 0x00000000 },
32241 - { 0x00009948, 0x9280c00a },
32242 - { 0x0000994c, 0x00020028 },
32243 - { 0x00009954, 0x5f3ca3de },
32244 - { 0x00009958, 0x0108ecff },
32245 - { 0x00009940, 0x14750604 },
32246 - { 0x0000c95c, 0x004b6a8e },
32247 - { 0x00009970, 0x990bb515 },
32248 - { 0x00009974, 0x00000000 },
32249 - { 0x00009978, 0x00000001 },
32250 - { 0x0000997c, 0x00000000 },
32251 - { 0x000099a0, 0x00000000 },
32252 - { 0x000099a4, 0x00000001 },
32253 - { 0x000099a8, 0x201fff00 },
32254 - { 0x000099ac, 0x0c6f0000 },
32255 - { 0x000099b0, 0x03051000 },
32256 - { 0x000099b4, 0x00000820 },
32257 - { 0x000099c4, 0x06336f77 },
32258 - { 0x000099c8, 0x6af65329 },
32259 - { 0x000099cc, 0x08f186c8 },
32260 - { 0x000099d0, 0x00046384 },
32261 - { 0x000099dc, 0x00000000 },
32262 - { 0x000099e0, 0x00000000 },
32263 - { 0x000099e4, 0xaaaaaaaa },
32264 - { 0x000099e8, 0x3c466478 },
32265 - { 0x000099ec, 0x0cc80caa },
32266 - { 0x000099f0, 0x00000000 },
32267 - { 0x000099fc, 0x00001042 },
32268 - { 0x0000a1f4, 0x00fffeff },
32269 - { 0x0000a1f8, 0x00f5f9ff },
32270 - { 0x0000a1fc, 0xb79f6427 },
32271 - { 0x0000a208, 0x803e4788 },
32272 - { 0x0000a210, 0x4080a333 },
32273 - { 0x0000a214, 0x40206c10 },
32274 - { 0x0000a218, 0x009c4060 },
32275 - { 0x0000a220, 0x01834061 },
32276 - { 0x0000a224, 0x00000400 },
32277 - { 0x0000a228, 0x000003b5 },
32278 - { 0x0000a22c, 0x233f7180 },
32279 - { 0x0000a234, 0x20202020 },
32280 - { 0x0000a238, 0x20202020 },
32281 - { 0x0000a23c, 0x13c889af },
32282 - { 0x0000a240, 0x38490a20 },
32283 - { 0x0000a244, 0x00000000 },
32284 - { 0x0000a248, 0xfffffffc },
32285 - { 0x0000a24c, 0x00000000 },
32286 - { 0x0000a254, 0x00000000 },
32287 - { 0x0000a258, 0x0cdbd380 },
32288 - { 0x0000a25c, 0x0f0f0f01 },
32289 - { 0x0000a260, 0xdfa91f01 },
32290 - { 0x0000a264, 0x00418a11 },
32291 - { 0x0000b264, 0x00418a11 },
32292 - { 0x0000a268, 0x00000000 },
32293 - { 0x0000a26c, 0x0e79e5c6 },
32294 - { 0x0000b26c, 0x0e79e5c6 },
32295 - { 0x0000d270, 0x00820820 },
32296 - { 0x0000a278, 0x1ce739ce },
32297 - { 0x0000a27c, 0x050701ce },
32298 - { 0x0000d35c, 0x07ffffef },
32299 - { 0x0000d360, 0x0fffffe7 },
32300 - { 0x0000d364, 0x17ffffe5 },
32301 - { 0x0000d368, 0x1fffffe4 },
32302 - { 0x0000d36c, 0x37ffffe3 },
32303 - { 0x0000d370, 0x3fffffe3 },
32304 - { 0x0000d374, 0x57ffffe3 },
32305 - { 0x0000d378, 0x5fffffe2 },
32306 - { 0x0000d37c, 0x7fffffe2 },
32307 - { 0x0000d380, 0x7f3c7bba },
32308 - { 0x0000d384, 0xf3307ff0 },
32309 - { 0x0000a388, 0x0c000000 },
32310 - { 0x0000a38c, 0x20202020 },
32311 - { 0x0000a390, 0x20202020 },
32312 - { 0x0000a394, 0x1ce739ce },
32313 - { 0x0000a398, 0x000001ce },
32314 - { 0x0000b398, 0x000001ce },
32315 - { 0x0000a39c, 0x00000001 },
32316 - { 0x0000a3c8, 0x00000246 },
32317 - { 0x0000a3cc, 0x20202020 },
32318 - { 0x0000a3d0, 0x20202020 },
32319 - { 0x0000a3d4, 0x20202020 },
32320 - { 0x0000a3dc, 0x1ce739ce },
32321 - { 0x0000a3e0, 0x000001ce },
32322 - { 0x0000a3e4, 0x00000000 },
32323 - { 0x0000a3e8, 0x18c43433 },
32324 - { 0x0000a3ec, 0x00f70081 },
32325 - { 0x0000a3f0, 0x01036a1e },
32326 - { 0x0000a3f4, 0x00000000 },
32327 - { 0x0000b3f4, 0x00000000 },
32328 - { 0x0000a7d8, 0x00000001 },
32329 - { 0x00007800, 0x00000800 },
32330 - { 0x00007804, 0x6c35ffb0 },
32331 - { 0x00007808, 0x6db6c000 },
32332 - { 0x0000780c, 0x6db6cb30 },
32333 - { 0x00007810, 0x6db6cb6c },
32334 - { 0x00007814, 0x0501e200 },
32335 - { 0x00007818, 0x0094128d },
32336 - { 0x0000781c, 0x976ee392 },
32337 - { 0x00007820, 0xf75ff6fc },
32338 - { 0x00007824, 0x00040000 },
32339 - { 0x00007828, 0xdb003012 },
32340 - { 0x0000782c, 0x04924914 },
32341 - { 0x00007830, 0x21084210 },
32342 - { 0x00007834, 0x00140000 },
32343 - { 0x00007838, 0x0e4548d8 },
32344 - { 0x0000783c, 0x54214514 },
32345 - { 0x00007840, 0x02025820 },
32346 - { 0x00007844, 0x71c0d388 },
32347 - { 0x00007848, 0x934934a8 },
32348 - { 0x00007850, 0x00000000 },
32349 - { 0x00007854, 0x00000800 },
32350 - { 0x00007858, 0x6c35ffb0 },
32351 - { 0x0000785c, 0x6db6c000 },
32352 - { 0x00007860, 0x6db6cb2c },
32353 - { 0x00007864, 0x6db6cb6c },
32354 - { 0x00007868, 0x0501e200 },
32355 - { 0x0000786c, 0x0094128d },
32356 - { 0x00007870, 0x976ee392 },
32357 - { 0x00007874, 0xf75ff6fc },
32358 - { 0x00007878, 0x00040000 },
32359 - { 0x0000787c, 0xdb003012 },
32360 - { 0x00007880, 0x04924914 },
32361 - { 0x00007884, 0x21084210 },
32362 - { 0x00007888, 0x001b6db0 },
32363 - { 0x0000788c, 0x00376b63 },
32364 - { 0x00007890, 0x06db6db6 },
32365 - { 0x00007894, 0x006d8000 },
32366 - { 0x00007898, 0x48100000 },
32367 - { 0x0000789c, 0x00000000 },
32368 - { 0x000078a0, 0x08000000 },
32369 - { 0x000078a4, 0x0007ffd8 },
32370 - { 0x000078a8, 0x0007ffd8 },
32371 - { 0x000078ac, 0x001c0020 },
32372 - { 0x000078b0, 0x000611eb },
32373 - { 0x000078b4, 0x40008080 },
32374 - { 0x000078b8, 0x2a850160 },
32375 -};
32376 -
32377 -static const u_int32_t ar9287Modes_tx_gain_9287_1_0[][6] = {
32378 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
32379 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
32380 - { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 },
32381 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004 },
32382 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a, 0x0000c00a },
32383 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c, 0x0001000c },
32384 - { 0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b, 0x0001420b },
32385 - { 0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a, 0x0001824a },
32386 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a, 0x0001c44a },
32387 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a, 0x0002064a },
32388 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a, 0x0002484a },
32389 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a, 0x00028a4a },
32390 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a },
32391 - { 0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a, 0x00030e4a },
32392 - { 0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a, 0x00034e8a },
32393 - { 0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c, 0x00038e8c },
32394 - { 0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc, 0x0003cecc },
32395 - { 0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4, 0x00040ed4 },
32396 - { 0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc, 0x00044edc },
32397 - { 0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede, 0x00048ede },
32398 - { 0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e },
32399 - { 0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e, 0x00050f5e },
32400 - { 0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e, 0x00054f9e },
32401 - { 0x0000a780, 0x00000000, 0x00000000, 0x00000060, 0x00000060, 0x00000060 },
32402 - { 0x0000a784, 0x00000000, 0x00000000, 0x00004062, 0x00004062, 0x00004062 },
32403 - { 0x0000a788, 0x00000000, 0x00000000, 0x00008064, 0x00008064, 0x00008064 },
32404 - { 0x0000a78c, 0x00000000, 0x00000000, 0x0000c0a4, 0x0000c0a4, 0x0000c0a4 },
32405 - { 0x0000a790, 0x00000000, 0x00000000, 0x000100b0, 0x000100b0, 0x000100b0 },
32406 - { 0x0000a794, 0x00000000, 0x00000000, 0x000140b2, 0x000140b2, 0x000140b2 },
32407 - { 0x0000a798, 0x00000000, 0x00000000, 0x000180b4, 0x000180b4, 0x000180b4 },
32408 - { 0x0000a79c, 0x00000000, 0x00000000, 0x0001c0f4, 0x0001c0f4, 0x0001c0f4 },
32409 - { 0x0000a7a0, 0x00000000, 0x00000000, 0x00020134, 0x00020134, 0x00020134 },
32410 - { 0x0000a7a4, 0x00000000, 0x00000000, 0x000240fe, 0x000240fe, 0x000240fe },
32411 - { 0x0000a7a8, 0x00000000, 0x00000000, 0x0002813e, 0x0002813e, 0x0002813e },
32412 - { 0x0000a7ac, 0x00000000, 0x00000000, 0x0002c17e, 0x0002c17e, 0x0002c17e },
32413 - { 0x0000a7b0, 0x00000000, 0x00000000, 0x000301be, 0x000301be, 0x000301be },
32414 - { 0x0000a7b4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32415 - { 0x0000a7b8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32416 - { 0x0000a7bc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32417 - { 0x0000a7c0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32418 - { 0x0000a7c4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32419 - { 0x0000a7c8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32420 - { 0x0000a7cc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32421 - { 0x0000a7d0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32422 - { 0x0000a7d4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32423 - { 0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000 },
32424 -};
32425 -
32426 -
32427 -static const u_int32_t ar9287Modes_rx_gain_9287_1_0[][6] = {
32428 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
32429 - { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
32430 - { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
32431 - { 0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
32432 - { 0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
32433 - { 0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
32434 - { 0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
32435 - { 0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
32436 - { 0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
32437 - { 0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
32438 - { 0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
32439 - { 0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
32440 - { 0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
32441 - { 0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
32442 - { 0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
32443 - { 0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
32444 - { 0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
32445 - { 0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
32446 - { 0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
32447 - { 0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
32448 - { 0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
32449 - { 0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
32450 - { 0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
32451 - { 0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
32452 - { 0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
32453 - { 0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
32454 - { 0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
32455 - { 0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
32456 - { 0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
32457 - { 0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
32458 - { 0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
32459 - { 0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
32460 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
32461 - { 0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
32462 - { 0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
32463 - { 0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
32464 - { 0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
32465 - { 0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
32466 - { 0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
32467 - { 0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
32468 - { 0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
32469 - { 0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
32470 - { 0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
32471 - { 0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
32472 - { 0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
32473 - { 0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
32474 - { 0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
32475 - { 0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
32476 - { 0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
32477 - { 0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
32478 - { 0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
32479 - { 0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
32480 - { 0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
32481 - { 0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
32482 - { 0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
32483 - { 0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
32484 - { 0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
32485 - { 0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
32486 - { 0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
32487 - { 0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
32488 - { 0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
32489 - { 0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
32490 - { 0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
32491 - { 0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
32492 - { 0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
32493 - { 0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
32494 - { 0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
32495 - { 0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
32496 - { 0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
32497 - { 0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
32498 - { 0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
32499 - { 0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
32500 - { 0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
32501 - { 0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
32502 - { 0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
32503 - { 0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
32504 - { 0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
32505 - { 0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
32506 - { 0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
32507 - { 0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
32508 - { 0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
32509 - { 0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
32510 - { 0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
32511 - { 0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
32512 - { 0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
32513 - { 0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
32514 - { 0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
32515 - { 0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
32516 - { 0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
32517 - { 0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
32518 - { 0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
32519 - { 0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
32520 - { 0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
32521 - { 0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
32522 - { 0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
32523 - { 0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
32524 - { 0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
32525 - { 0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
32526 - { 0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
32527 - { 0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
32528 - { 0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
32529 - { 0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
32530 - { 0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
32531 - { 0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
32532 - { 0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32533 - { 0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32534 - { 0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32535 - { 0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32536 - { 0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32537 - { 0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32538 - { 0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32539 - { 0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32540 - { 0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32541 - { 0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32542 - { 0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32543 - { 0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32544 - { 0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32545 - { 0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32546 - { 0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32547 - { 0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32548 - { 0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32549 - { 0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32550 - { 0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32551 - { 0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32552 - { 0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32553 - { 0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32554 - { 0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32555 - { 0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32556 - { 0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32557 - { 0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
32558 - { 0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
32559 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
32560 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
32561 - { 0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
32562 - { 0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
32563 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
32564 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
32565 - { 0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
32566 - { 0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
32567 - { 0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
32568 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
32569 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
32570 - { 0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
32571 - { 0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
32572 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
32573 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
32574 - { 0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
32575 - { 0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
32576 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
32577 - { 0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
32578 - { 0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
32579 - { 0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
32580 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
32581 - { 0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
32582 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
32583 - { 0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
32584 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
32585 - { 0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
32586 - { 0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
32587 - { 0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
32588 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
32589 - { 0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
32590 - { 0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
32591 - { 0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
32592 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
32593 - { 0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
32594 - { 0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
32595 - { 0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
32596 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
32597 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
32598 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
32599 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
32600 - { 0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
32601 - { 0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
32602 - { 0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
32603 - { 0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
32604 - { 0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
32605 - { 0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
32606 - { 0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
32607 - { 0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
32608 - { 0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
32609 - { 0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
32610 - { 0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
32611 - { 0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
32612 - { 0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
32613 - { 0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
32614 - { 0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
32615 - { 0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
32616 - { 0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
32617 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
32618 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
32619 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
32620 - { 0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
32621 - { 0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
32622 - { 0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
32623 - { 0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
32624 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
32625 - { 0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
32626 - { 0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
32627 - { 0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
32628 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
32629 - { 0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
32630 - { 0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
32631 - { 0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
32632 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
32633 - { 0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
32634 - { 0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
32635 - { 0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
32636 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
32637 - { 0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
32638 - { 0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
32639 - { 0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
32640 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
32641 - { 0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
32642 - { 0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
32643 - { 0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
32644 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
32645 - { 0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
32646 - { 0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
32647 - { 0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
32648 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
32649 - { 0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
32650 - { 0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
32651 - { 0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
32652 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
32653 - { 0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
32654 - { 0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
32655 - { 0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
32656 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
32657 - { 0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
32658 - { 0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
32659 - { 0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
32660 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32661 - { 0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32662 - { 0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32663 - { 0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32664 - { 0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32665 - { 0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32666 - { 0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32667 - { 0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32668 - { 0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32669 - { 0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32670 - { 0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32671 - { 0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32672 - { 0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32673 - { 0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32674 - { 0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32675 - { 0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32676 - { 0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32677 - { 0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32678 - { 0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32679 - { 0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32680 - { 0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32681 - { 0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32682 - { 0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32683 - { 0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32684 - { 0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32685 - { 0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
32686 - { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
32687 -};
32688 -
32689 -static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_0[][2] = {
32690 - {0x00004040, 0x9248fd00 },
32691 - {0x00004040, 0x24924924 },
32692 - {0x00004040, 0xa8000019 },
32693 - {0x00004040, 0x13160820 },
32694 - {0x00004040, 0xe5980560 },
32695 - {0x00004040, 0xc01dcffd },
32696 - {0x00004040, 0x1aaabe41 },
32697 - {0x00004040, 0xbe105554 },
32698 - {0x00004040, 0x00043007 },
32699 - {0x00004044, 0x00000000 },
32700 -};
32701 -
32702 -static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_0[][2] = {
32703 - {0x00004040, 0x9248fd00 },
32704 - {0x00004040, 0x24924924 },
32705 - {0x00004040, 0xa8000019 },
32706 - {0x00004040, 0x13160820 },
32707 - {0x00004040, 0xe5980560 },
32708 - {0x00004040, 0xc01dcffc },
32709 - {0x00004040, 0x1aaabe41 },
32710 - {0x00004040, 0xbe105554 },
32711 - {0x00004040, 0x00043007 },
32712 - {0x00004044, 0x00000000 },
32713 -};
32714 -
32715 -/* AR9287 Revision 11 */
32716 -
32717 -static const u_int32_t ar9287Modes_9287_1_1[][6] = {
32718 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
32719 - { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 },
32720 - { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 },
32721 - { 0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180 },
32722 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
32723 - { 0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00, 0x06e006e0 },
32724 - { 0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b, 0x0988004f },
32725 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
32726 - { 0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a, 0x0000320a },
32727 - { 0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440, 0x00006880 },
32728 - { 0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300, 0x00000303 },
32729 - { 0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200, 0x02020200 },
32730 - { 0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e, 0x01000e0e },
32731 - { 0x00009828, 0x00000000, 0x00000000, 0x3a020001, 0x3a020001, 0x3a020001 },
32732 - { 0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e, 0x00000e0e },
32733 - { 0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007, 0x00000007 },
32734 - { 0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e, 0x206a012e },
32735 - { 0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0, 0x037216a0 },
32736 - { 0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
32737 - { 0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
32738 - { 0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e, 0x31395d5e },
32739 - { 0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20, 0x00058d18 },
32740 - { 0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
32741 - { 0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
32742 - { 0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881, 0x06903881 },
32743 - { 0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898, 0x000007d0 },
32744 - { 0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b, 0x00000016 },
32745 - { 0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
32746 - { 0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010, 0xefbc1010 },
32747 - { 0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
32748 - { 0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
32749 - { 0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210, 0x00000210 },
32750 - { 0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce, 0x000003ce },
32751 - { 0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c, 0x0000001c },
32752 - { 0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00, 0x00000c00 },
32753 - { 0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
32754 - { 0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444, 0x00000444 },
32755 - { 0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
32756 - { 0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
32757 - { 0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a, 0x1883800a },
32758 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
32759 - { 0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000, 0x0004a000 },
32760 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
32761 - { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
32762 -};
32763 -
32764 -static const u_int32_t ar9287Common_9287_1_1[][2] = {
32765 - { 0x0000000c, 0x00000000 },
32766 - { 0x00000030, 0x00020015 },
32767 - { 0x00000034, 0x00000005 },
32768 - { 0x00000040, 0x00000000 },
32769 - { 0x00000044, 0x00000008 },
32770 - { 0x00000048, 0x00000008 },
32771 - { 0x0000004c, 0x00000010 },
32772 - { 0x00000050, 0x00000000 },
32773 - { 0x00000054, 0x0000001f },
32774 - { 0x00000800, 0x00000000 },
32775 - { 0x00000804, 0x00000000 },
32776 - { 0x00000808, 0x00000000 },
32777 - { 0x0000080c, 0x00000000 },
32778 - { 0x00000810, 0x00000000 },
32779 - { 0x00000814, 0x00000000 },
32780 - { 0x00000818, 0x00000000 },
32781 - { 0x0000081c, 0x00000000 },
32782 - { 0x00000820, 0x00000000 },
32783 - { 0x00000824, 0x00000000 },
32784 - { 0x00001040, 0x002ffc0f },
32785 - { 0x00001044, 0x002ffc0f },
32786 - { 0x00001048, 0x002ffc0f },
32787 - { 0x0000104c, 0x002ffc0f },
32788 - { 0x00001050, 0x002ffc0f },
32789 - { 0x00001054, 0x002ffc0f },
32790 - { 0x00001058, 0x002ffc0f },
32791 - { 0x0000105c, 0x002ffc0f },
32792 - { 0x00001060, 0x002ffc0f },
32793 - { 0x00001064, 0x002ffc0f },
32794 - { 0x00001230, 0x00000000 },
32795 - { 0x00001270, 0x00000000 },
32796 - { 0x00001038, 0x00000000 },
32797 - { 0x00001078, 0x00000000 },
32798 - { 0x000010b8, 0x00000000 },
32799 - { 0x000010f8, 0x00000000 },
32800 - { 0x00001138, 0x00000000 },
32801 - { 0x00001178, 0x00000000 },
32802 - { 0x000011b8, 0x00000000 },
32803 - { 0x000011f8, 0x00000000 },
32804 - { 0x00001238, 0x00000000 },
32805 - { 0x00001278, 0x00000000 },
32806 - { 0x000012b8, 0x00000000 },
32807 - { 0x000012f8, 0x00000000 },
32808 - { 0x00001338, 0x00000000 },
32809 - { 0x00001378, 0x00000000 },
32810 - { 0x000013b8, 0x00000000 },
32811 - { 0x000013f8, 0x00000000 },
32812 - { 0x00001438, 0x00000000 },
32813 - { 0x00001478, 0x00000000 },
32814 - { 0x000014b8, 0x00000000 },
32815 - { 0x000014f8, 0x00000000 },
32816 - { 0x00001538, 0x00000000 },
32817 - { 0x00001578, 0x00000000 },
32818 - { 0x000015b8, 0x00000000 },
32819 - { 0x000015f8, 0x00000000 },
32820 - { 0x00001638, 0x00000000 },
32821 - { 0x00001678, 0x00000000 },
32822 - { 0x000016b8, 0x00000000 },
32823 - { 0x000016f8, 0x00000000 },
32824 - { 0x00001738, 0x00000000 },
32825 - { 0x00001778, 0x00000000 },
32826 - { 0x000017b8, 0x00000000 },
32827 - { 0x000017f8, 0x00000000 },
32828 - { 0x0000103c, 0x00000000 },
32829 - { 0x0000107c, 0x00000000 },
32830 - { 0x000010bc, 0x00000000 },
32831 - { 0x000010fc, 0x00000000 },
32832 - { 0x0000113c, 0x00000000 },
32833 - { 0x0000117c, 0x00000000 },
32834 - { 0x000011bc, 0x00000000 },
32835 - { 0x000011fc, 0x00000000 },
32836 - { 0x0000123c, 0x00000000 },
32837 - { 0x0000127c, 0x00000000 },
32838 - { 0x000012bc, 0x00000000 },
32839 - { 0x000012fc, 0x00000000 },
32840 - { 0x0000133c, 0x00000000 },
32841 - { 0x0000137c, 0x00000000 },
32842 - { 0x000013bc, 0x00000000 },
32843 - { 0x000013fc, 0x00000000 },
32844 - { 0x0000143c, 0x00000000 },
32845 - { 0x0000147c, 0x00000000 },
32846 - { 0x00004030, 0x00000002 },
32847 - { 0x0000403c, 0x00000002 },
32848 - { 0x00004024, 0x0000001f },
32849 - { 0x00004060, 0x00000000 },
32850 - { 0x00004064, 0x00000000 },
32851 - { 0x00007010, 0x00000033 },
32852 - { 0x00007020, 0x00000000 },
32853 - { 0x00007034, 0x00000002 },
32854 - { 0x00007038, 0x000004c2 },
32855 - { 0x00008004, 0x00000000 },
32856 - { 0x00008008, 0x00000000 },
32857 - { 0x0000800c, 0x00000000 },
32858 - { 0x00008018, 0x00000700 },
32859 - { 0x00008020, 0x00000000 },
32860 - { 0x00008038, 0x00000000 },
32861 - { 0x0000803c, 0x00000000 },
32862 - { 0x00008048, 0x40000000 },
32863 - { 0x00008054, 0x00000000 },
32864 - { 0x00008058, 0x00000000 },
32865 - { 0x0000805c, 0x000fc78f },
32866 - { 0x00008060, 0x0000000f },
32867 - { 0x00008064, 0x00000000 },
32868 - { 0x00008070, 0x00000000 },
32869 - { 0x000080c0, 0x2a80001a },
32870 - { 0x000080c4, 0x05dc01e0 },
32871 - { 0x000080c8, 0x1f402710 },
32872 - { 0x000080cc, 0x01f40000 },
32873 - { 0x000080d0, 0x00001e00 },
32874 - { 0x000080d4, 0x00000000 },
32875 - { 0x000080d8, 0x00400000 },
32876 - { 0x000080e0, 0xffffffff },
32877 - { 0x000080e4, 0x0000ffff },
32878 - { 0x000080e8, 0x003f3f3f },
32879 - { 0x000080ec, 0x00000000 },
32880 - { 0x000080f0, 0x00000000 },
32881 - { 0x000080f4, 0x00000000 },
32882 - { 0x000080f8, 0x00000000 },
32883 - { 0x000080fc, 0x00020000 },
32884 - { 0x00008100, 0x00020000 },
32885 - { 0x00008104, 0x00000001 },
32886 - { 0x00008108, 0x00000052 },
32887 - { 0x0000810c, 0x00000000 },
32888 - { 0x00008110, 0x00000168 },
32889 - { 0x00008118, 0x000100aa },
32890 - { 0x0000811c, 0x00003210 },
32891 - { 0x00008124, 0x00000000 },
32892 - { 0x00008128, 0x00000000 },
32893 - { 0x0000812c, 0x00000000 },
32894 - { 0x00008130, 0x00000000 },
32895 - { 0x00008134, 0x00000000 },
32896 - { 0x00008138, 0x00000000 },
32897 - { 0x0000813c, 0x00000000 },
32898 - { 0x00008144, 0xffffffff },
32899 - { 0x00008168, 0x00000000 },
32900 - { 0x0000816c, 0x00000000 },
32901 - { 0x00008170, 0x18487320 },
32902 - { 0x00008174, 0xfaa4fa50 },
32903 - { 0x00008178, 0x00000100 },
32904 - { 0x0000817c, 0x00000000 },
32905 - { 0x000081c0, 0x00000000 },
32906 - { 0x000081c4, 0x00000000 },
32907 - { 0x000081d4, 0x00000000 },
32908 - { 0x000081ec, 0x00000000 },
32909 - { 0x000081f0, 0x00000000 },
32910 - { 0x000081f4, 0x00000000 },
32911 - { 0x000081f8, 0x00000000 },
32912 - { 0x000081fc, 0x00000000 },
32913 - { 0x00008200, 0x00000000 },
32914 - { 0x00008204, 0x00000000 },
32915 - { 0x00008208, 0x00000000 },
32916 - { 0x0000820c, 0x00000000 },
32917 - { 0x00008210, 0x00000000 },
32918 - { 0x00008214, 0x00000000 },
32919 - { 0x00008218, 0x00000000 },
32920 - { 0x0000821c, 0x00000000 },
32921 - { 0x00008220, 0x00000000 },
32922 - { 0x00008224, 0x00000000 },
32923 - { 0x00008228, 0x00000000 },
32924 - { 0x0000822c, 0x00000000 },
32925 - { 0x00008230, 0x00000000 },
32926 - { 0x00008234, 0x00000000 },
32927 - { 0x00008238, 0x00000000 },
32928 - { 0x0000823c, 0x00000000 },
32929 - { 0x00008240, 0x00100000 },
32930 - { 0x00008244, 0x0010f400 },
32931 - { 0x00008248, 0x00000100 },
32932 - { 0x0000824c, 0x0001e800 },
32933 - { 0x00008250, 0x00000000 },
32934 - { 0x00008254, 0x00000000 },
32935 - { 0x00008258, 0x00000000 },
32936 - { 0x0000825c, 0x400000ff },
32937 - { 0x00008260, 0x00080922 },
32938 - { 0x00008264, 0x88a00010 },
32939 - { 0x00008270, 0x00000000 },
32940 - { 0x00008274, 0x40000000 },
32941 - { 0x00008278, 0x003e4180 },
32942 - { 0x0000827c, 0x00000000 },
32943 - { 0x00008284, 0x0000002c },
32944 - { 0x00008288, 0x0000002c },
32945 - { 0x0000828c, 0x000000ff },
32946 - { 0x00008294, 0x00000000 },
32947 - { 0x00008298, 0x00000000 },
32948 - { 0x0000829c, 0x00000000 },
32949 - { 0x00008300, 0x00000040 },
32950 - { 0x00008314, 0x00000000 },
32951 - { 0x00008328, 0x00000000 },
32952 - { 0x0000832c, 0x00000007 },
32953 - { 0x00008330, 0x00000302 },
32954 - { 0x00008334, 0x00000e00 },
32955 - { 0x00008338, 0x00ff0000 },
32956 - { 0x0000833c, 0x00000000 },
32957 - { 0x00008340, 0x000107ff },
32958 - { 0x00008344, 0x01c81043 },
32959 - { 0x00008360, 0xffffffff },
32960 - { 0x00008364, 0xffffffff },
32961 - { 0x00008368, 0x00000000 },
32962 - { 0x00008370, 0x00000000 },
32963 - { 0x00008374, 0x000000ff },
32964 - { 0x00008378, 0x00000000 },
32965 - { 0x0000837c, 0x00000000 },
32966 - { 0x00008380, 0xffffffff },
32967 - { 0x00008384, 0xffffffff },
32968 - { 0x00008390, 0x0fffffff },
32969 - { 0x00008394, 0x0fffffff },
32970 - { 0x00008398, 0x00000000 },
32971 - { 0x0000839c, 0x00000000 },
32972 - { 0x000083a0, 0x00000000 },
32973 - { 0x00009808, 0x00000000 },
32974 - { 0x0000980c, 0xafe68e30 },
32975 - { 0x00009810, 0xfd14e000 },
32976 - { 0x00009814, 0x9c0a9f6b },
32977 - { 0x0000981c, 0x00000000 },
32978 - { 0x0000982c, 0x0000a000 },
32979 - { 0x00009830, 0x00000000 },
32980 - { 0x0000983c, 0x00200400 },
32981 - { 0x0000984c, 0x0040233c },
32982 - { 0x0000a84c, 0x0040233c },
32983 - { 0x00009854, 0x00000044 },
32984 - { 0x00009900, 0x00000000 },
32985 - { 0x00009904, 0x00000000 },
32986 - { 0x00009908, 0x00000000 },
32987 - { 0x0000990c, 0x00000000 },
32988 - { 0x00009910, 0x10002310 },
32989 - { 0x0000991c, 0x10000fff },
32990 - { 0x00009920, 0x04900000 },
32991 - { 0x0000a920, 0x04900000 },
32992 - { 0x00009928, 0x00000001 },
32993 - { 0x0000992c, 0x00000004 },
32994 - { 0x00009930, 0x00000000 },
32995 - { 0x0000a930, 0x00000000 },
32996 - { 0x00009934, 0x1e1f2022 },
32997 - { 0x00009938, 0x0a0b0c0d },
32998 - { 0x0000993c, 0x00000000 },
32999 - { 0x00009948, 0x9280c00a },
33000 - { 0x0000994c, 0x00020028 },
33001 - { 0x00009954, 0x5f3ca3de },
33002 - { 0x00009958, 0x0108ecff },
33003 - { 0x00009940, 0x14750604 },
33004 - { 0x0000c95c, 0x004b6a8e },
33005 - { 0x00009970, 0x990bb514 },
33006 - { 0x00009974, 0x00000000 },
33007 - { 0x00009978, 0x00000001 },
33008 - { 0x0000997c, 0x00000000 },
33009 - { 0x000099a0, 0x00000000 },
33010 - { 0x000099a4, 0x00000001 },
33011 - { 0x000099a8, 0x201fff00 },
33012 - { 0x000099ac, 0x0c6f0000 },
33013 - { 0x000099b0, 0x03051000 },
33014 - { 0x000099b4, 0x00000820 },
33015 - { 0x000099c4, 0x06336f77 },
33016 - { 0x000099c8, 0x6af6532f },
33017 - { 0x000099cc, 0x08f186c8 },
33018 - { 0x000099d0, 0x00046384 },
33019 - { 0x000099dc, 0x00000000 },
33020 - { 0x000099e0, 0x00000000 },
33021 - { 0x000099e4, 0xaaaaaaaa },
33022 - { 0x000099e8, 0x3c466478 },
33023 - { 0x000099ec, 0x0cc80caa },
33024 - { 0x000099f0, 0x00000000 },
33025 - { 0x000099fc, 0x00001042 },
33026 - { 0x0000a208, 0x803e4788 },
33027 - { 0x0000a210, 0x4080a333 },
33028 - { 0x0000a214, 0x40206c10 },
33029 - { 0x0000a218, 0x009c4060 },
33030 - { 0x0000a220, 0x01834061 },
33031 - { 0x0000a224, 0x00000400 },
33032 - { 0x0000a228, 0x000003b5 },
33033 - { 0x0000a22c, 0x233f7180 },
33034 - { 0x0000a234, 0x20202020 },
33035 - { 0x0000a238, 0x20202020 },
33036 - { 0x0000a23c, 0x13c889af },
33037 - { 0x0000a240, 0x38490a20 },
33038 - { 0x0000a244, 0x00000000 },
33039 - { 0x0000a248, 0xfffffffc },
33040 - { 0x0000a24c, 0x00000000 },
33041 - { 0x0000a254, 0x00000000 },
33042 - { 0x0000a258, 0x0cdbd380 },
33043 - { 0x0000a25c, 0x0f0f0f01 },
33044 - { 0x0000a260, 0xdfa91f01 },
33045 - { 0x0000a264, 0x00418a11 },
33046 - { 0x0000b264, 0x00418a11 },
33047 - { 0x0000a268, 0x00000000 },
33048 - { 0x0000a26c, 0x0e79e5c6 },
33049 - { 0x0000b26c, 0x0e79e5c6 },
33050 - { 0x0000d270, 0x00820820 },
33051 - { 0x0000a278, 0x1ce739ce },
33052 - { 0x0000a27c, 0x050701ce },
33053 - { 0x0000d35c, 0x07ffffef },
33054 - { 0x0000d360, 0x0fffffe7 },
33055 - { 0x0000d364, 0x17ffffe5 },
33056 - { 0x0000d368, 0x1fffffe4 },
33057 - { 0x0000d36c, 0x37ffffe3 },
33058 - { 0x0000d370, 0x3fffffe3 },
33059 - { 0x0000d374, 0x57ffffe3 },
33060 - { 0x0000d378, 0x5fffffe2 },
33061 - { 0x0000d37c, 0x7fffffe2 },
33062 - { 0x0000d380, 0x7f3c7bba },
33063 - { 0x0000d384, 0xf3307ff0 },
33064 - { 0x0000a388, 0x0c000000 },
33065 - { 0x0000a38c, 0x20202020 },
33066 - { 0x0000a390, 0x20202020 },
33067 - { 0x0000a394, 0x1ce739ce },
33068 - { 0x0000a398, 0x000001ce },
33069 - { 0x0000b398, 0x000001ce },
33070 - { 0x0000a39c, 0x00000001 },
33071 - { 0x0000a3c8, 0x00000246 },
33072 - { 0x0000a3cc, 0x20202020 },
33073 - { 0x0000a3d0, 0x20202020 },
33074 - { 0x0000a3d4, 0x20202020 },
33075 - { 0x0000a3dc, 0x1ce739ce },
33076 - { 0x0000a3e0, 0x000001ce },
33077 - { 0x0000a3e4, 0x00000000 },
33078 - { 0x0000a3e8, 0x18c43433 },
33079 - { 0x0000a3ec, 0x00f70081 },
33080 - { 0x0000a3f0, 0x01036a1e },
33081 - { 0x0000a3f4, 0x00000000 },
33082 - { 0x0000b3f4, 0x00000000 },
33083 - { 0x0000a7d8, 0x000003f1 },
33084 - { 0x00007800, 0x00000800 },
33085 - { 0x00007804, 0x6c35ffd2 },
33086 - { 0x00007808, 0x6db6c000 },
33087 - { 0x0000780c, 0x6db6cb30 },
33088 - { 0x00007810, 0x6db6cb6c },
33089 - { 0x00007814, 0x0501e200 },
33090 - { 0x00007818, 0x0094128d },
33091 - { 0x0000781c, 0x976ee392 },
33092 - { 0x00007820, 0xf75ff6fc },
33093 - { 0x00007824, 0x00040000 },
33094 - { 0x00007828, 0xdb003012 },
33095 - { 0x0000782c, 0x04924914 },
33096 - { 0x00007830, 0x21084210 },
33097 - { 0x00007834, 0x00140000 },
33098 - { 0x00007838, 0x0e4548d8 },
33099 - { 0x0000783c, 0x54214514 },
33100 - { 0x00007840, 0x02025830 },
33101 - { 0x00007844, 0x71c0d388 },
33102 - { 0x00007848, 0x934934a8 },
33103 - { 0x00007850, 0x00000000 },
33104 - { 0x00007854, 0x00000800 },
33105 - { 0x00007858, 0x6c35ffd2 },
33106 - { 0x0000785c, 0x6db6c000 },
33107 - { 0x00007860, 0x6db6cb30 },
33108 - { 0x00007864, 0x6db6cb6c },
33109 - { 0x00007868, 0x0501e200 },
33110 - { 0x0000786c, 0x0094128d },
33111 - { 0x00007870, 0x976ee392 },
33112 - { 0x00007874, 0xf75ff6fc },
33113 - { 0x00007878, 0x00040000 },
33114 - { 0x0000787c, 0xdb003012 },
33115 - { 0x00007880, 0x04924914 },
33116 - { 0x00007884, 0x21084210 },
33117 - { 0x00007888, 0x001b6db0 },
33118 - { 0x0000788c, 0x00376b63 },
33119 - { 0x00007890, 0x06db6db6 },
33120 - { 0x00007894, 0x006d8000 },
33121 - { 0x00007898, 0x48100000 },
33122 - { 0x0000789c, 0x00000000 },
33123 - { 0x000078a0, 0x08000000 },
33124 - { 0x000078a4, 0x0007ffd8 },
33125 - { 0x000078a8, 0x0007ffd8 },
33126 - { 0x000078ac, 0x001c0020 },
33127 - { 0x000078b0, 0x00060aeb },
33128 - { 0x000078b4, 0x40008080 },
33129 - { 0x000078b8, 0x2a850160 },
33130 -};
33131 -
33132 -/*
33133 - * For Japanese regulatory requirements, 2484 MHz requires the following three
33134 - * registers be programmed differently from the channel between 2412 and 2472 MHz.
33135 - */
33136 -static const u_int32_t ar9287Common_normal_cck_fir_coeff_92871_1[][2] = {
33137 - { 0x0000a1f4, 0x00fffeff },
33138 - { 0x0000a1f8, 0x00f5f9ff },
33139 - { 0x0000a1fc, 0xb79f6427 },
33140 -};
33141 -
33142 -static const u_int32_t ar9287Common_japan_2484_cck_fir_coeff_92871_1[][2] = {
33143 - { 0x0000a1f4, 0x00000000 },
33144 - { 0x0000a1f8, 0xefff0301 },
33145 - { 0x0000a1fc, 0xca9228ee },
33146 -};
33147 -
33148 -static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = {
33149 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
33150 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
33151 - { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 },
33152 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004 },
33153 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a, 0x0000c00a },
33154 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c, 0x0001000c },
33155 - { 0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b, 0x0001420b },
33156 - { 0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a, 0x0001824a },
33157 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a, 0x0001c44a },
33158 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a, 0x0002064a },
33159 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a, 0x0002484a },
33160 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a, 0x00028a4a },
33161 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a },
33162 - { 0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a, 0x00030e4a },
33163 - { 0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a, 0x00034e8a },
33164 - { 0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c, 0x00038e8c },
33165 - { 0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc, 0x0003cecc },
33166 - { 0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4, 0x00040ed4 },
33167 - { 0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc, 0x00044edc },
33168 - { 0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede, 0x00048ede },
33169 - { 0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e },
33170 - { 0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e, 0x00050f5e },
33171 - { 0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e, 0x00054f9e },
33172 - { 0x0000a780, 0x00000000, 0x00000000, 0x00000062, 0x00000062, 0x00000062 },
33173 - { 0x0000a784, 0x00000000, 0x00000000, 0x00004064, 0x00004064, 0x00004064 },
33174 - { 0x0000a788, 0x00000000, 0x00000000, 0x000080a4, 0x000080a4, 0x000080a4 },
33175 - { 0x0000a78c, 0x00000000, 0x00000000, 0x0000c0aa, 0x0000c0aa, 0x0000c0aa },
33176 - { 0x0000a790, 0x00000000, 0x00000000, 0x000100ac, 0x000100ac, 0x000100ac },
33177 - { 0x0000a794, 0x00000000, 0x00000000, 0x000140b4, 0x000140b4, 0x000140b4 },
33178 - { 0x0000a798, 0x00000000, 0x00000000, 0x000180f4, 0x000180f4, 0x000180f4 },
33179 - { 0x0000a79c, 0x00000000, 0x00000000, 0x0001c134, 0x0001c134, 0x0001c134 },
33180 - { 0x0000a7a0, 0x00000000, 0x00000000, 0x00020174, 0x00020174, 0x00020174 },
33181 - { 0x0000a7a4, 0x00000000, 0x00000000, 0x0002417c, 0x0002417c, 0x0002417c },
33182 - { 0x0000a7a8, 0x00000000, 0x00000000, 0x0002817e, 0x0002817e, 0x0002817e },
33183 - { 0x0000a7ac, 0x00000000, 0x00000000, 0x0002c1be, 0x0002c1be, 0x0002c1be },
33184 - { 0x0000a7b0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33185 - { 0x0000a7b4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33186 - { 0x0000a7b8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33187 - { 0x0000a7bc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33188 - { 0x0000a7c0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33189 - { 0x0000a7c4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33190 - { 0x0000a7c8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33191 - { 0x0000a7cc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33192 - { 0x0000a7d0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33193 - { 0x0000a7d4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33194 - { 0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000 },
33195 -};
33196 -
33197 -static const u_int32_t ar9287Modes_rx_gain_9287_1_1[][6] = {
33198 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
33199 - { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
33200 - { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
33201 - { 0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
33202 - { 0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
33203 - { 0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
33204 - { 0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
33205 - { 0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
33206 - { 0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
33207 - { 0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
33208 - { 0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
33209 - { 0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
33210 - { 0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
33211 - { 0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
33212 - { 0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
33213 - { 0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
33214 - { 0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
33215 - { 0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
33216 - { 0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
33217 - { 0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
33218 - { 0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
33219 - { 0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
33220 - { 0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
33221 - { 0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
33222 - { 0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
33223 - { 0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
33224 - { 0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
33225 - { 0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
33226 - { 0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
33227 - { 0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
33228 - { 0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
33229 - { 0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
33230 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
33231 - { 0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
33232 - { 0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
33233 - { 0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
33234 - { 0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
33235 - { 0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
33236 - { 0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
33237 - { 0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
33238 - { 0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
33239 - { 0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
33240 - { 0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
33241 - { 0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
33242 - { 0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
33243 - { 0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
33244 - { 0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
33245 - { 0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
33246 - { 0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
33247 - { 0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
33248 - { 0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
33249 - { 0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
33250 - { 0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
33251 - { 0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
33252 - { 0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
33253 - { 0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
33254 - { 0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
33255 - { 0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
33256 - { 0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
33257 - { 0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
33258 - { 0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
33259 - { 0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
33260 - { 0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
33261 - { 0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
33262 - { 0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
33263 - { 0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
33264 - { 0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
33265 - { 0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
33266 - { 0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
33267 - { 0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
33268 - { 0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
33269 - { 0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
33270 - { 0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
33271 - { 0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
33272 - { 0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
33273 - { 0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
33274 - { 0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
33275 - { 0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
33276 - { 0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
33277 - { 0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
33278 - { 0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
33279 - { 0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
33280 - { 0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
33281 - { 0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
33282 - { 0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
33283 - { 0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
33284 - { 0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
33285 - { 0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
33286 - { 0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
33287 - { 0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
33288 - { 0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
33289 - { 0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
33290 - { 0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
33291 - { 0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
33292 - { 0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
33293 - { 0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
33294 - { 0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
33295 - { 0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
33296 - { 0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
33297 - { 0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
33298 - { 0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
33299 - { 0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
33300 - { 0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
33301 - { 0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
33302 - { 0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33303 - { 0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33304 - { 0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33305 - { 0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33306 - { 0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33307 - { 0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33308 - { 0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33309 - { 0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33310 - { 0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33311 - { 0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33312 - { 0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33313 - { 0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33314 - { 0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33315 - { 0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33316 - { 0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33317 - { 0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33318 - { 0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33319 - { 0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33320 - { 0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33321 - { 0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33322 - { 0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33323 - { 0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33324 - { 0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33325 - { 0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33326 - { 0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33327 - { 0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
33328 - { 0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
33329 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
33330 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
33331 - { 0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
33332 - { 0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
33333 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
33334 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
33335 - { 0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
33336 - { 0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
33337 - { 0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
33338 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
33339 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
33340 - { 0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
33341 - { 0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
33342 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
33343 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
33344 - { 0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
33345 - { 0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
33346 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
33347 - { 0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
33348 - { 0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
33349 - { 0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
33350 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
33351 - { 0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
33352 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
33353 - { 0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
33354 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
33355 - { 0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
33356 - { 0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
33357 - { 0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
33358 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
33359 - { 0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
33360 - { 0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
33361 - { 0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
33362 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
33363 - { 0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
33364 - { 0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
33365 - { 0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
33366 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
33367 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
33368 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
33369 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
33370 - { 0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
33371 - { 0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
33372 - { 0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
33373 - { 0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
33374 - { 0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
33375 - { 0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
33376 - { 0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
33377 - { 0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
33378 - { 0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
33379 - { 0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
33380 - { 0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
33381 - { 0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
33382 - { 0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
33383 - { 0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
33384 - { 0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
33385 - { 0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
33386 - { 0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
33387 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
33388 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
33389 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
33390 - { 0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
33391 - { 0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
33392 - { 0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
33393 - { 0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
33394 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
33395 - { 0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
33396 - { 0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
33397 - { 0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
33398 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
33399 - { 0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
33400 - { 0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
33401 - { 0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
33402 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
33403 - { 0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
33404 - { 0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
33405 - { 0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
33406 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
33407 - { 0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
33408 - { 0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
33409 - { 0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
33410 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
33411 - { 0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
33412 - { 0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
33413 - { 0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
33414 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
33415 - { 0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
33416 - { 0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
33417 - { 0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
33418 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
33419 - { 0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
33420 - { 0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
33421 - { 0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
33422 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
33423 - { 0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
33424 - { 0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
33425 - { 0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
33426 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
33427 - { 0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
33428 - { 0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
33429 - { 0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
33430 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33431 - { 0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33432 - { 0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33433 - { 0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33434 - { 0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33435 - { 0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33436 - { 0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33437 - { 0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33438 - { 0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33439 - { 0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33440 - { 0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33441 - { 0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33442 - { 0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33443 - { 0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33444 - { 0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33445 - { 0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33446 - { 0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33447 - { 0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33448 - { 0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33449 - { 0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33450 - { 0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33451 - { 0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33452 - { 0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33453 - { 0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33454 - { 0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33455 - { 0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
33456 - { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
33457 -};
33458 -
33459 -static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
33460 - {0x00004040, 0x9248fd00 },
33461 - {0x00004040, 0x24924924 },
33462 - {0x00004040, 0xa8000019 },
33463 - {0x00004040, 0x13160820 },
33464 - {0x00004040, 0xe5980560 },
33465 - {0x00004040, 0xc01dcffd },
33466 - {0x00004040, 0x1aaabe41 },
33467 - {0x00004040, 0xbe105554 },
33468 - {0x00004040, 0x00043007 },
33469 - {0x00004044, 0x00000000 },
33470 -};
33471 -
33472 -static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
33473 - {0x00004040, 0x9248fd00 },
33474 - {0x00004040, 0x24924924 },
33475 - {0x00004040, 0xa8000019 },
33476 - {0x00004040, 0x13160820 },
33477 - {0x00004040, 0xe5980560 },
33478 - {0x00004040, 0xc01dcffc },
33479 - {0x00004040, 0x1aaabe41 },
33480 - {0x00004040, 0xbe105554 },
33481 - {0x00004040, 0x00043007 },
33482 - {0x00004044, 0x00000000 },
33483 -};
33484 -
33485 -
33486 -/* AR9271 initialization values automaticaly created: 06/04/09 */
33487 -static const u_int32_t ar9271Modes_9271[][6] = {
33488 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
33489 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
33490 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
33491 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
33492 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
33493 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
33494 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
33495 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
33496 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
33497 - { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
33498 - { 0x00009828, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001 },
33499 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
33500 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
33501 - { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
33502 - { 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
33503 - { 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
33504 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
33505 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
33506 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
33507 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
33508 - { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18 },
33509 - { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
33510 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
33511 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
33512 - { 0x00009910, 0x30002310, 0x30002310, 0x30002310, 0x30002310, 0x30002310 },
33513 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
33514 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
33515 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
33516 - { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
33517 - { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
33518 - { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
33519 - { 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
33520 - { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
33521 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
33522 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
33523 - { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
33524 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
33525 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
33526 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
33527 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
33528 - { 0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
33529 - { 0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
33530 - { 0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
33531 - { 0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
33532 - { 0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
33533 - { 0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
33534 - { 0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
33535 - { 0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
33536 - { 0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
33537 - { 0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
33538 - { 0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
33539 - { 0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
33540 - { 0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
33541 - { 0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
33542 - { 0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
33543 - { 0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
33544 - { 0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
33545 - { 0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
33546 - { 0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
33547 - { 0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
33548 - { 0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
33549 - { 0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
33550 - { 0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
33551 - { 0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
33552 - { 0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
33553 - { 0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
33554 - { 0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
33555 - { 0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
33556 - { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
33557 - { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
33558 - { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
33559 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
33560 - { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
33561 - { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
33562 - { 0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
33563 - { 0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
33564 - { 0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
33565 - { 0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
33566 - { 0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
33567 - { 0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
33568 - { 0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
33569 - { 0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
33570 - { 0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
33571 - { 0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
33572 - { 0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
33573 - { 0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
33574 - { 0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
33575 - { 0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
33576 - { 0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
33577 - { 0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
33578 - { 0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
33579 - { 0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
33580 - { 0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
33581 - { 0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
33582 - { 0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
33583 - { 0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
33584 - { 0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
33585 - { 0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
33586 - { 0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
33587 - { 0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
33588 - { 0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
33589 - { 0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
33590 - { 0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
33591 - { 0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
33592 - { 0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
33593 - { 0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
33594 - { 0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
33595 - { 0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
33596 - { 0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
33597 - { 0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
33598 - { 0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
33599 - { 0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
33600 - { 0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
33601 - { 0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
33602 - { 0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
33603 - { 0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
33604 - { 0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
33605 - { 0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
33606 - { 0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
33607 - { 0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
33608 - { 0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
33609 - { 0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
33610 - { 0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
33611 - { 0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
33612 - { 0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
33613 - { 0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
33614 - { 0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
33615 - { 0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
33616 - { 0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
33617 - { 0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33618 - { 0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33619 - { 0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33620 - { 0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33621 - { 0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33622 - { 0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33623 - { 0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33624 - { 0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33625 - { 0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33626 - { 0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33627 - { 0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33628 - { 0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33629 - { 0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33630 - { 0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33631 - { 0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33632 - { 0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33633 - { 0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33634 - { 0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33635 - { 0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33636 - { 0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33637 - { 0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33638 - { 0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33639 - { 0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33640 - { 0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33641 - { 0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33642 - { 0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33643 - { 0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33644 - { 0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33645 - { 0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33646 - { 0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33647 - { 0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33648 - { 0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33649 - { 0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33650 - { 0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33651 - { 0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33652 - { 0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33653 - { 0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33654 - { 0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33655 - { 0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33656 - { 0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
33657 - { 0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
33658 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
33659 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
33660 - { 0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
33661 - { 0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
33662 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
33663 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
33664 - { 0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
33665 - { 0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
33666 - { 0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
33667 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
33668 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
33669 - { 0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
33670 - { 0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
33671 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
33672 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
33673 - { 0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
33674 - { 0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
33675 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
33676 - { 0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
33677 - { 0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
33678 - { 0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
33679 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
33680 - { 0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
33681 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
33682 - { 0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
33683 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
33684 - { 0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
33685 - { 0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
33686 - { 0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
33687 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
33688 - { 0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
33689 - { 0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
33690 - { 0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
33691 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
33692 - { 0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
33693 - { 0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
33694 - { 0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
33695 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
33696 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
33697 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
33698 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
33699 - { 0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
33700 - { 0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
33701 - { 0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
33702 - { 0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
33703 - { 0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
33704 - { 0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
33705 - { 0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
33706 - { 0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
33707 - { 0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
33708 - { 0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
33709 - { 0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
33710 - { 0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
33711 - { 0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
33712 - { 0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
33713 - { 0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
33714 - { 0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
33715 - { 0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
33716 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
33717 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
33718 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
33719 - { 0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
33720 - { 0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
33721 - { 0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
33722 - { 0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
33723 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
33724 - { 0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
33725 - { 0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
33726 - { 0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
33727 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
33728 - { 0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
33729 - { 0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
33730 - { 0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
33731 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
33732 - { 0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
33733 - { 0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
33734 - { 0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
33735 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
33736 - { 0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
33737 - { 0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
33738 - { 0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
33739 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
33740 - { 0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
33741 - { 0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
33742 - { 0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
33743 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
33744 - { 0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
33745 - { 0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33746 - { 0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33747 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33748 - { 0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33749 - { 0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33750 - { 0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33751 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33752 - { 0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33753 - { 0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33754 - { 0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33755 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33756 - { 0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33757 - { 0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33758 - { 0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33759 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33760 - { 0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33761 - { 0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33762 - { 0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33763 - { 0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33764 - { 0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33765 - { 0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33766 - { 0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33767 - { 0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33768 - { 0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33769 - { 0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33770 - { 0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33771 - { 0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33772 - { 0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33773 - { 0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33774 - { 0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33775 - { 0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33776 - { 0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33777 - { 0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33778 - { 0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33779 - { 0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33780 - { 0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33781 - { 0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33782 - { 0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33783 - { 0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33784 - { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
33785 - { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
33786 - { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
33787 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
33788 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
33789 - { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
33790 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
33791 -};
33792 -
33793 -static const u_int32_t ar9271Common_9271[][2] = {
33794 - { 0x0000000c, 0x00000000 },
33795 - { 0x00000030, 0x00020045 },
33796 - { 0x00000034, 0x00000005 },
33797 - { 0x00000040, 0x00000000 },
33798 - { 0x00000044, 0x00000008 },
33799 - { 0x00000048, 0x00000008 },
33800 - { 0x0000004c, 0x00000010 },
33801 - { 0x00000050, 0x00000000 },
33802 - { 0x00000054, 0x0000001f },
33803 - { 0x00000800, 0x00000000 },
33804 - { 0x00000804, 0x00000000 },
33805 - { 0x00000808, 0x00000000 },
33806 - { 0x0000080c, 0x00000000 },
33807 - { 0x00000810, 0x00000000 },
33808 - { 0x00000814, 0x00000000 },
33809 - { 0x00000818, 0x00000000 },
33810 - { 0x0000081c, 0x00000000 },
33811 - { 0x00000820, 0x00000000 },
33812 - { 0x00000824, 0x00000000 },
33813 - { 0x00001040, 0x002ffc0f },
33814 - { 0x00001044, 0x002ffc0f },
33815 - { 0x00001048, 0x002ffc0f },
33816 - { 0x0000104c, 0x002ffc0f },
33817 - { 0x00001050, 0x002ffc0f },
33818 - { 0x00001054, 0x002ffc0f },
33819 - { 0x00001058, 0x002ffc0f },
33820 - { 0x0000105c, 0x002ffc0f },
33821 - { 0x00001060, 0x002ffc0f },
33822 - { 0x00001064, 0x002ffc0f },
33823 - { 0x00001230, 0x00000000 },
33824 - { 0x00001270, 0x00000000 },
33825 - { 0x00001038, 0x00000000 },
33826 - { 0x00001078, 0x00000000 },
33827 - { 0x000010b8, 0x00000000 },
33828 - { 0x000010f8, 0x00000000 },
33829 - { 0x00001138, 0x00000000 },
33830 - { 0x00001178, 0x00000000 },
33831 - { 0x000011b8, 0x00000000 },
33832 - { 0x000011f8, 0x00000000 },
33833 - { 0x00001238, 0x00000000 },
33834 - { 0x00001278, 0x00000000 },
33835 - { 0x000012b8, 0x00000000 },
33836 - { 0x000012f8, 0x00000000 },
33837 - { 0x00001338, 0x00000000 },
33838 - { 0x00001378, 0x00000000 },
33839 - { 0x000013b8, 0x00000000 },
33840 - { 0x000013f8, 0x00000000 },
33841 - { 0x00001438, 0x00000000 },
33842 - { 0x00001478, 0x00000000 },
33843 - { 0x000014b8, 0x00000000 },
33844 - { 0x000014f8, 0x00000000 },
33845 - { 0x00001538, 0x00000000 },
33846 - { 0x00001578, 0x00000000 },
33847 - { 0x000015b8, 0x00000000 },
33848 - { 0x000015f8, 0x00000000 },
33849 - { 0x00001638, 0x00000000 },
33850 - { 0x00001678, 0x00000000 },
33851 - { 0x000016b8, 0x00000000 },
33852 - { 0x000016f8, 0x00000000 },
33853 - { 0x00001738, 0x00000000 },
33854 - { 0x00001778, 0x00000000 },
33855 - { 0x000017b8, 0x00000000 },
33856 - { 0x000017f8, 0x00000000 },
33857 - { 0x0000103c, 0x00000000 },
33858 - { 0x0000107c, 0x00000000 },
33859 - { 0x000010bc, 0x00000000 },
33860 - { 0x000010fc, 0x00000000 },
33861 - { 0x0000113c, 0x00000000 },
33862 - { 0x0000117c, 0x00000000 },
33863 - { 0x000011bc, 0x00000000 },
33864 - { 0x000011fc, 0x00000000 },
33865 - { 0x0000123c, 0x00000000 },
33866 - { 0x0000127c, 0x00000000 },
33867 - { 0x000012bc, 0x00000000 },
33868 - { 0x000012fc, 0x00000000 },
33869 - { 0x0000133c, 0x00000000 },
33870 - { 0x0000137c, 0x00000000 },
33871 - { 0x000013bc, 0x00000000 },
33872 - { 0x000013fc, 0x00000000 },
33873 - { 0x0000143c, 0x00000000 },
33874 - { 0x0000147c, 0x00000000 },
33875 - { 0x00004030, 0x00000002 },
33876 - { 0x0000403c, 0x00000002 },
33877 - { 0x00004024, 0x0000001f },
33878 - { 0x00004060, 0x00000000 },
33879 - { 0x00004064, 0x00000000 },
33880 - { 0x00008004, 0x00000000 },
33881 - { 0x00008008, 0x00000000 },
33882 - { 0x0000800c, 0x00000000 },
33883 - { 0x00008018, 0x00000700 },
33884 - { 0x00008020, 0x00000000 },
33885 - { 0x00008038, 0x00000000 },
33886 - { 0x0000803c, 0x00000000 },
33887 - { 0x00008048, 0x00000000 },
33888 - { 0x00008054, 0x00000000 },
33889 - { 0x00008058, 0x00000000 },
33890 - { 0x0000805c, 0x000fc78f },
33891 - { 0x00008060, 0x0000000f },
33892 - { 0x00008064, 0x00000000 },
33893 - { 0x00008070, 0x00000000 },
33894 - { 0x000080b0, 0x00000000 },
33895 - { 0x000080b4, 0x00000000 },
33896 - { 0x000080b8, 0x00000000 },
33897 - { 0x000080bc, 0x00000000 },
33898 - { 0x000080c0, 0x2a80001a },
33899 - { 0x000080c4, 0x05dc01e0 },
33900 - { 0x000080c8, 0x1f402710 },
33901 - { 0x000080cc, 0x01f40000 },
33902 - { 0x000080d0, 0x00001e00 },
33903 - { 0x000080d4, 0x00000000 },
33904 - { 0x000080d8, 0x00400000 },
33905 - { 0x000080e0, 0xffffffff },
33906 - { 0x000080e4, 0x0000ffff },
33907 - { 0x000080e8, 0x003f3f3f },
33908 - { 0x000080ec, 0x00000000 },
33909 - { 0x000080f0, 0x00000000 },
33910 - { 0x000080f4, 0x00000000 },
33911 - { 0x000080f8, 0x00000000 },
33912 - { 0x000080fc, 0x00020000 },
33913 - { 0x00008100, 0x00020000 },
33914 - { 0x00008104, 0x00000001 },
33915 - { 0x00008108, 0x00000052 },
33916 - { 0x0000810c, 0x00000000 },
33917 - { 0x00008110, 0x00000168 },
33918 - { 0x00008118, 0x000100aa },
33919 - { 0x0000811c, 0x00003210 },
33920 - { 0x00008120, 0x08f04810 },
33921 - { 0x00008124, 0x00000000 },
33922 - { 0x00008128, 0x00000000 },
33923 - { 0x0000812c, 0x00000000 },
33924 - { 0x00008130, 0x00000000 },
33925 - { 0x00008134, 0x00000000 },
33926 - { 0x00008138, 0x00000000 },
33927 - { 0x0000813c, 0x00000000 },
33928 - { 0x00008144, 0xffffffff },
33929 - { 0x00008168, 0x00000000 },
33930 - { 0x0000816c, 0x00000000 },
33931 - { 0x00008170, 0x32143320 },
33932 - { 0x00008174, 0xfaa4fa50 },
33933 - { 0x00008178, 0x00000100 },
33934 - { 0x0000817c, 0x00000000 },
33935 - { 0x000081c0, 0x00000000 },
33936 - { 0x000081d0, 0x0000320a },
33937 - { 0x000081ec, 0x00000000 },
33938 - { 0x000081f0, 0x00000000 },
33939 - { 0x000081f4, 0x00000000 },
33940 - { 0x000081f8, 0x00000000 },
33941 - { 0x000081fc, 0x00000000 },
33942 - { 0x00008200, 0x00000000 },
33943 - { 0x00008204, 0x00000000 },
33944 - { 0x00008208, 0x00000000 },
33945 - { 0x0000820c, 0x00000000 },
33946 - { 0x00008210, 0x00000000 },
33947 - { 0x00008214, 0x00000000 },
33948 - { 0x00008218, 0x00000000 },
33949 - { 0x0000821c, 0x00000000 },
33950 - { 0x00008220, 0x00000000 },
33951 - { 0x00008224, 0x00000000 },
33952 - { 0x00008228, 0x00000000 },
33953 - { 0x0000822c, 0x00000000 },
33954 - { 0x00008230, 0x00000000 },
33955 - { 0x00008234, 0x00000000 },
33956 - { 0x00008238, 0x00000000 },
33957 - { 0x0000823c, 0x00000000 },
33958 - { 0x00008240, 0x00100000 },
33959 - { 0x00008244, 0x0010f400 },
33960 - { 0x00008248, 0x00000100 },
33961 - { 0x0000824c, 0x0001e800 },
33962 - { 0x00008250, 0x00000000 },
33963 - { 0x00008254, 0x00000000 },
33964 - { 0x00008258, 0x00000000 },
33965 - { 0x0000825c, 0x400000ff },
33966 - { 0x00008260, 0x00080922 },
33967 - { 0x00008264, 0xa8a00010 },
33968 - { 0x00008270, 0x00000000 },
33969 - { 0x00008274, 0x40000000 },
33970 - { 0x00008278, 0x003e4180 },
33971 - { 0x0000827c, 0x00000000 },
33972 - { 0x00008284, 0x0000002c },
33973 - { 0x00008288, 0x0000002c },
33974 - { 0x0000828c, 0x00000000 },
33975 - { 0x00008294, 0x00000000 },
33976 - { 0x00008298, 0x00000000 },
33977 - { 0x0000829c, 0x00000000 },
33978 - { 0x00008300, 0x00000040 },
33979 - { 0x00008314, 0x00000000 },
33980 - { 0x00008328, 0x00000000 },
33981 - { 0x0000832c, 0x00000001 },
33982 - { 0x00008330, 0x00000302 },
33983 - { 0x00008334, 0x00000e00 },
33984 - { 0x00008338, 0x00ff0000 },
33985 - { 0x0000833c, 0x00000000 },
33986 - { 0x00008340, 0x00010380 },
33987 - { 0x00008344, 0x00581043 },
33988 - { 0x00007010, 0x00000030 },
33989 - { 0x00007034, 0x00000002 },
33990 - { 0x00007038, 0x000004c2 },
33991 - { 0x00007800, 0x00140000 },
33992 - { 0x00007804, 0x0e4548d8 },
33993 - { 0x00007808, 0x54214514 },
33994 - { 0x0000780c, 0x02025820 },
33995 - { 0x00007810, 0x71c0d388 },
33996 - { 0x00007814, 0x924934a8 },
33997 - { 0x0000781c, 0x00000000 },
33998 - { 0x00007828, 0x66964300 },
33999 - { 0x0000782c, 0x8db6d961 },
34000 - { 0x00007830, 0x8db6d96c },
34001 - { 0x00007834, 0x6140008b },
34002 - { 0x0000783c, 0x72ee0a72 },
34003 - { 0x00007840, 0xbbfffffc },
34004 - { 0x00007844, 0x000c0db6 },
34005 - { 0x00007848, 0x6db61b6f },
34006 - { 0x0000784c, 0x6d9b66db },
34007 - { 0x00007850, 0x6d8c6dba },
34008 - { 0x00007854, 0x00040000 },
34009 - { 0x00007858, 0xdb003012 },
34010 - { 0x0000785c, 0x04924914 },
34011 - { 0x00007860, 0x21084210 },
34012 - { 0x00007864, 0xf7d7ffde },
34013 - { 0x00007868, 0xc2034080 },
34014 - { 0x00007870, 0x10142c00 },
34015 - { 0x00009808, 0x00000000 },
34016 - { 0x0000980c, 0xafe68e30 },
34017 - { 0x00009810, 0xfd14e000 },
34018 - { 0x00009814, 0x9c0a9f6b },
34019 - { 0x0000981c, 0x00000000 },
34020 - { 0x0000982c, 0x0000a000 },
34021 - { 0x00009830, 0x00000000 },
34022 - { 0x0000983c, 0x00200400 },
34023 - { 0x0000984c, 0x0040233c },
34024 - { 0x00009854, 0x00000044 },
34025 - { 0x00009900, 0x00000000 },
34026 - { 0x00009904, 0x00000000 },
34027 - { 0x00009908, 0x00000000 },
34028 - { 0x0000990c, 0x00000000 },
34029 - { 0x0000991c, 0x10000fff },
34030 - { 0x00009920, 0x04900000 },
34031 - { 0x00009928, 0x00000001 },
34032 - { 0x0000992c, 0x00000004 },
34033 - { 0x00009934, 0x1e1f2022 },
34034 - { 0x00009938, 0x0a0b0c0d },
34035 - { 0x0000993c, 0x00000000 },
34036 - { 0x00009940, 0x14750604 },
34037 - { 0x00009948, 0x9280c00a },
34038 - { 0x0000994c, 0x00020028 },
34039 - { 0x00009954, 0x5f3ca3de },
34040 - { 0x00009958, 0x0108ecff },
34041 - { 0x00009968, 0x000003ce },
34042 - { 0x00009970, 0x192bb514 },
34043 - { 0x00009974, 0x00000000 },
34044 - { 0x00009978, 0x00000001 },
34045 - { 0x0000997c, 0x00000000 },
34046 - { 0x00009980, 0x00000000 },
34047 - { 0x00009984, 0x00000000 },
34048 - { 0x00009988, 0x00000000 },
34049 - { 0x0000998c, 0x00000000 },
34050 - { 0x00009990, 0x00000000 },
34051 - { 0x00009994, 0x00000000 },
34052 - { 0x00009998, 0x00000000 },
34053 - { 0x0000999c, 0x00000000 },
34054 - { 0x000099a0, 0x00000000 },
34055 - { 0x000099a4, 0x00000001 },
34056 - { 0x000099a8, 0x201fff00 },
34057 - { 0x000099ac, 0x2def0400 },
34058 - { 0x000099b0, 0x03051000 },
34059 - { 0x000099b4, 0x00000820 },
34060 - { 0x000099dc, 0x00000000 },
34061 - { 0x000099e0, 0x00000000 },
34062 - { 0x000099e4, 0xaaaaaaaa },
34063 - { 0x000099e8, 0x3c466478 },
34064 - { 0x000099ec, 0x0cc80caa },
34065 - { 0x000099f0, 0x00000000 },
34066 - { 0x0000a208, 0x803e68c8 },
34067 - { 0x0000a210, 0x4080a333 },
34068 - { 0x0000a214, 0x00206c10 },
34069 - { 0x0000a218, 0x009c4060 },
34070 - { 0x0000a220, 0x01834061 },
34071 - { 0x0000a224, 0x00000400 },
34072 - { 0x0000a228, 0x000003b5 },
34073 - { 0x0000a22c, 0x00000000 },
34074 - { 0x0000a234, 0x20202020 },
34075 - { 0x0000a238, 0x20202020 },
34076 - { 0x0000a244, 0x00000000 },
34077 - { 0x0000a248, 0xfffffffc },
34078 - { 0x0000a24c, 0x00000000 },
34079 - { 0x0000a254, 0x00000000 },
34080 - { 0x0000a258, 0x0ccb5380 },
34081 - { 0x0000a25c, 0x15151501 },
34082 - { 0x0000a260, 0xdfa90f01 },
34083 - { 0x0000a268, 0x00000000 },
34084 - { 0x0000a26c, 0x0ebae9e6 },
34085 - { 0x0000a388, 0x0c000000 },
34086 - { 0x0000a38c, 0x20202020 },
34087 - { 0x0000a390, 0x20202020 },
34088 - { 0x0000a39c, 0x00000001 },
34089 - { 0x0000a3a0, 0x00000000 },
34090 - { 0x0000a3a4, 0x00000000 },
34091 - { 0x0000a3a8, 0x00000000 },
34092 - { 0x0000a3ac, 0x00000000 },
34093 - { 0x0000a3b0, 0x00000000 },
34094 - { 0x0000a3b4, 0x00000000 },
34095 - { 0x0000a3b8, 0x00000000 },
34096 - { 0x0000a3bc, 0x00000000 },
34097 - { 0x0000a3c0, 0x00000000 },
34098 - { 0x0000a3c4, 0x00000000 },
34099 - { 0x0000a3cc, 0x20202020 },
34100 - { 0x0000a3d0, 0x20202020 },
34101 - { 0x0000a3d4, 0x20202020 },
34102 - { 0x0000a3e4, 0x00000000 },
34103 - { 0x0000a3e8, 0x18c43433 },
34104 - { 0x0000a3ec, 0x00f70081 },
34105 - { 0x0000a3f0, 0x01036a2f },
34106 - { 0x0000a3f4, 0x00000000 },
34107 - { 0x0000d270, 0x0d820820 },
34108 - { 0x0000d35c, 0x07ffffef },
34109 - { 0x0000d360, 0x0fffffe7 },
34110 - { 0x0000d364, 0x17ffffe5 },
34111 - { 0x0000d368, 0x1fffffe4 },
34112 - { 0x0000d36c, 0x37ffffe3 },
34113 - { 0x0000d370, 0x3fffffe3 },
34114 - { 0x0000d374, 0x57ffffe3 },
34115 - { 0x0000d378, 0x5fffffe2 },
34116 - { 0x0000d37c, 0x7fffffe2 },
34117 - { 0x0000d380, 0x7f3c7bba },
34118 - { 0x0000d384, 0xf3307ff0 },
34119 -};
34120 -
34121 -static const u_int32_t ar9271Common_normal_cck_fir_coeff_9271[][2] = {
34122 - { 0x0000a1f4, 0x00fffeff },
34123 - { 0x0000a1f8, 0x00f5f9ff },
34124 - { 0x0000a1fc, 0xb79f6427 },
34125 -};
34126 -
34127 -static const u_int32_t ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = {
34128 - { 0x0000a1f4, 0x00000000 },
34129 - { 0x0000a1f8, 0xefff0301 },
34130 - { 0x0000a1fc, 0xca9228ee },
34131 -};
34132 -
34133 -static const u_int32_t ar9271Modes_9271_1_0_only[][6] = {
34134 - { 0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311 },
34135 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
34136 -};
34137 -
34138 -static const u_int32_t ar9271Modes_9271_ANI_reg[][6] = {
34139 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
34140 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
34141 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
34142 - { 0x0000986c, 0x06903881, 0x06903881, 0x06903881, 0x06903881, 0x06903881 },
34143 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
34144 - { 0x0000a208, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8 },
34145 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
34146 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
34147 -};
34148 -
34149 -static const u_int32_t ar9271Modes_normal_power_tx_gain_9271[][6] = {
34150 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
34151 - { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
34152 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
34153 - { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
34154 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001e610, 0x0001e610, 0x00000000 },
34155 - { 0x0000a314, 0x00000000, 0x00000000, 0x0002d6d0, 0x0002d6d0, 0x00000000 },
34156 - { 0x0000a318, 0x00000000, 0x00000000, 0x00039758, 0x00039758, 0x00000000 },
34157 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0003b759, 0x0003b759, 0x00000000 },
34158 - { 0x0000a320, 0x00000000, 0x00000000, 0x0003d75a, 0x0003d75a, 0x00000000 },
34159 - { 0x0000a324, 0x00000000, 0x00000000, 0x0004175c, 0x0004175c, 0x00000000 },
34160 - { 0x0000a328, 0x00000000, 0x00000000, 0x0004575e, 0x0004575e, 0x00000000 },
34161 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0004979f, 0x0004979f, 0x00000000 },
34162 - { 0x0000a330, 0x00000000, 0x00000000, 0x0004d7df, 0x0004d7df, 0x00000000 },
34163 - { 0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de, 0x00000000 },
34164 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
34165 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
34166 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34167 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34168 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34169 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34170 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34171 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34172 - { 0x00007838, 0x00000029, 0x00000029, 0x00000029, 0x00000029, 0x00000029 },
34173 - { 0x00007824, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff },
34174 - { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
34175 - { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
34176 - { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a218652, 0x0a218652, 0x0a22a652 },
34177 - { 0x0000a278, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
34178 - { 0x0000a27c, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd },
34179 - { 0x0000a394, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
34180 - { 0x0000a398, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd },
34181 - { 0x0000a3dc, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
34182 - { 0x0000a3e0, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd },
34183 -};
34184 -
34185 -static const u_int32_t ar9271Modes_high_power_tx_gain_9271[][6] = {
34186 - { 0x0000a300, 0x00000000, 0x00000000, 0x00010000, 0x00010000, 0x00000000 },
34187 - { 0x0000a304, 0x00000000, 0x00000000, 0x00016200, 0x00016200, 0x00000000 },
34188 - { 0x0000a308, 0x00000000, 0x00000000, 0x00018201, 0x00018201, 0x00000000 },
34189 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0001b240, 0x0001b240, 0x00000000 },
34190 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001d241, 0x0001d241, 0x00000000 },
34191 - { 0x0000a314, 0x00000000, 0x00000000, 0x0001f600, 0x0001f600, 0x00000000 },
34192 - { 0x0000a318, 0x00000000, 0x00000000, 0x00022800, 0x00022800, 0x00000000 },
34193 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00026802, 0x00026802, 0x00000000 },
34194 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002b805, 0x0002b805, 0x00000000 },
34195 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002ea41, 0x0002ea41, 0x00000000 },
34196 - { 0x0000a328, 0x00000000, 0x00000000, 0x00038b00, 0x00038b00, 0x00000000 },
34197 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0003ab40, 0x0003ab40, 0x00000000 },
34198 - { 0x0000a330, 0x00000000, 0x00000000, 0x0003cd80, 0x0003cd80, 0x00000000 },
34199 - { 0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de, 0x00000000 },
34200 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
34201 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
34202 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34203 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34204 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34205 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34206 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34207 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34208 - { 0x00007838, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b },
34209 - { 0x00007824, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff },
34210 - { 0x0000786c, 0x08609eb6, 0x08609eb6, 0x08609eba, 0x08609eba, 0x08609eb6 },
34211 - { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
34212 - { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a212652, 0x0a212652, 0x0a22a652 },
34213 - { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
34214 - { 0x0000a27c, 0x05018063, 0x05038063, 0x05018063, 0x05018063, 0x05018063 },
34215 - { 0x0000a394, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63 },
34216 - { 0x0000a398, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063 },
34217 - { 0x0000a3dc, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63 },
34218 - { 0x0000a3e0, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063 },
34219 -};
34220 diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
34221 index 4a2060e..c0a9a71 100644
34222 --- a/drivers/net/wireless/ath/ath9k/mac.c
34223 +++ b/drivers/net/wireless/ath/ath9k/mac.c
34224 @@ -207,281 +207,6 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
34225 }
34226 EXPORT_SYMBOL(ath9k_hw_stoptxdma);
34227
34228 -void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
34229 - u32 segLen, bool firstSeg,
34230 - bool lastSeg, const struct ath_desc *ds0)
34231 -{
34232 - struct ar5416_desc *ads = AR5416DESC(ds);
34233 -
34234 - if (firstSeg) {
34235 - ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
34236 - } else if (lastSeg) {
34237 - ads->ds_ctl0 = 0;
34238 - ads->ds_ctl1 = segLen;
34239 - ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
34240 - ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
34241 - } else {
34242 - ads->ds_ctl0 = 0;
34243 - ads->ds_ctl1 = segLen | AR_TxMore;
34244 - ads->ds_ctl2 = 0;
34245 - ads->ds_ctl3 = 0;
34246 - }
34247 - ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
34248 - ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
34249 - ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
34250 - ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
34251 - ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
34252 -}
34253 -EXPORT_SYMBOL(ath9k_hw_filltxdesc);
34254 -
34255 -void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
34256 -{
34257 - struct ar5416_desc *ads = AR5416DESC(ds);
34258 -
34259 - ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
34260 - ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
34261 - ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
34262 - ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
34263 - ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
34264 -}
34265 -EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
34266 -
34267 -int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds,
34268 - struct ath_tx_status *ts)
34269 -{
34270 - struct ar5416_desc *ads = AR5416DESC(ds);
34271 -
34272 - if ((ads->ds_txstatus9 & AR_TxDone) == 0)
34273 - return -EINPROGRESS;
34274 -
34275 - ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
34276 - ts->ts_tstamp = ads->AR_SendTimestamp;
34277 - ts->ts_status = 0;
34278 - ts->ts_flags = 0;
34279 -
34280 - if (ads->ds_txstatus1 & AR_FrmXmitOK)
34281 - ts->ts_status |= ATH9K_TX_ACKED;
34282 - if (ads->ds_txstatus1 & AR_ExcessiveRetries)
34283 - ts->ts_status |= ATH9K_TXERR_XRETRY;
34284 - if (ads->ds_txstatus1 & AR_Filtered)
34285 - ts->ts_status |= ATH9K_TXERR_FILT;
34286 - if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
34287 - ts->ts_status |= ATH9K_TXERR_FIFO;
34288 - ath9k_hw_updatetxtriglevel(ah, true);
34289 - }
34290 - if (ads->ds_txstatus9 & AR_TxOpExceeded)
34291 - ts->ts_status |= ATH9K_TXERR_XTXOP;
34292 - if (ads->ds_txstatus1 & AR_TxTimerExpired)
34293 - ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
34294 -
34295 - if (ads->ds_txstatus1 & AR_DescCfgErr)
34296 - ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
34297 - if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
34298 - ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
34299 - ath9k_hw_updatetxtriglevel(ah, true);
34300 - }
34301 - if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
34302 - ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
34303 - ath9k_hw_updatetxtriglevel(ah, true);
34304 - }
34305 - if (ads->ds_txstatus0 & AR_TxBaStatus) {
34306 - ts->ts_flags |= ATH9K_TX_BA;
34307 - ts->ba_low = ads->AR_BaBitmapLow;
34308 - ts->ba_high = ads->AR_BaBitmapHigh;
34309 - }
34310 -
34311 - ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
34312 - switch (ts->ts_rateindex) {
34313 - case 0:
34314 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
34315 - break;
34316 - case 1:
34317 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
34318 - break;
34319 - case 2:
34320 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
34321 - break;
34322 - case 3:
34323 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
34324 - break;
34325 - }
34326 -
34327 - ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
34328 - ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
34329 - ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
34330 - ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
34331 - ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
34332 - ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
34333 - ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
34334 - ts->evm0 = ads->AR_TxEVM0;
34335 - ts->evm1 = ads->AR_TxEVM1;
34336 - ts->evm2 = ads->AR_TxEVM2;
34337 - ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
34338 - ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
34339 - ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
34340 - ts->ts_antenna = 0;
34341 -
34342 - return 0;
34343 -}
34344 -EXPORT_SYMBOL(ath9k_hw_txprocdesc);
34345 -
34346 -void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
34347 - u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
34348 - u32 keyIx, enum ath9k_key_type keyType, u32 flags)
34349 -{
34350 - struct ar5416_desc *ads = AR5416DESC(ds);
34351 -
34352 - txPower += ah->txpower_indexoffset;
34353 - if (txPower > 63)
34354 - txPower = 63;
34355 -
34356 - ads->ds_ctl0 = (pktLen & AR_FrameLen)
34357 - | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
34358 - | SM(txPower, AR_XmitPower)
34359 - | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
34360 - | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
34361 - | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
34362 - | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
34363 -
34364 - ads->ds_ctl1 =
34365 - (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
34366 - | SM(type, AR_FrameType)
34367 - | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
34368 - | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
34369 - | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
34370 -
34371 - ads->ds_ctl6 = SM(keyType, AR_EncrType);
34372 -
34373 - if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
34374 - ads->ds_ctl8 = 0;
34375 - ads->ds_ctl9 = 0;
34376 - ads->ds_ctl10 = 0;
34377 - ads->ds_ctl11 = 0;
34378 - }
34379 -}
34380 -EXPORT_SYMBOL(ath9k_hw_set11n_txdesc);
34381 -
34382 -void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
34383 - struct ath_desc *lastds,
34384 - u32 durUpdateEn, u32 rtsctsRate,
34385 - u32 rtsctsDuration,
34386 - struct ath9k_11n_rate_series series[],
34387 - u32 nseries, u32 flags)
34388 -{
34389 - struct ar5416_desc *ads = AR5416DESC(ds);
34390 - struct ar5416_desc *last_ads = AR5416DESC(lastds);
34391 - u32 ds_ctl0;
34392 -
34393 - if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
34394 - ds_ctl0 = ads->ds_ctl0;
34395 -
34396 - if (flags & ATH9K_TXDESC_RTSENA) {
34397 - ds_ctl0 &= ~AR_CTSEnable;
34398 - ds_ctl0 |= AR_RTSEnable;
34399 - } else {
34400 - ds_ctl0 &= ~AR_RTSEnable;
34401 - ds_ctl0 |= AR_CTSEnable;
34402 - }
34403 -
34404 - ads->ds_ctl0 = ds_ctl0;
34405 - } else {
34406 - ads->ds_ctl0 =
34407 - (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
34408 - }
34409 -
34410 - ads->ds_ctl2 = set11nTries(series, 0)
34411 - | set11nTries(series, 1)
34412 - | set11nTries(series, 2)
34413 - | set11nTries(series, 3)
34414 - | (durUpdateEn ? AR_DurUpdateEna : 0)
34415 - | SM(0, AR_BurstDur);
34416 -
34417 - ads->ds_ctl3 = set11nRate(series, 0)
34418 - | set11nRate(series, 1)
34419 - | set11nRate(series, 2)
34420 - | set11nRate(series, 3);
34421 -
34422 - ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
34423 - | set11nPktDurRTSCTS(series, 1);
34424 -
34425 - ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
34426 - | set11nPktDurRTSCTS(series, 3);
34427 -
34428 - ads->ds_ctl7 = set11nRateFlags(series, 0)
34429 - | set11nRateFlags(series, 1)
34430 - | set11nRateFlags(series, 2)
34431 - | set11nRateFlags(series, 3)
34432 - | SM(rtsctsRate, AR_RTSCTSRate);
34433 - last_ads->ds_ctl2 = ads->ds_ctl2;
34434 - last_ads->ds_ctl3 = ads->ds_ctl3;
34435 -}
34436 -EXPORT_SYMBOL(ath9k_hw_set11n_ratescenario);
34437 -
34438 -void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
34439 - u32 aggrLen)
34440 -{
34441 - struct ar5416_desc *ads = AR5416DESC(ds);
34442 -
34443 - ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
34444 - ads->ds_ctl6 &= ~AR_AggrLen;
34445 - ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
34446 -}
34447 -EXPORT_SYMBOL(ath9k_hw_set11n_aggr_first);
34448 -
34449 -void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
34450 - u32 numDelims)
34451 -{
34452 - struct ar5416_desc *ads = AR5416DESC(ds);
34453 - unsigned int ctl6;
34454 -
34455 - ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
34456 -
34457 - ctl6 = ads->ds_ctl6;
34458 - ctl6 &= ~AR_PadDelim;
34459 - ctl6 |= SM(numDelims, AR_PadDelim);
34460 - ads->ds_ctl6 = ctl6;
34461 -}
34462 -EXPORT_SYMBOL(ath9k_hw_set11n_aggr_middle);
34463 -
34464 -void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
34465 -{
34466 - struct ar5416_desc *ads = AR5416DESC(ds);
34467 -
34468 - ads->ds_ctl1 |= AR_IsAggr;
34469 - ads->ds_ctl1 &= ~AR_MoreAggr;
34470 - ads->ds_ctl6 &= ~AR_PadDelim;
34471 -}
34472 -EXPORT_SYMBOL(ath9k_hw_set11n_aggr_last);
34473 -
34474 -void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
34475 -{
34476 - struct ar5416_desc *ads = AR5416DESC(ds);
34477 -
34478 - ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
34479 -}
34480 -EXPORT_SYMBOL(ath9k_hw_clr11n_aggr);
34481 -
34482 -void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
34483 - u32 burstDuration)
34484 -{
34485 - struct ar5416_desc *ads = AR5416DESC(ds);
34486 -
34487 - ads->ds_ctl2 &= ~AR_BurstDur;
34488 - ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
34489 -}
34490 -EXPORT_SYMBOL(ath9k_hw_set11n_burstduration);
34491 -
34492 -void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
34493 - u32 vmf)
34494 -{
34495 - struct ar5416_desc *ads = AR5416DESC(ds);
34496 -
34497 - if (vmf)
34498 - ads->ds_ctl0 |= AR_VirtMoreFrag;
34499 - else
34500 - ads->ds_ctl0 &= ~AR_VirtMoreFrag;
34501 -}
34502 -
34503 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
34504 {
34505 *txqs &= ah->intr_txqs;
34506 @@ -796,6 +521,12 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
34507 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
34508 | AR_D_MISC_BEACON_USE
34509 | AR_D_MISC_POST_FR_BKOFF_DIS);
34510 + /* cwmin and cwmax should be 0 for beacon queue */
34511 + if (AR_SREV_9300_20_OR_LATER(ah)) {
34512 + REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
34513 + | SM(0, AR_D_LCL_IFS_CWMAX)
34514 + | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
34515 + }
34516 break;
34517 case ATH9K_TX_QUEUE_CAB:
34518 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
34519 @@ -832,6 +563,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
34520 AR_D_MISC_POST_FR_BKOFF_DIS);
34521 }
34522
34523 + if (AR_SREV_9300_20_OR_LATER(ah))
34524 + REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
34525 +
34526 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
34527 ah->txok_interrupt_mask |= 1 << q;
34528 else
34529 @@ -999,12 +733,6 @@ void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
34530 }
34531 EXPORT_SYMBOL(ath9k_hw_putrxbuf);
34532
34533 -void ath9k_hw_rxena(struct ath_hw *ah)
34534 -{
34535 - REG_WRITE(ah, AR_CR, AR_CR_RXE);
34536 -}
34537 -EXPORT_SYMBOL(ath9k_hw_rxena);
34538 -
34539 void ath9k_hw_startpcureceive(struct ath_hw *ah)
34540 {
34541 ath9k_enable_mib_counters(ah);
34542 @@ -1023,6 +751,14 @@ void ath9k_hw_stoppcurecv(struct ath_hw *ah)
34543 }
34544 EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
34545
34546 +void ath9k_hw_abortpcurecv(struct ath_hw *ah)
34547 +{
34548 + REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
34549 +
34550 + ath9k_hw_disable_mib_counters(ah);
34551 +}
34552 +EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
34553 +
34554 bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
34555 {
34556 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
34557 @@ -1068,3 +804,140 @@ int ath9k_hw_beaconq_setup(struct ath_hw *ah)
34558 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
34559 }
34560 EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
34561 +
34562 +bool ath9k_hw_intrpend(struct ath_hw *ah)
34563 +{
34564 + u32 host_isr;
34565 +
34566 + if (AR_SREV_9100(ah))
34567 + return true;
34568 +
34569 + host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
34570 + if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
34571 + return true;
34572 +
34573 + host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
34574 + if ((host_isr & AR_INTR_SYNC_DEFAULT)
34575 + && (host_isr != AR_INTR_SPURIOUS))
34576 + return true;
34577 +
34578 + return false;
34579 +}
34580 +EXPORT_SYMBOL(ath9k_hw_intrpend);
34581 +
34582 +enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
34583 + enum ath9k_int ints)
34584 +{
34585 + enum ath9k_int omask = ah->imask;
34586 + u32 mask, mask2;
34587 + struct ath9k_hw_capabilities *pCap = &ah->caps;
34588 + struct ath_common *common = ath9k_hw_common(ah);
34589 +
34590 + ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
34591 +
34592 + if (omask & ATH9K_INT_GLOBAL) {
34593 + ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
34594 + REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
34595 + (void) REG_READ(ah, AR_IER);
34596 + if (!AR_SREV_9100(ah)) {
34597 + REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
34598 + (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
34599 +
34600 + REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
34601 + (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
34602 + }
34603 + }
34604 +
34605 + /* TODO: global int Ref count */
34606 + mask = ints & ATH9K_INT_COMMON;
34607 + mask2 = 0;
34608 +
34609 + if (ints & ATH9K_INT_TX) {
34610 + if (ah->config.tx_intr_mitigation)
34611 + mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
34612 + if (ah->txok_interrupt_mask)
34613 + mask |= AR_IMR_TXOK;
34614 + if (ah->txdesc_interrupt_mask)
34615 + mask |= AR_IMR_TXDESC;
34616 + if (ah->txerr_interrupt_mask)
34617 + mask |= AR_IMR_TXERR;
34618 + if (ah->txeol_interrupt_mask)
34619 + mask |= AR_IMR_TXEOL;
34620 + }
34621 + if (ints & ATH9K_INT_RX) {
34622 + if (AR_SREV_9300_20_OR_LATER(ah)) {
34623 + mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
34624 + if (ah->config.rx_intr_mitigation) {
34625 + mask &= ~AR_IMR_RXOK_LP;
34626 + mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
34627 + } else {
34628 + mask |= AR_IMR_RXOK_LP;
34629 + }
34630 + } else {
34631 + if (ah->config.rx_intr_mitigation)
34632 + mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
34633 + else
34634 + mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
34635 + }
34636 + if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
34637 + mask |= AR_IMR_GENTMR;
34638 + }
34639 +
34640 + if (ints & (ATH9K_INT_BMISC)) {
34641 + mask |= AR_IMR_BCNMISC;
34642 + if (ints & ATH9K_INT_TIM)
34643 + mask2 |= AR_IMR_S2_TIM;
34644 + if (ints & ATH9K_INT_DTIM)
34645 + mask2 |= AR_IMR_S2_DTIM;
34646 + if (ints & ATH9K_INT_DTIMSYNC)
34647 + mask2 |= AR_IMR_S2_DTIMSYNC;
34648 + if (ints & ATH9K_INT_CABEND)
34649 + mask2 |= AR_IMR_S2_CABEND;
34650 + if (ints & ATH9K_INT_TSFOOR)
34651 + mask2 |= AR_IMR_S2_TSFOOR;
34652 + }
34653 +
34654 + if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
34655 + mask |= AR_IMR_BCNMISC;
34656 + if (ints & ATH9K_INT_GTT)
34657 + mask2 |= AR_IMR_S2_GTT;
34658 + if (ints & ATH9K_INT_CST)
34659 + mask2 |= AR_IMR_S2_CST;
34660 + }
34661 +
34662 + ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
34663 + REG_WRITE(ah, AR_IMR, mask);
34664 + ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
34665 + AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
34666 + AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
34667 + ah->imrs2_reg |= mask2;
34668 + REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
34669 +
34670 + if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
34671 + if (ints & ATH9K_INT_TIM_TIMER)
34672 + REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
34673 + else
34674 + REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
34675 + }
34676 +
34677 + if (ints & ATH9K_INT_GLOBAL) {
34678 + ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
34679 + REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
34680 + if (!AR_SREV_9100(ah)) {
34681 + REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
34682 + AR_INTR_MAC_IRQ);
34683 + REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
34684 +
34685 +
34686 + REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
34687 + AR_INTR_SYNC_DEFAULT);
34688 + REG_WRITE(ah, AR_INTR_SYNC_MASK,
34689 + AR_INTR_SYNC_DEFAULT);
34690 + }
34691 + ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
34692 + REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
34693 + }
34694 +
34695 + return omask;
34696 +}
34697 +EXPORT_SYMBOL(ath9k_hw_set_interrupts);
34698 diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
34699 index 68dbd7a..bf27dde 100644
34700 --- a/drivers/net/wireless/ath/ath9k/mac.h
34701 +++ b/drivers/net/wireless/ath/ath9k/mac.h
34702 @@ -86,7 +86,6 @@
34703 #define ATH9K_TX_DESC_CFG_ERR 0x04
34704 #define ATH9K_TX_DATA_UNDERRUN 0x08
34705 #define ATH9K_TX_DELIM_UNDERRUN 0x10
34706 -#define ATH9K_TX_SW_ABORTED 0x40
34707 #define ATH9K_TX_SW_FILTERED 0x80
34708
34709 /* 64 bytes */
34710 @@ -117,7 +116,10 @@ struct ath_tx_status {
34711 int8_t ts_rssi_ext0;
34712 int8_t ts_rssi_ext1;
34713 int8_t ts_rssi_ext2;
34714 - u8 pad[3];
34715 + u8 qid;
34716 + u16 desc_id;
34717 + u8 tid;
34718 + u8 pad[2];
34719 u32 ba_low;
34720 u32 ba_high;
34721 u32 evm0;
34722 @@ -148,6 +150,8 @@ struct ath_rx_status {
34723 u32 evm0;
34724 u32 evm1;
34725 u32 evm2;
34726 + u32 evm3;
34727 + u32 evm4;
34728 };
34729
34730 struct ath_htc_rx_status {
34731 @@ -259,7 +263,8 @@ struct ath_desc {
34732 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
34733 #define ATH9K_TXDESC_VMF 0x0100
34734 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
34735 -#define ATH9K_TXDESC_CAB 0x0400
34736 +#define ATH9K_TXDESC_LOWRXCHAIN 0x0400
34737 +#define ATH9K_TXDESC_LDPC 0x00010000
34738
34739 #define ATH9K_RXDESC_INTREQ 0x0020
34740
34741 @@ -353,7 +358,8 @@ struct ar5416_desc {
34742 #define AR_DestIdxValid 0x40000000
34743 #define AR_CTSEnable 0x80000000
34744
34745 -#define AR_BufLen 0x00000fff
34746 +#define AR_BufLen AR_SREV_9300_20_OR_LATER(ah) ? 0x0fff0000 : \
34747 + 0x00000fff
34748 #define AR_TxMore 0x00001000
34749 #define AR_DestIdx 0x000fe000
34750 #define AR_DestIdx_S 13
34751 @@ -410,6 +416,7 @@ struct ar5416_desc {
34752 #define AR_EncrType 0x0c000000
34753 #define AR_EncrType_S 26
34754 #define AR_TxCtlRsvd61 0xf0000000
34755 +#define AR_LDPC 0x80000000
34756
34757 #define AR_2040_0 0x00000001
34758 #define AR_GI0 0x00000002
34759 @@ -493,7 +500,6 @@ struct ar5416_desc {
34760
34761 #define AR_RxCTLRsvd00 0xffffffff
34762
34763 -#define AR_BufLen 0x00000fff
34764 #define AR_RxCtlRsvd00 0x00001000
34765 #define AR_RxIntrReq 0x00002000
34766 #define AR_RxCtlRsvd01 0xffffc000
34767 @@ -689,31 +695,6 @@ void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
34768 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
34769 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
34770 bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
34771 -void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
34772 - u32 segLen, bool firstSeg,
34773 - bool lastSeg, const struct ath_desc *ds0);
34774 -void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds);
34775 -int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds,
34776 - struct ath_tx_status *ts);
34777 -void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
34778 - u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
34779 - u32 keyIx, enum ath9k_key_type keyType, u32 flags);
34780 -void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
34781 - struct ath_desc *lastds,
34782 - u32 durUpdateEn, u32 rtsctsRate,
34783 - u32 rtsctsDuration,
34784 - struct ath9k_11n_rate_series series[],
34785 - u32 nseries, u32 flags);
34786 -void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
34787 - u32 aggrLen);
34788 -void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
34789 - u32 numDelims);
34790 -void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds);
34791 -void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds);
34792 -void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
34793 - u32 burstDuration);
34794 -void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
34795 - u32 vmf);
34796 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
34797 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
34798 const struct ath9k_tx_queue_info *qinfo);
34799 @@ -729,10 +710,17 @@ void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
34800 u32 size, u32 flags);
34801 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
34802 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
34803 -void ath9k_hw_rxena(struct ath_hw *ah);
34804 void ath9k_hw_startpcureceive(struct ath_hw *ah);
34805 void ath9k_hw_stoppcurecv(struct ath_hw *ah);
34806 +void ath9k_hw_abortpcurecv(struct ath_hw *ah);
34807 bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
34808 int ath9k_hw_beaconq_setup(struct ath_hw *ah);
34809
34810 +/* Interrupt Handling */
34811 +bool ath9k_hw_intrpend(struct ath_hw *ah);
34812 +enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
34813 + enum ath9k_int ints);
34814 +
34815 +void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
34816 +
34817 #endif /* MAC_H */
34818 diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
34819 index f7ef114..dd2896f 100644
34820 --- a/drivers/net/wireless/ath/ath9k/main.c
34821 +++ b/drivers/net/wireless/ath/ath9k/main.c
34822 @@ -401,6 +401,7 @@ void ath9k_tasklet(unsigned long data)
34823 struct ath_common *common = ath9k_hw_common(ah);
34824
34825 u32 status = sc->intrstatus;
34826 + u32 rxmask;
34827
34828 ath9k_ps_wakeup(sc);
34829
34830 @@ -410,14 +411,30 @@ void ath9k_tasklet(unsigned long data)
34831 return;
34832 }
34833
34834 - if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
34835 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
34836 + rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
34837 + ATH9K_INT_RXORN);
34838 + else
34839 + rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
34840 +
34841 + if (status & rxmask) {
34842 spin_lock_bh(&sc->rx.rxflushlock);
34843 - ath_rx_tasklet(sc, 0);
34844 +
34845 + /* Check for high priority Rx first */
34846 + if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
34847 + (status & ATH9K_INT_RXHP))
34848 + ath_rx_tasklet(sc, 0, true);
34849 +
34850 + ath_rx_tasklet(sc, 0, false);
34851 spin_unlock_bh(&sc->rx.rxflushlock);
34852 }
34853
34854 - if (status & ATH9K_INT_TX)
34855 - ath_tx_tasklet(sc);
34856 + if (status & ATH9K_INT_TX) {
34857 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
34858 + ath_tx_edma_tasklet(sc);
34859 + else
34860 + ath_tx_tasklet(sc);
34861 + }
34862
34863 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
34864 /*
34865 @@ -445,6 +462,8 @@ irqreturn_t ath_isr(int irq, void *dev)
34866 ATH9K_INT_RXORN | \
34867 ATH9K_INT_RXEOL | \
34868 ATH9K_INT_RX | \
34869 + ATH9K_INT_RXLP | \
34870 + ATH9K_INT_RXHP | \
34871 ATH9K_INT_TX | \
34872 ATH9K_INT_BMISS | \
34873 ATH9K_INT_CST | \
34874 @@ -496,7 +515,8 @@ irqreturn_t ath_isr(int irq, void *dev)
34875 * If a FATAL or RXORN interrupt is received, we have to reset the
34876 * chip immediately.
34877 */
34878 - if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
34879 + if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
34880 + !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
34881 goto chip_reset;
34882
34883 if (status & ATH9K_INT_SWBA)
34884 @@ -505,6 +525,13 @@ irqreturn_t ath_isr(int irq, void *dev)
34885 if (status & ATH9K_INT_TXURN)
34886 ath9k_hw_updatetxtriglevel(ah, true);
34887
34888 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
34889 + if (status & ATH9K_INT_RXEOL) {
34890 + ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
34891 + ath9k_hw_set_interrupts(ah, ah->imask);
34892 + }
34893 + }
34894 +
34895 if (status & ATH9K_INT_MIB) {
34896 /*
34897 * Disable interrupts until we service the MIB
34898 @@ -537,6 +564,18 @@ chip_reset:
34899 if (sched) {
34900 /* turn off every interrupt except SWBA */
34901 ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
34902 +
34903 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
34904 + ath9k_hw_set_interrupts(ah,
34905 + ah->imask & (ATH9K_INT_GLOBAL |
34906 + ATH9K_INT_RXEOL |
34907 + ATH9K_INT_RXORN |
34908 + ATH9K_INT_SWBA));
34909 + else
34910 + /* turn off every interrupt except SWBA */
34911 + ath9k_hw_set_interrupts(ah,
34912 + (ah->imask & ATH9K_INT_SWBA));
34913 +
34914 tasklet_schedule(&sc->intr_tq);
34915 }
34916
34917 @@ -1162,9 +1201,14 @@ static int ath9k_start(struct ieee80211_hw *hw)
34918 }
34919
34920 /* Setup our intr mask. */
34921 - ah->imask = ATH9K_INT_RX | ATH9K_INT_TX
34922 - | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
34923 - | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
34924 + ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
34925 + ATH9K_INT_RXORN | ATH9K_INT_FATAL |
34926 + ATH9K_INT_GLOBAL;
34927 +
34928 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
34929 + ah->imask |= ATH9K_INT_RXHP | ATH9K_INT_RXLP;
34930 + else
34931 + ah->imask |= ATH9K_INT_RX;
34932
34933 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
34934 ah->imask |= ATH9K_INT_GTT;
34935 diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
34936 index 1ec836c..257b10b 100644
34937 --- a/drivers/net/wireless/ath/ath9k/pci.c
34938 +++ b/drivers/net/wireless/ath/ath9k/pci.c
34939 @@ -28,6 +28,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
34940 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
34941 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
34942 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
34943 + { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
34944 { 0 }
34945 };
34946
34947 diff --git a/drivers/net/wireless/ath/ath9k/phy.c b/drivers/net/wireless/ath/ath9k/phy.c
34948 deleted file mode 100644
34949 index c3b5939..0000000
34950 --- a/drivers/net/wireless/ath/ath9k/phy.c
34951 +++ /dev/null
34952 @@ -1,976 +0,0 @@
34953 -/*
34954 - * Copyright (c) 2008-2009 Atheros Communications Inc.
34955 - *
34956 - * Permission to use, copy, modify, and/or distribute this software for any
34957 - * purpose with or without fee is hereby granted, provided that the above
34958 - * copyright notice and this permission notice appear in all copies.
34959 - *
34960 - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
34961 - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
34962 - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
34963 - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
34964 - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
34965 - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
34966 - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
34967 - */
34968 -
34969 -/**
34970 - * DOC: Programming Atheros 802.11n analog front end radios
34971 - *
34972 - * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
34973 - * devices have either an external AR2133 analog front end radio for single
34974 - * band 2.4 GHz communication or an AR5133 analog front end radio for dual
34975 - * band 2.4 GHz / 5 GHz communication.
34976 - *
34977 - * All devices after the AR5416 and AR5418 family starting with the AR9280
34978 - * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
34979 - * into a single-chip and require less programming.
34980 - *
34981 - * The following single-chips exist with a respective embedded radio:
34982 - *
34983 - * AR9280 - 11n dual-band 2x2 MIMO for PCIe
34984 - * AR9281 - 11n single-band 1x2 MIMO for PCIe
34985 - * AR9285 - 11n single-band 1x1 for PCIe
34986 - * AR9287 - 11n single-band 2x2 MIMO for PCIe
34987 - *
34988 - * AR9220 - 11n dual-band 2x2 MIMO for PCI
34989 - * AR9223 - 11n single-band 2x2 MIMO for PCI
34990 - *
34991 - * AR9287 - 11n single-band 1x1 MIMO for USB
34992 - */
34993 -
34994 -#include "hw.h"
34995 -
34996 -/**
34997 - * ath9k_hw_write_regs - ??
34998 - *
34999 - * @ah: atheros hardware structure
35000 - * @freqIndex:
35001 - * @regWrites:
35002 - *
35003 - * Used for both the chipsets with an external AR2133/AR5133 radios and
35004 - * single-chip devices.
35005 - */
35006 -void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites)
35007 -{
35008 - REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
35009 -}
35010 -
35011 -/**
35012 - * ath9k_hw_ar9280_set_channel - set channel on single-chip device
35013 - * @ah: atheros hardware structure
35014 - * @chan:
35015 - *
35016 - * This is the function to change channel on single-chip devices, that is
35017 - * all devices after ar9280.
35018 - *
35019 - * This function takes the channel value in MHz and sets
35020 - * hardware channel value. Assumes writes have been enabled to analog bus.
35021 - *
35022 - * Actual Expression,
35023 - *
35024 - * For 2GHz channel,
35025 - * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
35026 - * (freq_ref = 40MHz)
35027 - *
35028 - * For 5GHz channel,
35029 - * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
35030 - * (freq_ref = 40MHz/(24>>amodeRefSel))
35031 - */
35032 -int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
35033 -{
35034 - u16 bMode, fracMode, aModeRefSel = 0;
35035 - u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
35036 - struct chan_centers centers;
35037 - u32 refDivA = 24;
35038 -
35039 - ath9k_hw_get_channel_centers(ah, chan, &centers);
35040 - freq = centers.synth_center;
35041 -
35042 - reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
35043 - reg32 &= 0xc0000000;
35044 -
35045 - if (freq < 4800) { /* 2 GHz, fractional mode */
35046 - u32 txctl;
35047 - int regWrites = 0;
35048 -
35049 - bMode = 1;
35050 - fracMode = 1;
35051 - aModeRefSel = 0;
35052 - channelSel = (freq * 0x10000) / 15;
35053 -
35054 - if (AR_SREV_9287_11_OR_LATER(ah)) {
35055 - if (freq == 2484) {
35056 - /* Enable channel spreading for channel 14 */
35057 - REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
35058 - 1, regWrites);
35059 - } else {
35060 - REG_WRITE_ARRAY(&ah->iniCckfirNormal,
35061 - 1, regWrites);
35062 - }
35063 - } else {
35064 - txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
35065 - if (freq == 2484) {
35066 - /* Enable channel spreading for channel 14 */
35067 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
35068 - txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
35069 - } else {
35070 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
35071 - txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
35072 - }
35073 - }
35074 - } else {
35075 - bMode = 0;
35076 - fracMode = 0;
35077 -
35078 - switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
35079 - case 0:
35080 - if ((freq % 20) == 0) {
35081 - aModeRefSel = 3;
35082 - } else if ((freq % 10) == 0) {
35083 - aModeRefSel = 2;
35084 - }
35085 - if (aModeRefSel)
35086 - break;
35087 - case 1:
35088 - default:
35089 - aModeRefSel = 0;
35090 - /*
35091 - * Enable 2G (fractional) mode for channels
35092 - * which are 5MHz spaced.
35093 - */
35094 - fracMode = 1;
35095 - refDivA = 1;
35096 - channelSel = (freq * 0x8000) / 15;
35097 -
35098 - /* RefDivA setting */
35099 - REG_RMW_FIELD(ah, AR_AN_SYNTH9,
35100 - AR_AN_SYNTH9_REFDIVA, refDivA);
35101 -
35102 - }
35103 -
35104 - if (!fracMode) {
35105 - ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
35106 - channelSel = ndiv & 0x1ff;
35107 - channelFrac = (ndiv & 0xfffffe00) * 2;
35108 - channelSel = (channelSel << 17) | channelFrac;
35109 - }
35110 - }
35111 -
35112 - reg32 = reg32 |
35113 - (bMode << 29) |
35114 - (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
35115 -
35116 - REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
35117 -
35118 - ah->curchan = chan;
35119 - ah->curchan_rad_index = -1;
35120 -
35121 - return 0;
35122 -}
35123 -
35124 -/**
35125 - * ath9k_hw_9280_spur_mitigate - convert baseband spur frequency
35126 - * @ah: atheros hardware structure
35127 - * @chan:
35128 - *
35129 - * For single-chip solutions. Converts to baseband spur frequency given the
35130 - * input channel frequency and compute register settings below.
35131 - */
35132 -void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
35133 -{
35134 - int bb_spur = AR_NO_SPUR;
35135 - int freq;
35136 - int bin, cur_bin;
35137 - int bb_spur_off, spur_subchannel_sd;
35138 - int spur_freq_sd;
35139 - int spur_delta_phase;
35140 - int denominator;
35141 - int upper, lower, cur_vit_mask;
35142 - int tmp, newVal;
35143 - int i;
35144 - int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
35145 - AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
35146 - };
35147 - int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
35148 - AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
35149 - };
35150 - int inc[4] = { 0, 100, 0, 0 };
35151 - struct chan_centers centers;
35152 -
35153 - int8_t mask_m[123];
35154 - int8_t mask_p[123];
35155 - int8_t mask_amt;
35156 - int tmp_mask;
35157 - int cur_bb_spur;
35158 - bool is2GHz = IS_CHAN_2GHZ(chan);
35159 -
35160 - memset(&mask_m, 0, sizeof(int8_t) * 123);
35161 - memset(&mask_p, 0, sizeof(int8_t) * 123);
35162 -
35163 - ath9k_hw_get_channel_centers(ah, chan, &centers);
35164 - freq = centers.synth_center;
35165 -
35166 - ah->config.spurmode = SPUR_ENABLE_EEPROM;
35167 - for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
35168 - cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
35169 -
35170 - if (is2GHz)
35171 - cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
35172 - else
35173 - cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
35174 -
35175 - if (AR_NO_SPUR == cur_bb_spur)
35176 - break;
35177 - cur_bb_spur = cur_bb_spur - freq;
35178 -
35179 - if (IS_CHAN_HT40(chan)) {
35180 - if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
35181 - (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
35182 - bb_spur = cur_bb_spur;
35183 - break;
35184 - }
35185 - } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
35186 - (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
35187 - bb_spur = cur_bb_spur;
35188 - break;
35189 - }
35190 - }
35191 -
35192 - if (AR_NO_SPUR == bb_spur) {
35193 - REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
35194 - AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
35195 - return;
35196 - } else {
35197 - REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
35198 - AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
35199 - }
35200 -
35201 - bin = bb_spur * 320;
35202 -
35203 - tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
35204 -
35205 - newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
35206 - AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
35207 - AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
35208 - AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
35209 - REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
35210 -
35211 - newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
35212 - AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
35213 - AR_PHY_SPUR_REG_MASK_RATE_SELECT |
35214 - AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
35215 - SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
35216 - REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
35217 -
35218 - if (IS_CHAN_HT40(chan)) {
35219 - if (bb_spur < 0) {
35220 - spur_subchannel_sd = 1;
35221 - bb_spur_off = bb_spur + 10;
35222 - } else {
35223 - spur_subchannel_sd = 0;
35224 - bb_spur_off = bb_spur - 10;
35225 - }
35226 - } else {
35227 - spur_subchannel_sd = 0;
35228 - bb_spur_off = bb_spur;
35229 - }
35230 -
35231 - if (IS_CHAN_HT40(chan))
35232 - spur_delta_phase =
35233 - ((bb_spur * 262144) /
35234 - 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
35235 - else
35236 - spur_delta_phase =
35237 - ((bb_spur * 524288) /
35238 - 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
35239 -
35240 - denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
35241 - spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
35242 -
35243 - newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
35244 - SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
35245 - SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
35246 - REG_WRITE(ah, AR_PHY_TIMING11, newVal);
35247 -
35248 - newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
35249 - REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
35250 -
35251 - cur_bin = -6000;
35252 - upper = bin + 100;
35253 - lower = bin - 100;
35254 -
35255 - for (i = 0; i < 4; i++) {
35256 - int pilot_mask = 0;
35257 - int chan_mask = 0;
35258 - int bp = 0;
35259 - for (bp = 0; bp < 30; bp++) {
35260 - if ((cur_bin > lower) && (cur_bin < upper)) {
35261 - pilot_mask = pilot_mask | 0x1 << bp;
35262 - chan_mask = chan_mask | 0x1 << bp;
35263 - }
35264 - cur_bin += 100;
35265 - }
35266 - cur_bin += inc[i];
35267 - REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
35268 - REG_WRITE(ah, chan_mask_reg[i], chan_mask);
35269 - }
35270 -
35271 - cur_vit_mask = 6100;
35272 - upper = bin + 120;
35273 - lower = bin - 120;
35274 -
35275 - for (i = 0; i < 123; i++) {
35276 - if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
35277 -
35278 - /* workaround for gcc bug #37014 */
35279 - volatile int tmp_v = abs(cur_vit_mask - bin);
35280 -
35281 - if (tmp_v < 75)
35282 - mask_amt = 1;
35283 - else
35284 - mask_amt = 0;
35285 - if (cur_vit_mask < 0)
35286 - mask_m[abs(cur_vit_mask / 100)] = mask_amt;
35287 - else
35288 - mask_p[cur_vit_mask / 100] = mask_amt;
35289 - }
35290 - cur_vit_mask -= 100;
35291 - }
35292 -
35293 - tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
35294 - | (mask_m[48] << 26) | (mask_m[49] << 24)
35295 - | (mask_m[50] << 22) | (mask_m[51] << 20)
35296 - | (mask_m[52] << 18) | (mask_m[53] << 16)
35297 - | (mask_m[54] << 14) | (mask_m[55] << 12)
35298 - | (mask_m[56] << 10) | (mask_m[57] << 8)
35299 - | (mask_m[58] << 6) | (mask_m[59] << 4)
35300 - | (mask_m[60] << 2) | (mask_m[61] << 0);
35301 - REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
35302 - REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
35303 -
35304 - tmp_mask = (mask_m[31] << 28)
35305 - | (mask_m[32] << 26) | (mask_m[33] << 24)
35306 - | (mask_m[34] << 22) | (mask_m[35] << 20)
35307 - | (mask_m[36] << 18) | (mask_m[37] << 16)
35308 - | (mask_m[48] << 14) | (mask_m[39] << 12)
35309 - | (mask_m[40] << 10) | (mask_m[41] << 8)
35310 - | (mask_m[42] << 6) | (mask_m[43] << 4)
35311 - | (mask_m[44] << 2) | (mask_m[45] << 0);
35312 - REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
35313 - REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
35314 -
35315 - tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
35316 - | (mask_m[18] << 26) | (mask_m[18] << 24)
35317 - | (mask_m[20] << 22) | (mask_m[20] << 20)
35318 - | (mask_m[22] << 18) | (mask_m[22] << 16)
35319 - | (mask_m[24] << 14) | (mask_m[24] << 12)
35320 - | (mask_m[25] << 10) | (mask_m[26] << 8)
35321 - | (mask_m[27] << 6) | (mask_m[28] << 4)
35322 - | (mask_m[29] << 2) | (mask_m[30] << 0);
35323 - REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
35324 - REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
35325 -
35326 - tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
35327 - | (mask_m[2] << 26) | (mask_m[3] << 24)
35328 - | (mask_m[4] << 22) | (mask_m[5] << 20)
35329 - | (mask_m[6] << 18) | (mask_m[7] << 16)
35330 - | (mask_m[8] << 14) | (mask_m[9] << 12)
35331 - | (mask_m[10] << 10) | (mask_m[11] << 8)
35332 - | (mask_m[12] << 6) | (mask_m[13] << 4)
35333 - | (mask_m[14] << 2) | (mask_m[15] << 0);
35334 - REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
35335 - REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
35336 -
35337 - tmp_mask = (mask_p[15] << 28)
35338 - | (mask_p[14] << 26) | (mask_p[13] << 24)
35339 - | (mask_p[12] << 22) | (mask_p[11] << 20)
35340 - | (mask_p[10] << 18) | (mask_p[9] << 16)
35341 - | (mask_p[8] << 14) | (mask_p[7] << 12)
35342 - | (mask_p[6] << 10) | (mask_p[5] << 8)
35343 - | (mask_p[4] << 6) | (mask_p[3] << 4)
35344 - | (mask_p[2] << 2) | (mask_p[1] << 0);
35345 - REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
35346 - REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
35347 -
35348 - tmp_mask = (mask_p[30] << 28)
35349 - | (mask_p[29] << 26) | (mask_p[28] << 24)
35350 - | (mask_p[27] << 22) | (mask_p[26] << 20)
35351 - | (mask_p[25] << 18) | (mask_p[24] << 16)
35352 - | (mask_p[23] << 14) | (mask_p[22] << 12)
35353 - | (mask_p[21] << 10) | (mask_p[20] << 8)
35354 - | (mask_p[19] << 6) | (mask_p[18] << 4)
35355 - | (mask_p[17] << 2) | (mask_p[16] << 0);
35356 - REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
35357 - REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
35358 -
35359 - tmp_mask = (mask_p[45] << 28)
35360 - | (mask_p[44] << 26) | (mask_p[43] << 24)
35361 - | (mask_p[42] << 22) | (mask_p[41] << 20)
35362 - | (mask_p[40] << 18) | (mask_p[39] << 16)
35363 - | (mask_p[38] << 14) | (mask_p[37] << 12)
35364 - | (mask_p[36] << 10) | (mask_p[35] << 8)
35365 - | (mask_p[34] << 6) | (mask_p[33] << 4)
35366 - | (mask_p[32] << 2) | (mask_p[31] << 0);
35367 - REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
35368 - REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
35369 -
35370 - tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
35371 - | (mask_p[59] << 26) | (mask_p[58] << 24)
35372 - | (mask_p[57] << 22) | (mask_p[56] << 20)
35373 - | (mask_p[55] << 18) | (mask_p[54] << 16)
35374 - | (mask_p[53] << 14) | (mask_p[52] << 12)
35375 - | (mask_p[51] << 10) | (mask_p[50] << 8)
35376 - | (mask_p[49] << 6) | (mask_p[48] << 4)
35377 - | (mask_p[47] << 2) | (mask_p[46] << 0);
35378 - REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
35379 - REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
35380 -}
35381 -
35382 -/* All code below is for non single-chip solutions */
35383 -
35384 -/**
35385 - * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters
35386 - * @rfbuf:
35387 - * @reg32:
35388 - * @numBits:
35389 - * @firstBit:
35390 - * @column:
35391 - *
35392 - * Performs analog "swizzling" of parameters into their location.
35393 - * Used on external AR2133/AR5133 radios.
35394 - */
35395 -static void ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
35396 - u32 numBits, u32 firstBit,
35397 - u32 column)
35398 -{
35399 - u32 tmp32, mask, arrayEntry, lastBit;
35400 - int32_t bitPosition, bitsLeft;
35401 -
35402 - tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
35403 - arrayEntry = (firstBit - 1) / 8;
35404 - bitPosition = (firstBit - 1) % 8;
35405 - bitsLeft = numBits;
35406 - while (bitsLeft > 0) {
35407 - lastBit = (bitPosition + bitsLeft > 8) ?
35408 - 8 : bitPosition + bitsLeft;
35409 - mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
35410 - (column * 8);
35411 - rfBuf[arrayEntry] &= ~mask;
35412 - rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
35413 - (column * 8)) & mask;
35414 - bitsLeft -= 8 - bitPosition;
35415 - tmp32 = tmp32 >> (8 - bitPosition);
35416 - bitPosition = 0;
35417 - arrayEntry++;
35418 - }
35419 -}
35420 -
35421 -/*
35422 - * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
35423 - * rf_pwd_icsyndiv.
35424 - *
35425 - * Theoretical Rules:
35426 - * if 2 GHz band
35427 - * if forceBiasAuto
35428 - * if synth_freq < 2412
35429 - * bias = 0
35430 - * else if 2412 <= synth_freq <= 2422
35431 - * bias = 1
35432 - * else // synth_freq > 2422
35433 - * bias = 2
35434 - * else if forceBias > 0
35435 - * bias = forceBias & 7
35436 - * else
35437 - * no change, use value from ini file
35438 - * else
35439 - * no change, invalid band
35440 - *
35441 - * 1st Mod:
35442 - * 2422 also uses value of 2
35443 - * <approved>
35444 - *
35445 - * 2nd Mod:
35446 - * Less than 2412 uses value of 0, 2412 and above uses value of 2
35447 - */
35448 -static void ath9k_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
35449 -{
35450 - struct ath_common *common = ath9k_hw_common(ah);
35451 - u32 tmp_reg;
35452 - int reg_writes = 0;
35453 - u32 new_bias = 0;
35454 -
35455 - if (!AR_SREV_5416(ah) || synth_freq >= 3000) {
35456 - return;
35457 - }
35458 -
35459 - BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
35460 -
35461 - if (synth_freq < 2412)
35462 - new_bias = 0;
35463 - else if (synth_freq < 2422)
35464 - new_bias = 1;
35465 - else
35466 - new_bias = 2;
35467 -
35468 - /* pre-reverse this field */
35469 - tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
35470 -
35471 - ath_print(common, ATH_DBG_CONFIG,
35472 - "Force rf_pwd_icsyndiv to %1d on %4d\n",
35473 - new_bias, synth_freq);
35474 -
35475 - /* swizzle rf_pwd_icsyndiv */
35476 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
35477 -
35478 - /* write Bank 6 with new params */
35479 - REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
35480 -}
35481 -
35482 -/**
35483 - * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
35484 - * @ah: atheros hardware stucture
35485 - * @chan:
35486 - *
35487 - * For the external AR2133/AR5133 radios, takes the MHz channel value and set
35488 - * the channel value. Assumes writes enabled to analog bus and bank6 register
35489 - * cache in ah->analogBank6Data.
35490 - */
35491 -int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
35492 -{
35493 - struct ath_common *common = ath9k_hw_common(ah);
35494 - u32 channelSel = 0;
35495 - u32 bModeSynth = 0;
35496 - u32 aModeRefSel = 0;
35497 - u32 reg32 = 0;
35498 - u16 freq;
35499 - struct chan_centers centers;
35500 -
35501 - ath9k_hw_get_channel_centers(ah, chan, &centers);
35502 - freq = centers.synth_center;
35503 -
35504 - if (freq < 4800) {
35505 - u32 txctl;
35506 -
35507 - if (((freq - 2192) % 5) == 0) {
35508 - channelSel = ((freq - 672) * 2 - 3040) / 10;
35509 - bModeSynth = 0;
35510 - } else if (((freq - 2224) % 5) == 0) {
35511 - channelSel = ((freq - 704) * 2 - 3040) / 10;
35512 - bModeSynth = 1;
35513 - } else {
35514 - ath_print(common, ATH_DBG_FATAL,
35515 - "Invalid channel %u MHz\n", freq);
35516 - return -EINVAL;
35517 - }
35518 -
35519 - channelSel = (channelSel << 2) & 0xff;
35520 - channelSel = ath9k_hw_reverse_bits(channelSel, 8);
35521 -
35522 - txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
35523 - if (freq == 2484) {
35524 -
35525 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
35526 - txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
35527 - } else {
35528 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
35529 - txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
35530 - }
35531 -
35532 - } else if ((freq % 20) == 0 && freq >= 5120) {
35533 - channelSel =
35534 - ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
35535 - aModeRefSel = ath9k_hw_reverse_bits(1, 2);
35536 - } else if ((freq % 10) == 0) {
35537 - channelSel =
35538 - ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
35539 - if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
35540 - aModeRefSel = ath9k_hw_reverse_bits(2, 2);
35541 - else
35542 - aModeRefSel = ath9k_hw_reverse_bits(1, 2);
35543 - } else if ((freq % 5) == 0) {
35544 - channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
35545 - aModeRefSel = ath9k_hw_reverse_bits(1, 2);
35546 - } else {
35547 - ath_print(common, ATH_DBG_FATAL,
35548 - "Invalid channel %u MHz\n", freq);
35549 - return -EINVAL;
35550 - }
35551 -
35552 - ath9k_hw_force_bias(ah, freq);
35553 -
35554 - reg32 =
35555 - (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
35556 - (1 << 5) | 0x1;
35557 -
35558 - REG_WRITE(ah, AR_PHY(0x37), reg32);
35559 -
35560 - ah->curchan = chan;
35561 - ah->curchan_rad_index = -1;
35562 -
35563 - return 0;
35564 -}
35565 -
35566 -/**
35567 - * ath9k_hw_spur_mitigate - convert baseband spur frequency for external radios
35568 - * @ah: atheros hardware structure
35569 - * @chan:
35570 - *
35571 - * For non single-chip solutions. Converts to baseband spur frequency given the
35572 - * input channel frequency and compute register settings below.
35573 - */
35574 -void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
35575 -{
35576 - int bb_spur = AR_NO_SPUR;
35577 - int bin, cur_bin;
35578 - int spur_freq_sd;
35579 - int spur_delta_phase;
35580 - int denominator;
35581 - int upper, lower, cur_vit_mask;
35582 - int tmp, new;
35583 - int i;
35584 - int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
35585 - AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
35586 - };
35587 - int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
35588 - AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
35589 - };
35590 - int inc[4] = { 0, 100, 0, 0 };
35591 -
35592 - int8_t mask_m[123];
35593 - int8_t mask_p[123];
35594 - int8_t mask_amt;
35595 - int tmp_mask;
35596 - int cur_bb_spur;
35597 - bool is2GHz = IS_CHAN_2GHZ(chan);
35598 -
35599 - memset(&mask_m, 0, sizeof(int8_t) * 123);
35600 - memset(&mask_p, 0, sizeof(int8_t) * 123);
35601 -
35602 - for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
35603 - cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
35604 - if (AR_NO_SPUR == cur_bb_spur)
35605 - break;
35606 - cur_bb_spur = cur_bb_spur - (chan->channel * 10);
35607 - if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
35608 - bb_spur = cur_bb_spur;
35609 - break;
35610 - }
35611 - }
35612 -
35613 - if (AR_NO_SPUR == bb_spur)
35614 - return;
35615 -
35616 - bin = bb_spur * 32;
35617 -
35618 - tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
35619 - new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
35620 - AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
35621 - AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
35622 - AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
35623 -
35624 - REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
35625 -
35626 - new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
35627 - AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
35628 - AR_PHY_SPUR_REG_MASK_RATE_SELECT |
35629 - AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
35630 - SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
35631 - REG_WRITE(ah, AR_PHY_SPUR_REG, new);
35632 -
35633 - spur_delta_phase = ((bb_spur * 524288) / 100) &
35634 - AR_PHY_TIMING11_SPUR_DELTA_PHASE;
35635 -
35636 - denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
35637 - spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
35638 -
35639 - new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
35640 - SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
35641 - SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
35642 - REG_WRITE(ah, AR_PHY_TIMING11, new);
35643 -
35644 - cur_bin = -6000;
35645 - upper = bin + 100;
35646 - lower = bin - 100;
35647 -
35648 - for (i = 0; i < 4; i++) {
35649 - int pilot_mask = 0;
35650 - int chan_mask = 0;
35651 - int bp = 0;
35652 - for (bp = 0; bp < 30; bp++) {
35653 - if ((cur_bin > lower) && (cur_bin < upper)) {
35654 - pilot_mask = pilot_mask | 0x1 << bp;
35655 - chan_mask = chan_mask | 0x1 << bp;
35656 - }
35657 - cur_bin += 100;
35658 - }
35659 - cur_bin += inc[i];
35660 - REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
35661 - REG_WRITE(ah, chan_mask_reg[i], chan_mask);
35662 - }
35663 -
35664 - cur_vit_mask = 6100;
35665 - upper = bin + 120;
35666 - lower = bin - 120;
35667 -
35668 - for (i = 0; i < 123; i++) {
35669 - if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
35670 -
35671 - /* workaround for gcc bug #37014 */
35672 - volatile int tmp_v = abs(cur_vit_mask - bin);
35673 -
35674 - if (tmp_v < 75)
35675 - mask_amt = 1;
35676 - else
35677 - mask_amt = 0;
35678 - if (cur_vit_mask < 0)
35679 - mask_m[abs(cur_vit_mask / 100)] = mask_amt;
35680 - else
35681 - mask_p[cur_vit_mask / 100] = mask_amt;
35682 - }
35683 - cur_vit_mask -= 100;
35684 - }
35685 -
35686 - tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
35687 - | (mask_m[48] << 26) | (mask_m[49] << 24)
35688 - | (mask_m[50] << 22) | (mask_m[51] << 20)
35689 - | (mask_m[52] << 18) | (mask_m[53] << 16)
35690 - | (mask_m[54] << 14) | (mask_m[55] << 12)
35691 - | (mask_m[56] << 10) | (mask_m[57] << 8)
35692 - | (mask_m[58] << 6) | (mask_m[59] << 4)
35693 - | (mask_m[60] << 2) | (mask_m[61] << 0);
35694 - REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
35695 - REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
35696 -
35697 - tmp_mask = (mask_m[31] << 28)
35698 - | (mask_m[32] << 26) | (mask_m[33] << 24)
35699 - | (mask_m[34] << 22) | (mask_m[35] << 20)
35700 - | (mask_m[36] << 18) | (mask_m[37] << 16)
35701 - | (mask_m[48] << 14) | (mask_m[39] << 12)
35702 - | (mask_m[40] << 10) | (mask_m[41] << 8)
35703 - | (mask_m[42] << 6) | (mask_m[43] << 4)
35704 - | (mask_m[44] << 2) | (mask_m[45] << 0);
35705 - REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
35706 - REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
35707 -
35708 - tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
35709 - | (mask_m[18] << 26) | (mask_m[18] << 24)
35710 - | (mask_m[20] << 22) | (mask_m[20] << 20)
35711 - | (mask_m[22] << 18) | (mask_m[22] << 16)
35712 - | (mask_m[24] << 14) | (mask_m[24] << 12)
35713 - | (mask_m[25] << 10) | (mask_m[26] << 8)
35714 - | (mask_m[27] << 6) | (mask_m[28] << 4)
35715 - | (mask_m[29] << 2) | (mask_m[30] << 0);
35716 - REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
35717 - REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
35718 -
35719 - tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
35720 - | (mask_m[2] << 26) | (mask_m[3] << 24)
35721 - | (mask_m[4] << 22) | (mask_m[5] << 20)
35722 - | (mask_m[6] << 18) | (mask_m[7] << 16)
35723 - | (mask_m[8] << 14) | (mask_m[9] << 12)
35724 - | (mask_m[10] << 10) | (mask_m[11] << 8)
35725 - | (mask_m[12] << 6) | (mask_m[13] << 4)
35726 - | (mask_m[14] << 2) | (mask_m[15] << 0);
35727 - REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
35728 - REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
35729 -
35730 - tmp_mask = (mask_p[15] << 28)
35731 - | (mask_p[14] << 26) | (mask_p[13] << 24)
35732 - | (mask_p[12] << 22) | (mask_p[11] << 20)
35733 - | (mask_p[10] << 18) | (mask_p[9] << 16)
35734 - | (mask_p[8] << 14) | (mask_p[7] << 12)
35735 - | (mask_p[6] << 10) | (mask_p[5] << 8)
35736 - | (mask_p[4] << 6) | (mask_p[3] << 4)
35737 - | (mask_p[2] << 2) | (mask_p[1] << 0);
35738 - REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
35739 - REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
35740 -
35741 - tmp_mask = (mask_p[30] << 28)
35742 - | (mask_p[29] << 26) | (mask_p[28] << 24)
35743 - | (mask_p[27] << 22) | (mask_p[26] << 20)
35744 - | (mask_p[25] << 18) | (mask_p[24] << 16)
35745 - | (mask_p[23] << 14) | (mask_p[22] << 12)
35746 - | (mask_p[21] << 10) | (mask_p[20] << 8)
35747 - | (mask_p[19] << 6) | (mask_p[18] << 4)
35748 - | (mask_p[17] << 2) | (mask_p[16] << 0);
35749 - REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
35750 - REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
35751 -
35752 - tmp_mask = (mask_p[45] << 28)
35753 - | (mask_p[44] << 26) | (mask_p[43] << 24)
35754 - | (mask_p[42] << 22) | (mask_p[41] << 20)
35755 - | (mask_p[40] << 18) | (mask_p[39] << 16)
35756 - | (mask_p[38] << 14) | (mask_p[37] << 12)
35757 - | (mask_p[36] << 10) | (mask_p[35] << 8)
35758 - | (mask_p[34] << 6) | (mask_p[33] << 4)
35759 - | (mask_p[32] << 2) | (mask_p[31] << 0);
35760 - REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
35761 - REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
35762 -
35763 - tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
35764 - | (mask_p[59] << 26) | (mask_p[58] << 24)
35765 - | (mask_p[57] << 22) | (mask_p[56] << 20)
35766 - | (mask_p[55] << 18) | (mask_p[54] << 16)
35767 - | (mask_p[53] << 14) | (mask_p[52] << 12)
35768 - | (mask_p[51] << 10) | (mask_p[50] << 8)
35769 - | (mask_p[49] << 6) | (mask_p[48] << 4)
35770 - | (mask_p[47] << 2) | (mask_p[46] << 0);
35771 - REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
35772 - REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
35773 -}
35774 -
35775 -/**
35776 - * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming
35777 - * @ah: atheros hardware structure
35778 - *
35779 - * Only required for older devices with external AR2133/AR5133 radios.
35780 - */
35781 -int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
35782 -{
35783 -#define ATH_ALLOC_BANK(bank, size) do { \
35784 - bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
35785 - if (!bank) { \
35786 - ath_print(common, ATH_DBG_FATAL, \
35787 - "Cannot allocate RF banks\n"); \
35788 - return -ENOMEM; \
35789 - } \
35790 - } while (0);
35791 -
35792 - struct ath_common *common = ath9k_hw_common(ah);
35793 -
35794 - BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
35795 -
35796 - ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
35797 - ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
35798 - ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
35799 - ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
35800 - ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
35801 - ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
35802 - ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
35803 - ATH_ALLOC_BANK(ah->addac5416_21,
35804 - ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
35805 - ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
35806 -
35807 - return 0;
35808 -#undef ATH_ALLOC_BANK
35809 -}
35810 -
35811 -
35812 -/**
35813 - * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
35814 - * @ah: atheros hardware struture
35815 - * For the external AR2133/AR5133 radios banks.
35816 - */
35817 -void
35818 -ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
35819 -{
35820 -#define ATH_FREE_BANK(bank) do { \
35821 - kfree(bank); \
35822 - bank = NULL; \
35823 - } while (0);
35824 -
35825 - BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
35826 -
35827 - ATH_FREE_BANK(ah->analogBank0Data);
35828 - ATH_FREE_BANK(ah->analogBank1Data);
35829 - ATH_FREE_BANK(ah->analogBank2Data);
35830 - ATH_FREE_BANK(ah->analogBank3Data);
35831 - ATH_FREE_BANK(ah->analogBank6Data);
35832 - ATH_FREE_BANK(ah->analogBank6TPCData);
35833 - ATH_FREE_BANK(ah->analogBank7Data);
35834 - ATH_FREE_BANK(ah->addac5416_21);
35835 - ATH_FREE_BANK(ah->bank6Temp);
35836 -
35837 -#undef ATH_FREE_BANK
35838 -}
35839 -
35840 -/* *
35841 - * ath9k_hw_set_rf_regs - programs rf registers based on EEPROM
35842 - * @ah: atheros hardware structure
35843 - * @chan:
35844 - * @modesIndex:
35845 - *
35846 - * Used for the external AR2133/AR5133 radios.
35847 - *
35848 - * Reads the EEPROM header info from the device structure and programs
35849 - * all rf registers. This routine requires access to the analog
35850 - * rf device. This is not required for single-chip devices.
35851 - */
35852 -bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
35853 - u16 modesIndex)
35854 -{
35855 - u32 eepMinorRev;
35856 - u32 ob5GHz = 0, db5GHz = 0;
35857 - u32 ob2GHz = 0, db2GHz = 0;
35858 - int regWrites = 0;
35859 -
35860 - /*
35861 - * Software does not need to program bank data
35862 - * for single chip devices, that is AR9280 or anything
35863 - * after that.
35864 - */
35865 - if (AR_SREV_9280_10_OR_LATER(ah))
35866 - return true;
35867 -
35868 - /* Setup rf parameters */
35869 - eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
35870 -
35871 - /* Setup Bank 0 Write */
35872 - RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
35873 -
35874 - /* Setup Bank 1 Write */
35875 - RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
35876 -
35877 - /* Setup Bank 2 Write */
35878 - RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
35879 -
35880 - /* Setup Bank 6 Write */
35881 - RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
35882 - modesIndex);
35883 - {
35884 - int i;
35885 - for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
35886 - ah->analogBank6Data[i] =
35887 - INI_RA(&ah->iniBank6TPC, i, modesIndex);
35888 - }
35889 - }
35890 -
35891 - /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
35892 - if (eepMinorRev >= 2) {
35893 - if (IS_CHAN_2GHZ(chan)) {
35894 - ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
35895 - db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
35896 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
35897 - ob2GHz, 3, 197, 0);
35898 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
35899 - db2GHz, 3, 194, 0);
35900 - } else {
35901 - ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
35902 - db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
35903 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
35904 - ob5GHz, 3, 203, 0);
35905 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
35906 - db5GHz, 3, 200, 0);
35907 - }
35908 - }
35909 -
35910 - /* Setup Bank 7 Setup */
35911 - RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
35912 -
35913 - /* Write Analog registers */
35914 - REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
35915 - regWrites);
35916 - REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
35917 - regWrites);
35918 - REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
35919 - regWrites);
35920 - REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
35921 - regWrites);
35922 - REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
35923 - regWrites);
35924 - REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
35925 - regWrites);
35926 -
35927 - return true;
35928 -}
35929 diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
35930 index 0132e4c..e724c2c 100644
35931 --- a/drivers/net/wireless/ath/ath9k/phy.h
35932 +++ b/drivers/net/wireless/ath/ath9k/phy.h
35933 @@ -17,504 +17,15 @@
35934 #ifndef PHY_H
35935 #define PHY_H
35936
35937 -/* Common between single chip and non single-chip solutions */
35938 -void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites);
35939 -
35940 -/* Single chip radio settings */
35941 -int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
35942 -void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
35943 -
35944 -/* Routines below are for non single-chip solutions */
35945 -int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
35946 -void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
35947 -
35948 -int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);
35949 -void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);
35950 -
35951 -bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
35952 - struct ath9k_channel *chan,
35953 - u16 modesIndex);
35954 +#define CHANSEL_DIV 15
35955 +#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV)
35956 +#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV)
35957
35958 #define AR_PHY_BASE 0x9800
35959 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
35960
35961 -#define AR_PHY_TEST 0x9800
35962 -#define PHY_AGC_CLR 0x10000000
35963 -#define RFSILENT_BB 0x00002000
35964 -
35965 -#define AR_PHY_TURBO 0x9804
35966 -#define AR_PHY_FC_TURBO_MODE 0x00000001
35967 -#define AR_PHY_FC_TURBO_SHORT 0x00000002
35968 -#define AR_PHY_FC_DYN2040_EN 0x00000004
35969 -#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
35970 -#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
35971 -/* For 25 MHz channel spacing -- not used but supported by hw */
35972 -#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
35973 -#define AR_PHY_FC_HT_EN 0x00000040
35974 -#define AR_PHY_FC_SHORT_GI_40 0x00000080
35975 -#define AR_PHY_FC_WALSH 0x00000100
35976 -#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
35977 -#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
35978 -
35979 -#define AR_PHY_TEST2 0x9808
35980 -
35981 -#define AR_PHY_TIMING2 0x9810
35982 -#define AR_PHY_TIMING3 0x9814
35983 -#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
35984 -#define AR_PHY_TIMING3_DSC_MAN_S 17
35985 -#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
35986 -#define AR_PHY_TIMING3_DSC_EXP_S 13
35987 -
35988 -#define AR_PHY_CHIP_ID 0x9818
35989 -#define AR_PHY_CHIP_ID_REV_0 0x80
35990 -#define AR_PHY_CHIP_ID_REV_1 0x81
35991 -#define AR_PHY_CHIP_ID_9160_REV_0 0xb0
35992 -
35993 -#define AR_PHY_ACTIVE 0x981C
35994 -#define AR_PHY_ACTIVE_EN 0x00000001
35995 -#define AR_PHY_ACTIVE_DIS 0x00000000
35996 -
35997 -#define AR_PHY_RF_CTL2 0x9824
35998 -#define AR_PHY_TX_END_DATA_START 0x000000FF
35999 -#define AR_PHY_TX_END_DATA_START_S 0
36000 -#define AR_PHY_TX_END_PA_ON 0x0000FF00
36001 -#define AR_PHY_TX_END_PA_ON_S 8
36002 -
36003 -#define AR_PHY_RF_CTL3 0x9828
36004 -#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
36005 -#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
36006 -
36007 -#define AR_PHY_ADC_CTL 0x982C
36008 -#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
36009 -#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
36010 -#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
36011 -#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
36012 -#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
36013 -#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
36014 -#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
36015 -
36016 -#define AR_PHY_ADC_SERIAL_CTL 0x9830
36017 -#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
36018 -#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
36019 -
36020 -#define AR_PHY_RF_CTL4 0x9834
36021 -#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
36022 -#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
36023 -#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
36024 -#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
36025 -#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
36026 -#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
36027 -#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
36028 -#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
36029 -
36030 -#define AR_PHY_TSTDAC_CONST 0x983c
36031 -
36032 -#define AR_PHY_SETTLING 0x9844
36033 -#define AR_PHY_SETTLING_SWITCH 0x00003F80
36034 -#define AR_PHY_SETTLING_SWITCH_S 7
36035 -
36036 -#define AR_PHY_RXGAIN 0x9848
36037 -#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
36038 -#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
36039 -#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
36040 -#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
36041 -#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
36042 -#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
36043 -#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
36044 -#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
36045 -
36046 -#define AR_PHY_DESIRED_SZ 0x9850
36047 -#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
36048 -#define AR_PHY_DESIRED_SZ_ADC_S 0
36049 -#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
36050 -#define AR_PHY_DESIRED_SZ_PGA_S 8
36051 -#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
36052 -#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
36053 -
36054 -#define AR_PHY_FIND_SIG 0x9858
36055 -#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
36056 -#define AR_PHY_FIND_SIG_FIRSTEP_S 12
36057 -#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
36058 -#define AR_PHY_FIND_SIG_FIRPWR_S 18
36059 -
36060 -#define AR_PHY_AGC_CTL1 0x985C
36061 -#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
36062 -#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
36063 -#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
36064 -#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
36065 -
36066 -#define AR_PHY_AGC_CONTROL 0x9860
36067 -#define AR_PHY_AGC_CONTROL_CAL 0x00000001
36068 -#define AR_PHY_AGC_CONTROL_NF 0x00000002
36069 -#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
36070 -#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
36071 -#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
36072 -
36073 -#define AR_PHY_CCA 0x9864
36074 -#define AR_PHY_MINCCA_PWR 0x0FF80000
36075 -#define AR_PHY_MINCCA_PWR_S 19
36076 -#define AR_PHY_CCA_THRESH62 0x0007F000
36077 -#define AR_PHY_CCA_THRESH62_S 12
36078 -#define AR9280_PHY_MINCCA_PWR 0x1FF00000
36079 -#define AR9280_PHY_MINCCA_PWR_S 20
36080 -#define AR9280_PHY_CCA_THRESH62 0x000FF000
36081 -#define AR9280_PHY_CCA_THRESH62_S 12
36082 -
36083 -#define AR_PHY_SFCORR_LOW 0x986C
36084 -#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
36085 -#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
36086 -#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
36087 -#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
36088 -#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
36089 -#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
36090 -#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
36091 -
36092 -#define AR_PHY_SFCORR 0x9868
36093 -#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
36094 -#define AR_PHY_SFCORR_M2COUNT_THR_S 0
36095 -#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
36096 -#define AR_PHY_SFCORR_M1_THRESH_S 17
36097 -#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
36098 -#define AR_PHY_SFCORR_M2_THRESH_S 24
36099 -
36100 -#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
36101 -#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
36102 -#define AR_PHY_SYNTH_CONTROL 0x9874
36103 -#define AR_PHY_SLEEP_SCAL 0x9878
36104 -
36105 -#define AR_PHY_PLL_CTL 0x987c
36106 -#define AR_PHY_PLL_CTL_40 0xaa
36107 -#define AR_PHY_PLL_CTL_40_5413 0x04
36108 -#define AR_PHY_PLL_CTL_44 0xab
36109 -#define AR_PHY_PLL_CTL_44_2133 0xeb
36110 -#define AR_PHY_PLL_CTL_40_2133 0xea
36111 -
36112 -#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
36113 -#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
36114 -#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
36115 -#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
36116 -#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
36117 -#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
36118 -#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
36119 -#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
36120 -#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
36121 -#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
36122 -#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
36123 -#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
36124 -#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
36125 -#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
36126 -
36127 -#define AR_PHY_RX_DELAY 0x9914
36128 -#define AR_PHY_SEARCH_START_DELAY 0x9918
36129 -#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
36130 -
36131 -#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
36132 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
36133 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
36134 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
36135 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
36136 -#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
36137 -#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
36138 -#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
36139 -#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
36140 -
36141 -#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
36142 -#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
36143 -#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
36144 -#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
36145 -
36146 -#define AR_PHY_TIMING5 0x9924
36147 -#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
36148 -#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
36149 -
36150 -#define AR_PHY_POWER_TX_RATE1 0x9934
36151 -#define AR_PHY_POWER_TX_RATE2 0x9938
36152 -#define AR_PHY_POWER_TX_RATE_MAX 0x993c
36153 -#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
36154 -
36155 -#define AR_PHY_FRAME_CTL 0x9944
36156 -#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
36157 -#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
36158 -
36159 -#define AR_PHY_TXPWRADJ 0x994C
36160 -#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
36161 -#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
36162 -#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
36163 -#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
36164 -
36165 -#define AR_PHY_RADAR_EXT 0x9940
36166 -#define AR_PHY_RADAR_EXT_ENA 0x00004000
36167 -
36168 -#define AR_PHY_RADAR_0 0x9954
36169 -#define AR_PHY_RADAR_0_ENA 0x00000001
36170 -#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
36171 -#define AR_PHY_RADAR_0_INBAND 0x0000003e
36172 -#define AR_PHY_RADAR_0_INBAND_S 1
36173 -#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
36174 -#define AR_PHY_RADAR_0_PRSSI_S 6
36175 -#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
36176 -#define AR_PHY_RADAR_0_HEIGHT_S 12
36177 -#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
36178 -#define AR_PHY_RADAR_0_RRSSI_S 18
36179 -#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
36180 -#define AR_PHY_RADAR_0_FIRPWR_S 24
36181 -
36182 -#define AR_PHY_RADAR_1 0x9958
36183 -#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
36184 -#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
36185 -#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
36186 -#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
36187 -#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
36188 -#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
36189 -#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
36190 -#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
36191 -#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
36192 -#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
36193 -#define AR_PHY_RADAR_1_MAXLEN_S 0
36194 -
36195 -#define AR_PHY_SWITCH_CHAIN_0 0x9960
36196 -#define AR_PHY_SWITCH_COM 0x9964
36197 -
36198 -#define AR_PHY_SIGMA_DELTA 0x996C
36199 -#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
36200 -#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
36201 -#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
36202 -#define AR_PHY_SIGMA_DELTA_FILT2_S 3
36203 -#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
36204 -#define AR_PHY_SIGMA_DELTA_FILT1_S 8
36205 -#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
36206 -#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
36207 -
36208 -#define AR_PHY_RESTART 0x9970
36209 -#define AR_PHY_RESTART_DIV_GC 0x001C0000
36210 -#define AR_PHY_RESTART_DIV_GC_S 18
36211 -
36212 -#define AR_PHY_RFBUS_REQ 0x997C
36213 -#define AR_PHY_RFBUS_REQ_EN 0x00000001
36214 -
36215 -#define AR_PHY_TIMING7 0x9980
36216 -#define AR_PHY_TIMING8 0x9984
36217 -#define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
36218 -#define AR_PHY_TIMING8_PILOT_MASK_2_S 0
36219 -
36220 -#define AR_PHY_BIN_MASK2_1 0x9988
36221 -#define AR_PHY_BIN_MASK2_2 0x998c
36222 -#define AR_PHY_BIN_MASK2_3 0x9990
36223 -#define AR_PHY_BIN_MASK2_4 0x9994
36224 -
36225 -#define AR_PHY_BIN_MASK_1 0x9900
36226 -#define AR_PHY_BIN_MASK_2 0x9904
36227 -#define AR_PHY_BIN_MASK_3 0x9908
36228 -
36229 -#define AR_PHY_MASK_CTL 0x990c
36230 -
36231 -#define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
36232 -#define AR_PHY_BIN_MASK2_4_MASK_4_S 0
36233 -
36234 -#define AR_PHY_TIMING9 0x9998
36235 -#define AR_PHY_TIMING10 0x999c
36236 -#define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
36237 -#define AR_PHY_TIMING10_PILOT_MASK_2_S 0
36238 -
36239 -#define AR_PHY_TIMING11 0x99a0
36240 -#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
36241 -#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
36242 -#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
36243 -#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
36244 -#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
36245 -#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
36246 -
36247 -#define AR_PHY_RX_CHAINMASK 0x99a4
36248 -#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
36249 -#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
36250 -#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
36251 -
36252 -#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
36253 -#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
36254 -#define AR_PHY_9285_ANT_DIV_CTL 0x01000000
36255 -#define AR_PHY_9285_ANT_DIV_CTL_S 24
36256 -#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
36257 -#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
36258 -#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
36259 -#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
36260 -#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
36261 -#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
36262 -#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
36263 -#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
36264 -#define AR_PHY_9285_ANT_DIV_LNA1 2
36265 -#define AR_PHY_9285_ANT_DIV_LNA2 1
36266 -#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
36267 -#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
36268 -#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
36269 -#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
36270 -
36271 -#define AR_PHY_EXT_CCA0 0x99b8
36272 -#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
36273 -#define AR_PHY_EXT_CCA0_THRESH62_S 0
36274 -
36275 -#define AR_PHY_EXT_CCA 0x99bc
36276 -#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
36277 -#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
36278 -#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
36279 -#define AR_PHY_EXT_CCA_THRESH62_S 16
36280 -#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
36281 -#define AR_PHY_EXT_MINCCA_PWR_S 23
36282 -#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
36283 -#define AR9280_PHY_EXT_MINCCA_PWR_S 16
36284 -
36285 -#define AR_PHY_SFCORR_EXT 0x99c0
36286 -#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
36287 -#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
36288 -#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
36289 -#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
36290 -#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
36291 -#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
36292 -#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
36293 -#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
36294 -#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
36295 -
36296 -#define AR_PHY_HALFGI 0x99D0
36297 -#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
36298 -#define AR_PHY_HALFGI_DSC_MAN_S 4
36299 -#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
36300 -#define AR_PHY_HALFGI_DSC_EXP_S 0
36301 -
36302 -#define AR_PHY_CHAN_INFO_MEMORY 0x99DC
36303 -#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
36304 -
36305 -#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
36306 -
36307 -#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC
36308 -#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
36309 -
36310 -#define AR_PHY_M_SLEEP 0x99f0
36311 -#define AR_PHY_REFCLKDLY 0x99f4
36312 -#define AR_PHY_REFCLKPD 0x99f8
36313 -
36314 -#define AR_PHY_CALMODE 0x99f0
36315 -
36316 -#define AR_PHY_CALMODE_IQ 0x00000000
36317 -#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
36318 -#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
36319 -#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
36320 -
36321 -#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
36322 -#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
36323 -#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
36324 -#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
36325 -
36326 -#define AR_PHY_CURRENT_RSSI 0x9c1c
36327 -#define AR9280_PHY_CURRENT_RSSI 0x9c3c
36328 -
36329 -#define AR_PHY_RFBUS_GRANT 0x9C20
36330 -#define AR_PHY_RFBUS_GRANT_EN 0x00000001
36331 -
36332 -#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
36333 -#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
36334 -
36335 -#define AR_PHY_CHAN_INFO_GAIN 0x9CFC
36336 -
36337 -#define AR_PHY_MODE 0xA200
36338 -#define AR_PHY_MODE_ASYNCFIFO 0x80
36339 -#define AR_PHY_MODE_AR2133 0x08
36340 -#define AR_PHY_MODE_AR5111 0x00
36341 -#define AR_PHY_MODE_AR5112 0x08
36342 -#define AR_PHY_MODE_DYNAMIC 0x04
36343 -#define AR_PHY_MODE_RF2GHZ 0x02
36344 -#define AR_PHY_MODE_RF5GHZ 0x00
36345 -#define AR_PHY_MODE_CCK 0x01
36346 -#define AR_PHY_MODE_OFDM 0x00
36347 -#define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
36348 -
36349 -#define AR_PHY_CCK_TX_CTRL 0xA204
36350 -#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
36351 -#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
36352 -#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
36353 -
36354 -#define AR_PHY_CCK_DETECT 0xA208
36355 -#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
36356 -#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
36357 -/* [12:6] settling time for antenna switch */
36358 -#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
36359 -#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
36360 -#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
36361 -#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
36362 -
36363 -#define AR_PHY_GAIN_2GHZ 0xA20C
36364 -#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
36365 -#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
36366 -#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
36367 -#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
36368 -#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
36369 -#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
36370 -
36371 -#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
36372 -#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
36373 -#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
36374 -#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
36375 -#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
36376 -#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
36377 -#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
36378 -#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
36379 -
36380 -#define AR_PHY_CCK_RXCTRL4 0xA21C
36381 -#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
36382 -#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
36383 -
36384 -#define AR_PHY_DAG_CTRLCCK 0xA228
36385 -#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
36386 -#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
36387 -#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
36388 -
36389 -#define AR_PHY_FORCE_CLKEN_CCK 0xA22C
36390 -#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
36391 -
36392 -#define AR_PHY_POWER_TX_RATE3 0xA234
36393 -#define AR_PHY_POWER_TX_RATE4 0xA238
36394 -
36395 -#define AR_PHY_SCRM_SEQ_XR 0xA23C
36396 -#define AR_PHY_HEADER_DETECT_XR 0xA240
36397 -#define AR_PHY_CHIRP_DETECTED_XR 0xA244
36398 -#define AR_PHY_BLUETOOTH 0xA254
36399 -
36400 -#define AR_PHY_TPCRG1 0xA258
36401 -#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
36402 -#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
36403 -
36404 -#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
36405 -#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
36406 -#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
36407 -#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
36408 -#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
36409 -#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
36410 -
36411 -#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
36412 -#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
36413 -
36414 -#define AR_PHY_TX_PWRCTRL4 0xa264
36415 -#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
36416 -#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
36417 -#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
36418 -#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
36419 -
36420 -#define AR_PHY_TX_PWRCTRL6_0 0xa270
36421 -#define AR_PHY_TX_PWRCTRL6_1 0xb270
36422 -#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
36423 -#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
36424 -
36425 -#define AR_PHY_TX_PWRCTRL7 0xa274
36426 #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000
36427 #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13
36428 -#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
36429 -#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
36430 -
36431 -#define AR_PHY_TX_PWRCTRL9 0xa27C
36432 -#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
36433 -#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
36434 -#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
36435 -#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
36436 -
36437 -#define AR_PHY_TX_GAIN_TBL1 0xa300
36438 #define AR_PHY_TX_GAIN_CLC 0x0000001E
36439 #define AR_PHY_TX_GAIN_CLC_S 1
36440 #define AR_PHY_TX_GAIN 0x0007F000
36441 @@ -526,91 +37,6 @@ bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
36442 #define AR_PHY_CLC_Q0 0x0000ffd0
36443 #define AR_PHY_CLC_Q0_S 5
36444
36445 -#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
36446 -#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
36447 -#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00
36448 -#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
36449 -
36450 -#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
36451 -#define AR_PHY_MASK2_M_31_45 0xa3a4
36452 -#define AR_PHY_MASK2_M_16_30 0xa3a8
36453 -#define AR_PHY_MASK2_M_00_15 0xa3ac
36454 -#define AR_PHY_MASK2_P_15_01 0xa3b8
36455 -#define AR_PHY_MASK2_P_30_16 0xa3bc
36456 -#define AR_PHY_MASK2_P_45_31 0xa3c0
36457 -#define AR_PHY_MASK2_P_61_45 0xa3c4
36458 -#define AR_PHY_SPUR_REG 0x994c
36459 -
36460 -#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
36461 -#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
36462 -
36463 -#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
36464 -#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
36465 -#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
36466 -#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
36467 -#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
36468 -#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
36469 -
36470 -#define AR_PHY_PILOT_MASK_01_30 0xa3b0
36471 -#define AR_PHY_PILOT_MASK_31_60 0xa3b4
36472 -
36473 -#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
36474 -#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
36475 -
36476 -#define AR_PHY_ANALOG_SWAP 0xa268
36477 -#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
36478 -
36479 -#define AR_PHY_TPCRG5 0xA26C
36480 -#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
36481 -#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
36482 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
36483 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
36484 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
36485 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
36486 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
36487 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
36488 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
36489 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
36490 -
36491 -/* Carrier leak calibration control, do it after AGC calibration */
36492 -#define AR_PHY_CL_CAL_CTL 0xA358
36493 -#define AR_PHY_CL_CAL_ENABLE 0x00000002
36494 -#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
36495 -
36496 -#define AR_PHY_POWER_TX_RATE5 0xA38C
36497 -#define AR_PHY_POWER_TX_RATE6 0xA390
36498 -
36499 -#define AR_PHY_CAL_CHAINMASK 0xA39C
36500 -
36501 -#define AR_PHY_POWER_TX_SUB 0xA3C8
36502 -#define AR_PHY_POWER_TX_RATE7 0xA3CC
36503 -#define AR_PHY_POWER_TX_RATE8 0xA3D0
36504 -#define AR_PHY_POWER_TX_RATE9 0xA3D4
36505 -
36506 -#define AR_PHY_XPA_CFG 0xA3D8
36507 -#define AR_PHY_FORCE_XPA_CFG 0x000000001
36508 -#define AR_PHY_FORCE_XPA_CFG_S 0
36509 -
36510 -#define AR_PHY_CH1_CCA 0xa864
36511 -#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
36512 -#define AR_PHY_CH1_MINCCA_PWR_S 19
36513 -#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
36514 -#define AR9280_PHY_CH1_MINCCA_PWR_S 20
36515 -
36516 -#define AR_PHY_CH2_CCA 0xb864
36517 -#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
36518 -#define AR_PHY_CH2_MINCCA_PWR_S 19
36519 -
36520 -#define AR_PHY_CH1_EXT_CCA 0xa9bc
36521 -#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
36522 -#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
36523 -#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
36524 -#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
36525 -
36526 -#define AR_PHY_CH2_EXT_CCA 0xb9bc
36527 -#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
36528 -#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
36529 -
36530 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \
36531 int r; \
36532 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
36533 @@ -625,6 +51,7 @@ bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
36534 #define ANTSWAP_AB 0x0001
36535 #define REDUCE_CHAIN_0 0x00000050
36536 #define REDUCE_CHAIN_1 0x00000051
36537 +#define AR_PHY_CHIP_ID 0x9818
36538
36539 #define RF_BANK_SETUP(_bank, _iniarray, _col) do { \
36540 int i; \
36541 @@ -632,4 +59,7 @@ bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
36542 (_bank)[i] = INI_RA((_iniarray), i, _col);; \
36543 } while (0)
36544
36545 +#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
36546 +#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
36547 +
36548 #endif
36549 diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
36550 index 3c4b5d2..f10bd06 100644
36551 --- a/drivers/net/wireless/ath/ath9k/rc.c
36552 +++ b/drivers/net/wireless/ath/ath9k/rc.c
36553 @@ -689,6 +689,15 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
36554 rate_table = sc->cur_rate_table;
36555 rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table, &is_probe);
36556
36557 + /*
36558 + * If we're in HT mode and both us and our peer supports LDPC.
36559 + * We don't need to check our own device's capabilities as our own
36560 + * ht capabilities would have already been intersected with our peer's.
36561 + */
36562 + if (conf_is_ht(&sc->hw->conf) &&
36563 + (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING))
36564 + tx_info->flags |= IEEE80211_TX_CTL_LDPC;
36565 +
36566 if (is_probe) {
36567 /* set one try for probe rates. For the
36568 * probes don't enable rts */
36569 diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
36570 index 94560e2..f84fcf0 100644
36571 --- a/drivers/net/wireless/ath/ath9k/recv.c
36572 +++ b/drivers/net/wireless/ath/ath9k/recv.c
36573 @@ -16,6 +16,8 @@
36574
36575 #include "ath9k.h"
36576
36577 +#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
36578 +
36579 static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
36580 struct ieee80211_hdr *hdr)
36581 {
36582 @@ -115,56 +117,246 @@ static void ath_opmode_init(struct ath_softc *sc)
36583 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
36584 }
36585
36586 -int ath_rx_init(struct ath_softc *sc, int nbufs)
36587 +static bool ath_rx_edma_buf_link(struct ath_softc *sc,
36588 + enum ath9k_rx_qtype qtype)
36589 {
36590 - struct ath_common *common = ath9k_hw_common(sc->sc_ah);
36591 + struct ath_hw *ah = sc->sc_ah;
36592 + struct ath_rx_edma *rx_edma;
36593 struct sk_buff *skb;
36594 struct ath_buf *bf;
36595 - int error = 0;
36596
36597 - spin_lock_init(&sc->rx.rxflushlock);
36598 - sc->sc_flags &= ~SC_OP_RXFLUSH;
36599 - spin_lock_init(&sc->rx.rxbuflock);
36600 + rx_edma = &sc->rx.rx_edma[qtype];
36601 + if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
36602 + return false;
36603
36604 - common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
36605 - min(common->cachelsz, (u16)64));
36606 + bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
36607 + list_del_init(&bf->list);
36608
36609 - ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
36610 - common->cachelsz, common->rx_bufsize);
36611 + skb = bf->bf_mpdu;
36612 +
36613 + ATH_RXBUF_RESET(bf);
36614 + memset(skb->data, 0, ah->caps.rx_status_len);
36615 + dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
36616 + ah->caps.rx_status_len, DMA_TO_DEVICE);
36617
36618 - /* Initialize rx descriptors */
36619 + SKB_CB_ATHBUF(skb) = bf;
36620 + ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
36621 + skb_queue_tail(&rx_edma->rx_fifo, skb);
36622
36623 - error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
36624 - "rx", nbufs, 1);
36625 - if (error != 0) {
36626 - ath_print(common, ATH_DBG_FATAL,
36627 - "failed to allocate rx descriptors: %d\n", error);
36628 - goto err;
36629 + return true;
36630 +}
36631 +
36632 +static void ath_rx_addbuffer_edma(struct ath_softc *sc,
36633 + enum ath9k_rx_qtype qtype, int size)
36634 +{
36635 + struct ath_rx_edma *rx_edma;
36636 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
36637 + u32 nbuf = 0;
36638 +
36639 + rx_edma = &sc->rx.rx_edma[qtype];
36640 + if (list_empty(&sc->rx.rxbuf)) {
36641 + ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n");
36642 + return;
36643 }
36644
36645 + while (!list_empty(&sc->rx.rxbuf)) {
36646 + nbuf++;
36647 +
36648 + if (!ath_rx_edma_buf_link(sc, qtype))
36649 + break;
36650 +
36651 + if (nbuf >= size)
36652 + break;
36653 + }
36654 +}
36655 +
36656 +static void ath_rx_remove_buffer(struct ath_softc *sc,
36657 + enum ath9k_rx_qtype qtype)
36658 +{
36659 + struct ath_buf *bf;
36660 + struct ath_rx_edma *rx_edma;
36661 + struct sk_buff *skb;
36662 +
36663 + rx_edma = &sc->rx.rx_edma[qtype];
36664 +
36665 + while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
36666 + bf = SKB_CB_ATHBUF(skb);
36667 + BUG_ON(!bf);
36668 + list_add_tail(&bf->list, &sc->rx.rxbuf);
36669 + }
36670 +}
36671 +
36672 +static void ath_rx_edma_cleanup(struct ath_softc *sc)
36673 +{
36674 + struct ath_buf *bf;
36675 +
36676 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
36677 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
36678 +
36679 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
36680 + if (bf->bf_mpdu)
36681 + dev_kfree_skb_any(bf->bf_mpdu);
36682 + }
36683 +
36684 + INIT_LIST_HEAD(&sc->rx.rxbuf);
36685 +
36686 + kfree(sc->rx.rx_bufptr);
36687 + sc->rx.rx_bufptr = NULL;
36688 +}
36689 +
36690 +static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
36691 +{
36692 + skb_queue_head_init(&rx_edma->rx_fifo);
36693 + skb_queue_head_init(&rx_edma->rx_buffers);
36694 + rx_edma->rx_fifo_hwsize = size;
36695 +}
36696 +
36697 +static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
36698 +{
36699 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
36700 + struct ath_hw *ah = sc->sc_ah;
36701 + struct sk_buff *skb;
36702 + struct ath_buf *bf;
36703 + int error = 0, i;
36704 + u32 size;
36705 +
36706 +
36707 + common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN +
36708 + ah->caps.rx_status_len,
36709 + min(common->cachelsz, (u16)64));
36710 +
36711 + ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
36712 + ah->caps.rx_status_len);
36713 +
36714 + ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
36715 + ah->caps.rx_lp_qdepth);
36716 + ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
36717 + ah->caps.rx_hp_qdepth);
36718 +
36719 + size = sizeof(struct ath_buf) * nbufs;
36720 + bf = kzalloc(size, GFP_KERNEL);
36721 + if (!bf)
36722 + return -ENOMEM;
36723 +
36724 + INIT_LIST_HEAD(&sc->rx.rxbuf);
36725 + sc->rx.rx_bufptr = bf;
36726 +
36727 + for (i = 0; i < nbufs; i++, bf++) {
36728 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
36729 - if (skb == NULL) {
36730 + if (!skb) {
36731 error = -ENOMEM;
36732 - goto err;
36733 + goto rx_init_fail;
36734 }
36735
36736 + memset(skb->data, 0, common->rx_bufsize);
36737 bf->bf_mpdu = skb;
36738 +
36739 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
36740 common->rx_bufsize,
36741 - DMA_FROM_DEVICE);
36742 + DMA_BIDIRECTIONAL);
36743 if (unlikely(dma_mapping_error(sc->dev,
36744 - bf->bf_buf_addr))) {
36745 - dev_kfree_skb_any(skb);
36746 - bf->bf_mpdu = NULL;
36747 + bf->bf_buf_addr))) {
36748 + dev_kfree_skb_any(skb);
36749 + bf->bf_mpdu = NULL;
36750 + ath_print(common, ATH_DBG_FATAL,
36751 + "dma_mapping_error() on RX init\n");
36752 + error = -ENOMEM;
36753 + goto rx_init_fail;
36754 + }
36755 +
36756 + list_add_tail(&bf->list, &sc->rx.rxbuf);
36757 + }
36758 +
36759 + return 0;
36760 +
36761 +rx_init_fail:
36762 + ath_rx_edma_cleanup(sc);
36763 + return error;
36764 +}
36765 +
36766 +static void ath_edma_start_recv(struct ath_softc *sc)
36767 +{
36768 + spin_lock_bh(&sc->rx.rxbuflock);
36769 +
36770 + ath9k_hw_rxena(sc->sc_ah);
36771 +
36772 + ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
36773 + sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
36774 +
36775 + ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
36776 + sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
36777 +
36778 + spin_unlock_bh(&sc->rx.rxbuflock);
36779 +
36780 + ath_opmode_init(sc);
36781 +
36782 + ath9k_hw_startpcureceive(sc->sc_ah);
36783 +}
36784 +
36785 +static void ath_edma_stop_recv(struct ath_softc *sc)
36786 +{
36787 + spin_lock_bh(&sc->rx.rxbuflock);
36788 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
36789 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
36790 + spin_unlock_bh(&sc->rx.rxbuflock);
36791 +}
36792 +
36793 +int ath_rx_init(struct ath_softc *sc, int nbufs)
36794 +{
36795 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
36796 + struct sk_buff *skb;
36797 + struct ath_buf *bf;
36798 + int error = 0;
36799 +
36800 + spin_lock_init(&sc->rx.rxflushlock);
36801 + sc->sc_flags &= ~SC_OP_RXFLUSH;
36802 + spin_lock_init(&sc->rx.rxbuflock);
36803 +
36804 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
36805 + return ath_rx_edma_init(sc, nbufs);
36806 + } else {
36807 + common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
36808 + min(common->cachelsz, (u16)64));
36809 +
36810 + ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
36811 + common->cachelsz, common->rx_bufsize);
36812 +
36813 + /* Initialize rx descriptors */
36814 +
36815 + error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
36816 + "rx", nbufs, 1, 0);
36817 + if (error != 0) {
36818 ath_print(common, ATH_DBG_FATAL,
36819 - "dma_mapping_error() on RX init\n");
36820 - error = -ENOMEM;
36821 + "failed to allocate rx descriptors: %d\n",
36822 + error);
36823 goto err;
36824 }
36825 - bf->bf_dmacontext = bf->bf_buf_addr;
36826 +
36827 + list_for_each_entry(bf, &sc->rx.rxbuf, list) {
36828 + skb = ath_rxbuf_alloc(common, common->rx_bufsize,
36829 + GFP_KERNEL);
36830 + if (skb == NULL) {
36831 + error = -ENOMEM;
36832 + goto err;
36833 + }
36834 +
36835 + bf->bf_mpdu = skb;
36836 + bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
36837 + common->rx_bufsize,
36838 + DMA_FROM_DEVICE);
36839 + if (unlikely(dma_mapping_error(sc->dev,
36840 + bf->bf_buf_addr))) {
36841 + dev_kfree_skb_any(skb);
36842 + bf->bf_mpdu = NULL;
36843 + ath_print(common, ATH_DBG_FATAL,
36844 + "dma_mapping_error() on RX init\n");
36845 + error = -ENOMEM;
36846 + goto err;
36847 + }
36848 + bf->bf_dmacontext = bf->bf_buf_addr;
36849 + }
36850 + sc->rx.rxlink = NULL;
36851 }
36852 - sc->rx.rxlink = NULL;
36853
36854 err:
36855 if (error)
36856 @@ -180,17 +372,23 @@ void ath_rx_cleanup(struct ath_softc *sc)
36857 struct sk_buff *skb;
36858 struct ath_buf *bf;
36859
36860 - list_for_each_entry(bf, &sc->rx.rxbuf, list) {
36861 - skb = bf->bf_mpdu;
36862 - if (skb) {
36863 - dma_unmap_single(sc->dev, bf->bf_buf_addr,
36864 - common->rx_bufsize, DMA_FROM_DEVICE);
36865 - dev_kfree_skb(skb);
36866 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
36867 + ath_rx_edma_cleanup(sc);
36868 + return;
36869 + } else {
36870 + list_for_each_entry(bf, &sc->rx.rxbuf, list) {
36871 + skb = bf->bf_mpdu;
36872 + if (skb) {
36873 + dma_unmap_single(sc->dev, bf->bf_buf_addr,
36874 + common->rx_bufsize,
36875 + DMA_FROM_DEVICE);
36876 + dev_kfree_skb(skb);
36877 + }
36878 }
36879 - }
36880
36881 - if (sc->rx.rxdma.dd_desc_len != 0)
36882 - ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
36883 + if (sc->rx.rxdma.dd_desc_len != 0)
36884 + ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
36885 + }
36886 }
36887
36888 /*
36889 @@ -273,6 +471,11 @@ int ath_startrecv(struct ath_softc *sc)
36890 struct ath_hw *ah = sc->sc_ah;
36891 struct ath_buf *bf, *tbf;
36892
36893 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
36894 + ath_edma_start_recv(sc);
36895 + return 0;
36896 + }
36897 +
36898 spin_lock_bh(&sc->rx.rxbuflock);
36899 if (list_empty(&sc->rx.rxbuf))
36900 goto start_recv;
36901 @@ -306,7 +509,12 @@ bool ath_stoprecv(struct ath_softc *sc)
36902 ath9k_hw_stoppcurecv(ah);
36903 ath9k_hw_setrxfilter(ah, 0);
36904 stopped = ath9k_hw_stopdmarecv(ah);
36905 - sc->rx.rxlink = NULL;
36906 +
36907 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
36908 + ath_edma_stop_recv(sc);
36909 + } else {
36910 + sc->rx.rxlink = NULL;
36911 + }
36912
36913 return stopped;
36914 }
36915 @@ -315,7 +523,9 @@ void ath_flushrecv(struct ath_softc *sc)
36916 {
36917 spin_lock_bh(&sc->rx.rxflushlock);
36918 sc->sc_flags |= SC_OP_RXFLUSH;
36919 - ath_rx_tasklet(sc, 1);
36920 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
36921 + ath_rx_tasklet(sc, 1, true);
36922 + ath_rx_tasklet(sc, 1, false);
36923 sc->sc_flags &= ~SC_OP_RXFLUSH;
36924 spin_unlock_bh(&sc->rx.rxflushlock);
36925 }
36926 @@ -469,14 +679,147 @@ static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
36927 ieee80211_rx(hw, skb);
36928 }
36929
36930 -int ath_rx_tasklet(struct ath_softc *sc, int flush)
36931 +static bool ath_edma_get_buffers(struct ath_softc *sc,
36932 + enum ath9k_rx_qtype qtype)
36933 {
36934 -#define PA2DESC(_sc, _pa) \
36935 - ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \
36936 - ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr)))
36937 + struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
36938 + struct ath_hw *ah = sc->sc_ah;
36939 + struct ath_common *common = ath9k_hw_common(ah);
36940 + struct sk_buff *skb;
36941 + struct ath_buf *bf;
36942 + int ret;
36943 +
36944 + skb = skb_peek(&rx_edma->rx_fifo);
36945 + if (!skb)
36946 + return false;
36947 +
36948 + bf = SKB_CB_ATHBUF(skb);
36949 + BUG_ON(!bf);
36950 +
36951 + dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
36952 + common->rx_bufsize, DMA_FROM_DEVICE);
36953 +
36954 + ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
36955 + if (ret == -EINPROGRESS)
36956 + return false;
36957 +
36958 + __skb_unlink(skb, &rx_edma->rx_fifo);
36959 + if (ret == -EINVAL) {
36960 + /* corrupt descriptor, skip this one and the following one */
36961 + list_add_tail(&bf->list, &sc->rx.rxbuf);
36962 + ath_rx_edma_buf_link(sc, qtype);
36963 + skb = skb_peek(&rx_edma->rx_fifo);
36964 + if (!skb)
36965 + return true;
36966 +
36967 + bf = SKB_CB_ATHBUF(skb);
36968 + BUG_ON(!bf);
36969 +
36970 + __skb_unlink(skb, &rx_edma->rx_fifo);
36971 + list_add_tail(&bf->list, &sc->rx.rxbuf);
36972 + ath_rx_edma_buf_link(sc, qtype);
36973 + }
36974 + skb_queue_tail(&rx_edma->rx_buffers, skb);
36975 +
36976 + return true;
36977 +}
36978
36979 +static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
36980 + struct ath_rx_status *rs,
36981 + enum ath9k_rx_qtype qtype)
36982 +{
36983 + struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
36984 + struct sk_buff *skb;
36985 struct ath_buf *bf;
36986 +
36987 + while (ath_edma_get_buffers(sc, qtype));
36988 + skb = __skb_dequeue(&rx_edma->rx_buffers);
36989 + if (!skb)
36990 + return NULL;
36991 +
36992 + bf = SKB_CB_ATHBUF(skb);
36993 + ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
36994 + return bf;
36995 +}
36996 +
36997 +static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
36998 + struct ath_rx_status *rs)
36999 +{
37000 + struct ath_hw *ah = sc->sc_ah;
37001 + struct ath_common *common = ath9k_hw_common(ah);
37002 struct ath_desc *ds;
37003 + struct ath_buf *bf;
37004 + int ret;
37005 +
37006 + if (list_empty(&sc->rx.rxbuf)) {
37007 + sc->rx.rxlink = NULL;
37008 + return NULL;
37009 + }
37010 +
37011 + bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
37012 + ds = bf->bf_desc;
37013 +
37014 + /*
37015 + * Must provide the virtual address of the current
37016 + * descriptor, the physical address, and the virtual
37017 + * address of the next descriptor in the h/w chain.
37018 + * This allows the HAL to look ahead to see if the
37019 + * hardware is done with a descriptor by checking the
37020 + * done bit in the following descriptor and the address
37021 + * of the current descriptor the DMA engine is working
37022 + * on. All this is necessary because of our use of
37023 + * a self-linked list to avoid rx overruns.
37024 + */
37025 + ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
37026 + if (ret == -EINPROGRESS) {
37027 + struct ath_rx_status trs;
37028 + struct ath_buf *tbf;
37029 + struct ath_desc *tds;
37030 +
37031 + memset(&trs, 0, sizeof(trs));
37032 + if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
37033 + sc->rx.rxlink = NULL;
37034 + return NULL;
37035 + }
37036 +
37037 + tbf = list_entry(bf->list.next, struct ath_buf, list);
37038 +
37039 + /*
37040 + * On some hardware the descriptor status words could
37041 + * get corrupted, including the done bit. Because of
37042 + * this, check if the next descriptor's done bit is
37043 + * set or not.
37044 + *
37045 + * If the next descriptor's done bit is set, the current
37046 + * descriptor has been corrupted. Force s/w to discard
37047 + * this descriptor and continue...
37048 + */
37049 +
37050 + tds = tbf->bf_desc;
37051 + ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
37052 + if (ret == -EINPROGRESS)
37053 + return NULL;
37054 + }
37055 +
37056 + if (!bf->bf_mpdu)
37057 + return bf;
37058 +
37059 + /*
37060 + * Synchronize the DMA transfer with CPU before
37061 + * 1. accessing the frame
37062 + * 2. requeueing the same buffer to h/w
37063 + */
37064 + dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
37065 + common->rx_bufsize,
37066 + DMA_FROM_DEVICE);
37067 +
37068 + return bf;
37069 +}
37070 +
37071 +
37072 +int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
37073 +{
37074 + struct ath_buf *bf;
37075 struct sk_buff *skb = NULL, *requeue_skb;
37076 struct ieee80211_rx_status *rxs;
37077 struct ath_hw *ah = sc->sc_ah;
37078 @@ -491,7 +834,16 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
37079 int retval;
37080 bool decrypt_error = false;
37081 struct ath_rx_status rs;
37082 + enum ath9k_rx_qtype qtype;
37083 + bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
37084 + int dma_type;
37085
37086 + if (edma)
37087 + dma_type = DMA_FROM_DEVICE;
37088 + else
37089 + dma_type = DMA_BIDIRECTIONAL;
37090 +
37091 + qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
37092 spin_lock_bh(&sc->rx.rxbuflock);
37093
37094 do {
37095 @@ -499,71 +851,19 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
37096 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
37097 break;
37098
37099 - if (list_empty(&sc->rx.rxbuf)) {
37100 - sc->rx.rxlink = NULL;
37101 - break;
37102 - }
37103 -
37104 - bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
37105 - ds = bf->bf_desc;
37106 -
37107 - /*
37108 - * Must provide the virtual address of the current
37109 - * descriptor, the physical address, and the virtual
37110 - * address of the next descriptor in the h/w chain.
37111 - * This allows the HAL to look ahead to see if the
37112 - * hardware is done with a descriptor by checking the
37113 - * done bit in the following descriptor and the address
37114 - * of the current descriptor the DMA engine is working
37115 - * on. All this is necessary because of our use of
37116 - * a self-linked list to avoid rx overruns.
37117 - */
37118 memset(&rs, 0, sizeof(rs));
37119 - retval = ath9k_hw_rxprocdesc(ah, ds, &rs, 0);
37120 - if (retval == -EINPROGRESS) {
37121 - struct ath_rx_status trs;
37122 - struct ath_buf *tbf;
37123 - struct ath_desc *tds;
37124 -
37125 - memset(&trs, 0, sizeof(trs));
37126 - if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
37127 - sc->rx.rxlink = NULL;
37128 - break;
37129 - }
37130 + if (edma)
37131 + bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
37132 + else
37133 + bf = ath_get_next_rx_buf(sc, &rs);
37134
37135 - tbf = list_entry(bf->list.next, struct ath_buf, list);
37136 -
37137 - /*
37138 - * On some hardware the descriptor status words could
37139 - * get corrupted, including the done bit. Because of
37140 - * this, check if the next descriptor's done bit is
37141 - * set or not.
37142 - *
37143 - * If the next descriptor's done bit is set, the current
37144 - * descriptor has been corrupted. Force s/w to discard
37145 - * this descriptor and continue...
37146 - */
37147 -
37148 - tds = tbf->bf_desc;
37149 - retval = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
37150 - if (retval == -EINPROGRESS) {
37151 - break;
37152 - }
37153 - }
37154 + if (!bf)
37155 + break;
37156
37157 skb = bf->bf_mpdu;
37158 if (!skb)
37159 continue;
37160
37161 - /*
37162 - * Synchronize the DMA transfer with CPU before
37163 - * 1. accessing the frame
37164 - * 2. requeueing the same buffer to h/w
37165 - */
37166 - dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
37167 - common->rx_bufsize,
37168 - DMA_FROM_DEVICE);
37169 -
37170 hdr = (struct ieee80211_hdr *) skb->data;
37171 rxs = IEEE80211_SKB_RXCB(skb);
37172
37173 @@ -597,9 +897,11 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
37174 /* Unmap the frame */
37175 dma_unmap_single(sc->dev, bf->bf_buf_addr,
37176 common->rx_bufsize,
37177 - DMA_FROM_DEVICE);
37178 + dma_type);
37179
37180 - skb_put(skb, rs.rs_datalen);
37181 + skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
37182 + if (ah->caps.rx_status_len)
37183 + skb_pull(skb, ah->caps.rx_status_len);
37184
37185 ath9k_cmn_rx_skb_postprocess(common, skb, &rs,
37186 rxs, decrypt_error);
37187 @@ -608,7 +910,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
37188 bf->bf_mpdu = requeue_skb;
37189 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
37190 common->rx_bufsize,
37191 - DMA_FROM_DEVICE);
37192 + dma_type);
37193 if (unlikely(dma_mapping_error(sc->dev,
37194 bf->bf_buf_addr))) {
37195 dev_kfree_skb_any(requeue_skb);
37196 @@ -639,12 +941,16 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
37197 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
37198
37199 requeue:
37200 - list_move_tail(&bf->list, &sc->rx.rxbuf);
37201 - ath_rx_buf_link(sc, bf);
37202 + if (edma) {
37203 + list_add_tail(&bf->list, &sc->rx.rxbuf);
37204 + ath_rx_edma_buf_link(sc, qtype);
37205 + } else {
37206 + list_move_tail(&bf->list, &sc->rx.rxbuf);
37207 + ath_rx_buf_link(sc, bf);
37208 + }
37209 } while (1);
37210
37211 spin_unlock_bh(&sc->rx.rxbuflock);
37212
37213 return 0;
37214 -#undef PA2DESC
37215 }
37216 diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
37217 index 7e36ad7..7fc1ddf 100644
37218 --- a/drivers/net/wireless/ath/ath9k/reg.h
37219 +++ b/drivers/net/wireless/ath/ath9k/reg.h
37220 @@ -20,7 +20,7 @@
37221 #include "../reg.h"
37222
37223 #define AR_CR 0x0008
37224 -#define AR_CR_RXE 0x00000004
37225 +#define AR_CR_RXE (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004)
37226 #define AR_CR_RXD 0x00000020
37227 #define AR_CR_SWI 0x00000040
37228
37229 @@ -39,6 +39,12 @@
37230 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000
37231 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17
37232
37233 +#define AR_RXBP_THRESH 0x0018
37234 +#define AR_RXBP_THRESH_HP 0x0000000f
37235 +#define AR_RXBP_THRESH_HP_S 0
37236 +#define AR_RXBP_THRESH_LP 0x00003f00
37237 +#define AR_RXBP_THRESH_LP_S 8
37238 +
37239 #define AR_MIRT 0x0020
37240 #define AR_MIRT_VAL 0x0000ffff
37241 #define AR_MIRT_VAL_S 16
37242 @@ -144,6 +150,9 @@
37243 #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15
37244 #define AR_MACMISC_MISC_OBS_BUS_1 1
37245
37246 +#define AR_DATABUF_SIZE 0x0060
37247 +#define AR_DATABUF_SIZE_MASK 0x00000FFF
37248 +
37249 #define AR_GTXTO 0x0064
37250 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF
37251 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000
37252 @@ -160,9 +169,14 @@
37253 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000
37254 #define AR_CST_TIMEOUT_LIMIT_S 16
37255
37256 +#define AR_HP_RXDP 0x0074
37257 +#define AR_LP_RXDP 0x0078
37258 +
37259 #define AR_ISR 0x0080
37260 #define AR_ISR_RXOK 0x00000001
37261 #define AR_ISR_RXDESC 0x00000002
37262 +#define AR_ISR_HP_RXOK 0x00000001
37263 +#define AR_ISR_LP_RXOK 0x00000002
37264 #define AR_ISR_RXERR 0x00000004
37265 #define AR_ISR_RXNOPKT 0x00000008
37266 #define AR_ISR_RXEOL 0x00000010
37267 @@ -232,7 +246,6 @@
37268 #define AR_ISR_S5_TIMER_THRESH 0x0007FE00
37269 #define AR_ISR_S5_TIM_TIMER 0x00000010
37270 #define AR_ISR_S5_DTIM_TIMER 0x00000020
37271 -#define AR_ISR_S5_S 0x00d8
37272 #define AR_IMR_S5 0x00b8
37273 #define AR_IMR_S5_TIM_TIMER 0x00000010
37274 #define AR_IMR_S5_DTIM_TIMER 0x00000020
37275 @@ -240,7 +253,6 @@
37276 #define AR_ISR_S5_GENTIMER_TRIG_S 0
37277 #define AR_ISR_S5_GENTIMER_THRESH 0xFF800000
37278 #define AR_ISR_S5_GENTIMER_THRESH_S 16
37279 -#define AR_ISR_S5_S 0x00d8
37280 #define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80
37281 #define AR_IMR_S5_GENTIMER_TRIG_S 0
37282 #define AR_IMR_S5_GENTIMER_THRESH 0xFF800000
37283 @@ -249,6 +261,8 @@
37284 #define AR_IMR 0x00a0
37285 #define AR_IMR_RXOK 0x00000001
37286 #define AR_IMR_RXDESC 0x00000002
37287 +#define AR_IMR_RXOK_HP 0x00000001
37288 +#define AR_IMR_RXOK_LP 0x00000002
37289 #define AR_IMR_RXERR 0x00000004
37290 #define AR_IMR_RXNOPKT 0x00000008
37291 #define AR_IMR_RXEOL 0x00000010
37292 @@ -332,10 +346,10 @@
37293 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000
37294 #define AR_ISR_S1_QCU_TXEOL_S 16
37295
37296 -#define AR_ISR_S2_S 0x00cc
37297 -#define AR_ISR_S3_S 0x00d0
37298 -#define AR_ISR_S4_S 0x00d4
37299 -#define AR_ISR_S5_S 0x00d8
37300 +#define AR_ISR_S2_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d0 : 0x00cc)
37301 +#define AR_ISR_S3_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d4 : 0x00d0)
37302 +#define AR_ISR_S4_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d8 : 0x00d4)
37303 +#define AR_ISR_S5_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00dc : 0x00d8)
37304 #define AR_DMADBG_0 0x00e0
37305 #define AR_DMADBG_1 0x00e4
37306 #define AR_DMADBG_2 0x00e8
37307 @@ -369,6 +383,9 @@
37308 #define AR_Q9_TXDP 0x0824
37309 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2))
37310
37311 +#define AR_Q_STATUS_RING_START 0x830
37312 +#define AR_Q_STATUS_RING_END 0x834
37313 +
37314 #define AR_Q_TXE 0x0840
37315 #define AR_Q_TXE_M 0x000003FF
37316
37317 @@ -461,6 +478,9 @@
37318 #define AR_Q_RDYTIMESHDN 0x0a40
37319 #define AR_Q_RDYTIMESHDN_M 0x000003FF
37320
37321 +/* MAC Descriptor CRC check */
37322 +#define AR_Q_DESC_CRCCHK 0xa44
37323 +#define AR_Q_DESC_CRCCHK_EN 1 /* Enable CRC check on the descriptor fetched from host */
37324
37325 #define AR_NUM_DCU 10
37326 #define AR_DCU_0 0x0001
37327 @@ -759,6 +779,8 @@
37328 #define AR_SREV_VERSION_9271 0x140
37329 #define AR_SREV_REVISION_9271_10 0
37330 #define AR_SREV_REVISION_9271_11 1
37331 +#define AR_SREV_VERSION_9300 0x1c0
37332 +#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
37333
37334 #define AR_SREV_5416(_ah) \
37335 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
37336 @@ -844,6 +866,15 @@
37337 #define AR_SREV_9271_11(_ah) \
37338 (AR_SREV_9271(_ah) && \
37339 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11))
37340 +#define AR_SREV_9300(_ah) \
37341 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))
37342 +#define AR_SREV_9300_20(_ah) \
37343 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
37344 + ((_ah)->hw_version.macRev == AR_SREV_REVISION_9300_20))
37345 +#define AR_SREV_9300_20_OR_LATER(_ah) \
37346 + (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9300) || \
37347 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
37348 + ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9300_20)))
37349
37350 #define AR_SREV_9285E_20(_ah) \
37351 (AR_SREV_9285_12_OR_LATER(_ah) && \
37352 @@ -945,6 +976,7 @@ enum {
37353 #define AR9285_NUM_GPIO 12
37354 #define AR9287_NUM_GPIO 11
37355 #define AR9271_NUM_GPIO 16
37356 +#define AR9300_NUM_GPIO 17
37357
37358 #define AR_GPIO_IN_OUT 0x4048
37359 #define AR_GPIO_IN_VAL 0x0FFFC000
37360 @@ -957,19 +989,21 @@ enum {
37361 #define AR9287_GPIO_IN_VAL_S 11
37362 #define AR9271_GPIO_IN_VAL 0xFFFF0000
37363 #define AR9271_GPIO_IN_VAL_S 16
37364 +#define AR9300_GPIO_IN_VAL 0x0001FFFF
37365 +#define AR9300_GPIO_IN_VAL_S 0
37366
37367 -#define AR_GPIO_OE_OUT 0x404c
37368 +#define AR_GPIO_OE_OUT (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c)
37369 #define AR_GPIO_OE_OUT_DRV 0x3
37370 #define AR_GPIO_OE_OUT_DRV_NO 0x0
37371 #define AR_GPIO_OE_OUT_DRV_LOW 0x1
37372 #define AR_GPIO_OE_OUT_DRV_HI 0x2
37373 #define AR_GPIO_OE_OUT_DRV_ALL 0x3
37374
37375 -#define AR_GPIO_INTR_POL 0x4050
37376 -#define AR_GPIO_INTR_POL_VAL 0x00001FFF
37377 +#define AR_GPIO_INTR_POL (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050)
37378 +#define AR_GPIO_INTR_POL_VAL 0x0001FFFF
37379 #define AR_GPIO_INTR_POL_VAL_S 0
37380
37381 -#define AR_GPIO_INPUT_EN_VAL 0x4054
37382 +#define AR_GPIO_INPUT_EN_VAL (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054)
37383 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004
37384 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2
37385 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008
37386 @@ -987,13 +1021,13 @@ enum {
37387 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
37388 #define AR_GPIO_JTAG_DISABLE 0x00020000
37389
37390 -#define AR_GPIO_INPUT_MUX1 0x4058
37391 +#define AR_GPIO_INPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058)
37392 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000
37393 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16
37394 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00
37395 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8
37396
37397 -#define AR_GPIO_INPUT_MUX2 0x405c
37398 +#define AR_GPIO_INPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c)
37399 #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f
37400 #define AR_GPIO_INPUT_MUX2_CLK25_S 0
37401 #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0
37402 @@ -1001,13 +1035,13 @@ enum {
37403 #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00
37404 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8
37405
37406 -#define AR_GPIO_OUTPUT_MUX1 0x4060
37407 -#define AR_GPIO_OUTPUT_MUX2 0x4064
37408 -#define AR_GPIO_OUTPUT_MUX3 0x4068
37409 +#define AR_GPIO_OUTPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060)
37410 +#define AR_GPIO_OUTPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064)
37411 +#define AR_GPIO_OUTPUT_MUX3 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068)
37412
37413 -#define AR_INPUT_STATE 0x406c
37414 +#define AR_INPUT_STATE (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c)
37415
37416 -#define AR_EEPROM_STATUS_DATA 0x407c
37417 +#define AR_EEPROM_STATUS_DATA (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c)
37418 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
37419 #define AR_EEPROM_STATUS_DATA_VAL_S 0
37420 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
37421 @@ -1015,13 +1049,24 @@ enum {
37422 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
37423 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
37424
37425 -#define AR_OBS 0x4080
37426 +#define AR_OBS (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080)
37427
37428 -#define AR_GPIO_PDPU 0x4088
37429 +#define AR_GPIO_PDPU (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)
37430
37431 -#define AR_PCIE_MSI 0x4094
37432 +#define AR_PCIE_MSI (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094)
37433 #define AR_PCIE_MSI_ENABLE 0x00000001
37434
37435 +#define AR_INTR_PRIO_SYNC_ENABLE 0x40c4
37436 +#define AR_INTR_PRIO_ASYNC_MASK 0x40c8
37437 +#define AR_INTR_PRIO_SYNC_MASK 0x40cc
37438 +#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
37439 +
37440 +#define AR_RTC_9300_PLL_DIV 0x000003ff
37441 +#define AR_RTC_9300_PLL_DIV_S 0
37442 +#define AR_RTC_9300_PLL_REFDIV 0x00003C00
37443 +#define AR_RTC_9300_PLL_REFDIV_S 10
37444 +#define AR_RTC_9300_PLL_CLKSEL 0x0000C000
37445 +#define AR_RTC_9300_PLL_CLKSEL_S 14
37446
37447 #define AR_RTC_9160_PLL_DIV 0x000003ff
37448 #define AR_RTC_9160_PLL_DIV_S 0
37449 @@ -1039,6 +1084,16 @@ enum {
37450 #define AR_RTC_RC_COLD_RESET 0x00000004
37451 #define AR_RTC_RC_WARM_RESET 0x00000008
37452
37453 +/* Crystal Control */
37454 +#define AR_RTC_XTAL_CONTROL 0x7004
37455 +
37456 +/* Reg Control 0 */
37457 +#define AR_RTC_REG_CONTROL0 0x7008
37458 +
37459 +/* Reg Control 1 */
37460 +#define AR_RTC_REG_CONTROL1 0x700c
37461 +#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001
37462 +
37463 #define AR_RTC_PLL_CONTROL \
37464 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
37465
37466 @@ -1069,6 +1124,7 @@ enum {
37467 #define AR_RTC_SLEEP_CLK \
37468 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)
37469 #define AR_RTC_FORCE_DERIVED_CLK 0x2
37470 +#define AR_RTC_FORCE_SWREG_PRD 0x00000004
37471
37472 #define AR_RTC_FORCE_WAKE \
37473 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)
37474 @@ -1533,7 +1589,7 @@ enum {
37475 #define AR_TSFOOR_THRESHOLD 0x813c
37476 #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF
37477
37478 -#define AR_PHY_ERR_EIFS_MASK 8144
37479 +#define AR_PHY_ERR_EIFS_MASK 0x8144
37480
37481 #define AR_PHY_ERR_3 0x8168
37482 #define AR_PHY_ERR_3_COUNT 0x00FFFFFF
37483 @@ -1599,24 +1655,26 @@ enum {
37484 #define AR_FIRST_NDP_TIMER 7
37485 #define AR_NDP2_PERIOD 0x81a0
37486 #define AR_NDP2_TIMER_MODE 0x81c0
37487 -#define AR_NEXT_TBTT_TIMER 0x8200
37488 -#define AR_NEXT_DMA_BEACON_ALERT 0x8204
37489 -#define AR_NEXT_SWBA 0x8208
37490 -#define AR_NEXT_CFP 0x8208
37491 -#define AR_NEXT_HCF 0x820C
37492 -#define AR_NEXT_TIM 0x8210
37493 -#define AR_NEXT_DTIM 0x8214
37494 -#define AR_NEXT_QUIET_TIMER 0x8218
37495 -#define AR_NEXT_NDP_TIMER 0x821C
37496 -
37497 -#define AR_BEACON_PERIOD 0x8220
37498 -#define AR_DMA_BEACON_PERIOD 0x8224
37499 -#define AR_SWBA_PERIOD 0x8228
37500 -#define AR_HCF_PERIOD 0x822C
37501 -#define AR_TIM_PERIOD 0x8230
37502 -#define AR_DTIM_PERIOD 0x8234
37503 -#define AR_QUIET_PERIOD 0x8238
37504 -#define AR_NDP_PERIOD 0x823C
37505 +
37506 +#define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2))
37507 +#define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0)
37508 +#define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1)
37509 +#define AR_NEXT_SWBA AR_GEN_TIMERS(2)
37510 +#define AR_NEXT_CFP AR_GEN_TIMERS(2)
37511 +#define AR_NEXT_HCF AR_GEN_TIMERS(3)
37512 +#define AR_NEXT_TIM AR_GEN_TIMERS(4)
37513 +#define AR_NEXT_DTIM AR_GEN_TIMERS(5)
37514 +#define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6)
37515 +#define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7)
37516 +
37517 +#define AR_BEACON_PERIOD AR_GEN_TIMERS(8)
37518 +#define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9)
37519 +#define AR_SWBA_PERIOD AR_GEN_TIMERS(10)
37520 +#define AR_HCF_PERIOD AR_GEN_TIMERS(11)
37521 +#define AR_TIM_PERIOD AR_GEN_TIMERS(12)
37522 +#define AR_DTIM_PERIOD AR_GEN_TIMERS(13)
37523 +#define AR_QUIET_PERIOD AR_GEN_TIMERS(14)
37524 +#define AR_NDP_PERIOD AR_GEN_TIMERS(15)
37525
37526 #define AR_TIMER_MODE 0x8240
37527 #define AR_TBTT_TIMER_EN 0x00000001
37528 @@ -1730,4 +1788,32 @@ enum {
37529 #define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */
37530 #define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
37531
37532 +#define AR_AGG_WEP_ENABLE_FIX 0x00000008 /* This allows the use of AR_AGG_WEP_ENABLE */
37533 +#define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search
37534 + * based on both MAC Address and Key ID.
37535 + * If bit is 0, then Multicast search is
37536 + * based on MAC address only.
37537 + * For Merlin and above only.
37538 + */
37539 +#define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature,
37540 + * when it is enable, AGG_WEP would takes
37541 + * charge of the encryption interface of
37542 + * pcu_txsm.
37543 + */
37544 +
37545 +#define AR9300_SM_BASE 0xa200
37546 +#define AR9002_PHY_AGC_CONTROL 0x9860
37547 +#define AR9003_PHY_AGC_CONTROL AR9300_SM_BASE + 0xc4
37548 +#define AR_PHY_AGC_CONTROL (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL)
37549 +#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */
37550 +#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */
37551 +#define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */
37552 +#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */
37553 +#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */
37554 +#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */
37555 +#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */
37556 +#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */
37557 +#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0
37558 +#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6
37559 +
37560 #endif
37561 diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
37562 index 02df4cb..c0de453 100644
37563 --- a/drivers/net/wireless/ath/ath9k/xmit.c
37564 +++ b/drivers/net/wireless/ath/ath9k/xmit.c
37565 @@ -91,7 +91,6 @@ static int ath_max_4ms_framelen[3][16] = {
37566 }
37567 };
37568
37569 -
37570 /*********************/
37571 /* Aggregation logic */
37572 /*********************/
37573 @@ -279,7 +278,7 @@ static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
37574 tbf->aphy = bf->aphy;
37575 tbf->bf_mpdu = bf->bf_mpdu;
37576 tbf->bf_buf_addr = bf->bf_buf_addr;
37577 - *(tbf->bf_desc) = *(bf->bf_desc);
37578 + memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
37579 tbf->bf_state = bf->bf_state;
37580 tbf->bf_dmacontext = bf->bf_dmacontext;
37581
37582 @@ -358,8 +357,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
37583 /* transmit completion */
37584 acked_cnt++;
37585 } else {
37586 - if (!(tid->state & AGGR_CLEANUP) &&
37587 - ts->ts_flags != ATH9K_TX_SW_ABORTED) {
37588 + if (!(tid->state & AGGR_CLEANUP) && !bf_last->bf_tx_aborted) {
37589 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
37590 ath_tx_set_retry(sc, txq, bf);
37591 txpending = 1;
37592 @@ -378,7 +376,8 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
37593 }
37594 }
37595
37596 - if (bf_next == NULL) {
37597 + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
37598 + bf_next == NULL) {
37599 /*
37600 * Make sure the last desc is reclaimed if it
37601 * not a holding desc.
37602 @@ -412,7 +411,8 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
37603 !txfail, sendbar);
37604 } else {
37605 /* retry the un-acked ones */
37606 - if (bf->bf_next == NULL && bf_last->bf_stale) {
37607 + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
37608 + bf->bf_next == NULL && bf_last->bf_stale) {
37609 struct ath_buf *tbf;
37610
37611 tbf = ath_clone_txbuf(sc, bf_last);
37612 @@ -665,7 +665,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
37613 bpad = PADBYTES(al_delta) + (ndelim << 2);
37614
37615 bf->bf_next = NULL;
37616 - bf->bf_desc->ds_link = 0;
37617 + ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
37618
37619 /* link buffers of this frame to the aggregate */
37620 ath_tx_addto_baw(sc, tid, bf);
37621 @@ -673,7 +673,8 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
37622 list_move_tail(&bf->list, bf_q);
37623 if (bf_prev) {
37624 bf_prev->bf_next = bf;
37625 - bf_prev->bf_desc->ds_link = bf->bf_daddr;
37626 + ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
37627 + bf->bf_daddr);
37628 }
37629 bf_prev = bf;
37630
37631 @@ -853,7 +854,7 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
37632 struct ath_hw *ah = sc->sc_ah;
37633 struct ath_common *common = ath9k_hw_common(ah);
37634 struct ath9k_tx_queue_info qi;
37635 - int qnum;
37636 + int qnum, i;
37637
37638 memset(&qi, 0, sizeof(qi));
37639 qi.tqi_subtype = subtype;
37640 @@ -877,11 +878,16 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
37641 * The UAPSD queue is an exception, since we take a desc-
37642 * based intr on the EOSP frames.
37643 */
37644 - if (qtype == ATH9K_TX_QUEUE_UAPSD)
37645 - qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
37646 - else
37647 - qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
37648 - TXQ_FLAG_TXDESCINT_ENABLE;
37649 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
37650 + qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
37651 + TXQ_FLAG_TXERRINT_ENABLE;
37652 + } else {
37653 + if (qtype == ATH9K_TX_QUEUE_UAPSD)
37654 + qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
37655 + else
37656 + qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
37657 + TXQ_FLAG_TXDESCINT_ENABLE;
37658 + }
37659 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
37660 if (qnum == -1) {
37661 /*
37662 @@ -908,6 +914,11 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
37663 txq->axq_depth = 0;
37664 txq->axq_tx_inprogress = false;
37665 sc->tx.txqsetup |= 1<<qnum;
37666 +
37667 + txq->txq_headidx = txq->txq_tailidx = 0;
37668 + for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
37669 + INIT_LIST_HEAD(&txq->txq_fifo[i]);
37670 + INIT_LIST_HEAD(&txq->txq_fifo_pending);
37671 }
37672 return &sc->tx.txq[qnum];
37673 }
37674 @@ -1035,36 +1046,64 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
37675 struct ath_tx_status ts;
37676
37677 memset(&ts, 0, sizeof(ts));
37678 - if (!retry_tx)
37679 - ts.ts_flags = ATH9K_TX_SW_ABORTED;
37680 -
37681 INIT_LIST_HEAD(&bf_head);
37682
37683 for (;;) {
37684 spin_lock_bh(&txq->axq_lock);
37685
37686 - if (list_empty(&txq->axq_q)) {
37687 - txq->axq_link = NULL;
37688 - spin_unlock_bh(&txq->axq_lock);
37689 - break;
37690 - }
37691 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
37692 + if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
37693 + if (list_empty(&txq->txq_fifo_pending)) {
37694 + txq->txq_headidx = txq->txq_tailidx = 0;
37695 + spin_unlock_bh(&txq->axq_lock);
37696 + break;
37697 + }
37698
37699 - bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
37700 + bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
37701 + struct ath_buf, list);
37702
37703 - if (bf->bf_stale) {
37704 - list_del(&bf->list);
37705 - spin_unlock_bh(&txq->axq_lock);
37706 + list_cut_position(
37707 + &txq->txq_fifo[txq->txq_tailidx],
37708 + &txq->txq_fifo_pending,
37709 + &bf->bf_lastbf->list);
37710 + } else {
37711 + bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
37712 + struct ath_buf, list);
37713 + }
37714 + } else {
37715 + if (list_empty(&txq->axq_q)) {
37716 + txq->axq_link = NULL;
37717 + spin_unlock_bh(&txq->axq_lock);
37718 + break;
37719 + }
37720 + bf = list_first_entry(&txq->axq_q, struct ath_buf,
37721 + list);
37722
37723 - spin_lock_bh(&sc->tx.txbuflock);
37724 - list_add_tail(&bf->list, &sc->tx.txbuf);
37725 - spin_unlock_bh(&sc->tx.txbuflock);
37726 - continue;
37727 + if (bf->bf_stale) {
37728 + list_del(&bf->list);
37729 + spin_unlock_bh(&txq->axq_lock);
37730 +
37731 + spin_lock_bh(&sc->tx.txbuflock);
37732 + list_add_tail(&bf->list, &sc->tx.txbuf);
37733 + spin_unlock_bh(&sc->tx.txbuflock);
37734 + continue;
37735 + }
37736 }
37737
37738 lastbf = bf->bf_lastbf;
37739 + if (!retry_tx)
37740 + lastbf->bf_tx_aborted = true;
37741 +
37742
37743 - /* remove ath_buf's of the same mpdu from txq */
37744 - list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
37745 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
37746 + list_cut_position(&bf_head,
37747 + &txq->txq_fifo[txq->txq_tailidx],
37748 + &lastbf->list);
37749 + INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
37750 + } else {
37751 + /* remove ath_buf's of the same mpdu from txq */
37752 + list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
37753 + }
37754 txq->axq_depth--;
37755
37756 spin_unlock_bh(&txq->axq_lock);
37757 @@ -1224,25 +1263,46 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
37758
37759 bf = list_first_entry(head, struct ath_buf, list);
37760
37761 - list_splice_tail_init(head, &txq->axq_q);
37762 - txq->axq_depth++;
37763 -
37764 ath_print(common, ATH_DBG_QUEUE,
37765 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
37766
37767 - if (txq->axq_link == NULL) {
37768 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
37769 + if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
37770 + list_splice_tail_init(head, &txq->txq_fifo_pending);
37771 + return;
37772 + }
37773 + if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
37774 + ath_print(common, ATH_DBG_XMIT,
37775 + "Initializing tx fifo %d which is non-empty\n",
37776 + txq->txq_headidx);
37777 + INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
37778 + list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
37779 + INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
37780 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
37781 ath_print(common, ATH_DBG_XMIT,
37782 "TXDP[%u] = %llx (%p)\n",
37783 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
37784 } else {
37785 - *txq->axq_link = bf->bf_daddr;
37786 - ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
37787 - txq->axq_qnum, txq->axq_link,
37788 - ito64(bf->bf_daddr), bf->bf_desc);
37789 + list_splice_tail_init(head, &txq->axq_q);
37790 +
37791 + if (txq->axq_link == NULL) {
37792 + ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
37793 + ath_print(common, ATH_DBG_XMIT,
37794 + "TXDP[%u] = %llx (%p)\n",
37795 + txq->axq_qnum, ito64(bf->bf_daddr),
37796 + bf->bf_desc);
37797 + } else {
37798 + *txq->axq_link = bf->bf_daddr;
37799 + ath_print(common, ATH_DBG_XMIT,
37800 + "link[%u] (%p)=%llx (%p)\n",
37801 + txq->axq_qnum, txq->axq_link,
37802 + ito64(bf->bf_daddr), bf->bf_desc);
37803 + }
37804 + ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
37805 + &txq->axq_link);
37806 + ath9k_hw_txstart(ah, txq->axq_qnum);
37807 }
37808 - txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
37809 - ath9k_hw_txstart(ah, txq->axq_qnum);
37810 + txq->axq_depth++;
37811 }
37812
37813 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
37814 @@ -1408,8 +1468,7 @@ static void assign_aggr_tid_seqno(struct sk_buff *skb,
37815 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
37816 }
37817
37818 -static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
37819 - struct ath_txq *txq)
37820 +static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
37821 {
37822 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
37823 int flags = 0;
37824 @@ -1420,6 +1479,9 @@ static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
37825 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
37826 flags |= ATH9K_TXDESC_NOACK;
37827
37828 + if (use_ldpc)
37829 + flags |= ATH9K_TXDESC_LDPC;
37830 +
37831 return flags;
37832 }
37833
37834 @@ -1571,6 +1633,7 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
37835 int hdrlen;
37836 __le16 fc;
37837 int padpos, padsize;
37838 + bool use_ldpc = false;
37839
37840 tx_info->pad[0] = 0;
37841 switch (txctl->frame_type) {
37842 @@ -1597,10 +1660,13 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
37843 bf->bf_frmlen -= padsize;
37844 }
37845
37846 - if (conf_is_ht(&hw->conf))
37847 + if (conf_is_ht(&hw->conf)) {
37848 bf->bf_state.bf_type |= BUF_HT;
37849 + if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
37850 + use_ldpc = true;
37851 + }
37852
37853 - bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
37854 + bf->bf_flags = setup_tx_flags(skb, use_ldpc);
37855
37856 bf->bf_keytype = get_hw_crypto_keytype(skb);
37857 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
37858 @@ -1659,8 +1725,7 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
37859 list_add_tail(&bf->list, &bf_head);
37860
37861 ds = bf->bf_desc;
37862 - ds->ds_link = 0;
37863 - ds->ds_data = bf->bf_buf_addr;
37864 + ath9k_hw_set_desc_link(ah, ds, 0);
37865
37866 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
37867 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
37868 @@ -1669,7 +1734,9 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
37869 skb->len, /* segment length */
37870 true, /* first segment */
37871 true, /* last segment */
37872 - ds); /* first descriptor */
37873 + ds, /* first descriptor */
37874 + bf->bf_buf_addr,
37875 + txctl->txq->axq_qnum);
37876
37877 spin_lock_bh(&txctl->txq->axq_lock);
37878
37879 @@ -1896,7 +1963,7 @@ static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
37880 int nbad = 0;
37881 int isaggr = 0;
37882
37883 - if (ts->ts_flags == ATH9K_TX_SW_ABORTED)
37884 + if (bf->bf_tx_aborted)
37885 return 0;
37886
37887 isaggr = bf_isaggr(bf);
37888 @@ -2138,10 +2205,119 @@ void ath_tx_tasklet(struct ath_softc *sc)
37889 }
37890 }
37891
37892 +void ath_tx_edma_tasklet(struct ath_softc *sc)
37893 +{
37894 + struct ath_tx_status txs;
37895 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
37896 + struct ath_hw *ah = sc->sc_ah;
37897 + struct ath_txq *txq;
37898 + struct ath_buf *bf, *lastbf;
37899 + struct list_head bf_head;
37900 + int status;
37901 + int txok;
37902 +
37903 + for (;;) {
37904 + status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
37905 + if (status == -EINPROGRESS)
37906 + break;
37907 + if (status == -EIO) {
37908 + ath_print(common, ATH_DBG_XMIT,
37909 + "Error processing tx status\n");
37910 + break;
37911 + }
37912 +
37913 + /* Skip beacon completions */
37914 + if (txs.qid == sc->beacon.beaconq)
37915 + continue;
37916 +
37917 + txq = &sc->tx.txq[txs.qid];
37918 +
37919 + spin_lock_bh(&txq->axq_lock);
37920 + if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
37921 + spin_unlock_bh(&txq->axq_lock);
37922 + return;
37923 + }
37924 +
37925 + bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
37926 + struct ath_buf, list);
37927 + lastbf = bf->bf_lastbf;
37928 +
37929 + INIT_LIST_HEAD(&bf_head);
37930 + list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
37931 + &lastbf->list);
37932 + INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
37933 + txq->axq_depth--;
37934 + txq->axq_tx_inprogress = false;
37935 + spin_unlock_bh(&txq->axq_lock);
37936 +
37937 + txok = !(txs.ts_status & ATH9K_TXERR_MASK);
37938 +
37939 + if (!bf_isampdu(bf)) {
37940 + bf->bf_retries = txs.ts_longretry;
37941 + if (txs.ts_status & ATH9K_TXERR_XRETRY)
37942 + bf->bf_state.bf_type |= BUF_XRETRY;
37943 + ath_tx_rc_status(bf, &txs, 0, txok, true);
37944 + }
37945 +
37946 + if (bf_isampdu(bf))
37947 + ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok);
37948 + else
37949 + ath_tx_complete_buf(sc, bf, txq, &bf_head,
37950 + &txs, txok, 0);
37951 +
37952 + spin_lock_bh(&txq->axq_lock);
37953 + if (!list_empty(&txq->txq_fifo_pending)) {
37954 + INIT_LIST_HEAD(&bf_head);
37955 + bf = list_first_entry(&txq->txq_fifo_pending,
37956 + struct ath_buf, list);
37957 + list_cut_position(&bf_head, &txq->txq_fifo_pending,
37958 + &bf->bf_lastbf->list);
37959 + ath_tx_txqaddbuf(sc, txq, &bf_head);
37960 + } else if (sc->sc_flags & SC_OP_TXAGGR)
37961 + ath_txq_schedule(sc, txq);
37962 + spin_unlock_bh(&txq->axq_lock);
37963 + }
37964 +}
37965 +
37966 /*****************/
37967 /* Init, Cleanup */
37968 /*****************/
37969
37970 +static int ath_txstatus_setup(struct ath_softc *sc, int size)
37971 +{
37972 + struct ath_descdma *dd = &sc->txsdma;
37973 + u8 txs_len = sc->sc_ah->caps.txs_len;
37974 +
37975 + dd->dd_desc_len = size * txs_len;
37976 + dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
37977 + &dd->dd_desc_paddr, GFP_KERNEL);
37978 + if (!dd->dd_desc)
37979 + return -ENOMEM;
37980 +
37981 + return 0;
37982 +}
37983 +
37984 +static int ath_tx_edma_init(struct ath_softc *sc)
37985 +{
37986 + int err;
37987 +
37988 + err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
37989 + if (!err)
37990 + ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
37991 + sc->txsdma.dd_desc_paddr,
37992 + ATH_TXSTATUS_RING_SIZE);
37993 +
37994 + return err;
37995 +}
37996 +
37997 +static void ath_tx_edma_cleanup(struct ath_softc *sc)
37998 +{
37999 + struct ath_descdma *dd = &sc->txsdma;
38000 +
38001 + dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
38002 + dd->dd_desc_paddr);
38003 +}
38004 +
38005 int ath_tx_init(struct ath_softc *sc, int nbufs)
38006 {
38007 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
38008 @@ -2150,7 +2326,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
38009 spin_lock_init(&sc->tx.txbuflock);
38010
38011 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
38012 - "tx", nbufs, 1);
38013 + "tx", nbufs, 1, 1);
38014 if (error != 0) {
38015 ath_print(common, ATH_DBG_FATAL,
38016 "Failed to allocate tx descriptors: %d\n", error);
38017 @@ -2158,7 +2334,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
38018 }
38019
38020 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
38021 - "beacon", ATH_BCBUF, 1);
38022 + "beacon", ATH_BCBUF, 1, 1);
38023 if (error != 0) {
38024 ath_print(common, ATH_DBG_FATAL,
38025 "Failed to allocate beacon descriptors: %d\n", error);
38026 @@ -2167,6 +2343,12 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
38027
38028 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
38029
38030 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
38031 + error = ath_tx_edma_init(sc);
38032 + if (error)
38033 + goto err;
38034 + }
38035 +
38036 err:
38037 if (error != 0)
38038 ath_tx_cleanup(sc);
38039 @@ -2181,6 +2363,9 @@ void ath_tx_cleanup(struct ath_softc *sc)
38040
38041 if (sc->tx.txdma.dd_desc_len != 0)
38042 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
38043 +
38044 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
38045 + ath_tx_edma_cleanup(sc);
38046 }
38047
38048 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
38049 diff --git a/include/net/mac80211.h b/include/net/mac80211.h
38050 index dcf3c5f..75056dd 100644
38051 --- a/include/net/mac80211.h
38052 +++ b/include/net/mac80211.h
38053 @@ -274,6 +274,7 @@ struct ieee80211_bss_conf {
38054 * @IEEE80211_TX_INTFL_NL80211_FRAME_TX: Frame was requested through nl80211
38055 * MLME command (internal to mac80211 to figure out whether to send TX
38056 * status to user space)
38057 + * @IEEE80211_TX_CTL_LDPC: tells the driver to use LDPC for this frame
38058 */
38059 enum mac80211_tx_control_flags {
38060 IEEE80211_TX_CTL_REQ_TX_STATUS = BIT(0),
38061 @@ -297,6 +298,7 @@ enum mac80211_tx_control_flags {
38062 IEEE80211_TX_INTFL_RETRANSMISSION = BIT(19),
38063 IEEE80211_TX_INTFL_HAS_RADIOTAP = BIT(20),
38064 IEEE80211_TX_INTFL_NL80211_FRAME_TX = BIT(21),
38065 + IEEE80211_TX_CTL_LDPC = BIT(22),
38066 };
38067
38068 /**
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