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ath9k: fix a crash in ath9k_hw_reset on older hw
[openwrt/svn-archive/archive.git] / package / mac80211 / patches / 300-ar9300_support.patch
1 --- a/drivers/net/wireless/ath/ath9k/Makefile
2 +++ b/drivers/net/wireless/ath/ath9k/Makefile
3 @@ -13,16 +13,26 @@ ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
4
5 obj-$(CONFIG_ATH9K) += ath9k.o
6
7 -ath9k_hw-y:= hw.o \
8 +ath9k_hw-y:= \
9 + ar9002_hw.o \
10 + ar9003_hw.o \
11 + hw.o \
12 + ar9003_phy.o \
13 + ar9002_phy.o \
14 + ar5008_phy.o \
15 + ar9002_calib.o \
16 + ar9003_calib.o \
17 + calib.o \
18 eeprom.o \
19 eeprom_def.o \
20 eeprom_4k.o \
21 eeprom_9287.o \
22 - calib.o \
23 ani.o \
24 - phy.o \
25 btcoex.o \
26 mac.o \
27 + ar9002_mac.o \
28 + ar9003_mac.o \
29 + ar9003_eeprom.o
30
31 obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o
32
33 --- a/drivers/net/wireless/ath/ath9k/ani.c
34 +++ b/drivers/net/wireless/ath/ath9k/ani.c
35 @@ -15,6 +15,7 @@
36 */
37
38 #include "hw.h"
39 +#include "hw-ops.h"
40
41 static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
42 struct ath9k_channel *chan)
43 @@ -37,190 +38,6 @@ static int ath9k_hw_get_ani_channel_idx(
44 return 0;
45 }
46
47 -static bool ath9k_hw_ani_control(struct ath_hw *ah,
48 - enum ath9k_ani_cmd cmd, int param)
49 -{
50 - struct ar5416AniState *aniState = ah->curani;
51 - struct ath_common *common = ath9k_hw_common(ah);
52 -
53 - switch (cmd & ah->ani_function) {
54 - case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
55 - u32 level = param;
56 -
57 - if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
58 - ath_print(common, ATH_DBG_ANI,
59 - "level out of range (%u > %u)\n",
60 - level,
61 - (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
62 - return false;
63 - }
64 -
65 - REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
66 - AR_PHY_DESIRED_SZ_TOT_DES,
67 - ah->totalSizeDesired[level]);
68 - REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
69 - AR_PHY_AGC_CTL1_COARSE_LOW,
70 - ah->coarse_low[level]);
71 - REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
72 - AR_PHY_AGC_CTL1_COARSE_HIGH,
73 - ah->coarse_high[level]);
74 - REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
75 - AR_PHY_FIND_SIG_FIRPWR,
76 - ah->firpwr[level]);
77 -
78 - if (level > aniState->noiseImmunityLevel)
79 - ah->stats.ast_ani_niup++;
80 - else if (level < aniState->noiseImmunityLevel)
81 - ah->stats.ast_ani_nidown++;
82 - aniState->noiseImmunityLevel = level;
83 - break;
84 - }
85 - case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
86 - const int m1ThreshLow[] = { 127, 50 };
87 - const int m2ThreshLow[] = { 127, 40 };
88 - const int m1Thresh[] = { 127, 0x4d };
89 - const int m2Thresh[] = { 127, 0x40 };
90 - const int m2CountThr[] = { 31, 16 };
91 - const int m2CountThrLow[] = { 63, 48 };
92 - u32 on = param ? 1 : 0;
93 -
94 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
95 - AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
96 - m1ThreshLow[on]);
97 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
98 - AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
99 - m2ThreshLow[on]);
100 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
101 - AR_PHY_SFCORR_M1_THRESH,
102 - m1Thresh[on]);
103 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
104 - AR_PHY_SFCORR_M2_THRESH,
105 - m2Thresh[on]);
106 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
107 - AR_PHY_SFCORR_M2COUNT_THR,
108 - m2CountThr[on]);
109 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
110 - AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
111 - m2CountThrLow[on]);
112 -
113 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
114 - AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
115 - m1ThreshLow[on]);
116 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
117 - AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
118 - m2ThreshLow[on]);
119 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
120 - AR_PHY_SFCORR_EXT_M1_THRESH,
121 - m1Thresh[on]);
122 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
123 - AR_PHY_SFCORR_EXT_M2_THRESH,
124 - m2Thresh[on]);
125 -
126 - if (on)
127 - REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
128 - AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
129 - else
130 - REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
131 - AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
132 -
133 - if (!on != aniState->ofdmWeakSigDetectOff) {
134 - if (on)
135 - ah->stats.ast_ani_ofdmon++;
136 - else
137 - ah->stats.ast_ani_ofdmoff++;
138 - aniState->ofdmWeakSigDetectOff = !on;
139 - }
140 - break;
141 - }
142 - case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
143 - const int weakSigThrCck[] = { 8, 6 };
144 - u32 high = param ? 1 : 0;
145 -
146 - REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
147 - AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
148 - weakSigThrCck[high]);
149 - if (high != aniState->cckWeakSigThreshold) {
150 - if (high)
151 - ah->stats.ast_ani_cckhigh++;
152 - else
153 - ah->stats.ast_ani_ccklow++;
154 - aniState->cckWeakSigThreshold = high;
155 - }
156 - break;
157 - }
158 - case ATH9K_ANI_FIRSTEP_LEVEL:{
159 - const int firstep[] = { 0, 4, 8 };
160 - u32 level = param;
161 -
162 - if (level >= ARRAY_SIZE(firstep)) {
163 - ath_print(common, ATH_DBG_ANI,
164 - "level out of range (%u > %u)\n",
165 - level,
166 - (unsigned) ARRAY_SIZE(firstep));
167 - return false;
168 - }
169 - REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
170 - AR_PHY_FIND_SIG_FIRSTEP,
171 - firstep[level]);
172 - if (level > aniState->firstepLevel)
173 - ah->stats.ast_ani_stepup++;
174 - else if (level < aniState->firstepLevel)
175 - ah->stats.ast_ani_stepdown++;
176 - aniState->firstepLevel = level;
177 - break;
178 - }
179 - case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
180 - const int cycpwrThr1[] =
181 - { 2, 4, 6, 8, 10, 12, 14, 16 };
182 - u32 level = param;
183 -
184 - if (level >= ARRAY_SIZE(cycpwrThr1)) {
185 - ath_print(common, ATH_DBG_ANI,
186 - "level out of range (%u > %u)\n",
187 - level,
188 - (unsigned) ARRAY_SIZE(cycpwrThr1));
189 - return false;
190 - }
191 - REG_RMW_FIELD(ah, AR_PHY_TIMING5,
192 - AR_PHY_TIMING5_CYCPWR_THR1,
193 - cycpwrThr1[level]);
194 - if (level > aniState->spurImmunityLevel)
195 - ah->stats.ast_ani_spurup++;
196 - else if (level < aniState->spurImmunityLevel)
197 - ah->stats.ast_ani_spurdown++;
198 - aniState->spurImmunityLevel = level;
199 - break;
200 - }
201 - case ATH9K_ANI_PRESENT:
202 - break;
203 - default:
204 - ath_print(common, ATH_DBG_ANI,
205 - "invalid cmd %u\n", cmd);
206 - return false;
207 - }
208 -
209 - ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
210 - ath_print(common, ATH_DBG_ANI,
211 - "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
212 - "ofdmWeakSigDetectOff=%d\n",
213 - aniState->noiseImmunityLevel,
214 - aniState->spurImmunityLevel,
215 - !aniState->ofdmWeakSigDetectOff);
216 - ath_print(common, ATH_DBG_ANI,
217 - "cckWeakSigThreshold=%d, "
218 - "firstepLevel=%d, listenTime=%d\n",
219 - aniState->cckWeakSigThreshold,
220 - aniState->firstepLevel,
221 - aniState->listenTime);
222 - ath_print(common, ATH_DBG_ANI,
223 - "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
224 - aniState->cycleCount,
225 - aniState->ofdmPhyErrCount,
226 - aniState->cckPhyErrCount);
227 -
228 - return true;
229 -}
230 -
231 static void ath9k_hw_update_mibstats(struct ath_hw *ah,
232 struct ath9k_mib_stats *stats)
233 {
234 --- /dev/null
235 +++ b/drivers/net/wireless/ath/ath9k/ar5008_initvals.h
236 @@ -0,0 +1,742 @@
237 +/*
238 + * Copyright (c) 2008-2009 Atheros Communications Inc.
239 + *
240 + * Permission to use, copy, modify, and/or distribute this software for any
241 + * purpose with or without fee is hereby granted, provided that the above
242 + * copyright notice and this permission notice appear in all copies.
243 + *
244 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
245 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
246 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
247 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
248 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
249 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
250 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
251 + */
252 +
253 +#ifndef INITVALS_AR5008_H
254 +#define INITVALS_AR5008_H
255 +
256 +static const u32 ar5416Modes[][6] = {
257 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
258 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
259 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
260 + { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
261 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
262 + { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
263 + { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
264 + { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
265 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
266 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
267 + { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
268 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
269 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
270 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
271 + { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
272 + { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
273 + { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
274 + { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
275 + { 0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de, 0x6c48b0de },
276 + { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
277 + { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
278 + { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 },
279 + { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
280 + { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 },
281 + { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
282 + { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
283 + { 0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134, 0x00000134 },
284 + { 0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b },
285 + { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
286 + { 0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
287 + { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
288 + { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
289 + { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 },
290 + { 0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 },
291 + { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
292 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
293 + { 0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c },
294 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
295 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
296 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
297 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
298 + { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
299 + { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
300 + { 0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
301 + { 0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
302 + { 0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
303 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
304 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
305 + { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
306 + { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
307 + { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
308 + { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
309 + { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
310 + { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
311 + { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
312 + { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
313 + { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
314 + { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
315 + { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
316 + { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
317 + { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
318 + { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
319 + { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
320 +};
321 +
322 +static const u32 ar5416Common[][2] = {
323 + { 0x0000000c, 0x00000000 },
324 + { 0x00000030, 0x00020015 },
325 + { 0x00000034, 0x00000005 },
326 + { 0x00000040, 0x00000000 },
327 + { 0x00000044, 0x00000008 },
328 + { 0x00000048, 0x00000008 },
329 + { 0x0000004c, 0x00000010 },
330 + { 0x00000050, 0x00000000 },
331 + { 0x00000054, 0x0000001f },
332 + { 0x00000800, 0x00000000 },
333 + { 0x00000804, 0x00000000 },
334 + { 0x00000808, 0x00000000 },
335 + { 0x0000080c, 0x00000000 },
336 + { 0x00000810, 0x00000000 },
337 + { 0x00000814, 0x00000000 },
338 + { 0x00000818, 0x00000000 },
339 + { 0x0000081c, 0x00000000 },
340 + { 0x00000820, 0x00000000 },
341 + { 0x00000824, 0x00000000 },
342 + { 0x00001040, 0x002ffc0f },
343 + { 0x00001044, 0x002ffc0f },
344 + { 0x00001048, 0x002ffc0f },
345 + { 0x0000104c, 0x002ffc0f },
346 + { 0x00001050, 0x002ffc0f },
347 + { 0x00001054, 0x002ffc0f },
348 + { 0x00001058, 0x002ffc0f },
349 + { 0x0000105c, 0x002ffc0f },
350 + { 0x00001060, 0x002ffc0f },
351 + { 0x00001064, 0x002ffc0f },
352 + { 0x00001230, 0x00000000 },
353 + { 0x00001270, 0x00000000 },
354 + { 0x00001038, 0x00000000 },
355 + { 0x00001078, 0x00000000 },
356 + { 0x000010b8, 0x00000000 },
357 + { 0x000010f8, 0x00000000 },
358 + { 0x00001138, 0x00000000 },
359 + { 0x00001178, 0x00000000 },
360 + { 0x000011b8, 0x00000000 },
361 + { 0x000011f8, 0x00000000 },
362 + { 0x00001238, 0x00000000 },
363 + { 0x00001278, 0x00000000 },
364 + { 0x000012b8, 0x00000000 },
365 + { 0x000012f8, 0x00000000 },
366 + { 0x00001338, 0x00000000 },
367 + { 0x00001378, 0x00000000 },
368 + { 0x000013b8, 0x00000000 },
369 + { 0x000013f8, 0x00000000 },
370 + { 0x00001438, 0x00000000 },
371 + { 0x00001478, 0x00000000 },
372 + { 0x000014b8, 0x00000000 },
373 + { 0x000014f8, 0x00000000 },
374 + { 0x00001538, 0x00000000 },
375 + { 0x00001578, 0x00000000 },
376 + { 0x000015b8, 0x00000000 },
377 + { 0x000015f8, 0x00000000 },
378 + { 0x00001638, 0x00000000 },
379 + { 0x00001678, 0x00000000 },
380 + { 0x000016b8, 0x00000000 },
381 + { 0x000016f8, 0x00000000 },
382 + { 0x00001738, 0x00000000 },
383 + { 0x00001778, 0x00000000 },
384 + { 0x000017b8, 0x00000000 },
385 + { 0x000017f8, 0x00000000 },
386 + { 0x0000103c, 0x00000000 },
387 + { 0x0000107c, 0x00000000 },
388 + { 0x000010bc, 0x00000000 },
389 + { 0x000010fc, 0x00000000 },
390 + { 0x0000113c, 0x00000000 },
391 + { 0x0000117c, 0x00000000 },
392 + { 0x000011bc, 0x00000000 },
393 + { 0x000011fc, 0x00000000 },
394 + { 0x0000123c, 0x00000000 },
395 + { 0x0000127c, 0x00000000 },
396 + { 0x000012bc, 0x00000000 },
397 + { 0x000012fc, 0x00000000 },
398 + { 0x0000133c, 0x00000000 },
399 + { 0x0000137c, 0x00000000 },
400 + { 0x000013bc, 0x00000000 },
401 + { 0x000013fc, 0x00000000 },
402 + { 0x0000143c, 0x00000000 },
403 + { 0x0000147c, 0x00000000 },
404 + { 0x00004030, 0x00000002 },
405 + { 0x0000403c, 0x00000002 },
406 + { 0x00007010, 0x00000000 },
407 + { 0x00007038, 0x000004c2 },
408 + { 0x00008004, 0x00000000 },
409 + { 0x00008008, 0x00000000 },
410 + { 0x0000800c, 0x00000000 },
411 + { 0x00008018, 0x00000700 },
412 + { 0x00008020, 0x00000000 },
413 + { 0x00008038, 0x00000000 },
414 + { 0x0000803c, 0x00000000 },
415 + { 0x00008048, 0x40000000 },
416 + { 0x00008054, 0x00000000 },
417 + { 0x00008058, 0x00000000 },
418 + { 0x0000805c, 0x000fc78f },
419 + { 0x00008060, 0x0000000f },
420 + { 0x00008064, 0x00000000 },
421 + { 0x000080c0, 0x2a82301a },
422 + { 0x000080c4, 0x05dc01e0 },
423 + { 0x000080c8, 0x1f402710 },
424 + { 0x000080cc, 0x01f40000 },
425 + { 0x000080d0, 0x00001e00 },
426 + { 0x000080d4, 0x00000000 },
427 + { 0x000080d8, 0x00400000 },
428 + { 0x000080e0, 0xffffffff },
429 + { 0x000080e4, 0x0000ffff },
430 + { 0x000080e8, 0x003f3f3f },
431 + { 0x000080ec, 0x00000000 },
432 + { 0x000080f0, 0x00000000 },
433 + { 0x000080f4, 0x00000000 },
434 + { 0x000080f8, 0x00000000 },
435 + { 0x000080fc, 0x00020000 },
436 + { 0x00008100, 0x00020000 },
437 + { 0x00008104, 0x00000001 },
438 + { 0x00008108, 0x00000052 },
439 + { 0x0000810c, 0x00000000 },
440 + { 0x00008110, 0x00000168 },
441 + { 0x00008118, 0x000100aa },
442 + { 0x0000811c, 0x00003210 },
443 + { 0x00008124, 0x00000000 },
444 + { 0x00008128, 0x00000000 },
445 + { 0x0000812c, 0x00000000 },
446 + { 0x00008130, 0x00000000 },
447 + { 0x00008134, 0x00000000 },
448 + { 0x00008138, 0x00000000 },
449 + { 0x0000813c, 0x00000000 },
450 + { 0x00008144, 0xffffffff },
451 + { 0x00008168, 0x00000000 },
452 + { 0x0000816c, 0x00000000 },
453 + { 0x00008170, 0x32143320 },
454 + { 0x00008174, 0xfaa4fa50 },
455 + { 0x00008178, 0x00000100 },
456 + { 0x0000817c, 0x00000000 },
457 + { 0x000081c4, 0x00000000 },
458 + { 0x000081ec, 0x00000000 },
459 + { 0x000081f0, 0x00000000 },
460 + { 0x000081f4, 0x00000000 },
461 + { 0x000081f8, 0x00000000 },
462 + { 0x000081fc, 0x00000000 },
463 + { 0x00008200, 0x00000000 },
464 + { 0x00008204, 0x00000000 },
465 + { 0x00008208, 0x00000000 },
466 + { 0x0000820c, 0x00000000 },
467 + { 0x00008210, 0x00000000 },
468 + { 0x00008214, 0x00000000 },
469 + { 0x00008218, 0x00000000 },
470 + { 0x0000821c, 0x00000000 },
471 + { 0x00008220, 0x00000000 },
472 + { 0x00008224, 0x00000000 },
473 + { 0x00008228, 0x00000000 },
474 + { 0x0000822c, 0x00000000 },
475 + { 0x00008230, 0x00000000 },
476 + { 0x00008234, 0x00000000 },
477 + { 0x00008238, 0x00000000 },
478 + { 0x0000823c, 0x00000000 },
479 + { 0x00008240, 0x00100000 },
480 + { 0x00008244, 0x0010f400 },
481 + { 0x00008248, 0x00000100 },
482 + { 0x0000824c, 0x0001e800 },
483 + { 0x00008250, 0x00000000 },
484 + { 0x00008254, 0x00000000 },
485 + { 0x00008258, 0x00000000 },
486 + { 0x0000825c, 0x400000ff },
487 + { 0x00008260, 0x00080922 },
488 + { 0x00008264, 0xa8000010 },
489 + { 0x00008270, 0x00000000 },
490 + { 0x00008274, 0x40000000 },
491 + { 0x00008278, 0x003e4180 },
492 + { 0x0000827c, 0x00000000 },
493 + { 0x00008284, 0x0000002c },
494 + { 0x00008288, 0x0000002c },
495 + { 0x0000828c, 0x00000000 },
496 + { 0x00008294, 0x00000000 },
497 + { 0x00008298, 0x00000000 },
498 + { 0x00008300, 0x00000000 },
499 + { 0x00008304, 0x00000000 },
500 + { 0x00008308, 0x00000000 },
501 + { 0x0000830c, 0x00000000 },
502 + { 0x00008310, 0x00000000 },
503 + { 0x00008314, 0x00000000 },
504 + { 0x00008318, 0x00000000 },
505 + { 0x00008328, 0x00000000 },
506 + { 0x0000832c, 0x00000007 },
507 + { 0x00008330, 0x00000302 },
508 + { 0x00008334, 0x00000e00 },
509 + { 0x00008338, 0x00070000 },
510 + { 0x0000833c, 0x00000000 },
511 + { 0x00008340, 0x000107ff },
512 + { 0x00009808, 0x00000000 },
513 + { 0x0000980c, 0xad848e19 },
514 + { 0x00009810, 0x7d14e000 },
515 + { 0x00009814, 0x9c0a9f6b },
516 + { 0x0000981c, 0x00000000 },
517 + { 0x0000982c, 0x0000a000 },
518 + { 0x00009830, 0x00000000 },
519 + { 0x0000983c, 0x00200400 },
520 + { 0x00009840, 0x206a002e },
521 + { 0x0000984c, 0x1284233c },
522 + { 0x00009854, 0x00000859 },
523 + { 0x00009900, 0x00000000 },
524 + { 0x00009904, 0x00000000 },
525 + { 0x00009908, 0x00000000 },
526 + { 0x0000990c, 0x00000000 },
527 + { 0x0000991c, 0x10000fff },
528 + { 0x00009920, 0x05100000 },
529 + { 0x0000a920, 0x05100000 },
530 + { 0x0000b920, 0x05100000 },
531 + { 0x00009928, 0x00000001 },
532 + { 0x0000992c, 0x00000004 },
533 + { 0x00009934, 0x1e1f2022 },
534 + { 0x00009938, 0x0a0b0c0d },
535 + { 0x0000993c, 0x00000000 },
536 + { 0x00009948, 0x9280b212 },
537 + { 0x0000994c, 0x00020028 },
538 + { 0x00009954, 0x5d50e188 },
539 + { 0x00009958, 0x00081fff },
540 + { 0x0000c95c, 0x004b6a8e },
541 + { 0x0000c968, 0x000003ce },
542 + { 0x00009970, 0x190fb515 },
543 + { 0x00009974, 0x00000000 },
544 + { 0x00009978, 0x00000001 },
545 + { 0x0000997c, 0x00000000 },
546 + { 0x00009980, 0x00000000 },
547 + { 0x00009984, 0x00000000 },
548 + { 0x00009988, 0x00000000 },
549 + { 0x0000998c, 0x00000000 },
550 + { 0x00009990, 0x00000000 },
551 + { 0x00009994, 0x00000000 },
552 + { 0x00009998, 0x00000000 },
553 + { 0x0000999c, 0x00000000 },
554 + { 0x000099a0, 0x00000000 },
555 + { 0x000099a4, 0x00000001 },
556 + { 0x000099a8, 0x001fff00 },
557 + { 0x000099ac, 0x00000000 },
558 + { 0x000099b0, 0x03051000 },
559 + { 0x000099dc, 0x00000000 },
560 + { 0x000099e0, 0x00000200 },
561 + { 0x000099e4, 0xaaaaaaaa },
562 + { 0x000099e8, 0x3c466478 },
563 + { 0x000099ec, 0x000000aa },
564 + { 0x000099fc, 0x00001042 },
565 + { 0x00009b00, 0x00000000 },
566 + { 0x00009b04, 0x00000001 },
567 + { 0x00009b08, 0x00000002 },
568 + { 0x00009b0c, 0x00000003 },
569 + { 0x00009b10, 0x00000004 },
570 + { 0x00009b14, 0x00000005 },
571 + { 0x00009b18, 0x00000008 },
572 + { 0x00009b1c, 0x00000009 },
573 + { 0x00009b20, 0x0000000a },
574 + { 0x00009b24, 0x0000000b },
575 + { 0x00009b28, 0x0000000c },
576 + { 0x00009b2c, 0x0000000d },
577 + { 0x00009b30, 0x00000010 },
578 + { 0x00009b34, 0x00000011 },
579 + { 0x00009b38, 0x00000012 },
580 + { 0x00009b3c, 0x00000013 },
581 + { 0x00009b40, 0x00000014 },
582 + { 0x00009b44, 0x00000015 },
583 + { 0x00009b48, 0x00000018 },
584 + { 0x00009b4c, 0x00000019 },
585 + { 0x00009b50, 0x0000001a },
586 + { 0x00009b54, 0x0000001b },
587 + { 0x00009b58, 0x0000001c },
588 + { 0x00009b5c, 0x0000001d },
589 + { 0x00009b60, 0x00000020 },
590 + { 0x00009b64, 0x00000021 },
591 + { 0x00009b68, 0x00000022 },
592 + { 0x00009b6c, 0x00000023 },
593 + { 0x00009b70, 0x00000024 },
594 + { 0x00009b74, 0x00000025 },
595 + { 0x00009b78, 0x00000028 },
596 + { 0x00009b7c, 0x00000029 },
597 + { 0x00009b80, 0x0000002a },
598 + { 0x00009b84, 0x0000002b },
599 + { 0x00009b88, 0x0000002c },
600 + { 0x00009b8c, 0x0000002d },
601 + { 0x00009b90, 0x00000030 },
602 + { 0x00009b94, 0x00000031 },
603 + { 0x00009b98, 0x00000032 },
604 + { 0x00009b9c, 0x00000033 },
605 + { 0x00009ba0, 0x00000034 },
606 + { 0x00009ba4, 0x00000035 },
607 + { 0x00009ba8, 0x00000035 },
608 + { 0x00009bac, 0x00000035 },
609 + { 0x00009bb0, 0x00000035 },
610 + { 0x00009bb4, 0x00000035 },
611 + { 0x00009bb8, 0x00000035 },
612 + { 0x00009bbc, 0x00000035 },
613 + { 0x00009bc0, 0x00000035 },
614 + { 0x00009bc4, 0x00000035 },
615 + { 0x00009bc8, 0x00000035 },
616 + { 0x00009bcc, 0x00000035 },
617 + { 0x00009bd0, 0x00000035 },
618 + { 0x00009bd4, 0x00000035 },
619 + { 0x00009bd8, 0x00000035 },
620 + { 0x00009bdc, 0x00000035 },
621 + { 0x00009be0, 0x00000035 },
622 + { 0x00009be4, 0x00000035 },
623 + { 0x00009be8, 0x00000035 },
624 + { 0x00009bec, 0x00000035 },
625 + { 0x00009bf0, 0x00000035 },
626 + { 0x00009bf4, 0x00000035 },
627 + { 0x00009bf8, 0x00000010 },
628 + { 0x00009bfc, 0x0000001a },
629 + { 0x0000a210, 0x40806333 },
630 + { 0x0000a214, 0x00106c10 },
631 + { 0x0000a218, 0x009c4060 },
632 + { 0x0000a220, 0x018830c6 },
633 + { 0x0000a224, 0x00000400 },
634 + { 0x0000a228, 0x00000bb5 },
635 + { 0x0000a22c, 0x00000011 },
636 + { 0x0000a234, 0x20202020 },
637 + { 0x0000a238, 0x20202020 },
638 + { 0x0000a23c, 0x13c889af },
639 + { 0x0000a240, 0x38490a20 },
640 + { 0x0000a244, 0x00007bb6 },
641 + { 0x0000a248, 0x0fff3ffc },
642 + { 0x0000a24c, 0x00000001 },
643 + { 0x0000a250, 0x0000a000 },
644 + { 0x0000a254, 0x00000000 },
645 + { 0x0000a258, 0x0cc75380 },
646 + { 0x0000a25c, 0x0f0f0f01 },
647 + { 0x0000a260, 0xdfa91f01 },
648 + { 0x0000a268, 0x00000000 },
649 + { 0x0000a26c, 0x0e79e5c6 },
650 + { 0x0000b26c, 0x0e79e5c6 },
651 + { 0x0000c26c, 0x0e79e5c6 },
652 + { 0x0000d270, 0x00820820 },
653 + { 0x0000a278, 0x1ce739ce },
654 + { 0x0000a27c, 0x051701ce },
655 + { 0x0000a338, 0x00000000 },
656 + { 0x0000a33c, 0x00000000 },
657 + { 0x0000a340, 0x00000000 },
658 + { 0x0000a344, 0x00000000 },
659 + { 0x0000a348, 0x3fffffff },
660 + { 0x0000a34c, 0x3fffffff },
661 + { 0x0000a350, 0x3fffffff },
662 + { 0x0000a354, 0x0003ffff },
663 + { 0x0000a358, 0x79a8aa1f },
664 + { 0x0000d35c, 0x07ffffef },
665 + { 0x0000d360, 0x0fffffe7 },
666 + { 0x0000d364, 0x17ffffe5 },
667 + { 0x0000d368, 0x1fffffe4 },
668 + { 0x0000d36c, 0x37ffffe3 },
669 + { 0x0000d370, 0x3fffffe3 },
670 + { 0x0000d374, 0x57ffffe3 },
671 + { 0x0000d378, 0x5fffffe2 },
672 + { 0x0000d37c, 0x7fffffe2 },
673 + { 0x0000d380, 0x7f3c7bba },
674 + { 0x0000d384, 0xf3307ff0 },
675 + { 0x0000a388, 0x08000000 },
676 + { 0x0000a38c, 0x20202020 },
677 + { 0x0000a390, 0x20202020 },
678 + { 0x0000a394, 0x1ce739ce },
679 + { 0x0000a398, 0x000001ce },
680 + { 0x0000a39c, 0x00000001 },
681 + { 0x0000a3a0, 0x00000000 },
682 + { 0x0000a3a4, 0x00000000 },
683 + { 0x0000a3a8, 0x00000000 },
684 + { 0x0000a3ac, 0x00000000 },
685 + { 0x0000a3b0, 0x00000000 },
686 + { 0x0000a3b4, 0x00000000 },
687 + { 0x0000a3b8, 0x00000000 },
688 + { 0x0000a3bc, 0x00000000 },
689 + { 0x0000a3c0, 0x00000000 },
690 + { 0x0000a3c4, 0x00000000 },
691 + { 0x0000a3c8, 0x00000246 },
692 + { 0x0000a3cc, 0x20202020 },
693 + { 0x0000a3d0, 0x20202020 },
694 + { 0x0000a3d4, 0x20202020 },
695 + { 0x0000a3dc, 0x1ce739ce },
696 + { 0x0000a3e0, 0x000001ce },
697 +};
698 +
699 +static const u32 ar5416Bank0[][2] = {
700 + { 0x000098b0, 0x1e5795e5 },
701 + { 0x000098e0, 0x02008020 },
702 +};
703 +
704 +static const u32 ar5416BB_RfGain[][3] = {
705 + { 0x00009a00, 0x00000000, 0x00000000 },
706 + { 0x00009a04, 0x00000040, 0x00000040 },
707 + { 0x00009a08, 0x00000080, 0x00000080 },
708 + { 0x00009a0c, 0x000001a1, 0x00000141 },
709 + { 0x00009a10, 0x000001e1, 0x00000181 },
710 + { 0x00009a14, 0x00000021, 0x000001c1 },
711 + { 0x00009a18, 0x00000061, 0x00000001 },
712 + { 0x00009a1c, 0x00000168, 0x00000041 },
713 + { 0x00009a20, 0x000001a8, 0x000001a8 },
714 + { 0x00009a24, 0x000001e8, 0x000001e8 },
715 + { 0x00009a28, 0x00000028, 0x00000028 },
716 + { 0x00009a2c, 0x00000068, 0x00000068 },
717 + { 0x00009a30, 0x00000189, 0x000000a8 },
718 + { 0x00009a34, 0x000001c9, 0x00000169 },
719 + { 0x00009a38, 0x00000009, 0x000001a9 },
720 + { 0x00009a3c, 0x00000049, 0x000001e9 },
721 + { 0x00009a40, 0x00000089, 0x00000029 },
722 + { 0x00009a44, 0x00000170, 0x00000069 },
723 + { 0x00009a48, 0x000001b0, 0x00000190 },
724 + { 0x00009a4c, 0x000001f0, 0x000001d0 },
725 + { 0x00009a50, 0x00000030, 0x00000010 },
726 + { 0x00009a54, 0x00000070, 0x00000050 },
727 + { 0x00009a58, 0x00000191, 0x00000090 },
728 + { 0x00009a5c, 0x000001d1, 0x00000151 },
729 + { 0x00009a60, 0x00000011, 0x00000191 },
730 + { 0x00009a64, 0x00000051, 0x000001d1 },
731 + { 0x00009a68, 0x00000091, 0x00000011 },
732 + { 0x00009a6c, 0x000001b8, 0x00000051 },
733 + { 0x00009a70, 0x000001f8, 0x00000198 },
734 + { 0x00009a74, 0x00000038, 0x000001d8 },
735 + { 0x00009a78, 0x00000078, 0x00000018 },
736 + { 0x00009a7c, 0x00000199, 0x00000058 },
737 + { 0x00009a80, 0x000001d9, 0x00000098 },
738 + { 0x00009a84, 0x00000019, 0x00000159 },
739 + { 0x00009a88, 0x00000059, 0x00000199 },
740 + { 0x00009a8c, 0x00000099, 0x000001d9 },
741 + { 0x00009a90, 0x000000d9, 0x00000019 },
742 + { 0x00009a94, 0x000000f9, 0x00000059 },
743 + { 0x00009a98, 0x000000f9, 0x00000099 },
744 + { 0x00009a9c, 0x000000f9, 0x000000d9 },
745 + { 0x00009aa0, 0x000000f9, 0x000000f9 },
746 + { 0x00009aa4, 0x000000f9, 0x000000f9 },
747 + { 0x00009aa8, 0x000000f9, 0x000000f9 },
748 + { 0x00009aac, 0x000000f9, 0x000000f9 },
749 + { 0x00009ab0, 0x000000f9, 0x000000f9 },
750 + { 0x00009ab4, 0x000000f9, 0x000000f9 },
751 + { 0x00009ab8, 0x000000f9, 0x000000f9 },
752 + { 0x00009abc, 0x000000f9, 0x000000f9 },
753 + { 0x00009ac0, 0x000000f9, 0x000000f9 },
754 + { 0x00009ac4, 0x000000f9, 0x000000f9 },
755 + { 0x00009ac8, 0x000000f9, 0x000000f9 },
756 + { 0x00009acc, 0x000000f9, 0x000000f9 },
757 + { 0x00009ad0, 0x000000f9, 0x000000f9 },
758 + { 0x00009ad4, 0x000000f9, 0x000000f9 },
759 + { 0x00009ad8, 0x000000f9, 0x000000f9 },
760 + { 0x00009adc, 0x000000f9, 0x000000f9 },
761 + { 0x00009ae0, 0x000000f9, 0x000000f9 },
762 + { 0x00009ae4, 0x000000f9, 0x000000f9 },
763 + { 0x00009ae8, 0x000000f9, 0x000000f9 },
764 + { 0x00009aec, 0x000000f9, 0x000000f9 },
765 + { 0x00009af0, 0x000000f9, 0x000000f9 },
766 + { 0x00009af4, 0x000000f9, 0x000000f9 },
767 + { 0x00009af8, 0x000000f9, 0x000000f9 },
768 + { 0x00009afc, 0x000000f9, 0x000000f9 },
769 +};
770 +
771 +static const u32 ar5416Bank1[][2] = {
772 + { 0x000098b0, 0x02108421 },
773 + { 0x000098ec, 0x00000008 },
774 +};
775 +
776 +static const u32 ar5416Bank2[][2] = {
777 + { 0x000098b0, 0x0e73ff17 },
778 + { 0x000098e0, 0x00000420 },
779 +};
780 +
781 +static const u32 ar5416Bank3[][3] = {
782 + { 0x000098f0, 0x01400018, 0x01c00018 },
783 +};
784 +
785 +static const u32 ar5416Bank6[][3] = {
786 +
787 + { 0x0000989c, 0x00000000, 0x00000000 },
788 + { 0x0000989c, 0x00000000, 0x00000000 },
789 + { 0x0000989c, 0x00000000, 0x00000000 },
790 + { 0x0000989c, 0x00e00000, 0x00e00000 },
791 + { 0x0000989c, 0x005e0000, 0x005e0000 },
792 + { 0x0000989c, 0x00120000, 0x00120000 },
793 + { 0x0000989c, 0x00620000, 0x00620000 },
794 + { 0x0000989c, 0x00020000, 0x00020000 },
795 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
796 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
797 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
798 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
799 + { 0x0000989c, 0x005f0000, 0x005f0000 },
800 + { 0x0000989c, 0x00870000, 0x00870000 },
801 + { 0x0000989c, 0x00f90000, 0x00f90000 },
802 + { 0x0000989c, 0x007b0000, 0x007b0000 },
803 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
804 + { 0x0000989c, 0x00f50000, 0x00f50000 },
805 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
806 + { 0x0000989c, 0x00110000, 0x00110000 },
807 + { 0x0000989c, 0x006100a8, 0x006100a8 },
808 + { 0x0000989c, 0x004210a2, 0x004210a2 },
809 + { 0x0000989c, 0x0014008f, 0x0014008f },
810 + { 0x0000989c, 0x00c40003, 0x00c40003 },
811 + { 0x0000989c, 0x003000f2, 0x003000f2 },
812 + { 0x0000989c, 0x00440016, 0x00440016 },
813 + { 0x0000989c, 0x00410040, 0x00410040 },
814 + { 0x0000989c, 0x0001805e, 0x0001805e },
815 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
816 + { 0x0000989c, 0x000000f1, 0x000000f1 },
817 + { 0x0000989c, 0x00002081, 0x00002081 },
818 + { 0x0000989c, 0x000000d4, 0x000000d4 },
819 + { 0x000098d0, 0x0000000f, 0x0010000f },
820 +};
821 +
822 +static const u32 ar5416Bank6TPC[][3] = {
823 + { 0x0000989c, 0x00000000, 0x00000000 },
824 + { 0x0000989c, 0x00000000, 0x00000000 },
825 + { 0x0000989c, 0x00000000, 0x00000000 },
826 + { 0x0000989c, 0x00e00000, 0x00e00000 },
827 + { 0x0000989c, 0x005e0000, 0x005e0000 },
828 + { 0x0000989c, 0x00120000, 0x00120000 },
829 + { 0x0000989c, 0x00620000, 0x00620000 },
830 + { 0x0000989c, 0x00020000, 0x00020000 },
831 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
832 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
833 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
834 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
835 + { 0x0000989c, 0x005f0000, 0x005f0000 },
836 + { 0x0000989c, 0x00870000, 0x00870000 },
837 + { 0x0000989c, 0x00f90000, 0x00f90000 },
838 + { 0x0000989c, 0x007b0000, 0x007b0000 },
839 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
840 + { 0x0000989c, 0x00f50000, 0x00f50000 },
841 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
842 + { 0x0000989c, 0x00110000, 0x00110000 },
843 + { 0x0000989c, 0x006100a8, 0x006100a8 },
844 + { 0x0000989c, 0x00423022, 0x00423022 },
845 + { 0x0000989c, 0x201400df, 0x201400df },
846 + { 0x0000989c, 0x00c40002, 0x00c40002 },
847 + { 0x0000989c, 0x003000f2, 0x003000f2 },
848 + { 0x0000989c, 0x00440016, 0x00440016 },
849 + { 0x0000989c, 0x00410040, 0x00410040 },
850 + { 0x0000989c, 0x0001805e, 0x0001805e },
851 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
852 + { 0x0000989c, 0x000000e1, 0x000000e1 },
853 + { 0x0000989c, 0x00007081, 0x00007081 },
854 + { 0x0000989c, 0x000000d4, 0x000000d4 },
855 + { 0x000098d0, 0x0000000f, 0x0010000f },
856 +};
857 +
858 +static const u32 ar5416Bank7[][2] = {
859 + { 0x0000989c, 0x00000500 },
860 + { 0x0000989c, 0x00000800 },
861 + { 0x000098cc, 0x0000000e },
862 +};
863 +
864 +static const u32 ar5416Addac[][2] = {
865 + {0x0000989c, 0x00000000 },
866 + {0x0000989c, 0x00000003 },
867 + {0x0000989c, 0x00000000 },
868 + {0x0000989c, 0x0000000c },
869 + {0x0000989c, 0x00000000 },
870 + {0x0000989c, 0x00000030 },
871 + {0x0000989c, 0x00000000 },
872 + {0x0000989c, 0x00000000 },
873 + {0x0000989c, 0x00000000 },
874 + {0x0000989c, 0x00000000 },
875 + {0x0000989c, 0x00000000 },
876 + {0x0000989c, 0x00000000 },
877 + {0x0000989c, 0x00000000 },
878 + {0x0000989c, 0x00000000 },
879 + {0x0000989c, 0x00000000 },
880 + {0x0000989c, 0x00000000 },
881 + {0x0000989c, 0x00000000 },
882 + {0x0000989c, 0x00000000 },
883 + {0x0000989c, 0x00000060 },
884 + {0x0000989c, 0x00000000 },
885 + {0x0000989c, 0x00000000 },
886 + {0x0000989c, 0x00000000 },
887 + {0x0000989c, 0x00000000 },
888 + {0x0000989c, 0x00000000 },
889 + {0x0000989c, 0x00000000 },
890 + {0x0000989c, 0x00000000 },
891 + {0x0000989c, 0x00000000 },
892 + {0x0000989c, 0x00000000 },
893 + {0x0000989c, 0x00000000 },
894 + {0x0000989c, 0x00000000 },
895 + {0x0000989c, 0x00000000 },
896 + {0x0000989c, 0x00000058 },
897 + {0x0000989c, 0x00000000 },
898 + {0x0000989c, 0x00000000 },
899 + {0x0000989c, 0x00000000 },
900 + {0x0000989c, 0x00000000 },
901 + {0x000098cc, 0x00000000 },
902 +};
903 +
904 +static const u32 ar5416Modes_9100[][6] = {
905 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
906 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
907 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
908 + { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
909 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
910 + { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
911 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
912 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
913 + { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
914 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
915 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
916 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
917 + { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
918 + { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
919 + { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
920 + { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
921 + { 0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2, 0x6d48b0e2 },
922 + { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec86d2e, 0x7ec84d2e, 0x7ec82d2e },
923 + { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
924 + { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
925 + { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
926 + { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
927 + { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
928 + { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
929 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
930 + { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a11, 0xd00a8a0d, 0xd00a8a0d },
931 + { 0x00009940, 0x00754604, 0x00754604, 0xfff81204, 0xfff81204, 0xfff81204 },
932 + { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },
933 + { 0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e, 0xe250a51e },
934 + { 0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff, 0x3388ffff },
935 +#ifdef TB243
936 + { 0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
937 + { 0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
938 + { 0x0000b960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
939 + { 0x00009964, 0x00000000, 0x00000000, 0x00002210, 0x00002210, 0x00001120 },
940 +#else
941 + { 0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
942 + { 0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
943 + { 0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
944 + { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
945 +#endif
946 + { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00, 0x001a0c00 },
947 + { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
948 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
949 + { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
950 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
951 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
952 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
953 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
954 + { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
955 + { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
956 + { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
957 + { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
958 + { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
959 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
960 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
961 + { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
962 + { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
963 + { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
964 + { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
965 + { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
966 + { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
967 + { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
968 + { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
969 + { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
970 + { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
971 + { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
972 + { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
973 + { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
974 + { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
975 + { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
976 +};
977 +
978 +#endif /* INITVALS_AR5008_H */
979 --- /dev/null
980 +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
981 @@ -0,0 +1,1345 @@
982 +/*
983 + * Copyright (c) 2008-2010 Atheros Communications Inc.
984 + *
985 + * Permission to use, copy, modify, and/or distribute this software for any
986 + * purpose with or without fee is hereby granted, provided that the above
987 + * copyright notice and this permission notice appear in all copies.
988 + *
989 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
990 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
991 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
992 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
993 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
994 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
995 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
996 + */
997 +
998 +#include "hw.h"
999 +#include "hw-ops.h"
1000 +#include "../regd.h"
1001 +#include "ar9002_phy.h"
1002 +
1003 +/* All code below is for non single-chip solutions */
1004 +
1005 +/**
1006 + * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
1007 + * @rfbuf:
1008 + * @reg32:
1009 + * @numBits:
1010 + * @firstBit:
1011 + * @column:
1012 + *
1013 + * Performs analog "swizzling" of parameters into their location.
1014 + * Used on external AR2133/AR5133 radios.
1015 + */
1016 +static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
1017 + u32 numBits, u32 firstBit,
1018 + u32 column)
1019 +{
1020 + u32 tmp32, mask, arrayEntry, lastBit;
1021 + int32_t bitPosition, bitsLeft;
1022 +
1023 + tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
1024 + arrayEntry = (firstBit - 1) / 8;
1025 + bitPosition = (firstBit - 1) % 8;
1026 + bitsLeft = numBits;
1027 + while (bitsLeft > 0) {
1028 + lastBit = (bitPosition + bitsLeft > 8) ?
1029 + 8 : bitPosition + bitsLeft;
1030 + mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
1031 + (column * 8);
1032 + rfBuf[arrayEntry] &= ~mask;
1033 + rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
1034 + (column * 8)) & mask;
1035 + bitsLeft -= 8 - bitPosition;
1036 + tmp32 = tmp32 >> (8 - bitPosition);
1037 + bitPosition = 0;
1038 + arrayEntry++;
1039 + }
1040 +}
1041 +
1042 +/*
1043 + * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
1044 + * rf_pwd_icsyndiv.
1045 + *
1046 + * Theoretical Rules:
1047 + * if 2 GHz band
1048 + * if forceBiasAuto
1049 + * if synth_freq < 2412
1050 + * bias = 0
1051 + * else if 2412 <= synth_freq <= 2422
1052 + * bias = 1
1053 + * else // synth_freq > 2422
1054 + * bias = 2
1055 + * else if forceBias > 0
1056 + * bias = forceBias & 7
1057 + * else
1058 + * no change, use value from ini file
1059 + * else
1060 + * no change, invalid band
1061 + *
1062 + * 1st Mod:
1063 + * 2422 also uses value of 2
1064 + * <approved>
1065 + *
1066 + * 2nd Mod:
1067 + * Less than 2412 uses value of 0, 2412 and above uses value of 2
1068 + */
1069 +static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
1070 +{
1071 + struct ath_common *common = ath9k_hw_common(ah);
1072 + u32 tmp_reg;
1073 + int reg_writes = 0;
1074 + u32 new_bias = 0;
1075 +
1076 + if (!AR_SREV_5416(ah) || synth_freq >= 3000) {
1077 + return;
1078 + }
1079 +
1080 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1081 +
1082 + if (synth_freq < 2412)
1083 + new_bias = 0;
1084 + else if (synth_freq < 2422)
1085 + new_bias = 1;
1086 + else
1087 + new_bias = 2;
1088 +
1089 + /* pre-reverse this field */
1090 + tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
1091 +
1092 + ath_print(common, ATH_DBG_CONFIG,
1093 + "Force rf_pwd_icsyndiv to %1d on %4d\n",
1094 + new_bias, synth_freq);
1095 +
1096 + /* swizzle rf_pwd_icsyndiv */
1097 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
1098 +
1099 + /* write Bank 6 with new params */
1100 + REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
1101 +}
1102 +
1103 +/**
1104 + * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
1105 + * @ah: atheros hardware stucture
1106 + * @chan:
1107 + *
1108 + * For the external AR2133/AR5133 radios, takes the MHz channel value and set
1109 + * the channel value. Assumes writes enabled to analog bus and bank6 register
1110 + * cache in ah->analogBank6Data.
1111 + */
1112 +static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
1113 +{
1114 + struct ath_common *common = ath9k_hw_common(ah);
1115 + u32 channelSel = 0;
1116 + u32 bModeSynth = 0;
1117 + u32 aModeRefSel = 0;
1118 + u32 reg32 = 0;
1119 + u16 freq;
1120 + struct chan_centers centers;
1121 +
1122 + ath9k_hw_get_channel_centers(ah, chan, &centers);
1123 + freq = centers.synth_center;
1124 +
1125 + if (freq < 4800) {
1126 + u32 txctl;
1127 +
1128 + if (((freq - 2192) % 5) == 0) {
1129 + channelSel = ((freq - 672) * 2 - 3040) / 10;
1130 + bModeSynth = 0;
1131 + } else if (((freq - 2224) % 5) == 0) {
1132 + channelSel = ((freq - 704) * 2 - 3040) / 10;
1133 + bModeSynth = 1;
1134 + } else {
1135 + ath_print(common, ATH_DBG_FATAL,
1136 + "Invalid channel %u MHz\n", freq);
1137 + return -EINVAL;
1138 + }
1139 +
1140 + channelSel = (channelSel << 2) & 0xff;
1141 + channelSel = ath9k_hw_reverse_bits(channelSel, 8);
1142 +
1143 + txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
1144 + if (freq == 2484) {
1145 +
1146 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
1147 + txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
1148 + } else {
1149 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
1150 + txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
1151 + }
1152 +
1153 + } else if ((freq % 20) == 0 && freq >= 5120) {
1154 + channelSel =
1155 + ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
1156 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1157 + } else if ((freq % 10) == 0) {
1158 + channelSel =
1159 + ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
1160 + if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
1161 + aModeRefSel = ath9k_hw_reverse_bits(2, 2);
1162 + else
1163 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1164 + } else if ((freq % 5) == 0) {
1165 + channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
1166 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1167 + } else {
1168 + ath_print(common, ATH_DBG_FATAL,
1169 + "Invalid channel %u MHz\n", freq);
1170 + return -EINVAL;
1171 + }
1172 +
1173 + ar5008_hw_force_bias(ah, freq);
1174 +
1175 + reg32 =
1176 + (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
1177 + (1 << 5) | 0x1;
1178 +
1179 + REG_WRITE(ah, AR_PHY(0x37), reg32);
1180 +
1181 + ah->curchan = chan;
1182 + ah->curchan_rad_index = -1;
1183 +
1184 + return 0;
1185 +}
1186 +
1187 +/**
1188 + * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
1189 + * @ah: atheros hardware structure
1190 + * @chan:
1191 + *
1192 + * For non single-chip solutions. Converts to baseband spur frequency given the
1193 + * input channel frequency and compute register settings below.
1194 + */
1195 +static void ar5008_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1196 +{
1197 + int bb_spur = AR_NO_SPUR;
1198 + int bin, cur_bin;
1199 + int spur_freq_sd;
1200 + int spur_delta_phase;
1201 + int denominator;
1202 + int upper, lower, cur_vit_mask;
1203 + int tmp, new;
1204 + int i;
1205 + int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1206 + AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1207 + };
1208 + int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1209 + AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1210 + };
1211 + int inc[4] = { 0, 100, 0, 0 };
1212 +
1213 + int8_t mask_m[123];
1214 + int8_t mask_p[123];
1215 + int8_t mask_amt;
1216 + int tmp_mask;
1217 + int cur_bb_spur;
1218 + bool is2GHz = IS_CHAN_2GHZ(chan);
1219 +
1220 + memset(&mask_m, 0, sizeof(int8_t) * 123);
1221 + memset(&mask_p, 0, sizeof(int8_t) * 123);
1222 +
1223 + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1224 + cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1225 + if (AR_NO_SPUR == cur_bb_spur)
1226 + break;
1227 + cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1228 + if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1229 + bb_spur = cur_bb_spur;
1230 + break;
1231 + }
1232 + }
1233 +
1234 + if (AR_NO_SPUR == bb_spur)
1235 + return;
1236 +
1237 + bin = bb_spur * 32;
1238 +
1239 + tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1240 + new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1241 + AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1242 + AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1243 + AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1244 +
1245 + REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
1246 +
1247 + new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1248 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1249 + AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1250 + AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1251 + SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1252 + REG_WRITE(ah, AR_PHY_SPUR_REG, new);
1253 +
1254 + spur_delta_phase = ((bb_spur * 524288) / 100) &
1255 + AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1256 +
1257 + denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
1258 + spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
1259 +
1260 + new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1261 + SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1262 + SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1263 + REG_WRITE(ah, AR_PHY_TIMING11, new);
1264 +
1265 + cur_bin = -6000;
1266 + upper = bin + 100;
1267 + lower = bin - 100;
1268 +
1269 + for (i = 0; i < 4; i++) {
1270 + int pilot_mask = 0;
1271 + int chan_mask = 0;
1272 + int bp = 0;
1273 + for (bp = 0; bp < 30; bp++) {
1274 + if ((cur_bin > lower) && (cur_bin < upper)) {
1275 + pilot_mask = pilot_mask | 0x1 << bp;
1276 + chan_mask = chan_mask | 0x1 << bp;
1277 + }
1278 + cur_bin += 100;
1279 + }
1280 + cur_bin += inc[i];
1281 + REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1282 + REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1283 + }
1284 +
1285 + cur_vit_mask = 6100;
1286 + upper = bin + 120;
1287 + lower = bin - 120;
1288 +
1289 + for (i = 0; i < 123; i++) {
1290 + if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1291 +
1292 + /* workaround for gcc bug #37014 */
1293 + volatile int tmp_v = abs(cur_vit_mask - bin);
1294 +
1295 + if (tmp_v < 75)
1296 + mask_amt = 1;
1297 + else
1298 + mask_amt = 0;
1299 + if (cur_vit_mask < 0)
1300 + mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1301 + else
1302 + mask_p[cur_vit_mask / 100] = mask_amt;
1303 + }
1304 + cur_vit_mask -= 100;
1305 + }
1306 +
1307 + tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1308 + | (mask_m[48] << 26) | (mask_m[49] << 24)
1309 + | (mask_m[50] << 22) | (mask_m[51] << 20)
1310 + | (mask_m[52] << 18) | (mask_m[53] << 16)
1311 + | (mask_m[54] << 14) | (mask_m[55] << 12)
1312 + | (mask_m[56] << 10) | (mask_m[57] << 8)
1313 + | (mask_m[58] << 6) | (mask_m[59] << 4)
1314 + | (mask_m[60] << 2) | (mask_m[61] << 0);
1315 + REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1316 + REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1317 +
1318 + tmp_mask = (mask_m[31] << 28)
1319 + | (mask_m[32] << 26) | (mask_m[33] << 24)
1320 + | (mask_m[34] << 22) | (mask_m[35] << 20)
1321 + | (mask_m[36] << 18) | (mask_m[37] << 16)
1322 + | (mask_m[48] << 14) | (mask_m[39] << 12)
1323 + | (mask_m[40] << 10) | (mask_m[41] << 8)
1324 + | (mask_m[42] << 6) | (mask_m[43] << 4)
1325 + | (mask_m[44] << 2) | (mask_m[45] << 0);
1326 + REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1327 + REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1328 +
1329 + tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1330 + | (mask_m[18] << 26) | (mask_m[18] << 24)
1331 + | (mask_m[20] << 22) | (mask_m[20] << 20)
1332 + | (mask_m[22] << 18) | (mask_m[22] << 16)
1333 + | (mask_m[24] << 14) | (mask_m[24] << 12)
1334 + | (mask_m[25] << 10) | (mask_m[26] << 8)
1335 + | (mask_m[27] << 6) | (mask_m[28] << 4)
1336 + | (mask_m[29] << 2) | (mask_m[30] << 0);
1337 + REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1338 + REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1339 +
1340 + tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1341 + | (mask_m[2] << 26) | (mask_m[3] << 24)
1342 + | (mask_m[4] << 22) | (mask_m[5] << 20)
1343 + | (mask_m[6] << 18) | (mask_m[7] << 16)
1344 + | (mask_m[8] << 14) | (mask_m[9] << 12)
1345 + | (mask_m[10] << 10) | (mask_m[11] << 8)
1346 + | (mask_m[12] << 6) | (mask_m[13] << 4)
1347 + | (mask_m[14] << 2) | (mask_m[15] << 0);
1348 + REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1349 + REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1350 +
1351 + tmp_mask = (mask_p[15] << 28)
1352 + | (mask_p[14] << 26) | (mask_p[13] << 24)
1353 + | (mask_p[12] << 22) | (mask_p[11] << 20)
1354 + | (mask_p[10] << 18) | (mask_p[9] << 16)
1355 + | (mask_p[8] << 14) | (mask_p[7] << 12)
1356 + | (mask_p[6] << 10) | (mask_p[5] << 8)
1357 + | (mask_p[4] << 6) | (mask_p[3] << 4)
1358 + | (mask_p[2] << 2) | (mask_p[1] << 0);
1359 + REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1360 + REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1361 +
1362 + tmp_mask = (mask_p[30] << 28)
1363 + | (mask_p[29] << 26) | (mask_p[28] << 24)
1364 + | (mask_p[27] << 22) | (mask_p[26] << 20)
1365 + | (mask_p[25] << 18) | (mask_p[24] << 16)
1366 + | (mask_p[23] << 14) | (mask_p[22] << 12)
1367 + | (mask_p[21] << 10) | (mask_p[20] << 8)
1368 + | (mask_p[19] << 6) | (mask_p[18] << 4)
1369 + | (mask_p[17] << 2) | (mask_p[16] << 0);
1370 + REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1371 + REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1372 +
1373 + tmp_mask = (mask_p[45] << 28)
1374 + | (mask_p[44] << 26) | (mask_p[43] << 24)
1375 + | (mask_p[42] << 22) | (mask_p[41] << 20)
1376 + | (mask_p[40] << 18) | (mask_p[39] << 16)
1377 + | (mask_p[38] << 14) | (mask_p[37] << 12)
1378 + | (mask_p[36] << 10) | (mask_p[35] << 8)
1379 + | (mask_p[34] << 6) | (mask_p[33] << 4)
1380 + | (mask_p[32] << 2) | (mask_p[31] << 0);
1381 + REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1382 + REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1383 +
1384 + tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1385 + | (mask_p[59] << 26) | (mask_p[58] << 24)
1386 + | (mask_p[57] << 22) | (mask_p[56] << 20)
1387 + | (mask_p[55] << 18) | (mask_p[54] << 16)
1388 + | (mask_p[53] << 14) | (mask_p[52] << 12)
1389 + | (mask_p[51] << 10) | (mask_p[50] << 8)
1390 + | (mask_p[49] << 6) | (mask_p[48] << 4)
1391 + | (mask_p[47] << 2) | (mask_p[46] << 0);
1392 + REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1393 + REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1394 +}
1395 +
1396 +/**
1397 + * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
1398 + * @ah: atheros hardware structure
1399 + *
1400 + * Only required for older devices with external AR2133/AR5133 radios.
1401 + */
1402 +static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
1403 +{
1404 +#define ATH_ALLOC_BANK(bank, size) do { \
1405 + bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
1406 + if (!bank) { \
1407 + ath_print(common, ATH_DBG_FATAL, \
1408 + "Cannot allocate RF banks\n"); \
1409 + return -ENOMEM; \
1410 + } \
1411 + } while (0);
1412 +
1413 + struct ath_common *common = ath9k_hw_common(ah);
1414 +
1415 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1416 +
1417 + ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
1418 + ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
1419 + ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
1420 + ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
1421 + ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
1422 + ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
1423 + ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
1424 + ATH_ALLOC_BANK(ah->addac5416_21,
1425 + ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
1426 + ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
1427 +
1428 + return 0;
1429 +#undef ATH_ALLOC_BANK
1430 +}
1431 +
1432 +
1433 +/**
1434 + * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
1435 + * @ah: atheros hardware struture
1436 + * For the external AR2133/AR5133 radios banks.
1437 + */
1438 +static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
1439 +{
1440 +#define ATH_FREE_BANK(bank) do { \
1441 + kfree(bank); \
1442 + bank = NULL; \
1443 + } while (0);
1444 +
1445 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1446 +
1447 + ATH_FREE_BANK(ah->analogBank0Data);
1448 + ATH_FREE_BANK(ah->analogBank1Data);
1449 + ATH_FREE_BANK(ah->analogBank2Data);
1450 + ATH_FREE_BANK(ah->analogBank3Data);
1451 + ATH_FREE_BANK(ah->analogBank6Data);
1452 + ATH_FREE_BANK(ah->analogBank6TPCData);
1453 + ATH_FREE_BANK(ah->analogBank7Data);
1454 + ATH_FREE_BANK(ah->addac5416_21);
1455 + ATH_FREE_BANK(ah->bank6Temp);
1456 +
1457 +#undef ATH_FREE_BANK
1458 +}
1459 +
1460 +/* *
1461 + * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
1462 + * @ah: atheros hardware structure
1463 + * @chan:
1464 + * @modesIndex:
1465 + *
1466 + * Used for the external AR2133/AR5133 radios.
1467 + *
1468 + * Reads the EEPROM header info from the device structure and programs
1469 + * all rf registers. This routine requires access to the analog
1470 + * rf device. This is not required for single-chip devices.
1471 + */
1472 +static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
1473 + struct ath9k_channel *chan,
1474 + u16 modesIndex)
1475 +{
1476 + u32 eepMinorRev;
1477 + u32 ob5GHz = 0, db5GHz = 0;
1478 + u32 ob2GHz = 0, db2GHz = 0;
1479 + int regWrites = 0;
1480 +
1481 + /*
1482 + * Software does not need to program bank data
1483 + * for single chip devices, that is AR9280 or anything
1484 + * after that.
1485 + */
1486 + if (AR_SREV_9280_10_OR_LATER(ah))
1487 + return true;
1488 +
1489 + /* Setup rf parameters */
1490 + eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
1491 +
1492 + /* Setup Bank 0 Write */
1493 + RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
1494 +
1495 + /* Setup Bank 1 Write */
1496 + RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
1497 +
1498 + /* Setup Bank 2 Write */
1499 + RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
1500 +
1501 + /* Setup Bank 6 Write */
1502 + RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
1503 + modesIndex);
1504 + {
1505 + int i;
1506 + for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
1507 + ah->analogBank6Data[i] =
1508 + INI_RA(&ah->iniBank6TPC, i, modesIndex);
1509 + }
1510 + }
1511 +
1512 + /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
1513 + if (eepMinorRev >= 2) {
1514 + if (IS_CHAN_2GHZ(chan)) {
1515 + ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
1516 + db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
1517 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1518 + ob2GHz, 3, 197, 0);
1519 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1520 + db2GHz, 3, 194, 0);
1521 + } else {
1522 + ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
1523 + db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
1524 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1525 + ob5GHz, 3, 203, 0);
1526 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1527 + db5GHz, 3, 200, 0);
1528 + }
1529 + }
1530 +
1531 + /* Setup Bank 7 Setup */
1532 + RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
1533 +
1534 + /* Write Analog registers */
1535 + REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
1536 + regWrites);
1537 + REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
1538 + regWrites);
1539 + REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
1540 + regWrites);
1541 + REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
1542 + regWrites);
1543 + REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
1544 + regWrites);
1545 + REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
1546 + regWrites);
1547 +
1548 + return true;
1549 +}
1550 +
1551 +static void ar5008_hw_init_bb(struct ath_hw *ah,
1552 + struct ath9k_channel *chan)
1553 +{
1554 + u32 synthDelay;
1555 +
1556 + synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1557 + if (IS_CHAN_B(chan))
1558 + synthDelay = (4 * synthDelay) / 22;
1559 + else
1560 + synthDelay /= 10;
1561 +
1562 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1563 +
1564 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
1565 +}
1566 +
1567 +static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
1568 +{
1569 + int rx_chainmask, tx_chainmask;
1570 +
1571 + rx_chainmask = ah->rxchainmask;
1572 + tx_chainmask = ah->txchainmask;
1573 +
1574 + switch (rx_chainmask) {
1575 + case 0x5:
1576 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1577 + AR_PHY_SWAP_ALT_CHAIN);
1578 + case 0x3:
1579 + if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1580 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1581 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1582 + break;
1583 + }
1584 + case 0x1:
1585 + case 0x2:
1586 + case 0x7:
1587 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1588 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1589 + break;
1590 + default:
1591 + break;
1592 + }
1593 +
1594 + REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1595 + if (tx_chainmask == 0x5) {
1596 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1597 + AR_PHY_SWAP_ALT_CHAIN);
1598 + }
1599 + if (AR_SREV_9100(ah))
1600 + REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1601 + REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1602 +}
1603 +
1604 +static void ar5008_hw_override_ini(struct ath_hw *ah,
1605 + struct ath9k_channel *chan)
1606 +{
1607 + u32 val;
1608 +
1609 + /*
1610 + * Set the RX_ABORT and RX_DIS and clear if off only after
1611 + * RXE is set for MAC. This prevents frames with corrupted
1612 + * descriptor status.
1613 + */
1614 + REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1615 +
1616 + if (AR_SREV_9280_10_OR_LATER(ah)) {
1617 + val = REG_READ(ah, AR_PCU_MISC_MODE2);
1618 +
1619 + if (!AR_SREV_9271(ah))
1620 + val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1621 +
1622 + if (AR_SREV_9287_10_OR_LATER(ah))
1623 + val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1624 +
1625 + REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1626 + }
1627 +
1628 + if (!AR_SREV_5416_20_OR_LATER(ah) ||
1629 + AR_SREV_9280_10_OR_LATER(ah))
1630 + return;
1631 + /*
1632 + * Disable BB clock gating
1633 + * Necessary to avoid issues on AR5416 2.0
1634 + */
1635 + REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1636 +
1637 + /*
1638 + * Disable RIFS search on some chips to avoid baseband
1639 + * hang issues.
1640 + */
1641 + if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1642 + val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1643 + val &= ~AR_PHY_RIFS_INIT_DELAY;
1644 + REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1645 + }
1646 +}
1647 +
1648 +static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
1649 + struct ath9k_channel *chan)
1650 +{
1651 + u32 phymode;
1652 + u32 enableDacFifo = 0;
1653 +
1654 + if (AR_SREV_9285_10_OR_LATER(ah))
1655 + enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1656 + AR_PHY_FC_ENABLE_DAC_FIFO);
1657 +
1658 + phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1659 + | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1660 +
1661 + if (IS_CHAN_HT40(chan)) {
1662 + phymode |= AR_PHY_FC_DYN2040_EN;
1663 +
1664 + if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1665 + (chan->chanmode == CHANNEL_G_HT40PLUS))
1666 + phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1667 +
1668 + }
1669 + REG_WRITE(ah, AR_PHY_TURBO, phymode);
1670 +
1671 + ath9k_hw_set11nmac2040(ah);
1672 +
1673 + REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1674 + REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1675 +}
1676 +
1677 +
1678 +static int ar5008_hw_process_ini(struct ath_hw *ah,
1679 + struct ath9k_channel *chan)
1680 +{
1681 + struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1682 + int i, regWrites = 0;
1683 + struct ieee80211_channel *channel = chan->chan;
1684 + u32 modesIndex, freqIndex;
1685 +
1686 + switch (chan->chanmode) {
1687 + case CHANNEL_A:
1688 + case CHANNEL_A_HT20:
1689 + modesIndex = 1;
1690 + freqIndex = 1;
1691 + break;
1692 + case CHANNEL_A_HT40PLUS:
1693 + case CHANNEL_A_HT40MINUS:
1694 + modesIndex = 2;
1695 + freqIndex = 1;
1696 + break;
1697 + case CHANNEL_G:
1698 + case CHANNEL_G_HT20:
1699 + case CHANNEL_B:
1700 + modesIndex = 4;
1701 + freqIndex = 2;
1702 + break;
1703 + case CHANNEL_G_HT40PLUS:
1704 + case CHANNEL_G_HT40MINUS:
1705 + modesIndex = 3;
1706 + freqIndex = 2;
1707 + break;
1708 +
1709 + default:
1710 + return -EINVAL;
1711 + }
1712 +
1713 + if (AR_SREV_9287_12_OR_LATER(ah)) {
1714 + /* Enable ASYNC FIFO */
1715 + REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1716 + AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1717 + REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1718 + REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1719 + AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1720 + REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1721 + AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1722 + }
1723 +
1724 + /* Set correct baseband to analog shift setting to access analog chips */
1725 + REG_WRITE(ah, AR_PHY(0), 0x00000007);
1726 +
1727 + /* Write ADDAC shifts */
1728 + REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1729 + ah->eep_ops->set_addac(ah, chan);
1730 +
1731 + if (AR_SREV_5416_22_OR_LATER(ah)) {
1732 + REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1733 + } else {
1734 + struct ar5416IniArray temp;
1735 + u32 addacSize =
1736 + sizeof(u32) * ah->iniAddac.ia_rows *
1737 + ah->iniAddac.ia_columns;
1738 +
1739 + /* For AR5416 2.0/2.1 */
1740 + memcpy(ah->addac5416_21,
1741 + ah->iniAddac.ia_array, addacSize);
1742 +
1743 + /* override CLKDRV value at [row, column] = [31, 1] */
1744 + (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1745 +
1746 + temp.ia_array = ah->addac5416_21;
1747 + temp.ia_columns = ah->iniAddac.ia_columns;
1748 + temp.ia_rows = ah->iniAddac.ia_rows;
1749 + REG_WRITE_ARRAY(&temp, 1, regWrites);
1750 + }
1751 +
1752 + REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1753 +
1754 + for (i = 0; i < ah->iniModes.ia_rows; i++) {
1755 + u32 reg = INI_RA(&ah->iniModes, i, 0);
1756 + u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1757 +
1758 + if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
1759 + val &= ~AR_AN_TOP2_PWDCLKIND;
1760 +
1761 + REG_WRITE(ah, reg, val);
1762 +
1763 + if (reg >= 0x7800 && reg < 0x78a0
1764 + && ah->config.analog_shiftreg) {
1765 + udelay(100);
1766 + }
1767 +
1768 + DO_DELAY(regWrites);
1769 + }
1770 +
1771 + if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1772 + REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1773 +
1774 + if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1775 + AR_SREV_9287_10_OR_LATER(ah))
1776 + REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1777 +
1778 + if (AR_SREV_9271_10(ah))
1779 + REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1780 + modesIndex, regWrites);
1781 +
1782 + /* Write common array parameters */
1783 + for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1784 + u32 reg = INI_RA(&ah->iniCommon, i, 0);
1785 + u32 val = INI_RA(&ah->iniCommon, i, 1);
1786 +
1787 + REG_WRITE(ah, reg, val);
1788 +
1789 + if (reg >= 0x7800 && reg < 0x78a0
1790 + && ah->config.analog_shiftreg) {
1791 + udelay(100);
1792 + }
1793 +
1794 + DO_DELAY(regWrites);
1795 + }
1796 +
1797 + if (AR_SREV_9271(ah)) {
1798 + if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1799 + REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1800 + modesIndex, regWrites);
1801 + else
1802 + REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1803 + modesIndex, regWrites);
1804 + }
1805 +
1806 + REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
1807 +
1808 + if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1809 + REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1810 + regWrites);
1811 + }
1812 +
1813 + ar5008_hw_override_ini(ah, chan);
1814 + ar5008_hw_set_channel_regs(ah, chan);
1815 + ar5008_hw_init_chain_masks(ah);
1816 + ath9k_olc_init(ah);
1817 +
1818 + /* Set TX power */
1819 + ah->eep_ops->set_txpower(ah, chan,
1820 + ath9k_regd_get_ctl(regulatory, chan),
1821 + channel->max_antenna_gain * 2,
1822 + channel->max_power * 2,
1823 + min((u32) MAX_RATE_POWER,
1824 + (u32) regulatory->power_limit));
1825 +
1826 + /* Write analog registers */
1827 + if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1828 + ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1829 + "ar5416SetRfRegs failed\n");
1830 + return -EIO;
1831 + }
1832 +
1833 + return 0;
1834 +}
1835 +
1836 +static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1837 +{
1838 + u32 rfMode = 0;
1839 +
1840 + if (chan == NULL)
1841 + return;
1842 +
1843 + rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1844 + ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1845 +
1846 + if (!AR_SREV_9280_10_OR_LATER(ah))
1847 + rfMode |= (IS_CHAN_5GHZ(chan)) ?
1848 + AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1849 +
1850 + if ((AR_SREV_9280_20(ah) || AR_SREV_9300_20_OR_LATER(ah))
1851 + && IS_CHAN_A_5MHZ_SPACED(chan))
1852 + rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1853 +
1854 + REG_WRITE(ah, AR_PHY_MODE, rfMode);
1855 +}
1856 +
1857 +static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
1858 +{
1859 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1860 +}
1861 +
1862 +static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
1863 + struct ath9k_channel *chan)
1864 +{
1865 + u32 coef_scaled, ds_coef_exp, ds_coef_man;
1866 + u32 clockMhzScaled = 0x64000000;
1867 + struct chan_centers centers;
1868 +
1869 + if (IS_CHAN_HALF_RATE(chan))
1870 + clockMhzScaled = clockMhzScaled >> 1;
1871 + else if (IS_CHAN_QUARTER_RATE(chan))
1872 + clockMhzScaled = clockMhzScaled >> 2;
1873 +
1874 + ath9k_hw_get_channel_centers(ah, chan, &centers);
1875 + coef_scaled = clockMhzScaled / centers.synth_center;
1876 +
1877 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1878 + &ds_coef_exp);
1879 +
1880 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1881 + AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1882 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1883 + AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1884 +
1885 + coef_scaled = (9 * coef_scaled) / 10;
1886 +
1887 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1888 + &ds_coef_exp);
1889 +
1890 + REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1891 + AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1892 + REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1893 + AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1894 +}
1895 +
1896 +static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
1897 +{
1898 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1899 + return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1900 + AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
1901 +}
1902 +
1903 +static void ar5008_hw_rfbus_done(struct ath_hw *ah)
1904 +{
1905 + u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1906 + if (IS_CHAN_B(ah->curchan))
1907 + synthDelay = (4 * synthDelay) / 22;
1908 + else
1909 + synthDelay /= 10;
1910 +
1911 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
1912 +
1913 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1914 +}
1915 +
1916 +static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
1917 +{
1918 + REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1919 + AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1920 +
1921 + REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1922 + AR_GPIO_INPUT_MUX2_RFSILENT);
1923 +
1924 + ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1925 + REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1926 +}
1927 +
1928 +static void ar5008_restore_chainmask(struct ath_hw *ah)
1929 +{
1930 + int rx_chainmask = ah->rxchainmask;
1931 +
1932 + if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
1933 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1934 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1935 + }
1936 +}
1937 +
1938 +static void ar5008_set_diversity(struct ath_hw *ah, bool value)
1939 +{
1940 + u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1941 + if (value)
1942 + v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1943 + else
1944 + v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1945 + REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1946 +}
1947 +
1948 +static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
1949 + struct ath9k_channel *chan)
1950 +{
1951 + if (chan && IS_CHAN_5GHZ(chan))
1952 + return 0x1450;
1953 + return 0x1458;
1954 +}
1955 +
1956 +static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
1957 + struct ath9k_channel *chan)
1958 +{
1959 + u32 pll;
1960 +
1961 + pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1962 +
1963 + if (chan && IS_CHAN_HALF_RATE(chan))
1964 + pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1965 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
1966 + pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1967 +
1968 + if (chan && IS_CHAN_5GHZ(chan))
1969 + pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1970 + else
1971 + pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1972 +
1973 + return pll;
1974 +}
1975 +
1976 +static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
1977 + struct ath9k_channel *chan)
1978 +{
1979 + u32 pll;
1980 +
1981 + pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1982 +
1983 + if (chan && IS_CHAN_HALF_RATE(chan))
1984 + pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1985 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
1986 + pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1987 +
1988 + if (chan && IS_CHAN_5GHZ(chan))
1989 + pll |= SM(0xa, AR_RTC_PLL_DIV);
1990 + else
1991 + pll |= SM(0xb, AR_RTC_PLL_DIV);
1992 +
1993 + return pll;
1994 +}
1995 +
1996 +static bool ar5008_hw_ani_control(struct ath_hw *ah,
1997 + enum ath9k_ani_cmd cmd, int param)
1998 +{
1999 + struct ar5416AniState *aniState = ah->curani;
2000 + struct ath_common *common = ath9k_hw_common(ah);
2001 +
2002 + switch (cmd & ah->ani_function) {
2003 + case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
2004 + u32 level = param;
2005 +
2006 + if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
2007 + ath_print(common, ATH_DBG_ANI,
2008 + "level out of range (%u > %u)\n",
2009 + level,
2010 + (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
2011 + return false;
2012 + }
2013 +
2014 + REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2015 + AR_PHY_DESIRED_SZ_TOT_DES,
2016 + ah->totalSizeDesired[level]);
2017 + REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2018 + AR_PHY_AGC_CTL1_COARSE_LOW,
2019 + ah->coarse_low[level]);
2020 + REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2021 + AR_PHY_AGC_CTL1_COARSE_HIGH,
2022 + ah->coarse_high[level]);
2023 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2024 + AR_PHY_FIND_SIG_FIRPWR,
2025 + ah->firpwr[level]);
2026 +
2027 + if (level > aniState->noiseImmunityLevel)
2028 + ah->stats.ast_ani_niup++;
2029 + else if (level < aniState->noiseImmunityLevel)
2030 + ah->stats.ast_ani_nidown++;
2031 + aniState->noiseImmunityLevel = level;
2032 + break;
2033 + }
2034 + case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2035 + const int m1ThreshLow[] = { 127, 50 };
2036 + const int m2ThreshLow[] = { 127, 40 };
2037 + const int m1Thresh[] = { 127, 0x4d };
2038 + const int m2Thresh[] = { 127, 0x40 };
2039 + const int m2CountThr[] = { 31, 16 };
2040 + const int m2CountThrLow[] = { 63, 48 };
2041 + u32 on = param ? 1 : 0;
2042 +
2043 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2044 + AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2045 + m1ThreshLow[on]);
2046 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2047 + AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2048 + m2ThreshLow[on]);
2049 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2050 + AR_PHY_SFCORR_M1_THRESH,
2051 + m1Thresh[on]);
2052 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2053 + AR_PHY_SFCORR_M2_THRESH,
2054 + m2Thresh[on]);
2055 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2056 + AR_PHY_SFCORR_M2COUNT_THR,
2057 + m2CountThr[on]);
2058 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2059 + AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2060 + m2CountThrLow[on]);
2061 +
2062 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2063 + AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2064 + m1ThreshLow[on]);
2065 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2066 + AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2067 + m2ThreshLow[on]);
2068 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2069 + AR_PHY_SFCORR_EXT_M1_THRESH,
2070 + m1Thresh[on]);
2071 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2072 + AR_PHY_SFCORR_EXT_M2_THRESH,
2073 + m2Thresh[on]);
2074 +
2075 + if (on)
2076 + REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2077 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2078 + else
2079 + REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
2080 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2081 +
2082 + if (!on != aniState->ofdmWeakSigDetectOff) {
2083 + if (on)
2084 + ah->stats.ast_ani_ofdmon++;
2085 + else
2086 + ah->stats.ast_ani_ofdmoff++;
2087 + aniState->ofdmWeakSigDetectOff = !on;
2088 + }
2089 + break;
2090 + }
2091 + case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
2092 + const int weakSigThrCck[] = { 8, 6 };
2093 + u32 high = param ? 1 : 0;
2094 +
2095 + REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2096 + AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2097 + weakSigThrCck[high]);
2098 + if (high != aniState->cckWeakSigThreshold) {
2099 + if (high)
2100 + ah->stats.ast_ani_cckhigh++;
2101 + else
2102 + ah->stats.ast_ani_ccklow++;
2103 + aniState->cckWeakSigThreshold = high;
2104 + }
2105 + break;
2106 + }
2107 + case ATH9K_ANI_FIRSTEP_LEVEL:{
2108 + const int firstep[] = { 0, 4, 8 };
2109 + u32 level = param;
2110 +
2111 + if (level >= ARRAY_SIZE(firstep)) {
2112 + ath_print(common, ATH_DBG_ANI,
2113 + "level out of range (%u > %u)\n",
2114 + level,
2115 + (unsigned) ARRAY_SIZE(firstep));
2116 + return false;
2117 + }
2118 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2119 + AR_PHY_FIND_SIG_FIRSTEP,
2120 + firstep[level]);
2121 + if (level > aniState->firstepLevel)
2122 + ah->stats.ast_ani_stepup++;
2123 + else if (level < aniState->firstepLevel)
2124 + ah->stats.ast_ani_stepdown++;
2125 + aniState->firstepLevel = level;
2126 + break;
2127 + }
2128 + case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
2129 + const int cycpwrThr1[] =
2130 + { 2, 4, 6, 8, 10, 12, 14, 16 };
2131 + u32 level = param;
2132 +
2133 + if (level >= ARRAY_SIZE(cycpwrThr1)) {
2134 + ath_print(common, ATH_DBG_ANI,
2135 + "level out of range (%u > %u)\n",
2136 + level,
2137 + (unsigned) ARRAY_SIZE(cycpwrThr1));
2138 + return false;
2139 + }
2140 + REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2141 + AR_PHY_TIMING5_CYCPWR_THR1,
2142 + cycpwrThr1[level]);
2143 + if (level > aniState->spurImmunityLevel)
2144 + ah->stats.ast_ani_spurup++;
2145 + else if (level < aniState->spurImmunityLevel)
2146 + ah->stats.ast_ani_spurdown++;
2147 + aniState->spurImmunityLevel = level;
2148 + break;
2149 + }
2150 + case ATH9K_ANI_PRESENT:
2151 + break;
2152 + default:
2153 + ath_print(common, ATH_DBG_ANI,
2154 + "invalid cmd %u\n", cmd);
2155 + return false;
2156 + }
2157 +
2158 + ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
2159 + ath_print(common, ATH_DBG_ANI,
2160 + "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2161 + "ofdmWeakSigDetectOff=%d\n",
2162 + aniState->noiseImmunityLevel,
2163 + aniState->spurImmunityLevel,
2164 + !aniState->ofdmWeakSigDetectOff);
2165 + ath_print(common, ATH_DBG_ANI,
2166 + "cckWeakSigThreshold=%d, "
2167 + "firstepLevel=%d, listenTime=%d\n",
2168 + aniState->cckWeakSigThreshold,
2169 + aniState->firstepLevel,
2170 + aniState->listenTime);
2171 + ath_print(common, ATH_DBG_ANI,
2172 + "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2173 + aniState->cycleCount,
2174 + aniState->ofdmPhyErrCount,
2175 + aniState->cckPhyErrCount);
2176 +
2177 + return true;
2178 +}
2179 +
2180 +static void ar5008_hw_do_getnf(struct ath_hw *ah,
2181 + int16_t nfarray[NUM_NF_READINGS])
2182 +{
2183 + struct ath_common *common = ath9k_hw_common(ah);
2184 + int16_t nf;
2185 +
2186 + nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
2187 + if (nf & 0x100)
2188 + nf = 0 - ((nf ^ 0x1ff) + 1);
2189 + ath_print(common, ATH_DBG_CALIBRATE,
2190 + "NF calibrated [ctl] [chain 0] is %d\n", nf);
2191 + nfarray[0] = nf;
2192 +
2193 + nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
2194 + if (nf & 0x100)
2195 + nf = 0 - ((nf ^ 0x1ff) + 1);
2196 + ath_print(common, ATH_DBG_CALIBRATE,
2197 + "NF calibrated [ctl] [chain 1] is %d\n", nf);
2198 + nfarray[1] = nf;
2199 +
2200 + nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
2201 + if (nf & 0x100)
2202 + nf = 0 - ((nf ^ 0x1ff) + 1);
2203 + ath_print(common, ATH_DBG_CALIBRATE,
2204 + "NF calibrated [ctl] [chain 2] is %d\n", nf);
2205 + nfarray[2] = nf;
2206 +
2207 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
2208 + if (nf & 0x100)
2209 + nf = 0 - ((nf ^ 0x1ff) + 1);
2210 + ath_print(common, ATH_DBG_CALIBRATE,
2211 + "NF calibrated [ext] [chain 0] is %d\n", nf);
2212 + nfarray[3] = nf;
2213 +
2214 + nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
2215 + if (nf & 0x100)
2216 + nf = 0 - ((nf ^ 0x1ff) + 1);
2217 + ath_print(common, ATH_DBG_CALIBRATE,
2218 + "NF calibrated [ext] [chain 1] is %d\n", nf);
2219 + nfarray[4] = nf;
2220 +
2221 + nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
2222 + if (nf & 0x100)
2223 + nf = 0 - ((nf ^ 0x1ff) + 1);
2224 + ath_print(common, ATH_DBG_CALIBRATE,
2225 + "NF calibrated [ext] [chain 2] is %d\n", nf);
2226 + nfarray[5] = nf;
2227 +}
2228 +
2229 +static void ar5008_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
2230 +{
2231 + struct ath9k_nfcal_hist *h;
2232 + int i, j;
2233 + int32_t val;
2234 + const u32 ar5416_cca_regs[6] = {
2235 + AR_PHY_CCA,
2236 + AR_PHY_CH1_CCA,
2237 + AR_PHY_CH2_CCA,
2238 + AR_PHY_EXT_CCA,
2239 + AR_PHY_CH1_EXT_CCA,
2240 + AR_PHY_CH2_EXT_CCA
2241 + };
2242 + u8 chainmask, rx_chain_status;
2243 +
2244 + rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
2245 + if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2246 + chainmask = 0x9;
2247 + else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
2248 + if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
2249 + chainmask = 0x1B;
2250 + else
2251 + chainmask = 0x09;
2252 + } else {
2253 + if (rx_chain_status & 0x4)
2254 + chainmask = 0x3F;
2255 + else if (rx_chain_status & 0x2)
2256 + chainmask = 0x1B;
2257 + else
2258 + chainmask = 0x09;
2259 + }
2260 +
2261 + h = ah->nfCalHist;
2262 +
2263 + for (i = 0; i < NUM_NF_READINGS; i++) {
2264 + if (chainmask & (1 << i)) {
2265 + val = REG_READ(ah, ar5416_cca_regs[i]);
2266 + val &= 0xFFFFFE00;
2267 + val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
2268 + REG_WRITE(ah, ar5416_cca_regs[i], val);
2269 + }
2270 + }
2271 +
2272 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
2273 + AR_PHY_AGC_CONTROL_ENABLE_NF);
2274 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
2275 + AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
2276 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2277 +
2278 + for (j = 0; j < 5; j++) {
2279 + if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
2280 + AR_PHY_AGC_CONTROL_NF) == 0)
2281 + break;
2282 + udelay(50);
2283 + }
2284 +
2285 + for (i = 0; i < NUM_NF_READINGS; i++) {
2286 + if (chainmask & (1 << i)) {
2287 + val = REG_READ(ah, ar5416_cca_regs[i]);
2288 + val &= 0xFFFFFE00;
2289 + val |= (((u32) (-50) << 1) & 0x1ff);
2290 + REG_WRITE(ah, ar5416_cca_regs[i], val);
2291 + }
2292 + }
2293 +}
2294 +
2295 +void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
2296 +{
2297 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
2298 +
2299 + priv_ops->rf_set_freq = ar5008_hw_set_channel;
2300 + priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
2301 +
2302 + priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
2303 + priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
2304 + priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
2305 + priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
2306 + priv_ops->init_bb = ar5008_hw_init_bb;
2307 + priv_ops->process_ini = ar5008_hw_process_ini;
2308 + priv_ops->set_rfmode = ar5008_hw_set_rfmode;
2309 + priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
2310 + priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
2311 + priv_ops->rfbus_req = ar5008_hw_rfbus_req;
2312 + priv_ops->rfbus_done = ar5008_hw_rfbus_done;
2313 + priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
2314 + priv_ops->restore_chainmask = ar5008_restore_chainmask;
2315 + priv_ops->set_diversity = ar5008_set_diversity;
2316 + priv_ops->ani_control = ar5008_hw_ani_control;
2317 + priv_ops->do_getnf = ar5008_hw_do_getnf;
2318 + priv_ops->loadnf = ar5008_hw_loadnf;
2319 +
2320 + if (AR_SREV_9100(ah))
2321 + priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
2322 + else if (AR_SREV_9160_10_OR_LATER(ah))
2323 + priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
2324 + else
2325 + priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
2326 +}
2327 --- /dev/null
2328 +++ b/drivers/net/wireless/ath/ath9k/ar9001_initvals.h
2329 @@ -0,0 +1,1254 @@
2330 +
2331 +static const u32 ar5416Common_9100[][2] = {
2332 + { 0x0000000c, 0x00000000 },
2333 + { 0x00000030, 0x00020015 },
2334 + { 0x00000034, 0x00000005 },
2335 + { 0x00000040, 0x00000000 },
2336 + { 0x00000044, 0x00000008 },
2337 + { 0x00000048, 0x00000008 },
2338 + { 0x0000004c, 0x00000010 },
2339 + { 0x00000050, 0x00000000 },
2340 + { 0x00000054, 0x0000001f },
2341 + { 0x00000800, 0x00000000 },
2342 + { 0x00000804, 0x00000000 },
2343 + { 0x00000808, 0x00000000 },
2344 + { 0x0000080c, 0x00000000 },
2345 + { 0x00000810, 0x00000000 },
2346 + { 0x00000814, 0x00000000 },
2347 + { 0x00000818, 0x00000000 },
2348 + { 0x0000081c, 0x00000000 },
2349 + { 0x00000820, 0x00000000 },
2350 + { 0x00000824, 0x00000000 },
2351 + { 0x00001040, 0x002ffc0f },
2352 + { 0x00001044, 0x002ffc0f },
2353 + { 0x00001048, 0x002ffc0f },
2354 + { 0x0000104c, 0x002ffc0f },
2355 + { 0x00001050, 0x002ffc0f },
2356 + { 0x00001054, 0x002ffc0f },
2357 + { 0x00001058, 0x002ffc0f },
2358 + { 0x0000105c, 0x002ffc0f },
2359 + { 0x00001060, 0x002ffc0f },
2360 + { 0x00001064, 0x002ffc0f },
2361 + { 0x00001230, 0x00000000 },
2362 + { 0x00001270, 0x00000000 },
2363 + { 0x00001038, 0x00000000 },
2364 + { 0x00001078, 0x00000000 },
2365 + { 0x000010b8, 0x00000000 },
2366 + { 0x000010f8, 0x00000000 },
2367 + { 0x00001138, 0x00000000 },
2368 + { 0x00001178, 0x00000000 },
2369 + { 0x000011b8, 0x00000000 },
2370 + { 0x000011f8, 0x00000000 },
2371 + { 0x00001238, 0x00000000 },
2372 + { 0x00001278, 0x00000000 },
2373 + { 0x000012b8, 0x00000000 },
2374 + { 0x000012f8, 0x00000000 },
2375 + { 0x00001338, 0x00000000 },
2376 + { 0x00001378, 0x00000000 },
2377 + { 0x000013b8, 0x00000000 },
2378 + { 0x000013f8, 0x00000000 },
2379 + { 0x00001438, 0x00000000 },
2380 + { 0x00001478, 0x00000000 },
2381 + { 0x000014b8, 0x00000000 },
2382 + { 0x000014f8, 0x00000000 },
2383 + { 0x00001538, 0x00000000 },
2384 + { 0x00001578, 0x00000000 },
2385 + { 0x000015b8, 0x00000000 },
2386 + { 0x000015f8, 0x00000000 },
2387 + { 0x00001638, 0x00000000 },
2388 + { 0x00001678, 0x00000000 },
2389 + { 0x000016b8, 0x00000000 },
2390 + { 0x000016f8, 0x00000000 },
2391 + { 0x00001738, 0x00000000 },
2392 + { 0x00001778, 0x00000000 },
2393 + { 0x000017b8, 0x00000000 },
2394 + { 0x000017f8, 0x00000000 },
2395 + { 0x0000103c, 0x00000000 },
2396 + { 0x0000107c, 0x00000000 },
2397 + { 0x000010bc, 0x00000000 },
2398 + { 0x000010fc, 0x00000000 },
2399 + { 0x0000113c, 0x00000000 },
2400 + { 0x0000117c, 0x00000000 },
2401 + { 0x000011bc, 0x00000000 },
2402 + { 0x000011fc, 0x00000000 },
2403 + { 0x0000123c, 0x00000000 },
2404 + { 0x0000127c, 0x00000000 },
2405 + { 0x000012bc, 0x00000000 },
2406 + { 0x000012fc, 0x00000000 },
2407 + { 0x0000133c, 0x00000000 },
2408 + { 0x0000137c, 0x00000000 },
2409 + { 0x000013bc, 0x00000000 },
2410 + { 0x000013fc, 0x00000000 },
2411 + { 0x0000143c, 0x00000000 },
2412 + { 0x0000147c, 0x00000000 },
2413 + { 0x00020010, 0x00000003 },
2414 + { 0x00020038, 0x000004c2 },
2415 + { 0x00008004, 0x00000000 },
2416 + { 0x00008008, 0x00000000 },
2417 + { 0x0000800c, 0x00000000 },
2418 + { 0x00008018, 0x00000700 },
2419 + { 0x00008020, 0x00000000 },
2420 + { 0x00008038, 0x00000000 },
2421 + { 0x0000803c, 0x00000000 },
2422 + { 0x00008048, 0x40000000 },
2423 + { 0x00008054, 0x00004000 },
2424 + { 0x00008058, 0x00000000 },
2425 + { 0x0000805c, 0x000fc78f },
2426 + { 0x00008060, 0x0000000f },
2427 + { 0x00008064, 0x00000000 },
2428 + { 0x000080c0, 0x2a82301a },
2429 + { 0x000080c4, 0x05dc01e0 },
2430 + { 0x000080c8, 0x1f402710 },
2431 + { 0x000080cc, 0x01f40000 },
2432 + { 0x000080d0, 0x00001e00 },
2433 + { 0x000080d4, 0x00000000 },
2434 + { 0x000080d8, 0x00400000 },
2435 + { 0x000080e0, 0xffffffff },
2436 + { 0x000080e4, 0x0000ffff },
2437 + { 0x000080e8, 0x003f3f3f },
2438 + { 0x000080ec, 0x00000000 },
2439 + { 0x000080f0, 0x00000000 },
2440 + { 0x000080f4, 0x00000000 },
2441 + { 0x000080f8, 0x00000000 },
2442 + { 0x000080fc, 0x00020000 },
2443 + { 0x00008100, 0x00020000 },
2444 + { 0x00008104, 0x00000001 },
2445 + { 0x00008108, 0x00000052 },
2446 + { 0x0000810c, 0x00000000 },
2447 + { 0x00008110, 0x00000168 },
2448 + { 0x00008118, 0x000100aa },
2449 + { 0x0000811c, 0x00003210 },
2450 + { 0x00008120, 0x08f04800 },
2451 + { 0x00008124, 0x00000000 },
2452 + { 0x00008128, 0x00000000 },
2453 + { 0x0000812c, 0x00000000 },
2454 + { 0x00008130, 0x00000000 },
2455 + { 0x00008134, 0x00000000 },
2456 + { 0x00008138, 0x00000000 },
2457 + { 0x0000813c, 0x00000000 },
2458 + { 0x00008144, 0x00000000 },
2459 + { 0x00008168, 0x00000000 },
2460 + { 0x0000816c, 0x00000000 },
2461 + { 0x00008170, 0x32143320 },
2462 + { 0x00008174, 0xfaa4fa50 },
2463 + { 0x00008178, 0x00000100 },
2464 + { 0x0000817c, 0x00000000 },
2465 + { 0x000081c4, 0x00000000 },
2466 + { 0x000081d0, 0x00003210 },
2467 + { 0x000081ec, 0x00000000 },
2468 + { 0x000081f0, 0x00000000 },
2469 + { 0x000081f4, 0x00000000 },
2470 + { 0x000081f8, 0x00000000 },
2471 + { 0x000081fc, 0x00000000 },
2472 + { 0x00008200, 0x00000000 },
2473 + { 0x00008204, 0x00000000 },
2474 + { 0x00008208, 0x00000000 },
2475 + { 0x0000820c, 0x00000000 },
2476 + { 0x00008210, 0x00000000 },
2477 + { 0x00008214, 0x00000000 },
2478 + { 0x00008218, 0x00000000 },
2479 + { 0x0000821c, 0x00000000 },
2480 + { 0x00008220, 0x00000000 },
2481 + { 0x00008224, 0x00000000 },
2482 + { 0x00008228, 0x00000000 },
2483 + { 0x0000822c, 0x00000000 },
2484 + { 0x00008230, 0x00000000 },
2485 + { 0x00008234, 0x00000000 },
2486 + { 0x00008238, 0x00000000 },
2487 + { 0x0000823c, 0x00000000 },
2488 + { 0x00008240, 0x00100000 },
2489 + { 0x00008244, 0x0010f400 },
2490 + { 0x00008248, 0x00000100 },
2491 + { 0x0000824c, 0x0001e800 },
2492 + { 0x00008250, 0x00000000 },
2493 + { 0x00008254, 0x00000000 },
2494 + { 0x00008258, 0x00000000 },
2495 + { 0x0000825c, 0x400000ff },
2496 + { 0x00008260, 0x00080922 },
2497 + { 0x00008270, 0x00000000 },
2498 + { 0x00008274, 0x40000000 },
2499 + { 0x00008278, 0x003e4180 },
2500 + { 0x0000827c, 0x00000000 },
2501 + { 0x00008284, 0x0000002c },
2502 + { 0x00008288, 0x0000002c },
2503 + { 0x0000828c, 0x00000000 },
2504 + { 0x00008294, 0x00000000 },
2505 + { 0x00008298, 0x00000000 },
2506 + { 0x00008300, 0x00000000 },
2507 + { 0x00008304, 0x00000000 },
2508 + { 0x00008308, 0x00000000 },
2509 + { 0x0000830c, 0x00000000 },
2510 + { 0x00008310, 0x00000000 },
2511 + { 0x00008314, 0x00000000 },
2512 + { 0x00008318, 0x00000000 },
2513 + { 0x00008328, 0x00000000 },
2514 + { 0x0000832c, 0x00000007 },
2515 + { 0x00008330, 0x00000302 },
2516 + { 0x00008334, 0x00000e00 },
2517 + { 0x00008338, 0x00000000 },
2518 + { 0x0000833c, 0x00000000 },
2519 + { 0x00008340, 0x000107ff },
2520 + { 0x00009808, 0x00000000 },
2521 + { 0x0000980c, 0xad848e19 },
2522 + { 0x00009810, 0x7d14e000 },
2523 + { 0x00009814, 0x9c0a9f6b },
2524 + { 0x0000981c, 0x00000000 },
2525 + { 0x0000982c, 0x0000a000 },
2526 + { 0x00009830, 0x00000000 },
2527 + { 0x0000983c, 0x00200400 },
2528 + { 0x00009840, 0x206a01ae },
2529 + { 0x0000984c, 0x1284233c },
2530 + { 0x00009854, 0x00000859 },
2531 + { 0x00009900, 0x00000000 },
2532 + { 0x00009904, 0x00000000 },
2533 + { 0x00009908, 0x00000000 },
2534 + { 0x0000990c, 0x00000000 },
2535 + { 0x0000991c, 0x10000fff },
2536 + { 0x00009920, 0x05100000 },
2537 + { 0x0000a920, 0x05100000 },
2538 + { 0x0000b920, 0x05100000 },
2539 + { 0x00009928, 0x00000001 },
2540 + { 0x0000992c, 0x00000004 },
2541 + { 0x00009934, 0x1e1f2022 },
2542 + { 0x00009938, 0x0a0b0c0d },
2543 + { 0x0000993c, 0x00000000 },
2544 + { 0x00009948, 0x9280b212 },
2545 + { 0x0000994c, 0x00020028 },
2546 + { 0x0000c95c, 0x004b6a8e },
2547 + { 0x0000c968, 0x000003ce },
2548 + { 0x00009970, 0x190fb515 },
2549 + { 0x00009974, 0x00000000 },
2550 + { 0x00009978, 0x00000001 },
2551 + { 0x0000997c, 0x00000000 },
2552 + { 0x00009980, 0x00000000 },
2553 + { 0x00009984, 0x00000000 },
2554 + { 0x00009988, 0x00000000 },
2555 + { 0x0000998c, 0x00000000 },
2556 + { 0x00009990, 0x00000000 },
2557 + { 0x00009994, 0x00000000 },
2558 + { 0x00009998, 0x00000000 },
2559 + { 0x0000999c, 0x00000000 },
2560 + { 0x000099a0, 0x00000000 },
2561 + { 0x000099a4, 0x00000001 },
2562 + { 0x000099a8, 0x201fff00 },
2563 + { 0x000099ac, 0x006f0000 },
2564 + { 0x000099b0, 0x03051000 },
2565 + { 0x000099dc, 0x00000000 },
2566 + { 0x000099e0, 0x00000200 },
2567 + { 0x000099e4, 0xaaaaaaaa },
2568 + { 0x000099e8, 0x3c466478 },
2569 + { 0x000099ec, 0x0cc80caa },
2570 + { 0x000099fc, 0x00001042 },
2571 + { 0x00009b00, 0x00000000 },
2572 + { 0x00009b04, 0x00000001 },
2573 + { 0x00009b08, 0x00000002 },
2574 + { 0x00009b0c, 0x00000003 },
2575 + { 0x00009b10, 0x00000004 },
2576 + { 0x00009b14, 0x00000005 },
2577 + { 0x00009b18, 0x00000008 },
2578 + { 0x00009b1c, 0x00000009 },
2579 + { 0x00009b20, 0x0000000a },
2580 + { 0x00009b24, 0x0000000b },
2581 + { 0x00009b28, 0x0000000c },
2582 + { 0x00009b2c, 0x0000000d },
2583 + { 0x00009b30, 0x00000010 },
2584 + { 0x00009b34, 0x00000011 },
2585 + { 0x00009b38, 0x00000012 },
2586 + { 0x00009b3c, 0x00000013 },
2587 + { 0x00009b40, 0x00000014 },
2588 + { 0x00009b44, 0x00000015 },
2589 + { 0x00009b48, 0x00000018 },
2590 + { 0x00009b4c, 0x00000019 },
2591 + { 0x00009b50, 0x0000001a },
2592 + { 0x00009b54, 0x0000001b },
2593 + { 0x00009b58, 0x0000001c },
2594 + { 0x00009b5c, 0x0000001d },
2595 + { 0x00009b60, 0x00000020 },
2596 + { 0x00009b64, 0x00000021 },
2597 + { 0x00009b68, 0x00000022 },
2598 + { 0x00009b6c, 0x00000023 },
2599 + { 0x00009b70, 0x00000024 },
2600 + { 0x00009b74, 0x00000025 },
2601 + { 0x00009b78, 0x00000028 },
2602 + { 0x00009b7c, 0x00000029 },
2603 + { 0x00009b80, 0x0000002a },
2604 + { 0x00009b84, 0x0000002b },
2605 + { 0x00009b88, 0x0000002c },
2606 + { 0x00009b8c, 0x0000002d },
2607 + { 0x00009b90, 0x00000030 },
2608 + { 0x00009b94, 0x00000031 },
2609 + { 0x00009b98, 0x00000032 },
2610 + { 0x00009b9c, 0x00000033 },
2611 + { 0x00009ba0, 0x00000034 },
2612 + { 0x00009ba4, 0x00000035 },
2613 + { 0x00009ba8, 0x00000035 },
2614 + { 0x00009bac, 0x00000035 },
2615 + { 0x00009bb0, 0x00000035 },
2616 + { 0x00009bb4, 0x00000035 },
2617 + { 0x00009bb8, 0x00000035 },
2618 + { 0x00009bbc, 0x00000035 },
2619 + { 0x00009bc0, 0x00000035 },
2620 + { 0x00009bc4, 0x00000035 },
2621 + { 0x00009bc8, 0x00000035 },
2622 + { 0x00009bcc, 0x00000035 },
2623 + { 0x00009bd0, 0x00000035 },
2624 + { 0x00009bd4, 0x00000035 },
2625 + { 0x00009bd8, 0x00000035 },
2626 + { 0x00009bdc, 0x00000035 },
2627 + { 0x00009be0, 0x00000035 },
2628 + { 0x00009be4, 0x00000035 },
2629 + { 0x00009be8, 0x00000035 },
2630 + { 0x00009bec, 0x00000035 },
2631 + { 0x00009bf0, 0x00000035 },
2632 + { 0x00009bf4, 0x00000035 },
2633 + { 0x00009bf8, 0x00000010 },
2634 + { 0x00009bfc, 0x0000001a },
2635 + { 0x0000a210, 0x40806333 },
2636 + { 0x0000a214, 0x00106c10 },
2637 + { 0x0000a218, 0x009c4060 },
2638 + { 0x0000a220, 0x018830c6 },
2639 + { 0x0000a224, 0x00000400 },
2640 + { 0x0000a228, 0x001a0bb5 },
2641 + { 0x0000a22c, 0x00000000 },
2642 + { 0x0000a234, 0x20202020 },
2643 + { 0x0000a238, 0x20202020 },
2644 + { 0x0000a23c, 0x13c889ae },
2645 + { 0x0000a240, 0x38490a20 },
2646 + { 0x0000a244, 0x00007bb6 },
2647 + { 0x0000a248, 0x0fff3ffc },
2648 + { 0x0000a24c, 0x00000001 },
2649 + { 0x0000a250, 0x0000a000 },
2650 + { 0x0000a254, 0x00000000 },
2651 + { 0x0000a258, 0x0cc75380 },
2652 + { 0x0000a25c, 0x0f0f0f01 },
2653 + { 0x0000a260, 0xdfa91f01 },
2654 + { 0x0000a268, 0x00000001 },
2655 + { 0x0000a26c, 0x0ebae9c6 },
2656 + { 0x0000b26c, 0x0ebae9c6 },
2657 + { 0x0000c26c, 0x0ebae9c6 },
2658 + { 0x0000d270, 0x00820820 },
2659 + { 0x0000a278, 0x1ce739ce },
2660 + { 0x0000a27c, 0x050701ce },
2661 + { 0x0000a338, 0x00000000 },
2662 + { 0x0000a33c, 0x00000000 },
2663 + { 0x0000a340, 0x00000000 },
2664 + { 0x0000a344, 0x00000000 },
2665 + { 0x0000a348, 0x3fffffff },
2666 + { 0x0000a34c, 0x3fffffff },
2667 + { 0x0000a350, 0x3fffffff },
2668 + { 0x0000a354, 0x0003ffff },
2669 + { 0x0000a358, 0x79a8aa33 },
2670 + { 0x0000d35c, 0x07ffffef },
2671 + { 0x0000d360, 0x0fffffe7 },
2672 + { 0x0000d364, 0x17ffffe5 },
2673 + { 0x0000d368, 0x1fffffe4 },
2674 + { 0x0000d36c, 0x37ffffe3 },
2675 + { 0x0000d370, 0x3fffffe3 },
2676 + { 0x0000d374, 0x57ffffe3 },
2677 + { 0x0000d378, 0x5fffffe2 },
2678 + { 0x0000d37c, 0x7fffffe2 },
2679 + { 0x0000d380, 0x7f3c7bba },
2680 + { 0x0000d384, 0xf3307ff0 },
2681 + { 0x0000a388, 0x0c000000 },
2682 + { 0x0000a38c, 0x20202020 },
2683 + { 0x0000a390, 0x20202020 },
2684 + { 0x0000a394, 0x1ce739ce },
2685 + { 0x0000a398, 0x000001ce },
2686 + { 0x0000a39c, 0x00000001 },
2687 + { 0x0000a3a0, 0x00000000 },
2688 + { 0x0000a3a4, 0x00000000 },
2689 + { 0x0000a3a8, 0x00000000 },
2690 + { 0x0000a3ac, 0x00000000 },
2691 + { 0x0000a3b0, 0x00000000 },
2692 + { 0x0000a3b4, 0x00000000 },
2693 + { 0x0000a3b8, 0x00000000 },
2694 + { 0x0000a3bc, 0x00000000 },
2695 + { 0x0000a3c0, 0x00000000 },
2696 + { 0x0000a3c4, 0x00000000 },
2697 + { 0x0000a3c8, 0x00000246 },
2698 + { 0x0000a3cc, 0x20202020 },
2699 + { 0x0000a3d0, 0x20202020 },
2700 + { 0x0000a3d4, 0x20202020 },
2701 + { 0x0000a3dc, 0x1ce739ce },
2702 + { 0x0000a3e0, 0x000001ce },
2703 +};
2704 +
2705 +static const u32 ar5416Bank0_9100[][2] = {
2706 + { 0x000098b0, 0x1e5795e5 },
2707 + { 0x000098e0, 0x02008020 },
2708 +};
2709 +
2710 +static const u32 ar5416BB_RfGain_9100[][3] = {
2711 + { 0x00009a00, 0x00000000, 0x00000000 },
2712 + { 0x00009a04, 0x00000040, 0x00000040 },
2713 + { 0x00009a08, 0x00000080, 0x00000080 },
2714 + { 0x00009a0c, 0x000001a1, 0x00000141 },
2715 + { 0x00009a10, 0x000001e1, 0x00000181 },
2716 + { 0x00009a14, 0x00000021, 0x000001c1 },
2717 + { 0x00009a18, 0x00000061, 0x00000001 },
2718 + { 0x00009a1c, 0x00000168, 0x00000041 },
2719 + { 0x00009a20, 0x000001a8, 0x000001a8 },
2720 + { 0x00009a24, 0x000001e8, 0x000001e8 },
2721 + { 0x00009a28, 0x00000028, 0x00000028 },
2722 + { 0x00009a2c, 0x00000068, 0x00000068 },
2723 + { 0x00009a30, 0x00000189, 0x000000a8 },
2724 + { 0x00009a34, 0x000001c9, 0x00000169 },
2725 + { 0x00009a38, 0x00000009, 0x000001a9 },
2726 + { 0x00009a3c, 0x00000049, 0x000001e9 },
2727 + { 0x00009a40, 0x00000089, 0x00000029 },
2728 + { 0x00009a44, 0x00000170, 0x00000069 },
2729 + { 0x00009a48, 0x000001b0, 0x00000190 },
2730 + { 0x00009a4c, 0x000001f0, 0x000001d0 },
2731 + { 0x00009a50, 0x00000030, 0x00000010 },
2732 + { 0x00009a54, 0x00000070, 0x00000050 },
2733 + { 0x00009a58, 0x00000191, 0x00000090 },
2734 + { 0x00009a5c, 0x000001d1, 0x00000151 },
2735 + { 0x00009a60, 0x00000011, 0x00000191 },
2736 + { 0x00009a64, 0x00000051, 0x000001d1 },
2737 + { 0x00009a68, 0x00000091, 0x00000011 },
2738 + { 0x00009a6c, 0x000001b8, 0x00000051 },
2739 + { 0x00009a70, 0x000001f8, 0x00000198 },
2740 + { 0x00009a74, 0x00000038, 0x000001d8 },
2741 + { 0x00009a78, 0x00000078, 0x00000018 },
2742 + { 0x00009a7c, 0x00000199, 0x00000058 },
2743 + { 0x00009a80, 0x000001d9, 0x00000098 },
2744 + { 0x00009a84, 0x00000019, 0x00000159 },
2745 + { 0x00009a88, 0x00000059, 0x00000199 },
2746 + { 0x00009a8c, 0x00000099, 0x000001d9 },
2747 + { 0x00009a90, 0x000000d9, 0x00000019 },
2748 + { 0x00009a94, 0x000000f9, 0x00000059 },
2749 + { 0x00009a98, 0x000000f9, 0x00000099 },
2750 + { 0x00009a9c, 0x000000f9, 0x000000d9 },
2751 + { 0x00009aa0, 0x000000f9, 0x000000f9 },
2752 + { 0x00009aa4, 0x000000f9, 0x000000f9 },
2753 + { 0x00009aa8, 0x000000f9, 0x000000f9 },
2754 + { 0x00009aac, 0x000000f9, 0x000000f9 },
2755 + { 0x00009ab0, 0x000000f9, 0x000000f9 },
2756 + { 0x00009ab4, 0x000000f9, 0x000000f9 },
2757 + { 0x00009ab8, 0x000000f9, 0x000000f9 },
2758 + { 0x00009abc, 0x000000f9, 0x000000f9 },
2759 + { 0x00009ac0, 0x000000f9, 0x000000f9 },
2760 + { 0x00009ac4, 0x000000f9, 0x000000f9 },
2761 + { 0x00009ac8, 0x000000f9, 0x000000f9 },
2762 + { 0x00009acc, 0x000000f9, 0x000000f9 },
2763 + { 0x00009ad0, 0x000000f9, 0x000000f9 },
2764 + { 0x00009ad4, 0x000000f9, 0x000000f9 },
2765 + { 0x00009ad8, 0x000000f9, 0x000000f9 },
2766 + { 0x00009adc, 0x000000f9, 0x000000f9 },
2767 + { 0x00009ae0, 0x000000f9, 0x000000f9 },
2768 + { 0x00009ae4, 0x000000f9, 0x000000f9 },
2769 + { 0x00009ae8, 0x000000f9, 0x000000f9 },
2770 + { 0x00009aec, 0x000000f9, 0x000000f9 },
2771 + { 0x00009af0, 0x000000f9, 0x000000f9 },
2772 + { 0x00009af4, 0x000000f9, 0x000000f9 },
2773 + { 0x00009af8, 0x000000f9, 0x000000f9 },
2774 + { 0x00009afc, 0x000000f9, 0x000000f9 },
2775 +};
2776 +
2777 +static const u32 ar5416Bank1_9100[][2] = {
2778 + { 0x000098b0, 0x02108421},
2779 + { 0x000098ec, 0x00000008},
2780 +};
2781 +
2782 +static const u32 ar5416Bank2_9100[][2] = {
2783 + { 0x000098b0, 0x0e73ff17},
2784 + { 0x000098e0, 0x00000420},
2785 +};
2786 +
2787 +static const u32 ar5416Bank3_9100[][3] = {
2788 + { 0x000098f0, 0x01400018, 0x01c00018 },
2789 +};
2790 +
2791 +static const u32 ar5416Bank6_9100[][3] = {
2792 +
2793 + { 0x0000989c, 0x00000000, 0x00000000 },
2794 + { 0x0000989c, 0x00000000, 0x00000000 },
2795 + { 0x0000989c, 0x00000000, 0x00000000 },
2796 + { 0x0000989c, 0x00e00000, 0x00e00000 },
2797 + { 0x0000989c, 0x005e0000, 0x005e0000 },
2798 + { 0x0000989c, 0x00120000, 0x00120000 },
2799 + { 0x0000989c, 0x00620000, 0x00620000 },
2800 + { 0x0000989c, 0x00020000, 0x00020000 },
2801 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2802 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2803 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2804 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2805 + { 0x0000989c, 0x005f0000, 0x005f0000 },
2806 + { 0x0000989c, 0x00870000, 0x00870000 },
2807 + { 0x0000989c, 0x00f90000, 0x00f90000 },
2808 + { 0x0000989c, 0x007b0000, 0x007b0000 },
2809 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2810 + { 0x0000989c, 0x00f50000, 0x00f50000 },
2811 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
2812 + { 0x0000989c, 0x00110000, 0x00110000 },
2813 + { 0x0000989c, 0x006100a8, 0x006100a8 },
2814 + { 0x0000989c, 0x004210a2, 0x004210a2 },
2815 + { 0x0000989c, 0x0014000f, 0x0014000f },
2816 + { 0x0000989c, 0x00c40002, 0x00c40002 },
2817 + { 0x0000989c, 0x003000f2, 0x003000f2 },
2818 + { 0x0000989c, 0x00440016, 0x00440016 },
2819 + { 0x0000989c, 0x00410040, 0x00410040 },
2820 + { 0x0000989c, 0x000180d6, 0x000180d6 },
2821 + { 0x0000989c, 0x0000c0aa, 0x0000c0aa },
2822 + { 0x0000989c, 0x000000b1, 0x000000b1 },
2823 + { 0x0000989c, 0x00002000, 0x00002000 },
2824 + { 0x0000989c, 0x000000d4, 0x000000d4 },
2825 + { 0x000098d0, 0x0000000f, 0x0010000f },
2826 +};
2827 +
2828 +
2829 +static const u32 ar5416Bank6TPC_9100[][3] = {
2830 +
2831 + { 0x0000989c, 0x00000000, 0x00000000 },
2832 + { 0x0000989c, 0x00000000, 0x00000000 },
2833 + { 0x0000989c, 0x00000000, 0x00000000 },
2834 + { 0x0000989c, 0x00e00000, 0x00e00000 },
2835 + { 0x0000989c, 0x005e0000, 0x005e0000 },
2836 + { 0x0000989c, 0x00120000, 0x00120000 },
2837 + { 0x0000989c, 0x00620000, 0x00620000 },
2838 + { 0x0000989c, 0x00020000, 0x00020000 },
2839 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2840 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2841 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2842 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
2843 + { 0x0000989c, 0x005f0000, 0x005f0000 },
2844 + { 0x0000989c, 0x00870000, 0x00870000 },
2845 + { 0x0000989c, 0x00f90000, 0x00f90000 },
2846 + { 0x0000989c, 0x007b0000, 0x007b0000 },
2847 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2848 + { 0x0000989c, 0x00f50000, 0x00f50000 },
2849 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
2850 + { 0x0000989c, 0x00110000, 0x00110000 },
2851 + { 0x0000989c, 0x006100a8, 0x006100a8 },
2852 + { 0x0000989c, 0x00423022, 0x00423022 },
2853 + { 0x0000989c, 0x2014008f, 0x2014008f },
2854 + { 0x0000989c, 0x00c40002, 0x00c40002 },
2855 + { 0x0000989c, 0x003000f2, 0x003000f2 },
2856 + { 0x0000989c, 0x00440016, 0x00440016 },
2857 + { 0x0000989c, 0x00410040, 0x00410040 },
2858 + { 0x0000989c, 0x0001805e, 0x0001805e },
2859 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
2860 + { 0x0000989c, 0x000000e1, 0x000000e1 },
2861 + { 0x0000989c, 0x00007080, 0x00007080 },
2862 + { 0x0000989c, 0x000000d4, 0x000000d4 },
2863 + { 0x000098d0, 0x0000000f, 0x0010000f },
2864 +};
2865 +
2866 +static const u32 ar5416Bank7_9100[][2] = {
2867 + { 0x0000989c, 0x00000500 },
2868 + { 0x0000989c, 0x00000800 },
2869 + { 0x000098cc, 0x0000000e },
2870 +};
2871 +
2872 +static const u32 ar5416Addac_9100[][2] = {
2873 + {0x0000989c, 0x00000000 },
2874 + {0x0000989c, 0x00000000 },
2875 + {0x0000989c, 0x00000000 },
2876 + {0x0000989c, 0x00000000 },
2877 + {0x0000989c, 0x00000000 },
2878 + {0x0000989c, 0x00000000 },
2879 + {0x0000989c, 0x00000000 },
2880 + {0x0000989c, 0x00000010 },
2881 + {0x0000989c, 0x00000000 },
2882 + {0x0000989c, 0x00000000 },
2883 + {0x0000989c, 0x00000000 },
2884 + {0x0000989c, 0x00000000 },
2885 + {0x0000989c, 0x00000000 },
2886 + {0x0000989c, 0x00000000 },
2887 + {0x0000989c, 0x00000000 },
2888 + {0x0000989c, 0x00000000 },
2889 + {0x0000989c, 0x00000000 },
2890 + {0x0000989c, 0x00000000 },
2891 + {0x0000989c, 0x00000000 },
2892 + {0x0000989c, 0x00000000 },
2893 + {0x0000989c, 0x00000000 },
2894 + {0x0000989c, 0x000000c0 },
2895 + {0x0000989c, 0x00000015 },
2896 + {0x0000989c, 0x00000000 },
2897 + {0x0000989c, 0x00000000 },
2898 + {0x0000989c, 0x00000000 },
2899 + {0x0000989c, 0x00000000 },
2900 + {0x0000989c, 0x00000000 },
2901 + {0x0000989c, 0x00000000 },
2902 + {0x0000989c, 0x00000000 },
2903 + {0x0000989c, 0x00000000 },
2904 + {0x000098cc, 0x00000000 },
2905 +};
2906 +
2907 +static const u32 ar5416Modes_9160[][6] = {
2908 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
2909 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
2910 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
2911 + { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
2912 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
2913 + { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
2914 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
2915 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
2916 + { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
2917 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
2918 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
2919 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
2920 + { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
2921 + { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
2922 + { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
2923 + { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
2924 + { 0x00009850, 0x6c48b4e2, 0x6c48b4e2, 0x6c48b0e2, 0x6c48b0e2, 0x6c48b0e2 },
2925 + { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
2926 + { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e },
2927 + { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
2928 + { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
2929 + { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
2930 + { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
2931 + { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
2932 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
2933 + { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
2934 + { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
2935 + { 0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
2936 + { 0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
2937 + { 0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
2938 + { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
2939 + { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
2940 + { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00, 0x001a0c00 },
2941 + { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
2942 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
2943 + { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
2944 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
2945 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
2946 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2947 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2948 + { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
2949 + { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
2950 + { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
2951 + { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
2952 + { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
2953 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
2954 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
2955 + { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
2956 + { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
2957 + { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
2958 + { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
2959 + { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
2960 + { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
2961 + { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
2962 + { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
2963 + { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
2964 + { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
2965 + { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
2966 + { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
2967 + { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2968 + { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2969 + { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2970 +};
2971 +
2972 +static const u32 ar5416Common_9160[][2] = {
2973 + { 0x0000000c, 0x00000000 },
2974 + { 0x00000030, 0x00020015 },
2975 + { 0x00000034, 0x00000005 },
2976 + { 0x00000040, 0x00000000 },
2977 + { 0x00000044, 0x00000008 },
2978 + { 0x00000048, 0x00000008 },
2979 + { 0x0000004c, 0x00000010 },
2980 + { 0x00000050, 0x00000000 },
2981 + { 0x00000054, 0x0000001f },
2982 + { 0x00000800, 0x00000000 },
2983 + { 0x00000804, 0x00000000 },
2984 + { 0x00000808, 0x00000000 },
2985 + { 0x0000080c, 0x00000000 },
2986 + { 0x00000810, 0x00000000 },
2987 + { 0x00000814, 0x00000000 },
2988 + { 0x00000818, 0x00000000 },
2989 + { 0x0000081c, 0x00000000 },
2990 + { 0x00000820, 0x00000000 },
2991 + { 0x00000824, 0x00000000 },
2992 + { 0x00001040, 0x002ffc0f },
2993 + { 0x00001044, 0x002ffc0f },
2994 + { 0x00001048, 0x002ffc0f },
2995 + { 0x0000104c, 0x002ffc0f },
2996 + { 0x00001050, 0x002ffc0f },
2997 + { 0x00001054, 0x002ffc0f },
2998 + { 0x00001058, 0x002ffc0f },
2999 + { 0x0000105c, 0x002ffc0f },
3000 + { 0x00001060, 0x002ffc0f },
3001 + { 0x00001064, 0x002ffc0f },
3002 + { 0x00001230, 0x00000000 },
3003 + { 0x00001270, 0x00000000 },
3004 + { 0x00001038, 0x00000000 },
3005 + { 0x00001078, 0x00000000 },
3006 + { 0x000010b8, 0x00000000 },
3007 + { 0x000010f8, 0x00000000 },
3008 + { 0x00001138, 0x00000000 },
3009 + { 0x00001178, 0x00000000 },
3010 + { 0x000011b8, 0x00000000 },
3011 + { 0x000011f8, 0x00000000 },
3012 + { 0x00001238, 0x00000000 },
3013 + { 0x00001278, 0x00000000 },
3014 + { 0x000012b8, 0x00000000 },
3015 + { 0x000012f8, 0x00000000 },
3016 + { 0x00001338, 0x00000000 },
3017 + { 0x00001378, 0x00000000 },
3018 + { 0x000013b8, 0x00000000 },
3019 + { 0x000013f8, 0x00000000 },
3020 + { 0x00001438, 0x00000000 },
3021 + { 0x00001478, 0x00000000 },
3022 + { 0x000014b8, 0x00000000 },
3023 + { 0x000014f8, 0x00000000 },
3024 + { 0x00001538, 0x00000000 },
3025 + { 0x00001578, 0x00000000 },
3026 + { 0x000015b8, 0x00000000 },
3027 + { 0x000015f8, 0x00000000 },
3028 + { 0x00001638, 0x00000000 },
3029 + { 0x00001678, 0x00000000 },
3030 + { 0x000016b8, 0x00000000 },
3031 + { 0x000016f8, 0x00000000 },
3032 + { 0x00001738, 0x00000000 },
3033 + { 0x00001778, 0x00000000 },
3034 + { 0x000017b8, 0x00000000 },
3035 + { 0x000017f8, 0x00000000 },
3036 + { 0x0000103c, 0x00000000 },
3037 + { 0x0000107c, 0x00000000 },
3038 + { 0x000010bc, 0x00000000 },
3039 + { 0x000010fc, 0x00000000 },
3040 + { 0x0000113c, 0x00000000 },
3041 + { 0x0000117c, 0x00000000 },
3042 + { 0x000011bc, 0x00000000 },
3043 + { 0x000011fc, 0x00000000 },
3044 + { 0x0000123c, 0x00000000 },
3045 + { 0x0000127c, 0x00000000 },
3046 + { 0x000012bc, 0x00000000 },
3047 + { 0x000012fc, 0x00000000 },
3048 + { 0x0000133c, 0x00000000 },
3049 + { 0x0000137c, 0x00000000 },
3050 + { 0x000013bc, 0x00000000 },
3051 + { 0x000013fc, 0x00000000 },
3052 + { 0x0000143c, 0x00000000 },
3053 + { 0x0000147c, 0x00000000 },
3054 + { 0x00004030, 0x00000002 },
3055 + { 0x0000403c, 0x00000002 },
3056 + { 0x00007010, 0x00000020 },
3057 + { 0x00007038, 0x000004c2 },
3058 + { 0x00008004, 0x00000000 },
3059 + { 0x00008008, 0x00000000 },
3060 + { 0x0000800c, 0x00000000 },
3061 + { 0x00008018, 0x00000700 },
3062 + { 0x00008020, 0x00000000 },
3063 + { 0x00008038, 0x00000000 },
3064 + { 0x0000803c, 0x00000000 },
3065 + { 0x00008048, 0x40000000 },
3066 + { 0x00008054, 0x00000000 },
3067 + { 0x00008058, 0x00000000 },
3068 + { 0x0000805c, 0x000fc78f },
3069 + { 0x00008060, 0x0000000f },
3070 + { 0x00008064, 0x00000000 },
3071 + { 0x000080c0, 0x2a82301a },
3072 + { 0x000080c4, 0x05dc01e0 },
3073 + { 0x000080c8, 0x1f402710 },
3074 + { 0x000080cc, 0x01f40000 },
3075 + { 0x000080d0, 0x00001e00 },
3076 + { 0x000080d4, 0x00000000 },
3077 + { 0x000080d8, 0x00400000 },
3078 + { 0x000080e0, 0xffffffff },
3079 + { 0x000080e4, 0x0000ffff },
3080 + { 0x000080e8, 0x003f3f3f },
3081 + { 0x000080ec, 0x00000000 },
3082 + { 0x000080f0, 0x00000000 },
3083 + { 0x000080f4, 0x00000000 },
3084 + { 0x000080f8, 0x00000000 },
3085 + { 0x000080fc, 0x00020000 },
3086 + { 0x00008100, 0x00020000 },
3087 + { 0x00008104, 0x00000001 },
3088 + { 0x00008108, 0x00000052 },
3089 + { 0x0000810c, 0x00000000 },
3090 + { 0x00008110, 0x00000168 },
3091 + { 0x00008118, 0x000100aa },
3092 + { 0x0000811c, 0x00003210 },
3093 + { 0x00008120, 0x08f04800 },
3094 + { 0x00008124, 0x00000000 },
3095 + { 0x00008128, 0x00000000 },
3096 + { 0x0000812c, 0x00000000 },
3097 + { 0x00008130, 0x00000000 },
3098 + { 0x00008134, 0x00000000 },
3099 + { 0x00008138, 0x00000000 },
3100 + { 0x0000813c, 0x00000000 },
3101 + { 0x00008144, 0xffffffff },
3102 + { 0x00008168, 0x00000000 },
3103 + { 0x0000816c, 0x00000000 },
3104 + { 0x00008170, 0x32143320 },
3105 + { 0x00008174, 0xfaa4fa50 },
3106 + { 0x00008178, 0x00000100 },
3107 + { 0x0000817c, 0x00000000 },
3108 + { 0x000081c4, 0x00000000 },
3109 + { 0x000081d0, 0x00003210 },
3110 + { 0x000081ec, 0x00000000 },
3111 + { 0x000081f0, 0x00000000 },
3112 + { 0x000081f4, 0x00000000 },
3113 + { 0x000081f8, 0x00000000 },
3114 + { 0x000081fc, 0x00000000 },
3115 + { 0x00008200, 0x00000000 },
3116 + { 0x00008204, 0x00000000 },
3117 + { 0x00008208, 0x00000000 },
3118 + { 0x0000820c, 0x00000000 },
3119 + { 0x00008210, 0x00000000 },
3120 + { 0x00008214, 0x00000000 },
3121 + { 0x00008218, 0x00000000 },
3122 + { 0x0000821c, 0x00000000 },
3123 + { 0x00008220, 0x00000000 },
3124 + { 0x00008224, 0x00000000 },
3125 + { 0x00008228, 0x00000000 },
3126 + { 0x0000822c, 0x00000000 },
3127 + { 0x00008230, 0x00000000 },
3128 + { 0x00008234, 0x00000000 },
3129 + { 0x00008238, 0x00000000 },
3130 + { 0x0000823c, 0x00000000 },
3131 + { 0x00008240, 0x00100000 },
3132 + { 0x00008244, 0x0010f400 },
3133 + { 0x00008248, 0x00000100 },
3134 + { 0x0000824c, 0x0001e800 },
3135 + { 0x00008250, 0x00000000 },
3136 + { 0x00008254, 0x00000000 },
3137 + { 0x00008258, 0x00000000 },
3138 + { 0x0000825c, 0x400000ff },
3139 + { 0x00008260, 0x00080922 },
3140 + { 0x00008270, 0x00000000 },
3141 + { 0x00008274, 0x40000000 },
3142 + { 0x00008278, 0x003e4180 },
3143 + { 0x0000827c, 0x00000000 },
3144 + { 0x00008284, 0x0000002c },
3145 + { 0x00008288, 0x0000002c },
3146 + { 0x0000828c, 0x00000000 },
3147 + { 0x00008294, 0x00000000 },
3148 + { 0x00008298, 0x00000000 },
3149 + { 0x00008300, 0x00000000 },
3150 + { 0x00008304, 0x00000000 },
3151 + { 0x00008308, 0x00000000 },
3152 + { 0x0000830c, 0x00000000 },
3153 + { 0x00008310, 0x00000000 },
3154 + { 0x00008314, 0x00000000 },
3155 + { 0x00008318, 0x00000000 },
3156 + { 0x00008328, 0x00000000 },
3157 + { 0x0000832c, 0x00000007 },
3158 + { 0x00008330, 0x00000302 },
3159 + { 0x00008334, 0x00000e00 },
3160 + { 0x00008338, 0x00ff0000 },
3161 + { 0x0000833c, 0x00000000 },
3162 + { 0x00008340, 0x000107ff },
3163 + { 0x00009808, 0x00000000 },
3164 + { 0x0000980c, 0xad848e19 },
3165 + { 0x00009810, 0x7d14e000 },
3166 + { 0x00009814, 0x9c0a9f6b },
3167 + { 0x0000981c, 0x00000000 },
3168 + { 0x0000982c, 0x0000a000 },
3169 + { 0x00009830, 0x00000000 },
3170 + { 0x0000983c, 0x00200400 },
3171 + { 0x00009840, 0x206a01ae },
3172 + { 0x0000984c, 0x1284233c },
3173 + { 0x00009854, 0x00000859 },
3174 + { 0x00009900, 0x00000000 },
3175 + { 0x00009904, 0x00000000 },
3176 + { 0x00009908, 0x00000000 },
3177 + { 0x0000990c, 0x00000000 },
3178 + { 0x0000991c, 0x10000fff },
3179 + { 0x00009920, 0x05100000 },
3180 + { 0x0000a920, 0x05100000 },
3181 + { 0x0000b920, 0x05100000 },
3182 + { 0x00009928, 0x00000001 },
3183 + { 0x0000992c, 0x00000004 },
3184 + { 0x00009934, 0x1e1f2022 },
3185 + { 0x00009938, 0x0a0b0c0d },
3186 + { 0x0000993c, 0x00000000 },
3187 + { 0x00009948, 0x9280b212 },
3188 + { 0x0000994c, 0x00020028 },
3189 + { 0x00009954, 0x5f3ca3de },
3190 + { 0x00009958, 0x2108ecff },
3191 + { 0x00009940, 0x00750604 },
3192 + { 0x0000c95c, 0x004b6a8e },
3193 + { 0x00009970, 0x190fb515 },
3194 + { 0x00009974, 0x00000000 },
3195 + { 0x00009978, 0x00000001 },
3196 + { 0x0000997c, 0x00000000 },
3197 + { 0x00009980, 0x00000000 },
3198 + { 0x00009984, 0x00000000 },
3199 + { 0x00009988, 0x00000000 },
3200 + { 0x0000998c, 0x00000000 },
3201 + { 0x00009990, 0x00000000 },
3202 + { 0x00009994, 0x00000000 },
3203 + { 0x00009998, 0x00000000 },
3204 + { 0x0000999c, 0x00000000 },
3205 + { 0x000099a0, 0x00000000 },
3206 + { 0x000099a4, 0x00000001 },
3207 + { 0x000099a8, 0x201fff00 },
3208 + { 0x000099ac, 0x006f0000 },
3209 + { 0x000099b0, 0x03051000 },
3210 + { 0x000099dc, 0x00000000 },
3211 + { 0x000099e0, 0x00000200 },
3212 + { 0x000099e4, 0xaaaaaaaa },
3213 + { 0x000099e8, 0x3c466478 },
3214 + { 0x000099ec, 0x0cc80caa },
3215 + { 0x000099fc, 0x00001042 },
3216 + { 0x00009b00, 0x00000000 },
3217 + { 0x00009b04, 0x00000001 },
3218 + { 0x00009b08, 0x00000002 },
3219 + { 0x00009b0c, 0x00000003 },
3220 + { 0x00009b10, 0x00000004 },
3221 + { 0x00009b14, 0x00000005 },
3222 + { 0x00009b18, 0x00000008 },
3223 + { 0x00009b1c, 0x00000009 },
3224 + { 0x00009b20, 0x0000000a },
3225 + { 0x00009b24, 0x0000000b },
3226 + { 0x00009b28, 0x0000000c },
3227 + { 0x00009b2c, 0x0000000d },
3228 + { 0x00009b30, 0x00000010 },
3229 + { 0x00009b34, 0x00000011 },
3230 + { 0x00009b38, 0x00000012 },
3231 + { 0x00009b3c, 0x00000013 },
3232 + { 0x00009b40, 0x00000014 },
3233 + { 0x00009b44, 0x00000015 },
3234 + { 0x00009b48, 0x00000018 },
3235 + { 0x00009b4c, 0x00000019 },
3236 + { 0x00009b50, 0x0000001a },
3237 + { 0x00009b54, 0x0000001b },
3238 + { 0x00009b58, 0x0000001c },
3239 + { 0x00009b5c, 0x0000001d },
3240 + { 0x00009b60, 0x00000020 },
3241 + { 0x00009b64, 0x00000021 },
3242 + { 0x00009b68, 0x00000022 },
3243 + { 0x00009b6c, 0x00000023 },
3244 + { 0x00009b70, 0x00000024 },
3245 + { 0x00009b74, 0x00000025 },
3246 + { 0x00009b78, 0x00000028 },
3247 + { 0x00009b7c, 0x00000029 },
3248 + { 0x00009b80, 0x0000002a },
3249 + { 0x00009b84, 0x0000002b },
3250 + { 0x00009b88, 0x0000002c },
3251 + { 0x00009b8c, 0x0000002d },
3252 + { 0x00009b90, 0x00000030 },
3253 + { 0x00009b94, 0x00000031 },
3254 + { 0x00009b98, 0x00000032 },
3255 + { 0x00009b9c, 0x00000033 },
3256 + { 0x00009ba0, 0x00000034 },
3257 + { 0x00009ba4, 0x00000035 },
3258 + { 0x00009ba8, 0x00000035 },
3259 + { 0x00009bac, 0x00000035 },
3260 + { 0x00009bb0, 0x00000035 },
3261 + { 0x00009bb4, 0x00000035 },
3262 + { 0x00009bb8, 0x00000035 },
3263 + { 0x00009bbc, 0x00000035 },
3264 + { 0x00009bc0, 0x00000035 },
3265 + { 0x00009bc4, 0x00000035 },
3266 + { 0x00009bc8, 0x00000035 },
3267 + { 0x00009bcc, 0x00000035 },
3268 + { 0x00009bd0, 0x00000035 },
3269 + { 0x00009bd4, 0x00000035 },
3270 + { 0x00009bd8, 0x00000035 },
3271 + { 0x00009bdc, 0x00000035 },
3272 + { 0x00009be0, 0x00000035 },
3273 + { 0x00009be4, 0x00000035 },
3274 + { 0x00009be8, 0x00000035 },
3275 + { 0x00009bec, 0x00000035 },
3276 + { 0x00009bf0, 0x00000035 },
3277 + { 0x00009bf4, 0x00000035 },
3278 + { 0x00009bf8, 0x00000010 },
3279 + { 0x00009bfc, 0x0000001a },
3280 + { 0x0000a210, 0x40806333 },
3281 + { 0x0000a214, 0x00106c10 },
3282 + { 0x0000a218, 0x009c4060 },
3283 + { 0x0000a220, 0x018830c6 },
3284 + { 0x0000a224, 0x00000400 },
3285 + { 0x0000a228, 0x001a0bb5 },
3286 + { 0x0000a22c, 0x00000000 },
3287 + { 0x0000a234, 0x20202020 },
3288 + { 0x0000a238, 0x20202020 },
3289 + { 0x0000a23c, 0x13c889af },
3290 + { 0x0000a240, 0x38490a20 },
3291 + { 0x0000a244, 0x00007bb6 },
3292 + { 0x0000a248, 0x0fff3ffc },
3293 + { 0x0000a24c, 0x00000001 },
3294 + { 0x0000a250, 0x0000e000 },
3295 + { 0x0000a254, 0x00000000 },
3296 + { 0x0000a258, 0x0cc75380 },
3297 + { 0x0000a25c, 0x0f0f0f01 },
3298 + { 0x0000a260, 0xdfa91f01 },
3299 + { 0x0000a268, 0x00000001 },
3300 + { 0x0000a26c, 0x0ebae9c6 },
3301 + { 0x0000b26c, 0x0ebae9c6 },
3302 + { 0x0000c26c, 0x0ebae9c6 },
3303 + { 0x0000d270, 0x00820820 },
3304 + { 0x0000a278, 0x1ce739ce },
3305 + { 0x0000a27c, 0x050701ce },
3306 + { 0x0000a338, 0x00000000 },
3307 + { 0x0000a33c, 0x00000000 },
3308 + { 0x0000a340, 0x00000000 },
3309 + { 0x0000a344, 0x00000000 },
3310 + { 0x0000a348, 0x3fffffff },
3311 + { 0x0000a34c, 0x3fffffff },
3312 + { 0x0000a350, 0x3fffffff },
3313 + { 0x0000a354, 0x0003ffff },
3314 + { 0x0000a358, 0x79bfaa03 },
3315 + { 0x0000d35c, 0x07ffffef },
3316 + { 0x0000d360, 0x0fffffe7 },
3317 + { 0x0000d364, 0x17ffffe5 },
3318 + { 0x0000d368, 0x1fffffe4 },
3319 + { 0x0000d36c, 0x37ffffe3 },
3320 + { 0x0000d370, 0x3fffffe3 },
3321 + { 0x0000d374, 0x57ffffe3 },
3322 + { 0x0000d378, 0x5fffffe2 },
3323 + { 0x0000d37c, 0x7fffffe2 },
3324 + { 0x0000d380, 0x7f3c7bba },
3325 + { 0x0000d384, 0xf3307ff0 },
3326 + { 0x0000a388, 0x0c000000 },
3327 + { 0x0000a38c, 0x20202020 },
3328 + { 0x0000a390, 0x20202020 },
3329 + { 0x0000a394, 0x1ce739ce },
3330 + { 0x0000a398, 0x000001ce },
3331 + { 0x0000a39c, 0x00000001 },
3332 + { 0x0000a3a0, 0x00000000 },
3333 + { 0x0000a3a4, 0x00000000 },
3334 + { 0x0000a3a8, 0x00000000 },
3335 + { 0x0000a3ac, 0x00000000 },
3336 + { 0x0000a3b0, 0x00000000 },
3337 + { 0x0000a3b4, 0x00000000 },
3338 + { 0x0000a3b8, 0x00000000 },
3339 + { 0x0000a3bc, 0x00000000 },
3340 + { 0x0000a3c0, 0x00000000 },
3341 + { 0x0000a3c4, 0x00000000 },
3342 + { 0x0000a3c8, 0x00000246 },
3343 + { 0x0000a3cc, 0x20202020 },
3344 + { 0x0000a3d0, 0x20202020 },
3345 + { 0x0000a3d4, 0x20202020 },
3346 + { 0x0000a3dc, 0x1ce739ce },
3347 + { 0x0000a3e0, 0x000001ce },
3348 +};
3349 +
3350 +static const u32 ar5416Bank0_9160[][2] = {
3351 + { 0x000098b0, 0x1e5795e5 },
3352 + { 0x000098e0, 0x02008020 },
3353 +};
3354 +
3355 +static const u32 ar5416BB_RfGain_9160[][3] = {
3356 + { 0x00009a00, 0x00000000, 0x00000000 },
3357 + { 0x00009a04, 0x00000040, 0x00000040 },
3358 + { 0x00009a08, 0x00000080, 0x00000080 },
3359 + { 0x00009a0c, 0x000001a1, 0x00000141 },
3360 + { 0x00009a10, 0x000001e1, 0x00000181 },
3361 + { 0x00009a14, 0x00000021, 0x000001c1 },
3362 + { 0x00009a18, 0x00000061, 0x00000001 },
3363 + { 0x00009a1c, 0x00000168, 0x00000041 },
3364 + { 0x00009a20, 0x000001a8, 0x000001a8 },
3365 + { 0x00009a24, 0x000001e8, 0x000001e8 },
3366 + { 0x00009a28, 0x00000028, 0x00000028 },
3367 + { 0x00009a2c, 0x00000068, 0x00000068 },
3368 + { 0x00009a30, 0x00000189, 0x000000a8 },
3369 + { 0x00009a34, 0x000001c9, 0x00000169 },
3370 + { 0x00009a38, 0x00000009, 0x000001a9 },
3371 + { 0x00009a3c, 0x00000049, 0x000001e9 },
3372 + { 0x00009a40, 0x00000089, 0x00000029 },
3373 + { 0x00009a44, 0x00000170, 0x00000069 },
3374 + { 0x00009a48, 0x000001b0, 0x00000190 },
3375 + { 0x00009a4c, 0x000001f0, 0x000001d0 },
3376 + { 0x00009a50, 0x00000030, 0x00000010 },
3377 + { 0x00009a54, 0x00000070, 0x00000050 },
3378 + { 0x00009a58, 0x00000191, 0x00000090 },
3379 + { 0x00009a5c, 0x000001d1, 0x00000151 },
3380 + { 0x00009a60, 0x00000011, 0x00000191 },
3381 + { 0x00009a64, 0x00000051, 0x000001d1 },
3382 + { 0x00009a68, 0x00000091, 0x00000011 },
3383 + { 0x00009a6c, 0x000001b8, 0x00000051 },
3384 + { 0x00009a70, 0x000001f8, 0x00000198 },
3385 + { 0x00009a74, 0x00000038, 0x000001d8 },
3386 + { 0x00009a78, 0x00000078, 0x00000018 },
3387 + { 0x00009a7c, 0x00000199, 0x00000058 },
3388 + { 0x00009a80, 0x000001d9, 0x00000098 },
3389 + { 0x00009a84, 0x00000019, 0x00000159 },
3390 + { 0x00009a88, 0x00000059, 0x00000199 },
3391 + { 0x00009a8c, 0x00000099, 0x000001d9 },
3392 + { 0x00009a90, 0x000000d9, 0x00000019 },
3393 + { 0x00009a94, 0x000000f9, 0x00000059 },
3394 + { 0x00009a98, 0x000000f9, 0x00000099 },
3395 + { 0x00009a9c, 0x000000f9, 0x000000d9 },
3396 + { 0x00009aa0, 0x000000f9, 0x000000f9 },
3397 + { 0x00009aa4, 0x000000f9, 0x000000f9 },
3398 + { 0x00009aa8, 0x000000f9, 0x000000f9 },
3399 + { 0x00009aac, 0x000000f9, 0x000000f9 },
3400 + { 0x00009ab0, 0x000000f9, 0x000000f9 },
3401 + { 0x00009ab4, 0x000000f9, 0x000000f9 },
3402 + { 0x00009ab8, 0x000000f9, 0x000000f9 },
3403 + { 0x00009abc, 0x000000f9, 0x000000f9 },
3404 + { 0x00009ac0, 0x000000f9, 0x000000f9 },
3405 + { 0x00009ac4, 0x000000f9, 0x000000f9 },
3406 + { 0x00009ac8, 0x000000f9, 0x000000f9 },
3407 + { 0x00009acc, 0x000000f9, 0x000000f9 },
3408 + { 0x00009ad0, 0x000000f9, 0x000000f9 },
3409 + { 0x00009ad4, 0x000000f9, 0x000000f9 },
3410 + { 0x00009ad8, 0x000000f9, 0x000000f9 },
3411 + { 0x00009adc, 0x000000f9, 0x000000f9 },
3412 + { 0x00009ae0, 0x000000f9, 0x000000f9 },
3413 + { 0x00009ae4, 0x000000f9, 0x000000f9 },
3414 + { 0x00009ae8, 0x000000f9, 0x000000f9 },
3415 + { 0x00009aec, 0x000000f9, 0x000000f9 },
3416 + { 0x00009af0, 0x000000f9, 0x000000f9 },
3417 + { 0x00009af4, 0x000000f9, 0x000000f9 },
3418 + { 0x00009af8, 0x000000f9, 0x000000f9 },
3419 + { 0x00009afc, 0x000000f9, 0x000000f9 },
3420 +};
3421 +
3422 +static const u32 ar5416Bank1_9160[][2] = {
3423 + { 0x000098b0, 0x02108421 },
3424 + { 0x000098ec, 0x00000008 },
3425 +};
3426 +
3427 +static const u32 ar5416Bank2_9160[][2] = {
3428 + { 0x000098b0, 0x0e73ff17 },
3429 + { 0x000098e0, 0x00000420 },
3430 +};
3431 +
3432 +static const u32 ar5416Bank3_9160[][3] = {
3433 + { 0x000098f0, 0x01400018, 0x01c00018 },
3434 +};
3435 +
3436 +static const u32 ar5416Bank6_9160[][3] = {
3437 + { 0x0000989c, 0x00000000, 0x00000000 },
3438 + { 0x0000989c, 0x00000000, 0x00000000 },
3439 + { 0x0000989c, 0x00000000, 0x00000000 },
3440 + { 0x0000989c, 0x00e00000, 0x00e00000 },
3441 + { 0x0000989c, 0x005e0000, 0x005e0000 },
3442 + { 0x0000989c, 0x00120000, 0x00120000 },
3443 + { 0x0000989c, 0x00620000, 0x00620000 },
3444 + { 0x0000989c, 0x00020000, 0x00020000 },
3445 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3446 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3447 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3448 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
3449 + { 0x0000989c, 0x005f0000, 0x005f0000 },
3450 + { 0x0000989c, 0x00870000, 0x00870000 },
3451 + { 0x0000989c, 0x00f90000, 0x00f90000 },
3452 + { 0x0000989c, 0x007b0000, 0x007b0000 },
3453 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3454 + { 0x0000989c, 0x00f50000, 0x00f50000 },
3455 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
3456 + { 0x0000989c, 0x00110000, 0x00110000 },
3457 + { 0x0000989c, 0x006100a8, 0x006100a8 },
3458 + { 0x0000989c, 0x004210a2, 0x004210a2 },
3459 + { 0x0000989c, 0x0014008f, 0x0014008f },
3460 + { 0x0000989c, 0x00c40003, 0x00c40003 },
3461 + { 0x0000989c, 0x003000f2, 0x003000f2 },
3462 + { 0x0000989c, 0x00440016, 0x00440016 },
3463 + { 0x0000989c, 0x00410040, 0x00410040 },
3464 + { 0x0000989c, 0x0001805e, 0x0001805e },
3465 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
3466 + { 0x0000989c, 0x000000f1, 0x000000f1 },
3467 + { 0x0000989c, 0x00002081, 0x00002081 },
3468 + { 0x0000989c, 0x000000d4, 0x000000d4 },
3469 + { 0x000098d0, 0x0000000f, 0x0010000f },
3470 +};
3471 +
3472 +static const u32 ar5416Bank6TPC_9160[][3] = {
3473 + { 0x0000989c, 0x00000000, 0x00000000 },
3474 + { 0x0000989c, 0x00000000, 0x00000000 },
3475 + { 0x0000989c, 0x00000000, 0x00000000 },
3476 + { 0x0000989c, 0x00e00000, 0x00e00000 },
3477 + { 0x0000989c, 0x005e0000, 0x005e0000 },
3478 + { 0x0000989c, 0x00120000, 0x00120000 },
3479 + { 0x0000989c, 0x00620000, 0x00620000 },
3480 + { 0x0000989c, 0x00020000, 0x00020000 },
3481 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3482 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3483 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3484 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
3485 + { 0x0000989c, 0x005f0000, 0x005f0000 },
3486 + { 0x0000989c, 0x00870000, 0x00870000 },
3487 + { 0x0000989c, 0x00f90000, 0x00f90000 },
3488 + { 0x0000989c, 0x007b0000, 0x007b0000 },
3489 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3490 + { 0x0000989c, 0x00f50000, 0x00f50000 },
3491 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
3492 + { 0x0000989c, 0x00110000, 0x00110000 },
3493 + { 0x0000989c, 0x006100a8, 0x006100a8 },
3494 + { 0x0000989c, 0x00423022, 0x00423022 },
3495 + { 0x0000989c, 0x2014008f, 0x2014008f },
3496 + { 0x0000989c, 0x00c40002, 0x00c40002 },
3497 + { 0x0000989c, 0x003000f2, 0x003000f2 },
3498 + { 0x0000989c, 0x00440016, 0x00440016 },
3499 + { 0x0000989c, 0x00410040, 0x00410040 },
3500 + { 0x0000989c, 0x0001805e, 0x0001805e },
3501 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
3502 + { 0x0000989c, 0x000000e1, 0x000000e1 },
3503 + { 0x0000989c, 0x00007080, 0x00007080 },
3504 + { 0x0000989c, 0x000000d4, 0x000000d4 },
3505 + { 0x000098d0, 0x0000000f, 0x0010000f },
3506 +};
3507 +
3508 +static const u32 ar5416Bank7_9160[][2] = {
3509 + { 0x0000989c, 0x00000500 },
3510 + { 0x0000989c, 0x00000800 },
3511 + { 0x000098cc, 0x0000000e },
3512 +};
3513 +
3514 +static u32 ar5416Addac_9160[][2] = {
3515 + {0x0000989c, 0x00000000 },
3516 + {0x0000989c, 0x00000000 },
3517 + {0x0000989c, 0x00000000 },
3518 + {0x0000989c, 0x00000000 },
3519 + {0x0000989c, 0x00000000 },
3520 + {0x0000989c, 0x00000000 },
3521 + {0x0000989c, 0x000000c0 },
3522 + {0x0000989c, 0x00000018 },
3523 + {0x0000989c, 0x00000004 },
3524 + {0x0000989c, 0x00000000 },
3525 + {0x0000989c, 0x00000000 },
3526 + {0x0000989c, 0x00000000 },
3527 + {0x0000989c, 0x00000000 },
3528 + {0x0000989c, 0x00000000 },
3529 + {0x0000989c, 0x00000000 },
3530 + {0x0000989c, 0x00000000 },
3531 + {0x0000989c, 0x00000000 },
3532 + {0x0000989c, 0x00000000 },
3533 + {0x0000989c, 0x00000000 },
3534 + {0x0000989c, 0x00000000 },
3535 + {0x0000989c, 0x00000000 },
3536 + {0x0000989c, 0x000000c0 },
3537 + {0x0000989c, 0x00000019 },
3538 + {0x0000989c, 0x00000004 },
3539 + {0x0000989c, 0x00000000 },
3540 + {0x0000989c, 0x00000000 },
3541 + {0x0000989c, 0x00000000 },
3542 + {0x0000989c, 0x00000004 },
3543 + {0x0000989c, 0x00000003 },
3544 + {0x0000989c, 0x00000008 },
3545 + {0x0000989c, 0x00000000 },
3546 + {0x000098cc, 0x00000000 },
3547 +};
3548 +
3549 +static u32 ar5416Addac_91601_1[][2] = {
3550 + {0x0000989c, 0x00000000 },
3551 + {0x0000989c, 0x00000000 },
3552 + {0x0000989c, 0x00000000 },
3553 + {0x0000989c, 0x00000000 },
3554 + {0x0000989c, 0x00000000 },
3555 + {0x0000989c, 0x00000000 },
3556 + {0x0000989c, 0x000000c0 },
3557 + {0x0000989c, 0x00000018 },
3558 + {0x0000989c, 0x00000004 },
3559 + {0x0000989c, 0x00000000 },
3560 + {0x0000989c, 0x00000000 },
3561 + {0x0000989c, 0x00000000 },
3562 + {0x0000989c, 0x00000000 },
3563 + {0x0000989c, 0x00000000 },
3564 + {0x0000989c, 0x00000000 },
3565 + {0x0000989c, 0x00000000 },
3566 + {0x0000989c, 0x00000000 },
3567 + {0x0000989c, 0x00000000 },
3568 + {0x0000989c, 0x00000000 },
3569 + {0x0000989c, 0x00000000 },
3570 + {0x0000989c, 0x00000000 },
3571 + {0x0000989c, 0x000000c0 },
3572 + {0x0000989c, 0x00000019 },
3573 + {0x0000989c, 0x00000004 },
3574 + {0x0000989c, 0x00000000 },
3575 + {0x0000989c, 0x00000000 },
3576 + {0x0000989c, 0x00000000 },
3577 + {0x0000989c, 0x00000000 },
3578 + {0x0000989c, 0x00000000 },
3579 + {0x0000989c, 0x00000000 },
3580 + {0x0000989c, 0x00000000 },
3581 + {0x000098cc, 0x00000000 },
3582 +};
3583 +
3584 --- /dev/null
3585 +++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
3586 @@ -0,0 +1,988 @@
3587 +/*
3588 + * Copyright (c) 2008-2010 Atheros Communications Inc.
3589 + *
3590 + * Permission to use, copy, modify, and/or distribute this software for any
3591 + * purpose with or without fee is hereby granted, provided that the above
3592 + * copyright notice and this permission notice appear in all copies.
3593 + *
3594 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
3595 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
3596 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
3597 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
3598 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
3599 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
3600 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
3601 + */
3602 +
3603 +#include "hw.h"
3604 +#include "hw-ops.h"
3605 +#include "ar9002_phy.h"
3606 +
3607 +#define AR9285_CLCAL_REDO_THRESH 1
3608 +
3609 +static void ar9002_hw_setup_calibration(struct ath_hw *ah,
3610 + struct ath9k_cal_list *currCal)
3611 +{
3612 + struct ath_common *common = ath9k_hw_common(ah);
3613 +
3614 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
3615 + AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
3616 + currCal->calData->calCountMax);
3617 +
3618 + switch (currCal->calData->calType) {
3619 + case IQ_MISMATCH_CAL:
3620 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
3621 + ath_print(common, ATH_DBG_CALIBRATE,
3622 + "starting IQ Mismatch Calibration\n");
3623 + break;
3624 + case ADC_GAIN_CAL:
3625 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
3626 + ath_print(common, ATH_DBG_CALIBRATE,
3627 + "starting ADC Gain Calibration\n");
3628 + break;
3629 + case ADC_DC_CAL:
3630 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
3631 + ath_print(common, ATH_DBG_CALIBRATE,
3632 + "starting ADC DC Calibration\n");
3633 + break;
3634 + case ADC_DC_INIT_CAL:
3635 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
3636 + ath_print(common, ATH_DBG_CALIBRATE,
3637 + "starting Init ADC DC Calibration\n");
3638 + break;
3639 + case TEMP_COMP_CAL:
3640 + break; /* Not supported */
3641 + }
3642 +
3643 + REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
3644 + AR_PHY_TIMING_CTRL4_DO_CAL);
3645 +}
3646 +
3647 +static bool ar9002_hw_per_calibration(struct ath_hw *ah,
3648 + struct ath9k_channel *ichan,
3649 + u8 rxchainmask,
3650 + struct ath9k_cal_list *currCal)
3651 +{
3652 + bool iscaldone = false;
3653 +
3654 + if (currCal->calState == CAL_RUNNING) {
3655 + if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
3656 + AR_PHY_TIMING_CTRL4_DO_CAL)) {
3657 +
3658 + currCal->calData->calCollect(ah);
3659 + ah->cal_samples++;
3660 +
3661 + if (ah->cal_samples >= currCal->calData->calNumSamples) {
3662 + int i, numChains = 0;
3663 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3664 + if (rxchainmask & (1 << i))
3665 + numChains++;
3666 + }
3667 +
3668 + currCal->calData->calPostProc(ah, numChains);
3669 + ichan->CalValid |= currCal->calData->calType;
3670 + currCal->calState = CAL_DONE;
3671 + iscaldone = true;
3672 + } else {
3673 + ar9002_hw_setup_calibration(ah, currCal);
3674 + }
3675 + }
3676 + } else if (!(ichan->CalValid & currCal->calData->calType)) {
3677 + ath9k_hw_reset_calibration(ah, currCal);
3678 + }
3679 +
3680 + return iscaldone;
3681 +}
3682 +
3683 +/* Assumes you are talking about the currently configured channel */
3684 +static bool ar9002_hw_iscal_supported(struct ath_hw *ah,
3685 + enum ath9k_cal_types calType)
3686 +{
3687 + struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3688 +
3689 + switch (calType & ah->supp_cals) {
3690 + case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
3691 + return true;
3692 + case ADC_GAIN_CAL:
3693 + case ADC_DC_CAL:
3694 + if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
3695 + conf_is_ht20(conf)))
3696 + return true;
3697 + break;
3698 + }
3699 + return false;
3700 +}
3701 +
3702 +static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
3703 +{
3704 + int i;
3705 +
3706 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3707 + ah->totalPowerMeasI[i] +=
3708 + REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3709 + ah->totalPowerMeasQ[i] +=
3710 + REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3711 + ah->totalIqCorrMeas[i] +=
3712 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3713 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3714 + "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
3715 + ah->cal_samples, i, ah->totalPowerMeasI[i],
3716 + ah->totalPowerMeasQ[i],
3717 + ah->totalIqCorrMeas[i]);
3718 + }
3719 +}
3720 +
3721 +static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
3722 +{
3723 + int i;
3724 +
3725 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3726 + ah->totalAdcIOddPhase[i] +=
3727 + REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3728 + ah->totalAdcIEvenPhase[i] +=
3729 + REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3730 + ah->totalAdcQOddPhase[i] +=
3731 + REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3732 + ah->totalAdcQEvenPhase[i] +=
3733 + REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
3734 +
3735 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3736 + "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
3737 + "oddq=0x%08x; evenq=0x%08x;\n",
3738 + ah->cal_samples, i,
3739 + ah->totalAdcIOddPhase[i],
3740 + ah->totalAdcIEvenPhase[i],
3741 + ah->totalAdcQOddPhase[i],
3742 + ah->totalAdcQEvenPhase[i]);
3743 + }
3744 +}
3745 +
3746 +static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
3747 +{
3748 + int i;
3749 +
3750 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3751 + ah->totalAdcDcOffsetIOddPhase[i] +=
3752 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3753 + ah->totalAdcDcOffsetIEvenPhase[i] +=
3754 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3755 + ah->totalAdcDcOffsetQOddPhase[i] +=
3756 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3757 + ah->totalAdcDcOffsetQEvenPhase[i] +=
3758 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
3759 +
3760 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3761 + "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
3762 + "oddq=0x%08x; evenq=0x%08x;\n",
3763 + ah->cal_samples, i,
3764 + ah->totalAdcDcOffsetIOddPhase[i],
3765 + ah->totalAdcDcOffsetIEvenPhase[i],
3766 + ah->totalAdcDcOffsetQOddPhase[i],
3767 + ah->totalAdcDcOffsetQEvenPhase[i]);
3768 + }
3769 +}
3770 +
3771 +static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
3772 +{
3773 + struct ath_common *common = ath9k_hw_common(ah);
3774 + u32 powerMeasQ, powerMeasI, iqCorrMeas;
3775 + u32 qCoffDenom, iCoffDenom;
3776 + int32_t qCoff, iCoff;
3777 + int iqCorrNeg, i;
3778 +
3779 + for (i = 0; i < numChains; i++) {
3780 + powerMeasI = ah->totalPowerMeasI[i];
3781 + powerMeasQ = ah->totalPowerMeasQ[i];
3782 + iqCorrMeas = ah->totalIqCorrMeas[i];
3783 +
3784 + ath_print(common, ATH_DBG_CALIBRATE,
3785 + "Starting IQ Cal and Correction for Chain %d\n",
3786 + i);
3787 +
3788 + ath_print(common, ATH_DBG_CALIBRATE,
3789 + "Orignal: Chn %diq_corr_meas = 0x%08x\n",
3790 + i, ah->totalIqCorrMeas[i]);
3791 +
3792 + iqCorrNeg = 0;
3793 +
3794 + if (iqCorrMeas > 0x80000000) {
3795 + iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
3796 + iqCorrNeg = 1;
3797 + }
3798 +
3799 + ath_print(common, ATH_DBG_CALIBRATE,
3800 + "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
3801 + ath_print(common, ATH_DBG_CALIBRATE,
3802 + "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
3803 + ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
3804 + iqCorrNeg);
3805 +
3806 + iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
3807 + qCoffDenom = powerMeasQ / 64;
3808 +
3809 + if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
3810 + (qCoffDenom != 0)) {
3811 + iCoff = iqCorrMeas / iCoffDenom;
3812 + qCoff = powerMeasI / qCoffDenom - 64;
3813 + ath_print(common, ATH_DBG_CALIBRATE,
3814 + "Chn %d iCoff = 0x%08x\n", i, iCoff);
3815 + ath_print(common, ATH_DBG_CALIBRATE,
3816 + "Chn %d qCoff = 0x%08x\n", i, qCoff);
3817 +
3818 + iCoff = iCoff & 0x3f;
3819 + ath_print(common, ATH_DBG_CALIBRATE,
3820 + "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
3821 + if (iqCorrNeg == 0x0)
3822 + iCoff = 0x40 - iCoff;
3823 +
3824 + if (qCoff > 15)
3825 + qCoff = 15;
3826 + else if (qCoff <= -16)
3827 + qCoff = 16;
3828 +
3829 + ath_print(common, ATH_DBG_CALIBRATE,
3830 + "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
3831 + i, iCoff, qCoff);
3832 +
3833 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
3834 + AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
3835 + iCoff);
3836 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
3837 + AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
3838 + qCoff);
3839 + ath_print(common, ATH_DBG_CALIBRATE,
3840 + "IQ Cal and Correction done for Chain %d\n",
3841 + i);
3842 + }
3843 + }
3844 +
3845 + REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
3846 + AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
3847 +}
3848 +
3849 +static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
3850 +{
3851 + struct ath_common *common = ath9k_hw_common(ah);
3852 + u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
3853 + u32 qGainMismatch, iGainMismatch, val, i;
3854 +
3855 + for (i = 0; i < numChains; i++) {
3856 + iOddMeasOffset = ah->totalAdcIOddPhase[i];
3857 + iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
3858 + qOddMeasOffset = ah->totalAdcQOddPhase[i];
3859 + qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
3860 +
3861 + ath_print(common, ATH_DBG_CALIBRATE,
3862 + "Starting ADC Gain Cal for Chain %d\n", i);
3863 +
3864 + ath_print(common, ATH_DBG_CALIBRATE,
3865 + "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
3866 + iOddMeasOffset);
3867 + ath_print(common, ATH_DBG_CALIBRATE,
3868 + "Chn %d pwr_meas_even_i = 0x%08x\n", i,
3869 + iEvenMeasOffset);
3870 + ath_print(common, ATH_DBG_CALIBRATE,
3871 + "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
3872 + qOddMeasOffset);
3873 + ath_print(common, ATH_DBG_CALIBRATE,
3874 + "Chn %d pwr_meas_even_q = 0x%08x\n", i,
3875 + qEvenMeasOffset);
3876 +
3877 + if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
3878 + iGainMismatch =
3879 + ((iEvenMeasOffset * 32) /
3880 + iOddMeasOffset) & 0x3f;
3881 + qGainMismatch =
3882 + ((qOddMeasOffset * 32) /
3883 + qEvenMeasOffset) & 0x3f;
3884 +
3885 + ath_print(common, ATH_DBG_CALIBRATE,
3886 + "Chn %d gain_mismatch_i = 0x%08x\n", i,
3887 + iGainMismatch);
3888 + ath_print(common, ATH_DBG_CALIBRATE,
3889 + "Chn %d gain_mismatch_q = 0x%08x\n", i,
3890 + qGainMismatch);
3891 +
3892 + val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
3893 + val &= 0xfffff000;
3894 + val |= (qGainMismatch) | (iGainMismatch << 6);
3895 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
3896 +
3897 + ath_print(common, ATH_DBG_CALIBRATE,
3898 + "ADC Gain Cal done for Chain %d\n", i);
3899 + }
3900 + }
3901 +
3902 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
3903 + REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
3904 + AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
3905 +}
3906 +
3907 +static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
3908 +{
3909 + struct ath_common *common = ath9k_hw_common(ah);
3910 + u32 iOddMeasOffset, iEvenMeasOffset, val, i;
3911 + int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
3912 + const struct ath9k_percal_data *calData =
3913 + ah->cal_list_curr->calData;
3914 + u32 numSamples =
3915 + (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
3916 +
3917 + for (i = 0; i < numChains; i++) {
3918 + iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
3919 + iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
3920 + qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
3921 + qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
3922 +
3923 + ath_print(common, ATH_DBG_CALIBRATE,
3924 + "Starting ADC DC Offset Cal for Chain %d\n", i);
3925 +
3926 + ath_print(common, ATH_DBG_CALIBRATE,
3927 + "Chn %d pwr_meas_odd_i = %d\n", i,
3928 + iOddMeasOffset);
3929 + ath_print(common, ATH_DBG_CALIBRATE,
3930 + "Chn %d pwr_meas_even_i = %d\n", i,
3931 + iEvenMeasOffset);
3932 + ath_print(common, ATH_DBG_CALIBRATE,
3933 + "Chn %d pwr_meas_odd_q = %d\n", i,
3934 + qOddMeasOffset);
3935 + ath_print(common, ATH_DBG_CALIBRATE,
3936 + "Chn %d pwr_meas_even_q = %d\n", i,
3937 + qEvenMeasOffset);
3938 +
3939 + iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
3940 + numSamples) & 0x1ff;
3941 + qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
3942 + numSamples) & 0x1ff;
3943 +
3944 + ath_print(common, ATH_DBG_CALIBRATE,
3945 + "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
3946 + iDcMismatch);
3947 + ath_print(common, ATH_DBG_CALIBRATE,
3948 + "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
3949 + qDcMismatch);
3950 +
3951 + val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
3952 + val &= 0xc0000fff;
3953 + val |= (qDcMismatch << 12) | (iDcMismatch << 21);
3954 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
3955 +
3956 + ath_print(common, ATH_DBG_CALIBRATE,
3957 + "ADC DC Offset Cal done for Chain %d\n", i);
3958 + }
3959 +
3960 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
3961 + REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
3962 + AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
3963 +}
3964 +
3965 +static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
3966 +{
3967 + u32 rddata;
3968 + int32_t delta, currPDADC, slope;
3969 +
3970 + rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
3971 + currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
3972 +
3973 + if (ah->initPDADC == 0 || currPDADC == 0) {
3974 + /*
3975 + * Zero value indicates that no frames have been transmitted yet,
3976 + * can't do temperature compensation until frames are transmitted.
3977 + */
3978 + return;
3979 + } else {
3980 + slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
3981 +
3982 + if (slope == 0) { /* to avoid divide by zero case */
3983 + delta = 0;
3984 + } else {
3985 + delta = ((currPDADC - ah->initPDADC)*4) / slope;
3986 + }
3987 + REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
3988 + AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
3989 + REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
3990 + AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
3991 + }
3992 +}
3993 +
3994 +static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah)
3995 +{
3996 + u32 rddata, i;
3997 + int delta, currPDADC, regval;
3998 +
3999 + rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
4000 + currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
4001 +
4002 + if (ah->initPDADC == 0 || currPDADC == 0)
4003 + return;
4004 +
4005 + if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
4006 + delta = (currPDADC - ah->initPDADC + 4) / 8;
4007 + else
4008 + delta = (currPDADC - ah->initPDADC + 5) / 10;
4009 +
4010 + if (delta != ah->PDADCdelta) {
4011 + ah->PDADCdelta = delta;
4012 + for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
4013 + regval = ah->originalGain[i] - delta;
4014 + if (regval < 0)
4015 + regval = 0;
4016 +
4017 + REG_RMW_FIELD(ah,
4018 + AR_PHY_TX_GAIN_TBL1 + i * 4,
4019 + AR_PHY_TX_GAIN, regval);
4020 + }
4021 + }
4022 +}
4023 +
4024 +static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
4025 +{
4026 + u32 regVal;
4027 + unsigned int i;
4028 + u32 regList [][2] = {
4029 + { 0x786c, 0 },
4030 + { 0x7854, 0 },
4031 + { 0x7820, 0 },
4032 + { 0x7824, 0 },
4033 + { 0x7868, 0 },
4034 + { 0x783c, 0 },
4035 + { 0x7838, 0 } ,
4036 + { 0x7828, 0 } ,
4037 + };
4038 +
4039 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4040 + regList[i][1] = REG_READ(ah, regList[i][0]);
4041 +
4042 + regVal = REG_READ(ah, 0x7834);
4043 + regVal &= (~(0x1));
4044 + REG_WRITE(ah, 0x7834, regVal);
4045 + regVal = REG_READ(ah, 0x9808);
4046 + regVal |= (0x1 << 27);
4047 + REG_WRITE(ah, 0x9808, regVal);
4048 +
4049 + /* 786c,b23,1, pwddac=1 */
4050 + REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
4051 + /* 7854, b5,1, pdrxtxbb=1 */
4052 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
4053 + /* 7854, b7,1, pdv2i=1 */
4054 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
4055 + /* 7854, b8,1, pddacinterface=1 */
4056 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
4057 + /* 7824,b12,0, offcal=0 */
4058 + REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
4059 + /* 7838, b1,0, pwddb=0 */
4060 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
4061 + /* 7820,b11,0, enpacal=0 */
4062 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
4063 + /* 7820,b25,1, pdpadrv1=0 */
4064 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
4065 + /* 7820,b24,0, pdpadrv2=0 */
4066 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0);
4067 + /* 7820,b23,0, pdpaout=0 */
4068 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
4069 + /* 783c,b14-16,7, padrvgn2tab_0=7 */
4070 + REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
4071 + /*
4072 + * 7838,b29-31,0, padrvgn1tab_0=0
4073 + * does not matter since we turn it off
4074 + */
4075 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
4076 +
4077 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
4078 +
4079 + /* Set:
4080 + * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
4081 + * txon=1,paon=1,oscon=1,synthon_force=1
4082 + */
4083 + REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
4084 + udelay(30);
4085 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
4086 +
4087 + /* find off_6_1; */
4088 + for (i = 6; i > 0; i--) {
4089 + regVal = REG_READ(ah, 0x7834);
4090 + regVal |= (1 << (20 + i));
4091 + REG_WRITE(ah, 0x7834, regVal);
4092 + udelay(1);
4093 + //regVal = REG_READ(ah, 0x7834);
4094 + regVal &= (~(0x1 << (20 + i)));
4095 + regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
4096 + << (20 + i));
4097 + REG_WRITE(ah, 0x7834, regVal);
4098 + }
4099 +
4100 + regVal = (regVal >>20) & 0x7f;
4101 +
4102 + /* Update PA cal info */
4103 + if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
4104 + if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
4105 + ah->pacal_info.max_skipcount =
4106 + 2 * ah->pacal_info.max_skipcount;
4107 + ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
4108 + } else {
4109 + ah->pacal_info.max_skipcount = 1;
4110 + ah->pacal_info.skipcount = 0;
4111 + ah->pacal_info.prev_offset = regVal;
4112 + }
4113 +
4114 + regVal = REG_READ(ah, 0x7834);
4115 + regVal |= 0x1;
4116 + REG_WRITE(ah, 0x7834, regVal);
4117 + regVal = REG_READ(ah, 0x9808);
4118 + regVal &= (~(0x1 << 27));
4119 + REG_WRITE(ah, 0x9808, regVal);
4120 +
4121 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4122 + REG_WRITE(ah, regList[i][0], regList[i][1]);
4123 +}
4124 +
4125 +static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
4126 +{
4127 + struct ath_common *common = ath9k_hw_common(ah);
4128 + u32 regVal;
4129 + int i, offset, offs_6_1, offs_0;
4130 + u32 ccomp_org, reg_field;
4131 + u32 regList[][2] = {
4132 + { 0x786c, 0 },
4133 + { 0x7854, 0 },
4134 + { 0x7820, 0 },
4135 + { 0x7824, 0 },
4136 + { 0x7868, 0 },
4137 + { 0x783c, 0 },
4138 + { 0x7838, 0 },
4139 + };
4140 +
4141 + ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
4142 +
4143 + /* PA CAL is not needed for high power solution */
4144 + if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
4145 + AR5416_EEP_TXGAIN_HIGH_POWER)
4146 + return;
4147 +
4148 + if (AR_SREV_9285_11(ah)) {
4149 + REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
4150 + udelay(10);
4151 + }
4152 +
4153 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4154 + regList[i][1] = REG_READ(ah, regList[i][0]);
4155 +
4156 + regVal = REG_READ(ah, 0x7834);
4157 + regVal &= (~(0x1));
4158 + REG_WRITE(ah, 0x7834, regVal);
4159 + regVal = REG_READ(ah, 0x9808);
4160 + regVal |= (0x1 << 27);
4161 + REG_WRITE(ah, 0x9808, regVal);
4162 +
4163 + REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
4164 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
4165 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
4166 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
4167 + REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
4168 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
4169 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
4170 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
4171 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
4172 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
4173 + REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
4174 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
4175 + ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
4176 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
4177 +
4178 + REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
4179 + udelay(30);
4180 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
4181 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
4182 +
4183 + for (i = 6; i > 0; i--) {
4184 + regVal = REG_READ(ah, 0x7834);
4185 + regVal |= (1 << (19 + i));
4186 + REG_WRITE(ah, 0x7834, regVal);
4187 + udelay(1);
4188 + regVal = REG_READ(ah, 0x7834);
4189 + regVal &= (~(0x1 << (19 + i)));
4190 + reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
4191 + regVal |= (reg_field << (19 + i));
4192 + REG_WRITE(ah, 0x7834, regVal);
4193 + }
4194 +
4195 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
4196 + udelay(1);
4197 + reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
4198 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
4199 + offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
4200 + offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
4201 +
4202 + offset = (offs_6_1<<1) | offs_0;
4203 + offset = offset - 0;
4204 + offs_6_1 = offset>>1;
4205 + offs_0 = offset & 1;
4206 +
4207 + if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
4208 + if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
4209 + ah->pacal_info.max_skipcount =
4210 + 2 * ah->pacal_info.max_skipcount;
4211 + ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
4212 + } else {
4213 + ah->pacal_info.max_skipcount = 1;
4214 + ah->pacal_info.skipcount = 0;
4215 + ah->pacal_info.prev_offset = offset;
4216 + }
4217 +
4218 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
4219 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
4220 +
4221 + regVal = REG_READ(ah, 0x7834);
4222 + regVal |= 0x1;
4223 + REG_WRITE(ah, 0x7834, regVal);
4224 + regVal = REG_READ(ah, 0x9808);
4225 + regVal &= (~(0x1 << 27));
4226 + REG_WRITE(ah, 0x9808, regVal);
4227 +
4228 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4229 + REG_WRITE(ah, regList[i][0], regList[i][1]);
4230 +
4231 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
4232 +
4233 + if (AR_SREV_9285_11(ah))
4234 + REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
4235 +
4236 +}
4237 +
4238 +static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
4239 +{
4240 + if (AR_SREV_9271(ah)) {
4241 + if (is_reset || !ah->pacal_info.skipcount)
4242 + ar9271_hw_pa_cal(ah, is_reset);
4243 + else
4244 + ah->pacal_info.skipcount--;
4245 + } else if (AR_SREV_9285_11_OR_LATER(ah)) {
4246 + if (is_reset || !ah->pacal_info.skipcount)
4247 + ar9285_hw_pa_cal(ah, is_reset);
4248 + else
4249 + ah->pacal_info.skipcount--;
4250 + }
4251 +}
4252 +
4253 +static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
4254 +{
4255 + if (OLC_FOR_AR9287_10_LATER)
4256 + ar9287_hw_olc_temp_compensation(ah);
4257 + else if (OLC_FOR_AR9280_20_LATER)
4258 + ar9280_hw_olc_temp_compensation(ah);
4259 +}
4260 +
4261 +static bool ar9002_hw_calibrate(struct ath_hw *ah,
4262 + struct ath9k_channel *chan,
4263 + u8 rxchainmask,
4264 + bool longcal)
4265 +{
4266 + bool iscaldone = true;
4267 + struct ath9k_cal_list *currCal = ah->cal_list_curr;
4268 +
4269 + if (currCal &&
4270 + (currCal->calState == CAL_RUNNING ||
4271 + currCal->calState == CAL_WAITING)) {
4272 + iscaldone = ar9002_hw_per_calibration(ah, chan,
4273 + rxchainmask, currCal);
4274 + if (iscaldone) {
4275 + ah->cal_list_curr = currCal = currCal->calNext;
4276 +
4277 + if (currCal->calState == CAL_WAITING) {
4278 + iscaldone = false;
4279 + ath9k_hw_reset_calibration(ah, currCal);
4280 + }
4281 + }
4282 + }
4283 +
4284 + /* Do NF cal only at longer intervals */
4285 + if (longcal) {
4286 + /* Do periodic PAOffset Cal */
4287 + ar9002_hw_pa_cal(ah, false);
4288 + ar9002_hw_olc_temp_compensation(ah);
4289 +
4290 + /* Get the value from the previous NF cal and update history buffer */
4291 + ath9k_hw_getnf(ah, chan);
4292 +
4293 + /*
4294 + * Load the NF from history buffer of the current channel.
4295 + * NF is slow time-variant, so it is OK to use a historical value.
4296 + */
4297 + ath9k_hw_loadnf(ah, ah->curchan);
4298 +
4299 + ath9k_hw_start_nfcal(ah);
4300 + }
4301 +
4302 + return iscaldone;
4303 +}
4304 +
4305 +/* Carrier leakage Calibration fix */
4306 +static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
4307 +{
4308 + struct ath_common *common = ath9k_hw_common(ah);
4309 +
4310 + REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
4311 + if (IS_CHAN_HT20(chan)) {
4312 + REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
4313 + REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
4314 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
4315 + AR_PHY_AGC_CONTROL_FLTR_CAL);
4316 + REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
4317 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
4318 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
4319 + AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
4320 + ath_print(common, ATH_DBG_CALIBRATE, "offset "
4321 + "calibration failed to complete in "
4322 + "1ms; noisy ??\n");
4323 + return false;
4324 + }
4325 + REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
4326 + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
4327 + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
4328 + }
4329 + REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
4330 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
4331 + REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
4332 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
4333 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
4334 + 0, AH_WAIT_TIMEOUT)) {
4335 + ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
4336 + "failed to complete in 1ms; noisy ??\n");
4337 + return false;
4338 + }
4339 +
4340 + REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
4341 + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
4342 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
4343 +
4344 + return true;
4345 +}
4346 +
4347 +static bool ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan)
4348 +{
4349 + int i;
4350 + u_int32_t txgain_max;
4351 + u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
4352 + u_int32_t reg_clc_I0, reg_clc_Q0;
4353 + u_int32_t i0_num = 0;
4354 + u_int32_t q0_num = 0;
4355 + u_int32_t total_num = 0;
4356 + u_int32_t reg_rf2g5_org;
4357 + bool retv = true;
4358 +
4359 + if (!(ar9285_hw_cl_cal(ah, chan)))
4360 + return false;
4361 +
4362 + txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
4363 + AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
4364 +
4365 + for (i = 0; i < (txgain_max+1); i++) {
4366 + clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
4367 + AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
4368 + if (!(gain_mask & (1 << clc_gain))) {
4369 + gain_mask |= (1 << clc_gain);
4370 + clc_num++;
4371 + }
4372 + }
4373 +
4374 + for (i = 0; i < clc_num; i++) {
4375 + reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
4376 + & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
4377 + reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
4378 + & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
4379 + if (reg_clc_I0 == 0)
4380 + i0_num++;
4381 +
4382 + if (reg_clc_Q0 == 0)
4383 + q0_num++;
4384 + }
4385 + total_num = i0_num + q0_num;
4386 + if (total_num > AR9285_CLCAL_REDO_THRESH) {
4387 + reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
4388 + if (AR_SREV_9285E_20(ah)) {
4389 + REG_WRITE(ah, AR9285_RF2G5,
4390 + (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
4391 + AR9285_RF2G5_IC50TX_XE_SET);
4392 + } else {
4393 + REG_WRITE(ah, AR9285_RF2G5,
4394 + (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
4395 + AR9285_RF2G5_IC50TX_SET);
4396 + }
4397 + retv = ar9285_hw_cl_cal(ah, chan);
4398 + REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
4399 + }
4400 + return retv;
4401 +}
4402 +
4403 +static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
4404 +{
4405 + struct ath_common *common = ath9k_hw_common(ah);
4406 +
4407 + if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
4408 + if (!ar9285_hw_clc(ah, chan))
4409 + return false;
4410 + } else {
4411 + if (AR_SREV_9280_10_OR_LATER(ah)) {
4412 + if (!AR_SREV_9287_10_OR_LATER(ah))
4413 + REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
4414 + AR_PHY_ADC_CTL_OFF_PWDADC);
4415 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
4416 + AR_PHY_AGC_CONTROL_FLTR_CAL);
4417 + }
4418 +
4419 + /* Calibrate the AGC */
4420 + REG_WRITE(ah, AR_PHY_AGC_CONTROL,
4421 + REG_READ(ah, AR_PHY_AGC_CONTROL) |
4422 + AR_PHY_AGC_CONTROL_CAL);
4423 +
4424 + /* Poll for offset calibration complete */
4425 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
4426 + 0, AH_WAIT_TIMEOUT)) {
4427 + ath_print(common, ATH_DBG_CALIBRATE,
4428 + "offset calibration failed to "
4429 + "complete in 1ms; noisy environment?\n");
4430 + return false;
4431 + }
4432 +
4433 + if (AR_SREV_9280_10_OR_LATER(ah)) {
4434 + if (!AR_SREV_9287_10_OR_LATER(ah))
4435 + REG_SET_BIT(ah, AR_PHY_ADC_CTL,
4436 + AR_PHY_ADC_CTL_OFF_PWDADC);
4437 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
4438 + AR_PHY_AGC_CONTROL_FLTR_CAL);
4439 + }
4440 + }
4441 +
4442 + /* Do PA Calibration */
4443 + ar9002_hw_pa_cal(ah, true);
4444 +
4445 + /* Do NF Calibration after DC offset and other calibrations */
4446 + REG_WRITE(ah, AR_PHY_AGC_CONTROL,
4447 + REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
4448 +
4449 + ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
4450 +
4451 + /* Enable IQ, ADC Gain and ADC DC offset CALs */
4452 + if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
4453 + if (ar9002_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
4454 + INIT_CAL(&ah->adcgain_caldata);
4455 + INSERT_CAL(ah, &ah->adcgain_caldata);
4456 + ath_print(common, ATH_DBG_CALIBRATE,
4457 + "enabling ADC Gain Calibration.\n");
4458 + }
4459 + if (ar9002_hw_iscal_supported(ah, ADC_DC_CAL)) {
4460 + INIT_CAL(&ah->adcdc_caldata);
4461 + INSERT_CAL(ah, &ah->adcdc_caldata);
4462 + ath_print(common, ATH_DBG_CALIBRATE,
4463 + "enabling ADC DC Calibration.\n");
4464 + }
4465 + if (ar9002_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
4466 + INIT_CAL(&ah->iq_caldata);
4467 + INSERT_CAL(ah, &ah->iq_caldata);
4468 + ath_print(common, ATH_DBG_CALIBRATE,
4469 + "enabling IQ Calibration.\n");
4470 + }
4471 +
4472 + ah->cal_list_curr = ah->cal_list;
4473 +
4474 + if (ah->cal_list_curr)
4475 + ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
4476 + }
4477 +
4478 + chan->CalValid = 0;
4479 +
4480 + return true;
4481 +}
4482 +
4483 +static const struct ath9k_percal_data iq_cal_multi_sample = {
4484 + IQ_MISMATCH_CAL,
4485 + MAX_CAL_SAMPLES,
4486 + PER_MIN_LOG_COUNT,
4487 + ar9002_hw_iqcal_collect,
4488 + ar9002_hw_iqcalibrate
4489 +};
4490 +static const struct ath9k_percal_data iq_cal_single_sample = {
4491 + IQ_MISMATCH_CAL,
4492 + MIN_CAL_SAMPLES,
4493 + PER_MAX_LOG_COUNT,
4494 + ar9002_hw_iqcal_collect,
4495 + ar9002_hw_iqcalibrate
4496 +};
4497 +static const struct ath9k_percal_data adc_gain_cal_multi_sample = {
4498 + ADC_GAIN_CAL,
4499 + MAX_CAL_SAMPLES,
4500 + PER_MIN_LOG_COUNT,
4501 + ar9002_hw_adc_gaincal_collect,
4502 + ar9002_hw_adc_gaincal_calibrate
4503 +};
4504 +static const struct ath9k_percal_data adc_gain_cal_single_sample = {
4505 + ADC_GAIN_CAL,
4506 + MIN_CAL_SAMPLES,
4507 + PER_MAX_LOG_COUNT,
4508 + ar9002_hw_adc_gaincal_collect,
4509 + ar9002_hw_adc_gaincal_calibrate
4510 +};
4511 +static const struct ath9k_percal_data adc_dc_cal_multi_sample = {
4512 + ADC_DC_CAL,
4513 + MAX_CAL_SAMPLES,
4514 + PER_MIN_LOG_COUNT,
4515 + ar9002_hw_adc_dccal_collect,
4516 + ar9002_hw_adc_dccal_calibrate
4517 +};
4518 +static const struct ath9k_percal_data adc_dc_cal_single_sample = {
4519 + ADC_DC_CAL,
4520 + MIN_CAL_SAMPLES,
4521 + PER_MAX_LOG_COUNT,
4522 + ar9002_hw_adc_dccal_collect,
4523 + ar9002_hw_adc_dccal_calibrate
4524 +};
4525 +static const struct ath9k_percal_data adc_init_dc_cal = {
4526 + ADC_DC_INIT_CAL,
4527 + MIN_CAL_SAMPLES,
4528 + INIT_LOG_COUNT,
4529 + ar9002_hw_adc_dccal_collect,
4530 + ar9002_hw_adc_dccal_calibrate
4531 +};
4532 +
4533 +static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
4534 +{
4535 + if (AR_SREV_9100(ah)) {
4536 + ah->iq_caldata.calData = &iq_cal_multi_sample;
4537 + ah->supp_cals = IQ_MISMATCH_CAL;
4538 + return;
4539 + }
4540 +
4541 + if (AR_SREV_9160_10_OR_LATER(ah)) {
4542 + if (AR_SREV_9280_10_OR_LATER(ah)) {
4543 + ah->iq_caldata.calData = &iq_cal_single_sample;
4544 + ah->adcgain_caldata.calData =
4545 + &adc_gain_cal_single_sample;
4546 + ah->adcdc_caldata.calData =
4547 + &adc_dc_cal_single_sample;
4548 + ah->adcdc_calinitdata.calData =
4549 + &adc_init_dc_cal;
4550 + } else {
4551 + ah->iq_caldata.calData = &iq_cal_multi_sample;
4552 + ah->adcgain_caldata.calData =
4553 + &adc_gain_cal_multi_sample;
4554 + ah->adcdc_caldata.calData =
4555 + &adc_dc_cal_multi_sample;
4556 + ah->adcdc_calinitdata.calData =
4557 + &adc_init_dc_cal;
4558 + }
4559 + ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
4560 + }
4561 +}
4562 +
4563 +void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
4564 +{
4565 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
4566 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
4567 +
4568 + priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
4569 + priv_ops->init_cal = ar9002_hw_init_cal;
4570 + priv_ops->setup_calibration = ar9002_hw_setup_calibration;
4571 + priv_ops->iscal_supported = ar9002_hw_iscal_supported;
4572 +
4573 + ops->calibrate = ar9002_hw_calibrate;
4574 +}
4575 --- /dev/null
4576 +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
4577 @@ -0,0 +1,584 @@
4578 +/*
4579 + * Copyright (c) 2008-2010 Atheros Communications Inc.
4580 + *
4581 + * Permission to use, copy, modify, and/or distribute this software for any
4582 + * purpose with or without fee is hereby granted, provided that the above
4583 + * copyright notice and this permission notice appear in all copies.
4584 + *
4585 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
4586 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
4587 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
4588 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
4589 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
4590 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
4591 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
4592 + */
4593 +
4594 +#include "hw.h"
4595 +#include "ar5008_initvals.h"
4596 +#include "ar9001_initvals.h"
4597 +#include "ar9002_initvals.h"
4598 +
4599 +/* General hardware code for the A5008/AR9001/AR9002 hadware families */
4600 +
4601 +static bool ar9002_hw_macversion_supported(u32 macversion)
4602 +{
4603 + switch (macversion) {
4604 + case AR_SREV_VERSION_5416_PCI:
4605 + case AR_SREV_VERSION_5416_PCIE:
4606 + case AR_SREV_VERSION_9160:
4607 + case AR_SREV_VERSION_9100:
4608 + case AR_SREV_VERSION_9280:
4609 + case AR_SREV_VERSION_9285:
4610 + case AR_SREV_VERSION_9287:
4611 + case AR_SREV_VERSION_9271:
4612 + return true;
4613 + default:
4614 + break;
4615 + }
4616 + return false;
4617 +}
4618 +
4619 +static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
4620 +{
4621 + if (AR_SREV_9271(ah)) {
4622 + INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
4623 + ARRAY_SIZE(ar9271Modes_9271), 6);
4624 + INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
4625 + ARRAY_SIZE(ar9271Common_9271), 2);
4626 + INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
4627 + ar9271Common_normal_cck_fir_coeff_9271,
4628 + ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
4629 + INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
4630 + ar9271Common_japan_2484_cck_fir_coeff_9271,
4631 + ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
4632 + INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
4633 + ar9271Modes_9271_1_0_only,
4634 + ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
4635 + INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
4636 + ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
4637 + INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
4638 + ar9271Modes_high_power_tx_gain_9271,
4639 + ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
4640 + INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
4641 + ar9271Modes_normal_power_tx_gain_9271,
4642 + ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
4643 + return;
4644 + }
4645 +
4646 + if (AR_SREV_9287_11_OR_LATER(ah)) {
4647 + INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
4648 + ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
4649 + INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
4650 + ARRAY_SIZE(ar9287Common_9287_1_1), 2);
4651 + if (ah->config.pcie_clock_req)
4652 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4653 + ar9287PciePhy_clkreq_off_L1_9287_1_1,
4654 + ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
4655 + else
4656 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4657 + ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
4658 + ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
4659 + 2);
4660 + } else if (AR_SREV_9287_10_OR_LATER(ah)) {
4661 + INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
4662 + ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
4663 + INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
4664 + ARRAY_SIZE(ar9287Common_9287_1_0), 2);
4665 +
4666 + if (ah->config.pcie_clock_req)
4667 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4668 + ar9287PciePhy_clkreq_off_L1_9287_1_0,
4669 + ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
4670 + else
4671 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4672 + ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
4673 + ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
4674 + 2);
4675 + } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4676 +
4677 +
4678 + INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
4679 + ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
4680 + INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
4681 + ARRAY_SIZE(ar9285Common_9285_1_2), 2);
4682 +
4683 + if (ah->config.pcie_clock_req) {
4684 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4685 + ar9285PciePhy_clkreq_off_L1_9285_1_2,
4686 + ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
4687 + } else {
4688 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4689 + ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
4690 + ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
4691 + 2);
4692 + }
4693 + } else if (AR_SREV_9285_10_OR_LATER(ah)) {
4694 + INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
4695 + ARRAY_SIZE(ar9285Modes_9285), 6);
4696 + INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
4697 + ARRAY_SIZE(ar9285Common_9285), 2);
4698 +
4699 + if (ah->config.pcie_clock_req) {
4700 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4701 + ar9285PciePhy_clkreq_off_L1_9285,
4702 + ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
4703 + } else {
4704 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4705 + ar9285PciePhy_clkreq_always_on_L1_9285,
4706 + ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
4707 + }
4708 + } else if (AR_SREV_9280_20_OR_LATER(ah)) {
4709 + INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
4710 + ARRAY_SIZE(ar9280Modes_9280_2), 6);
4711 + INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
4712 + ARRAY_SIZE(ar9280Common_9280_2), 2);
4713 +
4714 + if (ah->config.pcie_clock_req) {
4715 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4716 + ar9280PciePhy_clkreq_off_L1_9280,
4717 + ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
4718 + } else {
4719 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4720 + ar9280PciePhy_clkreq_always_on_L1_9280,
4721 + ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
4722 + }
4723 + INIT_INI_ARRAY(&ah->iniModesAdditional,
4724 + ar9280Modes_fast_clock_9280_2,
4725 + ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
4726 + } else if (AR_SREV_9280_10_OR_LATER(ah)) {
4727 + INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
4728 + ARRAY_SIZE(ar9280Modes_9280), 6);
4729 + INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
4730 + ARRAY_SIZE(ar9280Common_9280), 2);
4731 + } else if (AR_SREV_9160_10_OR_LATER(ah)) {
4732 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
4733 + ARRAY_SIZE(ar5416Modes_9160), 6);
4734 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
4735 + ARRAY_SIZE(ar5416Common_9160), 2);
4736 + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
4737 + ARRAY_SIZE(ar5416Bank0_9160), 2);
4738 + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
4739 + ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
4740 + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
4741 + ARRAY_SIZE(ar5416Bank1_9160), 2);
4742 + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
4743 + ARRAY_SIZE(ar5416Bank2_9160), 2);
4744 + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
4745 + ARRAY_SIZE(ar5416Bank3_9160), 3);
4746 + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
4747 + ARRAY_SIZE(ar5416Bank6_9160), 3);
4748 + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
4749 + ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
4750 + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
4751 + ARRAY_SIZE(ar5416Bank7_9160), 2);
4752 + if (AR_SREV_9160_11(ah)) {
4753 + INIT_INI_ARRAY(&ah->iniAddac,
4754 + ar5416Addac_91601_1,
4755 + ARRAY_SIZE(ar5416Addac_91601_1), 2);
4756 + } else {
4757 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
4758 + ARRAY_SIZE(ar5416Addac_9160), 2);
4759 + }
4760 + } else if (AR_SREV_9100_OR_LATER(ah)) {
4761 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
4762 + ARRAY_SIZE(ar5416Modes_9100), 6);
4763 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
4764 + ARRAY_SIZE(ar5416Common_9100), 2);
4765 + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
4766 + ARRAY_SIZE(ar5416Bank0_9100), 2);
4767 + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
4768 + ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
4769 + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
4770 + ARRAY_SIZE(ar5416Bank1_9100), 2);
4771 + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
4772 + ARRAY_SIZE(ar5416Bank2_9100), 2);
4773 + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
4774 + ARRAY_SIZE(ar5416Bank3_9100), 3);
4775 + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
4776 + ARRAY_SIZE(ar5416Bank6_9100), 3);
4777 + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
4778 + ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
4779 + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
4780 + ARRAY_SIZE(ar5416Bank7_9100), 2);
4781 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
4782 + ARRAY_SIZE(ar5416Addac_9100), 2);
4783 + } else {
4784 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
4785 + ARRAY_SIZE(ar5416Modes), 6);
4786 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
4787 + ARRAY_SIZE(ar5416Common), 2);
4788 + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
4789 + ARRAY_SIZE(ar5416Bank0), 2);
4790 + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
4791 + ARRAY_SIZE(ar5416BB_RfGain), 3);
4792 + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
4793 + ARRAY_SIZE(ar5416Bank1), 2);
4794 + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
4795 + ARRAY_SIZE(ar5416Bank2), 2);
4796 + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
4797 + ARRAY_SIZE(ar5416Bank3), 3);
4798 + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
4799 + ARRAY_SIZE(ar5416Bank6), 3);
4800 + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
4801 + ARRAY_SIZE(ar5416Bank6TPC), 3);
4802 + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
4803 + ARRAY_SIZE(ar5416Bank7), 2);
4804 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
4805 + ARRAY_SIZE(ar5416Addac), 2);
4806 + }
4807 +}
4808 +
4809 +/* Support for Japan ch.14 (2484) spread */
4810 +void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
4811 +{
4812 + if (AR_SREV_9287_11_OR_LATER(ah)) {
4813 + INIT_INI_ARRAY(&ah->iniCckfirNormal,
4814 + ar9287Common_normal_cck_fir_coeff_92871_1,
4815 + ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
4816 + INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
4817 + ar9287Common_japan_2484_cck_fir_coeff_92871_1,
4818 + ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
4819 + }
4820 +}
4821 +
4822 +static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
4823 +{
4824 + u32 rxgain_type;
4825 +
4826 + if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
4827 + rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
4828 +
4829 + if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
4830 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4831 + ar9280Modes_backoff_13db_rxgain_9280_2,
4832 + ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
4833 + else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
4834 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4835 + ar9280Modes_backoff_23db_rxgain_9280_2,
4836 + ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
4837 + else
4838 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4839 + ar9280Modes_original_rxgain_9280_2,
4840 + ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
4841 + } else {
4842 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4843 + ar9280Modes_original_rxgain_9280_2,
4844 + ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
4845 + }
4846 +}
4847 +
4848 +static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah)
4849 +{
4850 + u32 txgain_type;
4851 +
4852 + if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
4853 + txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
4854 +
4855 + if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
4856 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4857 + ar9280Modes_high_power_tx_gain_9280_2,
4858 + ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
4859 + else
4860 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4861 + ar9280Modes_original_tx_gain_9280_2,
4862 + ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
4863 + } else {
4864 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4865 + ar9280Modes_original_tx_gain_9280_2,
4866 + ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
4867 + }
4868 +}
4869 +
4870 +static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
4871 +{
4872 + if (AR_SREV_9287_11_OR_LATER(ah))
4873 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4874 + ar9287Modes_rx_gain_9287_1_1,
4875 + ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
4876 + else if (AR_SREV_9287_10(ah))
4877 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4878 + ar9287Modes_rx_gain_9287_1_0,
4879 + ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
4880 + else if (AR_SREV_9280_20(ah))
4881 + ar9280_20_hw_init_rxgain_ini(ah);
4882 +
4883 + if (AR_SREV_9287_11_OR_LATER(ah)) {
4884 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4885 + ar9287Modes_tx_gain_9287_1_1,
4886 + ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
4887 + } else if (AR_SREV_9287_10(ah)) {
4888 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4889 + ar9287Modes_tx_gain_9287_1_0,
4890 + ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
4891 + } else if (AR_SREV_9280_20(ah)) {
4892 + ar9280_20_hw_init_txgain_ini(ah);
4893 + } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4894 + u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
4895 +
4896 + /* txgain table */
4897 + if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
4898 + if (AR_SREV_9285E_20(ah)) {
4899 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4900 + ar9285Modes_XE2_0_high_power,
4901 + ARRAY_SIZE(
4902 + ar9285Modes_XE2_0_high_power), 6);
4903 + } else {
4904 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4905 + ar9285Modes_high_power_tx_gain_9285_1_2,
4906 + ARRAY_SIZE(
4907 + ar9285Modes_high_power_tx_gain_9285_1_2), 6);
4908 + }
4909 + } else {
4910 + if (AR_SREV_9285E_20(ah)) {
4911 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4912 + ar9285Modes_XE2_0_normal_power,
4913 + ARRAY_SIZE(
4914 + ar9285Modes_XE2_0_normal_power), 6);
4915 + } else {
4916 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4917 + ar9285Modes_original_tx_gain_9285_1_2,
4918 + ARRAY_SIZE(
4919 + ar9285Modes_original_tx_gain_9285_1_2), 6);
4920 + }
4921 + }
4922 + }
4923 +}
4924 +
4925 +/*
4926 + * Helper for ASPM support.
4927 + *
4928 + * Disable PLL when in L0s as well as receiver clock when in L1.
4929 + * This power saving option must be enabled through the SerDes.
4930 + *
4931 + * Programming the SerDes must go through the same 288 bit serial shift
4932 + * register as the other analog registers. Hence the 9 writes.
4933 + */
4934 +static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
4935 + int restore,
4936 + int power_off)
4937 +{
4938 + u8 i;
4939 + u32 val;
4940 +
4941 + if (ah->is_pciexpress != true)
4942 + return;
4943 +
4944 + /* Do not touch SerDes registers */
4945 + if (ah->config.pcie_powersave_enable == 2)
4946 + return;
4947 +
4948 + /* Nothing to do on restore for 11N */
4949 + if (!restore) {
4950 + if (AR_SREV_9280_20_OR_LATER(ah)) {
4951 + /*
4952 + * AR9280 2.0 or later chips use SerDes values from the
4953 + * initvals.h initialized depending on chipset during
4954 + * __ath9k_hw_init()
4955 + */
4956 + for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
4957 + REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
4958 + INI_RA(&ah->iniPcieSerdes, i, 1));
4959 + }
4960 + } else if (AR_SREV_9280(ah) &&
4961 + (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
4962 + REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
4963 + REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
4964 +
4965 + /* RX shut off when elecidle is asserted */
4966 + REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
4967 + REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
4968 + REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
4969 +
4970 + /* Shut off CLKREQ active in L1 */
4971 + if (ah->config.pcie_clock_req)
4972 + REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
4973 + else
4974 + REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
4975 +
4976 + REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
4977 + REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
4978 + REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
4979 +
4980 + /* Load the new settings */
4981 + REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
4982 +
4983 + } else {
4984 + REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
4985 + REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
4986 +
4987 + /* RX shut off when elecidle is asserted */
4988 + REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
4989 + REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
4990 + REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
4991 +
4992 + /*
4993 + * Ignore ah->ah_config.pcie_clock_req setting for
4994 + * pre-AR9280 11n
4995 + */
4996 + REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
4997 +
4998 + REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
4999 + REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
5000 + REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
5001 +
5002 + /* Load the new settings */
5003 + REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
5004 + }
5005 +
5006 + udelay(1000);
5007 +
5008 + /* set bit 19 to allow forcing of pcie core into L1 state */
5009 + REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
5010 +
5011 + /* Several PCIe massages to ensure proper behaviour */
5012 + if (ah->config.pcie_waen) {
5013 + val = ah->config.pcie_waen;
5014 + if (!power_off)
5015 + val &= (~AR_WA_D3_L1_DISABLE);
5016 + } else {
5017 + if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
5018 + AR_SREV_9287(ah)) {
5019 + val = AR9285_WA_DEFAULT;
5020 + if (!power_off)
5021 + val &= (~AR_WA_D3_L1_DISABLE);
5022 + } else if (AR_SREV_9280(ah)) {
5023 + /*
5024 + * On AR9280 chips bit 22 of 0x4004 needs to be
5025 + * set otherwise card may disappear.
5026 + */
5027 + val = AR9280_WA_DEFAULT;
5028 + if (!power_off)
5029 + val &= (~AR_WA_D3_L1_DISABLE);
5030 + } else
5031 + val = AR_WA_DEFAULT;
5032 + }
5033 +
5034 + REG_WRITE(ah, AR_WA, val);
5035 + }
5036 +
5037 + if (power_off) {
5038 + /*
5039 + * Set PCIe workaround bits
5040 + * bit 14 in WA register (disable L1) should only
5041 + * be set when device enters D3 and be cleared
5042 + * when device comes back to D0.
5043 + */
5044 + if (ah->config.pcie_waen) {
5045 + if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
5046 + REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
5047 + } else {
5048 + if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
5049 + AR_SREV_9287(ah)) &&
5050 + (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
5051 + (AR_SREV_9280(ah) &&
5052 + (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
5053 + REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
5054 + }
5055 + }
5056 + }
5057 +}
5058 +
5059 +static int ar9002_hw_get_radiorev(struct ath_hw *ah)
5060 +{
5061 + u32 val;
5062 + int i;
5063 +
5064 + REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
5065 +
5066 + for (i = 0; i < 8; i++)
5067 + REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
5068 + val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
5069 + val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
5070 +
5071 + return ath9k_hw_reverse_bits(val, 8);
5072 +}
5073 +
5074 +int ar9002_hw_rf_claim(struct ath_hw *ah)
5075 +{
5076 + u32 val;
5077 +
5078 + REG_WRITE(ah, AR_PHY(0), 0x00000007);
5079 +
5080 + val = ar9002_hw_get_radiorev(ah);
5081 + switch (val & AR_RADIO_SREV_MAJOR) {
5082 + case 0:
5083 + val = AR_RAD5133_SREV_MAJOR;
5084 + break;
5085 + case AR_RAD5133_SREV_MAJOR:
5086 + case AR_RAD5122_SREV_MAJOR:
5087 + case AR_RAD2133_SREV_MAJOR:
5088 + case AR_RAD2122_SREV_MAJOR:
5089 + break;
5090 + default:
5091 + ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
5092 + "Radio Chip Rev 0x%02X not supported\n",
5093 + val & AR_RADIO_SREV_MAJOR);
5094 + return -EOPNOTSUPP;
5095 + }
5096 +
5097 + ah->hw_version.analog5GhzRev = val;
5098 +
5099 + return 0;
5100 +}
5101 +
5102 +/*
5103 + * Enable ASYNC FIFO
5104 + *
5105 + * If Async FIFO is enabled, the following counters change as MAC now runs
5106 + * at 117 Mhz instead of 88/44MHz when async FIFO is disabled.
5107 + *
5108 + * The values below tested for ht40 2 chain.
5109 + * Overwrite the delay/timeouts initialized in process ini.
5110 + */
5111 +void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
5112 +{
5113 + if (AR_SREV_9287_12_OR_LATER(ah)) {
5114 + REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
5115 + AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
5116 + REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
5117 + AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
5118 + REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
5119 + AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
5120 +
5121 + REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
5122 + REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
5123 +
5124 + REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
5125 + AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
5126 + REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
5127 + AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
5128 + }
5129 +}
5130 +
5131 +/*
5132 + * We don't enable WEP aggregation on mac80211 but we keep this
5133 + * around for HAL unification purposes.
5134 + */
5135 +void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
5136 +{
5137 + if (AR_SREV_9287_12_OR_LATER(ah)) {
5138 + REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
5139 + AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
5140 + }
5141 +}
5142 +
5143 +/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
5144 +void ar9002_hw_attach_ops(struct ath_hw *ah)
5145 +{
5146 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
5147 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
5148 +
5149 + priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
5150 + priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
5151 + priv_ops->macversion_supported = ar9002_hw_macversion_supported;
5152 +
5153 + ops->config_pci_powersave = ar9002_hw_configpcipowersave;
5154 +
5155 + ar5008_hw_attach_phy_ops(ah);
5156 + if (AR_SREV_9280_10_OR_LATER(ah))
5157 + ar9002_hw_attach_phy_ops(ah);
5158 +
5159 + ar9002_hw_attach_calib_ops(ah);
5160 + ar9002_hw_attach_mac_ops(ah);
5161 +}
5162 --- /dev/null
5163 +++ b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
5164 @@ -0,0 +1,5229 @@
5165 +/*
5166 + * Copyright (c) 2010 Atheros Communications Inc.
5167 + *
5168 + * Permission to use, copy, modify, and/or distribute this software for any
5169 + * purpose with or without fee is hereby granted, provided that the above
5170 + * copyright notice and this permission notice appear in all copies.
5171 + *
5172 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
5173 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
5174 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
5175 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
5176 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
5177 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
5178 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
5179 + */
5180 +
5181 +#ifndef INITVALS_9002_10_H
5182 +#define INITVALS_9002_10_H
5183 +
5184 +static const u32 ar9280Modes_9280[][6] = {
5185 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
5186 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
5187 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
5188 + { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
5189 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801080, 0x08400840, 0x06e006e0 },
5190 + { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
5191 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
5192 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
5193 + { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
5194 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
5195 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
5196 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
5197 + { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
5198 + { 0x00009848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 },
5199 + { 0x0000a848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 },
5200 + { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
5201 + { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
5202 + { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
5203 + { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d20, 0x00049d20, 0x00049d18 },
5204 + { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
5205 + { 0x00009868, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190 },
5206 + { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
5207 + { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
5208 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
5209 + { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
5210 + { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010 },
5211 + { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
5212 + { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
5213 + { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
5214 + { 0x0000c9b8, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a },
5215 + { 0x0000c9bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
5216 + { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
5217 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
5218 + { 0x000099c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c },
5219 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
5220 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
5221 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
5222 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
5223 + { 0x00009a00, 0x00008184, 0x00008184, 0x00000214, 0x00000214, 0x00000214 },
5224 + { 0x00009a04, 0x00008188, 0x00008188, 0x00000218, 0x00000218, 0x00000218 },
5225 + { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000224, 0x00000224, 0x00000224 },
5226 + { 0x00009a0c, 0x00008190, 0x00008190, 0x00000228, 0x00000228, 0x00000228 },
5227 + { 0x00009a10, 0x00008194, 0x00008194, 0x0000022c, 0x0000022c, 0x0000022c },
5228 + { 0x00009a14, 0x00008200, 0x00008200, 0x00000230, 0x00000230, 0x00000230 },
5229 + { 0x00009a18, 0x00008204, 0x00008204, 0x000002a4, 0x000002a4, 0x000002a4 },
5230 + { 0x00009a1c, 0x00008208, 0x00008208, 0x000002a8, 0x000002a8, 0x000002a8 },
5231 + { 0x00009a20, 0x0000820c, 0x0000820c, 0x000002ac, 0x000002ac, 0x000002ac },
5232 + { 0x00009a24, 0x00008210, 0x00008210, 0x000002b0, 0x000002b0, 0x000002b0 },
5233 + { 0x00009a28, 0x00008214, 0x00008214, 0x000002b4, 0x000002b4, 0x000002b4 },
5234 + { 0x00009a2c, 0x00008280, 0x00008280, 0x000002b8, 0x000002b8, 0x000002b8 },
5235 + { 0x00009a30, 0x00008284, 0x00008284, 0x00000390, 0x00000390, 0x00000390 },
5236 + { 0x00009a34, 0x00008288, 0x00008288, 0x00000394, 0x00000394, 0x00000394 },
5237 + { 0x00009a38, 0x0000828c, 0x0000828c, 0x00000398, 0x00000398, 0x00000398 },
5238 + { 0x00009a3c, 0x00008290, 0x00008290, 0x00000334, 0x00000334, 0x00000334 },
5239 + { 0x00009a40, 0x00008300, 0x00008300, 0x00000338, 0x00000338, 0x00000338 },
5240 + { 0x00009a44, 0x00008304, 0x00008304, 0x000003ac, 0x000003ac, 0x000003ac },
5241 + { 0x00009a48, 0x00008308, 0x00008308, 0x000003b0, 0x000003b0, 0x000003b0 },
5242 + { 0x00009a4c, 0x0000830c, 0x0000830c, 0x000003b4, 0x000003b4, 0x000003b4 },
5243 + { 0x00009a50, 0x00008310, 0x00008310, 0x000003b8, 0x000003b8, 0x000003b8 },
5244 + { 0x00009a54, 0x00008314, 0x00008314, 0x000003a5, 0x000003a5, 0x000003a5 },
5245 + { 0x00009a58, 0x00008380, 0x00008380, 0x000003a9, 0x000003a9, 0x000003a9 },
5246 + { 0x00009a5c, 0x00008384, 0x00008384, 0x000003ad, 0x000003ad, 0x000003ad },
5247 + { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
5248 + { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
5249 + { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
5250 + { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
5251 + { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
5252 + { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
5253 + { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
5254 + { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
5255 + { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
5256 + { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
5257 + { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
5258 + { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
5259 + { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
5260 + { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
5261 + { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
5262 + { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
5263 + { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
5264 + { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
5265 + { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
5266 + { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
5267 + { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
5268 + { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
5269 + { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
5270 + { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
5271 + { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
5272 + { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
5273 + { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
5274 + { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
5275 + { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
5276 + { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
5277 + { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
5278 + { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
5279 + { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
5280 + { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
5281 + { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c },
5282 + { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 },
5283 + { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 },
5284 + { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 },
5285 + { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 },
5286 + { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 },
5287 + { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 },
5288 + { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 },
5289 + { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 },
5290 + { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 },
5291 + { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 },
5292 + { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 },
5293 + { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 },
5294 + { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c },
5295 + { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 },
5296 + { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 },
5297 + { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 },
5298 + { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 },
5299 + { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 },
5300 + { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 },
5301 + { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 },
5302 + { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 },
5303 + { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad },
5304 + { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 },
5305 + { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 },
5306 + { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 },
5307 + { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 },
5308 + { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 },
5309 + { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 },
5310 + { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 },
5311 + { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 },
5312 + { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 },
5313 + { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca },
5314 + { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce },
5315 + { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 },
5316 + { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 },
5317 + { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 },
5318 + { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 },
5319 + { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb },
5320 + { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf },
5321 + { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 },
5322 + { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db },
5323 + { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db },
5324 + { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db },
5325 + { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5326 + { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5327 + { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5328 + { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5329 + { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5330 + { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5331 + { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5332 + { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5333 + { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5334 + { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5335 + { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5336 + { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5337 + { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5338 + { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5339 + { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5340 + { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5341 + { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5342 + { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5343 + { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5344 + { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5345 + { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5346 + { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5347 + { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5348 + { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5349 + { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5350 + { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5351 + { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 },
5352 + { 0x0000a208, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788 },
5353 + { 0x0000a20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 },
5354 + { 0x0000b20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 },
5355 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
5356 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
5357 + { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
5358 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
5359 + { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
5360 + { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
5361 + { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b },
5362 + { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 },
5363 + { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 },
5364 + { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a },
5365 + { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 },
5366 + { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
5367 + { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b },
5368 + { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 },
5369 + { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 },
5370 + { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a },
5371 + { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 },
5372 + { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b },
5373 + { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 },
5374 + { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 },
5375 + { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a },
5376 + { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 },
5377 + { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a },
5378 + { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 },
5379 + { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 },
5380 + { 0x0000784c, 0x0e4f048c, 0x0e4f048c, 0x0e4d048c, 0x0e4d048c, 0x0e4d048c },
5381 + { 0x00007854, 0x12031828, 0x12031828, 0x12035828, 0x12035828, 0x12035828 },
5382 + { 0x00007870, 0x807ec400, 0x807ec400, 0x807ec000, 0x807ec000, 0x807ec000 },
5383 + { 0x0000788c, 0x00010000, 0x00010000, 0x00110000, 0x00110000, 0x00110000 },
5384 +};
5385 +
5386 +static const u32 ar9280Common_9280[][2] = {
5387 + { 0x0000000c, 0x00000000 },
5388 + { 0x00000030, 0x00020015 },
5389 + { 0x00000034, 0x00000005 },
5390 + { 0x00000040, 0x00000000 },
5391 + { 0x00000044, 0x00000008 },
5392 + { 0x00000048, 0x00000008 },
5393 + { 0x0000004c, 0x00000010 },
5394 + { 0x00000050, 0x00000000 },
5395 + { 0x00000054, 0x0000001f },
5396 + { 0x00000800, 0x00000000 },
5397 + { 0x00000804, 0x00000000 },
5398 + { 0x00000808, 0x00000000 },
5399 + { 0x0000080c, 0x00000000 },
5400 + { 0x00000810, 0x00000000 },
5401 + { 0x00000814, 0x00000000 },
5402 + { 0x00000818, 0x00000000 },
5403 + { 0x0000081c, 0x00000000 },
5404 + { 0x00000820, 0x00000000 },
5405 + { 0x00000824, 0x00000000 },
5406 + { 0x00001040, 0x002ffc0f },
5407 + { 0x00001044, 0x002ffc0f },
5408 + { 0x00001048, 0x002ffc0f },
5409 + { 0x0000104c, 0x002ffc0f },
5410 + { 0x00001050, 0x002ffc0f },
5411 + { 0x00001054, 0x002ffc0f },
5412 + { 0x00001058, 0x002ffc0f },
5413 + { 0x0000105c, 0x002ffc0f },
5414 + { 0x00001060, 0x002ffc0f },
5415 + { 0x00001064, 0x002ffc0f },
5416 + { 0x00001230, 0x00000000 },
5417 + { 0x00001270, 0x00000000 },
5418 + { 0x00001038, 0x00000000 },
5419 + { 0x00001078, 0x00000000 },
5420 + { 0x000010b8, 0x00000000 },
5421 + { 0x000010f8, 0x00000000 },
5422 + { 0x00001138, 0x00000000 },
5423 + { 0x00001178, 0x00000000 },
5424 + { 0x000011b8, 0x00000000 },
5425 + { 0x000011f8, 0x00000000 },
5426 + { 0x00001238, 0x00000000 },
5427 + { 0x00001278, 0x00000000 },
5428 + { 0x000012b8, 0x00000000 },
5429 + { 0x000012f8, 0x00000000 },
5430 + { 0x00001338, 0x00000000 },
5431 + { 0x00001378, 0x00000000 },
5432 + { 0x000013b8, 0x00000000 },
5433 + { 0x000013f8, 0x00000000 },
5434 + { 0x00001438, 0x00000000 },
5435 + { 0x00001478, 0x00000000 },
5436 + { 0x000014b8, 0x00000000 },
5437 + { 0x000014f8, 0x00000000 },
5438 + { 0x00001538, 0x00000000 },
5439 + { 0x00001578, 0x00000000 },
5440 + { 0x000015b8, 0x00000000 },
5441 + { 0x000015f8, 0x00000000 },
5442 + { 0x00001638, 0x00000000 },
5443 + { 0x00001678, 0x00000000 },
5444 + { 0x000016b8, 0x00000000 },
5445 + { 0x000016f8, 0x00000000 },
5446 + { 0x00001738, 0x00000000 },
5447 + { 0x00001778, 0x00000000 },
5448 + { 0x000017b8, 0x00000000 },
5449 + { 0x000017f8, 0x00000000 },
5450 + { 0x0000103c, 0x00000000 },
5451 + { 0x0000107c, 0x00000000 },
5452 + { 0x000010bc, 0x00000000 },
5453 + { 0x000010fc, 0x00000000 },
5454 + { 0x0000113c, 0x00000000 },
5455 + { 0x0000117c, 0x00000000 },
5456 + { 0x000011bc, 0x00000000 },
5457 + { 0x000011fc, 0x00000000 },
5458 + { 0x0000123c, 0x00000000 },
5459 + { 0x0000127c, 0x00000000 },
5460 + { 0x000012bc, 0x00000000 },
5461 + { 0x000012fc, 0x00000000 },
5462 + { 0x0000133c, 0x00000000 },
5463 + { 0x0000137c, 0x00000000 },
5464 + { 0x000013bc, 0x00000000 },
5465 + { 0x000013fc, 0x00000000 },
5466 + { 0x0000143c, 0x00000000 },
5467 + { 0x0000147c, 0x00000000 },
5468 + { 0x00004030, 0x00000002 },
5469 + { 0x0000403c, 0x00000002 },
5470 + { 0x00004024, 0x0000001f },
5471 + { 0x00007010, 0x00000033 },
5472 + { 0x00007038, 0x000004c2 },
5473 + { 0x00008004, 0x00000000 },
5474 + { 0x00008008, 0x00000000 },
5475 + { 0x0000800c, 0x00000000 },
5476 + { 0x00008018, 0x00000700 },
5477 + { 0x00008020, 0x00000000 },
5478 + { 0x00008038, 0x00000000 },
5479 + { 0x0000803c, 0x00000000 },
5480 + { 0x00008048, 0x40000000 },
5481 + { 0x00008054, 0x00000000 },
5482 + { 0x00008058, 0x00000000 },
5483 + { 0x0000805c, 0x000fc78f },
5484 + { 0x00008060, 0x0000000f },
5485 + { 0x00008064, 0x00000000 },
5486 + { 0x00008070, 0x00000000 },
5487 + { 0x000080c0, 0x2a82301a },
5488 + { 0x000080c4, 0x05dc01e0 },
5489 + { 0x000080c8, 0x1f402710 },
5490 + { 0x000080cc, 0x01f40000 },
5491 + { 0x000080d0, 0x00001e00 },
5492 + { 0x000080d4, 0x00000000 },
5493 + { 0x000080d8, 0x00400000 },
5494 + { 0x000080e0, 0xffffffff },
5495 + { 0x000080e4, 0x0000ffff },
5496 + { 0x000080e8, 0x003f3f3f },
5497 + { 0x000080ec, 0x00000000 },
5498 + { 0x000080f0, 0x00000000 },
5499 + { 0x000080f4, 0x00000000 },
5500 + { 0x000080f8, 0x00000000 },
5501 + { 0x000080fc, 0x00020000 },
5502 + { 0x00008100, 0x00020000 },
5503 + { 0x00008104, 0x00000001 },
5504 + { 0x00008108, 0x00000052 },
5505 + { 0x0000810c, 0x00000000 },
5506 + { 0x00008110, 0x00000168 },
5507 + { 0x00008118, 0x000100aa },
5508 + { 0x0000811c, 0x00003210 },
5509 + { 0x00008120, 0x08f04800 },
5510 + { 0x00008124, 0x00000000 },
5511 + { 0x00008128, 0x00000000 },
5512 + { 0x0000812c, 0x00000000 },
5513 + { 0x00008130, 0x00000000 },
5514 + { 0x00008134, 0x00000000 },
5515 + { 0x00008138, 0x00000000 },
5516 + { 0x0000813c, 0x00000000 },
5517 + { 0x00008144, 0x00000000 },
5518 + { 0x00008168, 0x00000000 },
5519 + { 0x0000816c, 0x00000000 },
5520 + { 0x00008170, 0x32143320 },
5521 + { 0x00008174, 0xfaa4fa50 },
5522 + { 0x00008178, 0x00000100 },
5523 + { 0x0000817c, 0x00000000 },
5524 + { 0x000081c4, 0x00000000 },
5525 + { 0x000081d0, 0x00003210 },
5526 + { 0x000081ec, 0x00000000 },
5527 + { 0x000081f0, 0x00000000 },
5528 + { 0x000081f4, 0x00000000 },
5529 + { 0x000081f8, 0x00000000 },
5530 + { 0x000081fc, 0x00000000 },
5531 + { 0x00008200, 0x00000000 },
5532 + { 0x00008204, 0x00000000 },
5533 + { 0x00008208, 0x00000000 },
5534 + { 0x0000820c, 0x00000000 },
5535 + { 0x00008210, 0x00000000 },
5536 + { 0x00008214, 0x00000000 },
5537 + { 0x00008218, 0x00000000 },
5538 + { 0x0000821c, 0x00000000 },
5539 + { 0x00008220, 0x00000000 },
5540 + { 0x00008224, 0x00000000 },
5541 + { 0x00008228, 0x00000000 },
5542 + { 0x0000822c, 0x00000000 },
5543 + { 0x00008230, 0x00000000 },
5544 + { 0x00008234, 0x00000000 },
5545 + { 0x00008238, 0x00000000 },
5546 + { 0x0000823c, 0x00000000 },
5547 + { 0x00008240, 0x00100000 },
5548 + { 0x00008244, 0x0010f400 },
5549 + { 0x00008248, 0x00000100 },
5550 + { 0x0000824c, 0x0001e800 },
5551 + { 0x00008250, 0x00000000 },
5552 + { 0x00008254, 0x00000000 },
5553 + { 0x00008258, 0x00000000 },
5554 + { 0x0000825c, 0x400000ff },
5555 + { 0x00008260, 0x00080922 },
5556 + { 0x00008270, 0x00000000 },
5557 + { 0x00008274, 0x40000000 },
5558 + { 0x00008278, 0x003e4180 },
5559 + { 0x0000827c, 0x00000000 },
5560 + { 0x00008284, 0x0000002c },
5561 + { 0x00008288, 0x0000002c },
5562 + { 0x0000828c, 0x00000000 },
5563 + { 0x00008294, 0x00000000 },
5564 + { 0x00008298, 0x00000000 },
5565 + { 0x00008300, 0x00000000 },
5566 + { 0x00008304, 0x00000000 },
5567 + { 0x00008308, 0x00000000 },
5568 + { 0x0000830c, 0x00000000 },
5569 + { 0x00008310, 0x00000000 },
5570 + { 0x00008314, 0x00000000 },
5571 + { 0x00008318, 0x00000000 },
5572 + { 0x00008328, 0x00000000 },
5573 + { 0x0000832c, 0x00000007 },
5574 + { 0x00008330, 0x00000302 },
5575 + { 0x00008334, 0x00000e00 },
5576 + { 0x00008338, 0x00000000 },
5577 + { 0x0000833c, 0x00000000 },
5578 + { 0x00008340, 0x000107ff },
5579 + { 0x00008344, 0x00000000 },
5580 + { 0x00009808, 0x00000000 },
5581 + { 0x0000980c, 0xaf268e30 },
5582 + { 0x00009810, 0xfd14e000 },
5583 + { 0x00009814, 0x9c0a9f6b },
5584 + { 0x0000981c, 0x00000000 },
5585 + { 0x0000982c, 0x0000a000 },
5586 + { 0x00009830, 0x00000000 },
5587 + { 0x0000983c, 0x00200400 },
5588 + { 0x00009840, 0x206a01ae },
5589 + { 0x0000984c, 0x0040233c },
5590 + { 0x0000a84c, 0x0040233c },
5591 + { 0x00009854, 0x00000044 },
5592 + { 0x00009900, 0x00000000 },
5593 + { 0x00009904, 0x00000000 },
5594 + { 0x00009908, 0x00000000 },
5595 + { 0x0000990c, 0x00000000 },
5596 + { 0x0000991c, 0x10000fff },
5597 + { 0x00009920, 0x04900000 },
5598 + { 0x0000a920, 0x04900000 },
5599 + { 0x00009928, 0x00000001 },
5600 + { 0x0000992c, 0x00000004 },
5601 + { 0x00009934, 0x1e1f2022 },
5602 + { 0x00009938, 0x0a0b0c0d },
5603 + { 0x0000993c, 0x00000000 },
5604 + { 0x00009948, 0x9280c00a },
5605 + { 0x0000994c, 0x00020028 },
5606 + { 0x00009954, 0xe250a51e },
5607 + { 0x00009958, 0x3388ffff },
5608 + { 0x00009940, 0x00781204 },
5609 + { 0x0000c95c, 0x004b6a8e },
5610 + { 0x0000c968, 0x000003ce },
5611 + { 0x00009970, 0x190fb514 },
5612 + { 0x00009974, 0x00000000 },
5613 + { 0x00009978, 0x00000001 },
5614 + { 0x0000997c, 0x00000000 },
5615 + { 0x00009980, 0x00000000 },
5616 + { 0x00009984, 0x00000000 },
5617 + { 0x00009988, 0x00000000 },
5618 + { 0x0000998c, 0x00000000 },
5619 + { 0x00009990, 0x00000000 },
5620 + { 0x00009994, 0x00000000 },
5621 + { 0x00009998, 0x00000000 },
5622 + { 0x0000999c, 0x00000000 },
5623 + { 0x000099a0, 0x00000000 },
5624 + { 0x000099a4, 0x00000001 },
5625 + { 0x000099a8, 0x201fff00 },
5626 + { 0x000099ac, 0x006f00c4 },
5627 + { 0x000099b0, 0x03051000 },
5628 + { 0x000099b4, 0x00000820 },
5629 + { 0x000099dc, 0x00000000 },
5630 + { 0x000099e0, 0x00000000 },
5631 + { 0x000099e4, 0xaaaaaaaa },
5632 + { 0x000099e8, 0x3c466478 },
5633 + { 0x000099ec, 0x0cc80caa },
5634 + { 0x000099fc, 0x00001042 },
5635 + { 0x0000a210, 0x4080a333 },
5636 + { 0x0000a214, 0x40206c10 },
5637 + { 0x0000a218, 0x009c4060 },
5638 + { 0x0000a220, 0x01834061 },
5639 + { 0x0000a224, 0x00000400 },
5640 + { 0x0000a228, 0x000003b5 },
5641 + { 0x0000a22c, 0x23277200 },
5642 + { 0x0000a234, 0x20202020 },
5643 + { 0x0000a238, 0x20202020 },
5644 + { 0x0000a23c, 0x13c889af },
5645 + { 0x0000a240, 0x38490a20 },
5646 + { 0x0000a244, 0x00007bb6 },
5647 + { 0x0000a248, 0x0fff3ffc },
5648 + { 0x0000a24c, 0x00000001 },
5649 + { 0x0000a250, 0x001da000 },
5650 + { 0x0000a254, 0x00000000 },
5651 + { 0x0000a258, 0x0cdbd380 },
5652 + { 0x0000a25c, 0x0f0f0f01 },
5653 + { 0x0000a260, 0xdfa91f01 },
5654 + { 0x0000a268, 0x00000000 },
5655 + { 0x0000a26c, 0x0ebae9c6 },
5656 + { 0x0000b26c, 0x0ebae9c6 },
5657 + { 0x0000d270, 0x00820820 },
5658 + { 0x0000a278, 0x1ce739ce },
5659 + { 0x0000a27c, 0x050701ce },
5660 + { 0x0000a358, 0x7999aa0f },
5661 + { 0x0000d35c, 0x07ffffef },
5662 + { 0x0000d360, 0x0fffffe7 },
5663 + { 0x0000d364, 0x17ffffe5 },
5664 + { 0x0000d368, 0x1fffffe4 },
5665 + { 0x0000d36c, 0x37ffffe3 },
5666 + { 0x0000d370, 0x3fffffe3 },
5667 + { 0x0000d374, 0x57ffffe3 },
5668 + { 0x0000d378, 0x5fffffe2 },
5669 + { 0x0000d37c, 0x7fffffe2 },
5670 + { 0x0000d380, 0x7f3c7bba },
5671 + { 0x0000d384, 0xf3307ff0 },
5672 + { 0x0000a388, 0x0c000000 },
5673 + { 0x0000a38c, 0x20202020 },
5674 + { 0x0000a390, 0x20202020 },
5675 + { 0x0000a394, 0x1ce739ce },
5676 + { 0x0000a398, 0x000001ce },
5677 + { 0x0000a39c, 0x00000001 },
5678 + { 0x0000a3a0, 0x00000000 },
5679 + { 0x0000a3a4, 0x00000000 },
5680 + { 0x0000a3a8, 0x00000000 },
5681 + { 0x0000a3ac, 0x00000000 },
5682 + { 0x0000a3b0, 0x00000000 },
5683 + { 0x0000a3b4, 0x00000000 },
5684 + { 0x0000a3b8, 0x00000000 },
5685 + { 0x0000a3bc, 0x00000000 },
5686 + { 0x0000a3c0, 0x00000000 },
5687 + { 0x0000a3c4, 0x00000000 },
5688 + { 0x0000a3c8, 0x00000246 },
5689 + { 0x0000a3cc, 0x20202020 },
5690 + { 0x0000a3d0, 0x20202020 },
5691 + { 0x0000a3d4, 0x20202020 },
5692 + { 0x0000a3dc, 0x1ce739ce },
5693 + { 0x0000a3e0, 0x000001ce },
5694 + { 0x0000a3e4, 0x00000000 },
5695 + { 0x0000a3e8, 0x18c43433 },
5696 + { 0x0000a3ec, 0x00f38081 },
5697 + { 0x00007800, 0x00040000 },
5698 + { 0x00007804, 0xdb005012 },
5699 + { 0x00007808, 0x04924914 },
5700 + { 0x0000780c, 0x21084210 },
5701 + { 0x00007810, 0x6d801300 },
5702 + { 0x00007814, 0x0019beff },
5703 + { 0x00007818, 0x07e40000 },
5704 + { 0x0000781c, 0x00492000 },
5705 + { 0x00007820, 0x92492480 },
5706 + { 0x00007824, 0x00040000 },
5707 + { 0x00007828, 0xdb005012 },
5708 + { 0x0000782c, 0x04924914 },
5709 + { 0x00007830, 0x21084210 },
5710 + { 0x00007834, 0x6d801300 },
5711 + { 0x00007838, 0x0019beff },
5712 + { 0x0000783c, 0x07e40000 },
5713 + { 0x00007840, 0x00492000 },
5714 + { 0x00007844, 0x92492480 },
5715 + { 0x00007848, 0x00120000 },
5716 + { 0x00007850, 0x54214514 },
5717 + { 0x00007858, 0x92592692 },
5718 + { 0x00007860, 0x52802000 },
5719 + { 0x00007864, 0x0a8e370e },
5720 + { 0x00007868, 0xc0102850 },
5721 + { 0x0000786c, 0x812d4000 },
5722 + { 0x00007874, 0x001b6db0 },
5723 + { 0x00007878, 0x00376b63 },
5724 + { 0x0000787c, 0x06db6db6 },
5725 + { 0x00007880, 0x006d8000 },
5726 + { 0x00007884, 0xffeffffe },
5727 + { 0x00007888, 0xffeffffe },
5728 + { 0x00007890, 0x00060aeb },
5729 + { 0x00007894, 0x5a108000 },
5730 + { 0x00007898, 0x2a850160 },
5731 +};
5732 +
5733 +/* XXX 9280 2 */
5734 +static const u32 ar9280Modes_9280_2[][6] = {
5735 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
5736 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
5737 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
5738 + { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
5739 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
5740 + { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
5741 + { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
5742 + { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
5743 + { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
5744 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
5745 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
5746 + { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
5747 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
5748 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
5749 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
5750 + { 0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e, 0x206a012e },
5751 + { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
5752 + { 0x00009850, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
5753 + { 0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
5754 + { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
5755 + { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
5756 + { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
5757 + { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
5758 + { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
5759 + { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
5760 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000268, 0x0000000b, 0x00000016 },
5761 + { 0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
5762 + { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010 },
5763 + { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
5764 + { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
5765 + { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
5766 + { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
5767 + { 0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c },
5768 + { 0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00, 0x00000c00 },
5769 + { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
5770 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
5771 + { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
5772 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
5773 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
5774 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
5775 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
5776 + { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 },
5777 + { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
5778 + { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
5779 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
5780 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
5781 + { 0x0000a23c, 0x13c88000, 0x13c88000, 0x13c88001, 0x13c88000, 0x13c88000 },
5782 + { 0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000, 0x0004a000 },
5783 + { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
5784 + { 0x0000a388, 0x0c000000, 0x0c000000, 0x08000000, 0x0c000000, 0x0c000000 },
5785 + { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
5786 + { 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 },
5787 +};
5788 +
5789 +static const u32 ar9280Common_9280_2[][2] = {
5790 + { 0x0000000c, 0x00000000 },
5791 + { 0x00000030, 0x00020015 },
5792 + { 0x00000034, 0x00000005 },
5793 + { 0x00000040, 0x00000000 },
5794 + { 0x00000044, 0x00000008 },
5795 + { 0x00000048, 0x00000008 },
5796 + { 0x0000004c, 0x00000010 },
5797 + { 0x00000050, 0x00000000 },
5798 + { 0x00000054, 0x0000001f },
5799 + { 0x00000800, 0x00000000 },
5800 + { 0x00000804, 0x00000000 },
5801 + { 0x00000808, 0x00000000 },
5802 + { 0x0000080c, 0x00000000 },
5803 + { 0x00000810, 0x00000000 },
5804 + { 0x00000814, 0x00000000 },
5805 + { 0x00000818, 0x00000000 },
5806 + { 0x0000081c, 0x00000000 },
5807 + { 0x00000820, 0x00000000 },
5808 + { 0x00000824, 0x00000000 },
5809 + { 0x00001040, 0x002ffc0f },
5810 + { 0x00001044, 0x002ffc0f },
5811 + { 0x00001048, 0x002ffc0f },
5812 + { 0x0000104c, 0x002ffc0f },
5813 + { 0x00001050, 0x002ffc0f },
5814 + { 0x00001054, 0x002ffc0f },
5815 + { 0x00001058, 0x002ffc0f },
5816 + { 0x0000105c, 0x002ffc0f },
5817 + { 0x00001060, 0x002ffc0f },
5818 + { 0x00001064, 0x002ffc0f },
5819 + { 0x00001230, 0x00000000 },
5820 + { 0x00001270, 0x00000000 },
5821 + { 0x00001038, 0x00000000 },
5822 + { 0x00001078, 0x00000000 },
5823 + { 0x000010b8, 0x00000000 },
5824 + { 0x000010f8, 0x00000000 },
5825 + { 0x00001138, 0x00000000 },
5826 + { 0x00001178, 0x00000000 },
5827 + { 0x000011b8, 0x00000000 },
5828 + { 0x000011f8, 0x00000000 },
5829 + { 0x00001238, 0x00000000 },
5830 + { 0x00001278, 0x00000000 },
5831 + { 0x000012b8, 0x00000000 },
5832 + { 0x000012f8, 0x00000000 },
5833 + { 0x00001338, 0x00000000 },
5834 + { 0x00001378, 0x00000000 },
5835 + { 0x000013b8, 0x00000000 },
5836 + { 0x000013f8, 0x00000000 },
5837 + { 0x00001438, 0x00000000 },
5838 + { 0x00001478, 0x00000000 },
5839 + { 0x000014b8, 0x00000000 },
5840 + { 0x000014f8, 0x00000000 },
5841 + { 0x00001538, 0x00000000 },
5842 + { 0x00001578, 0x00000000 },
5843 + { 0x000015b8, 0x00000000 },
5844 + { 0x000015f8, 0x00000000 },
5845 + { 0x00001638, 0x00000000 },
5846 + { 0x00001678, 0x00000000 },
5847 + { 0x000016b8, 0x00000000 },
5848 + { 0x000016f8, 0x00000000 },
5849 + { 0x00001738, 0x00000000 },
5850 + { 0x00001778, 0x00000000 },
5851 + { 0x000017b8, 0x00000000 },
5852 + { 0x000017f8, 0x00000000 },
5853 + { 0x0000103c, 0x00000000 },
5854 + { 0x0000107c, 0x00000000 },
5855 + { 0x000010bc, 0x00000000 },
5856 + { 0x000010fc, 0x00000000 },
5857 + { 0x0000113c, 0x00000000 },
5858 + { 0x0000117c, 0x00000000 },
5859 + { 0x000011bc, 0x00000000 },
5860 + { 0x000011fc, 0x00000000 },
5861 + { 0x0000123c, 0x00000000 },
5862 + { 0x0000127c, 0x00000000 },
5863 + { 0x000012bc, 0x00000000 },
5864 + { 0x000012fc, 0x00000000 },
5865 + { 0x0000133c, 0x00000000 },
5866 + { 0x0000137c, 0x00000000 },
5867 + { 0x000013bc, 0x00000000 },
5868 + { 0x000013fc, 0x00000000 },
5869 + { 0x0000143c, 0x00000000 },
5870 + { 0x0000147c, 0x00000000 },
5871 + { 0x00004030, 0x00000002 },
5872 + { 0x0000403c, 0x00000002 },
5873 + { 0x00004024, 0x0000001f },
5874 + { 0x00004060, 0x00000000 },
5875 + { 0x00004064, 0x00000000 },
5876 + { 0x00007010, 0x00000033 },
5877 + { 0x00007034, 0x00000002 },
5878 + { 0x00007038, 0x000004c2 },
5879 + { 0x00008004, 0x00000000 },
5880 + { 0x00008008, 0x00000000 },
5881 + { 0x0000800c, 0x00000000 },
5882 + { 0x00008018, 0x00000700 },
5883 + { 0x00008020, 0x00000000 },
5884 + { 0x00008038, 0x00000000 },
5885 + { 0x0000803c, 0x00000000 },
5886 + { 0x00008048, 0x40000000 },
5887 + { 0x00008054, 0x00000000 },
5888 + { 0x00008058, 0x00000000 },
5889 + { 0x0000805c, 0x000fc78f },
5890 + { 0x00008060, 0x0000000f },
5891 + { 0x00008064, 0x00000000 },
5892 + { 0x00008070, 0x00000000 },
5893 + { 0x000080c0, 0x2a80001a },
5894 + { 0x000080c4, 0x05dc01e0 },
5895 + { 0x000080c8, 0x1f402710 },
5896 + { 0x000080cc, 0x01f40000 },
5897 + { 0x000080d0, 0x00001e00 },
5898 + { 0x000080d4, 0x00000000 },
5899 + { 0x000080d8, 0x00400000 },
5900 + { 0x000080e0, 0xffffffff },
5901 + { 0x000080e4, 0x0000ffff },
5902 + { 0x000080e8, 0x003f3f3f },
5903 + { 0x000080ec, 0x00000000 },
5904 + { 0x000080f0, 0x00000000 },
5905 + { 0x000080f4, 0x00000000 },
5906 + { 0x000080f8, 0x00000000 },
5907 + { 0x000080fc, 0x00020000 },
5908 + { 0x00008100, 0x00020000 },
5909 + { 0x00008104, 0x00000001 },
5910 + { 0x00008108, 0x00000052 },
5911 + { 0x0000810c, 0x00000000 },
5912 + { 0x00008110, 0x00000168 },
5913 + { 0x00008118, 0x000100aa },
5914 + { 0x0000811c, 0x00003210 },
5915 + { 0x00008124, 0x00000000 },
5916 + { 0x00008128, 0x00000000 },
5917 + { 0x0000812c, 0x00000000 },
5918 + { 0x00008130, 0x00000000 },
5919 + { 0x00008134, 0x00000000 },
5920 + { 0x00008138, 0x00000000 },
5921 + { 0x0000813c, 0x00000000 },
5922 + { 0x00008144, 0xffffffff },
5923 + { 0x00008168, 0x00000000 },
5924 + { 0x0000816c, 0x00000000 },
5925 + { 0x00008170, 0x32143320 },
5926 + { 0x00008174, 0xfaa4fa50 },
5927 + { 0x00008178, 0x00000100 },
5928 + { 0x0000817c, 0x00000000 },
5929 + { 0x000081c0, 0x00000000 },
5930 + { 0x000081ec, 0x00000000 },
5931 + { 0x000081f0, 0x00000000 },
5932 + { 0x000081f4, 0x00000000 },
5933 + { 0x000081f8, 0x00000000 },
5934 + { 0x000081fc, 0x00000000 },
5935 + { 0x00008200, 0x00000000 },
5936 + { 0x00008204, 0x00000000 },
5937 + { 0x00008208, 0x00000000 },
5938 + { 0x0000820c, 0x00000000 },
5939 + { 0x00008210, 0x00000000 },
5940 + { 0x00008214, 0x00000000 },
5941 + { 0x00008218, 0x00000000 },
5942 + { 0x0000821c, 0x00000000 },
5943 + { 0x00008220, 0x00000000 },
5944 + { 0x00008224, 0x00000000 },
5945 + { 0x00008228, 0x00000000 },
5946 + { 0x0000822c, 0x00000000 },
5947 + { 0x00008230, 0x00000000 },
5948 + { 0x00008234, 0x00000000 },
5949 + { 0x00008238, 0x00000000 },
5950 + { 0x0000823c, 0x00000000 },
5951 + { 0x00008240, 0x00100000 },
5952 + { 0x00008244, 0x0010f400 },
5953 + { 0x00008248, 0x00000100 },
5954 + { 0x0000824c, 0x0001e800 },
5955 + { 0x00008250, 0x00000000 },
5956 + { 0x00008254, 0x00000000 },
5957 + { 0x00008258, 0x00000000 },
5958 + { 0x0000825c, 0x400000ff },
5959 + { 0x00008260, 0x00080922 },
5960 + { 0x00008264, 0xa8a00010 },
5961 + { 0x00008270, 0x00000000 },
5962 + { 0x00008274, 0x40000000 },
5963 + { 0x00008278, 0x003e4180 },
5964 + { 0x0000827c, 0x00000000 },
5965 + { 0x00008284, 0x0000002c },
5966 + { 0x00008288, 0x0000002c },
5967 + { 0x0000828c, 0x00000000 },
5968 + { 0x00008294, 0x00000000 },
5969 + { 0x00008298, 0x00000000 },
5970 + { 0x0000829c, 0x00000000 },
5971 + { 0x00008300, 0x00000040 },
5972 + { 0x00008314, 0x00000000 },
5973 + { 0x00008328, 0x00000000 },
5974 + { 0x0000832c, 0x00000007 },
5975 + { 0x00008330, 0x00000302 },
5976 + { 0x00008334, 0x00000e00 },
5977 + { 0x00008338, 0x00ff0000 },
5978 + { 0x0000833c, 0x00000000 },
5979 + { 0x00008340, 0x000107ff },
5980 + { 0x00008344, 0x00481043 },
5981 + { 0x00009808, 0x00000000 },
5982 + { 0x0000980c, 0xafa68e30 },
5983 + { 0x00009810, 0xfd14e000 },
5984 + { 0x00009814, 0x9c0a9f6b },
5985 + { 0x0000981c, 0x00000000 },
5986 + { 0x0000982c, 0x0000a000 },
5987 + { 0x00009830, 0x00000000 },
5988 + { 0x0000983c, 0x00200400 },
5989 + { 0x0000984c, 0x0040233c },
5990 + { 0x0000a84c, 0x0040233c },
5991 + { 0x00009854, 0x00000044 },
5992 + { 0x00009900, 0x00000000 },
5993 + { 0x00009904, 0x00000000 },
5994 + { 0x00009908, 0x00000000 },
5995 + { 0x0000990c, 0x00000000 },
5996 + { 0x00009910, 0x01002310 },
5997 + { 0x0000991c, 0x10000fff },
5998 + { 0x00009920, 0x04900000 },
5999 + { 0x0000a920, 0x04900000 },
6000 + { 0x00009928, 0x00000001 },
6001 + { 0x0000992c, 0x00000004 },
6002 + { 0x00009934, 0x1e1f2022 },
6003 + { 0x00009938, 0x0a0b0c0d },
6004 + { 0x0000993c, 0x00000000 },
6005 + { 0x00009948, 0x9280c00a },
6006 + { 0x0000994c, 0x00020028 },
6007 + { 0x00009954, 0x5f3ca3de },
6008 + { 0x00009958, 0x2108ecff },
6009 + { 0x00009940, 0x14750604 },
6010 + { 0x0000c95c, 0x004b6a8e },
6011 + { 0x00009970, 0x190fb515 },
6012 + { 0x00009974, 0x00000000 },
6013 + { 0x00009978, 0x00000001 },
6014 + { 0x0000997c, 0x00000000 },
6015 + { 0x00009980, 0x00000000 },
6016 + { 0x00009984, 0x00000000 },
6017 + { 0x00009988, 0x00000000 },
6018 + { 0x0000998c, 0x00000000 },
6019 + { 0x00009990, 0x00000000 },
6020 + { 0x00009994, 0x00000000 },
6021 + { 0x00009998, 0x00000000 },
6022 + { 0x0000999c, 0x00000000 },
6023 + { 0x000099a0, 0x00000000 },
6024 + { 0x000099a4, 0x00000001 },
6025 + { 0x000099a8, 0x201fff00 },
6026 + { 0x000099ac, 0x006f0000 },
6027 + { 0x000099b0, 0x03051000 },
6028 + { 0x000099b4, 0x00000820 },
6029 + { 0x000099dc, 0x00000000 },
6030 + { 0x000099e0, 0x00000000 },
6031 + { 0x000099e4, 0xaaaaaaaa },
6032 + { 0x000099e8, 0x3c466478 },
6033 + { 0x000099ec, 0x0cc80caa },
6034 + { 0x000099f0, 0x00000000 },
6035 + { 0x000099fc, 0x00001042 },
6036 + { 0x0000a208, 0x803e4788 },
6037 + { 0x0000a210, 0x4080a333 },
6038 + { 0x0000a214, 0x40206c10 },
6039 + { 0x0000a218, 0x009c4060 },
6040 + { 0x0000a220, 0x01834061 },
6041 + { 0x0000a224, 0x00000400 },
6042 + { 0x0000a228, 0x000003b5 },
6043 + { 0x0000a22c, 0x233f7180 },
6044 + { 0x0000a234, 0x20202020 },
6045 + { 0x0000a238, 0x20202020 },
6046 + { 0x0000a240, 0x38490a20 },
6047 + { 0x0000a244, 0x00007bb6 },
6048 + { 0x0000a248, 0x0fff3ffc },
6049 + { 0x0000a24c, 0x00000000 },
6050 + { 0x0000a254, 0x00000000 },
6051 + { 0x0000a258, 0x0cdbd380 },
6052 + { 0x0000a25c, 0x0f0f0f01 },
6053 + { 0x0000a260, 0xdfa91f01 },
6054 + { 0x0000a268, 0x00000000 },
6055 + { 0x0000a26c, 0x0e79e5c6 },
6056 + { 0x0000b26c, 0x0e79e5c6 },
6057 + { 0x0000d270, 0x00820820 },
6058 + { 0x0000a278, 0x1ce739ce },
6059 + { 0x0000d35c, 0x07ffffef },
6060 + { 0x0000d360, 0x0fffffe7 },
6061 + { 0x0000d364, 0x17ffffe5 },
6062 + { 0x0000d368, 0x1fffffe4 },
6063 + { 0x0000d36c, 0x37ffffe3 },
6064 + { 0x0000d370, 0x3fffffe3 },
6065 + { 0x0000d374, 0x57ffffe3 },
6066 + { 0x0000d378, 0x5fffffe2 },
6067 + { 0x0000d37c, 0x7fffffe2 },
6068 + { 0x0000d380, 0x7f3c7bba },
6069 + { 0x0000d384, 0xf3307ff0 },
6070 + { 0x0000a38c, 0x20202020 },
6071 + { 0x0000a390, 0x20202020 },
6072 + { 0x0000a394, 0x1ce739ce },
6073 + { 0x0000a398, 0x000001ce },
6074 + { 0x0000a39c, 0x00000001 },
6075 + { 0x0000a3a0, 0x00000000 },
6076 + { 0x0000a3a4, 0x00000000 },
6077 + { 0x0000a3a8, 0x00000000 },
6078 + { 0x0000a3ac, 0x00000000 },
6079 + { 0x0000a3b0, 0x00000000 },
6080 + { 0x0000a3b4, 0x00000000 },
6081 + { 0x0000a3b8, 0x00000000 },
6082 + { 0x0000a3bc, 0x00000000 },
6083 + { 0x0000a3c0, 0x00000000 },
6084 + { 0x0000a3c4, 0x00000000 },
6085 + { 0x0000a3c8, 0x00000246 },
6086 + { 0x0000a3cc, 0x20202020 },
6087 + { 0x0000a3d0, 0x20202020 },
6088 + { 0x0000a3d4, 0x20202020 },
6089 + { 0x0000a3dc, 0x1ce739ce },
6090 + { 0x0000a3e0, 0x000001ce },
6091 + { 0x0000a3e4, 0x00000000 },
6092 + { 0x0000a3e8, 0x18c43433 },
6093 + { 0x0000a3ec, 0x00f70081 },
6094 + { 0x00007800, 0x00040000 },
6095 + { 0x00007804, 0xdb005012 },
6096 + { 0x00007808, 0x04924914 },
6097 + { 0x0000780c, 0x21084210 },
6098 + { 0x00007810, 0x6d801300 },
6099 + { 0x00007818, 0x07e41000 },
6100 + { 0x00007824, 0x00040000 },
6101 + { 0x00007828, 0xdb005012 },
6102 + { 0x0000782c, 0x04924914 },
6103 + { 0x00007830, 0x21084210 },
6104 + { 0x00007834, 0x6d801300 },
6105 + { 0x0000783c, 0x07e40000 },
6106 + { 0x00007848, 0x00100000 },
6107 + { 0x0000784c, 0x773f0567 },
6108 + { 0x00007850, 0x54214514 },
6109 + { 0x00007854, 0x12035828 },
6110 + { 0x00007858, 0x9259269a },
6111 + { 0x00007860, 0x52802000 },
6112 + { 0x00007864, 0x0a8e370e },
6113 + { 0x00007868, 0xc0102850 },
6114 + { 0x0000786c, 0x812d4000 },
6115 + { 0x00007870, 0x807ec400 },
6116 + { 0x00007874, 0x001b6db0 },
6117 + { 0x00007878, 0x00376b63 },
6118 + { 0x0000787c, 0x06db6db6 },
6119 + { 0x00007880, 0x006d8000 },
6120 + { 0x00007884, 0xffeffffe },
6121 + { 0x00007888, 0xffeffffe },
6122 + { 0x0000788c, 0x00010000 },
6123 + { 0x00007890, 0x02060aeb },
6124 + { 0x00007898, 0x2a850160 },
6125 +};
6126 +
6127 +static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
6128 + { 0x00001030, 0x00000268, 0x000004d0 },
6129 + { 0x00001070, 0x0000018c, 0x00000318 },
6130 + { 0x000010b0, 0x00000fd0, 0x00001fa0 },
6131 + { 0x00008014, 0x044c044c, 0x08980898 },
6132 + { 0x0000801c, 0x148ec02b, 0x148ec057 },
6133 + { 0x00008318, 0x000044c0, 0x00008980 },
6134 + { 0x00009820, 0x02020200, 0x02020200 },
6135 + { 0x00009824, 0x01000f0f, 0x01000f0f },
6136 + { 0x00009828, 0x0b020001, 0x0b020001 },
6137 + { 0x00009834, 0x00000f0f, 0x00000f0f },
6138 + { 0x00009844, 0x03721821, 0x03721821 },
6139 + { 0x00009914, 0x00000898, 0x00001130 },
6140 + { 0x00009918, 0x0000000b, 0x00000016 },
6141 +};
6142 +
6143 +static const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = {
6144 + { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
6145 + { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
6146 + { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
6147 + { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
6148 + { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
6149 + { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
6150 + { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
6151 + { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
6152 + { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
6153 + { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
6154 + { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
6155 + { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
6156 + { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
6157 + { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
6158 + { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
6159 + { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
6160 + { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
6161 + { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
6162 + { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
6163 + { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
6164 + { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
6165 + { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
6166 + { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
6167 + { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
6168 + { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
6169 + { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
6170 + { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
6171 + { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
6172 + { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
6173 + { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
6174 + { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
6175 + { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
6176 + { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
6177 + { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
6178 + { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
6179 + { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
6180 + { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
6181 + { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
6182 + { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
6183 + { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
6184 + { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
6185 + { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
6186 + { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
6187 + { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
6188 + { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
6189 + { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
6190 + { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
6191 + { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
6192 + { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b10, 0x00008b10, 0x00008b10 },
6193 + { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b14, 0x00008b14, 0x00008b14 },
6194 + { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b01, 0x00008b01, 0x00008b01 },
6195 + { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b05, 0x00008b05, 0x00008b05 },
6196 + { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b09, 0x00008b09, 0x00008b09 },
6197 + { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008b0d, 0x00008b0d, 0x00008b0d },
6198 + { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008b11, 0x00008b11, 0x00008b11 },
6199 + { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008b15, 0x00008b15, 0x00008b15 },
6200 + { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008b02, 0x00008b02, 0x00008b02 },
6201 + { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008b06, 0x00008b06, 0x00008b06 },
6202 + { 0x00009ae8, 0x0000b780, 0x0000b780, 0x00008b0a, 0x00008b0a, 0x00008b0a },
6203 + { 0x00009aec, 0x0000b784, 0x0000b784, 0x00008b0e, 0x00008b0e, 0x00008b0e },
6204 + { 0x00009af0, 0x0000b788, 0x0000b788, 0x00008b12, 0x00008b12, 0x00008b12 },
6205 + { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00008b16, 0x00008b16, 0x00008b16 },
6206 + { 0x00009af8, 0x0000b790, 0x0000b790, 0x00008b03, 0x00008b03, 0x00008b03 },
6207 + { 0x00009afc, 0x0000b794, 0x0000b794, 0x00008b07, 0x00008b07, 0x00008b07 },
6208 + { 0x00009b00, 0x0000b798, 0x0000b798, 0x00008b0b, 0x00008b0b, 0x00008b0b },
6209 + { 0x00009b04, 0x0000d784, 0x0000d784, 0x00008b0f, 0x00008b0f, 0x00008b0f },
6210 + { 0x00009b08, 0x0000d788, 0x0000d788, 0x00008b13, 0x00008b13, 0x00008b13 },
6211 + { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00008b17, 0x00008b17, 0x00008b17 },
6212 + { 0x00009b10, 0x0000d790, 0x0000d790, 0x00008b23, 0x00008b23, 0x00008b23 },
6213 + { 0x00009b14, 0x0000f780, 0x0000f780, 0x00008b27, 0x00008b27, 0x00008b27 },
6214 + { 0x00009b18, 0x0000f784, 0x0000f784, 0x00008b2b, 0x00008b2b, 0x00008b2b },
6215 + { 0x00009b1c, 0x0000f788, 0x0000f788, 0x00008b2f, 0x00008b2f, 0x00008b2f },
6216 + { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x00008b33, 0x00008b33, 0x00008b33 },
6217 + { 0x00009b24, 0x0000f790, 0x0000f790, 0x00008b37, 0x00008b37, 0x00008b37 },
6218 + { 0x00009b28, 0x0000f794, 0x0000f794, 0x00008b43, 0x00008b43, 0x00008b43 },
6219 + { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x00008b47, 0x00008b47, 0x00008b47 },
6220 + { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00008b4b, 0x00008b4b, 0x00008b4b },
6221 + { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00008b4f, 0x00008b4f, 0x00008b4f },
6222 + { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00008b53, 0x00008b53, 0x00008b53 },
6223 + { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00008b57, 0x00008b57, 0x00008b57 },
6224 + { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6225 + { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6226 + { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6227 + { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6228 + { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6229 + { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6230 + { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6231 + { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6232 + { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6233 + { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6234 + { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6235 + { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6236 + { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6237 + { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6238 + { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6239 + { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6240 + { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6241 + { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6242 + { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6243 + { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6244 + { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6245 + { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6246 + { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6247 + { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6248 + { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6249 + { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6250 + { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6251 + { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6252 + { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6253 + { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6254 + { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6255 + { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6256 + { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6257 + { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6258 + { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6259 + { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6260 + { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6261 + { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6262 + { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6263 + { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6264 + { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6265 + { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6266 + { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6267 + { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6268 + { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6269 + { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6270 + { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6271 + { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6272 + { 0x00009848, 0x00001066, 0x00001066, 0x00001050, 0x00001050, 0x00001050 },
6273 + { 0x0000a848, 0x00001066, 0x00001066, 0x00001050, 0x00001050, 0x00001050 },
6274 +};
6275 +
6276 +static const u32 ar9280Modes_original_rxgain_9280_2[][6] = {
6277 + { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
6278 + { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
6279 + { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
6280 + { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
6281 + { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
6282 + { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
6283 + { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
6284 + { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
6285 + { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
6286 + { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
6287 + { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
6288 + { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
6289 + { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
6290 + { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
6291 + { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
6292 + { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
6293 + { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
6294 + { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
6295 + { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
6296 + { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
6297 + { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
6298 + { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
6299 + { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
6300 + { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
6301 + { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
6302 + { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
6303 + { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
6304 + { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
6305 + { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
6306 + { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
6307 + { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
6308 + { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
6309 + { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
6310 + { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
6311 + { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
6312 + { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
6313 + { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
6314 + { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
6315 + { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
6316 + { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
6317 + { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
6318 + { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
6319 + { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
6320 + { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
6321 + { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
6322 + { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
6323 + { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
6324 + { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
6325 + { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
6326 + { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
6327 + { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
6328 + { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
6329 + { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
6330 + { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
6331 + { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
6332 + { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
6333 + { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
6334 + { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
6335 + { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c },
6336 + { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 },
6337 + { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 },
6338 + { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 },
6339 + { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 },
6340 + { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 },
6341 + { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 },
6342 + { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 },
6343 + { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 },
6344 + { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 },
6345 + { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 },
6346 + { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 },
6347 + { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 },
6348 + { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c },
6349 + { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 },
6350 + { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 },
6351 + { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 },
6352 + { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 },
6353 + { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 },
6354 + { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 },
6355 + { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 },
6356 + { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 },
6357 + { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad },
6358 + { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 },
6359 + { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 },
6360 + { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 },
6361 + { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 },
6362 + { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 },
6363 + { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 },
6364 + { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 },
6365 + { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 },
6366 + { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 },
6367 + { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca },
6368 + { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce },
6369 + { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 },
6370 + { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 },
6371 + { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 },
6372 + { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 },
6373 + { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb },
6374 + { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf },
6375 + { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 },
6376 + { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db },
6377 + { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db },
6378 + { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db },
6379 + { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6380 + { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6381 + { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6382 + { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6383 + { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6384 + { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6385 + { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6386 + { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6387 + { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6388 + { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6389 + { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6390 + { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6391 + { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6392 + { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6393 + { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6394 + { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6395 + { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6396 + { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6397 + { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6398 + { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6399 + { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6400 + { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6401 + { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6402 + { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6403 + { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6404 + { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6405 + { 0x00009848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 },
6406 + { 0x0000a848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 },
6407 +};
6408 +
6409 +static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
6410 + { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
6411 + { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
6412 + { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
6413 + { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
6414 + { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
6415 + { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
6416 + { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
6417 + { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
6418 + { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
6419 + { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
6420 + { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
6421 + { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
6422 + { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
6423 + { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
6424 + { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
6425 + { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
6426 + { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
6427 + { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
6428 + { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
6429 + { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
6430 + { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
6431 + { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
6432 + { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
6433 + { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
6434 + { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
6435 + { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
6436 + { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
6437 + { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
6438 + { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
6439 + { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
6440 + { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
6441 + { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
6442 + { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
6443 + { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
6444 + { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
6445 + { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
6446 + { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
6447 + { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
6448 + { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
6449 + { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
6450 + { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
6451 + { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
6452 + { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
6453 + { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
6454 + { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
6455 + { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
6456 + { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
6457 + { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
6458 + { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
6459 + { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
6460 + { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
6461 + { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
6462 + { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
6463 + { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
6464 + { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
6465 + { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
6466 + { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
6467 + { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
6468 + { 0x00009ae8, 0x0000b780, 0x0000b780, 0x00009310, 0x00009310, 0x00009310 },
6469 + { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009314, 0x00009314, 0x00009314 },
6470 + { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009320, 0x00009320, 0x00009320 },
6471 + { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009324, 0x00009324, 0x00009324 },
6472 + { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009328, 0x00009328, 0x00009328 },
6473 + { 0x00009afc, 0x0000b794, 0x0000b794, 0x0000932c, 0x0000932c, 0x0000932c },
6474 + { 0x00009b00, 0x0000b798, 0x0000b798, 0x00009330, 0x00009330, 0x00009330 },
6475 + { 0x00009b04, 0x0000d784, 0x0000d784, 0x00009334, 0x00009334, 0x00009334 },
6476 + { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009321, 0x00009321, 0x00009321 },
6477 + { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009325, 0x00009325, 0x00009325 },
6478 + { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009329, 0x00009329, 0x00009329 },
6479 + { 0x00009b14, 0x0000f780, 0x0000f780, 0x0000932d, 0x0000932d, 0x0000932d },
6480 + { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009331, 0x00009331, 0x00009331 },
6481 + { 0x00009b1c, 0x0000f788, 0x0000f788, 0x00009335, 0x00009335, 0x00009335 },
6482 + { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x00009322, 0x00009322, 0x00009322 },
6483 + { 0x00009b24, 0x0000f790, 0x0000f790, 0x00009326, 0x00009326, 0x00009326 },
6484 + { 0x00009b28, 0x0000f794, 0x0000f794, 0x0000932a, 0x0000932a, 0x0000932a },
6485 + { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x0000932e, 0x0000932e, 0x0000932e },
6486 + { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00009332, 0x00009332, 0x00009332 },
6487 + { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00009336, 0x00009336, 0x00009336 },
6488 + { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00009323, 0x00009323, 0x00009323 },
6489 + { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00009327, 0x00009327, 0x00009327 },
6490 + { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x0000932b, 0x0000932b, 0x0000932b },
6491 + { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x0000932f, 0x0000932f, 0x0000932f },
6492 + { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00009333, 0x00009333, 0x00009333 },
6493 + { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00009337, 0x00009337, 0x00009337 },
6494 + { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00009343, 0x00009343, 0x00009343 },
6495 + { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00009347, 0x00009347, 0x00009347 },
6496 + { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x0000934b, 0x0000934b, 0x0000934b },
6497 + { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x0000934f, 0x0000934f, 0x0000934f },
6498 + { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00009353, 0x00009353, 0x00009353 },
6499 + { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00009357, 0x00009357, 0x00009357 },
6500 + { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x0000935b, 0x0000935b, 0x0000935b },
6501 + { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x0000935b, 0x0000935b, 0x0000935b },
6502 + { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x0000935b, 0x0000935b, 0x0000935b },
6503 + { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x0000935b, 0x0000935b, 0x0000935b },
6504 + { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x0000935b, 0x0000935b, 0x0000935b },
6505 + { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x0000935b, 0x0000935b, 0x0000935b },
6506 + { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x0000935b, 0x0000935b, 0x0000935b },
6507 + { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x0000935b, 0x0000935b, 0x0000935b },
6508 + { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x0000935b, 0x0000935b, 0x0000935b },
6509 + { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x0000935b, 0x0000935b, 0x0000935b },
6510 + { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x0000935b, 0x0000935b, 0x0000935b },
6511 + { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x0000935b, 0x0000935b, 0x0000935b },
6512 + { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6513 + { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6514 + { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6515 + { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6516 + { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6517 + { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6518 + { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6519 + { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6520 + { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6521 + { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6522 + { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6523 + { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6524 + { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6525 + { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6526 + { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6527 + { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6528 + { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6529 + { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6530 + { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6531 + { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6532 + { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6533 + { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6534 + { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6535 + { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6536 + { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6537 + { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6538 + { 0x00009848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a },
6539 + { 0x0000a848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a },
6540 +};
6541 +
6542 +static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
6543 + { 0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
6544 + { 0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce },
6545 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6546 + { 0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002, 0x00004002 },
6547 + { 0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008, 0x00007008 },
6548 + { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000c010, 0x0000c010, 0x0000c010 },
6549 + { 0x0000a310, 0x0000e012, 0x0000e012, 0x00010012, 0x00010012, 0x00010012 },
6550 + { 0x0000a314, 0x00011014, 0x00011014, 0x00013014, 0x00013014, 0x00013014 },
6551 + { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001820a, 0x0001820a, 0x0001820a },
6552 + { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001b211, 0x0001b211, 0x0001b211 },
6553 + { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
6554 + { 0x0000a324, 0x00021092, 0x00021092, 0x00022411, 0x00022411, 0x00022411 },
6555 + { 0x0000a328, 0x0002510a, 0x0002510a, 0x00025413, 0x00025413, 0x00025413 },
6556 + { 0x0000a32c, 0x0002910c, 0x0002910c, 0x00029811, 0x00029811, 0x00029811 },
6557 + { 0x0000a330, 0x0002c18b, 0x0002c18b, 0x0002c813, 0x0002c813, 0x0002c813 },
6558 + { 0x0000a334, 0x0002f1cc, 0x0002f1cc, 0x00030a14, 0x00030a14, 0x00030a14 },
6559 + { 0x0000a338, 0x000321eb, 0x000321eb, 0x00035a50, 0x00035a50, 0x00035a50 },
6560 + { 0x0000a33c, 0x000341ec, 0x000341ec, 0x00039c4c, 0x00039c4c, 0x00039c4c },
6561 + { 0x0000a340, 0x000341ec, 0x000341ec, 0x0003de8a, 0x0003de8a, 0x0003de8a },
6562 + { 0x0000a344, 0x000341ec, 0x000341ec, 0x00042e92, 0x00042e92, 0x00042e92 },
6563 + { 0x0000a348, 0x000341ec, 0x000341ec, 0x00046ed2, 0x00046ed2, 0x00046ed2 },
6564 + { 0x0000a34c, 0x000341ec, 0x000341ec, 0x0004bed5, 0x0004bed5, 0x0004bed5 },
6565 + { 0x0000a350, 0x000341ec, 0x000341ec, 0x0004ff54, 0x0004ff54, 0x0004ff54 },
6566 + { 0x0000a354, 0x000341ec, 0x000341ec, 0x00055fd5, 0x00055fd5, 0x00055fd5 },
6567 + { 0x00007814, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff },
6568 + { 0x00007838, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff },
6569 + { 0x0000781c, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 },
6570 + { 0x00007840, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 },
6571 + { 0x00007820, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
6572 + { 0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
6573 +};
6574 +
6575 +static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
6576 + { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
6577 + { 0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce },
6578 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6579 + { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
6580 + { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
6581 + { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b },
6582 + { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 },
6583 + { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 },
6584 + { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a },
6585 + { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 },
6586 + { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
6587 + { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b },
6588 + { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 },
6589 + { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 },
6590 + { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a },
6591 + { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 },
6592 + { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b },
6593 + { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 },
6594 + { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 },
6595 + { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a },
6596 + { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 },
6597 + { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a },
6598 + { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 },
6599 + { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 },
6600 + { 0x00007814, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff },
6601 + { 0x00007838, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff },
6602 + { 0x0000781c, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 },
6603 + { 0x00007840, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 },
6604 + { 0x00007820, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
6605 + { 0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
6606 +};
6607 +
6608 +static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
6609 + {0x00004040, 0x9248fd00 },
6610 + {0x00004040, 0x24924924 },
6611 + {0x00004040, 0xa8000019 },
6612 + {0x00004040, 0x13160820 },
6613 + {0x00004040, 0xe5980560 },
6614 + {0x00004040, 0xc01dcffc },
6615 + {0x00004040, 0x1aaabe41 },
6616 + {0x00004040, 0xbe105554 },
6617 + {0x00004040, 0x00043007 },
6618 + {0x00004044, 0x00000000 },
6619 +};
6620 +
6621 +static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
6622 + {0x00004040, 0x9248fd00 },
6623 + {0x00004040, 0x24924924 },
6624 + {0x00004040, 0xa8000019 },
6625 + {0x00004040, 0x13160820 },
6626 + {0x00004040, 0xe5980560 },
6627 + {0x00004040, 0xc01dcffd },
6628 + {0x00004040, 0x1aaabe41 },
6629 + {0x00004040, 0xbe105554 },
6630 + {0x00004040, 0x00043007 },
6631 + {0x00004044, 0x00000000 },
6632 +};
6633 +
6634 +/* AR9285 Revsion 10*/
6635 +static const u_int32_t ar9285Modes_9285[][6] = {
6636 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
6637 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
6638 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
6639 + { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
6640 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
6641 + { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
6642 + { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
6643 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
6644 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
6645 + { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
6646 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
6647 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
6648 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
6649 + { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
6650 + { 0x00009844, 0x0372161e, 0x0372161e, 0x03720020, 0x03720020, 0x037216a0 },
6651 + { 0x00009848, 0x00001066, 0x00001066, 0x0000004e, 0x0000004e, 0x00001059 },
6652 + { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
6653 + { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
6654 + { 0x0000985c, 0x3139605e, 0x3139605e, 0x3136605e, 0x3136605e, 0x3139605e },
6655 + { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
6656 + { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
6657 + { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
6658 + { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
6659 + { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
6660 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
6661 + { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
6662 + { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1020, 0xdfbc1020, 0xdfbc1010 },
6663 + { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6664 + { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6665 + { 0x000099b8, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c },
6666 + { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
6667 + { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
6668 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
6669 + { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
6670 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
6671 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
6672 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6673 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6674 + { 0x00009a00, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
6675 + { 0x00009a04, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
6676 + { 0x00009a08, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
6677 + { 0x00009a0c, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
6678 + { 0x00009a10, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
6679 + { 0x00009a14, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
6680 + { 0x00009a18, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
6681 + { 0x00009a1c, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
6682 + { 0x00009a20, 0x00000000, 0x00000000, 0x00068114, 0x00068114, 0x00000000 },
6683 + { 0x00009a24, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
6684 + { 0x00009a28, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
6685 + { 0x00009a2c, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
6686 + { 0x00009a30, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
6687 + { 0x00009a34, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
6688 + { 0x00009a38, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
6689 + { 0x00009a3c, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
6690 + { 0x00009a40, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
6691 + { 0x00009a44, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
6692 + { 0x00009a48, 0x00000000, 0x00000000, 0x00068284, 0x00068284, 0x00000000 },
6693 + { 0x00009a4c, 0x00000000, 0x00000000, 0x00068288, 0x00068288, 0x00000000 },
6694 + { 0x00009a50, 0x00000000, 0x00000000, 0x00068220, 0x00068220, 0x00000000 },
6695 + { 0x00009a54, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
6696 + { 0x00009a58, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
6697 + { 0x00009a5c, 0x00000000, 0x00000000, 0x00068304, 0x00068304, 0x00000000 },
6698 + { 0x00009a60, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
6699 + { 0x00009a64, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
6700 + { 0x00009a68, 0x00000000, 0x00000000, 0x00068380, 0x00068380, 0x00000000 },
6701 + { 0x00009a6c, 0x00000000, 0x00000000, 0x00068384, 0x00068384, 0x00000000 },
6702 + { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
6703 + { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
6704 + { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
6705 + { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
6706 + { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
6707 + { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
6708 + { 0x00009a88, 0x00000000, 0x00000000, 0x00068b04, 0x00068b04, 0x00000000 },
6709 + { 0x00009a8c, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
6710 + { 0x00009a90, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
6711 + { 0x00009a94, 0x00000000, 0x00000000, 0x00068b0c, 0x00068b0c, 0x00000000 },
6712 + { 0x00009a98, 0x00000000, 0x00000000, 0x00068b80, 0x00068b80, 0x00000000 },
6713 + { 0x00009a9c, 0x00000000, 0x00000000, 0x00068b84, 0x00068b84, 0x00000000 },
6714 + { 0x00009aa0, 0x00000000, 0x00000000, 0x00068b88, 0x00068b88, 0x00000000 },
6715 + { 0x00009aa4, 0x00000000, 0x00000000, 0x00068b8c, 0x00068b8c, 0x00000000 },
6716 + { 0x00009aa8, 0x00000000, 0x00000000, 0x000b8b90, 0x000b8b90, 0x00000000 },
6717 + { 0x00009aac, 0x00000000, 0x00000000, 0x000b8f80, 0x000b8f80, 0x00000000 },
6718 + { 0x00009ab0, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
6719 + { 0x00009ab4, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
6720 + { 0x00009ab8, 0x00000000, 0x00000000, 0x000b8f8c, 0x000b8f8c, 0x00000000 },
6721 + { 0x00009abc, 0x00000000, 0x00000000, 0x000b8f90, 0x000b8f90, 0x00000000 },
6722 + { 0x00009ac0, 0x00000000, 0x00000000, 0x000bb30c, 0x000bb30c, 0x00000000 },
6723 + { 0x00009ac4, 0x00000000, 0x00000000, 0x000bb310, 0x000bb310, 0x00000000 },
6724 + { 0x00009ac8, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
6725 + { 0x00009acc, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
6726 + { 0x00009ad0, 0x00000000, 0x00000000, 0x000bb324, 0x000bb324, 0x00000000 },
6727 + { 0x00009ad4, 0x00000000, 0x00000000, 0x000bb704, 0x000bb704, 0x00000000 },
6728 + { 0x00009ad8, 0x00000000, 0x00000000, 0x000f96a4, 0x000f96a4, 0x00000000 },
6729 + { 0x00009adc, 0x00000000, 0x00000000, 0x000f96a8, 0x000f96a8, 0x00000000 },
6730 + { 0x00009ae0, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
6731 + { 0x00009ae4, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
6732 + { 0x00009ae8, 0x00000000, 0x00000000, 0x000f9720, 0x000f9720, 0x00000000 },
6733 + { 0x00009aec, 0x00000000, 0x00000000, 0x000f9724, 0x000f9724, 0x00000000 },
6734 + { 0x00009af0, 0x00000000, 0x00000000, 0x000f9728, 0x000f9728, 0x00000000 },
6735 + { 0x00009af4, 0x00000000, 0x00000000, 0x000f972c, 0x000f972c, 0x00000000 },
6736 + { 0x00009af8, 0x00000000, 0x00000000, 0x000f97a0, 0x000f97a0, 0x00000000 },
6737 + { 0x00009afc, 0x00000000, 0x00000000, 0x000f97a4, 0x000f97a4, 0x00000000 },
6738 + { 0x00009b00, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
6739 + { 0x00009b04, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
6740 + { 0x00009b08, 0x00000000, 0x00000000, 0x000fb7b4, 0x000fb7b4, 0x00000000 },
6741 + { 0x00009b0c, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
6742 + { 0x00009b10, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
6743 + { 0x00009b14, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
6744 + { 0x00009b18, 0x00000000, 0x00000000, 0x000fb7ad, 0x000fb7ad, 0x00000000 },
6745 + { 0x00009b1c, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
6746 + { 0x00009b20, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
6747 + { 0x00009b24, 0x00000000, 0x00000000, 0x000fb7b9, 0x000fb7b9, 0x00000000 },
6748 + { 0x00009b28, 0x00000000, 0x00000000, 0x000fb7c5, 0x000fb7c5, 0x00000000 },
6749 + { 0x00009b2c, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
6750 + { 0x00009b30, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
6751 + { 0x00009b34, 0x00000000, 0x00000000, 0x000fb7d5, 0x000fb7d5, 0x00000000 },
6752 + { 0x00009b38, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
6753 + { 0x00009b3c, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
6754 + { 0x00009b40, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
6755 + { 0x00009b44, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
6756 + { 0x00009b48, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
6757 + { 0x00009b4c, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
6758 + { 0x00009b50, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
6759 + { 0x00009b54, 0x00000000, 0x00000000, 0x000fb7c7, 0x000fb7c7, 0x00000000 },
6760 + { 0x00009b58, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
6761 + { 0x00009b5c, 0x00000000, 0x00000000, 0x000fb7cf, 0x000fb7cf, 0x00000000 },
6762 + { 0x00009b60, 0x00000000, 0x00000000, 0x000fb7d7, 0x000fb7d7, 0x00000000 },
6763 + { 0x00009b64, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6764 + { 0x00009b68, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6765 + { 0x00009b6c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6766 + { 0x00009b70, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6767 + { 0x00009b74, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6768 + { 0x00009b78, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6769 + { 0x00009b7c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6770 + { 0x00009b80, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6771 + { 0x00009b84, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6772 + { 0x00009b88, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6773 + { 0x00009b8c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6774 + { 0x00009b90, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6775 + { 0x00009b94, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6776 + { 0x00009b98, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6777 + { 0x00009b9c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6778 + { 0x00009ba0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6779 + { 0x00009ba4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6780 + { 0x00009ba8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6781 + { 0x00009bac, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6782 + { 0x00009bb0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6783 + { 0x00009bb4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6784 + { 0x00009bb8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6785 + { 0x00009bbc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6786 + { 0x00009bc0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6787 + { 0x00009bc4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6788 + { 0x00009bc8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6789 + { 0x00009bcc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6790 + { 0x00009bd0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6791 + { 0x00009bd4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6792 + { 0x00009bd8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6793 + { 0x00009bdc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6794 + { 0x00009be0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6795 + { 0x00009be4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6796 + { 0x00009be8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6797 + { 0x00009bec, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6798 + { 0x00009bf0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6799 + { 0x00009bf4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6800 + { 0x00009bf8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6801 + { 0x00009bfc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6802 + { 0x0000aa00, 0x00000000, 0x00000000, 0x0006801c, 0x0006801c, 0x00000000 },
6803 + { 0x0000aa04, 0x00000000, 0x00000000, 0x00068080, 0x00068080, 0x00000000 },
6804 + { 0x0000aa08, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
6805 + { 0x0000aa0c, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
6806 + { 0x0000aa10, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
6807 + { 0x0000aa14, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
6808 + { 0x0000aa18, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
6809 + { 0x0000aa1c, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
6810 + { 0x0000aa20, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
6811 + { 0x0000aa24, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
6812 + { 0x0000aa28, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
6813 + { 0x0000aa2c, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
6814 + { 0x0000aa30, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
6815 + { 0x0000aa34, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
6816 + { 0x0000aa38, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
6817 + { 0x0000aa3c, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
6818 + { 0x0000aa40, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
6819 + { 0x0000aa44, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
6820 + { 0x0000aa48, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
6821 + { 0x0000aa4c, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
6822 + { 0x0000aa50, 0x00000000, 0x00000000, 0x000681ac, 0x000681ac, 0x00000000 },
6823 + { 0x0000aa54, 0x00000000, 0x00000000, 0x0006821c, 0x0006821c, 0x00000000 },
6824 + { 0x0000aa58, 0x00000000, 0x00000000, 0x00068224, 0x00068224, 0x00000000 },
6825 + { 0x0000aa5c, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
6826 + { 0x0000aa60, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
6827 + { 0x0000aa64, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
6828 + { 0x0000aa68, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
6829 + { 0x0000aa6c, 0x00000000, 0x00000000, 0x00068310, 0x00068310, 0x00000000 },
6830 + { 0x0000aa70, 0x00000000, 0x00000000, 0x00068788, 0x00068788, 0x00000000 },
6831 + { 0x0000aa74, 0x00000000, 0x00000000, 0x0006878c, 0x0006878c, 0x00000000 },
6832 + { 0x0000aa78, 0x00000000, 0x00000000, 0x00068790, 0x00068790, 0x00000000 },
6833 + { 0x0000aa7c, 0x00000000, 0x00000000, 0x00068794, 0x00068794, 0x00000000 },
6834 + { 0x0000aa80, 0x00000000, 0x00000000, 0x00068798, 0x00068798, 0x00000000 },
6835 + { 0x0000aa84, 0x00000000, 0x00000000, 0x0006879c, 0x0006879c, 0x00000000 },
6836 + { 0x0000aa88, 0x00000000, 0x00000000, 0x00068b89, 0x00068b89, 0x00000000 },
6837 + { 0x0000aa8c, 0x00000000, 0x00000000, 0x00068b8d, 0x00068b8d, 0x00000000 },
6838 + { 0x0000aa90, 0x00000000, 0x00000000, 0x00068b91, 0x00068b91, 0x00000000 },
6839 + { 0x0000aa94, 0x00000000, 0x00000000, 0x00068b95, 0x00068b95, 0x00000000 },
6840 + { 0x0000aa98, 0x00000000, 0x00000000, 0x00068b99, 0x00068b99, 0x00000000 },
6841 + { 0x0000aa9c, 0x00000000, 0x00000000, 0x00068ba5, 0x00068ba5, 0x00000000 },
6842 + { 0x0000aaa0, 0x00000000, 0x00000000, 0x00068ba9, 0x00068ba9, 0x00000000 },
6843 + { 0x0000aaa4, 0x00000000, 0x00000000, 0x00068bad, 0x00068bad, 0x00000000 },
6844 + { 0x0000aaa8, 0x00000000, 0x00000000, 0x000b8b0c, 0x000b8b0c, 0x00000000 },
6845 + { 0x0000aaac, 0x00000000, 0x00000000, 0x000b8f10, 0x000b8f10, 0x00000000 },
6846 + { 0x0000aab0, 0x00000000, 0x00000000, 0x000b8f14, 0x000b8f14, 0x00000000 },
6847 + { 0x0000aab4, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
6848 + { 0x0000aab8, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
6849 + { 0x0000aabc, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
6850 + { 0x0000aac0, 0x00000000, 0x00000000, 0x000bb380, 0x000bb380, 0x00000000 },
6851 + { 0x0000aac4, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
6852 + { 0x0000aac8, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
6853 + { 0x0000aacc, 0x00000000, 0x00000000, 0x000bb38c, 0x000bb38c, 0x00000000 },
6854 + { 0x0000aad0, 0x00000000, 0x00000000, 0x000bb394, 0x000bb394, 0x00000000 },
6855 + { 0x0000aad4, 0x00000000, 0x00000000, 0x000bb798, 0x000bb798, 0x00000000 },
6856 + { 0x0000aad8, 0x00000000, 0x00000000, 0x000f970c, 0x000f970c, 0x00000000 },
6857 + { 0x0000aadc, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
6858 + { 0x0000aae0, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
6859 + { 0x0000aae4, 0x00000000, 0x00000000, 0x000f9718, 0x000f9718, 0x00000000 },
6860 + { 0x0000aae8, 0x00000000, 0x00000000, 0x000f9705, 0x000f9705, 0x00000000 },
6861 + { 0x0000aaec, 0x00000000, 0x00000000, 0x000f9709, 0x000f9709, 0x00000000 },
6862 + { 0x0000aaf0, 0x00000000, 0x00000000, 0x000f970d, 0x000f970d, 0x00000000 },
6863 + { 0x0000aaf4, 0x00000000, 0x00000000, 0x000f9711, 0x000f9711, 0x00000000 },
6864 + { 0x0000aaf8, 0x00000000, 0x00000000, 0x000f9715, 0x000f9715, 0x00000000 },
6865 + { 0x0000aafc, 0x00000000, 0x00000000, 0x000f9719, 0x000f9719, 0x00000000 },
6866 + { 0x0000ab00, 0x00000000, 0x00000000, 0x000fb7a4, 0x000fb7a4, 0x00000000 },
6867 + { 0x0000ab04, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
6868 + { 0x0000ab08, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
6869 + { 0x0000ab0c, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
6870 + { 0x0000ab10, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
6871 + { 0x0000ab14, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
6872 + { 0x0000ab18, 0x00000000, 0x00000000, 0x000fb7bc, 0x000fb7bc, 0x00000000 },
6873 + { 0x0000ab1c, 0x00000000, 0x00000000, 0x000fb7a1, 0x000fb7a1, 0x00000000 },
6874 + { 0x0000ab20, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
6875 + { 0x0000ab24, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
6876 + { 0x0000ab28, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
6877 + { 0x0000ab2c, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
6878 + { 0x0000ab30, 0x00000000, 0x00000000, 0x000fb7bd, 0x000fb7bd, 0x00000000 },
6879 + { 0x0000ab34, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
6880 + { 0x0000ab38, 0x00000000, 0x00000000, 0x000fb7cd, 0x000fb7cd, 0x00000000 },
6881 + { 0x0000ab3c, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
6882 + { 0x0000ab40, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
6883 + { 0x0000ab44, 0x00000000, 0x00000000, 0x000fb7c2, 0x000fb7c2, 0x00000000 },
6884 + { 0x0000ab48, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
6885 + { 0x0000ab4c, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
6886 + { 0x0000ab50, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
6887 + { 0x0000ab54, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
6888 + { 0x0000ab58, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
6889 + { 0x0000ab5c, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
6890 + { 0x0000ab60, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
6891 + { 0x0000ab64, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6892 + { 0x0000ab68, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6893 + { 0x0000ab6c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6894 + { 0x0000ab70, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6895 + { 0x0000ab74, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6896 + { 0x0000ab78, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6897 + { 0x0000ab7c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6898 + { 0x0000ab80, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6899 + { 0x0000ab84, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6900 + { 0x0000ab88, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6901 + { 0x0000ab8c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6902 + { 0x0000ab90, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6903 + { 0x0000ab94, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6904 + { 0x0000ab98, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6905 + { 0x0000ab9c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6906 + { 0x0000aba0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6907 + { 0x0000aba4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6908 + { 0x0000aba8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6909 + { 0x0000abac, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6910 + { 0x0000abb0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6911 + { 0x0000abb4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6912 + { 0x0000abb8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6913 + { 0x0000abbc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6914 + { 0x0000abc0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6915 + { 0x0000abc4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6916 + { 0x0000abc8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6917 + { 0x0000abcc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6918 + { 0x0000abd0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6919 + { 0x0000abd4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6920 + { 0x0000abd8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6921 + { 0x0000abdc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6922 + { 0x0000abe0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6923 + { 0x0000abe4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6924 + { 0x0000abe8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6925 + { 0x0000abec, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6926 + { 0x0000abf0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6927 + { 0x0000abf4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6928 + { 0x0000abf8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6929 + { 0x0000abfc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6930 + { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
6931 + { 0x0000a20c, 0x00000014, 0x00000014, 0x00000000, 0x00000000, 0x0001f000 },
6932 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
6933 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
6934 + { 0x0000a250, 0x001ff000, 0x001ff000, 0x001ca000, 0x001ca000, 0x001da000 },
6935 + { 0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652, 0x0a82a652 },
6936 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6937 + { 0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
6938 + { 0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408, 0x00000000 },
6939 + { 0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a, 0x00000000 },
6940 + { 0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818, 0x00000000 },
6941 + { 0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858, 0x00000000 },
6942 + { 0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859, 0x00000000 },
6943 + { 0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b, 0x00000000 },
6944 + { 0x0000a320, 0x00000000, 0x00000000, 0x0002c89a, 0x0002c89a, 0x00000000 },
6945 + { 0x0000a324, 0x00000000, 0x00000000, 0x0002e89b, 0x0002e89b, 0x00000000 },
6946 + { 0x0000a328, 0x00000000, 0x00000000, 0x0003089c, 0x0003089c, 0x00000000 },
6947 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0003289d, 0x0003289d, 0x00000000 },
6948 + { 0x0000a330, 0x00000000, 0x00000000, 0x0003489e, 0x0003489e, 0x00000000 },
6949 + { 0x0000a334, 0x00000000, 0x00000000, 0x000388de, 0x000388de, 0x00000000 },
6950 + { 0x0000a338, 0x00000000, 0x00000000, 0x0003b91e, 0x0003b91e, 0x00000000 },
6951 + { 0x0000a33c, 0x00000000, 0x00000000, 0x0003d95e, 0x0003d95e, 0x00000000 },
6952 + { 0x0000a340, 0x00000000, 0x00000000, 0x000419df, 0x000419df, 0x00000000 },
6953 + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
6954 + { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
6955 +};
6956 +
6957 +static const u_int32_t ar9285Common_9285[][2] = {
6958 + { 0x0000000c, 0x00000000 },
6959 + { 0x00000030, 0x00020045 },
6960 + { 0x00000034, 0x00000005 },
6961 + { 0x00000040, 0x00000000 },
6962 + { 0x00000044, 0x00000008 },
6963 + { 0x00000048, 0x00000008 },
6964 + { 0x0000004c, 0x00000010 },
6965 + { 0x00000050, 0x00000000 },
6966 + { 0x00000054, 0x0000001f },
6967 + { 0x00000800, 0x00000000 },
6968 + { 0x00000804, 0x00000000 },
6969 + { 0x00000808, 0x00000000 },
6970 + { 0x0000080c, 0x00000000 },
6971 + { 0x00000810, 0x00000000 },
6972 + { 0x00000814, 0x00000000 },
6973 + { 0x00000818, 0x00000000 },
6974 + { 0x0000081c, 0x00000000 },
6975 + { 0x00000820, 0x00000000 },
6976 + { 0x00000824, 0x00000000 },
6977 + { 0x00001040, 0x002ffc0f },
6978 + { 0x00001044, 0x002ffc0f },
6979 + { 0x00001048, 0x002ffc0f },
6980 + { 0x0000104c, 0x002ffc0f },
6981 + { 0x00001050, 0x002ffc0f },
6982 + { 0x00001054, 0x002ffc0f },
6983 + { 0x00001058, 0x002ffc0f },
6984 + { 0x0000105c, 0x002ffc0f },
6985 + { 0x00001060, 0x002ffc0f },
6986 + { 0x00001064, 0x002ffc0f },
6987 + { 0x00001230, 0x00000000 },
6988 + { 0x00001270, 0x00000000 },
6989 + { 0x00001038, 0x00000000 },
6990 + { 0x00001078, 0x00000000 },
6991 + { 0x000010b8, 0x00000000 },
6992 + { 0x000010f8, 0x00000000 },
6993 + { 0x00001138, 0x00000000 },
6994 + { 0x00001178, 0x00000000 },
6995 + { 0x000011b8, 0x00000000 },
6996 + { 0x000011f8, 0x00000000 },
6997 + { 0x00001238, 0x00000000 },
6998 + { 0x00001278, 0x00000000 },
6999 + { 0x000012b8, 0x00000000 },
7000 + { 0x000012f8, 0x00000000 },
7001 + { 0x00001338, 0x00000000 },
7002 + { 0x00001378, 0x00000000 },
7003 + { 0x000013b8, 0x00000000 },
7004 + { 0x000013f8, 0x00000000 },
7005 + { 0x00001438, 0x00000000 },
7006 + { 0x00001478, 0x00000000 },
7007 + { 0x000014b8, 0x00000000 },
7008 + { 0x000014f8, 0x00000000 },
7009 + { 0x00001538, 0x00000000 },
7010 + { 0x00001578, 0x00000000 },
7011 + { 0x000015b8, 0x00000000 },
7012 + { 0x000015f8, 0x00000000 },
7013 + { 0x00001638, 0x00000000 },
7014 + { 0x00001678, 0x00000000 },
7015 + { 0x000016b8, 0x00000000 },
7016 + { 0x000016f8, 0x00000000 },
7017 + { 0x00001738, 0x00000000 },
7018 + { 0x00001778, 0x00000000 },
7019 + { 0x000017b8, 0x00000000 },
7020 + { 0x000017f8, 0x00000000 },
7021 + { 0x0000103c, 0x00000000 },
7022 + { 0x0000107c, 0x00000000 },
7023 + { 0x000010bc, 0x00000000 },
7024 + { 0x000010fc, 0x00000000 },
7025 + { 0x0000113c, 0x00000000 },
7026 + { 0x0000117c, 0x00000000 },
7027 + { 0x000011bc, 0x00000000 },
7028 + { 0x000011fc, 0x00000000 },
7029 + { 0x0000123c, 0x00000000 },
7030 + { 0x0000127c, 0x00000000 },
7031 + { 0x000012bc, 0x00000000 },
7032 + { 0x000012fc, 0x00000000 },
7033 + { 0x0000133c, 0x00000000 },
7034 + { 0x0000137c, 0x00000000 },
7035 + { 0x000013bc, 0x00000000 },
7036 + { 0x000013fc, 0x00000000 },
7037 + { 0x0000143c, 0x00000000 },
7038 + { 0x0000147c, 0x00000000 },
7039 + { 0x00004030, 0x00000002 },
7040 + { 0x0000403c, 0x00000002 },
7041 + { 0x00004024, 0x0000001f },
7042 + { 0x00004060, 0x00000000 },
7043 + { 0x00004064, 0x00000000 },
7044 + { 0x00007010, 0x00000031 },
7045 + { 0x00007034, 0x00000002 },
7046 + { 0x00007038, 0x000004c2 },
7047 + { 0x00008004, 0x00000000 },
7048 + { 0x00008008, 0x00000000 },
7049 + { 0x0000800c, 0x00000000 },
7050 + { 0x00008018, 0x00000700 },
7051 + { 0x00008020, 0x00000000 },
7052 + { 0x00008038, 0x00000000 },
7053 + { 0x0000803c, 0x00000000 },
7054 + { 0x00008048, 0x00000000 },
7055 + { 0x00008054, 0x00000000 },
7056 + { 0x00008058, 0x00000000 },
7057 + { 0x0000805c, 0x000fc78f },
7058 + { 0x00008060, 0x0000000f },
7059 + { 0x00008064, 0x00000000 },
7060 + { 0x00008070, 0x00000000 },
7061 + { 0x000080c0, 0x2a80001a },
7062 + { 0x000080c4, 0x05dc01e0 },
7063 + { 0x000080c8, 0x1f402710 },
7064 + { 0x000080cc, 0x01f40000 },
7065 + { 0x000080d0, 0x00001e00 },
7066 + { 0x000080d4, 0x00000000 },
7067 + { 0x000080d8, 0x00400000 },
7068 + { 0x000080e0, 0xffffffff },
7069 + { 0x000080e4, 0x0000ffff },
7070 + { 0x000080e8, 0x003f3f3f },
7071 + { 0x000080ec, 0x00000000 },
7072 + { 0x000080f0, 0x00000000 },
7073 + { 0x000080f4, 0x00000000 },
7074 + { 0x000080f8, 0x00000000 },
7075 + { 0x000080fc, 0x00020000 },
7076 + { 0x00008100, 0x00020000 },
7077 + { 0x00008104, 0x00000001 },
7078 + { 0x00008108, 0x00000052 },
7079 + { 0x0000810c, 0x00000000 },
7080 + { 0x00008110, 0x00000168 },
7081 + { 0x00008118, 0x000100aa },
7082 + { 0x0000811c, 0x00003210 },
7083 + { 0x00008120, 0x08f04800 },
7084 + { 0x00008124, 0x00000000 },
7085 + { 0x00008128, 0x00000000 },
7086 + { 0x0000812c, 0x00000000 },
7087 + { 0x00008130, 0x00000000 },
7088 + { 0x00008134, 0x00000000 },
7089 + { 0x00008138, 0x00000000 },
7090 + { 0x0000813c, 0x00000000 },
7091 + { 0x00008144, 0x00000000 },
7092 + { 0x00008168, 0x00000000 },
7093 + { 0x0000816c, 0x00000000 },
7094 + { 0x00008170, 0x32143320 },
7095 + { 0x00008174, 0xfaa4fa50 },
7096 + { 0x00008178, 0x00000100 },
7097 + { 0x0000817c, 0x00000000 },
7098 + { 0x000081c0, 0x00000000 },
7099 + { 0x000081d0, 0x00003210 },
7100 + { 0x000081ec, 0x00000000 },
7101 + { 0x000081f0, 0x00000000 },
7102 + { 0x000081f4, 0x00000000 },
7103 + { 0x000081f8, 0x00000000 },
7104 + { 0x000081fc, 0x00000000 },
7105 + { 0x00008200, 0x00000000 },
7106 + { 0x00008204, 0x00000000 },
7107 + { 0x00008208, 0x00000000 },
7108 + { 0x0000820c, 0x00000000 },
7109 + { 0x00008210, 0x00000000 },
7110 + { 0x00008214, 0x00000000 },
7111 + { 0x00008218, 0x00000000 },
7112 + { 0x0000821c, 0x00000000 },
7113 + { 0x00008220, 0x00000000 },
7114 + { 0x00008224, 0x00000000 },
7115 + { 0x00008228, 0x00000000 },
7116 + { 0x0000822c, 0x00000000 },
7117 + { 0x00008230, 0x00000000 },
7118 + { 0x00008234, 0x00000000 },
7119 + { 0x00008238, 0x00000000 },
7120 + { 0x0000823c, 0x00000000 },
7121 + { 0x00008240, 0x00100000 },
7122 + { 0x00008244, 0x0010f400 },
7123 + { 0x00008248, 0x00000100 },
7124 + { 0x0000824c, 0x0001e800 },
7125 + { 0x00008250, 0x00000000 },
7126 + { 0x00008254, 0x00000000 },
7127 + { 0x00008258, 0x00000000 },
7128 + { 0x0000825c, 0x400000ff },
7129 + { 0x00008260, 0x00080922 },
7130 + { 0x00008264, 0xa8a00010 },
7131 + { 0x00008270, 0x00000000 },
7132 + { 0x00008274, 0x40000000 },
7133 + { 0x00008278, 0x003e4180 },
7134 + { 0x0000827c, 0x00000000 },
7135 + { 0x00008284, 0x0000002c },
7136 + { 0x00008288, 0x0000002c },
7137 + { 0x0000828c, 0x00000000 },
7138 + { 0x00008294, 0x00000000 },
7139 + { 0x00008298, 0x00000000 },
7140 + { 0x0000829c, 0x00000000 },
7141 + { 0x00008300, 0x00000040 },
7142 + { 0x00008314, 0x00000000 },
7143 + { 0x00008328, 0x00000000 },
7144 + { 0x0000832c, 0x00000001 },
7145 + { 0x00008330, 0x00000302 },
7146 + { 0x00008334, 0x00000e00 },
7147 + { 0x00008338, 0x00000000 },
7148 + { 0x0000833c, 0x00000000 },
7149 + { 0x00008340, 0x00010380 },
7150 + { 0x00008344, 0x00481043 },
7151 + { 0x00009808, 0x00000000 },
7152 + { 0x0000980c, 0xafe68e30 },
7153 + { 0x00009810, 0xfd14e000 },
7154 + { 0x00009814, 0x9c0a9f6b },
7155 + { 0x0000981c, 0x00000000 },
7156 + { 0x0000982c, 0x0000a000 },
7157 + { 0x00009830, 0x00000000 },
7158 + { 0x0000983c, 0x00200400 },
7159 + { 0x0000984c, 0x0040233c },
7160 + { 0x00009854, 0x00000044 },
7161 + { 0x00009900, 0x00000000 },
7162 + { 0x00009904, 0x00000000 },
7163 + { 0x00009908, 0x00000000 },
7164 + { 0x0000990c, 0x00000000 },
7165 + { 0x00009910, 0x01002310 },
7166 + { 0x0000991c, 0x10000fff },
7167 + { 0x00009920, 0x04900000 },
7168 + { 0x00009928, 0x00000001 },
7169 + { 0x0000992c, 0x00000004 },
7170 + { 0x00009934, 0x1e1f2022 },
7171 + { 0x00009938, 0x0a0b0c0d },
7172 + { 0x0000993c, 0x00000000 },
7173 + { 0x00009940, 0x14750604 },
7174 + { 0x00009948, 0x9280c00a },
7175 + { 0x0000994c, 0x00020028 },
7176 + { 0x00009954, 0x5f3ca3de },
7177 + { 0x00009958, 0x2108ecff },
7178 + { 0x00009968, 0x000003ce },
7179 + { 0x00009970, 0x1927b515 },
7180 + { 0x00009974, 0x00000000 },
7181 + { 0x00009978, 0x00000001 },
7182 + { 0x0000997c, 0x00000000 },
7183 + { 0x00009980, 0x00000000 },
7184 + { 0x00009984, 0x00000000 },
7185 + { 0x00009988, 0x00000000 },
7186 + { 0x0000998c, 0x00000000 },
7187 + { 0x00009990, 0x00000000 },
7188 + { 0x00009994, 0x00000000 },
7189 + { 0x00009998, 0x00000000 },
7190 + { 0x0000999c, 0x00000000 },
7191 + { 0x000099a0, 0x00000000 },
7192 + { 0x000099a4, 0x00000001 },
7193 + { 0x000099a8, 0x201fff00 },
7194 + { 0x000099ac, 0x2def0a00 },
7195 + { 0x000099b0, 0x03051000 },
7196 + { 0x000099b4, 0x00000820 },
7197 + { 0x000099dc, 0x00000000 },
7198 + { 0x000099e0, 0x00000000 },
7199 + { 0x000099e4, 0xaaaaaaaa },
7200 + { 0x000099e8, 0x3c466478 },
7201 + { 0x000099ec, 0x0cc80caa },
7202 + { 0x000099f0, 0x00000000 },
7203 + { 0x0000a208, 0x803e6788 },
7204 + { 0x0000a210, 0x4080a333 },
7205 + { 0x0000a214, 0x00206c10 },
7206 + { 0x0000a218, 0x009c4060 },
7207 + { 0x0000a220, 0x01834061 },
7208 + { 0x0000a224, 0x00000400 },
7209 + { 0x0000a228, 0x000003b5 },
7210 + { 0x0000a22c, 0x00000000 },
7211 + { 0x0000a234, 0x20202020 },
7212 + { 0x0000a238, 0x20202020 },
7213 + { 0x0000a244, 0x00000000 },
7214 + { 0x0000a248, 0xfffffffc },
7215 + { 0x0000a24c, 0x00000000 },
7216 + { 0x0000a254, 0x00000000 },
7217 + { 0x0000a258, 0x0ccb5380 },
7218 + { 0x0000a25c, 0x15151501 },
7219 + { 0x0000a260, 0xdfa90f01 },
7220 + { 0x0000a268, 0x00000000 },
7221 + { 0x0000a26c, 0x0ebae9e6 },
7222 + { 0x0000d270, 0x0d820820 },
7223 + { 0x0000a278, 0x39ce739c },
7224 + { 0x0000a27c, 0x050e039c },
7225 + { 0x0000d35c, 0x07ffffef },
7226 + { 0x0000d360, 0x0fffffe7 },
7227 + { 0x0000d364, 0x17ffffe5 },
7228 + { 0x0000d368, 0x1fffffe4 },
7229 + { 0x0000d36c, 0x37ffffe3 },
7230 + { 0x0000d370, 0x3fffffe3 },
7231 + { 0x0000d374, 0x57ffffe3 },
7232 + { 0x0000d378, 0x5fffffe2 },
7233 + { 0x0000d37c, 0x7fffffe2 },
7234 + { 0x0000d380, 0x7f3c7bba },
7235 + { 0x0000d384, 0xf3307ff0 },
7236 + { 0x0000a388, 0x0c000000 },
7237 + { 0x0000a38c, 0x20202020 },
7238 + { 0x0000a390, 0x20202020 },
7239 + { 0x0000a394, 0x39ce739c },
7240 + { 0x0000a398, 0x0000039c },
7241 + { 0x0000a39c, 0x00000001 },
7242 + { 0x0000a3a0, 0x00000000 },
7243 + { 0x0000a3a4, 0x00000000 },
7244 + { 0x0000a3a8, 0x00000000 },
7245 + { 0x0000a3ac, 0x00000000 },
7246 + { 0x0000a3b0, 0x00000000 },
7247 + { 0x0000a3b4, 0x00000000 },
7248 + { 0x0000a3b8, 0x00000000 },
7249 + { 0x0000a3bc, 0x00000000 },
7250 + { 0x0000a3c0, 0x00000000 },
7251 + { 0x0000a3c4, 0x00000000 },
7252 + { 0x0000a3cc, 0x20202020 },
7253 + { 0x0000a3d0, 0x20202020 },
7254 + { 0x0000a3d4, 0x20202020 },
7255 + { 0x0000a3dc, 0x39ce739c },
7256 + { 0x0000a3e0, 0x0000039c },
7257 + { 0x0000a3e4, 0x00000000 },
7258 + { 0x0000a3e8, 0x18c43433 },
7259 + { 0x0000a3ec, 0x00f70081 },
7260 + { 0x00007800, 0x00140000 },
7261 + { 0x00007804, 0x0e4548d8 },
7262 + { 0x00007808, 0x54214514 },
7263 + { 0x0000780c, 0x02025820 },
7264 + { 0x00007810, 0x71c0d388 },
7265 + { 0x00007814, 0x924934a8 },
7266 + { 0x0000781c, 0x00000000 },
7267 + { 0x00007820, 0x00000c04 },
7268 + { 0x00007824, 0x00d86fff },
7269 + { 0x00007828, 0x26d2491b },
7270 + { 0x0000782c, 0x6e36d97b },
7271 + { 0x00007830, 0xedb6d96c },
7272 + { 0x00007834, 0x71400086 },
7273 + { 0x00007838, 0xfac68800 },
7274 + { 0x0000783c, 0x0001fffe },
7275 + { 0x00007840, 0xffeb1a20 },
7276 + { 0x00007844, 0x000c0db6 },
7277 + { 0x00007848, 0x6db61b6f },
7278 + { 0x0000784c, 0x6d9b66db },
7279 + { 0x00007850, 0x6d8c6dba },
7280 + { 0x00007854, 0x00040000 },
7281 + { 0x00007858, 0xdb003012 },
7282 + { 0x0000785c, 0x04924914 },
7283 + { 0x00007860, 0x21084210 },
7284 + { 0x00007864, 0xf7d7ffde },
7285 + { 0x00007868, 0xc2034080 },
7286 + { 0x0000786c, 0x48609eb4 },
7287 + { 0x00007870, 0x10142c00 },
7288 +};
7289 +
7290 +static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
7291 + {0x00004040, 0x9248fd00 },
7292 + {0x00004040, 0x24924924 },
7293 + {0x00004040, 0xa8000019 },
7294 + {0x00004040, 0x13160820 },
7295 + {0x00004040, 0xe5980560 },
7296 + {0x00004040, 0xc01dcffd },
7297 + {0x00004040, 0x1aaabe41 },
7298 + {0x00004040, 0xbe105554 },
7299 + {0x00004040, 0x00043007 },
7300 + {0x00004044, 0x00000000 },
7301 +};
7302 +
7303 +static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285[][2] = {
7304 + {0x00004040, 0x9248fd00 },
7305 + {0x00004040, 0x24924924 },
7306 + {0x00004040, 0xa8000019 },
7307 + {0x00004040, 0x13160820 },
7308 + {0x00004040, 0xe5980560 },
7309 + {0x00004040, 0xc01dcffc },
7310 + {0x00004040, 0x1aaabe41 },
7311 + {0x00004040, 0xbe105554 },
7312 + {0x00004040, 0x00043007 },
7313 + {0x00004044, 0x00000000 },
7314 +};
7315 +
7316 +/* AR9285 v1_2 PCI Register Writes. Created: 04/13/09 */
7317 +static const u_int32_t ar9285Modes_9285_1_2[][6] = {
7318 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
7319 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
7320 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
7321 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
7322 + { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
7323 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
7324 + { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
7325 + { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
7326 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
7327 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
7328 + { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
7329 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
7330 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
7331 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
7332 + { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
7333 + { 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
7334 + { 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
7335 + { 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
7336 + { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
7337 + { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
7338 + { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
7339 + { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
7340 + { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
7341 + { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
7342 + { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
7343 + { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
7344 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
7345 + { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
7346 + { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
7347 + { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
7348 + { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
7349 + { 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
7350 + { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
7351 + { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
7352 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
7353 + { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
7354 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
7355 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
7356 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
7357 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
7358 + { 0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
7359 + { 0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
7360 + { 0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
7361 + { 0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
7362 + { 0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
7363 + { 0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
7364 + { 0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
7365 + { 0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
7366 + { 0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
7367 + { 0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
7368 + { 0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
7369 + { 0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
7370 + { 0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
7371 + { 0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
7372 + { 0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
7373 + { 0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
7374 + { 0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
7375 + { 0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
7376 + { 0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
7377 + { 0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
7378 + { 0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
7379 + { 0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
7380 + { 0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
7381 + { 0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
7382 + { 0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
7383 + { 0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
7384 + { 0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
7385 + { 0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
7386 + { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
7387 + { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
7388 + { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
7389 + { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
7390 + { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
7391 + { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
7392 + { 0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
7393 + { 0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
7394 + { 0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
7395 + { 0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
7396 + { 0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
7397 + { 0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
7398 + { 0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
7399 + { 0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
7400 + { 0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
7401 + { 0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
7402 + { 0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
7403 + { 0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
7404 + { 0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
7405 + { 0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
7406 + { 0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
7407 + { 0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
7408 + { 0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
7409 + { 0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
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7617 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
7618 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
7619 + { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
7620 + { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
7621 +};
7622 +
7623 +static const u_int32_t ar9285Common_9285_1_2[][2] = {
7624 + { 0x0000000c, 0x00000000 },
7625 + { 0x00000030, 0x00020045 },
7626 + { 0x00000034, 0x00000005 },
7627 + { 0x00000040, 0x00000000 },
7628 + { 0x00000044, 0x00000008 },
7629 + { 0x00000048, 0x00000008 },
7630 + { 0x0000004c, 0x00000010 },
7631 + { 0x00000050, 0x00000000 },
7632 + { 0x00000054, 0x0000001f },
7633 + { 0x00000800, 0x00000000 },
7634 + { 0x00000804, 0x00000000 },
7635 + { 0x00000808, 0x00000000 },
7636 + { 0x0000080c, 0x00000000 },
7637 + { 0x00000810, 0x00000000 },
7638 + { 0x00000814, 0x00000000 },
7639 + { 0x00000818, 0x00000000 },
7640 + { 0x0000081c, 0x00000000 },
7641 + { 0x00000820, 0x00000000 },
7642 + { 0x00000824, 0x00000000 },
7643 + { 0x00001040, 0x002ffc0f },
7644 + { 0x00001044, 0x002ffc0f },
7645 + { 0x00001048, 0x002ffc0f },
7646 + { 0x0000104c, 0x002ffc0f },
7647 + { 0x00001050, 0x002ffc0f },
7648 + { 0x00001054, 0x002ffc0f },
7649 + { 0x00001058, 0x002ffc0f },
7650 + { 0x0000105c, 0x002ffc0f },
7651 + { 0x00001060, 0x002ffc0f },
7652 + { 0x00001064, 0x002ffc0f },
7653 + { 0x00001230, 0x00000000 },
7654 + { 0x00001270, 0x00000000 },
7655 + { 0x00001038, 0x00000000 },
7656 + { 0x00001078, 0x00000000 },
7657 + { 0x000010b8, 0x00000000 },
7658 + { 0x000010f8, 0x00000000 },
7659 + { 0x00001138, 0x00000000 },
7660 + { 0x00001178, 0x00000000 },
7661 + { 0x000011b8, 0x00000000 },
7662 + { 0x000011f8, 0x00000000 },
7663 + { 0x00001238, 0x00000000 },
7664 + { 0x00001278, 0x00000000 },
7665 + { 0x000012b8, 0x00000000 },
7666 + { 0x000012f8, 0x00000000 },
7667 + { 0x00001338, 0x00000000 },
7668 + { 0x00001378, 0x00000000 },
7669 + { 0x000013b8, 0x00000000 },
7670 + { 0x000013f8, 0x00000000 },
7671 + { 0x00001438, 0x00000000 },
7672 + { 0x00001478, 0x00000000 },
7673 + { 0x000014b8, 0x00000000 },
7674 + { 0x000014f8, 0x00000000 },
7675 + { 0x00001538, 0x00000000 },
7676 + { 0x00001578, 0x00000000 },
7677 + { 0x000015b8, 0x00000000 },
7678 + { 0x000015f8, 0x00000000 },
7679 + { 0x00001638, 0x00000000 },
7680 + { 0x00001678, 0x00000000 },
7681 + { 0x000016b8, 0x00000000 },
7682 + { 0x000016f8, 0x00000000 },
7683 + { 0x00001738, 0x00000000 },
7684 + { 0x00001778, 0x00000000 },
7685 + { 0x000017b8, 0x00000000 },
7686 + { 0x000017f8, 0x00000000 },
7687 + { 0x0000103c, 0x00000000 },
7688 + { 0x0000107c, 0x00000000 },
7689 + { 0x000010bc, 0x00000000 },
7690 + { 0x000010fc, 0x00000000 },
7691 + { 0x0000113c, 0x00000000 },
7692 + { 0x0000117c, 0x00000000 },
7693 + { 0x000011bc, 0x00000000 },
7694 + { 0x000011fc, 0x00000000 },
7695 + { 0x0000123c, 0x00000000 },
7696 + { 0x0000127c, 0x00000000 },
7697 + { 0x000012bc, 0x00000000 },
7698 + { 0x000012fc, 0x00000000 },
7699 + { 0x0000133c, 0x00000000 },
7700 + { 0x0000137c, 0x00000000 },
7701 + { 0x000013bc, 0x00000000 },
7702 + { 0x000013fc, 0x00000000 },
7703 + { 0x0000143c, 0x00000000 },
7704 + { 0x0000147c, 0x00000000 },
7705 + { 0x00004030, 0x00000002 },
7706 + { 0x0000403c, 0x00000002 },
7707 + { 0x00004024, 0x0000001f },
7708 + { 0x00004060, 0x00000000 },
7709 + { 0x00004064, 0x00000000 },
7710 + { 0x00007010, 0x00000031 },
7711 + { 0x00007034, 0x00000002 },
7712 + { 0x00007038, 0x000004c2 },
7713 + { 0x00008004, 0x00000000 },
7714 + { 0x00008008, 0x00000000 },
7715 + { 0x0000800c, 0x00000000 },
7716 + { 0x00008018, 0x00000700 },
7717 + { 0x00008020, 0x00000000 },
7718 + { 0x00008038, 0x00000000 },
7719 + { 0x0000803c, 0x00000000 },
7720 + { 0x00008048, 0x00000000 },
7721 + { 0x00008054, 0x00000000 },
7722 + { 0x00008058, 0x00000000 },
7723 + { 0x0000805c, 0x000fc78f },
7724 + { 0x00008060, 0x0000000f },
7725 + { 0x00008064, 0x00000000 },
7726 + { 0x00008070, 0x00000000 },
7727 + { 0x000080c0, 0x2a80001a },
7728 + { 0x000080c4, 0x05dc01e0 },
7729 + { 0x000080c8, 0x1f402710 },
7730 + { 0x000080cc, 0x01f40000 },
7731 + { 0x000080d0, 0x00001e00 },
7732 + { 0x000080d4, 0x00000000 },
7733 + { 0x000080d8, 0x00400000 },
7734 + { 0x000080e0, 0xffffffff },
7735 + { 0x000080e4, 0x0000ffff },
7736 + { 0x000080e8, 0x003f3f3f },
7737 + { 0x000080ec, 0x00000000 },
7738 + { 0x000080f0, 0x00000000 },
7739 + { 0x000080f4, 0x00000000 },
7740 + { 0x000080f8, 0x00000000 },
7741 + { 0x000080fc, 0x00020000 },
7742 + { 0x00008100, 0x00020000 },
7743 + { 0x00008104, 0x00000001 },
7744 + { 0x00008108, 0x00000052 },
7745 + { 0x0000810c, 0x00000000 },
7746 + { 0x00008110, 0x00000168 },
7747 + { 0x00008118, 0x000100aa },
7748 + { 0x0000811c, 0x00003210 },
7749 + { 0x00008120, 0x08f04810 },
7750 + { 0x00008124, 0x00000000 },
7751 + { 0x00008128, 0x00000000 },
7752 + { 0x0000812c, 0x00000000 },
7753 + { 0x00008130, 0x00000000 },
7754 + { 0x00008134, 0x00000000 },
7755 + { 0x00008138, 0x00000000 },
7756 + { 0x0000813c, 0x00000000 },
7757 + { 0x00008144, 0xffffffff },
7758 + { 0x00008168, 0x00000000 },
7759 + { 0x0000816c, 0x00000000 },
7760 + { 0x00008170, 0x32143320 },
7761 + { 0x00008174, 0xfaa4fa50 },
7762 + { 0x00008178, 0x00000100 },
7763 + { 0x0000817c, 0x00000000 },
7764 + { 0x000081c0, 0x00000000 },
7765 + { 0x000081d0, 0x0000320a },
7766 + { 0x000081ec, 0x00000000 },
7767 + { 0x000081f0, 0x00000000 },
7768 + { 0x000081f4, 0x00000000 },
7769 + { 0x000081f8, 0x00000000 },
7770 + { 0x000081fc, 0x00000000 },
7771 + { 0x00008200, 0x00000000 },
7772 + { 0x00008204, 0x00000000 },
7773 + { 0x00008208, 0x00000000 },
7774 + { 0x0000820c, 0x00000000 },
7775 + { 0x00008210, 0x00000000 },
7776 + { 0x00008214, 0x00000000 },
7777 + { 0x00008218, 0x00000000 },
7778 + { 0x0000821c, 0x00000000 },
7779 + { 0x00008220, 0x00000000 },
7780 + { 0x00008224, 0x00000000 },
7781 + { 0x00008228, 0x00000000 },
7782 + { 0x0000822c, 0x00000000 },
7783 + { 0x00008230, 0x00000000 },
7784 + { 0x00008234, 0x00000000 },
7785 + { 0x00008238, 0x00000000 },
7786 + { 0x0000823c, 0x00000000 },
7787 + { 0x00008240, 0x00100000 },
7788 + { 0x00008244, 0x0010f400 },
7789 + { 0x00008248, 0x00000100 },
7790 + { 0x0000824c, 0x0001e800 },
7791 + { 0x00008250, 0x00000000 },
7792 + { 0x00008254, 0x00000000 },
7793 + { 0x00008258, 0x00000000 },
7794 + { 0x0000825c, 0x400000ff },
7795 + { 0x00008260, 0x00080922 },
7796 + { 0x00008264, 0x88a00010 },
7797 + { 0x00008270, 0x00000000 },
7798 + { 0x00008274, 0x40000000 },
7799 + { 0x00008278, 0x003e4180 },
7800 + { 0x0000827c, 0x00000000 },
7801 + { 0x00008284, 0x0000002c },
7802 + { 0x00008288, 0x0000002c },
7803 + { 0x0000828c, 0x00000000 },
7804 + { 0x00008294, 0x00000000 },
7805 + { 0x00008298, 0x00000000 },
7806 + { 0x0000829c, 0x00000000 },
7807 + { 0x00008300, 0x00000040 },
7808 + { 0x00008314, 0x00000000 },
7809 + { 0x00008328, 0x00000000 },
7810 + { 0x0000832c, 0x00000001 },
7811 + { 0x00008330, 0x00000302 },
7812 + { 0x00008334, 0x00000e00 },
7813 + { 0x00008338, 0x00ff0000 },
7814 + { 0x0000833c, 0x00000000 },
7815 + { 0x00008340, 0x00010380 },
7816 + { 0x00008344, 0x00481043 },
7817 + { 0x00009808, 0x00000000 },
7818 + { 0x0000980c, 0xafe68e30 },
7819 + { 0x00009810, 0xfd14e000 },
7820 + { 0x00009814, 0x9c0a9f6b },
7821 + { 0x0000981c, 0x00000000 },
7822 + { 0x0000982c, 0x0000a000 },
7823 + { 0x00009830, 0x00000000 },
7824 + { 0x0000983c, 0x00200400 },
7825 + { 0x0000984c, 0x0040233c },
7826 + { 0x00009854, 0x00000044 },
7827 + { 0x00009900, 0x00000000 },
7828 + { 0x00009904, 0x00000000 },
7829 + { 0x00009908, 0x00000000 },
7830 + { 0x0000990c, 0x00000000 },
7831 + { 0x00009910, 0x01002310 },
7832 + { 0x0000991c, 0x10000fff },
7833 + { 0x00009920, 0x04900000 },
7834 + { 0x00009928, 0x00000001 },
7835 + { 0x0000992c, 0x00000004 },
7836 + { 0x00009934, 0x1e1f2022 },
7837 + { 0x00009938, 0x0a0b0c0d },
7838 + { 0x0000993c, 0x00000000 },
7839 + { 0x00009940, 0x14750604 },
7840 + { 0x00009948, 0x9280c00a },
7841 + { 0x0000994c, 0x00020028 },
7842 + { 0x00009954, 0x5f3ca3de },
7843 + { 0x00009958, 0x2108ecff },
7844 + { 0x00009968, 0x000003ce },
7845 + { 0x00009970, 0x192bb514 },
7846 + { 0x00009974, 0x00000000 },
7847 + { 0x00009978, 0x00000001 },
7848 + { 0x0000997c, 0x00000000 },
7849 + { 0x00009980, 0x00000000 },
7850 + { 0x00009984, 0x00000000 },
7851 + { 0x00009988, 0x00000000 },
7852 + { 0x0000998c, 0x00000000 },
7853 + { 0x00009990, 0x00000000 },
7854 + { 0x00009994, 0x00000000 },
7855 + { 0x00009998, 0x00000000 },
7856 + { 0x0000999c, 0x00000000 },
7857 + { 0x000099a0, 0x00000000 },
7858 + { 0x000099a4, 0x00000001 },
7859 + { 0x000099a8, 0x201fff00 },
7860 + { 0x000099ac, 0x2def0400 },
7861 + { 0x000099b0, 0x03051000 },
7862 + { 0x000099b4, 0x00000820 },
7863 + { 0x000099dc, 0x00000000 },
7864 + { 0x000099e0, 0x00000000 },
7865 + { 0x000099e4, 0xaaaaaaaa },
7866 + { 0x000099e8, 0x3c466478 },
7867 + { 0x000099ec, 0x0cc80caa },
7868 + { 0x000099f0, 0x00000000 },
7869 + { 0x0000a208, 0x803e68c8 },
7870 + { 0x0000a210, 0x4080a333 },
7871 + { 0x0000a214, 0x00206c10 },
7872 + { 0x0000a218, 0x009c4060 },
7873 + { 0x0000a220, 0x01834061 },
7874 + { 0x0000a224, 0x00000400 },
7875 + { 0x0000a228, 0x000003b5 },
7876 + { 0x0000a22c, 0x00000000 },
7877 + { 0x0000a234, 0x20202020 },
7878 + { 0x0000a238, 0x20202020 },
7879 + { 0x0000a244, 0x00000000 },
7880 + { 0x0000a248, 0xfffffffc },
7881 + { 0x0000a24c, 0x00000000 },
7882 + { 0x0000a254, 0x00000000 },
7883 + { 0x0000a258, 0x0ccb5380 },
7884 + { 0x0000a25c, 0x15151501 },
7885 + { 0x0000a260, 0xdfa90f01 },
7886 + { 0x0000a268, 0x00000000 },
7887 + { 0x0000a26c, 0x0ebae9e6 },
7888 + { 0x0000d270, 0x0d820820 },
7889 + { 0x0000d35c, 0x07ffffef },
7890 + { 0x0000d360, 0x0fffffe7 },
7891 + { 0x0000d364, 0x17ffffe5 },
7892 + { 0x0000d368, 0x1fffffe4 },
7893 + { 0x0000d36c, 0x37ffffe3 },
7894 + { 0x0000d370, 0x3fffffe3 },
7895 + { 0x0000d374, 0x57ffffe3 },
7896 + { 0x0000d378, 0x5fffffe2 },
7897 + { 0x0000d37c, 0x7fffffe2 },
7898 + { 0x0000d380, 0x7f3c7bba },
7899 + { 0x0000d384, 0xf3307ff0 },
7900 + { 0x0000a388, 0x0c000000 },
7901 + { 0x0000a38c, 0x20202020 },
7902 + { 0x0000a390, 0x20202020 },
7903 + { 0x0000a39c, 0x00000001 },
7904 + { 0x0000a3a0, 0x00000000 },
7905 + { 0x0000a3a4, 0x00000000 },
7906 + { 0x0000a3a8, 0x00000000 },
7907 + { 0x0000a3ac, 0x00000000 },
7908 + { 0x0000a3b0, 0x00000000 },
7909 + { 0x0000a3b4, 0x00000000 },
7910 + { 0x0000a3b8, 0x00000000 },
7911 + { 0x0000a3bc, 0x00000000 },
7912 + { 0x0000a3c0, 0x00000000 },
7913 + { 0x0000a3c4, 0x00000000 },
7914 + { 0x0000a3cc, 0x20202020 },
7915 + { 0x0000a3d0, 0x20202020 },
7916 + { 0x0000a3d4, 0x20202020 },
7917 + { 0x0000a3e4, 0x00000000 },
7918 + { 0x0000a3e8, 0x18c43433 },
7919 + { 0x0000a3ec, 0x00f70081 },
7920 + { 0x00007800, 0x00140000 },
7921 + { 0x00007804, 0x0e4548d8 },
7922 + { 0x00007808, 0x54214514 },
7923 + { 0x0000780c, 0x02025830 },
7924 + { 0x00007810, 0x71c0d388 },
7925 + { 0x0000781c, 0x00000000 },
7926 + { 0x00007824, 0x00d86fff },
7927 + { 0x0000782c, 0x6e36d97b },
7928 + { 0x00007834, 0x71400087 },
7929 + { 0x00007844, 0x000c0db6 },
7930 + { 0x00007848, 0x6db6246f },
7931 + { 0x0000784c, 0x6d9b66db },
7932 + { 0x00007850, 0x6d8c6dba },
7933 + { 0x00007854, 0x00040000 },
7934 + { 0x00007858, 0xdb003012 },
7935 + { 0x0000785c, 0x04924914 },
7936 + { 0x00007860, 0x21084210 },
7937 + { 0x00007864, 0xf7d7ffde },
7938 + { 0x00007868, 0xc2034080 },
7939 + { 0x00007870, 0x10142c00 },
7940 +};
7941 +
7942 +static const u_int32_t ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
7943 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
7944 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
7945 + { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
7946 + { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
7947 + { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
7948 + { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
7949 + { 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
7950 + { 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
7951 + { 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
7952 + { 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
7953 + { 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
7954 + { 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
7955 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
7956 + { 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
7957 + { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
7958 + { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
7959 + { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
7960 + { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
7961 + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
7962 + { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
7963 + { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
7964 + { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
7965 + { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
7966 + { 0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8 },
7967 + { 0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b },
7968 + { 0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e },
7969 + { 0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803 },
7970 + { 0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe },
7971 + { 0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20 },
7972 + { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
7973 + { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
7974 + { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
7975 + { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
7976 + { 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
7977 + { 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
7978 + { 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
7979 + { 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
7980 + { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
7981 +};
7982 +
7983 +static const u_int32_t ar9285Modes_original_tx_gain_9285_1_2[][6] = {
7984 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
7985 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
7986 + { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
7987 + { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
7988 + { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
7989 + { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
7990 + { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
7991 + { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
7992 + { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
7993 + { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
7994 + { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
7995 + { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
7996 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
7997 + { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
7998 + { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
7999 + { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
8000 + { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
8001 + { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8002 + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8003 + { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8004 + { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8005 + { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8006 + { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8007 + { 0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8 },
8008 + { 0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b },
8009 + { 0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e },
8010 + { 0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801 },
8011 + { 0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe },
8012 + { 0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20 },
8013 + { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
8014 + { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
8015 + { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
8016 + { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
8017 + { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
8018 + { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
8019 + { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
8020 + { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
8021 + { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
8022 +};
8023 +
8024 +static const u_int32_t ar9285Modes_XE2_0_normal_power[][6] = {
8025 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8026 + { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
8027 + { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
8028 + { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
8029 + { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
8030 + { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
8031 + { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
8032 + { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
8033 + { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
8034 + { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
8035 + { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
8036 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
8037 + { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
8038 + { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
8039 + { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
8040 + { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
8041 + { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8042 + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8043 + { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8044 + { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8045 + { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8046 + { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8047 + { 0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8 },
8048 + { 0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b, 0x4ad2491b },
8049 + { 0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6dbae },
8050 + { 0x00007838, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441 },
8051 + { 0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe },
8052 + { 0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c },
8053 + { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
8054 + { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
8055 + { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
8056 + { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
8057 + { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
8058 + { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
8059 + { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
8060 + { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
8061 + { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
8062 +};
8063 +
8064 +static const u_int32_t ar9285Modes_XE2_0_high_power[][6] = {
8065 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8066 + { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
8067 + { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
8068 + { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
8069 + { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
8070 + { 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
8071 + { 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
8072 + { 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
8073 + { 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
8074 + { 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
8075 + { 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
8076 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
8077 + { 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
8078 + { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
8079 + { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
8080 + { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
8081 + { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8082 + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8083 + { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8084 + { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8085 + { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8086 + { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8087 + { 0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8 },
8088 + { 0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b, 0x4ad2491b },
8089 + { 0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e },
8090 + { 0x00007838, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443 },
8091 + { 0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe },
8092 + { 0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c },
8093 + { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
8094 + { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
8095 + { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
8096 + { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
8097 + { 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
8098 + { 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
8099 + { 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
8100 + { 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
8101 + { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
8102 +};
8103 +
8104 +static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
8105 + {0x00004040, 0x9248fd00 },
8106 + {0x00004040, 0x24924924 },
8107 + {0x00004040, 0xa8000019 },
8108 + {0x00004040, 0x13160820 },
8109 + {0x00004040, 0xe5980560 },
8110 + {0x00004040, 0xc01dcffd },
8111 + {0x00004040, 0x1aaabe41 },
8112 + {0x00004040, 0xbe105554 },
8113 + {0x00004040, 0x00043007 },
8114 + {0x00004044, 0x00000000 },
8115 +};
8116 +
8117 +static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
8118 + {0x00004040, 0x9248fd00 },
8119 + {0x00004040, 0x24924924 },
8120 + {0x00004040, 0xa8000019 },
8121 + {0x00004040, 0x13160820 },
8122 + {0x00004040, 0xe5980560 },
8123 + {0x00004040, 0xc01dcffc },
8124 + {0x00004040, 0x1aaabe41 },
8125 + {0x00004040, 0xbe105554 },
8126 + {0x00004040, 0x00043007 },
8127 + {0x00004044, 0x00000000 },
8128 +};
8129 +
8130 +/* AR9287 Revision 10 */
8131 +static const u_int32_t ar9287Modes_9287_1_0[][6] = {
8132 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
8133 + { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 },
8134 + { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 },
8135 + { 0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180 },
8136 + { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
8137 + { 0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00, 0x06e006e0 },
8138 + { 0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b, 0x0988004f },
8139 + { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
8140 + { 0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a, 0x0000320a },
8141 + { 0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440, 0x00006880 },
8142 + { 0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300, 0x00000303 },
8143 + { 0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200, 0x02020200 },
8144 + { 0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e, 0x01000e0e },
8145 + { 0x00009828, 0x00000000, 0x00000000, 0x0a020001, 0x0a020001, 0x0a020001 },
8146 + { 0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e, 0x00000e0e },
8147 + { 0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007, 0x00000007 },
8148 + { 0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e, 0x206a012e },
8149 + { 0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0, 0x037216a0 },
8150 + { 0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
8151 + { 0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
8152 + { 0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e, 0x31395d5e },
8153 + { 0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20, 0x00058d18 },
8154 + { 0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
8155 + { 0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
8156 + { 0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881, 0x06903881 },
8157 + { 0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898, 0x000007d0 },
8158 + { 0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b, 0x00000016 },
8159 + { 0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
8160 + { 0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010, 0xefbc1010 },
8161 + { 0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
8162 + { 0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
8163 + { 0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210, 0x00000210 },
8164 + { 0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce, 0x000003ce },
8165 + { 0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c, 0x0000001c },
8166 + { 0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00, 0x00000c00 },
8167 + { 0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
8168 + { 0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444, 0x00000444 },
8169 + { 0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8170 + { 0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8171 + { 0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a, 0x1883800a },
8172 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
8173 + { 0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000, 0x0004a000 },
8174 + { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
8175 + { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8176 +};
8177 +
8178 +static const u_int32_t ar9287Common_9287_1_0[][2] = {
8179 + { 0x0000000c, 0x00000000 },
8180 + { 0x00000030, 0x00020015 },
8181 + { 0x00000034, 0x00000005 },
8182 + { 0x00000040, 0x00000000 },
8183 + { 0x00000044, 0x00000008 },
8184 + { 0x00000048, 0x00000008 },
8185 + { 0x0000004c, 0x00000010 },
8186 + { 0x00000050, 0x00000000 },
8187 + { 0x00000054, 0x0000001f },
8188 + { 0x00000800, 0x00000000 },
8189 + { 0x00000804, 0x00000000 },
8190 + { 0x00000808, 0x00000000 },
8191 + { 0x0000080c, 0x00000000 },
8192 + { 0x00000810, 0x00000000 },
8193 + { 0x00000814, 0x00000000 },
8194 + { 0x00000818, 0x00000000 },
8195 + { 0x0000081c, 0x00000000 },
8196 + { 0x00000820, 0x00000000 },
8197 + { 0x00000824, 0x00000000 },
8198 + { 0x00001040, 0x002ffc0f },
8199 + { 0x00001044, 0x002ffc0f },
8200 + { 0x00001048, 0x002ffc0f },
8201 + { 0x0000104c, 0x002ffc0f },
8202 + { 0x00001050, 0x002ffc0f },
8203 + { 0x00001054, 0x002ffc0f },
8204 + { 0x00001058, 0x002ffc0f },
8205 + { 0x0000105c, 0x002ffc0f },
8206 + { 0x00001060, 0x002ffc0f },
8207 + { 0x00001064, 0x002ffc0f },
8208 + { 0x00001230, 0x00000000 },
8209 + { 0x00001270, 0x00000000 },
8210 + { 0x00001038, 0x00000000 },
8211 + { 0x00001078, 0x00000000 },
8212 + { 0x000010b8, 0x00000000 },
8213 + { 0x000010f8, 0x00000000 },
8214 + { 0x00001138, 0x00000000 },
8215 + { 0x00001178, 0x00000000 },
8216 + { 0x000011b8, 0x00000000 },
8217 + { 0x000011f8, 0x00000000 },
8218 + { 0x00001238, 0x00000000 },
8219 + { 0x00001278, 0x00000000 },
8220 + { 0x000012b8, 0x00000000 },
8221 + { 0x000012f8, 0x00000000 },
8222 + { 0x00001338, 0x00000000 },
8223 + { 0x00001378, 0x00000000 },
8224 + { 0x000013b8, 0x00000000 },
8225 + { 0x000013f8, 0x00000000 },
8226 + { 0x00001438, 0x00000000 },
8227 + { 0x00001478, 0x00000000 },
8228 + { 0x000014b8, 0x00000000 },
8229 + { 0x000014f8, 0x00000000 },
8230 + { 0x00001538, 0x00000000 },
8231 + { 0x00001578, 0x00000000 },
8232 + { 0x000015b8, 0x00000000 },
8233 + { 0x000015f8, 0x00000000 },
8234 + { 0x00001638, 0x00000000 },
8235 + { 0x00001678, 0x00000000 },
8236 + { 0x000016b8, 0x00000000 },
8237 + { 0x000016f8, 0x00000000 },
8238 + { 0x00001738, 0x00000000 },
8239 + { 0x00001778, 0x00000000 },
8240 + { 0x000017b8, 0x00000000 },
8241 + { 0x000017f8, 0x00000000 },
8242 + { 0x0000103c, 0x00000000 },
8243 + { 0x0000107c, 0x00000000 },
8244 + { 0x000010bc, 0x00000000 },
8245 + { 0x000010fc, 0x00000000 },
8246 + { 0x0000113c, 0x00000000 },
8247 + { 0x0000117c, 0x00000000 },
8248 + { 0x000011bc, 0x00000000 },
8249 + { 0x000011fc, 0x00000000 },
8250 + { 0x0000123c, 0x00000000 },
8251 + { 0x0000127c, 0x00000000 },
8252 + { 0x000012bc, 0x00000000 },
8253 + { 0x000012fc, 0x00000000 },
8254 + { 0x0000133c, 0x00000000 },
8255 + { 0x0000137c, 0x00000000 },
8256 + { 0x000013bc, 0x00000000 },
8257 + { 0x000013fc, 0x00000000 },
8258 + { 0x0000143c, 0x00000000 },
8259 + { 0x0000147c, 0x00000000 },
8260 + { 0x00004030, 0x00000002 },
8261 + { 0x0000403c, 0x00000002 },
8262 + { 0x00004024, 0x0000001f },
8263 + { 0x00004060, 0x00000000 },
8264 + { 0x00004064, 0x00000000 },
8265 + { 0x00007010, 0x00000033 },
8266 + { 0x00007020, 0x00000000 },
8267 + { 0x00007034, 0x00000002 },
8268 + { 0x00007038, 0x000004c2 },
8269 + { 0x00008004, 0x00000000 },
8270 + { 0x00008008, 0x00000000 },
8271 + { 0x0000800c, 0x00000000 },
8272 + { 0x00008018, 0x00000700 },
8273 + { 0x00008020, 0x00000000 },
8274 + { 0x00008038, 0x00000000 },
8275 + { 0x0000803c, 0x00000000 },
8276 + { 0x00008048, 0x40000000 },
8277 + { 0x00008054, 0x00000000 },
8278 + { 0x00008058, 0x00000000 },
8279 + { 0x0000805c, 0x000fc78f },
8280 + { 0x00008060, 0x0000000f },
8281 + { 0x00008064, 0x00000000 },
8282 + { 0x00008070, 0x00000000 },
8283 + { 0x000080c0, 0x2a80001a },
8284 + { 0x000080c4, 0x05dc01e0 },
8285 + { 0x000080c8, 0x1f402710 },
8286 + { 0x000080cc, 0x01f40000 },
8287 + { 0x000080d0, 0x00001e00 },
8288 + { 0x000080d4, 0x00000000 },
8289 + { 0x000080d8, 0x00400000 },
8290 + { 0x000080e0, 0xffffffff },
8291 + { 0x000080e4, 0x0000ffff },
8292 + { 0x000080e8, 0x003f3f3f },
8293 + { 0x000080ec, 0x00000000 },
8294 + { 0x000080f0, 0x00000000 },
8295 + { 0x000080f4, 0x00000000 },
8296 + { 0x000080f8, 0x00000000 },
8297 + { 0x000080fc, 0x00020000 },
8298 + { 0x00008100, 0x00020000 },
8299 + { 0x00008104, 0x00000001 },
8300 + { 0x00008108, 0x00000052 },
8301 + { 0x0000810c, 0x00000000 },
8302 + { 0x00008110, 0x00000168 },
8303 + { 0x00008118, 0x000100aa },
8304 + { 0x0000811c, 0x00003210 },
8305 + { 0x00008124, 0x00000000 },
8306 + { 0x00008128, 0x00000000 },
8307 + { 0x0000812c, 0x00000000 },
8308 + { 0x00008130, 0x00000000 },
8309 + { 0x00008134, 0x00000000 },
8310 + { 0x00008138, 0x00000000 },
8311 + { 0x0000813c, 0x00000000 },
8312 + { 0x00008144, 0xffffffff },
8313 + { 0x00008168, 0x00000000 },
8314 + { 0x0000816c, 0x00000000 },
8315 + { 0x00008170, 0x18487320 },
8316 + { 0x00008174, 0xfaa4fa50 },
8317 + { 0x00008178, 0x00000100 },
8318 + { 0x0000817c, 0x00000000 },
8319 + { 0x000081c0, 0x00000000 },
8320 + { 0x000081c4, 0x00000000 },
8321 + { 0x000081d4, 0x00000000 },
8322 + { 0x000081ec, 0x00000000 },
8323 + { 0x000081f0, 0x00000000 },
8324 + { 0x000081f4, 0x00000000 },
8325 + { 0x000081f8, 0x00000000 },
8326 + { 0x000081fc, 0x00000000 },
8327 + { 0x00008200, 0x00000000 },
8328 + { 0x00008204, 0x00000000 },
8329 + { 0x00008208, 0x00000000 },
8330 + { 0x0000820c, 0x00000000 },
8331 + { 0x00008210, 0x00000000 },
8332 + { 0x00008214, 0x00000000 },
8333 + { 0x00008218, 0x00000000 },
8334 + { 0x0000821c, 0x00000000 },
8335 + { 0x00008220, 0x00000000 },
8336 + { 0x00008224, 0x00000000 },
8337 + { 0x00008228, 0x00000000 },
8338 + { 0x0000822c, 0x00000000 },
8339 + { 0x00008230, 0x00000000 },
8340 + { 0x00008234, 0x00000000 },
8341 + { 0x00008238, 0x00000000 },
8342 + { 0x0000823c, 0x00000000 },
8343 + { 0x00008240, 0x00100000 },
8344 + { 0x00008244, 0x0010f400 },
8345 + { 0x00008248, 0x00000100 },
8346 + { 0x0000824c, 0x0001e800 },
8347 + { 0x00008250, 0x00000000 },
8348 + { 0x00008254, 0x00000000 },
8349 + { 0x00008258, 0x00000000 },
8350 + { 0x0000825c, 0x400000ff },
8351 + { 0x00008260, 0x00080922 },
8352 + { 0x00008264, 0xa8a00010 },
8353 + { 0x00008270, 0x00000000 },
8354 + { 0x00008274, 0x40000000 },
8355 + { 0x00008278, 0x003e4180 },
8356 + { 0x0000827c, 0x00000000 },
8357 + { 0x00008284, 0x0000002c },
8358 + { 0x00008288, 0x0000002c },
8359 + { 0x0000828c, 0x000000ff },
8360 + { 0x00008294, 0x00000000 },
8361 + { 0x00008298, 0x00000000 },
8362 + { 0x0000829c, 0x00000000 },
8363 + { 0x00008300, 0x00000040 },
8364 + { 0x00008314, 0x00000000 },
8365 + { 0x00008328, 0x00000000 },
8366 + { 0x0000832c, 0x00000007 },
8367 + { 0x00008330, 0x00000302 },
8368 + { 0x00008334, 0x00000e00 },
8369 + { 0x00008338, 0x00ff0000 },
8370 + { 0x0000833c, 0x00000000 },
8371 + { 0x00008340, 0x000107ff },
8372 + { 0x00008344, 0x01c81043 },
8373 + { 0x00008360, 0xffffffff },
8374 + { 0x00008364, 0xffffffff },
8375 + { 0x00008368, 0x00000000 },
8376 + { 0x00008370, 0x00000000 },
8377 + { 0x00008374, 0x000000ff },
8378 + { 0x00008378, 0x00000000 },
8379 + { 0x0000837c, 0x00000000 },
8380 + { 0x00008380, 0xffffffff },
8381 + { 0x00008384, 0xffffffff },
8382 + { 0x00008390, 0x0fffffff },
8383 + { 0x00008394, 0x0fffffff },
8384 + { 0x00008398, 0x00000000 },
8385 + { 0x0000839c, 0x00000000 },
8386 + { 0x000083a0, 0x00000000 },
8387 + { 0x00009808, 0x00000000 },
8388 + { 0x0000980c, 0xafe68e30 },
8389 + { 0x00009810, 0xfd14e000 },
8390 + { 0x00009814, 0x9c0a9f6b },
8391 + { 0x0000981c, 0x00000000 },
8392 + { 0x0000982c, 0x0000a000 },
8393 + { 0x00009830, 0x00000000 },
8394 + { 0x0000983c, 0x00200400 },
8395 + { 0x0000984c, 0x0040233c },
8396 + { 0x0000a84c, 0x0040233c },
8397 + { 0x00009854, 0x00000044 },
8398 + { 0x00009900, 0x00000000 },
8399 + { 0x00009904, 0x00000000 },
8400 + { 0x00009908, 0x00000000 },
8401 + { 0x0000990c, 0x00000000 },
8402 + { 0x00009910, 0x10002310 },
8403 + { 0x0000991c, 0x10000fff },
8404 + { 0x00009920, 0x04900000 },
8405 + { 0x0000a920, 0x04900000 },
8406 + { 0x00009928, 0x00000001 },
8407 + { 0x0000992c, 0x00000004 },
8408 + { 0x00009930, 0x00000000 },
8409 + { 0x0000a930, 0x00000000 },
8410 + { 0x00009934, 0x1e1f2022 },
8411 + { 0x00009938, 0x0a0b0c0d },
8412 + { 0x0000993c, 0x00000000 },
8413 + { 0x00009948, 0x9280c00a },
8414 + { 0x0000994c, 0x00020028 },
8415 + { 0x00009954, 0x5f3ca3de },
8416 + { 0x00009958, 0x0108ecff },
8417 + { 0x00009940, 0x14750604 },
8418 + { 0x0000c95c, 0x004b6a8e },
8419 + { 0x00009970, 0x990bb515 },
8420 + { 0x00009974, 0x00000000 },
8421 + { 0x00009978, 0x00000001 },
8422 + { 0x0000997c, 0x00000000 },
8423 + { 0x000099a0, 0x00000000 },
8424 + { 0x000099a4, 0x00000001 },
8425 + { 0x000099a8, 0x201fff00 },
8426 + { 0x000099ac, 0x0c6f0000 },
8427 + { 0x000099b0, 0x03051000 },
8428 + { 0x000099b4, 0x00000820 },
8429 + { 0x000099c4, 0x06336f77 },
8430 + { 0x000099c8, 0x6af65329 },
8431 + { 0x000099cc, 0x08f186c8 },
8432 + { 0x000099d0, 0x00046384 },
8433 + { 0x000099dc, 0x00000000 },
8434 + { 0x000099e0, 0x00000000 },
8435 + { 0x000099e4, 0xaaaaaaaa },
8436 + { 0x000099e8, 0x3c466478 },
8437 + { 0x000099ec, 0x0cc80caa },
8438 + { 0x000099f0, 0x00000000 },
8439 + { 0x000099fc, 0x00001042 },
8440 + { 0x0000a1f4, 0x00fffeff },
8441 + { 0x0000a1f8, 0x00f5f9ff },
8442 + { 0x0000a1fc, 0xb79f6427 },
8443 + { 0x0000a208, 0x803e4788 },
8444 + { 0x0000a210, 0x4080a333 },
8445 + { 0x0000a214, 0x40206c10 },
8446 + { 0x0000a218, 0x009c4060 },
8447 + { 0x0000a220, 0x01834061 },
8448 + { 0x0000a224, 0x00000400 },
8449 + { 0x0000a228, 0x000003b5 },
8450 + { 0x0000a22c, 0x233f7180 },
8451 + { 0x0000a234, 0x20202020 },
8452 + { 0x0000a238, 0x20202020 },
8453 + { 0x0000a23c, 0x13c889af },
8454 + { 0x0000a240, 0x38490a20 },
8455 + { 0x0000a244, 0x00000000 },
8456 + { 0x0000a248, 0xfffffffc },
8457 + { 0x0000a24c, 0x00000000 },
8458 + { 0x0000a254, 0x00000000 },
8459 + { 0x0000a258, 0x0cdbd380 },
8460 + { 0x0000a25c, 0x0f0f0f01 },
8461 + { 0x0000a260, 0xdfa91f01 },
8462 + { 0x0000a264, 0x00418a11 },
8463 + { 0x0000b264, 0x00418a11 },
8464 + { 0x0000a268, 0x00000000 },
8465 + { 0x0000a26c, 0x0e79e5c6 },
8466 + { 0x0000b26c, 0x0e79e5c6 },
8467 + { 0x0000d270, 0x00820820 },
8468 + { 0x0000a278, 0x1ce739ce },
8469 + { 0x0000a27c, 0x050701ce },
8470 + { 0x0000d35c, 0x07ffffef },
8471 + { 0x0000d360, 0x0fffffe7 },
8472 + { 0x0000d364, 0x17ffffe5 },
8473 + { 0x0000d368, 0x1fffffe4 },
8474 + { 0x0000d36c, 0x37ffffe3 },
8475 + { 0x0000d370, 0x3fffffe3 },
8476 + { 0x0000d374, 0x57ffffe3 },
8477 + { 0x0000d378, 0x5fffffe2 },
8478 + { 0x0000d37c, 0x7fffffe2 },
8479 + { 0x0000d380, 0x7f3c7bba },
8480 + { 0x0000d384, 0xf3307ff0 },
8481 + { 0x0000a388, 0x0c000000 },
8482 + { 0x0000a38c, 0x20202020 },
8483 + { 0x0000a390, 0x20202020 },
8484 + { 0x0000a394, 0x1ce739ce },
8485 + { 0x0000a398, 0x000001ce },
8486 + { 0x0000b398, 0x000001ce },
8487 + { 0x0000a39c, 0x00000001 },
8488 + { 0x0000a3c8, 0x00000246 },
8489 + { 0x0000a3cc, 0x20202020 },
8490 + { 0x0000a3d0, 0x20202020 },
8491 + { 0x0000a3d4, 0x20202020 },
8492 + { 0x0000a3dc, 0x1ce739ce },
8493 + { 0x0000a3e0, 0x000001ce },
8494 + { 0x0000a3e4, 0x00000000 },
8495 + { 0x0000a3e8, 0x18c43433 },
8496 + { 0x0000a3ec, 0x00f70081 },
8497 + { 0x0000a3f0, 0x01036a1e },
8498 + { 0x0000a3f4, 0x00000000 },
8499 + { 0x0000b3f4, 0x00000000 },
8500 + { 0x0000a7d8, 0x00000001 },
8501 + { 0x00007800, 0x00000800 },
8502 + { 0x00007804, 0x6c35ffb0 },
8503 + { 0x00007808, 0x6db6c000 },
8504 + { 0x0000780c, 0x6db6cb30 },
8505 + { 0x00007810, 0x6db6cb6c },
8506 + { 0x00007814, 0x0501e200 },
8507 + { 0x00007818, 0x0094128d },
8508 + { 0x0000781c, 0x976ee392 },
8509 + { 0x00007820, 0xf75ff6fc },
8510 + { 0x00007824, 0x00040000 },
8511 + { 0x00007828, 0xdb003012 },
8512 + { 0x0000782c, 0x04924914 },
8513 + { 0x00007830, 0x21084210 },
8514 + { 0x00007834, 0x00140000 },
8515 + { 0x00007838, 0x0e4548d8 },
8516 + { 0x0000783c, 0x54214514 },
8517 + { 0x00007840, 0x02025820 },
8518 + { 0x00007844, 0x71c0d388 },
8519 + { 0x00007848, 0x934934a8 },
8520 + { 0x00007850, 0x00000000 },
8521 + { 0x00007854, 0x00000800 },
8522 + { 0x00007858, 0x6c35ffb0 },
8523 + { 0x0000785c, 0x6db6c000 },
8524 + { 0x00007860, 0x6db6cb2c },
8525 + { 0x00007864, 0x6db6cb6c },
8526 + { 0x00007868, 0x0501e200 },
8527 + { 0x0000786c, 0x0094128d },
8528 + { 0x00007870, 0x976ee392 },
8529 + { 0x00007874, 0xf75ff6fc },
8530 + { 0x00007878, 0x00040000 },
8531 + { 0x0000787c, 0xdb003012 },
8532 + { 0x00007880, 0x04924914 },
8533 + { 0x00007884, 0x21084210 },
8534 + { 0x00007888, 0x001b6db0 },
8535 + { 0x0000788c, 0x00376b63 },
8536 + { 0x00007890, 0x06db6db6 },
8537 + { 0x00007894, 0x006d8000 },
8538 + { 0x00007898, 0x48100000 },
8539 + { 0x0000789c, 0x00000000 },
8540 + { 0x000078a0, 0x08000000 },
8541 + { 0x000078a4, 0x0007ffd8 },
8542 + { 0x000078a8, 0x0007ffd8 },
8543 + { 0x000078ac, 0x001c0020 },
8544 + { 0x000078b0, 0x000611eb },
8545 + { 0x000078b4, 0x40008080 },
8546 + { 0x000078b8, 0x2a850160 },
8547 +};
8548 +
8549 +static const u_int32_t ar9287Modes_tx_gain_9287_1_0[][6] = {
8550 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
8551 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8552 + { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 },
8553 + { 0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004 },
8554 + { 0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a, 0x0000c00a },
8555 + { 0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c, 0x0001000c },
8556 + { 0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b, 0x0001420b },
8557 + { 0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a, 0x0001824a },
8558 + { 0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a, 0x0001c44a },
8559 + { 0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a, 0x0002064a },
8560 + { 0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a, 0x0002484a },
8561 + { 0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a, 0x00028a4a },
8562 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a },
8563 + { 0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a, 0x00030e4a },
8564 + { 0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a, 0x00034e8a },
8565 + { 0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c, 0x00038e8c },
8566 + { 0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc, 0x0003cecc },
8567 + { 0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4, 0x00040ed4 },
8568 + { 0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc, 0x00044edc },
8569 + { 0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede, 0x00048ede },
8570 + { 0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e },
8571 + { 0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e, 0x00050f5e },
8572 + { 0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e, 0x00054f9e },
8573 + { 0x0000a780, 0x00000000, 0x00000000, 0x00000060, 0x00000060, 0x00000060 },
8574 + { 0x0000a784, 0x00000000, 0x00000000, 0x00004062, 0x00004062, 0x00004062 },
8575 + { 0x0000a788, 0x00000000, 0x00000000, 0x00008064, 0x00008064, 0x00008064 },
8576 + { 0x0000a78c, 0x00000000, 0x00000000, 0x0000c0a4, 0x0000c0a4, 0x0000c0a4 },
8577 + { 0x0000a790, 0x00000000, 0x00000000, 0x000100b0, 0x000100b0, 0x000100b0 },
8578 + { 0x0000a794, 0x00000000, 0x00000000, 0x000140b2, 0x000140b2, 0x000140b2 },
8579 + { 0x0000a798, 0x00000000, 0x00000000, 0x000180b4, 0x000180b4, 0x000180b4 },
8580 + { 0x0000a79c, 0x00000000, 0x00000000, 0x0001c0f4, 0x0001c0f4, 0x0001c0f4 },
8581 + { 0x0000a7a0, 0x00000000, 0x00000000, 0x00020134, 0x00020134, 0x00020134 },
8582 + { 0x0000a7a4, 0x00000000, 0x00000000, 0x000240fe, 0x000240fe, 0x000240fe },
8583 + { 0x0000a7a8, 0x00000000, 0x00000000, 0x0002813e, 0x0002813e, 0x0002813e },
8584 + { 0x0000a7ac, 0x00000000, 0x00000000, 0x0002c17e, 0x0002c17e, 0x0002c17e },
8585 + { 0x0000a7b0, 0x00000000, 0x00000000, 0x000301be, 0x000301be, 0x000301be },
8586 + { 0x0000a7b4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8587 + { 0x0000a7b8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8588 + { 0x0000a7bc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8589 + { 0x0000a7c0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8590 + { 0x0000a7c4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8591 + { 0x0000a7c8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8592 + { 0x0000a7cc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8593 + { 0x0000a7d0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8594 + { 0x0000a7d4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8595 + { 0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000 },
8596 +};
8597 +
8598 +
8599 +static const u_int32_t ar9287Modes_rx_gain_9287_1_0[][6] = {
8600 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
8601 + { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
8602 + { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
8603 + { 0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
8604 + { 0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
8605 + { 0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
8606 + { 0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
8607 + { 0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
8608 + { 0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
8609 + { 0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
8610 + { 0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
8611 + { 0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
8612 + { 0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
8613 + { 0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
8614 + { 0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
8615 + { 0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
8616 + { 0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
8617 + { 0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
8618 + { 0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
8619 + { 0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
8620 + { 0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
8621 + { 0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
8622 + { 0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
8623 + { 0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
8624 + { 0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
8625 + { 0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
8626 + { 0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
8627 + { 0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
8628 + { 0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
8629 + { 0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
8630 + { 0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
8631 + { 0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
8632 + { 0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
8633 + { 0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
8634 + { 0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
8635 + { 0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
8636 + { 0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
8637 + { 0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
8638 + { 0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
8639 + { 0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
8640 + { 0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
8641 + { 0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
8642 + { 0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
8643 + { 0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
8644 + { 0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
8645 + { 0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
8646 + { 0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
8647 + { 0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
8648 + { 0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
8649 + { 0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
8650 + { 0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
8651 + { 0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
8652 + { 0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
8653 + { 0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
8654 + { 0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
8655 + { 0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
8656 + { 0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
8657 + { 0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
8658 + { 0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
8659 + { 0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
8660 + { 0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
8661 + { 0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
8662 + { 0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
8663 + { 0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
8664 + { 0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
8665 + { 0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
8666 + { 0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
8667 + { 0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
8668 + { 0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
8669 + { 0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
8670 + { 0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
8671 + { 0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
8672 + { 0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
8673 + { 0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
8674 + { 0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
8675 + { 0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
8676 + { 0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
8677 + { 0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
8678 + { 0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
8679 + { 0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
8680 + { 0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
8681 + { 0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
8682 + { 0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
8683 + { 0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
8684 + { 0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
8685 + { 0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
8686 + { 0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
8687 + { 0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
8688 + { 0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
8689 + { 0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
8690 + { 0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
8691 + { 0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
8692 + { 0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
8693 + { 0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
8694 + { 0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
8695 + { 0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
8696 + { 0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
8697 + { 0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
8698 + { 0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
8699 + { 0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
8700 + { 0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
8701 + { 0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
8702 + { 0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
8703 + { 0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
8704 + { 0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8705 + { 0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8706 + { 0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8707 + { 0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8708 + { 0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8709 + { 0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8710 + { 0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8711 + { 0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8712 + { 0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8713 + { 0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8714 + { 0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8715 + { 0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8716 + { 0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8717 + { 0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8718 + { 0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8719 + { 0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8720 + { 0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8721 + { 0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8722 + { 0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8723 + { 0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8724 + { 0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8725 + { 0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8726 + { 0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8727 + { 0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8728 + { 0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8729 + { 0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
8730 + { 0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
8731 + { 0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
8732 + { 0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
8733 + { 0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
8734 + { 0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
8735 + { 0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
8736 + { 0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
8737 + { 0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
8738 + { 0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
8739 + { 0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
8740 + { 0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
8741 + { 0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
8742 + { 0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
8743 + { 0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
8744 + { 0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
8745 + { 0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
8746 + { 0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
8747 + { 0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
8748 + { 0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
8749 + { 0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
8750 + { 0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
8751 + { 0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
8752 + { 0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
8753 + { 0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
8754 + { 0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
8755 + { 0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
8756 + { 0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
8757 + { 0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
8758 + { 0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
8759 + { 0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
8760 + { 0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
8761 + { 0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
8762 + { 0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
8763 + { 0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
8764 + { 0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
8765 + { 0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
8766 + { 0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
8767 + { 0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
8768 + { 0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
8769 + { 0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
8770 + { 0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
8771 + { 0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
8772 + { 0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
8773 + { 0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
8774 + { 0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
8775 + { 0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
8776 + { 0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
8777 + { 0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
8778 + { 0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
8779 + { 0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
8780 + { 0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
8781 + { 0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
8782 + { 0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
8783 + { 0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
8784 + { 0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
8785 + { 0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
8786 + { 0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
8787 + { 0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
8788 + { 0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
8789 + { 0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
8790 + { 0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
8791 + { 0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
8792 + { 0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
8793 + { 0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
8794 + { 0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
8795 + { 0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
8796 + { 0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
8797 + { 0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
8798 + { 0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
8799 + { 0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
8800 + { 0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
8801 + { 0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
8802 + { 0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
8803 + { 0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
8804 + { 0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
8805 + { 0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
8806 + { 0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
8807 + { 0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
8808 + { 0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
8809 + { 0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
8810 + { 0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
8811 + { 0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
8812 + { 0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
8813 + { 0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
8814 + { 0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
8815 + { 0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
8816 + { 0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
8817 + { 0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
8818 + { 0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
8819 + { 0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
8820 + { 0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
8821 + { 0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
8822 + { 0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
8823 + { 0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
8824 + { 0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
8825 + { 0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
8826 + { 0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
8827 + { 0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
8828 + { 0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
8829 + { 0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
8830 + { 0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
8831 + { 0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
8832 + { 0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8833 + { 0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8834 + { 0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8835 + { 0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8836 + { 0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8837 + { 0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8838 + { 0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8839 + { 0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8840 + { 0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8841 + { 0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8842 + { 0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8843 + { 0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8844 + { 0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8845 + { 0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8846 + { 0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8847 + { 0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8848 + { 0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8849 + { 0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8850 + { 0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8851 + { 0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8852 + { 0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8853 + { 0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8854 + { 0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8855 + { 0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8856 + { 0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8857 + { 0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
8858 + { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
8859 +};
8860 +
8861 +static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_0[][2] = {
8862 + {0x00004040, 0x9248fd00 },
8863 + {0x00004040, 0x24924924 },
8864 + {0x00004040, 0xa8000019 },
8865 + {0x00004040, 0x13160820 },
8866 + {0x00004040, 0xe5980560 },
8867 + {0x00004040, 0xc01dcffd },
8868 + {0x00004040, 0x1aaabe41 },
8869 + {0x00004040, 0xbe105554 },
8870 + {0x00004040, 0x00043007 },
8871 + {0x00004044, 0x00000000 },
8872 +};
8873 +
8874 +static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_0[][2] = {
8875 + {0x00004040, 0x9248fd00 },
8876 + {0x00004040, 0x24924924 },
8877 + {0x00004040, 0xa8000019 },
8878 + {0x00004040, 0x13160820 },
8879 + {0x00004040, 0xe5980560 },
8880 + {0x00004040, 0xc01dcffc },
8881 + {0x00004040, 0x1aaabe41 },
8882 + {0x00004040, 0xbe105554 },
8883 + {0x00004040, 0x00043007 },
8884 + {0x00004044, 0x00000000 },
8885 +};
8886 +
8887 +/* AR9287 Revision 11 */
8888 +
8889 +static const u_int32_t ar9287Modes_9287_1_1[][6] = {
8890 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
8891 + { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 },
8892 + { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 },
8893 + { 0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180 },
8894 + { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
8895 + { 0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00, 0x06e006e0 },
8896 + { 0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b, 0x0988004f },
8897 + { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
8898 + { 0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a, 0x0000320a },
8899 + { 0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440, 0x00006880 },
8900 + { 0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300, 0x00000303 },
8901 + { 0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200, 0x02020200 },
8902 + { 0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e, 0x01000e0e },
8903 + { 0x00009828, 0x00000000, 0x00000000, 0x3a020001, 0x3a020001, 0x3a020001 },
8904 + { 0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e, 0x00000e0e },
8905 + { 0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007, 0x00000007 },
8906 + { 0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e, 0x206a012e },
8907 + { 0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0, 0x037216a0 },
8908 + { 0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
8909 + { 0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
8910 + { 0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e, 0x31395d5e },
8911 + { 0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20, 0x00058d18 },
8912 + { 0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
8913 + { 0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
8914 + { 0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881, 0x06903881 },
8915 + { 0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898, 0x000007d0 },
8916 + { 0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b, 0x00000016 },
8917 + { 0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
8918 + { 0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010, 0xefbc1010 },
8919 + { 0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
8920 + { 0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
8921 + { 0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210, 0x00000210 },
8922 + { 0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce, 0x000003ce },
8923 + { 0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c, 0x0000001c },
8924 + { 0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00, 0x00000c00 },
8925 + { 0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
8926 + { 0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444, 0x00000444 },
8927 + { 0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8928 + { 0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8929 + { 0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a, 0x1883800a },
8930 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
8931 + { 0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000, 0x0004a000 },
8932 + { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
8933 + { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8934 +};
8935 +
8936 +static const u_int32_t ar9287Common_9287_1_1[][2] = {
8937 + { 0x0000000c, 0x00000000 },
8938 + { 0x00000030, 0x00020015 },
8939 + { 0x00000034, 0x00000005 },
8940 + { 0x00000040, 0x00000000 },
8941 + { 0x00000044, 0x00000008 },
8942 + { 0x00000048, 0x00000008 },
8943 + { 0x0000004c, 0x00000010 },
8944 + { 0x00000050, 0x00000000 },
8945 + { 0x00000054, 0x0000001f },
8946 + { 0x00000800, 0x00000000 },
8947 + { 0x00000804, 0x00000000 },
8948 + { 0x00000808, 0x00000000 },
8949 + { 0x0000080c, 0x00000000 },
8950 + { 0x00000810, 0x00000000 },
8951 + { 0x00000814, 0x00000000 },
8952 + { 0x00000818, 0x00000000 },
8953 + { 0x0000081c, 0x00000000 },
8954 + { 0x00000820, 0x00000000 },
8955 + { 0x00000824, 0x00000000 },
8956 + { 0x00001040, 0x002ffc0f },
8957 + { 0x00001044, 0x002ffc0f },
8958 + { 0x00001048, 0x002ffc0f },
8959 + { 0x0000104c, 0x002ffc0f },
8960 + { 0x00001050, 0x002ffc0f },
8961 + { 0x00001054, 0x002ffc0f },
8962 + { 0x00001058, 0x002ffc0f },
8963 + { 0x0000105c, 0x002ffc0f },
8964 + { 0x00001060, 0x002ffc0f },
8965 + { 0x00001064, 0x002ffc0f },
8966 + { 0x00001230, 0x00000000 },
8967 + { 0x00001270, 0x00000000 },
8968 + { 0x00001038, 0x00000000 },
8969 + { 0x00001078, 0x00000000 },
8970 + { 0x000010b8, 0x00000000 },
8971 + { 0x000010f8, 0x00000000 },
8972 + { 0x00001138, 0x00000000 },
8973 + { 0x00001178, 0x00000000 },
8974 + { 0x000011b8, 0x00000000 },
8975 + { 0x000011f8, 0x00000000 },
8976 + { 0x00001238, 0x00000000 },
8977 + { 0x00001278, 0x00000000 },
8978 + { 0x000012b8, 0x00000000 },
8979 + { 0x000012f8, 0x00000000 },
8980 + { 0x00001338, 0x00000000 },
8981 + { 0x00001378, 0x00000000 },
8982 + { 0x000013b8, 0x00000000 },
8983 + { 0x000013f8, 0x00000000 },
8984 + { 0x00001438, 0x00000000 },
8985 + { 0x00001478, 0x00000000 },
8986 + { 0x000014b8, 0x00000000 },
8987 + { 0x000014f8, 0x00000000 },
8988 + { 0x00001538, 0x00000000 },
8989 + { 0x00001578, 0x00000000 },
8990 + { 0x000015b8, 0x00000000 },
8991 + { 0x000015f8, 0x00000000 },
8992 + { 0x00001638, 0x00000000 },
8993 + { 0x00001678, 0x00000000 },
8994 + { 0x000016b8, 0x00000000 },
8995 + { 0x000016f8, 0x00000000 },
8996 + { 0x00001738, 0x00000000 },
8997 + { 0x00001778, 0x00000000 },
8998 + { 0x000017b8, 0x00000000 },
8999 + { 0x000017f8, 0x00000000 },
9000 + { 0x0000103c, 0x00000000 },
9001 + { 0x0000107c, 0x00000000 },
9002 + { 0x000010bc, 0x00000000 },
9003 + { 0x000010fc, 0x00000000 },
9004 + { 0x0000113c, 0x00000000 },
9005 + { 0x0000117c, 0x00000000 },
9006 + { 0x000011bc, 0x00000000 },
9007 + { 0x000011fc, 0x00000000 },
9008 + { 0x0000123c, 0x00000000 },
9009 + { 0x0000127c, 0x00000000 },
9010 + { 0x000012bc, 0x00000000 },
9011 + { 0x000012fc, 0x00000000 },
9012 + { 0x0000133c, 0x00000000 },
9013 + { 0x0000137c, 0x00000000 },
9014 + { 0x000013bc, 0x00000000 },
9015 + { 0x000013fc, 0x00000000 },
9016 + { 0x0000143c, 0x00000000 },
9017 + { 0x0000147c, 0x00000000 },
9018 + { 0x00004030, 0x00000002 },
9019 + { 0x0000403c, 0x00000002 },
9020 + { 0x00004024, 0x0000001f },
9021 + { 0x00004060, 0x00000000 },
9022 + { 0x00004064, 0x00000000 },
9023 + { 0x00007010, 0x00000033 },
9024 + { 0x00007020, 0x00000000 },
9025 + { 0x00007034, 0x00000002 },
9026 + { 0x00007038, 0x000004c2 },
9027 + { 0x00008004, 0x00000000 },
9028 + { 0x00008008, 0x00000000 },
9029 + { 0x0000800c, 0x00000000 },
9030 + { 0x00008018, 0x00000700 },
9031 + { 0x00008020, 0x00000000 },
9032 + { 0x00008038, 0x00000000 },
9033 + { 0x0000803c, 0x00000000 },
9034 + { 0x00008048, 0x40000000 },
9035 + { 0x00008054, 0x00000000 },
9036 + { 0x00008058, 0x00000000 },
9037 + { 0x0000805c, 0x000fc78f },
9038 + { 0x00008060, 0x0000000f },
9039 + { 0x00008064, 0x00000000 },
9040 + { 0x00008070, 0x00000000 },
9041 + { 0x000080c0, 0x2a80001a },
9042 + { 0x000080c4, 0x05dc01e0 },
9043 + { 0x000080c8, 0x1f402710 },
9044 + { 0x000080cc, 0x01f40000 },
9045 + { 0x000080d0, 0x00001e00 },
9046 + { 0x000080d4, 0x00000000 },
9047 + { 0x000080d8, 0x00400000 },
9048 + { 0x000080e0, 0xffffffff },
9049 + { 0x000080e4, 0x0000ffff },
9050 + { 0x000080e8, 0x003f3f3f },
9051 + { 0x000080ec, 0x00000000 },
9052 + { 0x000080f0, 0x00000000 },
9053 + { 0x000080f4, 0x00000000 },
9054 + { 0x000080f8, 0x00000000 },
9055 + { 0x000080fc, 0x00020000 },
9056 + { 0x00008100, 0x00020000 },
9057 + { 0x00008104, 0x00000001 },
9058 + { 0x00008108, 0x00000052 },
9059 + { 0x0000810c, 0x00000000 },
9060 + { 0x00008110, 0x00000168 },
9061 + { 0x00008118, 0x000100aa },
9062 + { 0x0000811c, 0x00003210 },
9063 + { 0x00008124, 0x00000000 },
9064 + { 0x00008128, 0x00000000 },
9065 + { 0x0000812c, 0x00000000 },
9066 + { 0x00008130, 0x00000000 },
9067 + { 0x00008134, 0x00000000 },
9068 + { 0x00008138, 0x00000000 },
9069 + { 0x0000813c, 0x00000000 },
9070 + { 0x00008144, 0xffffffff },
9071 + { 0x00008168, 0x00000000 },
9072 + { 0x0000816c, 0x00000000 },
9073 + { 0x00008170, 0x18487320 },
9074 + { 0x00008174, 0xfaa4fa50 },
9075 + { 0x00008178, 0x00000100 },
9076 + { 0x0000817c, 0x00000000 },
9077 + { 0x000081c0, 0x00000000 },
9078 + { 0x000081c4, 0x00000000 },
9079 + { 0x000081d4, 0x00000000 },
9080 + { 0x000081ec, 0x00000000 },
9081 + { 0x000081f0, 0x00000000 },
9082 + { 0x000081f4, 0x00000000 },
9083 + { 0x000081f8, 0x00000000 },
9084 + { 0x000081fc, 0x00000000 },
9085 + { 0x00008200, 0x00000000 },
9086 + { 0x00008204, 0x00000000 },
9087 + { 0x00008208, 0x00000000 },
9088 + { 0x0000820c, 0x00000000 },
9089 + { 0x00008210, 0x00000000 },
9090 + { 0x00008214, 0x00000000 },
9091 + { 0x00008218, 0x00000000 },
9092 + { 0x0000821c, 0x00000000 },
9093 + { 0x00008220, 0x00000000 },
9094 + { 0x00008224, 0x00000000 },
9095 + { 0x00008228, 0x00000000 },
9096 + { 0x0000822c, 0x00000000 },
9097 + { 0x00008230, 0x00000000 },
9098 + { 0x00008234, 0x00000000 },
9099 + { 0x00008238, 0x00000000 },
9100 + { 0x0000823c, 0x00000000 },
9101 + { 0x00008240, 0x00100000 },
9102 + { 0x00008244, 0x0010f400 },
9103 + { 0x00008248, 0x00000100 },
9104 + { 0x0000824c, 0x0001e800 },
9105 + { 0x00008250, 0x00000000 },
9106 + { 0x00008254, 0x00000000 },
9107 + { 0x00008258, 0x00000000 },
9108 + { 0x0000825c, 0x400000ff },
9109 + { 0x00008260, 0x00080922 },
9110 + { 0x00008264, 0x88a00010 },
9111 + { 0x00008270, 0x00000000 },
9112 + { 0x00008274, 0x40000000 },
9113 + { 0x00008278, 0x003e4180 },
9114 + { 0x0000827c, 0x00000000 },
9115 + { 0x00008284, 0x0000002c },
9116 + { 0x00008288, 0x0000002c },
9117 + { 0x0000828c, 0x000000ff },
9118 + { 0x00008294, 0x00000000 },
9119 + { 0x00008298, 0x00000000 },
9120 + { 0x0000829c, 0x00000000 },
9121 + { 0x00008300, 0x00000040 },
9122 + { 0x00008314, 0x00000000 },
9123 + { 0x00008328, 0x00000000 },
9124 + { 0x0000832c, 0x00000007 },
9125 + { 0x00008330, 0x00000302 },
9126 + { 0x00008334, 0x00000e00 },
9127 + { 0x00008338, 0x00ff0000 },
9128 + { 0x0000833c, 0x00000000 },
9129 + { 0x00008340, 0x000107ff },
9130 + { 0x00008344, 0x01c81043 },
9131 + { 0x00008360, 0xffffffff },
9132 + { 0x00008364, 0xffffffff },
9133 + { 0x00008368, 0x00000000 },
9134 + { 0x00008370, 0x00000000 },
9135 + { 0x00008374, 0x000000ff },
9136 + { 0x00008378, 0x00000000 },
9137 + { 0x0000837c, 0x00000000 },
9138 + { 0x00008380, 0xffffffff },
9139 + { 0x00008384, 0xffffffff },
9140 + { 0x00008390, 0x0fffffff },
9141 + { 0x00008394, 0x0fffffff },
9142 + { 0x00008398, 0x00000000 },
9143 + { 0x0000839c, 0x00000000 },
9144 + { 0x000083a0, 0x00000000 },
9145 + { 0x00009808, 0x00000000 },
9146 + { 0x0000980c, 0xafe68e30 },
9147 + { 0x00009810, 0xfd14e000 },
9148 + { 0x00009814, 0x9c0a9f6b },
9149 + { 0x0000981c, 0x00000000 },
9150 + { 0x0000982c, 0x0000a000 },
9151 + { 0x00009830, 0x00000000 },
9152 + { 0x0000983c, 0x00200400 },
9153 + { 0x0000984c, 0x0040233c },
9154 + { 0x0000a84c, 0x0040233c },
9155 + { 0x00009854, 0x00000044 },
9156 + { 0x00009900, 0x00000000 },
9157 + { 0x00009904, 0x00000000 },
9158 + { 0x00009908, 0x00000000 },
9159 + { 0x0000990c, 0x00000000 },
9160 + { 0x00009910, 0x10002310 },
9161 + { 0x0000991c, 0x10000fff },
9162 + { 0x00009920, 0x04900000 },
9163 + { 0x0000a920, 0x04900000 },
9164 + { 0x00009928, 0x00000001 },
9165 + { 0x0000992c, 0x00000004 },
9166 + { 0x00009930, 0x00000000 },
9167 + { 0x0000a930, 0x00000000 },
9168 + { 0x00009934, 0x1e1f2022 },
9169 + { 0x00009938, 0x0a0b0c0d },
9170 + { 0x0000993c, 0x00000000 },
9171 + { 0x00009948, 0x9280c00a },
9172 + { 0x0000994c, 0x00020028 },
9173 + { 0x00009954, 0x5f3ca3de },
9174 + { 0x00009958, 0x0108ecff },
9175 + { 0x00009940, 0x14750604 },
9176 + { 0x0000c95c, 0x004b6a8e },
9177 + { 0x00009970, 0x990bb514 },
9178 + { 0x00009974, 0x00000000 },
9179 + { 0x00009978, 0x00000001 },
9180 + { 0x0000997c, 0x00000000 },
9181 + { 0x000099a0, 0x00000000 },
9182 + { 0x000099a4, 0x00000001 },
9183 + { 0x000099a8, 0x201fff00 },
9184 + { 0x000099ac, 0x0c6f0000 },
9185 + { 0x000099b0, 0x03051000 },
9186 + { 0x000099b4, 0x00000820 },
9187 + { 0x000099c4, 0x06336f77 },
9188 + { 0x000099c8, 0x6af6532f },
9189 + { 0x000099cc, 0x08f186c8 },
9190 + { 0x000099d0, 0x00046384 },
9191 + { 0x000099dc, 0x00000000 },
9192 + { 0x000099e0, 0x00000000 },
9193 + { 0x000099e4, 0xaaaaaaaa },
9194 + { 0x000099e8, 0x3c466478 },
9195 + { 0x000099ec, 0x0cc80caa },
9196 + { 0x000099f0, 0x00000000 },
9197 + { 0x000099fc, 0x00001042 },
9198 + { 0x0000a208, 0x803e4788 },
9199 + { 0x0000a210, 0x4080a333 },
9200 + { 0x0000a214, 0x40206c10 },
9201 + { 0x0000a218, 0x009c4060 },
9202 + { 0x0000a220, 0x01834061 },
9203 + { 0x0000a224, 0x00000400 },
9204 + { 0x0000a228, 0x000003b5 },
9205 + { 0x0000a22c, 0x233f7180 },
9206 + { 0x0000a234, 0x20202020 },
9207 + { 0x0000a238, 0x20202020 },
9208 + { 0x0000a23c, 0x13c889af },
9209 + { 0x0000a240, 0x38490a20 },
9210 + { 0x0000a244, 0x00000000 },
9211 + { 0x0000a248, 0xfffffffc },
9212 + { 0x0000a24c, 0x00000000 },
9213 + { 0x0000a254, 0x00000000 },
9214 + { 0x0000a258, 0x0cdbd380 },
9215 + { 0x0000a25c, 0x0f0f0f01 },
9216 + { 0x0000a260, 0xdfa91f01 },
9217 + { 0x0000a264, 0x00418a11 },
9218 + { 0x0000b264, 0x00418a11 },
9219 + { 0x0000a268, 0x00000000 },
9220 + { 0x0000a26c, 0x0e79e5c6 },
9221 + { 0x0000b26c, 0x0e79e5c6 },
9222 + { 0x0000d270, 0x00820820 },
9223 + { 0x0000a278, 0x1ce739ce },
9224 + { 0x0000a27c, 0x050701ce },
9225 + { 0x0000d35c, 0x07ffffef },
9226 + { 0x0000d360, 0x0fffffe7 },
9227 + { 0x0000d364, 0x17ffffe5 },
9228 + { 0x0000d368, 0x1fffffe4 },
9229 + { 0x0000d36c, 0x37ffffe3 },
9230 + { 0x0000d370, 0x3fffffe3 },
9231 + { 0x0000d374, 0x57ffffe3 },
9232 + { 0x0000d378, 0x5fffffe2 },
9233 + { 0x0000d37c, 0x7fffffe2 },
9234 + { 0x0000d380, 0x7f3c7bba },
9235 + { 0x0000d384, 0xf3307ff0 },
9236 + { 0x0000a388, 0x0c000000 },
9237 + { 0x0000a38c, 0x20202020 },
9238 + { 0x0000a390, 0x20202020 },
9239 + { 0x0000a394, 0x1ce739ce },
9240 + { 0x0000a398, 0x000001ce },
9241 + { 0x0000b398, 0x000001ce },
9242 + { 0x0000a39c, 0x00000001 },
9243 + { 0x0000a3c8, 0x00000246 },
9244 + { 0x0000a3cc, 0x20202020 },
9245 + { 0x0000a3d0, 0x20202020 },
9246 + { 0x0000a3d4, 0x20202020 },
9247 + { 0x0000a3dc, 0x1ce739ce },
9248 + { 0x0000a3e0, 0x000001ce },
9249 + { 0x0000a3e4, 0x00000000 },
9250 + { 0x0000a3e8, 0x18c43433 },
9251 + { 0x0000a3ec, 0x00f70081 },
9252 + { 0x0000a3f0, 0x01036a1e },
9253 + { 0x0000a3f4, 0x00000000 },
9254 + { 0x0000b3f4, 0x00000000 },
9255 + { 0x0000a7d8, 0x000003f1 },
9256 + { 0x00007800, 0x00000800 },
9257 + { 0x00007804, 0x6c35ffd2 },
9258 + { 0x00007808, 0x6db6c000 },
9259 + { 0x0000780c, 0x6db6cb30 },
9260 + { 0x00007810, 0x6db6cb6c },
9261 + { 0x00007814, 0x0501e200 },
9262 + { 0x00007818, 0x0094128d },
9263 + { 0x0000781c, 0x976ee392 },
9264 + { 0x00007820, 0xf75ff6fc },
9265 + { 0x00007824, 0x00040000 },
9266 + { 0x00007828, 0xdb003012 },
9267 + { 0x0000782c, 0x04924914 },
9268 + { 0x00007830, 0x21084210 },
9269 + { 0x00007834, 0x00140000 },
9270 + { 0x00007838, 0x0e4548d8 },
9271 + { 0x0000783c, 0x54214514 },
9272 + { 0x00007840, 0x02025830 },
9273 + { 0x00007844, 0x71c0d388 },
9274 + { 0x00007848, 0x934934a8 },
9275 + { 0x00007850, 0x00000000 },
9276 + { 0x00007854, 0x00000800 },
9277 + { 0x00007858, 0x6c35ffd2 },
9278 + { 0x0000785c, 0x6db6c000 },
9279 + { 0x00007860, 0x6db6cb30 },
9280 + { 0x00007864, 0x6db6cb6c },
9281 + { 0x00007868, 0x0501e200 },
9282 + { 0x0000786c, 0x0094128d },
9283 + { 0x00007870, 0x976ee392 },
9284 + { 0x00007874, 0xf75ff6fc },
9285 + { 0x00007878, 0x00040000 },
9286 + { 0x0000787c, 0xdb003012 },
9287 + { 0x00007880, 0x04924914 },
9288 + { 0x00007884, 0x21084210 },
9289 + { 0x00007888, 0x001b6db0 },
9290 + { 0x0000788c, 0x00376b63 },
9291 + { 0x00007890, 0x06db6db6 },
9292 + { 0x00007894, 0x006d8000 },
9293 + { 0x00007898, 0x48100000 },
9294 + { 0x0000789c, 0x00000000 },
9295 + { 0x000078a0, 0x08000000 },
9296 + { 0x000078a4, 0x0007ffd8 },
9297 + { 0x000078a8, 0x0007ffd8 },
9298 + { 0x000078ac, 0x001c0020 },
9299 + { 0x000078b0, 0x00060aeb },
9300 + { 0x000078b4, 0x40008080 },
9301 + { 0x000078b8, 0x2a850160 },
9302 +};
9303 +
9304 +/*
9305 + * For Japanese regulatory requirements, 2484 MHz requires the following three
9306 + * registers be programmed differently from the channel between 2412 and 2472 MHz.
9307 + */
9308 +static const u_int32_t ar9287Common_normal_cck_fir_coeff_92871_1[][2] = {
9309 + { 0x0000a1f4, 0x00fffeff },
9310 + { 0x0000a1f8, 0x00f5f9ff },
9311 + { 0x0000a1fc, 0xb79f6427 },
9312 +};
9313 +
9314 +static const u_int32_t ar9287Common_japan_2484_cck_fir_coeff_92871_1[][2] = {
9315 + { 0x0000a1f4, 0x00000000 },
9316 + { 0x0000a1f8, 0xefff0301 },
9317 + { 0x0000a1fc, 0xca9228ee },
9318 +};
9319 +
9320 +static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = {
9321 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
9322 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
9323 + { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 },
9324 + { 0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004 },
9325 + { 0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a, 0x0000c00a },
9326 + { 0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c, 0x0001000c },
9327 + { 0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b, 0x0001420b },
9328 + { 0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a, 0x0001824a },
9329 + { 0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a, 0x0001c44a },
9330 + { 0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a, 0x0002064a },
9331 + { 0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a, 0x0002484a },
9332 + { 0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a, 0x00028a4a },
9333 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a },
9334 + { 0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a, 0x00030e4a },
9335 + { 0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a, 0x00034e8a },
9336 + { 0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c, 0x00038e8c },
9337 + { 0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc, 0x0003cecc },
9338 + { 0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4, 0x00040ed4 },
9339 + { 0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc, 0x00044edc },
9340 + { 0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede, 0x00048ede },
9341 + { 0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e },
9342 + { 0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e, 0x00050f5e },
9343 + { 0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e, 0x00054f9e },
9344 + { 0x0000a780, 0x00000000, 0x00000000, 0x00000062, 0x00000062, 0x00000062 },
9345 + { 0x0000a784, 0x00000000, 0x00000000, 0x00004064, 0x00004064, 0x00004064 },
9346 + { 0x0000a788, 0x00000000, 0x00000000, 0x000080a4, 0x000080a4, 0x000080a4 },
9347 + { 0x0000a78c, 0x00000000, 0x00000000, 0x0000c0aa, 0x0000c0aa, 0x0000c0aa },
9348 + { 0x0000a790, 0x00000000, 0x00000000, 0x000100ac, 0x000100ac, 0x000100ac },
9349 + { 0x0000a794, 0x00000000, 0x00000000, 0x000140b4, 0x000140b4, 0x000140b4 },
9350 + { 0x0000a798, 0x00000000, 0x00000000, 0x000180f4, 0x000180f4, 0x000180f4 },
9351 + { 0x0000a79c, 0x00000000, 0x00000000, 0x0001c134, 0x0001c134, 0x0001c134 },
9352 + { 0x0000a7a0, 0x00000000, 0x00000000, 0x00020174, 0x00020174, 0x00020174 },
9353 + { 0x0000a7a4, 0x00000000, 0x00000000, 0x0002417c, 0x0002417c, 0x0002417c },
9354 + { 0x0000a7a8, 0x00000000, 0x00000000, 0x0002817e, 0x0002817e, 0x0002817e },
9355 + { 0x0000a7ac, 0x00000000, 0x00000000, 0x0002c1be, 0x0002c1be, 0x0002c1be },
9356 + { 0x0000a7b0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9357 + { 0x0000a7b4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9358 + { 0x0000a7b8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9359 + { 0x0000a7bc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9360 + { 0x0000a7c0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9361 + { 0x0000a7c4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9362 + { 0x0000a7c8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9363 + { 0x0000a7cc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9364 + { 0x0000a7d0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9365 + { 0x0000a7d4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9366 + { 0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000 },
9367 +};
9368 +
9369 +static const u_int32_t ar9287Modes_rx_gain_9287_1_1[][6] = {
9370 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
9371 + { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
9372 + { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
9373 + { 0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
9374 + { 0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
9375 + { 0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
9376 + { 0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
9377 + { 0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
9378 + { 0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
9379 + { 0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
9380 + { 0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
9381 + { 0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
9382 + { 0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
9383 + { 0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
9384 + { 0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
9385 + { 0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
9386 + { 0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
9387 + { 0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
9388 + { 0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
9389 + { 0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
9390 + { 0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
9391 + { 0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
9392 + { 0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
9393 + { 0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
9394 + { 0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
9395 + { 0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
9396 + { 0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
9397 + { 0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
9398 + { 0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
9399 + { 0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
9400 + { 0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
9401 + { 0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
9402 + { 0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
9403 + { 0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
9404 + { 0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
9405 + { 0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
9406 + { 0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
9407 + { 0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
9408 + { 0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
9409 + { 0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
9410 + { 0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
9411 + { 0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
9412 + { 0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
9413 + { 0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
9414 + { 0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
9415 + { 0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
9416 + { 0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
9417 + { 0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
9418 + { 0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
9419 + { 0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
9420 + { 0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
9421 + { 0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
9422 + { 0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
9423 + { 0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
9424 + { 0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
9425 + { 0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
9426 + { 0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
9427 + { 0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
9428 + { 0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
9429 + { 0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
9430 + { 0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
9431 + { 0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
9432 + { 0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
9433 + { 0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
9434 + { 0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
9435 + { 0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
9436 + { 0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
9437 + { 0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
9438 + { 0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
9439 + { 0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
9440 + { 0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
9441 + { 0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
9442 + { 0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
9443 + { 0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
9444 + { 0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
9445 + { 0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
9446 + { 0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
9447 + { 0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
9448 + { 0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
9449 + { 0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
9450 + { 0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
9451 + { 0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
9452 + { 0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
9453 + { 0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
9454 + { 0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
9455 + { 0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
9456 + { 0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
9457 + { 0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
9458 + { 0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
9459 + { 0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
9460 + { 0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
9461 + { 0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
9462 + { 0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
9463 + { 0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
9464 + { 0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
9465 + { 0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
9466 + { 0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
9467 + { 0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
9468 + { 0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
9469 + { 0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
9470 + { 0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
9471 + { 0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
9472 + { 0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
9473 + { 0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
9474 + { 0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9475 + { 0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9476 + { 0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9477 + { 0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9478 + { 0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9479 + { 0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9480 + { 0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9481 + { 0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9482 + { 0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9483 + { 0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9484 + { 0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9485 + { 0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9486 + { 0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9487 + { 0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9488 + { 0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9489 + { 0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9490 + { 0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9491 + { 0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9492 + { 0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9493 + { 0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9494 + { 0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9495 + { 0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9496 + { 0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9497 + { 0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9498 + { 0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9499 + { 0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
9500 + { 0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
9501 + { 0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
9502 + { 0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
9503 + { 0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
9504 + { 0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
9505 + { 0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
9506 + { 0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
9507 + { 0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
9508 + { 0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
9509 + { 0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
9510 + { 0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
9511 + { 0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
9512 + { 0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
9513 + { 0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
9514 + { 0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
9515 + { 0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
9516 + { 0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
9517 + { 0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
9518 + { 0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
9519 + { 0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
9520 + { 0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
9521 + { 0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
9522 + { 0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
9523 + { 0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
9524 + { 0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
9525 + { 0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
9526 + { 0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
9527 + { 0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
9528 + { 0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
9529 + { 0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
9530 + { 0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
9531 + { 0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
9532 + { 0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
9533 + { 0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
9534 + { 0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
9535 + { 0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
9536 + { 0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
9537 + { 0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
9538 + { 0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
9539 + { 0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
9540 + { 0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
9541 + { 0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
9542 + { 0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
9543 + { 0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
9544 + { 0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
9545 + { 0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
9546 + { 0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
9547 + { 0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
9548 + { 0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
9549 + { 0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
9550 + { 0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
9551 + { 0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
9552 + { 0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
9553 + { 0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
9554 + { 0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
9555 + { 0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
9556 + { 0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
9557 + { 0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
9558 + { 0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
9559 + { 0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
9560 + { 0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
9561 + { 0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
9562 + { 0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
9563 + { 0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
9564 + { 0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
9565 + { 0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
9566 + { 0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
9567 + { 0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
9568 + { 0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
9569 + { 0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
9570 + { 0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
9571 + { 0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
9572 + { 0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
9573 + { 0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
9574 + { 0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
9575 + { 0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
9576 + { 0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
9577 + { 0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
9578 + { 0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
9579 + { 0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
9580 + { 0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
9581 + { 0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
9582 + { 0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
9583 + { 0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
9584 + { 0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
9585 + { 0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
9586 + { 0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
9587 + { 0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
9588 + { 0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
9589 + { 0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
9590 + { 0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
9591 + { 0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
9592 + { 0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
9593 + { 0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
9594 + { 0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
9595 + { 0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
9596 + { 0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
9597 + { 0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
9598 + { 0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
9599 + { 0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
9600 + { 0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
9601 + { 0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
9602 + { 0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9603 + { 0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9604 + { 0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9605 + { 0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9606 + { 0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9607 + { 0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9608 + { 0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9609 + { 0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9610 + { 0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9611 + { 0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9612 + { 0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9613 + { 0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9614 + { 0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9615 + { 0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9616 + { 0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9617 + { 0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9618 + { 0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9619 + { 0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9620 + { 0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9621 + { 0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9622 + { 0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9623 + { 0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9624 + { 0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9625 + { 0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9626 + { 0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9627 + { 0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
9628 + { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
9629 +};
9630 +
9631 +static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
9632 + {0x00004040, 0x9248fd00 },
9633 + {0x00004040, 0x24924924 },
9634 + {0x00004040, 0xa8000019 },
9635 + {0x00004040, 0x13160820 },
9636 + {0x00004040, 0xe5980560 },
9637 + {0x00004040, 0xc01dcffd },
9638 + {0x00004040, 0x1aaabe41 },
9639 + {0x00004040, 0xbe105554 },
9640 + {0x00004040, 0x00043007 },
9641 + {0x00004044, 0x00000000 },
9642 +};
9643 +
9644 +static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
9645 + {0x00004040, 0x9248fd00 },
9646 + {0x00004040, 0x24924924 },
9647 + {0x00004040, 0xa8000019 },
9648 + {0x00004040, 0x13160820 },
9649 + {0x00004040, 0xe5980560 },
9650 + {0x00004040, 0xc01dcffc },
9651 + {0x00004040, 0x1aaabe41 },
9652 + {0x00004040, 0xbe105554 },
9653 + {0x00004040, 0x00043007 },
9654 + {0x00004044, 0x00000000 },
9655 +};
9656 +
9657 +
9658 +/* AR9271 initialization values automaticaly created: 06/04/09 */
9659 +static const u_int32_t ar9271Modes_9271[][6] = {
9660 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
9661 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
9662 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
9663 + { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
9664 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
9665 + { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
9666 + { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
9667 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
9668 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
9669 + { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
9670 + { 0x00009828, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001 },
9671 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
9672 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
9673 + { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
9674 + { 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
9675 + { 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
9676 + { 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
9677 + { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
9678 + { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
9679 + { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
9680 + { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18 },
9681 + { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
9682 + { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
9683 + { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
9684 + { 0x00009910, 0x30002310, 0x30002310, 0x30002310, 0x30002310, 0x30002310 },
9685 + { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
9686 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
9687 + { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
9688 + { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
9689 + { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
9690 + { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
9691 + { 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
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9877 + { 0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
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9899 + { 0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
9900 + { 0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
9901 + { 0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
9902 + { 0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
9903 + { 0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
9904 + { 0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
9905 + { 0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
9906 + { 0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
9907 + { 0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
9908 + { 0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
9909 + { 0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
9910 + { 0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
9911 + { 0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
9912 + { 0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
9913 + { 0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
9914 + { 0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
9915 + { 0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
9916 + { 0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
9917 + { 0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9918 + { 0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9919 + { 0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9920 + { 0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9921 + { 0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9922 + { 0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9923 + { 0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9924 + { 0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9925 + { 0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9926 + { 0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9927 + { 0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9928 + { 0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9929 + { 0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9930 + { 0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9931 + { 0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9932 + { 0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9933 + { 0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9934 + { 0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9935 + { 0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9936 + { 0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9937 + { 0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9938 + { 0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9939 + { 0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9940 + { 0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9941 + { 0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9942 + { 0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9943 + { 0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9944 + { 0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9945 + { 0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9946 + { 0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9947 + { 0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9948 + { 0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9949 + { 0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9950 + { 0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9951 + { 0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9952 + { 0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9953 + { 0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9954 + { 0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9955 + { 0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9956 + { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
9957 + { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
9958 + { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
9959 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
9960 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
9961 + { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
9962 + { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
9963 +};
9964 +
9965 +static const u_int32_t ar9271Common_9271[][2] = {
9966 + { 0x0000000c, 0x00000000 },
9967 + { 0x00000030, 0x00020045 },
9968 + { 0x00000034, 0x00000005 },
9969 + { 0x00000040, 0x00000000 },
9970 + { 0x00000044, 0x00000008 },
9971 + { 0x00000048, 0x00000008 },
9972 + { 0x0000004c, 0x00000010 },
9973 + { 0x00000050, 0x00000000 },
9974 + { 0x00000054, 0x0000001f },
9975 + { 0x00000800, 0x00000000 },
9976 + { 0x00000804, 0x00000000 },
9977 + { 0x00000808, 0x00000000 },
9978 + { 0x0000080c, 0x00000000 },
9979 + { 0x00000810, 0x00000000 },
9980 + { 0x00000814, 0x00000000 },
9981 + { 0x00000818, 0x00000000 },
9982 + { 0x0000081c, 0x00000000 },
9983 + { 0x00000820, 0x00000000 },
9984 + { 0x00000824, 0x00000000 },
9985 + { 0x00001040, 0x002ffc0f },
9986 + { 0x00001044, 0x002ffc0f },
9987 + { 0x00001048, 0x002ffc0f },
9988 + { 0x0000104c, 0x002ffc0f },
9989 + { 0x00001050, 0x002ffc0f },
9990 + { 0x00001054, 0x002ffc0f },
9991 + { 0x00001058, 0x002ffc0f },
9992 + { 0x0000105c, 0x002ffc0f },
9993 + { 0x00001060, 0x002ffc0f },
9994 + { 0x00001064, 0x002ffc0f },
9995 + { 0x00001230, 0x00000000 },
9996 + { 0x00001270, 0x00000000 },
9997 + { 0x00001038, 0x00000000 },
9998 + { 0x00001078, 0x00000000 },
9999 + { 0x000010b8, 0x00000000 },
10000 + { 0x000010f8, 0x00000000 },
10001 + { 0x00001138, 0x00000000 },
10002 + { 0x00001178, 0x00000000 },
10003 + { 0x000011b8, 0x00000000 },
10004 + { 0x000011f8, 0x00000000 },
10005 + { 0x00001238, 0x00000000 },
10006 + { 0x00001278, 0x00000000 },
10007 + { 0x000012b8, 0x00000000 },
10008 + { 0x000012f8, 0x00000000 },
10009 + { 0x00001338, 0x00000000 },
10010 + { 0x00001378, 0x00000000 },
10011 + { 0x000013b8, 0x00000000 },
10012 + { 0x000013f8, 0x00000000 },
10013 + { 0x00001438, 0x00000000 },
10014 + { 0x00001478, 0x00000000 },
10015 + { 0x000014b8, 0x00000000 },
10016 + { 0x000014f8, 0x00000000 },
10017 + { 0x00001538, 0x00000000 },
10018 + { 0x00001578, 0x00000000 },
10019 + { 0x000015b8, 0x00000000 },
10020 + { 0x000015f8, 0x00000000 },
10021 + { 0x00001638, 0x00000000 },
10022 + { 0x00001678, 0x00000000 },
10023 + { 0x000016b8, 0x00000000 },
10024 + { 0x000016f8, 0x00000000 },
10025 + { 0x00001738, 0x00000000 },
10026 + { 0x00001778, 0x00000000 },
10027 + { 0x000017b8, 0x00000000 },
10028 + { 0x000017f8, 0x00000000 },
10029 + { 0x0000103c, 0x00000000 },
10030 + { 0x0000107c, 0x00000000 },
10031 + { 0x000010bc, 0x00000000 },
10032 + { 0x000010fc, 0x00000000 },
10033 + { 0x0000113c, 0x00000000 },
10034 + { 0x0000117c, 0x00000000 },
10035 + { 0x000011bc, 0x00000000 },
10036 + { 0x000011fc, 0x00000000 },
10037 + { 0x0000123c, 0x00000000 },
10038 + { 0x0000127c, 0x00000000 },
10039 + { 0x000012bc, 0x00000000 },
10040 + { 0x000012fc, 0x00000000 },
10041 + { 0x0000133c, 0x00000000 },
10042 + { 0x0000137c, 0x00000000 },
10043 + { 0x000013bc, 0x00000000 },
10044 + { 0x000013fc, 0x00000000 },
10045 + { 0x0000143c, 0x00000000 },
10046 + { 0x0000147c, 0x00000000 },
10047 + { 0x00004030, 0x00000002 },
10048 + { 0x0000403c, 0x00000002 },
10049 + { 0x00004024, 0x0000001f },
10050 + { 0x00004060, 0x00000000 },
10051 + { 0x00004064, 0x00000000 },
10052 + { 0x00008004, 0x00000000 },
10053 + { 0x00008008, 0x00000000 },
10054 + { 0x0000800c, 0x00000000 },
10055 + { 0x00008018, 0x00000700 },
10056 + { 0x00008020, 0x00000000 },
10057 + { 0x00008038, 0x00000000 },
10058 + { 0x0000803c, 0x00000000 },
10059 + { 0x00008048, 0x00000000 },
10060 + { 0x00008054, 0x00000000 },
10061 + { 0x00008058, 0x00000000 },
10062 + { 0x0000805c, 0x000fc78f },
10063 + { 0x00008060, 0x0000000f },
10064 + { 0x00008064, 0x00000000 },
10065 + { 0x00008070, 0x00000000 },
10066 + { 0x000080b0, 0x00000000 },
10067 + { 0x000080b4, 0x00000000 },
10068 + { 0x000080b8, 0x00000000 },
10069 + { 0x000080bc, 0x00000000 },
10070 + { 0x000080c0, 0x2a80001a },
10071 + { 0x000080c4, 0x05dc01e0 },
10072 + { 0x000080c8, 0x1f402710 },
10073 + { 0x000080cc, 0x01f40000 },
10074 + { 0x000080d0, 0x00001e00 },
10075 + { 0x000080d4, 0x00000000 },
10076 + { 0x000080d8, 0x00400000 },
10077 + { 0x000080e0, 0xffffffff },
10078 + { 0x000080e4, 0x0000ffff },
10079 + { 0x000080e8, 0x003f3f3f },
10080 + { 0x000080ec, 0x00000000 },
10081 + { 0x000080f0, 0x00000000 },
10082 + { 0x000080f4, 0x00000000 },
10083 + { 0x000080f8, 0x00000000 },
10084 + { 0x000080fc, 0x00020000 },
10085 + { 0x00008100, 0x00020000 },
10086 + { 0x00008104, 0x00000001 },
10087 + { 0x00008108, 0x00000052 },
10088 + { 0x0000810c, 0x00000000 },
10089 + { 0x00008110, 0x00000168 },
10090 + { 0x00008118, 0x000100aa },
10091 + { 0x0000811c, 0x00003210 },
10092 + { 0x00008120, 0x08f04810 },
10093 + { 0x00008124, 0x00000000 },
10094 + { 0x00008128, 0x00000000 },
10095 + { 0x0000812c, 0x00000000 },
10096 + { 0x00008130, 0x00000000 },
10097 + { 0x00008134, 0x00000000 },
10098 + { 0x00008138, 0x00000000 },
10099 + { 0x0000813c, 0x00000000 },
10100 + { 0x00008144, 0xffffffff },
10101 + { 0x00008168, 0x00000000 },
10102 + { 0x0000816c, 0x00000000 },
10103 + { 0x00008170, 0x32143320 },
10104 + { 0x00008174, 0xfaa4fa50 },
10105 + { 0x00008178, 0x00000100 },
10106 + { 0x0000817c, 0x00000000 },
10107 + { 0x000081c0, 0x00000000 },
10108 + { 0x000081d0, 0x0000320a },
10109 + { 0x000081ec, 0x00000000 },
10110 + { 0x000081f0, 0x00000000 },
10111 + { 0x000081f4, 0x00000000 },
10112 + { 0x000081f8, 0x00000000 },
10113 + { 0x000081fc, 0x00000000 },
10114 + { 0x00008200, 0x00000000 },
10115 + { 0x00008204, 0x00000000 },
10116 + { 0x00008208, 0x00000000 },
10117 + { 0x0000820c, 0x00000000 },
10118 + { 0x00008210, 0x00000000 },
10119 + { 0x00008214, 0x00000000 },
10120 + { 0x00008218, 0x00000000 },
10121 + { 0x0000821c, 0x00000000 },
10122 + { 0x00008220, 0x00000000 },
10123 + { 0x00008224, 0x00000000 },
10124 + { 0x00008228, 0x00000000 },
10125 + { 0x0000822c, 0x00000000 },
10126 + { 0x00008230, 0x00000000 },
10127 + { 0x00008234, 0x00000000 },
10128 + { 0x00008238, 0x00000000 },
10129 + { 0x0000823c, 0x00000000 },
10130 + { 0x00008240, 0x00100000 },
10131 + { 0x00008244, 0x0010f400 },
10132 + { 0x00008248, 0x00000100 },
10133 + { 0x0000824c, 0x0001e800 },
10134 + { 0x00008250, 0x00000000 },
10135 + { 0x00008254, 0x00000000 },
10136 + { 0x00008258, 0x00000000 },
10137 + { 0x0000825c, 0x400000ff },
10138 + { 0x00008260, 0x00080922 },
10139 + { 0x00008264, 0xa8a00010 },
10140 + { 0x00008270, 0x00000000 },
10141 + { 0x00008274, 0x40000000 },
10142 + { 0x00008278, 0x003e4180 },
10143 + { 0x0000827c, 0x00000000 },
10144 + { 0x00008284, 0x0000002c },
10145 + { 0x00008288, 0x0000002c },
10146 + { 0x0000828c, 0x00000000 },
10147 + { 0x00008294, 0x00000000 },
10148 + { 0x00008298, 0x00000000 },
10149 + { 0x0000829c, 0x00000000 },
10150 + { 0x00008300, 0x00000040 },
10151 + { 0x00008314, 0x00000000 },
10152 + { 0x00008328, 0x00000000 },
10153 + { 0x0000832c, 0x00000001 },
10154 + { 0x00008330, 0x00000302 },
10155 + { 0x00008334, 0x00000e00 },
10156 + { 0x00008338, 0x00ff0000 },
10157 + { 0x0000833c, 0x00000000 },
10158 + { 0x00008340, 0x00010380 },
10159 + { 0x00008344, 0x00581043 },
10160 + { 0x00007010, 0x00000030 },
10161 + { 0x00007034, 0x00000002 },
10162 + { 0x00007038, 0x000004c2 },
10163 + { 0x00007800, 0x00140000 },
10164 + { 0x00007804, 0x0e4548d8 },
10165 + { 0x00007808, 0x54214514 },
10166 + { 0x0000780c, 0x02025820 },
10167 + { 0x00007810, 0x71c0d388 },
10168 + { 0x00007814, 0x924934a8 },
10169 + { 0x0000781c, 0x00000000 },
10170 + { 0x00007828, 0x66964300 },
10171 + { 0x0000782c, 0x8db6d961 },
10172 + { 0x00007830, 0x8db6d96c },
10173 + { 0x00007834, 0x6140008b },
10174 + { 0x0000783c, 0x72ee0a72 },
10175 + { 0x00007840, 0xbbfffffc },
10176 + { 0x00007844, 0x000c0db6 },
10177 + { 0x00007848, 0x6db61b6f },
10178 + { 0x0000784c, 0x6d9b66db },
10179 + { 0x00007850, 0x6d8c6dba },
10180 + { 0x00007854, 0x00040000 },
10181 + { 0x00007858, 0xdb003012 },
10182 + { 0x0000785c, 0x04924914 },
10183 + { 0x00007860, 0x21084210 },
10184 + { 0x00007864, 0xf7d7ffde },
10185 + { 0x00007868, 0xc2034080 },
10186 + { 0x00007870, 0x10142c00 },
10187 + { 0x00009808, 0x00000000 },
10188 + { 0x0000980c, 0xafe68e30 },
10189 + { 0x00009810, 0xfd14e000 },
10190 + { 0x00009814, 0x9c0a9f6b },
10191 + { 0x0000981c, 0x00000000 },
10192 + { 0x0000982c, 0x0000a000 },
10193 + { 0x00009830, 0x00000000 },
10194 + { 0x0000983c, 0x00200400 },
10195 + { 0x0000984c, 0x0040233c },
10196 + { 0x00009854, 0x00000044 },
10197 + { 0x00009900, 0x00000000 },
10198 + { 0x00009904, 0x00000000 },
10199 + { 0x00009908, 0x00000000 },
10200 + { 0x0000990c, 0x00000000 },
10201 + { 0x0000991c, 0x10000fff },
10202 + { 0x00009920, 0x04900000 },
10203 + { 0x00009928, 0x00000001 },
10204 + { 0x0000992c, 0x00000004 },
10205 + { 0x00009934, 0x1e1f2022 },
10206 + { 0x00009938, 0x0a0b0c0d },
10207 + { 0x0000993c, 0x00000000 },
10208 + { 0x00009940, 0x14750604 },
10209 + { 0x00009948, 0x9280c00a },
10210 + { 0x0000994c, 0x00020028 },
10211 + { 0x00009954, 0x5f3ca3de },
10212 + { 0x00009958, 0x0108ecff },
10213 + { 0x00009968, 0x000003ce },
10214 + { 0x00009970, 0x192bb514 },
10215 + { 0x00009974, 0x00000000 },
10216 + { 0x00009978, 0x00000001 },
10217 + { 0x0000997c, 0x00000000 },
10218 + { 0x00009980, 0x00000000 },
10219 + { 0x00009984, 0x00000000 },
10220 + { 0x00009988, 0x00000000 },
10221 + { 0x0000998c, 0x00000000 },
10222 + { 0x00009990, 0x00000000 },
10223 + { 0x00009994, 0x00000000 },
10224 + { 0x00009998, 0x00000000 },
10225 + { 0x0000999c, 0x00000000 },
10226 + { 0x000099a0, 0x00000000 },
10227 + { 0x000099a4, 0x00000001 },
10228 + { 0x000099a8, 0x201fff00 },
10229 + { 0x000099ac, 0x2def0400 },
10230 + { 0x000099b0, 0x03051000 },
10231 + { 0x000099b4, 0x00000820 },
10232 + { 0x000099dc, 0x00000000 },
10233 + { 0x000099e0, 0x00000000 },
10234 + { 0x000099e4, 0xaaaaaaaa },
10235 + { 0x000099e8, 0x3c466478 },
10236 + { 0x000099ec, 0x0cc80caa },
10237 + { 0x000099f0, 0x00000000 },
10238 + { 0x0000a208, 0x803e68c8 },
10239 + { 0x0000a210, 0x4080a333 },
10240 + { 0x0000a214, 0x00206c10 },
10241 + { 0x0000a218, 0x009c4060 },
10242 + { 0x0000a220, 0x01834061 },
10243 + { 0x0000a224, 0x00000400 },
10244 + { 0x0000a228, 0x000003b5 },
10245 + { 0x0000a22c, 0x00000000 },
10246 + { 0x0000a234, 0x20202020 },
10247 + { 0x0000a238, 0x20202020 },
10248 + { 0x0000a244, 0x00000000 },
10249 + { 0x0000a248, 0xfffffffc },
10250 + { 0x0000a24c, 0x00000000 },
10251 + { 0x0000a254, 0x00000000 },
10252 + { 0x0000a258, 0x0ccb5380 },
10253 + { 0x0000a25c, 0x15151501 },
10254 + { 0x0000a260, 0xdfa90f01 },
10255 + { 0x0000a268, 0x00000000 },
10256 + { 0x0000a26c, 0x0ebae9e6 },
10257 + { 0x0000a388, 0x0c000000 },
10258 + { 0x0000a38c, 0x20202020 },
10259 + { 0x0000a390, 0x20202020 },
10260 + { 0x0000a39c, 0x00000001 },
10261 + { 0x0000a3a0, 0x00000000 },
10262 + { 0x0000a3a4, 0x00000000 },
10263 + { 0x0000a3a8, 0x00000000 },
10264 + { 0x0000a3ac, 0x00000000 },
10265 + { 0x0000a3b0, 0x00000000 },
10266 + { 0x0000a3b4, 0x00000000 },
10267 + { 0x0000a3b8, 0x00000000 },
10268 + { 0x0000a3bc, 0x00000000 },
10269 + { 0x0000a3c0, 0x00000000 },
10270 + { 0x0000a3c4, 0x00000000 },
10271 + { 0x0000a3cc, 0x20202020 },
10272 + { 0x0000a3d0, 0x20202020 },
10273 + { 0x0000a3d4, 0x20202020 },
10274 + { 0x0000a3e4, 0x00000000 },
10275 + { 0x0000a3e8, 0x18c43433 },
10276 + { 0x0000a3ec, 0x00f70081 },
10277 + { 0x0000a3f0, 0x01036a2f },
10278 + { 0x0000a3f4, 0x00000000 },
10279 + { 0x0000d270, 0x0d820820 },
10280 + { 0x0000d35c, 0x07ffffef },
10281 + { 0x0000d360, 0x0fffffe7 },
10282 + { 0x0000d364, 0x17ffffe5 },
10283 + { 0x0000d368, 0x1fffffe4 },
10284 + { 0x0000d36c, 0x37ffffe3 },
10285 + { 0x0000d370, 0x3fffffe3 },
10286 + { 0x0000d374, 0x57ffffe3 },
10287 + { 0x0000d378, 0x5fffffe2 },
10288 + { 0x0000d37c, 0x7fffffe2 },
10289 + { 0x0000d380, 0x7f3c7bba },
10290 + { 0x0000d384, 0xf3307ff0 },
10291 +};
10292 +
10293 +static const u_int32_t ar9271Common_normal_cck_fir_coeff_9271[][2] = {
10294 + { 0x0000a1f4, 0x00fffeff },
10295 + { 0x0000a1f8, 0x00f5f9ff },
10296 + { 0x0000a1fc, 0xb79f6427 },
10297 +};
10298 +
10299 +static const u_int32_t ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = {
10300 + { 0x0000a1f4, 0x00000000 },
10301 + { 0x0000a1f8, 0xefff0301 },
10302 + { 0x0000a1fc, 0xca9228ee },
10303 +};
10304 +
10305 +static const u_int32_t ar9271Modes_9271_1_0_only[][6] = {
10306 + { 0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311 },
10307 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
10308 +};
10309 +
10310 +static const u_int32_t ar9271Modes_9271_ANI_reg[][6] = {
10311 + { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
10312 + { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
10313 + { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
10314 + { 0x0000986c, 0x06903881, 0x06903881, 0x06903881, 0x06903881, 0x06903881 },
10315 + { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
10316 + { 0x0000a208, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8 },
10317 + { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
10318 + { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
10319 +};
10320 +
10321 +static const u_int32_t ar9271Modes_normal_power_tx_gain_9271[][6] = {
10322 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
10323 + { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
10324 + { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
10325 + { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
10326 + { 0x0000a310, 0x00000000, 0x00000000, 0x0001e610, 0x0001e610, 0x00000000 },
10327 + { 0x0000a314, 0x00000000, 0x00000000, 0x0002d6d0, 0x0002d6d0, 0x00000000 },
10328 + { 0x0000a318, 0x00000000, 0x00000000, 0x00039758, 0x00039758, 0x00000000 },
10329 + { 0x0000a31c, 0x00000000, 0x00000000, 0x0003b759, 0x0003b759, 0x00000000 },
10330 + { 0x0000a320, 0x00000000, 0x00000000, 0x0003d75a, 0x0003d75a, 0x00000000 },
10331 + { 0x0000a324, 0x00000000, 0x00000000, 0x0004175c, 0x0004175c, 0x00000000 },
10332 + { 0x0000a328, 0x00000000, 0x00000000, 0x0004575e, 0x0004575e, 0x00000000 },
10333 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0004979f, 0x0004979f, 0x00000000 },
10334 + { 0x0000a330, 0x00000000, 0x00000000, 0x0004d7df, 0x0004d7df, 0x00000000 },
10335 + { 0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de, 0x00000000 },
10336 + { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
10337 + { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
10338 + { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10339 + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10340 + { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10341 + { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10342 + { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10343 + { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10344 + { 0x00007838, 0x00000029, 0x00000029, 0x00000029, 0x00000029, 0x00000029 },
10345 + { 0x00007824, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff },
10346 + { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
10347 + { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
10348 + { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a218652, 0x0a218652, 0x0a22a652 },
10349 + { 0x0000a278, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
10350 + { 0x0000a27c, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd },
10351 + { 0x0000a394, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
10352 + { 0x0000a398, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd },
10353 + { 0x0000a3dc, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
10354 + { 0x0000a3e0, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd },
10355 +};
10356 +
10357 +static const u_int32_t ar9271Modes_high_power_tx_gain_9271[][6] = {
10358 + { 0x0000a300, 0x00000000, 0x00000000, 0x00010000, 0x00010000, 0x00000000 },
10359 + { 0x0000a304, 0x00000000, 0x00000000, 0x00016200, 0x00016200, 0x00000000 },
10360 + { 0x0000a308, 0x00000000, 0x00000000, 0x00018201, 0x00018201, 0x00000000 },
10361 + { 0x0000a30c, 0x00000000, 0x00000000, 0x0001b240, 0x0001b240, 0x00000000 },
10362 + { 0x0000a310, 0x00000000, 0x00000000, 0x0001d241, 0x0001d241, 0x00000000 },
10363 + { 0x0000a314, 0x00000000, 0x00000000, 0x0001f600, 0x0001f600, 0x00000000 },
10364 + { 0x0000a318, 0x00000000, 0x00000000, 0x00022800, 0x00022800, 0x00000000 },
10365 + { 0x0000a31c, 0x00000000, 0x00000000, 0x00026802, 0x00026802, 0x00000000 },
10366 + { 0x0000a320, 0x00000000, 0x00000000, 0x0002b805, 0x0002b805, 0x00000000 },
10367 + { 0x0000a324, 0x00000000, 0x00000000, 0x0002ea41, 0x0002ea41, 0x00000000 },
10368 + { 0x0000a328, 0x00000000, 0x00000000, 0x00038b00, 0x00038b00, 0x00000000 },
10369 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0003ab40, 0x0003ab40, 0x00000000 },
10370 + { 0x0000a330, 0x00000000, 0x00000000, 0x0003cd80, 0x0003cd80, 0x00000000 },
10371 + { 0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de, 0x00000000 },
10372 + { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
10373 + { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
10374 + { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10375 + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10376 + { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10377 + { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10378 + { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10379 + { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10380 + { 0x00007838, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b },
10381 + { 0x00007824, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff },
10382 + { 0x0000786c, 0x08609eb6, 0x08609eb6, 0x08609eba, 0x08609eba, 0x08609eb6 },
10383 + { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
10384 + { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a212652, 0x0a212652, 0x0a22a652 },
10385 + { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
10386 + { 0x0000a27c, 0x05018063, 0x05038063, 0x05018063, 0x05018063, 0x05018063 },
10387 + { 0x0000a394, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63 },
10388 + { 0x0000a398, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063 },
10389 + { 0x0000a3dc, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63 },
10390 + { 0x0000a3e0, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063 },
10391 +};
10392 +
10393 +#endif /* INITVALS_9002_10_H */
10394 --- /dev/null
10395 +++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
10396 @@ -0,0 +1,462 @@
10397 +/*
10398 + * Copyright (c) 2008-2009 Atheros Communications Inc.
10399 + *
10400 + * Permission to use, copy, modify, and/or distribute this software for any
10401 + * purpose with or without fee is hereby granted, provided that the above
10402 + * copyright notice and this permission notice appear in all copies.
10403 + *
10404 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10405 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10406 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
10407 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
10408 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
10409 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
10410 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
10411 + */
10412 +
10413 +#include "hw.h"
10414 +
10415 +static void ar9002_hw_rx_enable(struct ath_hw *ah)
10416 +{
10417 + REG_WRITE(ah, AR_CR, AR_CR_RXE);
10418 +}
10419 +
10420 +static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
10421 +{
10422 + ((struct ath_desc*) ds)->ds_link = ds_link;
10423 +}
10424 +
10425 +static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
10426 +{
10427 + *ds_link = &((struct ath_desc *)ds)->ds_link;
10428 +}
10429 +
10430 +static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
10431 +{
10432 + u32 isr = 0;
10433 + u32 mask2 = 0;
10434 + struct ath9k_hw_capabilities *pCap = &ah->caps;
10435 + u32 sync_cause = 0;
10436 + bool fatal_int = false;
10437 + struct ath_common *common = ath9k_hw_common(ah);
10438 +
10439 + if (!AR_SREV_9100(ah)) {
10440 + if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
10441 + if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
10442 + == AR_RTC_STATUS_ON) {
10443 + isr = REG_READ(ah, AR_ISR);
10444 + }
10445 + }
10446 +
10447 + sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
10448 + AR_INTR_SYNC_DEFAULT;
10449 +
10450 + *masked = 0;
10451 +
10452 + if (!isr && !sync_cause)
10453 + return false;
10454 + } else {
10455 + *masked = 0;
10456 + isr = REG_READ(ah, AR_ISR);
10457 + }
10458 +
10459 + if (isr) {
10460 + if (isr & AR_ISR_BCNMISC) {
10461 + u32 isr2;
10462 + isr2 = REG_READ(ah, AR_ISR_S2);
10463 + if (isr2 & AR_ISR_S2_TIM)
10464 + mask2 |= ATH9K_INT_TIM;
10465 + if (isr2 & AR_ISR_S2_DTIM)
10466 + mask2 |= ATH9K_INT_DTIM;
10467 + if (isr2 & AR_ISR_S2_DTIMSYNC)
10468 + mask2 |= ATH9K_INT_DTIMSYNC;
10469 + if (isr2 & (AR_ISR_S2_CABEND))
10470 + mask2 |= ATH9K_INT_CABEND;
10471 + if (isr2 & AR_ISR_S2_GTT)
10472 + mask2 |= ATH9K_INT_GTT;
10473 + if (isr2 & AR_ISR_S2_CST)
10474 + mask2 |= ATH9K_INT_CST;
10475 + if (isr2 & AR_ISR_S2_TSFOOR)
10476 + mask2 |= ATH9K_INT_TSFOOR;
10477 + }
10478 +
10479 + isr = REG_READ(ah, AR_ISR_RAC);
10480 + if (isr == 0xffffffff) {
10481 + *masked = 0;
10482 + return false;
10483 + }
10484 +
10485 + *masked = isr & ATH9K_INT_COMMON;
10486 +
10487 + if (ah->config.rx_intr_mitigation) {
10488 + if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
10489 + *masked |= ATH9K_INT_RX;
10490 + }
10491 +
10492 + if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
10493 + *masked |= ATH9K_INT_RX;
10494 + if (isr &
10495 + (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
10496 + AR_ISR_TXEOL)) {
10497 + u32 s0_s, s1_s;
10498 +
10499 + *masked |= ATH9K_INT_TX;
10500 +
10501 + s0_s = REG_READ(ah, AR_ISR_S0_S);
10502 + ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
10503 + ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
10504 +
10505 + s1_s = REG_READ(ah, AR_ISR_S1_S);
10506 + ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
10507 + ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
10508 + }
10509 +
10510 + if (isr & AR_ISR_RXORN) {
10511 + ath_print(common, ATH_DBG_INTERRUPT,
10512 + "receive FIFO overrun interrupt\n");
10513 + }
10514 +
10515 + if (!AR_SREV_9100(ah)) {
10516 + if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
10517 + u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
10518 + if (isr5 & AR_ISR_S5_TIM_TIMER)
10519 + *masked |= ATH9K_INT_TIM_TIMER;
10520 + }
10521 + }
10522 +
10523 + *masked |= mask2;
10524 + }
10525 +
10526 + if (AR_SREV_9100(ah))
10527 + return true;
10528 +
10529 + if (isr & AR_ISR_GENTMR) {
10530 + u32 s5_s;
10531 +
10532 + s5_s = REG_READ(ah, AR_ISR_S5_S);
10533 + if (isr & AR_ISR_GENTMR) {
10534 + ah->intr_gen_timer_trigger =
10535 + MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
10536 +
10537 + ah->intr_gen_timer_thresh =
10538 + MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
10539 +
10540 + if (ah->intr_gen_timer_trigger)
10541 + *masked |= ATH9K_INT_GENTIMER;
10542 +
10543 + }
10544 + }
10545 +
10546 + if (sync_cause) {
10547 + fatal_int =
10548 + (sync_cause &
10549 + (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
10550 + ? true : false;
10551 +
10552 + if (fatal_int) {
10553 + if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
10554 + ath_print(common, ATH_DBG_ANY,
10555 + "received PCI FATAL interrupt\n");
10556 + }
10557 + if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
10558 + ath_print(common, ATH_DBG_ANY,
10559 + "received PCI PERR interrupt\n");
10560 + }
10561 + *masked |= ATH9K_INT_FATAL;
10562 + }
10563 + if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
10564 + ath_print(common, ATH_DBG_INTERRUPT,
10565 + "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
10566 + REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
10567 + REG_WRITE(ah, AR_RC, 0);
10568 + *masked |= ATH9K_INT_FATAL;
10569 + }
10570 + if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
10571 + ath_print(common, ATH_DBG_INTERRUPT,
10572 + "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
10573 + }
10574 +
10575 + REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
10576 + (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
10577 + }
10578 +
10579 + return true;
10580 +}
10581 +
10582 +static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
10583 + bool is_firstseg, bool is_lastseg,
10584 + const void *ds0, dma_addr_t buf_addr,
10585 + unsigned int qcu)
10586 +{
10587 + struct ar5416_desc *ads = AR5416DESC(ds);
10588 +
10589 + ads->ds_data = buf_addr;
10590 +
10591 + if (is_firstseg) {
10592 + ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
10593 + } else if (is_lastseg) {
10594 + ads->ds_ctl0 = 0;
10595 + ads->ds_ctl1 = seglen;
10596 + ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
10597 + ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
10598 + } else {
10599 + ads->ds_ctl0 = 0;
10600 + ads->ds_ctl1 = seglen | AR_TxMore;
10601 + ads->ds_ctl2 = 0;
10602 + ads->ds_ctl3 = 0;
10603 + }
10604 + ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
10605 + ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
10606 + ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
10607 + ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
10608 + ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
10609 +}
10610 +
10611 +static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
10612 + struct ath_tx_status *ts)
10613 +{
10614 + struct ar5416_desc *ads = AR5416DESC(ds);
10615 +
10616 + if ((ads->ds_txstatus9 & AR_TxDone) == 0)
10617 + return -EINPROGRESS;
10618 +
10619 + ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
10620 + ts->ts_tstamp = ads->AR_SendTimestamp;
10621 + ts->ts_status = 0;
10622 + ts->ts_flags = 0;
10623 +
10624 + if (ads->ds_txstatus1 & AR_FrmXmitOK)
10625 + ts->ts_status |= ATH9K_TX_ACKED;
10626 + if (ads->ds_txstatus1 & AR_ExcessiveRetries)
10627 + ts->ts_status |= ATH9K_TXERR_XRETRY;
10628 + if (ads->ds_txstatus1 & AR_Filtered)
10629 + ts->ts_status |= ATH9K_TXERR_FILT;
10630 + if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
10631 + ts->ts_status |= ATH9K_TXERR_FIFO;
10632 + ath9k_hw_updatetxtriglevel(ah, true);
10633 + }
10634 + if (ads->ds_txstatus9 & AR_TxOpExceeded)
10635 + ts->ts_status |= ATH9K_TXERR_XTXOP;
10636 + if (ads->ds_txstatus1 & AR_TxTimerExpired)
10637 + ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
10638 +
10639 + if (ads->ds_txstatus1 & AR_DescCfgErr)
10640 + ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
10641 + if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
10642 + ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
10643 + ath9k_hw_updatetxtriglevel(ah, true);
10644 + }
10645 + if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
10646 + ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
10647 + ath9k_hw_updatetxtriglevel(ah, true);
10648 + }
10649 + if (ads->ds_txstatus0 & AR_TxBaStatus) {
10650 + ts->ts_flags |= ATH9K_TX_BA;
10651 + ts->ba_low = ads->AR_BaBitmapLow;
10652 + ts->ba_high = ads->AR_BaBitmapHigh;
10653 + }
10654 +
10655 + ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
10656 + switch (ts->ts_rateindex) {
10657 + case 0:
10658 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
10659 + break;
10660 + case 1:
10661 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
10662 + break;
10663 + case 2:
10664 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
10665 + break;
10666 + case 3:
10667 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
10668 + break;
10669 + }
10670 +
10671 + ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
10672 + ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
10673 + ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
10674 + ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
10675 + ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
10676 + ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
10677 + ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
10678 + ts->evm0 = ads->AR_TxEVM0;
10679 + ts->evm1 = ads->AR_TxEVM1;
10680 + ts->evm2 = ads->AR_TxEVM2;
10681 + ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
10682 + ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
10683 + ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
10684 + ts->ts_antenna = 0;
10685 +
10686 + return 0;
10687 +}
10688 +
10689 +static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
10690 + u32 pktLen, enum ath9k_pkt_type type,
10691 + u32 txPower, u32 keyIx,
10692 + enum ath9k_key_type keyType, u32 flags)
10693 +{
10694 + struct ar5416_desc *ads = AR5416DESC(ds);
10695 +
10696 + txPower += ah->txpower_indexoffset;
10697 + if (txPower > 63)
10698 + txPower = 63;
10699 +
10700 + ads->ds_ctl0 = (pktLen & AR_FrameLen)
10701 + | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
10702 + | SM(txPower, AR_XmitPower)
10703 + | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
10704 + | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
10705 + | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
10706 + | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
10707 +
10708 + ads->ds_ctl1 =
10709 + (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
10710 + | SM(type, AR_FrameType)
10711 + | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
10712 + | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
10713 + | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
10714 +
10715 + ads->ds_ctl6 = SM(keyType, AR_EncrType);
10716 +
10717 + if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
10718 + ads->ds_ctl8 = 0;
10719 + ads->ds_ctl9 = 0;
10720 + ads->ds_ctl10 = 0;
10721 + ads->ds_ctl11 = 0;
10722 + }
10723 +}
10724 +
10725 +static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
10726 + void *lastds,
10727 + u32 durUpdateEn, u32 rtsctsRate,
10728 + u32 rtsctsDuration,
10729 + struct ath9k_11n_rate_series series[],
10730 + u32 nseries, u32 flags)
10731 +{
10732 + struct ar5416_desc *ads = AR5416DESC(ds);
10733 + struct ar5416_desc *last_ads = AR5416DESC(lastds);
10734 + u32 ds_ctl0;
10735 +
10736 + if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
10737 + ds_ctl0 = ads->ds_ctl0;
10738 +
10739 + if (flags & ATH9K_TXDESC_RTSENA) {
10740 + ds_ctl0 &= ~AR_CTSEnable;
10741 + ds_ctl0 |= AR_RTSEnable;
10742 + } else {
10743 + ds_ctl0 &= ~AR_RTSEnable;
10744 + ds_ctl0 |= AR_CTSEnable;
10745 + }
10746 +
10747 + ads->ds_ctl0 = ds_ctl0;
10748 + } else {
10749 + ads->ds_ctl0 =
10750 + (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
10751 + }
10752 +
10753 + ads->ds_ctl2 = set11nTries(series, 0)
10754 + | set11nTries(series, 1)
10755 + | set11nTries(series, 2)
10756 + | set11nTries(series, 3)
10757 + | (durUpdateEn ? AR_DurUpdateEna : 0)
10758 + | SM(0, AR_BurstDur);
10759 +
10760 + ads->ds_ctl3 = set11nRate(series, 0)
10761 + | set11nRate(series, 1)
10762 + | set11nRate(series, 2)
10763 + | set11nRate(series, 3);
10764 +
10765 + ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
10766 + | set11nPktDurRTSCTS(series, 1);
10767 +
10768 + ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
10769 + | set11nPktDurRTSCTS(series, 3);
10770 +
10771 + ads->ds_ctl7 = set11nRateFlags(series, 0)
10772 + | set11nRateFlags(series, 1)
10773 + | set11nRateFlags(series, 2)
10774 + | set11nRateFlags(series, 3)
10775 + | SM(rtsctsRate, AR_RTSCTSRate);
10776 + last_ads->ds_ctl2 = ads->ds_ctl2;
10777 + last_ads->ds_ctl3 = ads->ds_ctl3;
10778 +}
10779 +
10780 +static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
10781 + u32 aggrLen)
10782 +{
10783 + struct ar5416_desc *ads = AR5416DESC(ds);
10784 +
10785 + ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
10786 + ads->ds_ctl6 &= ~AR_AggrLen;
10787 + ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
10788 +}
10789 +
10790 +static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
10791 + u32 numDelims)
10792 +{
10793 + struct ar5416_desc *ads = AR5416DESC(ds);
10794 + unsigned int ctl6;
10795 +
10796 + ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
10797 +
10798 + ctl6 = ads->ds_ctl6;
10799 + ctl6 &= ~AR_PadDelim;
10800 + ctl6 |= SM(numDelims, AR_PadDelim);
10801 + ads->ds_ctl6 = ctl6;
10802 +}
10803 +
10804 +static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
10805 +{
10806 + struct ar5416_desc *ads = AR5416DESC(ds);
10807 +
10808 + ads->ds_ctl1 |= AR_IsAggr;
10809 + ads->ds_ctl1 &= ~AR_MoreAggr;
10810 + ads->ds_ctl6 &= ~AR_PadDelim;
10811 +}
10812 +
10813 +static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
10814 +{
10815 + struct ar5416_desc *ads = AR5416DESC(ds);
10816 +
10817 + ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
10818 +}
10819 +
10820 +static void ar9002_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
10821 + u32 burstDuration)
10822 +{
10823 + struct ar5416_desc *ads = AR5416DESC(ds);
10824 +
10825 + ads->ds_ctl2 &= ~AR_BurstDur;
10826 + ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
10827 +}
10828 +
10829 +static void ar9002_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
10830 + u32 vmf)
10831 +{
10832 + struct ar5416_desc *ads = AR5416DESC(ds);
10833 +
10834 + if (vmf)
10835 + ads->ds_ctl0 |= AR_VirtMoreFrag;
10836 + else
10837 + ads->ds_ctl0 &= ~AR_VirtMoreFrag;
10838 +}
10839 +
10840 +void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
10841 +{
10842 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
10843 +
10844 + ops->rx_enable = ar9002_hw_rx_enable;
10845 + ops->set_desc_link = ar9002_hw_set_desc_link;
10846 + ops->get_desc_link = ar9002_hw_get_desc_link;
10847 + ops->get_isr = ar9002_hw_get_isr;
10848 + ops->fill_txdesc = ar9002_hw_fill_txdesc;
10849 + ops->proc_txdesc = ar9002_hw_proc_txdesc;
10850 + ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
10851 + ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
10852 + ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
10853 + ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
10854 + ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
10855 + ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
10856 + ops->set11n_burstduration = ar9002_hw_set11n_burstduration;
10857 + ops->set11n_virtualmorefrag = ar9002_hw_set11n_virtualmorefrag;
10858 +}
10859 --- /dev/null
10860 +++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
10861 @@ -0,0 +1,534 @@
10862 +/*
10863 + * Copyright (c) 2008-2010 Atheros Communications Inc.
10864 + *
10865 + * Permission to use, copy, modify, and/or distribute this software for any
10866 + * purpose with or without fee is hereby granted, provided that the above
10867 + * copyright notice and this permission notice appear in all copies.
10868 + *
10869 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10870 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10871 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
10872 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
10873 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
10874 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
10875 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
10876 + */
10877 +
10878 +/**
10879 + * DOC: Programming Atheros 802.11n analog front end radios
10880 + *
10881 + * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
10882 + * devices have either an external AR2133 analog front end radio for single
10883 + * band 2.4 GHz communication or an AR5133 analog front end radio for dual
10884 + * band 2.4 GHz / 5 GHz communication.
10885 + *
10886 + * All devices after the AR5416 and AR5418 family starting with the AR9280
10887 + * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
10888 + * into a single-chip and require less programming.
10889 + *
10890 + * The following single-chips exist with a respective embedded radio:
10891 + *
10892 + * AR9280 - 11n dual-band 2x2 MIMO for PCIe
10893 + * AR9281 - 11n single-band 1x2 MIMO for PCIe
10894 + * AR9285 - 11n single-band 1x1 for PCIe
10895 + * AR9287 - 11n single-band 2x2 MIMO for PCIe
10896 + *
10897 + * AR9220 - 11n dual-band 2x2 MIMO for PCI
10898 + * AR9223 - 11n single-band 2x2 MIMO for PCI
10899 + *
10900 + * AR9287 - 11n single-band 1x1 MIMO for USB
10901 + */
10902 +
10903 +#include "hw.h"
10904 +#include "ar9002_phy.h"
10905 +
10906 +/**
10907 + * ar9002_hw_set_channel - set channel on single-chip device
10908 + * @ah: atheros hardware structure
10909 + * @chan:
10910 + *
10911 + * This is the function to change channel on single-chip devices, that is
10912 + * all devices after ar9280.
10913 + *
10914 + * This function takes the channel value in MHz and sets
10915 + * hardware channel value. Assumes writes have been enabled to analog bus.
10916 + *
10917 + * Actual Expression,
10918 + *
10919 + * For 2GHz channel,
10920 + * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
10921 + * (freq_ref = 40MHz)
10922 + *
10923 + * For 5GHz channel,
10924 + * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
10925 + * (freq_ref = 40MHz/(24>>amodeRefSel))
10926 + */
10927 +static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
10928 +{
10929 + u16 bMode, fracMode, aModeRefSel = 0;
10930 + u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
10931 + struct chan_centers centers;
10932 + u32 refDivA = 24;
10933 +
10934 + ath9k_hw_get_channel_centers(ah, chan, &centers);
10935 + freq = centers.synth_center;
10936 +
10937 + reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
10938 + reg32 &= 0xc0000000;
10939 +
10940 + if (freq < 4800) { /* 2 GHz, fractional mode */
10941 + u32 txctl;
10942 + int regWrites = 0;
10943 +
10944 + bMode = 1;
10945 + fracMode = 1;
10946 + aModeRefSel = 0;
10947 + channelSel = CHANSEL_2G(freq);
10948 +
10949 + if (AR_SREV_9287_11_OR_LATER(ah)) {
10950 + if (freq == 2484) {
10951 + /* Enable channel spreading for channel 14 */
10952 + REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
10953 + 1, regWrites);
10954 + } else {
10955 + REG_WRITE_ARRAY(&ah->iniCckfirNormal,
10956 + 1, regWrites);
10957 + }
10958 + } else {
10959 + txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
10960 + if (freq == 2484) {
10961 + /* Enable channel spreading for channel 14 */
10962 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
10963 + txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
10964 + } else {
10965 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
10966 + txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
10967 + }
10968 + }
10969 + } else {
10970 + bMode = 0;
10971 + fracMode = 0;
10972 +
10973 + switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
10974 + case 0:
10975 + if ((freq % 20) == 0) {
10976 + aModeRefSel = 3;
10977 + } else if ((freq % 10) == 0) {
10978 + aModeRefSel = 2;
10979 + }
10980 + if (aModeRefSel)
10981 + break;
10982 + case 1:
10983 + default:
10984 + aModeRefSel = 0;
10985 + /*
10986 + * Enable 2G (fractional) mode for channels
10987 + * which are 5MHz spaced.
10988 + */
10989 + fracMode = 1;
10990 + refDivA = 1;
10991 + channelSel = CHANSEL_5G(freq);
10992 +
10993 + /* RefDivA setting */
10994 + REG_RMW_FIELD(ah, AR_AN_SYNTH9,
10995 + AR_AN_SYNTH9_REFDIVA, refDivA);
10996 +
10997 + }
10998 +
10999 + if (!fracMode) {
11000 + ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
11001 + channelSel = ndiv & 0x1ff;
11002 + channelFrac = (ndiv & 0xfffffe00) * 2;
11003 + channelSel = (channelSel << 17) | channelFrac;
11004 + }
11005 + }
11006 +
11007 + reg32 = reg32 |
11008 + (bMode << 29) |
11009 + (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
11010 +
11011 + REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
11012 +
11013 + ah->curchan = chan;
11014 + ah->curchan_rad_index = -1;
11015 +
11016 + return 0;
11017 +}
11018 +
11019 +/**
11020 + * ar9002_hw_spur_mitigate - convert baseband spur frequency
11021 + * @ah: atheros hardware structure
11022 + * @chan:
11023 + *
11024 + * For single-chip solutions. Converts to baseband spur frequency given the
11025 + * input channel frequency and compute register settings below.
11026 + */
11027 +static void ar9002_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
11028 +{
11029 + int bb_spur = AR_NO_SPUR;
11030 + int freq;
11031 + int bin, cur_bin;
11032 + int bb_spur_off, spur_subchannel_sd;
11033 + int spur_freq_sd;
11034 + int spur_delta_phase;
11035 + int denominator;
11036 + int upper, lower, cur_vit_mask;
11037 + int tmp, newVal;
11038 + int i;
11039 + int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
11040 + AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
11041 + };
11042 + int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
11043 + AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
11044 + };
11045 + int inc[4] = { 0, 100, 0, 0 };
11046 + struct chan_centers centers;
11047 +
11048 + int8_t mask_m[123];
11049 + int8_t mask_p[123];
11050 + int8_t mask_amt;
11051 + int tmp_mask;
11052 + int cur_bb_spur;
11053 + bool is2GHz = IS_CHAN_2GHZ(chan);
11054 +
11055 + memset(&mask_m, 0, sizeof(int8_t) * 123);
11056 + memset(&mask_p, 0, sizeof(int8_t) * 123);
11057 +
11058 + ath9k_hw_get_channel_centers(ah, chan, &centers);
11059 + freq = centers.synth_center;
11060 +
11061 + ah->config.spurmode = SPUR_ENABLE_EEPROM;
11062 + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
11063 + cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
11064 +
11065 + if (is2GHz)
11066 + cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
11067 + else
11068 + cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
11069 +
11070 + if (AR_NO_SPUR == cur_bb_spur)
11071 + break;
11072 + cur_bb_spur = cur_bb_spur - freq;
11073 +
11074 + if (IS_CHAN_HT40(chan)) {
11075 + if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
11076 + (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
11077 + bb_spur = cur_bb_spur;
11078 + break;
11079 + }
11080 + } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
11081 + (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
11082 + bb_spur = cur_bb_spur;
11083 + break;
11084 + }
11085 + }
11086 +
11087 + if (AR_NO_SPUR == bb_spur) {
11088 + REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
11089 + AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
11090 + return;
11091 + } else {
11092 + REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
11093 + AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
11094 + }
11095 +
11096 + bin = bb_spur * 320;
11097 +
11098 + tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
11099 +
11100 + newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
11101 + AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
11102 + AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
11103 + AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
11104 + REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
11105 +
11106 + newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
11107 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
11108 + AR_PHY_SPUR_REG_MASK_RATE_SELECT |
11109 + AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
11110 + SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
11111 + REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
11112 +
11113 + if (IS_CHAN_HT40(chan)) {
11114 + if (bb_spur < 0) {
11115 + spur_subchannel_sd = 1;
11116 + bb_spur_off = bb_spur + 10;
11117 + } else {
11118 + spur_subchannel_sd = 0;
11119 + bb_spur_off = bb_spur - 10;
11120 + }
11121 + } else {
11122 + spur_subchannel_sd = 0;
11123 + bb_spur_off = bb_spur;
11124 + }
11125 +
11126 + if (IS_CHAN_HT40(chan))
11127 + spur_delta_phase =
11128 + ((bb_spur * 262144) /
11129 + 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
11130 + else
11131 + spur_delta_phase =
11132 + ((bb_spur * 524288) /
11133 + 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
11134 +
11135 + denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
11136 + spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
11137 +
11138 + newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
11139 + SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
11140 + SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
11141 + REG_WRITE(ah, AR_PHY_TIMING11, newVal);
11142 +
11143 + newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
11144 + REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
11145 +
11146 + cur_bin = -6000;
11147 + upper = bin + 100;
11148 + lower = bin - 100;
11149 +
11150 + for (i = 0; i < 4; i++) {
11151 + int pilot_mask = 0;
11152 + int chan_mask = 0;
11153 + int bp = 0;
11154 + for (bp = 0; bp < 30; bp++) {
11155 + if ((cur_bin > lower) && (cur_bin < upper)) {
11156 + pilot_mask = pilot_mask | 0x1 << bp;
11157 + chan_mask = chan_mask | 0x1 << bp;
11158 + }
11159 + cur_bin += 100;
11160 + }
11161 + cur_bin += inc[i];
11162 + REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
11163 + REG_WRITE(ah, chan_mask_reg[i], chan_mask);
11164 + }
11165 +
11166 + cur_vit_mask = 6100;
11167 + upper = bin + 120;
11168 + lower = bin - 120;
11169 +
11170 + for (i = 0; i < 123; i++) {
11171 + if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
11172 +
11173 + /* workaround for gcc bug #37014 */
11174 + volatile int tmp_v = abs(cur_vit_mask - bin);
11175 +
11176 + if (tmp_v < 75)
11177 + mask_amt = 1;
11178 + else
11179 + mask_amt = 0;
11180 + if (cur_vit_mask < 0)
11181 + mask_m[abs(cur_vit_mask / 100)] = mask_amt;
11182 + else
11183 + mask_p[cur_vit_mask / 100] = mask_amt;
11184 + }
11185 + cur_vit_mask -= 100;
11186 + }
11187 +
11188 + tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
11189 + | (mask_m[48] << 26) | (mask_m[49] << 24)
11190 + | (mask_m[50] << 22) | (mask_m[51] << 20)
11191 + | (mask_m[52] << 18) | (mask_m[53] << 16)
11192 + | (mask_m[54] << 14) | (mask_m[55] << 12)
11193 + | (mask_m[56] << 10) | (mask_m[57] << 8)
11194 + | (mask_m[58] << 6) | (mask_m[59] << 4)
11195 + | (mask_m[60] << 2) | (mask_m[61] << 0);
11196 + REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
11197 + REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
11198 +
11199 + tmp_mask = (mask_m[31] << 28)
11200 + | (mask_m[32] << 26) | (mask_m[33] << 24)
11201 + | (mask_m[34] << 22) | (mask_m[35] << 20)
11202 + | (mask_m[36] << 18) | (mask_m[37] << 16)
11203 + | (mask_m[48] << 14) | (mask_m[39] << 12)
11204 + | (mask_m[40] << 10) | (mask_m[41] << 8)
11205 + | (mask_m[42] << 6) | (mask_m[43] << 4)
11206 + | (mask_m[44] << 2) | (mask_m[45] << 0);
11207 + REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
11208 + REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
11209 +
11210 + tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
11211 + | (mask_m[18] << 26) | (mask_m[18] << 24)
11212 + | (mask_m[20] << 22) | (mask_m[20] << 20)
11213 + | (mask_m[22] << 18) | (mask_m[22] << 16)
11214 + | (mask_m[24] << 14) | (mask_m[24] << 12)
11215 + | (mask_m[25] << 10) | (mask_m[26] << 8)
11216 + | (mask_m[27] << 6) | (mask_m[28] << 4)
11217 + | (mask_m[29] << 2) | (mask_m[30] << 0);
11218 + REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
11219 + REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
11220 +
11221 + tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
11222 + | (mask_m[2] << 26) | (mask_m[3] << 24)
11223 + | (mask_m[4] << 22) | (mask_m[5] << 20)
11224 + | (mask_m[6] << 18) | (mask_m[7] << 16)
11225 + | (mask_m[8] << 14) | (mask_m[9] << 12)
11226 + | (mask_m[10] << 10) | (mask_m[11] << 8)
11227 + | (mask_m[12] << 6) | (mask_m[13] << 4)
11228 + | (mask_m[14] << 2) | (mask_m[15] << 0);
11229 + REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
11230 + REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
11231 +
11232 + tmp_mask = (mask_p[15] << 28)
11233 + | (mask_p[14] << 26) | (mask_p[13] << 24)
11234 + | (mask_p[12] << 22) | (mask_p[11] << 20)
11235 + | (mask_p[10] << 18) | (mask_p[9] << 16)
11236 + | (mask_p[8] << 14) | (mask_p[7] << 12)
11237 + | (mask_p[6] << 10) | (mask_p[5] << 8)
11238 + | (mask_p[4] << 6) | (mask_p[3] << 4)
11239 + | (mask_p[2] << 2) | (mask_p[1] << 0);
11240 + REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
11241 + REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
11242 +
11243 + tmp_mask = (mask_p[30] << 28)
11244 + | (mask_p[29] << 26) | (mask_p[28] << 24)
11245 + | (mask_p[27] << 22) | (mask_p[26] << 20)
11246 + | (mask_p[25] << 18) | (mask_p[24] << 16)
11247 + | (mask_p[23] << 14) | (mask_p[22] << 12)
11248 + | (mask_p[21] << 10) | (mask_p[20] << 8)
11249 + | (mask_p[19] << 6) | (mask_p[18] << 4)
11250 + | (mask_p[17] << 2) | (mask_p[16] << 0);
11251 + REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
11252 + REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
11253 +
11254 + tmp_mask = (mask_p[45] << 28)
11255 + | (mask_p[44] << 26) | (mask_p[43] << 24)
11256 + | (mask_p[42] << 22) | (mask_p[41] << 20)
11257 + | (mask_p[40] << 18) | (mask_p[39] << 16)
11258 + | (mask_p[38] << 14) | (mask_p[37] << 12)
11259 + | (mask_p[36] << 10) | (mask_p[35] << 8)
11260 + | (mask_p[34] << 6) | (mask_p[33] << 4)
11261 + | (mask_p[32] << 2) | (mask_p[31] << 0);
11262 + REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
11263 + REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
11264 +
11265 + tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
11266 + | (mask_p[59] << 26) | (mask_p[58] << 24)
11267 + | (mask_p[57] << 22) | (mask_p[56] << 20)
11268 + | (mask_p[55] << 18) | (mask_p[54] << 16)
11269 + | (mask_p[53] << 14) | (mask_p[52] << 12)
11270 + | (mask_p[51] << 10) | (mask_p[50] << 8)
11271 + | (mask_p[49] << 6) | (mask_p[48] << 4)
11272 + | (mask_p[47] << 2) | (mask_p[46] << 0);
11273 + REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
11274 + REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
11275 +}
11276 +
11277 +static void ar9002_olc_init(struct ath_hw *ah)
11278 +{
11279 + u32 i;
11280 +
11281 + if (!OLC_FOR_AR9280_20_LATER)
11282 + return;
11283 +
11284 + if (OLC_FOR_AR9287_10_LATER) {
11285 + REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
11286 + AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
11287 + ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
11288 + AR9287_AN_TXPC0_TXPCMODE,
11289 + AR9287_AN_TXPC0_TXPCMODE_S,
11290 + AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
11291 + udelay(100);
11292 + } else {
11293 + for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
11294 + ah->originalGain[i] =
11295 + MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
11296 + AR_PHY_TX_GAIN);
11297 + ah->PDADCdelta = 0;
11298 + }
11299 +}
11300 +
11301 +static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
11302 + struct ath9k_channel *chan)
11303 +{
11304 + u32 pll;
11305 +
11306 + pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
11307 +
11308 + if (chan && IS_CHAN_HALF_RATE(chan))
11309 + pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
11310 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
11311 + pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
11312 +
11313 + if (chan && IS_CHAN_5GHZ(chan)) {
11314 + pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
11315 +
11316 +
11317 + if (AR_SREV_9280_20(ah)) {
11318 + if (((chan->channel % 20) == 0)
11319 + || ((chan->channel % 10) == 0))
11320 + pll = 0x2850;
11321 + else
11322 + pll = 0x142c;
11323 + }
11324 + } else {
11325 + pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
11326 + }
11327 +
11328 + return pll;
11329 +}
11330 +
11331 +static void ar9002_hw_do_getnf(struct ath_hw *ah,
11332 + int16_t nfarray[NUM_NF_READINGS])
11333 +{
11334 + struct ath_common *common = ath9k_hw_common(ah);
11335 + int16_t nf;
11336 +
11337 + nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
11338 +
11339 + if (nf & 0x100)
11340 + nf = 0 - ((nf ^ 0x1ff) + 1);
11341 + ath_print(common, ATH_DBG_CALIBRATE,
11342 + "NF calibrated [ctl] [chain 0] is %d\n", nf);
11343 +
11344 + if (AR_SREV_9271(ah) && (nf >= -114))
11345 + nf = -116;
11346 +
11347 + nfarray[0] = nf;
11348 +
11349 + if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
11350 + nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
11351 + AR9280_PHY_CH1_MINCCA_PWR);
11352 +
11353 + if (nf & 0x100)
11354 + nf = 0 - ((nf ^ 0x1ff) + 1);
11355 + ath_print(common, ATH_DBG_CALIBRATE,
11356 + "NF calibrated [ctl] [chain 1] is %d\n", nf);
11357 + nfarray[1] = nf;
11358 + }
11359 +
11360 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
11361 + if (nf & 0x100)
11362 + nf = 0 - ((nf ^ 0x1ff) + 1);
11363 + ath_print(common, ATH_DBG_CALIBRATE,
11364 + "NF calibrated [ext] [chain 0] is %d\n", nf);
11365 +
11366 + if (AR_SREV_9271(ah) && (nf >= -114))
11367 + nf = -116;
11368 +
11369 + nfarray[3] = nf;
11370 +
11371 + if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
11372 + nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
11373 + AR9280_PHY_CH1_EXT_MINCCA_PWR);
11374 +
11375 + if (nf & 0x100)
11376 + nf = 0 - ((nf ^ 0x1ff) + 1);
11377 + ath_print(common, ATH_DBG_CALIBRATE,
11378 + "NF calibrated [ext] [chain 1] is %d\n", nf);
11379 + nfarray[4] = nf;
11380 + }
11381 +}
11382 +
11383 +void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
11384 +{
11385 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
11386 +
11387 + priv_ops->set_rf_regs = NULL;
11388 + priv_ops->rf_alloc_ext_banks = NULL;
11389 + priv_ops->rf_free_ext_banks = NULL;
11390 + priv_ops->rf_set_freq = ar9002_hw_set_channel;
11391 + priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
11392 + priv_ops->olc_init = ar9002_olc_init;
11393 + priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
11394 + priv_ops->do_getnf = ar9002_hw_do_getnf;
11395 +}
11396 --- /dev/null
11397 +++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
11398 @@ -0,0 +1,572 @@
11399 +/*
11400 + * Copyright (c) 2008-2010 Atheros Communications Inc.
11401 + *
11402 + * Permission to use, copy, modify, and/or distribute this software for any
11403 + * purpose with or without fee is hereby granted, provided that the above
11404 + * copyright notice and this permission notice appear in all copies.
11405 + *
11406 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11407 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11408 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11409 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11410 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
11411 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
11412 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
11413 + */
11414 +#ifndef AR9002_PHY_H
11415 +#define AR9002_PHY_H
11416 +
11417 +#define AR_PHY_TEST 0x9800
11418 +#define PHY_AGC_CLR 0x10000000
11419 +#define RFSILENT_BB 0x00002000
11420 +
11421 +#define AR_PHY_TURBO 0x9804
11422 +#define AR_PHY_FC_TURBO_MODE 0x00000001
11423 +#define AR_PHY_FC_TURBO_SHORT 0x00000002
11424 +#define AR_PHY_FC_DYN2040_EN 0x00000004
11425 +#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
11426 +#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
11427 +/* For 25 MHz channel spacing -- not used but supported by hw */
11428 +#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
11429 +#define AR_PHY_FC_HT_EN 0x00000040
11430 +#define AR_PHY_FC_SHORT_GI_40 0x00000080
11431 +#define AR_PHY_FC_WALSH 0x00000100
11432 +#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
11433 +#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
11434 +
11435 +#define AR_PHY_TEST2 0x9808
11436 +
11437 +#define AR_PHY_TIMING2 0x9810
11438 +#define AR_PHY_TIMING3 0x9814
11439 +#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
11440 +#define AR_PHY_TIMING3_DSC_MAN_S 17
11441 +#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
11442 +#define AR_PHY_TIMING3_DSC_EXP_S 13
11443 +
11444 +#define AR_PHY_CHIP_ID_REV_0 0x80
11445 +#define AR_PHY_CHIP_ID_REV_1 0x81
11446 +#define AR_PHY_CHIP_ID_9160_REV_0 0xb0
11447 +
11448 +#define AR_PHY_ACTIVE 0x981C
11449 +#define AR_PHY_ACTIVE_EN 0x00000001
11450 +#define AR_PHY_ACTIVE_DIS 0x00000000
11451 +
11452 +#define AR_PHY_RF_CTL2 0x9824
11453 +#define AR_PHY_TX_END_DATA_START 0x000000FF
11454 +#define AR_PHY_TX_END_DATA_START_S 0
11455 +#define AR_PHY_TX_END_PA_ON 0x0000FF00
11456 +#define AR_PHY_TX_END_PA_ON_S 8
11457 +
11458 +#define AR_PHY_RF_CTL3 0x9828
11459 +#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
11460 +#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
11461 +
11462 +#define AR_PHY_ADC_CTL 0x982C
11463 +#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
11464 +#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
11465 +#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
11466 +#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
11467 +#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
11468 +#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
11469 +#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
11470 +
11471 +#define AR_PHY_ADC_SERIAL_CTL 0x9830
11472 +#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
11473 +#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
11474 +
11475 +#define AR_PHY_RF_CTL4 0x9834
11476 +#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
11477 +#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
11478 +#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
11479 +#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
11480 +#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
11481 +#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
11482 +#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
11483 +#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
11484 +
11485 +#define AR_PHY_TSTDAC_CONST 0x983c
11486 +
11487 +#define AR_PHY_SETTLING 0x9844
11488 +#define AR_PHY_SETTLING_SWITCH 0x00003F80
11489 +#define AR_PHY_SETTLING_SWITCH_S 7
11490 +
11491 +#define AR_PHY_RXGAIN 0x9848
11492 +#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
11493 +#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
11494 +#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
11495 +#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
11496 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
11497 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
11498 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
11499 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
11500 +
11501 +#define AR_PHY_DESIRED_SZ 0x9850
11502 +#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
11503 +#define AR_PHY_DESIRED_SZ_ADC_S 0
11504 +#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
11505 +#define AR_PHY_DESIRED_SZ_PGA_S 8
11506 +#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
11507 +#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
11508 +
11509 +#define AR_PHY_FIND_SIG 0x9858
11510 +#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
11511 +#define AR_PHY_FIND_SIG_FIRSTEP_S 12
11512 +#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
11513 +#define AR_PHY_FIND_SIG_FIRPWR_S 18
11514 +
11515 +#define AR_PHY_AGC_CTL1 0x985C
11516 +#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
11517 +#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
11518 +#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
11519 +#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
11520 +
11521 +#define AR_PHY_CCA 0x9864
11522 +#define AR_PHY_MINCCA_PWR 0x0FF80000
11523 +#define AR_PHY_MINCCA_PWR_S 19
11524 +#define AR_PHY_CCA_THRESH62 0x0007F000
11525 +#define AR_PHY_CCA_THRESH62_S 12
11526 +#define AR9280_PHY_MINCCA_PWR 0x1FF00000
11527 +#define AR9280_PHY_MINCCA_PWR_S 20
11528 +#define AR9280_PHY_CCA_THRESH62 0x000FF000
11529 +#define AR9280_PHY_CCA_THRESH62_S 12
11530 +
11531 +#define AR_PHY_SFCORR_LOW 0x986C
11532 +#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
11533 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
11534 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
11535 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
11536 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
11537 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
11538 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
11539 +
11540 +#define AR_PHY_SFCORR 0x9868
11541 +#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
11542 +#define AR_PHY_SFCORR_M2COUNT_THR_S 0
11543 +#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
11544 +#define AR_PHY_SFCORR_M1_THRESH_S 17
11545 +#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
11546 +#define AR_PHY_SFCORR_M2_THRESH_S 24
11547 +
11548 +#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
11549 +#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
11550 +#define AR_PHY_SYNTH_CONTROL 0x9874
11551 +#define AR_PHY_SLEEP_SCAL 0x9878
11552 +
11553 +#define AR_PHY_PLL_CTL 0x987c
11554 +#define AR_PHY_PLL_CTL_40 0xaa
11555 +#define AR_PHY_PLL_CTL_40_5413 0x04
11556 +#define AR_PHY_PLL_CTL_44 0xab
11557 +#define AR_PHY_PLL_CTL_44_2133 0xeb
11558 +#define AR_PHY_PLL_CTL_40_2133 0xea
11559 +
11560 +#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
11561 +#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
11562 +#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
11563 +#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
11564 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
11565 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
11566 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
11567 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
11568 +#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
11569 +#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
11570 +#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
11571 +#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
11572 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
11573 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
11574 +
11575 +#define AR_PHY_RX_DELAY 0x9914
11576 +#define AR_PHY_SEARCH_START_DELAY 0x9918
11577 +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
11578 +
11579 +#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
11580 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
11581 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
11582 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
11583 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
11584 +#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
11585 +#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
11586 +#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
11587 +#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
11588 +
11589 +#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
11590 +#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
11591 +#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
11592 +#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
11593 +
11594 +#define AR_PHY_TIMING5 0x9924
11595 +#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
11596 +#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
11597 +
11598 +#define AR_PHY_POWER_TX_RATE1 0x9934
11599 +#define AR_PHY_POWER_TX_RATE2 0x9938
11600 +#define AR_PHY_POWER_TX_RATE_MAX 0x993c
11601 +#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
11602 +
11603 +#define AR_PHY_FRAME_CTL 0x9944
11604 +#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
11605 +#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
11606 +
11607 +#define AR_PHY_TXPWRADJ 0x994C
11608 +#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
11609 +#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
11610 +#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
11611 +#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
11612 +
11613 +#define AR_PHY_RADAR_EXT 0x9940
11614 +#define AR_PHY_RADAR_EXT_ENA 0x00004000
11615 +
11616 +#define AR_PHY_RADAR_0 0x9954
11617 +#define AR_PHY_RADAR_0_ENA 0x00000001
11618 +#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
11619 +#define AR_PHY_RADAR_0_INBAND 0x0000003e
11620 +#define AR_PHY_RADAR_0_INBAND_S 1
11621 +#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
11622 +#define AR_PHY_RADAR_0_PRSSI_S 6
11623 +#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
11624 +#define AR_PHY_RADAR_0_HEIGHT_S 12
11625 +#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
11626 +#define AR_PHY_RADAR_0_RRSSI_S 18
11627 +#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
11628 +#define AR_PHY_RADAR_0_FIRPWR_S 24
11629 +
11630 +#define AR_PHY_RADAR_1 0x9958
11631 +#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
11632 +#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
11633 +#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
11634 +#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
11635 +#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
11636 +#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
11637 +#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
11638 +#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
11639 +#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
11640 +#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
11641 +#define AR_PHY_RADAR_1_MAXLEN_S 0
11642 +
11643 +#define AR_PHY_SWITCH_CHAIN_0 0x9960
11644 +#define AR_PHY_SWITCH_COM 0x9964
11645 +
11646 +#define AR_PHY_SIGMA_DELTA 0x996C
11647 +#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
11648 +#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
11649 +#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
11650 +#define AR_PHY_SIGMA_DELTA_FILT2_S 3
11651 +#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
11652 +#define AR_PHY_SIGMA_DELTA_FILT1_S 8
11653 +#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
11654 +#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
11655 +
11656 +#define AR_PHY_RESTART 0x9970
11657 +#define AR_PHY_RESTART_DIV_GC 0x001C0000
11658 +#define AR_PHY_RESTART_DIV_GC_S 18
11659 +
11660 +#define AR_PHY_RFBUS_REQ 0x997C
11661 +#define AR_PHY_RFBUS_REQ_EN 0x00000001
11662 +
11663 +#define AR_PHY_TIMING7 0x9980
11664 +#define AR_PHY_TIMING8 0x9984
11665 +#define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
11666 +#define AR_PHY_TIMING8_PILOT_MASK_2_S 0
11667 +
11668 +#define AR_PHY_BIN_MASK2_1 0x9988
11669 +#define AR_PHY_BIN_MASK2_2 0x998c
11670 +#define AR_PHY_BIN_MASK2_3 0x9990
11671 +#define AR_PHY_BIN_MASK2_4 0x9994
11672 +
11673 +#define AR_PHY_BIN_MASK_1 0x9900
11674 +#define AR_PHY_BIN_MASK_2 0x9904
11675 +#define AR_PHY_BIN_MASK_3 0x9908
11676 +
11677 +#define AR_PHY_MASK_CTL 0x990c
11678 +
11679 +#define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
11680 +#define AR_PHY_BIN_MASK2_4_MASK_4_S 0
11681 +
11682 +#define AR_PHY_TIMING9 0x9998
11683 +#define AR_PHY_TIMING10 0x999c
11684 +#define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
11685 +#define AR_PHY_TIMING10_PILOT_MASK_2_S 0
11686 +
11687 +#define AR_PHY_TIMING11 0x99a0
11688 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
11689 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
11690 +#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
11691 +#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
11692 +
11693 +#define AR_PHY_RX_CHAINMASK 0x99a4
11694 +#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
11695 +#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
11696 +#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
11697 +
11698 +#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
11699 +#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
11700 +#define AR_PHY_9285_ANT_DIV_CTL 0x01000000
11701 +#define AR_PHY_9285_ANT_DIV_CTL_S 24
11702 +#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
11703 +#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
11704 +#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
11705 +#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
11706 +#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
11707 +#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
11708 +#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
11709 +#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
11710 +#define AR_PHY_9285_ANT_DIV_LNA1 2
11711 +#define AR_PHY_9285_ANT_DIV_LNA2 1
11712 +#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
11713 +#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
11714 +#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
11715 +#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
11716 +
11717 +#define AR_PHY_EXT_CCA0 0x99b8
11718 +#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
11719 +#define AR_PHY_EXT_CCA0_THRESH62_S 0
11720 +
11721 +#define AR_PHY_EXT_CCA 0x99bc
11722 +#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
11723 +#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
11724 +#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
11725 +#define AR_PHY_EXT_CCA_THRESH62_S 16
11726 +#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
11727 +#define AR_PHY_EXT_MINCCA_PWR_S 23
11728 +#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
11729 +#define AR9280_PHY_EXT_MINCCA_PWR_S 16
11730 +
11731 +#define AR_PHY_SFCORR_EXT 0x99c0
11732 +#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
11733 +#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
11734 +#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
11735 +#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
11736 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
11737 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
11738 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
11739 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
11740 +#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
11741 +
11742 +#define AR_PHY_HALFGI 0x99D0
11743 +#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
11744 +#define AR_PHY_HALFGI_DSC_MAN_S 4
11745 +#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
11746 +#define AR_PHY_HALFGI_DSC_EXP_S 0
11747 +
11748 +#define AR_PHY_CHAN_INFO_MEMORY 0x99DC
11749 +#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
11750 +
11751 +#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
11752 +
11753 +#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC
11754 +#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
11755 +
11756 +#define AR_PHY_M_SLEEP 0x99f0
11757 +#define AR_PHY_REFCLKDLY 0x99f4
11758 +#define AR_PHY_REFCLKPD 0x99f8
11759 +
11760 +#define AR_PHY_CALMODE 0x99f0
11761 +
11762 +#define AR_PHY_CALMODE_IQ 0x00000000
11763 +#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
11764 +#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
11765 +#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
11766 +
11767 +#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
11768 +#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
11769 +#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
11770 +#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
11771 +
11772 +#define AR_PHY_CURRENT_RSSI 0x9c1c
11773 +#define AR9280_PHY_CURRENT_RSSI 0x9c3c
11774 +
11775 +#define AR_PHY_RFBUS_GRANT 0x9C20
11776 +#define AR_PHY_RFBUS_GRANT_EN 0x00000001
11777 +
11778 +#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
11779 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
11780 +
11781 +#define AR_PHY_CHAN_INFO_GAIN 0x9CFC
11782 +
11783 +#define AR_PHY_MODE 0xA200
11784 +#define AR_PHY_MODE_ASYNCFIFO 0x80
11785 +#define AR_PHY_MODE_AR2133 0x08
11786 +#define AR_PHY_MODE_AR5111 0x00
11787 +#define AR_PHY_MODE_AR5112 0x08
11788 +#define AR_PHY_MODE_DYNAMIC 0x04
11789 +#define AR_PHY_MODE_RF2GHZ 0x02
11790 +#define AR_PHY_MODE_RF5GHZ 0x00
11791 +#define AR_PHY_MODE_CCK 0x01
11792 +#define AR_PHY_MODE_OFDM 0x00
11793 +#define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
11794 +
11795 +#define AR_PHY_CCK_TX_CTRL 0xA204
11796 +#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
11797 +#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
11798 +#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
11799 +
11800 +#define AR_PHY_CCK_DETECT 0xA208
11801 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
11802 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
11803 +/* [12:6] settling time for antenna switch */
11804 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
11805 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
11806 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
11807 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
11808 +
11809 +#define AR_PHY_GAIN_2GHZ 0xA20C
11810 +#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
11811 +#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
11812 +#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
11813 +#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
11814 +#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
11815 +#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
11816 +
11817 +#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
11818 +#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
11819 +#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
11820 +#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
11821 +#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
11822 +#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
11823 +#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
11824 +#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
11825 +
11826 +#define AR_PHY_CCK_RXCTRL4 0xA21C
11827 +#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
11828 +#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
11829 +
11830 +#define AR_PHY_DAG_CTRLCCK 0xA228
11831 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
11832 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
11833 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
11834 +
11835 +#define AR_PHY_FORCE_CLKEN_CCK 0xA22C
11836 +#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
11837 +
11838 +#define AR_PHY_POWER_TX_RATE3 0xA234
11839 +#define AR_PHY_POWER_TX_RATE4 0xA238
11840 +
11841 +#define AR_PHY_SCRM_SEQ_XR 0xA23C
11842 +#define AR_PHY_HEADER_DETECT_XR 0xA240
11843 +#define AR_PHY_CHIRP_DETECTED_XR 0xA244
11844 +#define AR_PHY_BLUETOOTH 0xA254
11845 +
11846 +#define AR_PHY_TPCRG1 0xA258
11847 +#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
11848 +#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
11849 +
11850 +#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
11851 +#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
11852 +#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
11853 +#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
11854 +#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
11855 +#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
11856 +
11857 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
11858 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
11859 +
11860 +#define AR_PHY_TX_PWRCTRL4 0xa264
11861 +#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
11862 +#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
11863 +#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
11864 +#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
11865 +
11866 +#define AR_PHY_TX_PWRCTRL6_0 0xa270
11867 +#define AR_PHY_TX_PWRCTRL6_1 0xb270
11868 +#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
11869 +#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
11870 +
11871 +#define AR_PHY_TX_PWRCTRL7 0xa274
11872 +#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
11873 +#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
11874 +
11875 +#define AR_PHY_TX_PWRCTRL9 0xa27C
11876 +#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
11877 +#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
11878 +#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
11879 +#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
11880 +
11881 +#define AR_PHY_TX_GAIN_TBL1 0xa300
11882 +#define AR_PHY_TX_GAIN 0x0007F000
11883 +#define AR_PHY_TX_GAIN_S 12
11884 +
11885 +#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
11886 +#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
11887 +#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00
11888 +#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
11889 +
11890 +#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
11891 +#define AR_PHY_MASK2_M_31_45 0xa3a4
11892 +#define AR_PHY_MASK2_M_16_30 0xa3a8
11893 +#define AR_PHY_MASK2_M_00_15 0xa3ac
11894 +#define AR_PHY_MASK2_P_15_01 0xa3b8
11895 +#define AR_PHY_MASK2_P_30_16 0xa3bc
11896 +#define AR_PHY_MASK2_P_45_31 0xa3c0
11897 +#define AR_PHY_MASK2_P_61_45 0xa3c4
11898 +#define AR_PHY_SPUR_REG 0x994c
11899 +
11900 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
11901 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
11902 +
11903 +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
11904 +#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
11905 +#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
11906 +#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
11907 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
11908 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
11909 +
11910 +#define AR_PHY_PILOT_MASK_01_30 0xa3b0
11911 +#define AR_PHY_PILOT_MASK_31_60 0xa3b4
11912 +
11913 +#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
11914 +#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
11915 +
11916 +#define AR_PHY_ANALOG_SWAP 0xa268
11917 +#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
11918 +
11919 +#define AR_PHY_TPCRG5 0xA26C
11920 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
11921 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
11922 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
11923 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
11924 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
11925 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
11926 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
11927 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
11928 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
11929 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
11930 +
11931 +/* Carrier leak calibration control, do it after AGC calibration */
11932 +#define AR_PHY_CL_CAL_CTL 0xA358
11933 +#define AR_PHY_CL_CAL_ENABLE 0x00000002
11934 +#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
11935 +
11936 +#define AR_PHY_POWER_TX_RATE5 0xA38C
11937 +#define AR_PHY_POWER_TX_RATE6 0xA390
11938 +
11939 +#define AR_PHY_CAL_CHAINMASK 0xA39C
11940 +
11941 +#define AR_PHY_POWER_TX_SUB 0xA3C8
11942 +#define AR_PHY_POWER_TX_RATE7 0xA3CC
11943 +#define AR_PHY_POWER_TX_RATE8 0xA3D0
11944 +#define AR_PHY_POWER_TX_RATE9 0xA3D4
11945 +
11946 +#define AR_PHY_XPA_CFG 0xA3D8
11947 +#define AR_PHY_FORCE_XPA_CFG 0x000000001
11948 +#define AR_PHY_FORCE_XPA_CFG_S 0
11949 +
11950 +#define AR_PHY_CH1_CCA 0xa864
11951 +#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
11952 +#define AR_PHY_CH1_MINCCA_PWR_S 19
11953 +#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
11954 +#define AR9280_PHY_CH1_MINCCA_PWR_S 20
11955 +
11956 +#define AR_PHY_CH2_CCA 0xb864
11957 +#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
11958 +#define AR_PHY_CH2_MINCCA_PWR_S 19
11959 +
11960 +#define AR_PHY_CH1_EXT_CCA 0xa9bc
11961 +#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
11962 +#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
11963 +#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
11964 +#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
11965 +
11966 +#define AR_PHY_CH2_EXT_CCA 0xb9bc
11967 +#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
11968 +#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
11969 +
11970 +#endif
11971 --- /dev/null
11972 +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
11973 @@ -0,0 +1,798 @@
11974 +/*
11975 + * Copyright (c) 2010 Atheros Communications Inc.
11976 + *
11977 + * Permission to use, copy, modify, and/or distribute this software for any
11978 + * purpose with or without fee is hereby granted, provided that the above
11979 + * copyright notice and this permission notice appear in all copies.
11980 + *
11981 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11982 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11983 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11984 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11985 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
11986 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
11987 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
11988 + */
11989 +
11990 +#include "hw.h"
11991 +#include "hw-ops.h"
11992 +#include "ar9003_phy.h"
11993 +
11994 +static void ar9003_hw_setup_calibration(struct ath_hw *ah,
11995 + struct ath9k_cal_list *currCal)
11996 +{
11997 + struct ath_common *common = ath9k_hw_common(ah);
11998 +
11999 + /* Select calibration to run */
12000 + switch(currCal->calData->calType) {
12001 + case IQ_MISMATCH_CAL:
12002 + /*
12003 + * Start calibration with
12004 + * 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples
12005 + */
12006 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
12007 + AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX,
12008 + currCal->calData->calCountMax);
12009 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
12010 +
12011 + ath_print(common, ATH_DBG_CALIBRATE,
12012 + "starting IQ Mismatch Calibration\n");
12013 +
12014 + /* Kick-off cal */
12015 + REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
12016 + break;
12017 + case TEMP_COMP_CAL:
12018 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
12019 + AR_PHY_65NM_CH0_THERM_LOCAL, 1);
12020 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
12021 + AR_PHY_65NM_CH0_THERM_START, 1);
12022 +
12023 + ath_print(common, ATH_DBG_CALIBRATE,
12024 + "starting Temperature Compensation Calibration\n");
12025 + break;
12026 + case ADC_DC_INIT_CAL:
12027 + case ADC_GAIN_CAL:
12028 + case ADC_DC_CAL:
12029 + /* Not yet */
12030 + break;
12031 + }
12032 +}
12033 +
12034 +/*
12035 + * Generic calibration routine.
12036 + * Recalibrate the lower PHY chips to account for temperature/environment
12037 + * changes.
12038 + */
12039 +static bool ar9003_hw_per_calibration(struct ath_hw *ah,
12040 + struct ath9k_channel *ichan,
12041 + u8 rxchainmask,
12042 + struct ath9k_cal_list *currCal)
12043 +{
12044 + /* Cal is assumed not done until explicitly set below */
12045 + bool iscaldone = false;
12046 +
12047 + /* Calibration in progress. */
12048 + if (currCal->calState == CAL_RUNNING) {
12049 + /* Check to see if it has finished. */
12050 + if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) {
12051 + /*
12052 + * Accumulate cal measures for active chains
12053 + */
12054 + currCal->calData->calCollect(ah);
12055 + ah->cal_samples++;
12056 +
12057 + if (ah->cal_samples >=
12058 + currCal->calData->calNumSamples) {
12059 + unsigned int i, numChains = 0;
12060 + for (i = 0; i < AR9300_MAX_CHAINS; i++) {
12061 + if (rxchainmask & (1 << i))
12062 + numChains++;
12063 + }
12064 +
12065 + /*
12066 + * Process accumulated data
12067 + */
12068 + currCal->calData->calPostProc(ah, numChains);
12069 +
12070 + /* Calibration has finished. */
12071 + ichan->CalValid |= currCal->calData->calType;
12072 + currCal->calState = CAL_DONE;
12073 + iscaldone = true;
12074 + } else {
12075 + /*
12076 + * Set-up collection of another sub-sample until we
12077 + * get desired number
12078 + */
12079 + ar9003_hw_setup_calibration(ah, currCal);
12080 + }
12081 + }
12082 + } else if (!(ichan->CalValid & currCal->calData->calType)) {
12083 + /* If current cal is marked invalid in channel, kick it off */
12084 + ath9k_hw_reset_calibration(ah, currCal);
12085 + }
12086 +
12087 + return iscaldone;
12088 +}
12089 +
12090 +static bool ar9003_hw_calibrate(struct ath_hw *ah,
12091 + struct ath9k_channel *chan,
12092 + u8 rxchainmask,
12093 + bool longcal)
12094 +{
12095 + bool iscaldone = true;
12096 + struct ath9k_cal_list *currCal = ah->cal_list_curr;
12097 +
12098 + /*
12099 + * For given calibration:
12100 + * 1. Call generic cal routine
12101 + * 2. When this cal is done (isCalDone) if we have more cals waiting
12102 + * (eg after reset), mask this to upper layers by not propagating
12103 + * isCalDone if it is set to TRUE.
12104 + * Instead, change isCalDone to FALSE and setup the waiting cal(s)
12105 + * to be run.
12106 + */
12107 + if (currCal &&
12108 + (currCal->calState == CAL_RUNNING ||
12109 + currCal->calState == CAL_WAITING)) {
12110 + iscaldone = ar9003_hw_per_calibration(ah, chan,
12111 + rxchainmask, currCal);
12112 + if (iscaldone) {
12113 + ah->cal_list_curr = currCal = currCal->calNext;
12114 +
12115 + if (currCal->calState == CAL_WAITING) {
12116 + iscaldone = false;
12117 + ath9k_hw_reset_calibration(ah, currCal);
12118 + }
12119 + }
12120 + }
12121 +
12122 + /* Do NF cal only at longer intervals */
12123 + if (longcal) {
12124 + /*
12125 + * Load the NF from history buffer of the current channel.
12126 + * NF is slow time-variant, so it is OK to use a historical value.
12127 + */
12128 + ath9k_hw_loadnf(ah, ah->curchan);
12129 +
12130 + /* start NF calibration, without updating BB NF register */
12131 + ath9k_hw_start_nfcal(ah);
12132 + }
12133 +
12134 + return iscaldone;
12135 +}
12136 +
12137 +static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
12138 +{
12139 + int i;
12140 +
12141 + /* Accumulate IQ cal measures for active chains */
12142 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
12143 + ah->totalPowerMeasI[i] +=
12144 + REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
12145 + ah->totalPowerMeasQ[i] +=
12146 + REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
12147 + ah->totalIqCorrMeas[i] +=
12148 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
12149 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
12150 + "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
12151 + ah->cal_samples, i, ah->totalPowerMeasI[i],
12152 + ah->totalPowerMeasQ[i],
12153 + ah->totalIqCorrMeas[i]);
12154 + }
12155 +}
12156 +
12157 +static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
12158 +{
12159 + struct ath_common *common = ath9k_hw_common(ah);
12160 + u32 powerMeasQ, powerMeasI, iqCorrMeas;
12161 + u32 qCoffDenom, iCoffDenom;
12162 + int32_t qCoff, iCoff;
12163 + int iqCorrNeg, i;
12164 + const u_int32_t offset_array[3] = {
12165 + AR_PHY_RX_IQCAL_CORR_B0,
12166 + AR_PHY_RX_IQCAL_CORR_B1,
12167 + AR_PHY_RX_IQCAL_CORR_B2,
12168 + };
12169 +
12170 + for (i = 0; i < numChains; i++) {
12171 + powerMeasI = ah->totalPowerMeasI[i];
12172 + powerMeasQ = ah->totalPowerMeasQ[i];
12173 + iqCorrMeas = ah->totalIqCorrMeas[i];
12174 +
12175 + ath_print(common, ATH_DBG_CALIBRATE,
12176 + "Starting IQ Cal and Correction for Chain %d\n",
12177 + i);
12178 +
12179 + ath_print(common, ATH_DBG_CALIBRATE,
12180 + "Orignal: Chn %diq_corr_meas = 0x%08x\n",
12181 + i, ah->totalIqCorrMeas[i]);
12182 +
12183 + iqCorrNeg = 0;
12184 +
12185 + if (iqCorrMeas > 0x80000000) {
12186 + iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
12187 + iqCorrNeg = 1;
12188 + }
12189 +
12190 + ath_print(common, ATH_DBG_CALIBRATE,
12191 + "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
12192 + ath_print(common, ATH_DBG_CALIBRATE,
12193 + "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
12194 + ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
12195 + iqCorrNeg);
12196 +
12197 + iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
12198 + qCoffDenom = powerMeasQ / 64;
12199 +
12200 + if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
12201 + iCoff = iqCorrMeas / iCoffDenom;
12202 + qCoff = powerMeasI / qCoffDenom - 64;
12203 + ath_print(common, ATH_DBG_CALIBRATE,
12204 + "Chn %d iCoff = 0x%08x\n", i, iCoff);
12205 + ath_print(common, ATH_DBG_CALIBRATE,
12206 + "Chn %d qCoff = 0x%08x\n", i, qCoff);
12207 +
12208 + /* Force bounds on iCoff */
12209 + if (iCoff >= 63)
12210 + iCoff = 63;
12211 + else if (iCoff <= -63)
12212 + iCoff = -63;
12213 +
12214 + /* Negate iCoff if iqCorrNeg == 0 */
12215 + if (iqCorrNeg == 0x0)
12216 + iCoff = -iCoff;
12217 +
12218 + /* Force bounds on qCoff */
12219 + if (qCoff >= 63)
12220 + qCoff = 63;
12221 + else if (qCoff <= -63)
12222 + qCoff = -63;
12223 +
12224 + iCoff = iCoff & 0x7f;
12225 + qCoff = qCoff & 0x7f;
12226 +
12227 + ath_print(common, ATH_DBG_CALIBRATE,
12228 + "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
12229 + i, iCoff, qCoff);
12230 + ath_print(common, ATH_DBG_CALIBRATE,
12231 + "Register offset (0x%04x) "
12232 + "before update = 0x%x\n",
12233 + offset_array[i],
12234 + REG_READ(ah, offset_array[i]));
12235 +
12236 + REG_RMW_FIELD(ah, offset_array[i],
12237 + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
12238 + iCoff);
12239 + REG_RMW_FIELD(ah, offset_array[i],
12240 + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
12241 + qCoff);
12242 + ath_print(common, ATH_DBG_CALIBRATE,
12243 + "Register offset (0x%04x) QI COFF "
12244 + "(bitfields 0x%08x) after update = 0x%x\n",
12245 + offset_array[i],
12246 + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
12247 + REG_READ(ah, offset_array[i]));
12248 + ath_print(common, ATH_DBG_CALIBRATE,
12249 + "Register offset (0x%04x) QQ COFF "
12250 + "(bitfields 0x%08x) after update = 0x%x\n",
12251 + offset_array[i], AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
12252 + REG_READ(ah, offset_array[i]));
12253 +
12254 + ath_print(common, ATH_DBG_CALIBRATE,
12255 + "IQ Cal and Correction done for Chain %d\n",
12256 + i);
12257 + }
12258 + }
12259 +
12260 + REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
12261 + AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
12262 + ath_print(common, ATH_DBG_CALIBRATE,
12263 + "IQ Cal and Correction (offset 0x%04x) enabled "
12264 + "(bit position 0x%08x). New Value 0x%08x\n",
12265 + (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
12266 + AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
12267 + REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
12268 +}
12269 +
12270 +static const struct ath9k_percal_data iq_cal_single_sample = {
12271 + IQ_MISMATCH_CAL,
12272 + MIN_CAL_SAMPLES,
12273 + PER_MAX_LOG_COUNT,
12274 + ar9003_hw_iqcal_collect,
12275 + ar9003_hw_iqcalibrate
12276 +};
12277 +
12278 +static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
12279 +{
12280 + ah->iq_caldata.calData = &iq_cal_single_sample;
12281 + ah->supp_cals = IQ_MISMATCH_CAL;
12282 +}
12283 +
12284 +static bool ar9003_hw_iscal_supported(struct ath_hw *ah,
12285 + enum ath9k_cal_types calType)
12286 +{
12287 + switch (calType & ah->supp_cals) {
12288 + case IQ_MISMATCH_CAL:
12289 + /*
12290 + * XXX: Run IQ Mismatch for non-CCK only
12291 + * Note that CHANNEL_B is never set though.
12292 + */
12293 + return true;
12294 + case ADC_GAIN_CAL:
12295 + case ADC_DC_CAL:
12296 + return false;
12297 + case TEMP_COMP_CAL:
12298 + return true;
12299 + }
12300 +
12301 + return false;
12302 +}
12303 +
12304 +/*
12305 + * solve 4x4 linear equation used in loopback iq cal.
12306 + */
12307 +static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
12308 + s32 sin_2phi_1,
12309 + s32 cos_2phi_1,
12310 + s32 sin_2phi_2,
12311 + s32 cos_2phi_2,
12312 + s32 mag_a0_d0,
12313 + s32 phs_a0_d0,
12314 + s32 mag_a1_d0,
12315 + s32 phs_a1_d0,
12316 + s32 solved_eq[])
12317 +{
12318 + s32 f1 = cos_2phi_1 - cos_2phi_2,
12319 + f3 = sin_2phi_1 - sin_2phi_2,
12320 + f2;
12321 + s32 mag_tx, phs_tx, mag_rx, phs_rx;
12322 + const s32 result_shift = 1 << 15;
12323 + struct ath_common *common = ath9k_hw_common(ah);
12324 +
12325 + f2 = (f1 * f1 + f3 * f3) / result_shift;
12326 +
12327 + if (!f2) {
12328 + ath_print(common, ATH_DBG_CALIBRATE, "Divide by 0\n");
12329 + return false;
12330 + }
12331 +
12332 + /* mag mismatch, tx */
12333 + mag_tx = f1 * (mag_a0_d0 - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0);
12334 + /* phs mismatch, tx */
12335 + phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0);
12336 +
12337 + mag_tx = (mag_tx / f2);
12338 + phs_tx = (phs_tx / f2);
12339 +
12340 + /* mag mismatch, rx */
12341 + mag_rx = mag_a0_d0 - (cos_2phi_1 * mag_tx + sin_2phi_1 * phs_tx) /
12342 + result_shift;
12343 + /* phs mismatch, rx */
12344 + phs_rx = phs_a0_d0 + (sin_2phi_1 * mag_tx - cos_2phi_1 * phs_tx) /
12345 + result_shift;
12346 +
12347 + solved_eq[0] = mag_tx;
12348 + solved_eq[1] = phs_tx;
12349 + solved_eq[2] = mag_rx;
12350 + solved_eq[3] = phs_rx;
12351 +
12352 + return true;
12353 +}
12354 +
12355 +static s32 ar9003_hw_find_mag_approx(struct ath_hw *ah, s32 in_re, s32 in_im)
12356 +{
12357 + s32 abs_i = abs(in_re),
12358 + abs_q = abs(in_im),
12359 + max_abs, min_abs;
12360 +
12361 + if (abs_i > abs_q) {
12362 + max_abs = abs_i;
12363 + min_abs = abs_q;
12364 + } else {
12365 + max_abs = abs_q;
12366 + min_abs = abs_i;
12367 + }
12368 +
12369 + return (max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4));
12370 +}
12371 +
12372 +#define DELPT 32
12373 +
12374 +static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
12375 + s32 chain_idx,
12376 + const s32 iq_res[],
12377 + s32 iqc_coeff[])
12378 +{
12379 + s32 i2_m_q2_a0_d0, i2_p_q2_a0_d0, iq_corr_a0_d0,
12380 + i2_m_q2_a0_d1, i2_p_q2_a0_d1, iq_corr_a0_d1,
12381 + i2_m_q2_a1_d0, i2_p_q2_a1_d0, iq_corr_a1_d0,
12382 + i2_m_q2_a1_d1, i2_p_q2_a1_d1, iq_corr_a1_d1;
12383 + s32 mag_a0_d0, mag_a1_d0, mag_a0_d1, mag_a1_d1,
12384 + phs_a0_d0, phs_a1_d0, phs_a0_d1, phs_a1_d1,
12385 + sin_2phi_1, cos_2phi_1,
12386 + sin_2phi_2, cos_2phi_2;
12387 + s32 mag_tx, phs_tx, mag_rx, phs_rx;
12388 + s32 solved_eq[4], mag_corr_tx, phs_corr_tx, mag_corr_rx, phs_corr_rx,
12389 + q_q_coff, q_i_coff;
12390 + const s32 res_scale = 1 << 15;
12391 + const s32 delpt_shift = 1 << 8;
12392 + s32 mag1, mag2;
12393 + struct ath_common *common = ath9k_hw_common(ah);
12394 +
12395 + i2_m_q2_a0_d0 = iq_res[0] & 0xfff;
12396 + i2_p_q2_a0_d0 = (iq_res[0] >> 12) & 0xfff;
12397 + iq_corr_a0_d0 = ((iq_res[0] >> 24) & 0xff) + ((iq_res[1] & 0xf) << 8);
12398 +
12399 + if (i2_m_q2_a0_d0 > 0x800)
12400 + i2_m_q2_a0_d0 = -((0xfff - i2_m_q2_a0_d0) + 1);
12401 +
12402 + if (i2_p_q2_a0_d0 > 0x800)
12403 + i2_p_q2_a0_d0 = -((0xfff - i2_p_q2_a0_d0) + 1);
12404 +
12405 + if (iq_corr_a0_d0 > 0x800)
12406 + iq_corr_a0_d0 = -((0xfff - iq_corr_a0_d0) + 1);
12407 +
12408 + i2_m_q2_a0_d1 = (iq_res[1] >> 4) & 0xfff;
12409 + i2_p_q2_a0_d1 = (iq_res[2] & 0xfff);
12410 + iq_corr_a0_d1 = (iq_res[2] >> 12) & 0xfff;
12411 +
12412 + if (i2_m_q2_a0_d1 > 0x800)
12413 + i2_m_q2_a0_d1 = -((0xfff - i2_m_q2_a0_d1) + 1);
12414 +
12415 + if (i2_p_q2_a0_d1 > 0x800)
12416 + i2_p_q2_a0_d1 = -((0xfff - i2_p_q2_a0_d1) + 1);
12417 +
12418 + if (iq_corr_a0_d1 > 0x800)
12419 + iq_corr_a0_d1 = -((0xfff - iq_corr_a0_d1) + 1);
12420 +
12421 + i2_m_q2_a1_d0 = ((iq_res[2] >> 24) & 0xff) + ((iq_res[3] & 0xf) << 8);
12422 + i2_p_q2_a1_d0 = (iq_res[3] >> 4) & 0xfff;
12423 + iq_corr_a1_d0 = iq_res[4] & 0xfff;
12424 +
12425 + if (i2_m_q2_a1_d0 > 0x800)
12426 + i2_m_q2_a1_d0 = -((0xfff - i2_m_q2_a1_d0) + 1);
12427 +
12428 + if (i2_p_q2_a1_d0 > 0x800)
12429 + i2_p_q2_a1_d0 = -((0xfff - i2_p_q2_a1_d0) + 1);
12430 +
12431 + if (iq_corr_a1_d0 > 0x800)
12432 + iq_corr_a1_d0 = -((0xfff - iq_corr_a1_d0) + 1);
12433 +
12434 + i2_m_q2_a1_d1 = (iq_res[4] >> 12) & 0xfff;
12435 + i2_p_q2_a1_d1 = ((iq_res[4] >> 24) & 0xff) + ((iq_res[5] & 0xf) << 8);
12436 + iq_corr_a1_d1 = (iq_res[5] >> 4) & 0xfff;
12437 +
12438 + if (i2_m_q2_a1_d1 > 0x800)
12439 + i2_m_q2_a1_d1 = -((0xfff - i2_m_q2_a1_d1) + 1);
12440 +
12441 + if (i2_p_q2_a1_d1 > 0x800)
12442 + i2_p_q2_a1_d1 = -((0xfff - i2_p_q2_a1_d1) + 1);
12443 +
12444 + if (iq_corr_a1_d1 > 0x800)
12445 + iq_corr_a1_d1 = -((0xfff - iq_corr_a1_d1) + 1);
12446 +
12447 + if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
12448 + (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
12449 + ath_print(common, ATH_DBG_CALIBRATE,
12450 + "Divide by 0:\na0_d0=%d\n"
12451 + "a0_d1=%d\na2_d0=%d\na1_d1=%d\n",
12452 + i2_p_q2_a0_d0, i2_p_q2_a0_d1,
12453 + i2_p_q2_a1_d0, i2_p_q2_a1_d1);
12454 + return false;
12455 + }
12456 +
12457 + mag_a0_d0 = (i2_m_q2_a0_d0 * res_scale) / i2_p_q2_a0_d0;
12458 + phs_a0_d0 = (iq_corr_a0_d0 * res_scale) / i2_p_q2_a0_d0;
12459 +
12460 + mag_a0_d1 = (i2_m_q2_a0_d1 * res_scale) / i2_p_q2_a0_d1;
12461 + phs_a0_d1 = (iq_corr_a0_d1 * res_scale) / i2_p_q2_a0_d1;
12462 +
12463 + mag_a1_d0 = (i2_m_q2_a1_d0 * res_scale) / i2_p_q2_a1_d0;
12464 + phs_a1_d0 = (iq_corr_a1_d0 * res_scale) / i2_p_q2_a1_d0;
12465 +
12466 + mag_a1_d1 = (i2_m_q2_a1_d1 * res_scale) / i2_p_q2_a1_d1;
12467 + phs_a1_d1 = (iq_corr_a1_d1 * res_scale) / i2_p_q2_a1_d1;
12468 +
12469 + /* w/o analog phase shift */
12470 + sin_2phi_1 = (((mag_a0_d0 - mag_a0_d1) * delpt_shift) / DELPT);
12471 + /* w/o analog phase shift */
12472 + cos_2phi_1 = (((phs_a0_d1 - phs_a0_d0) * delpt_shift) / DELPT);
12473 + /* w/ analog phase shift */
12474 + sin_2phi_2 = (((mag_a1_d0 - mag_a1_d1) * delpt_shift) / DELPT);
12475 + /* w/ analog phase shift */
12476 + cos_2phi_2 = (((phs_a1_d1 - phs_a1_d0) * delpt_shift) / DELPT);
12477 +
12478 + /*
12479 + * force sin^2 + cos^2 = 1;
12480 + * find magnitude by approximation
12481 + */
12482 + mag1 = ar9003_hw_find_mag_approx(ah, cos_2phi_1, sin_2phi_1);
12483 + mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
12484 +
12485 + if ((mag1 == 0) || (mag2 == 0)) {
12486 + ath_print(common, ATH_DBG_CALIBRATE,
12487 + "Divide by 0: mag1=%d, mag2=%d\n",
12488 + mag1, mag2);
12489 + return false;
12490 + }
12491 +
12492 + /* normalization sin and cos by mag */
12493 + sin_2phi_1 = (sin_2phi_1 * res_scale / mag1);
12494 + cos_2phi_1 = (cos_2phi_1 * res_scale / mag1);
12495 + sin_2phi_2 = (sin_2phi_2 * res_scale / mag2);
12496 + cos_2phi_2 = (cos_2phi_2 * res_scale / mag2);
12497 +
12498 + /* calculate IQ mismatch */
12499 + if (!ar9003_hw_solve_iq_cal(ah,
12500 + sin_2phi_1, cos_2phi_1,
12501 + sin_2phi_2, cos_2phi_2,
12502 + mag_a0_d0, phs_a0_d0,
12503 + mag_a1_d0,
12504 + phs_a1_d0, solved_eq)) {
12505 + ath_print(common, ATH_DBG_CALIBRATE,
12506 + "Call to ar9003_hw_solve_iq_cal() failed.\n");
12507 + return false;
12508 + }
12509 +
12510 + mag_tx = solved_eq[0];
12511 + phs_tx = solved_eq[1];
12512 + mag_rx = solved_eq[2];
12513 + phs_rx = solved_eq[3];
12514 +
12515 + ath_print(common, ATH_DBG_CALIBRATE,
12516 + "chain %d: mag mismatch=%d phase mismatch=%d\n",
12517 + chain_idx, mag_tx/res_scale, phs_tx/res_scale);
12518 +
12519 + if (res_scale == mag_tx) {
12520 + ath_print(common, ATH_DBG_CALIBRATE,
12521 + "Divide by 0: mag_tx=%d, res_scale=%d\n",
12522 + mag_tx, res_scale);
12523 + return false;
12524 + }
12525 +
12526 + /* calculate and quantize Tx IQ correction factor */
12527 + mag_corr_tx = (mag_tx * res_scale) / (res_scale - mag_tx);
12528 + phs_corr_tx = -phs_tx;
12529 +
12530 + q_q_coff = (mag_corr_tx * 128 / res_scale);
12531 + q_i_coff = (phs_corr_tx * 256 / res_scale);
12532 +
12533 + ath_print(common, ATH_DBG_CALIBRATE,
12534 + "tx chain %d: mag corr=%d phase corr=%d\n",
12535 + chain_idx, q_q_coff, q_i_coff);
12536 +
12537 + if (q_i_coff < -63)
12538 + q_i_coff = -63;
12539 + if (q_i_coff > 63)
12540 + q_i_coff = 63;
12541 + if (q_q_coff < -63)
12542 + q_q_coff = -63;
12543 + if (q_q_coff > 63)
12544 + q_q_coff = 63;
12545 +
12546 + iqc_coeff[0] = (q_q_coff * 128) + q_i_coff;
12547 +
12548 + ath_print(common, ATH_DBG_CALIBRATE,
12549 + "tx chain %d: iq corr coeff=%x\n",
12550 + chain_idx, iqc_coeff[0]);
12551 +
12552 + if (-mag_rx == res_scale) {
12553 + ath_print(common, ATH_DBG_CALIBRATE,
12554 + "Divide by 0: mag_rx=%d, res_scale=%d\n",
12555 + mag_rx, res_scale);
12556 + return false;
12557 + }
12558 +
12559 + /* calculate and quantize Rx IQ correction factors */
12560 + mag_corr_rx = (-mag_rx * res_scale) / (res_scale + mag_rx);
12561 + phs_corr_rx = -phs_rx;
12562 +
12563 + q_q_coff = (mag_corr_rx * 128 / res_scale);
12564 + q_i_coff = (phs_corr_rx * 256 / res_scale);
12565 +
12566 + ath_print(common, ATH_DBG_CALIBRATE,
12567 + "rx chain %d: mag corr=%d phase corr=%d\n",
12568 + chain_idx, q_q_coff, q_i_coff);
12569 +
12570 + if (q_i_coff < -63)
12571 + q_i_coff = -63;
12572 + if (q_i_coff > 63)
12573 + q_i_coff = 63;
12574 + if (q_q_coff < -63)
12575 + q_q_coff = -63;
12576 + if (q_q_coff > 63)
12577 + q_q_coff = 63;
12578 +
12579 + iqc_coeff[1] = (q_q_coff * 128) + q_i_coff;
12580 +
12581 + ath_print(common, ATH_DBG_CALIBRATE,
12582 + "rx chain %d: iq corr coeff=%x\n",
12583 + chain_idx, iqc_coeff[1]);
12584 +
12585 + return true;
12586 +}
12587 +
12588 +static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
12589 +{
12590 + struct ath_common *common = ath9k_hw_common(ah);
12591 + const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
12592 + AR_PHY_TX_IQCAL_STATUS_B0,
12593 + AR_PHY_TX_IQCAL_STATUS_B1,
12594 + AR_PHY_TX_IQCAL_STATUS_B2,
12595 + };
12596 + const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = {
12597 + AR_PHY_TX_IQCAL_CORR_COEFF_01_B0,
12598 + AR_PHY_TX_IQCAL_CORR_COEFF_01_B1,
12599 + AR_PHY_TX_IQCAL_CORR_COEFF_01_B2,
12600 + };
12601 + const u32 rx_corr[AR9300_MAX_CHAINS] = {
12602 + AR_PHY_RX_IQCAL_CORR_B0,
12603 + AR_PHY_RX_IQCAL_CORR_B1,
12604 + AR_PHY_RX_IQCAL_CORR_B2,
12605 + };
12606 + const u_int32_t chan_info_tab[] = {
12607 + AR_PHY_CHAN_INFO_TAB_0,
12608 + AR_PHY_CHAN_INFO_TAB_1,
12609 + AR_PHY_CHAN_INFO_TAB_2,
12610 + };
12611 + s32 iq_res[6];
12612 + s32 iqc_coeff[2];
12613 + s32 i, j;
12614 + u32 num_chains = 0;
12615 +
12616 + for (i = 0; i < AR9300_MAX_CHAINS; i++) {
12617 + if (ah->txchainmask & (1 << i))
12618 + num_chains++;
12619 + }
12620 +
12621 + REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
12622 + AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
12623 + DELPT);
12624 + REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
12625 + AR_PHY_TX_IQCAL_START_DO_CAL,
12626 + AR_PHY_TX_IQCAL_START_DO_CAL);
12627 +
12628 + if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
12629 + AR_PHY_TX_IQCAL_START_DO_CAL,
12630 + 0, AH_WAIT_TIMEOUT)) {
12631 + ath_print(common, ATH_DBG_CALIBRATE,
12632 + "Tx IQ Cal not complete.\n");
12633 + goto TX_IQ_CAL_FAILED;
12634 + }
12635 +
12636 + for (i = 0; i < num_chains; i++) {
12637 + ath_print(common, ATH_DBG_CALIBRATE,
12638 + "Doing Tx IQ Cal for chain %d.\n", i);
12639 +
12640 + if (REG_READ(ah, txiqcal_status[i]) &
12641 + AR_PHY_TX_IQCAL_STATUS_FAILED) {
12642 + ath_print(common, ATH_DBG_CALIBRATE,
12643 + "Tx IQ Cal failed for chain %d.\n", i);
12644 + goto TX_IQ_CAL_FAILED;
12645 + }
12646 +
12647 + for (j = 0; j < 3; j++) {
12648 + u_int8_t idx = 2 * j,
12649 + offset = 4 * j;
12650 +
12651 + REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
12652 + AR_PHY_CHAN_INFO_TAB_S2_READ, 0);
12653 +
12654 + /* 32 bits */
12655 + iq_res[idx] = REG_READ(ah, chan_info_tab[i] + offset);
12656 +
12657 + REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
12658 + AR_PHY_CHAN_INFO_TAB_S2_READ, 1);
12659 +
12660 + /* 16 bits */
12661 + iq_res[idx+1] = 0xffff & REG_READ(ah, chan_info_tab[i] + offset);
12662 +
12663 + ath_print(common, ATH_DBG_CALIBRATE,
12664 + "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
12665 + idx, iq_res[idx], idx+1, iq_res[idx+1]);
12666 + }
12667 +
12668 + if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) {
12669 + ath_print(common, ATH_DBG_CALIBRATE,
12670 + "Failed in calculation of IQ correction.\n");
12671 + goto TX_IQ_CAL_FAILED;
12672 + }
12673 +
12674 + ath_print(common, ATH_DBG_CALIBRATE,
12675 + "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n",
12676 + iqc_coeff[0], iqc_coeff[1]);
12677 +
12678 + REG_RMW_FIELD(ah, tx_corr_coeff[i],
12679 + AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
12680 + iqc_coeff[0]);
12681 + REG_RMW_FIELD(ah, rx_corr[i],
12682 + AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,
12683 + iqc_coeff[1] >> 7);
12684 + REG_RMW_FIELD(ah, rx_corr[i],
12685 + AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
12686 + iqc_coeff[1]);
12687 + }
12688 +
12689 + REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
12690 + AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
12691 + REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
12692 + AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
12693 +
12694 + return;
12695 +
12696 +TX_IQ_CAL_FAILED:
12697 + ath_print(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
12698 + return;
12699 +}
12700 +
12701 +static bool ar9003_hw_init_cal(struct ath_hw *ah,
12702 + struct ath9k_channel *chan)
12703 +{
12704 + struct ath_common *common = ath9k_hw_common(ah);
12705 +
12706 + /*
12707 + * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
12708 + * running AGC/TxIQ cals
12709 + */
12710 + ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
12711 +
12712 + /* Calibrate the AGC */
12713 + REG_WRITE(ah, AR_PHY_AGC_CONTROL,
12714 + REG_READ(ah, AR_PHY_AGC_CONTROL) |
12715 + AR_PHY_AGC_CONTROL_CAL);
12716 +
12717 + /* Poll for offset calibration complete */
12718 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
12719 + 0, AH_WAIT_TIMEOUT)) {
12720 + ath_print(common, ATH_DBG_CALIBRATE,
12721 + "offset calibration failed to "
12722 + "complete in 1ms; noisy environment?\n");
12723 + return false;
12724 + }
12725 +
12726 + /* Do Tx IQ Calibration */
12727 + ar9003_hw_tx_iq_cal(ah);
12728 +
12729 + /* Revert chainmasks to their original values before NF cal */
12730 + ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
12731 +
12732 + /* Initialize list pointers */
12733 + ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
12734 +
12735 + if (ar9003_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
12736 + INIT_CAL(&ah->iq_caldata);
12737 + INSERT_CAL(ah, &ah->iq_caldata);
12738 + ath_print(common, ATH_DBG_CALIBRATE,
12739 + "enabling IQ Calibration.\n");
12740 + }
12741 +
12742 + if (ar9003_hw_iscal_supported(ah, TEMP_COMP_CAL)) {
12743 + INIT_CAL(&ah->tempCompCalData);
12744 + INSERT_CAL(ah, &ah->tempCompCalData);
12745 + ath_print(common, ATH_DBG_CALIBRATE,
12746 + "enabling Temperature Compensation Calibration.\n");
12747 + }
12748 +
12749 + /* Initialize current pointer to first element in list */
12750 + ah->cal_list_curr = ah->cal_list;
12751 +
12752 + if (ah->cal_list_curr)
12753 + ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
12754 +
12755 + chan->CalValid = 0;
12756 +
12757 + return true;
12758 +}
12759 +
12760 +void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
12761 +{
12762 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
12763 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
12764 +
12765 + priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
12766 + priv_ops->init_cal = ar9003_hw_init_cal;
12767 + priv_ops->setup_calibration = ar9003_hw_setup_calibration;
12768 + priv_ops->iscal_supported = ar9003_hw_iscal_supported;
12769 +
12770 + ops->calibrate = ar9003_hw_calibrate;
12771 +}
12772 --- /dev/null
12773 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
12774 @@ -0,0 +1,1841 @@
12775 +/*
12776 + * Copyright (c) 2010 Atheros Communications Inc.
12777 + *
12778 + * Permission to use, copy, modify, and/or distribute this software for any
12779 + * purpose with or without fee is hereby granted, provided that the above
12780 + * copyright notice and this permission notice appear in all copies.
12781 + *
12782 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12783 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12784 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12785 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12786 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
12787 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
12788 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
12789 + */
12790 +
12791 +#include "hw.h"
12792 +#include "ar9003_phy.h"
12793 +#include "ar9003_eeprom.h"
12794 +
12795 +#define COMP_HDR_LEN 4
12796 +#define COMP_CKSUM_LEN 2
12797 +
12798 +#define AR_CH0_TOP (0x00016288)
12799 +#define AR_CH0_TOP_XPABIASLVL (0x3)
12800 +#define AR_CH0_TOP_XPABIASLVL_S (8)
12801 +
12802 +#define AR_CH0_THERM (0x00016290)
12803 +#define AR_CH0_THERM_SPARE (0x3f)
12804 +#define AR_CH0_THERM_SPARE_S (0)
12805 +
12806 +#define AR_SWITCH_TABLE_COM_ALL (0xffff)
12807 +#define AR_SWITCH_TABLE_COM_ALL_S (0)
12808 +
12809 +#define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
12810 +#define AR_SWITCH_TABLE_COM2_ALL_S (0)
12811 +
12812 +#define AR_SWITCH_TABLE_ALL (0xfff)
12813 +#define AR_SWITCH_TABLE_ALL_S (0)
12814 +
12815 +static const struct ar9300_eeprom ar9300_default = {
12816 + .eepromVersion = 2,
12817 + .templateVersion = 2,
12818 + .macAddr = {1, 2, 3, 4, 5, 6},
12819 + .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
12820 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
12821 + .baseEepHeader = {
12822 + .regDmn = {0, 0x1f},
12823 + .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
12824 + .opCapFlags = {
12825 + .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
12826 + .eepMisc = 0,
12827 + },
12828 + .rfSilent = 0,
12829 + .blueToothOptions = 0,
12830 + .deviceCap = 0,
12831 + .deviceType = 5, /* takes lower byte in eeprom location */
12832 + .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
12833 + .params_for_tuning_caps = {0, 0},
12834 + .featureEnable = 0x0c,
12835 + /*
12836 + * bit0 - enable tx temp comp - disabled
12837 + * bit1 - enable tx volt comp - disabled
12838 + * bit2 - enable fastClock - enabled
12839 + * bit3 - enable doubling - enabled
12840 + * bit4 - enable internal regulator - disabled
12841 + */
12842 + .miscConfiguration = 0, /* bit0 - turn down drivestrength */
12843 + .eepromWriteEnableGpio = 3,
12844 + .wlanDisableGpio = 0,
12845 + .wlanLedGpio = 8,
12846 + .rxBandSelectGpio = 0xff,
12847 + .txrxgain = 0,
12848 + .swreg = 0,
12849 + },
12850 + .modalHeader2G = {
12851 + /* ar9300_modal_eep_header 2g */
12852 + /* 4 idle,t1,t2,b(4 bits per setting) */
12853 + .antCtrlCommon = 0x110,
12854 + /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
12855 + .antCtrlCommon2 = 0x22222,
12856 +
12857 + /*
12858 + * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
12859 + * rx1, rx12, b (2 bits each)
12860 + */
12861 + .antCtrlChain = {0x150, 0x150, 0x150},
12862 +
12863 + /*
12864 + * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
12865 + * for ar9280 (0xa20c/b20c 5:0)
12866 + */
12867 + .xatten1DB = {0, 0, 0},
12868 +
12869 + /*
12870 + * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
12871 + * for ar9280 (0xa20c/b20c 16:12
12872 + */
12873 + .xatten1Margin = {0, 0, 0},
12874 + .tempSlope = 36,
12875 + .voltSlope = 0,
12876 +
12877 + /*
12878 + * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
12879 + * channels in usual fbin coding format
12880 + */
12881 + .spurChans = {0, 0, 0, 0, 0},
12882 +
12883 + /*
12884 + * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
12885 + * if the register is per chain
12886 + */
12887 + .noiseFloorThreshCh = {-1, 0, 0},
12888 + .ob = {1, 1, 1},/* 3 chain */
12889 + .db_stage2 = {1, 1, 1}, /* 3 chain */
12890 + .db_stage3 = {0, 0, 0},
12891 + .db_stage4 = {0, 0, 0},
12892 + .xpaBiasLvl = 0,
12893 + .txFrameToDataStart = 0x0e,
12894 + .txFrameToPaOn = 0x0e,
12895 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
12896 + .antennaGain = 0,
12897 + .switchSettling = 0x2c,
12898 + .adcDesiredSize = -30,
12899 + .txEndToXpaOff = 0,
12900 + .txEndToRxOn = 0x2,
12901 + .txFrameToXpaOn = 0xe,
12902 + .thresh62 = 28,
12903 + .futureModal = { /* [32] */
12904 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
12905 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
12906 + },
12907 + },
12908 + .calFreqPier2G = {
12909 + FREQ2FBIN(2412, 1),
12910 + FREQ2FBIN(2437, 1),
12911 + FREQ2FBIN(2472, 1),
12912 + },
12913 + /* ar9300_cal_data_per_freq_op_loop 2g */
12914 + .calPierData2G = {
12915 + {{0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}},
12916 + {{0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}},
12917 + {{0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}},
12918 + },
12919 + .calTarget_freqbin_Cck = {
12920 + FREQ2FBIN(2412, 1),
12921 + FREQ2FBIN(2484, 1),
12922 + },
12923 + .calTarget_freqbin_2G = {
12924 + FREQ2FBIN(2412, 1),
12925 + FREQ2FBIN(2437, 1),
12926 + FREQ2FBIN(2472, 1)
12927 + },
12928 + .calTarget_freqbin_2GHT20 = {
12929 + FREQ2FBIN(2412, 1),
12930 + FREQ2FBIN(2437, 1),
12931 + FREQ2FBIN(2472, 1)
12932 + },
12933 + .calTarget_freqbin_2GHT40 = {
12934 + FREQ2FBIN(2412, 1),
12935 + FREQ2FBIN(2437, 1),
12936 + FREQ2FBIN(2472, 1)
12937 + },
12938 + .calTargetPowerCck = {
12939 + /* 1L-5L,5S,11L,11S */
12940 + {{36, 36, 36, 36}},
12941 + {{36, 36, 36, 36}},
12942 + },
12943 + .calTargetPower2G = {
12944 + /* 6-24,36,48,54 */
12945 + {{32, 32, 28, 24}},
12946 + {{32, 32, 28, 24}},
12947 + {{32, 32, 28, 24}},
12948 + },
12949 + .calTargetPower2GHT20 = {
12950 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
12951 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
12952 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
12953 + },
12954 + .calTargetPower2GHT40 = {
12955 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
12956 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
12957 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
12958 + },
12959 + .ctlIndex_2G = {
12960 + 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
12961 + 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
12962 + },
12963 + .ctl_freqbin_2G = {
12964 + {
12965 + FREQ2FBIN(2412, 1),
12966 + FREQ2FBIN(2417, 1),
12967 + FREQ2FBIN(2457, 1),
12968 + FREQ2FBIN(2462, 1)
12969 + },
12970 + {
12971 + FREQ2FBIN(2412, 1),
12972 + FREQ2FBIN(2417, 1),
12973 + FREQ2FBIN(2462, 1),
12974 + 0xFF,
12975 + },
12976 +
12977 + {
12978 + FREQ2FBIN(2412, 1),
12979 + FREQ2FBIN(2417, 1),
12980 + FREQ2FBIN(2462, 1),
12981 + 0xFF,
12982 + },
12983 + {
12984 + FREQ2FBIN(2422, 1),
12985 + FREQ2FBIN(2427, 1),
12986 + FREQ2FBIN(2447, 1),
12987 + FREQ2FBIN(2452, 1)
12988 + },
12989 +
12990 + {
12991 + /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
12992 + /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
12993 + /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
12994 + /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
12995 + },
12996 +
12997 + {
12998 + /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
12999 + /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
13000 + /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
13001 + 0,
13002 + },
13003 +
13004 + {
13005 + /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
13006 + /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
13007 + FREQ2FBIN(2472, 1),
13008 + 0,
13009 + },
13010 +
13011 + {
13012 + /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
13013 + /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
13014 + /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
13015 + /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
13016 + },
13017 +
13018 + {
13019 + /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
13020 + /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
13021 + /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
13022 + },
13023 +
13024 + {
13025 + /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
13026 + /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
13027 + /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
13028 + 0
13029 + },
13030 +
13031 + {
13032 + /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
13033 + /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
13034 + /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
13035 + 0
13036 + },
13037 +
13038 + {
13039 + /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
13040 + /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
13041 + /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
13042 + /* Data[11].ctlEdges[3].bChannel */
13043 + FREQ2FBIN(2462, 1),
13044 + }
13045 + },
13046 + .ctlPowerData_2G = {
13047 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
13048 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
13049 + {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}},
13050 +
13051 + {{{60, 1}, {60, 0}, {0, 0}, {0, 0}}},
13052 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
13053 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
13054 +
13055 + {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}},
13056 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
13057 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
13058 +
13059 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
13060 + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}},
13061 + },
13062 + .modalHeader5G = {
13063 + /* 4 idle,t1,t2,b (4 bits per setting) */
13064 + .antCtrlCommon = 0x110,
13065 + /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
13066 + .antCtrlCommon2 = 0x22222,
13067 + /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
13068 + .antCtrlChain = {
13069 + 0x000, 0x000, 0x000,
13070 + },
13071 + /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
13072 + .xatten1DB = {0, 0, 0},
13073 +
13074 + /*
13075 + * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
13076 + * for merlin (0xa20c/b20c 16:12
13077 + */
13078 + .xatten1Margin = {0, 0, 0},
13079 + .tempSlope = 68,
13080 + .voltSlope = 0,
13081 + /* spurChans spur channels in usual fbin coding format */
13082 + .spurChans = {0, 0, 0, 0, 0},
13083 + /* noiseFloorThreshCh Check if the register is per chain */
13084 + .noiseFloorThreshCh = {-1, 0, 0},
13085 + .ob = {3, 3, 3}, /* 3 chain */
13086 + .db_stage2 = {3, 3, 3}, /* 3 chain */
13087 + .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
13088 + .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
13089 + .xpaBiasLvl = 0,
13090 + .txFrameToDataStart = 0x0e,
13091 + .txFrameToPaOn = 0x0e,
13092 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
13093 + .antennaGain = 0,
13094 + .switchSettling = 0x2d,
13095 + .adcDesiredSize = -30,
13096 + .txEndToXpaOff = 0,
13097 + .txEndToRxOn = 0x2,
13098 + .txFrameToXpaOn = 0xe,
13099 + .thresh62 = 28,
13100 + .futureModal = {
13101 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13102 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
13103 + },
13104 + },
13105 + .calFreqPier5G = {
13106 + FREQ2FBIN(5180, 0),
13107 + FREQ2FBIN(5220, 0),
13108 + FREQ2FBIN(5320, 0),
13109 + FREQ2FBIN(5400, 0),
13110 + FREQ2FBIN(5500, 0),
13111 + FREQ2FBIN(5600, 0),
13112 + FREQ2FBIN(5725, 0),
13113 + FREQ2FBIN(5825, 0)
13114 + },
13115 + .calPierData5G = {
13116 + {
13117 + {0, 0, 0, 0, 0},
13118 + {0, 0, 0, 0, 0},
13119 + {0, 0, 0, 0, 0},
13120 + {0, 0, 0, 0, 0},
13121 + {0, 0, 0, 0, 0},
13122 + {0, 0, 0, 0, 0},
13123 + {0, 0, 0, 0, 0},
13124 + {0, 0, 0, 0, 0},
13125 + },
13126 + {
13127 + {0, 0, 0, 0, 0},
13128 + {0, 0, 0, 0, 0},
13129 + {0, 0, 0, 0, 0},
13130 + {0, 0, 0, 0, 0},
13131 + {0, 0, 0, 0, 0},
13132 + {0, 0, 0, 0, 0},
13133 + {0, 0, 0, 0, 0},
13134 + {0, 0, 0, 0, 0},
13135 + },
13136 + {
13137 + {0, 0, 0, 0, 0},
13138 + {0, 0, 0, 0, 0},
13139 + {0, 0, 0, 0, 0},
13140 + {0, 0, 0, 0, 0},
13141 + {0, 0, 0, 0, 0},
13142 + {0, 0, 0, 0, 0},
13143 + {0, 0, 0, 0, 0},
13144 + {0, 0, 0, 0, 0},
13145 + },
13146 +
13147 + },
13148 + .calTarget_freqbin_5G = {
13149 + FREQ2FBIN(5180, 0),
13150 + FREQ2FBIN(5220, 0),
13151 + FREQ2FBIN(5320, 0),
13152 + FREQ2FBIN(5400, 0),
13153 + FREQ2FBIN(5500, 0),
13154 + FREQ2FBIN(5600, 0),
13155 + FREQ2FBIN(5725, 0),
13156 + FREQ2FBIN(5825, 0)
13157 + },
13158 + .calTarget_freqbin_5GHT20 = {
13159 + FREQ2FBIN(5180, 0),
13160 + FREQ2FBIN(5240, 0),
13161 + FREQ2FBIN(5320, 0),
13162 + FREQ2FBIN(5500, 0),
13163 + FREQ2FBIN(5700, 0),
13164 + FREQ2FBIN(5745, 0),
13165 + FREQ2FBIN(5725, 0),
13166 + FREQ2FBIN(5825, 0)
13167 + },
13168 + .calTarget_freqbin_5GHT40 = {
13169 + FREQ2FBIN(5180, 0),
13170 + FREQ2FBIN(5240, 0),
13171 + FREQ2FBIN(5320, 0),
13172 + FREQ2FBIN(5500, 0),
13173 + FREQ2FBIN(5700, 0),
13174 + FREQ2FBIN(5745, 0),
13175 + FREQ2FBIN(5725, 0),
13176 + FREQ2FBIN(5825, 0)
13177 + },
13178 + .calTargetPower5G = {
13179 + /* 6-24,36,48,54 */
13180 + {{20, 20, 20, 10}},
13181 + {{20, 20, 20, 10}},
13182 + {{20, 20, 20, 10}},
13183 + {{20, 20, 20, 10}},
13184 + {{20, 20, 20, 10}},
13185 + {{20, 20, 20, 10}},
13186 + {{20, 20, 20, 10}},
13187 + {{20, 20, 20, 10}},
13188 + },
13189 + .calTargetPower5GHT20 = {
13190 + /*
13191 + * 0_8_16,1-3_9-11_17-19,
13192 + * 4,5,6,7,12,13,14,15,20,21,22,23
13193 + */
13194 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13195 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13196 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13197 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13198 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13199 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13200 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13201 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13202 + },
13203 + .calTargetPower5GHT40 = {
13204 + /*
13205 + * 0_8_16,1-3_9-11_17-19,
13206 + * 4,5,6,7,12,13,14,15,20,21,22,23
13207 + */
13208 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13209 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13210 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13211 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13212 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13213 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13214 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13215 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
13216 + },
13217 + .ctlIndex_5G = {
13218 + 0x10, 0x16, 0x18, 0x40, 0x46,
13219 + 0x48, 0x30, 0x36, 0x38
13220 + },
13221 + .ctl_freqbin_5G = {
13222 + {
13223 + /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
13224 + /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
13225 + /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
13226 + /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
13227 + /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
13228 + /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
13229 + /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
13230 + /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
13231 + },
13232 + {
13233 + /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
13234 + /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
13235 + /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
13236 + /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
13237 + /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
13238 + /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
13239 + /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
13240 + /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
13241 + },
13242 +
13243 + {
13244 + /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
13245 + /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
13246 + /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
13247 + /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
13248 + /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
13249 + /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
13250 + /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
13251 + /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
13252 + },
13253 +
13254 + {
13255 + /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
13256 + /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
13257 + /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
13258 + /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
13259 + /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
13260 + /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
13261 + /* Data[3].ctlEdges[6].bChannel */ 0xFF,
13262 + /* Data[3].ctlEdges[7].bChannel */ 0xFF,
13263 + },
13264 +
13265 + {
13266 + /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
13267 + /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
13268 + /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
13269 + /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
13270 + /* Data[4].ctlEdges[4].bChannel */ 0xFF,
13271 + /* Data[4].ctlEdges[5].bChannel */ 0xFF,
13272 + /* Data[4].ctlEdges[6].bChannel */ 0xFF,
13273 + /* Data[4].ctlEdges[7].bChannel */ 0xFF,
13274 + },
13275 +
13276 + {
13277 + /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
13278 + /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
13279 + /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
13280 + /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
13281 + /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
13282 + /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
13283 + /* Data[5].ctlEdges[6].bChannel */ 0xFF,
13284 + /* Data[5].ctlEdges[7].bChannel */ 0xFF
13285 + },
13286 +
13287 + {
13288 + /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
13289 + /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
13290 + /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
13291 + /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
13292 + /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
13293 + /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
13294 + /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
13295 + /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
13296 + },
13297 +
13298 + {
13299 + /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
13300 + /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
13301 + /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
13302 + /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
13303 + /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
13304 + /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
13305 + /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
13306 + /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
13307 + },
13308 +
13309 + {
13310 + /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
13311 + /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
13312 + /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
13313 + /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
13314 + /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
13315 + /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
13316 + /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
13317 + /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
13318 + }
13319 + },
13320 + .ctlPowerData_5G = {
13321 + {
13322 + {
13323 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
13324 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
13325 + }
13326 + },
13327 + {
13328 + {
13329 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
13330 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
13331 + }
13332 + },
13333 + {
13334 + {
13335 + {60, 0}, {60, 1}, {60, 0}, {60, 1},
13336 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
13337 + }
13338 + },
13339 + {
13340 + {
13341 + {60, 0}, {60, 1}, {60, 1}, {60, 0},
13342 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
13343 + }
13344 + },
13345 + {
13346 + {
13347 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
13348 + {60, 0}, {60, 0}, {60, 0}, {60, 0},
13349 + }
13350 + },
13351 + {
13352 + {
13353 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
13354 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
13355 + }
13356 + },
13357 + {
13358 + {
13359 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
13360 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
13361 + }
13362 + },
13363 + {
13364 + {
13365 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
13366 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
13367 + }
13368 + },
13369 + {
13370 + {
13371 + {60, 1}, {60, 0}, {60, 1}, {60, 1},
13372 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
13373 + }
13374 + },
13375 + }
13376 +};
13377 +
13378 +static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
13379 +{
13380 + return 0;
13381 +}
13382 +
13383 +static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
13384 + enum eeprom_param param)
13385 +{
13386 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
13387 + struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
13388 +
13389 + switch (param) {
13390 + case EEP_MAC_LSW:
13391 + return eep->macAddr[0] << 8 | eep->macAddr[1];
13392 + case EEP_MAC_MID:
13393 + return eep->macAddr[2] << 8 | eep->macAddr[3];
13394 + case EEP_MAC_MSW:
13395 + return eep->macAddr[4] << 8 | eep->macAddr[5];
13396 + case EEP_REG_0:
13397 + return pBase->regDmn[0];
13398 + case EEP_REG_1:
13399 + return pBase->regDmn[1];
13400 + case EEP_OP_CAP:
13401 + return pBase->deviceCap;
13402 + case EEP_OP_MODE:
13403 + return pBase->opCapFlags.opFlags;
13404 + case EEP_RF_SILENT:
13405 + return pBase->rfSilent;
13406 + case EEP_TX_MASK:
13407 + return (pBase->txrxMask >> 4) & 0xf;
13408 + case EEP_RX_MASK:
13409 + return pBase->txrxMask & 0xf;
13410 + case EEP_DRIVE_STRENGTH:
13411 +#define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
13412 + return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
13413 + case EEP_INTERNAL_REGULATOR:
13414 + /* Bit 4 is internal regulator flag */
13415 + return ((pBase->featureEnable & 0x10) >> 4);
13416 + case EEP_SWREG:
13417 + return (pBase->swreg);
13418 + default:
13419 + return 0;
13420 + }
13421 +}
13422 +
13423 +#ifdef __BIG_ENDIAN
13424 +static void ar9300_swap_eeprom(struct ar9300_eeprom *eep)
13425 +{
13426 + u32 dword;
13427 + u16 word;
13428 + int i;
13429 +
13430 + word = swab16(eep->baseEepHeader.regDmn[0]);
13431 + eep->baseEepHeader.regDmn[0] = word;
13432 +
13433 + word = swab16(eep->baseEepHeader.regDmn[1]);
13434 + eep->baseEepHeader.regDmn[1] = word;
13435 +
13436 + dword = swab32(eep->modalHeader2G.antCtrlCommon);
13437 + eep->modalHeader2G.antCtrlCommon = dword;
13438 +
13439 + dword = swab32(eep->modalHeader2G.antCtrlCommon2);
13440 + eep->modalHeader2G.antCtrlCommon2 = dword;
13441 +
13442 + dword = swab32(eep->modalHeader5G.antCtrlCommon);
13443 + eep->modalHeader5G.antCtrlCommon = dword;
13444 +
13445 + dword = swab32(eep->modalHeader5G.antCtrlCommon2);
13446 + eep->modalHeader5G.antCtrlCommon2 = dword;
13447 +
13448 + for (i = 0; i < AR9300_MAX_CHAINS; i++) {
13449 + word = swab16(eep->modalHeader2G.antCtrlChain[i]);
13450 + eep->modalHeader2G.antCtrlChain[i] = word;
13451 +
13452 + word = swab16(eep->modalHeader5G.antCtrlChain[i]);
13453 + eep->modalHeader5G.antCtrlChain[i] = word;
13454 + }
13455 +}
13456 +#endif
13457 +
13458 +static bool ar9300_hw_read_eeprom(struct ath_hw *ah,
13459 + long address, u8 * buffer, int many)
13460 +{
13461 + int i;
13462 + u8 value[2];
13463 + unsigned long eepAddr;
13464 + unsigned long byteAddr;
13465 + u16 *svalue;
13466 + struct ath_common *common = ath9k_hw_common(ah);
13467 +
13468 + if ((address < 0) || ((address + many) > AR9300_EEPROM_SIZE - 1)) {
13469 + ath_print(common, ATH_DBG_EEPROM,
13470 + "eeprom address not in range \n");
13471 + return false;
13472 + }
13473 +
13474 + for (i = 0; i < many; i++) {
13475 + eepAddr = (u16) (address + i) / 2;
13476 + byteAddr = (u16) (address + i) % 2;
13477 + svalue = (u16 *) value;
13478 + if (!ath9k_hw_nvram_read(common, eepAddr, svalue)) {
13479 + ath_print(common, ATH_DBG_EEPROM,
13480 + "unable to read eeprom region\n");
13481 + return false;
13482 + }
13483 + *svalue = le16_to_cpu(*svalue);
13484 + buffer[i] = value[byteAddr];
13485 + }
13486 +
13487 + return true;
13488 +}
13489 +
13490 +static bool ar9300_read_eeprom(struct ath_hw *ah,
13491 + int address, u8 * buffer, int many)
13492 +{
13493 + int it;
13494 +
13495 + for (it = 0; it < many; it++)
13496 + if (!ar9300_hw_read_eeprom(ah, (address - it), (buffer + it), 1))
13497 + return false;
13498 + return true;
13499 +}
13500 +
13501 +static void ar9300_comp_hdr_unpack(u8 * best, int *code, int *reference,
13502 + int *length, int *major, int *minor)
13503 +{
13504 + unsigned long value[4];
13505 +
13506 + value[0] = best[0];
13507 + value[1] = best[1];
13508 + value[2] = best[2];
13509 + value[3] = best[3];
13510 + *code = ((value[0] >> 5) & 0x0007);
13511 + *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
13512 + *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
13513 + *major = (value[2] & 0x000f);
13514 + *minor = (value[3] & 0x00ff);
13515 +}
13516 +
13517 +static u16 ar9300_comp_cksum(u8 * data, int dsize)
13518 +{
13519 + int it, checksum = 0;
13520 +
13521 + for (it = 0; it < dsize; it++) {
13522 + checksum += data[it];
13523 + checksum &= 0xffff;
13524 + }
13525 +
13526 + return checksum;
13527 +}
13528 +
13529 +static bool ar9300_uncompress_block(struct ath_hw *ah,
13530 + u8 *mptr,
13531 + int mdataSize,
13532 + u8 *block,
13533 + int size)
13534 +{
13535 + int it;
13536 + int spot;
13537 + int offset;
13538 + int length;
13539 + struct ath_common *common = ath9k_hw_common(ah);
13540 +
13541 + spot = 0;
13542 +
13543 + for (it = 0; it < size; it += (length+2)) {
13544 + offset = block[it];
13545 + offset &= 0xff;
13546 + spot += offset;
13547 + length = block[it+1];
13548 + length &= 0xff;
13549 +
13550 + if (length > 0 && spot >= 0 && spot+length < mdataSize) {
13551 + ath_print(common, ATH_DBG_EEPROM,
13552 + "Restore at %d: spot=%d offset=%d length=%d\n",
13553 + it, spot, offset, length);
13554 + memcpy(&mptr[spot],&block[it+2],length);
13555 + spot += length;
13556 + } else if (length > 0) {
13557 + ath_print(common, ATH_DBG_EEPROM,
13558 + "Bad restore at %d: spot=%d offset=%d length=%d\n",
13559 + it, spot, offset, length);
13560 + return false;
13561 + }
13562 + }
13563 + return true;
13564 +}
13565 +
13566 +static int ar9300_compress_decision(struct ath_hw *ah,
13567 + int it,
13568 + int code,
13569 + int reference,
13570 + u8 * mptr,
13571 + u8 * word, int length, int mdata_size)
13572 +{
13573 + struct ath_common *common = ath9k_hw_common(ah);
13574 + u8 *dptr;
13575 +
13576 + switch (code) {
13577 + case _CompressNone:
13578 + if (length != mdata_size) {
13579 + ath_print(common, ATH_DBG_EEPROM,
13580 + "EEPROM structure size mismatch"
13581 + "memory=%d eeprom=%d\n", mdata_size, length);
13582 + return -1;
13583 + }
13584 + memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
13585 + ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:"
13586 + " uncompressed, length %d\n", it, length);
13587 + break;
13588 + case _CompressBlock:
13589 + if (reference == 0) {
13590 + dptr = mptr;
13591 + } else {
13592 + if (reference != 2) {
13593 + ath_print(common, ATH_DBG_EEPROM,
13594 + "cant find reference eeprom"
13595 + "struct %d\n", reference);
13596 + return -1;
13597 + }
13598 + memcpy(mptr, &ar9300_default, mdata_size);
13599 + }
13600 + ath_print(common, ATH_DBG_EEPROM,
13601 + "restore eeprom %d: block, reference %d,"
13602 + " length %d\n", it, reference, length);
13603 + ar9300_uncompress_block(ah, mptr, mdata_size,
13604 + (u8 *) (word + COMP_HDR_LEN), length);
13605 + break;
13606 + default:
13607 + ath_print(common, ATH_DBG_EEPROM, "unknown compression"
13608 + " code %d\n", code);
13609 + return -1;
13610 + }
13611 + return 0;
13612 +}
13613 +
13614 +/*
13615 + * Read the configuration data from the eeprom.
13616 + * The data can be put in any specified memory buffer.
13617 + *
13618 + * Returns -1 on error.
13619 + * Returns address of next memory location on success.
13620 + */
13621 +static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
13622 + u8 * mptr, int mdata_size)
13623 +{
13624 +#define MDEFAULT 15
13625 +#define MSTATE 100
13626 + int cptr;
13627 + u8 *word;
13628 + int code;
13629 + int reference, length, major, minor;
13630 + int osize;
13631 + int it;
13632 + u16 checksum, mchecksum;
13633 + struct ath_common *common = ath9k_hw_common(ah);
13634 +
13635 + word = kzalloc(2048, GFP_KERNEL);
13636 + if (!word)
13637 + return -1;
13638 +
13639 + memcpy(mptr, &ar9300_default, mdata_size);
13640 +
13641 + cptr = AR9300_BASE_ADDR;
13642 + for (it = 0; it < MSTATE; it++) {
13643 + if (!ar9300_read_eeprom(ah, cptr, word, COMP_HDR_LEN))
13644 + goto fail;
13645 +
13646 + if ((word[0] == 0 && word[1] == 0 && word[2] == 0 &&
13647 + word[3] == 0) || (word[0] == 0xff && word[1] == 0xff
13648 + && word[2] == 0xff && word[3] == 0xff))
13649 + break;
13650 +
13651 + ar9300_comp_hdr_unpack(word, &code, &reference,
13652 + &length, &major, &minor);
13653 + ath_print(common, ATH_DBG_EEPROM,
13654 + "Found block at %x: code=%d ref=%d"
13655 + "length=%d major=%d minor=%d\n", cptr, code,
13656 + reference, length, major, minor);
13657 + if (length >= 1024) {
13658 + ath_print(common, ATH_DBG_EEPROM,
13659 + "Skipping bad header\n");
13660 + cptr -= COMP_HDR_LEN;
13661 + continue;
13662 + }
13663 +
13664 + osize = length;
13665 + ar9300_read_eeprom(ah, cptr, word,
13666 + COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
13667 + checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
13668 + mchecksum = word[COMP_HDR_LEN + osize] |
13669 + (word[COMP_HDR_LEN + osize + 1] << 8);
13670 + ath_print(common, ATH_DBG_EEPROM,
13671 + "checksum %x %x\n", checksum, mchecksum);
13672 + if (checksum == mchecksum) {
13673 + ar9300_compress_decision(ah, it, code, reference, mptr,
13674 + word, length, mdata_size);
13675 + } else {
13676 + ath_print(common, ATH_DBG_EEPROM,
13677 + "skipping block with bad checksum\n");
13678 + }
13679 + cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
13680 + }
13681 +
13682 + kfree(word);
13683 + return cptr;
13684 +
13685 +fail:
13686 + kfree(word);
13687 + return -1;
13688 +}
13689 +
13690 +/*
13691 + * Restore the configuration structure by reading the eeprom.
13692 + * This function destroys any existing in-memory structure
13693 + * content.
13694 + */
13695 +static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
13696 +{
13697 + u8 *mptr = NULL;
13698 + int mdata_size;
13699 +
13700 + mptr = (u8 *) & ah->eeprom.ar9300_eep;
13701 + mdata_size = sizeof(struct ar9300_eeprom);
13702 +
13703 + if (mptr && mdata_size > 0) {
13704 + /* At this point, mptr points to the eeprom data structure
13705 + * in it's "default" state. If this is big endian, swap the
13706 + * data structures back to "little endian"
13707 + */
13708 + /* First swap, default to Little Endian */
13709 +#ifdef __BIG_ENDIAN
13710 + ar9300_swap_eeprom((struct ar9300_eeprom *)mptr);
13711 +#endif
13712 + if (ar9300_eeprom_restore_internal(ah, mptr, mdata_size) >= 0)
13713 + return true;
13714 +
13715 + /* Second Swap, back to Big Endian */
13716 +#ifdef __BIG_ENDIAN
13717 + ar9300_swap_eeprom((struct ar9300_eeprom *)mptr);
13718 +#endif
13719 + }
13720 + return false;
13721 +}
13722 +
13723 +/* XXX: review hardware docs */
13724 +static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
13725 +{
13726 + return ah->eeprom.ar9300_eep.eepromVersion;
13727 +}
13728 +
13729 +/* XXX: could be read from the eepromVersion, not sure yet */
13730 +static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
13731 +{
13732 + return 0;
13733 +}
13734 +
13735 +static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
13736 + enum ieee80211_band freq_band)
13737 +{
13738 + return 1;
13739 +}
13740 +
13741 +static u16 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
13742 + struct ath9k_channel *chan)
13743 +{
13744 + return -EINVAL;
13745 +}
13746 +
13747 +static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
13748 +{
13749 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
13750 +
13751 + if (is2ghz)
13752 + return eep->modalHeader2G.xpaBiasLvl;
13753 + else
13754 + return eep->modalHeader5G.xpaBiasLvl;
13755 +}
13756 +
13757 +static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
13758 +{
13759 + int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
13760 + REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, (bias & 0x3));
13761 + REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_SPARE,
13762 + ((bias >> 2) & 0x3));
13763 +}
13764 +
13765 +static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
13766 +{
13767 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
13768 +
13769 + if (is2ghz)
13770 + return eep->modalHeader2G.antCtrlCommon;
13771 + else
13772 + return eep->modalHeader5G.antCtrlCommon;
13773 +}
13774 +
13775 +static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
13776 +{
13777 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
13778 +
13779 + if (is2ghz)
13780 + return eep->modalHeader2G.antCtrlCommon2;
13781 + else
13782 + return eep->modalHeader5G.antCtrlCommon2;
13783 +}
13784 +
13785 +static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, bool is2ghz)
13786 +{
13787 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
13788 +
13789 + if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
13790 + if (is2ghz)
13791 + return eep->modalHeader2G.antCtrlChain[chain];
13792 + else
13793 + return eep->modalHeader5G.antCtrlChain[chain];
13794 + }
13795 +
13796 + return 0;
13797 +}
13798 +
13799 +static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
13800 +{
13801 + u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
13802 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
13803 +
13804 + value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
13805 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
13806 +
13807 + value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
13808 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
13809 +
13810 + value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
13811 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
13812 +
13813 + value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
13814 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
13815 +}
13816 +
13817 +static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
13818 +{
13819 + int drive_strength;
13820 + unsigned long reg;
13821 +
13822 + drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
13823 +
13824 + if (!drive_strength)
13825 + return;
13826 +
13827 + reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
13828 + reg &= ~0x00ffffc0;
13829 + reg |= 0x5 << 21;
13830 + reg |= 0x5 << 18;
13831 + reg |= 0x5 << 15;
13832 + reg |= 0x5 << 12;
13833 + reg |= 0x5 << 9;
13834 + reg |= 0x5 << 6;
13835 + REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
13836 +
13837 + reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
13838 + reg &= ~0xffffffe0;
13839 + reg |= 0x5 << 29;
13840 + reg |= 0x5 << 26;
13841 + reg |= 0x5 << 23;
13842 + reg |= 0x5 << 20;
13843 + reg |= 0x5 << 17;
13844 + reg |= 0x5 << 14;
13845 + reg |= 0x5 << 11;
13846 + reg |= 0x5 << 8;
13847 + reg |= 0x5 << 5;
13848 + REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
13849 +
13850 + reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
13851 + reg &= ~0xff800000;
13852 + reg |= 0x5 << 29;
13853 + reg |= 0x5 << 26;
13854 + reg |= 0x5 << 23;
13855 + REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
13856 +}
13857 +
13858 +static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
13859 +{
13860 + int internal_regulator =
13861 + ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
13862 +
13863 + if (internal_regulator) {
13864 + /* Internal regulator is ON. Write swreg register. */
13865 + int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
13866 + REG_WRITE(ah, AR_RTC_REG_CONTROL1,
13867 + REG_READ(ah, AR_RTC_REG_CONTROL1) &
13868 + (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
13869 + REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
13870 + /* Set REG_CONTROL1.SWREG_PROGRAM */
13871 + REG_WRITE(ah, AR_RTC_REG_CONTROL1,
13872 + REG_READ(ah,
13873 + AR_RTC_REG_CONTROL1) |
13874 + AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
13875 + } else {
13876 + REG_WRITE(ah, AR_RTC_SLEEP_CLK,
13877 + (REG_READ(ah,
13878 + AR_RTC_SLEEP_CLK) |
13879 + AR_RTC_FORCE_SWREG_PRD));
13880 + }
13881 +}
13882 +
13883 +static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
13884 + struct ath9k_channel *chan)
13885 +{
13886 + ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
13887 + ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
13888 + ar9003_hw_drive_strength_apply(ah);
13889 + ar9003_hw_internal_regulator_apply(ah);
13890 +}
13891 +
13892 +static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
13893 + struct ath9k_channel *chan)
13894 +{
13895 +}
13896 +
13897 +/*
13898 + * Returns the interpolated y value corresponding to the specified x value
13899 + * from the np ordered pairs of data (px,py).
13900 + * The pairs do not have to be in any order.
13901 + * If the specified x value is less than any of the px,
13902 + * the returned y value is equal to the py for the lowest px.
13903 + * If the specified x value is greater than any of the px,
13904 + * the returned y value is equal to the py for the highest px.
13905 + */
13906 +static int ar9003_hw_power_interpolate(int32_t x,
13907 + int32_t * px, int32_t * py, u_int16_t np)
13908 +{
13909 + int ip = 0;
13910 + int lx = 0, ly = 0, lhave = 0;
13911 + int hx = 0, hy = 0, hhave = 0;
13912 + int dx = 0;
13913 + int y = 0;
13914 +
13915 + lhave = 0;
13916 + hhave = 0;
13917 +
13918 + /* identify best lower and higher x calibration measurement */
13919 + for (ip = 0; ip < np; ip++) {
13920 + dx = x - px[ip];
13921 +
13922 + /* this measurement is higher than our desired x */
13923 + if (dx <= 0) {
13924 + if (!hhave || dx > (x - hx)) {
13925 + /* new best higher x measurement */
13926 + hx = px[ip];
13927 + hy = py[ip];
13928 + hhave = 1;
13929 + }
13930 + }
13931 + /* this measurement is lower than our desired x */
13932 + if (dx >= 0) {
13933 + if (!lhave || dx < (x - lx)) {
13934 + /* new best lower x measurement */
13935 + lx = px[ip];
13936 + ly = py[ip];
13937 + lhave = 1;
13938 + }
13939 + }
13940 + }
13941 +
13942 + /* the low x is good */
13943 + if (lhave) {
13944 + /* so is the high x */
13945 + if (hhave) {
13946 + /* they're the same, so just pick one */
13947 + if (hx == lx)
13948 + y = ly;
13949 + else /* interpolate */
13950 + y = ly + (((x - lx) * (hy - ly)) / (hx - lx));
13951 + } else /* only low is good, use it */
13952 + y = ly;
13953 + } else if (hhave) /* only high is good, use it */
13954 + y = hy;
13955 + else /* nothing is good,this should never happen unless np=0, ???? */
13956 + y = -(1 << 30);
13957 + return y;
13958 +}
13959 +
13960 +static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
13961 + u16 rateIndex, u16 freq, bool is2GHz)
13962 +{
13963 + u16 numPiers, i;
13964 + s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
13965 + s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
13966 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
13967 + struct cal_tgt_pow_legacy *pEepromTargetPwr;
13968 + u8 *pFreqBin;
13969 +
13970 + if (is2GHz) {
13971 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
13972 + pEepromTargetPwr = eep->calTargetPower2G;
13973 + pFreqBin = eep->calTarget_freqbin_2G;
13974 + } else {
13975 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
13976 + pEepromTargetPwr = eep->calTargetPower5G;
13977 + pFreqBin = eep->calTarget_freqbin_5G;
13978 + }
13979 +
13980 + /*
13981 + * create array of channels and targetpower from
13982 + * targetpower piers stored on eeprom
13983 + */
13984 + for (i = 0; i < numPiers; i++) {
13985 + freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
13986 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
13987 + }
13988 +
13989 + /* interpolate to get target power for given frequency */
13990 + return ((u8) ar9003_hw_power_interpolate((s32) freq,
13991 + freqArray,
13992 + targetPowerArray, numPiers));
13993 +}
13994 +
13995 +static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
13996 + u16 rateIndex,
13997 + u16 freq, bool is2GHz)
13998 +{
13999 + u16 numPiers, i;
14000 + s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
14001 + s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
14002 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14003 + struct cal_tgt_pow_ht *pEepromTargetPwr;
14004 + u8 *pFreqBin;
14005 +
14006 + if (is2GHz) {
14007 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
14008 + pEepromTargetPwr = eep->calTargetPower2GHT20;
14009 + pFreqBin = eep->calTarget_freqbin_2GHT20;
14010 + } else {
14011 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
14012 + pEepromTargetPwr = eep->calTargetPower5GHT20;
14013 + pFreqBin = eep->calTarget_freqbin_5GHT20;
14014 + }
14015 +
14016 + /*
14017 + * create array of channels and targetpower
14018 + * from targetpower piers stored on eeprom
14019 + */
14020 + for (i = 0; i < numPiers; i++) {
14021 + freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
14022 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
14023 + }
14024 +
14025 + /* interpolate to get target power for given frequency */
14026 + return ((u8) ar9003_hw_power_interpolate((s32) freq,
14027 + freqArray,
14028 + targetPowerArray, numPiers));
14029 +}
14030 +
14031 +static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
14032 + u16 rateIndex,
14033 + u16 freq, bool is2GHz)
14034 +{
14035 + u16 numPiers, i;
14036 + s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
14037 + s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
14038 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14039 + struct cal_tgt_pow_ht *pEepromTargetPwr;
14040 + u8 *pFreqBin;
14041 +
14042 + if (is2GHz) {
14043 + numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
14044 + pEepromTargetPwr = eep->calTargetPower2GHT40;
14045 + pFreqBin = eep->calTarget_freqbin_2GHT40;
14046 + } else {
14047 + numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
14048 + pEepromTargetPwr = eep->calTargetPower5GHT40;
14049 + pFreqBin = eep->calTarget_freqbin_5GHT40;
14050 + }
14051 +
14052 + /*
14053 + * create array of channels and targetpower from
14054 + * targetpower piers stored on eeprom
14055 + */
14056 + for (i = 0; i < numPiers; i++) {
14057 + freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
14058 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
14059 + }
14060 +
14061 + /* interpolate to get target power for given frequency */
14062 + return ((u8) ar9003_hw_power_interpolate((s32) freq,
14063 + freqArray,
14064 + targetPowerArray, numPiers));
14065 +}
14066 +
14067 +static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
14068 + u16 rateIndex, u16 freq)
14069 +{
14070 + u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
14071 + s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
14072 + s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
14073 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14074 + struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
14075 + u8 *pFreqBin = eep->calTarget_freqbin_Cck;
14076 +
14077 + /*
14078 + * create array of channels and targetpower from
14079 + * targetpower piers stored on eeprom
14080 + */
14081 + for (i = 0; i < numPiers; i++) {
14082 + freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
14083 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
14084 + }
14085 +
14086 + /* interpolate to get target power for given frequency */
14087 + return ((u8) ar9003_hw_power_interpolate((s32) freq,
14088 + freqArray,
14089 + targetPowerArray, numPiers));
14090 +}
14091 +
14092 +/* Set tx power registers to array of values passed in */
14093 +static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
14094 +{
14095 +#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
14096 + /* make sure forced gain is not set */
14097 + REG_WRITE(ah, 0xa458, 0);
14098 +
14099 + /* Write the OFDM power per rate set */
14100 +
14101 + /* 6 (LSB), 9, 12, 18 (MSB) */
14102 + REG_WRITE(ah, 0xa3c0,
14103 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
14104 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
14105 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
14106 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
14107 +
14108 + /* 24 (LSB), 36, 48, 54 (MSB) */
14109 + REG_WRITE(ah, 0xa3c4,
14110 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
14111 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
14112 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
14113 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
14114 +
14115 + /* Write the CCK power per rate set */
14116 +
14117 + /* 1L (LSB), reserved, 2L, 2S (MSB) */
14118 + REG_WRITE(ah, 0xa3c8,
14119 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
14120 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
14121 + // POW_SM(txPowerTimes2, 8) | /* this is reserved for AR9003 */
14122 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
14123 +
14124 + /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
14125 + REG_WRITE(ah, 0xa3cc,
14126 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
14127 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
14128 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
14129 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
14130 + );
14131 +
14132 + /* Write the HT20 power per rate set */
14133 +
14134 + /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
14135 + REG_WRITE(ah, 0xa3d0,
14136 + POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
14137 + POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
14138 + POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
14139 + POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
14140 + );
14141 +
14142 + /* 6 (LSB), 7, 12, 13 (MSB) */
14143 + REG_WRITE(ah, 0xa3d4,
14144 + POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
14145 + POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
14146 + POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
14147 + POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
14148 + );
14149 +
14150 + /* 14 (LSB), 15, 20, 21 */
14151 + REG_WRITE(ah, 0xa3e4,
14152 + POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
14153 + POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
14154 + POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
14155 + POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
14156 + );
14157 +
14158 + /* Mixed HT20 and HT40 rates */
14159 +
14160 + /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
14161 + REG_WRITE(ah, 0xa3e8,
14162 + POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
14163 + POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
14164 + POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
14165 + POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
14166 + );
14167 +
14168 + /* Write the HT40 power per rate set */
14169 + // correct PAR difference between HT40 and HT20/LEGACY
14170 + /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
14171 + REG_WRITE(ah, 0xa3d8,
14172 + POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
14173 + POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
14174 + POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
14175 + POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
14176 + );
14177 +
14178 + /* 6 (LSB), 7, 12, 13 (MSB) */
14179 + REG_WRITE(ah, 0xa3dc,
14180 + POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
14181 + POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
14182 + POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
14183 + POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
14184 + );
14185 +
14186 + /* 14 (LSB), 15, 20, 21 */
14187 + REG_WRITE(ah, 0xa3ec,
14188 + POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
14189 + POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
14190 + POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
14191 + POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
14192 + );
14193 +
14194 + return 0;
14195 +#undef POW_SM
14196 +}
14197 +
14198 +static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq)
14199 +{
14200 + u8 targetPowerValT2[ar9300RateSize];
14201 + /* XXX: hard code for now, need to get from eeprom struct */
14202 + u8 ht40PowerIncForPdadc = 0;
14203 + bool is2GHz = false;
14204 + unsigned int i = 0;
14205 + struct ath_common *common = ath9k_hw_common(ah);
14206 +
14207 + if (freq < 4000)
14208 + is2GHz = true;
14209 +
14210 + targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
14211 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
14212 + is2GHz);
14213 + targetPowerValT2[ALL_TARGET_LEGACY_36] =
14214 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
14215 + is2GHz);
14216 + targetPowerValT2[ALL_TARGET_LEGACY_48] =
14217 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
14218 + is2GHz);
14219 + targetPowerValT2[ALL_TARGET_LEGACY_54] =
14220 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
14221 + is2GHz);
14222 + targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
14223 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
14224 + freq);
14225 + targetPowerValT2[ALL_TARGET_LEGACY_5S] =
14226 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
14227 + targetPowerValT2[ALL_TARGET_LEGACY_11L] =
14228 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
14229 + targetPowerValT2[ALL_TARGET_LEGACY_11S] =
14230 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
14231 + targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
14232 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
14233 + is2GHz);
14234 + targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
14235 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
14236 + freq, is2GHz);
14237 + targetPowerValT2[ALL_TARGET_HT20_4] =
14238 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
14239 + is2GHz);
14240 + targetPowerValT2[ALL_TARGET_HT20_5] =
14241 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
14242 + is2GHz);
14243 + targetPowerValT2[ALL_TARGET_HT20_6] =
14244 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
14245 + is2GHz);
14246 + targetPowerValT2[ALL_TARGET_HT20_7] =
14247 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
14248 + is2GHz);
14249 + targetPowerValT2[ALL_TARGET_HT20_12] =
14250 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
14251 + is2GHz);
14252 + targetPowerValT2[ALL_TARGET_HT20_13] =
14253 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
14254 + is2GHz);
14255 + targetPowerValT2[ALL_TARGET_HT20_14] =
14256 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
14257 + is2GHz);
14258 + targetPowerValT2[ALL_TARGET_HT20_15] =
14259 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
14260 + is2GHz);
14261 + targetPowerValT2[ALL_TARGET_HT20_20] =
14262 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
14263 + is2GHz);
14264 + targetPowerValT2[ALL_TARGET_HT20_21] =
14265 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
14266 + is2GHz);
14267 + targetPowerValT2[ALL_TARGET_HT20_22] =
14268 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
14269 + is2GHz);
14270 + targetPowerValT2[ALL_TARGET_HT20_23] =
14271 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
14272 + is2GHz);
14273 + targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
14274 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
14275 + is2GHz) + ht40PowerIncForPdadc;
14276 + targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
14277 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
14278 + freq,
14279 + is2GHz) + ht40PowerIncForPdadc;
14280 + targetPowerValT2[ALL_TARGET_HT40_4] =
14281 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
14282 + is2GHz) + ht40PowerIncForPdadc;
14283 + targetPowerValT2[ALL_TARGET_HT40_5] =
14284 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
14285 + is2GHz) + ht40PowerIncForPdadc;
14286 + targetPowerValT2[ALL_TARGET_HT40_6] =
14287 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
14288 + is2GHz) + ht40PowerIncForPdadc;
14289 + targetPowerValT2[ALL_TARGET_HT40_7] =
14290 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
14291 + is2GHz) + ht40PowerIncForPdadc;
14292 + targetPowerValT2[ALL_TARGET_HT40_12] =
14293 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
14294 + is2GHz) + ht40PowerIncForPdadc;
14295 + targetPowerValT2[ALL_TARGET_HT40_13] =
14296 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
14297 + is2GHz) + ht40PowerIncForPdadc;
14298 + targetPowerValT2[ALL_TARGET_HT40_14] =
14299 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
14300 + is2GHz) + ht40PowerIncForPdadc;
14301 + targetPowerValT2[ALL_TARGET_HT40_15] =
14302 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
14303 + is2GHz) + ht40PowerIncForPdadc;
14304 + targetPowerValT2[ALL_TARGET_HT40_20] =
14305 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
14306 + is2GHz) + ht40PowerIncForPdadc;
14307 + targetPowerValT2[ALL_TARGET_HT40_21] =
14308 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
14309 + is2GHz) + ht40PowerIncForPdadc;
14310 + targetPowerValT2[ALL_TARGET_HT40_22] =
14311 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
14312 + is2GHz) + ht40PowerIncForPdadc;
14313 + targetPowerValT2[ALL_TARGET_HT40_23] =
14314 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
14315 + is2GHz) + ht40PowerIncForPdadc;
14316 +
14317 + while (i < ar9300RateSize) {
14318 + ath_print(common, ATH_DBG_EEPROM,
14319 + "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
14320 + i++;
14321 +
14322 + ath_print(common, ATH_DBG_EEPROM,
14323 + "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
14324 + i++;
14325 +
14326 + ath_print(common, ATH_DBG_EEPROM,
14327 + "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
14328 + i++;
14329 +
14330 + ath_print(common, ATH_DBG_EEPROM,
14331 + "TPC[%02d] 0x%08x \n", i, targetPowerValT2[i]);
14332 + i++;
14333 + }
14334 +
14335 + /* Write target power array to registers */
14336 + ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
14337 +}
14338 +
14339 +static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
14340 + int mode,
14341 + int ipier,
14342 + int ichain,
14343 + int *pfrequency,
14344 + int *pcorrection,
14345 + int *ptemperature, int *pvoltage)
14346 +{
14347 + u8 *pCalPier;
14348 + struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
14349 + int is2GHz;
14350 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14351 + struct ath_common *common = ath9k_hw_common(ah);
14352 +
14353 + if (ichain >= AR9300_MAX_CHAINS) {
14354 + ath_print(common, ATH_DBG_EEPROM,
14355 + "Invalid chain index, must be less than %d\n",
14356 + AR9300_MAX_CHAINS);
14357 + return -1;
14358 + }
14359 +
14360 + if (mode) { /* 5GHz */
14361 + if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
14362 + ath_print(common, ATH_DBG_EEPROM,
14363 + "Invalid 5GHz cal pier index, must be less than %d\n",
14364 + AR9300_NUM_5G_CAL_PIERS);
14365 + return -1;
14366 + }
14367 + pCalPier = &(eep->calFreqPier5G[ipier]);
14368 + pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
14369 + is2GHz = 0;
14370 + } else {
14371 + if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
14372 + ath_print(common, ATH_DBG_EEPROM,
14373 + "Invalid 2GHz cal pier index, must "
14374 + "be less than %d\n", AR9300_NUM_2G_CAL_PIERS);
14375 + return -1;
14376 + }
14377 +
14378 + pCalPier = &(eep->calFreqPier2G[ipier]);
14379 + pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
14380 + is2GHz = 1;
14381 + }
14382 +
14383 + *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
14384 + *pcorrection = pCalPierStruct->refPower;
14385 + *ptemperature = pCalPierStruct->tempMeas;
14386 + *pvoltage = pCalPierStruct->voltMeas;
14387 +
14388 + return 0;
14389 +}
14390 +
14391 +static int ar9003_hw_power_control_override(struct ath_hw *ah,
14392 + int frequency,
14393 + int *correction,
14394 + int *voltage, int *temperature)
14395 +{
14396 + int tempSlope = 0;
14397 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14398 +
14399 + REG_RMW(ah, AR_PHY_TPC_11_B0,
14400 + (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
14401 + AR_PHY_TPC_OLPC_GAIN_DELTA);
14402 + REG_RMW(ah, AR_PHY_TPC_11_B1,
14403 + (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
14404 + AR_PHY_TPC_OLPC_GAIN_DELTA);
14405 + REG_RMW(ah, AR_PHY_TPC_11_B2,
14406 + (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
14407 + AR_PHY_TPC_OLPC_GAIN_DELTA);
14408 +
14409 + /* enable open loop power control on chip */
14410 + REG_RMW(ah, AR_PHY_TPC_6_B0,
14411 + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
14412 + AR_PHY_TPC_6_ERROR_EST_MODE);
14413 + REG_RMW(ah, AR_PHY_TPC_6_B1,
14414 + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
14415 + AR_PHY_TPC_6_ERROR_EST_MODE);
14416 + REG_RMW(ah, AR_PHY_TPC_6_B2,
14417 + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
14418 + AR_PHY_TPC_6_ERROR_EST_MODE);
14419 +
14420 + /*
14421 + * enable temperature compensation
14422 + * Need to use register names
14423 + */
14424 + if (frequency < 4000)
14425 + tempSlope = eep->modalHeader2G.tempSlope;
14426 + else
14427 + tempSlope = eep->modalHeader5G.tempSlope;
14428 +
14429 + REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
14430 + REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
14431 + temperature[0]);
14432 +
14433 + return 0;
14434 +}
14435 +
14436 +/* Apply the recorded correction values. */
14437 +static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
14438 +{
14439 + int ichain, ipier, npier;
14440 + int mode;
14441 + int lfrequency[AR9300_MAX_CHAINS],
14442 + lcorrection[AR9300_MAX_CHAINS],
14443 + ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
14444 + int hfrequency[AR9300_MAX_CHAINS],
14445 + hcorrection[AR9300_MAX_CHAINS],
14446 + htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
14447 + int fdiff;
14448 + int correction[AR9300_MAX_CHAINS],
14449 + voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
14450 + int pfrequency, pcorrection, ptemperature, pvoltage;
14451 + struct ath_common *common = ath9k_hw_common(ah);
14452 +
14453 + mode = (frequency >= 4000);
14454 + if (mode)
14455 + npier = AR9300_NUM_5G_CAL_PIERS;
14456 + else
14457 + npier = AR9300_NUM_2G_CAL_PIERS;
14458 +
14459 + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
14460 + lfrequency[ichain] = 0;
14461 + hfrequency[ichain] = 100000;
14462 + }
14463 + /* identify best lower and higher frequency calibration measurement */
14464 + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
14465 + for (ipier = 0; ipier < npier; ipier++) {
14466 + if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
14467 + &pfrequency, &pcorrection,
14468 + &ptemperature, &pvoltage)) {
14469 + fdiff = frequency - pfrequency;
14470 +
14471 + /*
14472 + * this measurement is higher than
14473 + * our desired frequency
14474 + */
14475 + if (fdiff <= 0) {
14476 + if (hfrequency[ichain] <= 0 ||
14477 + hfrequency[ichain] >= 100000 ||
14478 + fdiff >
14479 + (frequency - hfrequency[ichain])) {
14480 + /* new best higher frequency measurement */
14481 + hfrequency[ichain] = pfrequency;
14482 + hcorrection[ichain] =
14483 + pcorrection;
14484 + htemperature[ichain] =
14485 + ptemperature;
14486 + hvoltage[ichain] = pvoltage;
14487 + }
14488 + }
14489 + if (fdiff >= 0) {
14490 + if (lfrequency[ichain] <= 0
14491 + || fdiff <
14492 + (frequency - lfrequency[ichain])) {
14493 + /* new best lower frequency measurement */
14494 + lfrequency[ichain] = pfrequency;
14495 + lcorrection[ichain] =
14496 + pcorrection;
14497 + ltemperature[ichain] =
14498 + ptemperature;
14499 + lvoltage[ichain] = pvoltage;
14500 + }
14501 + }
14502 + }
14503 + }
14504 + }
14505 +
14506 + /* interpolate */
14507 + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
14508 + ath_print(common, ATH_DBG_EEPROM,
14509 + "ch=%d f=%d low=%d %d h=%d %d\n",
14510 + ichain, frequency, lfrequency[ichain],
14511 + lcorrection[ichain], hfrequency[ichain],
14512 + hcorrection[ichain]);
14513 + /* they're the same, so just pick one */
14514 + if (hfrequency[ichain] == lfrequency[ichain]) {
14515 + correction[ichain] = lcorrection[ichain];
14516 + voltage[ichain] = lvoltage[ichain];
14517 + temperature[ichain] = ltemperature[ichain];
14518 + }
14519 + /* the low frequency is good */
14520 + else if (frequency - lfrequency[ichain] < 1000) {
14521 + /* so is the high frequency, interpolate */
14522 + if (hfrequency[ichain] - frequency < 1000) {
14523 +
14524 + correction[ichain] = lcorrection[ichain] +
14525 + (((frequency - lfrequency[ichain]) *
14526 + (hcorrection[ichain] -
14527 + lcorrection[ichain])) /
14528 + (hfrequency[ichain] - lfrequency[ichain]));
14529 +
14530 + temperature[ichain] = ltemperature[ichain] +
14531 + (((frequency - lfrequency[ichain]) *
14532 + (htemperature[ichain] -
14533 + ltemperature[ichain])) /
14534 + (hfrequency[ichain] - lfrequency[ichain]));
14535 +
14536 + voltage[ichain] =
14537 + lvoltage[ichain] +
14538 + (((frequency -
14539 + lfrequency[ichain]) * (hvoltage[ichain] -
14540 + lvoltage[ichain]))
14541 + / (hfrequency[ichain] -
14542 + lfrequency[ichain]));
14543 + }
14544 + /* only low is good, use it */
14545 + else {
14546 + correction[ichain] = lcorrection[ichain];
14547 + temperature[ichain] = ltemperature[ichain];
14548 + voltage[ichain] = lvoltage[ichain];
14549 + }
14550 + }
14551 + /* only high is good, use it */
14552 + else if (hfrequency[ichain] - frequency < 1000) {
14553 + correction[ichain] = hcorrection[ichain];
14554 + temperature[ichain] = htemperature[ichain];
14555 + voltage[ichain] = hvoltage[ichain];
14556 + } else { /* nothing is good, presume 0???? */
14557 + correction[ichain] = 0;
14558 + temperature[ichain] = 0;
14559 + voltage[ichain] = 0;
14560 + }
14561 + }
14562 +
14563 + ar9003_hw_power_control_override(ah, frequency, correction, voltage,
14564 + temperature);
14565 +
14566 + ath_print(common, ATH_DBG_EEPROM,
14567 + "for frequency=%d, calibration correction = %d %d %d\n",
14568 + frequency, correction[0], correction[1], correction[2]);
14569 +
14570 + return 0;
14571 +}
14572 +
14573 +static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
14574 + struct ath9k_channel *chan, u16 cfgCtl,
14575 + u8 twiceAntennaReduction,
14576 + u8 twiceMaxRegulatoryPower,
14577 + u8 powerLimit)
14578 +{
14579 + ar9003_hw_set_target_power_eeprom(ah, chan->channel);
14580 + ar9003_hw_calibration_apply(ah, chan->channel);
14581 +}
14582 +
14583 +static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
14584 + u16 i, bool is2GHz)
14585 +{
14586 + return AR_NO_SPUR;
14587 +}
14588 +
14589 +s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
14590 +{
14591 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14592 +
14593 + return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
14594 +}
14595 +
14596 +s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
14597 +{
14598 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14599 +
14600 + return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
14601 +}
14602 +
14603 +const struct eeprom_ops eep_ar9300_ops = {
14604 + .check_eeprom = ath9k_hw_ar9300_check_eeprom,
14605 + .get_eeprom = ath9k_hw_ar9300_get_eeprom,
14606 + .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
14607 + .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
14608 + .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
14609 + .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
14610 + .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
14611 + .set_board_values = ath9k_hw_ar9300_set_board_values,
14612 + .set_addac = ath9k_hw_ar9300_set_addac,
14613 + .set_txpower = ath9k_hw_ar9300_set_txpower,
14614 + .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
14615 +};
14616 --- /dev/null
14617 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
14618 @@ -0,0 +1,323 @@
14619 +#ifndef AR9003_EEPROM_H
14620 +#define AR9003_EEPROM_H
14621 +
14622 +#include <linux/types.h>
14623 +
14624 +#define AR9300_EEP_VER 0xD000
14625 +#define AR9300_EEP_VER_MINOR_MASK 0xFFF
14626 +#define AR9300_EEP_MINOR_VER_1 0x1
14627 +#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
14628 +
14629 +// 16-bit offset location start of calibration struct
14630 +#define AR9300_EEP_START_LOC 256
14631 +#define AR9300_NUM_5G_CAL_PIERS 8
14632 +#define AR9300_NUM_2G_CAL_PIERS 3
14633 +#define AR9300_NUM_5G_20_TARGET_POWERS 8
14634 +#define AR9300_NUM_5G_40_TARGET_POWERS 8
14635 +#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
14636 +#define AR9300_NUM_2G_20_TARGET_POWERS 3
14637 +#define AR9300_NUM_2G_40_TARGET_POWERS 3
14638 +//#define AR9300_NUM_CTLS 21
14639 +#define AR9300_NUM_CTLS_5G 9
14640 +#define AR9300_NUM_CTLS_2G 12
14641 +#define AR9300_CTL_MODE_M 0xF
14642 +#define AR9300_NUM_BAND_EDGES_5G 8
14643 +#define AR9300_NUM_BAND_EDGES_2G 4
14644 +#define AR9300_NUM_PD_GAINS 4
14645 +#define AR9300_PD_GAINS_IN_MASK 4
14646 +#define AR9300_PD_GAIN_ICEPTS 5
14647 +#define AR9300_EEPROM_MODAL_SPURS 5
14648 +#define AR9300_MAX_RATE_POWER 63
14649 +#define AR9300_NUM_PDADC_VALUES 128
14650 +#define AR9300_NUM_RATES 16
14651 +#define AR9300_BCHAN_UNUSED 0xFF
14652 +#define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64
14653 +#define AR9300_OPFLAGS_11A 0x01
14654 +#define AR9300_OPFLAGS_11G 0x02
14655 +#define AR9300_OPFLAGS_5G_HT40 0x04
14656 +#define AR9300_OPFLAGS_2G_HT40 0x08
14657 +#define AR9300_OPFLAGS_5G_HT20 0x10
14658 +#define AR9300_OPFLAGS_2G_HT20 0x20
14659 +#define AR9300_EEPMISC_BIG_ENDIAN 0x01
14660 +#define AR9300_EEPMISC_WOW 0x02
14661 +#define AR9300_CUSTOMER_DATA_SIZE 20
14662 +
14663 +#define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
14664 +#define FBIN2FREQ(x,y) ((y) ? (2300 + x) : (4800 + 5 * x))
14665 +#define AR9300_MAX_CHAINS 3
14666 +#define AR9300_ANT_16S 25
14667 +#define AR9300_FUTURE_MODAL_SZ 6
14668 +
14669 +#define AR9300_NUM_ANT_CHAIN_FIELDS 7
14670 +#define AR9300_NUM_ANT_COMMON_FIELDS 4
14671 +#define AR9300_SIZE_ANT_CHAIN_FIELD 3
14672 +#define AR9300_SIZE_ANT_COMMON_FIELD 4
14673 +#define AR9300_ANT_CHAIN_MASK 0x7
14674 +#define AR9300_ANT_COMMON_MASK 0xf
14675 +#define AR9300_CHAIN_0_IDX 0
14676 +#define AR9300_CHAIN_1_IDX 1
14677 +#define AR9300_CHAIN_2_IDX 2
14678 +
14679 +#define AR928X_NUM_ANT_CHAIN_FIELDS 6
14680 +#define AR928X_SIZE_ANT_CHAIN_FIELD 2
14681 +#define AR928X_ANT_CHAIN_MASK 0x3
14682 +
14683 +/* Delta from which to start power to pdadc table */
14684 +/* This offset is used in both open loop and closed loop power control
14685 + * schemes. In open loop power control, it is not really needed, but for
14686 + * the "sake of consistency" it was kept. For certain AP designs, this
14687 + * value is overwritten by the value in the flag "pwrTableOffset" just
14688 + * before writing the pdadc vs pwr into the chip registers.
14689 + */
14690 +#define AR9300_PWR_TABLE_OFFSET 0
14691 +
14692 +/* enable flags for voltage and temp compensation */
14693 +#define ENABLE_TEMP_COMPENSATION 0x01
14694 +#define ENABLE_VOLT_COMPENSATION 0x02
14695 +/* byte addressable */
14696 +#define AR9300_EEPROM_SIZE 16*1024
14697 +#define FIXED_CCA_THRESHOLD 15
14698 +
14699 +#define AR9300_BASE_ADDR 0x3ff
14700 +
14701 +enum targetPowerHTRates {
14702 + HT_TARGET_RATE_0_8_16,
14703 + HT_TARGET_RATE_1_3_9_11_17_19,
14704 + HT_TARGET_RATE_4,
14705 + HT_TARGET_RATE_5,
14706 + HT_TARGET_RATE_6,
14707 + HT_TARGET_RATE_7,
14708 + HT_TARGET_RATE_12,
14709 + HT_TARGET_RATE_13,
14710 + HT_TARGET_RATE_14,
14711 + HT_TARGET_RATE_15,
14712 + HT_TARGET_RATE_20,
14713 + HT_TARGET_RATE_21,
14714 + HT_TARGET_RATE_22,
14715 + HT_TARGET_RATE_23
14716 +};
14717 +
14718 +enum targetPowerLegacyRates {
14719 + LEGACY_TARGET_RATE_6_24,
14720 + LEGACY_TARGET_RATE_36,
14721 + LEGACY_TARGET_RATE_48,
14722 + LEGACY_TARGET_RATE_54
14723 +};
14724 +
14725 +enum targetPowerCckRates {
14726 + LEGACY_TARGET_RATE_1L_5L,
14727 + LEGACY_TARGET_RATE_5S,
14728 + LEGACY_TARGET_RATE_11L,
14729 + LEGACY_TARGET_RATE_11S
14730 +};
14731 +
14732 +enum ar9300_Rates {
14733 + ALL_TARGET_LEGACY_6_24,
14734 + ALL_TARGET_LEGACY_36,
14735 + ALL_TARGET_LEGACY_48,
14736 + ALL_TARGET_LEGACY_54,
14737 + ALL_TARGET_LEGACY_1L_5L,
14738 + ALL_TARGET_LEGACY_5S,
14739 + ALL_TARGET_LEGACY_11L,
14740 + ALL_TARGET_LEGACY_11S,
14741 + ALL_TARGET_HT20_0_8_16,
14742 + ALL_TARGET_HT20_1_3_9_11_17_19,
14743 + ALL_TARGET_HT20_4,
14744 + ALL_TARGET_HT20_5,
14745 + ALL_TARGET_HT20_6,
14746 + ALL_TARGET_HT20_7,
14747 + ALL_TARGET_HT20_12,
14748 + ALL_TARGET_HT20_13,
14749 + ALL_TARGET_HT20_14,
14750 + ALL_TARGET_HT20_15,
14751 + ALL_TARGET_HT20_20,
14752 + ALL_TARGET_HT20_21,
14753 + ALL_TARGET_HT20_22,
14754 + ALL_TARGET_HT20_23,
14755 + ALL_TARGET_HT40_0_8_16,
14756 + ALL_TARGET_HT40_1_3_9_11_17_19,
14757 + ALL_TARGET_HT40_4,
14758 + ALL_TARGET_HT40_5,
14759 + ALL_TARGET_HT40_6,
14760 + ALL_TARGET_HT40_7,
14761 + ALL_TARGET_HT40_12,
14762 + ALL_TARGET_HT40_13,
14763 + ALL_TARGET_HT40_14,
14764 + ALL_TARGET_HT40_15,
14765 + ALL_TARGET_HT40_20,
14766 + ALL_TARGET_HT40_21,
14767 + ALL_TARGET_HT40_22,
14768 + ALL_TARGET_HT40_23,
14769 + ar9300RateSize,
14770 +};
14771 +
14772 +
14773 +struct eepFlags {
14774 + u8 opFlags;
14775 + u8 eepMisc;
14776 +} __packed;
14777 +
14778 +enum CompressAlgorithm {
14779 + _CompressNone = 0,
14780 + _CompressLzma,
14781 + _CompressPairs,
14782 + _CompressBlock,
14783 + _Compress4,
14784 + _Compress5,
14785 + _Compress6,
14786 + _Compress7,
14787 +};
14788 +
14789 +struct ar9300_base_eep_hdr {
14790 + u16 regDmn[2];
14791 + /* 4 bits tx and 4 bits rx */
14792 + u8 txrxMask;
14793 + struct eepFlags opCapFlags;
14794 + u8 rfSilent;
14795 + u8 blueToothOptions;
14796 + u8 deviceCap;
14797 + /* takes lower byte in eeprom location */
14798 + u8 deviceType;
14799 + /* offset in dB to be added to beginning
14800 + * of pdadc table in calibration
14801 + */
14802 + int8_t pwrTableOffset;
14803 + u8 params_for_tuning_caps[2];
14804 + /*
14805 + * bit0 - enable tx temp comp
14806 + * bit1 - enable tx volt comp
14807 + * bit2 - enable fastClock - default to 1
14808 + * bit3 - enable doubling - default to 1
14809 + * bit4 - enable internal regulator - default to 1
14810 + */
14811 + u8 featureEnable;
14812 + /* misc flags: bit0 - turn down drivestrength */
14813 + u8 miscConfiguration;
14814 + u8 eepromWriteEnableGpio;
14815 + u8 wlanDisableGpio;
14816 + u8 wlanLedGpio;
14817 + u8 rxBandSelectGpio;
14818 + u8 txrxgain;
14819 + /* SW controlled internal regulator fields */
14820 + u32 swreg;
14821 +} __packed;
14822 +
14823 +struct ar9300_modal_eep_header {
14824 + /* 4 idle, t1, t2, b (4 bits per setting) */
14825 + u32 antCtrlCommon;
14826 + /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
14827 + u32 antCtrlCommon2;
14828 + /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
14829 + u16 antCtrlChain[AR9300_MAX_CHAINS];
14830 + /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
14831 + u8 xatten1DB[AR9300_MAX_CHAINS];
14832 + /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
14833 + u8 xatten1Margin[AR9300_MAX_CHAINS];
14834 + int8_t tempSlope;
14835 + int8_t voltSlope;
14836 + /* spur channels in usual fbin coding format */
14837 + u8 spurChans[AR9300_EEPROM_MODAL_SPURS];
14838 + /* 3 Check if the register is per chain */
14839 + int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
14840 + u8 ob[AR9300_MAX_CHAINS];
14841 + u8 db_stage2[AR9300_MAX_CHAINS];
14842 + u8 db_stage3[AR9300_MAX_CHAINS];
14843 + u8 db_stage4[AR9300_MAX_CHAINS];
14844 + u8 xpaBiasLvl;
14845 + u8 txFrameToDataStart;
14846 + u8 txFrameToPaOn;
14847 + u8 txClip;
14848 + int8_t antennaGain;
14849 + u8 switchSettling;
14850 + int8_t adcDesiredSize;
14851 + u8 txEndToXpaOff;
14852 + u8 txEndToRxOn;
14853 + u8 txFrameToXpaOn;
14854 + u8 thresh62;
14855 + u8 futureModal[32];
14856 +} __packed;
14857 +
14858 +struct ar9300_cal_data_per_freq_op_loop {
14859 + int8_t refPower;
14860 + /* pdadc voltage at power measurement */
14861 + u8 voltMeas;
14862 + /* pcdac used for power measurement */
14863 + u8 tempMeas;
14864 + /* range is -60 to -127 create a mapping equation 1db resolution */
14865 + int8_t rxNoisefloorCal;
14866 + /*range is same as noisefloor */
14867 + int8_t rxNoisefloorPower;
14868 + /* temp measured when noisefloor cal was performed */
14869 + u8 rxTempMeas;
14870 +} __packed;
14871 +
14872 +struct cal_tgt_pow_legacy {
14873 + u8 tPow2x[4];
14874 +} __packed;
14875 +
14876 +struct cal_tgt_pow_ht {
14877 + u8 tPow2x[14];
14878 +} __packed;
14879 +
14880 +struct cal_ctl_edge_pwr {
14881 + u8 tPower :6,
14882 + flag :2;
14883 +} __packed;
14884 +
14885 +struct cal_ctl_data_2g {
14886 + struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
14887 +} __packed;
14888 +
14889 +struct cal_ctl_data_5g {
14890 + struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
14891 +} __packed;
14892 +
14893 +struct ar9300_eeprom {
14894 + u8 eepromVersion;
14895 + u8 templateVersion;
14896 + u8 macAddr[6];
14897 + u8 custData[AR9300_CUSTOMER_DATA_SIZE];
14898 +
14899 + struct ar9300_base_eep_hdr baseEepHeader;
14900 +
14901 + struct ar9300_modal_eep_header modalHeader2G;
14902 + u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
14903 + struct ar9300_cal_data_per_freq_op_loop
14904 + calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
14905 + u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
14906 + u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
14907 + u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
14908 + u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
14909 + struct cal_tgt_pow_legacy
14910 + calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
14911 + struct cal_tgt_pow_legacy
14912 + calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
14913 + struct cal_tgt_pow_ht
14914 + calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
14915 + struct cal_tgt_pow_ht
14916 + calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
14917 + u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
14918 + u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
14919 + struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
14920 + struct ar9300_modal_eep_header modalHeader5G;
14921 + u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
14922 + struct ar9300_cal_data_per_freq_op_loop
14923 + calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
14924 + u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
14925 + u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
14926 + u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
14927 + struct cal_tgt_pow_legacy
14928 + calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
14929 + struct cal_tgt_pow_ht
14930 + calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
14931 + struct cal_tgt_pow_ht
14932 + calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
14933 + u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
14934 + u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
14935 + struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
14936 +} __packed;
14937 +
14938 +s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
14939 +s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
14940 +
14941 +#endif
14942 --- /dev/null
14943 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
14944 @@ -0,0 +1,205 @@
14945 +/*
14946 + * Copyright (c) 2008-2010 Atheros Communications Inc.
14947 + *
14948 + * Permission to use, copy, modify, and/or distribute this software for any
14949 + * purpose with or without fee is hereby granted, provided that the above
14950 + * copyright notice and this permission notice appear in all copies.
14951 + *
14952 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14953 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14954 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14955 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14956 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14957 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14958 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14959 + */
14960 +
14961 +#include "hw.h"
14962 +#include "ar9003_initvals.h"
14963 +
14964 +/* General hardware code for the AR9003 hadware family */
14965 +
14966 +static bool ar9003_hw_macversion_supported(u32 macversion)
14967 +{
14968 + switch (macversion) {
14969 + case AR_SREV_VERSION_9300:
14970 + return true;
14971 + default:
14972 + break;
14973 + }
14974 + return false;
14975 +}
14976 +
14977 +/* AR9003 2.0 - new INI format (pre, core, post arrays per subsystem) */
14978 +/*
14979 + * XXX: move TX/RX gain INI to its own init_mode_gain_regs after
14980 + * ensuring it does not affect hardware bring up
14981 + */
14982 +static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
14983 +{
14984 + /* mac */
14985 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
14986 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
14987 + ar9300_2p0_mac_core,
14988 + ARRAY_SIZE(ar9300_2p0_mac_core), 2);
14989 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
14990 + ar9300_2p0_mac_postamble,
14991 + ARRAY_SIZE(ar9300_2p0_mac_postamble), 5);
14992 +
14993 + /* bb */
14994 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
14995 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
14996 + ar9300_2p0_baseband_core,
14997 + ARRAY_SIZE(ar9300_2p0_baseband_core), 2);
14998 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
14999 + ar9300_2p0_baseband_postamble,
15000 + ARRAY_SIZE(ar9300_2p0_baseband_postamble), 5);
15001 +
15002 + /* radio */
15003 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
15004 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
15005 + ar9300_2p0_radio_core,
15006 + ARRAY_SIZE(ar9300_2p0_radio_core), 2);
15007 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
15008 + ar9300_2p0_radio_postamble,
15009 + ARRAY_SIZE(ar9300_2p0_radio_postamble), 5);
15010 +
15011 + /* soc */
15012 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
15013 + ar9300_2p0_soc_preamble,
15014 + ARRAY_SIZE(ar9300_2p0_soc_preamble), 2);
15015 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
15016 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
15017 + ar9300_2p0_soc_postamble,
15018 + ARRAY_SIZE(ar9300_2p0_soc_postamble), 5);
15019 +
15020 + /* rx/tx gain */
15021 + INIT_INI_ARRAY(&ah->iniModesRxGain,
15022 + ar9300Common_rx_gain_table_2p0,
15023 + ARRAY_SIZE(ar9300Common_rx_gain_table_2p0), 2);
15024 + INIT_INI_ARRAY(&ah->iniModesTxGain,
15025 + ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
15026 + ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
15027 + 5);
15028 +
15029 + /* Load PCIE SERDES settings from INI */
15030 +
15031 + /* Awake Setting */
15032 +
15033 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
15034 + ar9300PciePhy_pll_on_clkreq_disable_L1_2p0,
15035 + ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p0),
15036 + 2);
15037 +
15038 + /* Sleep Setting */
15039 +
15040 + INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
15041 + ar9300PciePhy_clkreq_enable_L1_2p0,
15042 + ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p0),
15043 + 2);
15044 +
15045 + /* Fast clock modal settings */
15046 + INIT_INI_ARRAY(&ah->iniModesAdditional,
15047 + ar9300Modes_fast_clock_2p0,
15048 + ARRAY_SIZE(ar9300Modes_fast_clock_2p0),
15049 + 3);
15050 +}
15051 +
15052 +static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
15053 +{
15054 + switch(ar9003_hw_get_tx_gain_idx(ah)) {
15055 + case 0:
15056 + default:
15057 + INIT_INI_ARRAY(&ah->iniModesTxGain,
15058 + ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
15059 + ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
15060 + 5);
15061 + break;
15062 + case 1:
15063 + INIT_INI_ARRAY(&ah->iniModesTxGain,
15064 + ar9300Modes_high_ob_db_tx_gain_table_2p0,
15065 + ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p0),
15066 + 5);
15067 + break;
15068 + case 2:
15069 + INIT_INI_ARRAY(&ah->iniModesTxGain,
15070 + ar9300Modes_low_ob_db_tx_gain_table_2p0,
15071 + ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p0),
15072 + 5);
15073 + break;
15074 + }
15075 +}
15076 +
15077 +static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
15078 +{
15079 + switch(ar9003_hw_get_rx_gain_idx(ah))
15080 + {
15081 + case 0:
15082 + default:
15083 + INIT_INI_ARRAY(&ah->iniModesRxGain, ar9300Common_rx_gain_table_2p0,
15084 + ARRAY_SIZE(ar9300Common_rx_gain_table_2p0),
15085 + 2);
15086 + break;
15087 + case 1:
15088 + INIT_INI_ARRAY(&ah->iniModesRxGain,
15089 + ar9300Common_wo_xlna_rx_gain_table_2p0,
15090 + ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p0),
15091 + 2);
15092 + break;
15093 + }
15094 +}
15095 +
15096 +/* set gain table pointers according to values read from the eeprom */
15097 +static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
15098 +{
15099 + ar9003_tx_gain_table_apply(ah);
15100 + ar9003_rx_gain_table_apply(ah);
15101 +}
15102 +
15103 +/*
15104 + * Helper for ASPM support.
15105 + *
15106 + * Disable PLL when in L0s as well as receiver clock when in L1.
15107 + * This power saving option must be enabled through the SerDes.
15108 + *
15109 + * Programming the SerDes must go through the same 288 bit serial shift
15110 + * register as the other analog registers. Hence the 9 writes.
15111 + */
15112 +static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
15113 + int restore,
15114 + int power_off)
15115 +{
15116 + if (ah->is_pciexpress != true)
15117 + return;
15118 +
15119 + /* Do not touch SerDes registers */
15120 + if (ah->config.pcie_powersave_enable == 2)
15121 + return;
15122 +
15123 + /* Nothing to do on restore for 11N */
15124 + if (!restore) {
15125 + /* set bit 19 to allow forcing of pcie core into L1 state */
15126 + REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
15127 +
15128 + /* Several PCIe massages to ensure proper behaviour */
15129 + if (ah->config.pcie_waen)
15130 + REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
15131 + }
15132 +}
15133 +
15134 +/* Sets up the AR9003 hardware familiy callbacks */
15135 +void ar9003_hw_attach_ops(struct ath_hw *ah)
15136 +{
15137 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
15138 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
15139 +
15140 + priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
15141 + priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
15142 + priv_ops->macversion_supported = ar9003_hw_macversion_supported;
15143 +
15144 + ops->config_pci_powersave = ar9003_hw_configpcipowersave;
15145 +
15146 + ar9003_hw_attach_phy_ops(ah);
15147 + ar9003_hw_attach_calib_ops(ah);
15148 + ar9003_hw_attach_mac_ops(ah);
15149 +}
15150 --- /dev/null
15151 +++ b/drivers/net/wireless/ath/ath9k/ar9003_initvals.h
15152 @@ -0,0 +1,1793 @@
15153 +/*
15154 + * Copyright (c) 2010 Atheros Communications Inc.
15155 + *
15156 + * Permission to use, copy, modify, and/or distribute this software for any
15157 + * purpose with or without fee is hereby granted, provided that the above
15158 + * copyright notice and this permission notice appear in all copies.
15159 + *
15160 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15161 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15162 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15163 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15164 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15165 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15166 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15167 + */
15168 +
15169 +#ifndef INITVALS_9003_H
15170 +#define INITVALS_9003_H
15171 +
15172 +/* AR9003 2.0 */
15173 +
15174 +static const u32 ar9300_2p0_radio_postamble[][5] = {
15175 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
15176 + {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
15177 + {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
15178 + {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
15179 + {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
15180 + {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
15181 + {0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
15182 +};
15183 +
15184 +static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p0[][5] = {
15185 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
15186 + {0x0000a410, 0x000050da, 0x000050da, 0x000050da, 0x000050da},
15187 + {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
15188 + {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
15189 + {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
15190 + {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
15191 + {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
15192 + {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
15193 + {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
15194 + {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
15195 + {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
15196 + {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
15197 + {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
15198 + {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
15199 + {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
15200 + {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
15201 + {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
15202 + {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
15203 + {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
15204 + {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
15205 + {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
15206 + {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
15207 + {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
15208 + {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
15209 + {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
15210 + {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
15211 + {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
15212 + {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
15213 + {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
15214 + {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
15215 + {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
15216 + {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
15217 + {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
15218 + {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
15219 + {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
15220 + {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
15221 + {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
15222 + {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
15223 + {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
15224 + {0x0000a594, 0x1c800223, 0x1c800223, 0x12800400, 0x12800400},
15225 + {0x0000a598, 0x21820220, 0x21820220, 0x16800402, 0x16800402},
15226 + {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
15227 + {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1c800603, 0x1c800603},
15228 + {0x0000a5a4, 0x2f822222, 0x2f822222, 0x21800a02, 0x21800a02},
15229 + {0x0000a5a8, 0x34822225, 0x34822225, 0x25800a04, 0x25800a04},
15230 + {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x28800a20, 0x28800a20},
15231 + {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2c800e20, 0x2c800e20},
15232 + {0x0000a5b4, 0x4282242a, 0x4282242a, 0x30800e22, 0x30800e22},
15233 + {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
15234 + {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
15235 + {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
15236 + {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
15237 + {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
15238 + {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x47801a83, 0x47801a83},
15239 + {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x4a801c84, 0x4a801c84},
15240 + {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x4e801ce3, 0x4e801ce3},
15241 + {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x52801ce5, 0x52801ce5},
15242 + {0x0000a5dc, 0x7086308c, 0x7086308c, 0x56801ce9, 0x56801ce9},
15243 + {0x0000a5e0, 0x738a308a, 0x738a308a, 0x5a801ceb, 0x5a801ceb},
15244 + {0x0000a5e4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
15245 + {0x0000a5e8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
15246 + {0x0000a5ec, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
15247 + {0x0000a5f0, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
15248 + {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
15249 + {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
15250 + {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
15251 + {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
15252 + {0x00016048, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
15253 + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
15254 + {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
15255 + {0x00016448, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
15256 + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
15257 + {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
15258 + {0x00016848, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
15259 + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
15260 +};
15261 +
15262 +static const u32 ar9300Modes_fast_clock_2p0[][3] = {
15263 + /* Addr 5G_HT20 5G_HT40 */
15264 + {0x00001030, 0x00000268, 0x000004d0},
15265 + {0x00001070, 0x0000018c, 0x00000318},
15266 + {0x000010b0, 0x00000fd0, 0x00001fa0},
15267 + {0x00008014, 0x044c044c, 0x08980898},
15268 + {0x0000801c, 0x148ec02b, 0x148ec057},
15269 + {0x00008318, 0x000044c0, 0x00008980},
15270 + {0x00009e00, 0x03721821, 0x03721821},
15271 + {0x0000a230, 0x0000000b, 0x00000016},
15272 + {0x0000a254, 0x00000898, 0x00001130},
15273 +};
15274 +
15275 +static const u32 ar9300_2p0_radio_core[][2] = {
15276 + /* Addr allmodes */
15277 + {0x00016000, 0x36db6db6},
15278 + {0x00016004, 0x6db6db40},
15279 + {0x00016008, 0x73f00000},
15280 + {0x0001600c, 0x00000000},
15281 + {0x00016040, 0x7f80fff8},
15282 + {0x0001604c, 0x76d005b5},
15283 + {0x00016050, 0x556cf031},
15284 + {0x00016054, 0x43449440},
15285 + {0x00016058, 0x0c51c92c},
15286 + {0x0001605c, 0x3db7fffc},
15287 + {0x00016060, 0xfffffffc},
15288 + {0x00016064, 0x000f0278},
15289 + {0x0001606c, 0x6db60000},
15290 + {0x00016080, 0x00000000},
15291 + {0x00016084, 0x0e48048c},
15292 + {0x00016088, 0x54214514},
15293 + {0x0001608c, 0x119f481e},
15294 + {0x00016090, 0x24926490},
15295 + {0x00016098, 0xd2888888},
15296 + {0x000160a0, 0x0a108ffe},
15297 + {0x000160a4, 0x812fc370},
15298 + {0x000160a8, 0x423c8000},
15299 + {0x000160b4, 0x92480080},
15300 + {0x000160c0, 0x00adb6d0},
15301 + {0x000160c4, 0x6db6db60},
15302 + {0x000160c8, 0x6db6db6c},
15303 + {0x000160cc, 0x01e6c000},
15304 + {0x00016100, 0x3fffbe01},
15305 + {0x00016104, 0xfff80000},
15306 + {0x00016108, 0x00080010},
15307 + {0x00016140, 0x10804008},
15308 + {0x00016144, 0x02084080},
15309 + {0x00016148, 0x00000000},
15310 + {0x00016280, 0x058a0001},
15311 + {0x00016284, 0x3d840208},
15312 + {0x00016288, 0x01a20408},
15313 + {0x0001628c, 0x00038c07},
15314 + {0x00016290, 0x40000004},
15315 + {0x00016294, 0x458aa14f},
15316 + {0x00016380, 0x00000000},
15317 + {0x00016384, 0x00000000},
15318 + {0x00016388, 0x00800700},
15319 + {0x0001638c, 0x00800700},
15320 + {0x00016390, 0x00800700},
15321 + {0x00016394, 0x00000000},
15322 + {0x00016398, 0x00000000},
15323 + {0x0001639c, 0x00000000},
15324 + {0x000163a0, 0x00000001},
15325 + {0x000163a4, 0x00000001},
15326 + {0x000163a8, 0x00000000},
15327 + {0x000163ac, 0x00000000},
15328 + {0x000163b0, 0x00000000},
15329 + {0x000163b4, 0x00000000},
15330 + {0x000163b8, 0x00000000},
15331 + {0x000163bc, 0x00000000},
15332 + {0x000163c0, 0x000000a0},
15333 + {0x000163c4, 0x000c0000},
15334 + {0x000163c8, 0x14021402},
15335 + {0x000163cc, 0x00001402},
15336 + {0x000163d0, 0x00000000},
15337 + {0x000163d4, 0x00000000},
15338 + {0x00016400, 0x36db6db6},
15339 + {0x00016404, 0x6db6db40},
15340 + {0x00016408, 0x73f00000},
15341 + {0x0001640c, 0x00000000},
15342 + {0x00016440, 0x7f80fff8},
15343 + {0x0001644c, 0x76d005b5},
15344 + {0x00016450, 0x556cf031},
15345 + {0x00016454, 0x43449440},
15346 + {0x00016458, 0x0c51c92c},
15347 + {0x0001645c, 0x3db7fffc},
15348 + {0x00016460, 0xfffffffc},
15349 + {0x00016464, 0x000f0278},
15350 + {0x0001646c, 0x6db60000},
15351 + {0x00016500, 0x3fffbe01},
15352 + {0x00016504, 0xfff80000},
15353 + {0x00016508, 0x00080010},
15354 + {0x00016540, 0x10804008},
15355 + {0x00016544, 0x02084080},
15356 + {0x00016548, 0x00000000},
15357 + {0x00016780, 0x00000000},
15358 + {0x00016784, 0x00000000},
15359 + {0x00016788, 0x00800700},
15360 + {0x0001678c, 0x00800700},
15361 + {0x00016790, 0x00800700},
15362 + {0x00016794, 0x00000000},
15363 + {0x00016798, 0x00000000},
15364 + {0x0001679c, 0x00000000},
15365 + {0x000167a0, 0x00000001},
15366 + {0x000167a4, 0x00000001},
15367 + {0x000167a8, 0x00000000},
15368 + {0x000167ac, 0x00000000},
15369 + {0x000167b0, 0x00000000},
15370 + {0x000167b4, 0x00000000},
15371 + {0x000167b8, 0x00000000},
15372 + {0x000167bc, 0x00000000},
15373 + {0x000167c0, 0x000000a0},
15374 + {0x000167c4, 0x000c0000},
15375 + {0x000167c8, 0x14021402},
15376 + {0x000167cc, 0x00001402},
15377 + {0x000167d0, 0x00000000},
15378 + {0x000167d4, 0x00000000},
15379 + {0x00016800, 0x36db6db6},
15380 + {0x00016804, 0x6db6db40},
15381 + {0x00016808, 0x73f00000},
15382 + {0x0001680c, 0x00000000},
15383 + {0x00016840, 0x7f80fff8},
15384 + {0x0001684c, 0x76d005b5},
15385 + {0x00016850, 0x556cf031},
15386 + {0x00016854, 0x43449440},
15387 + {0x00016858, 0x0c51c92c},
15388 + {0x0001685c, 0x3db7fffc},
15389 + {0x00016860, 0xfffffffc},
15390 + {0x00016864, 0x000f0278},
15391 + {0x0001686c, 0x6db60000},
15392 + {0x00016900, 0x3fffbe01},
15393 + {0x00016904, 0xfff80000},
15394 + {0x00016908, 0x00080010},
15395 + {0x00016940, 0x10804008},
15396 + {0x00016944, 0x02084080},
15397 + {0x00016948, 0x00000000},
15398 + {0x00016b80, 0x00000000},
15399 + {0x00016b84, 0x00000000},
15400 + {0x00016b88, 0x00800700},
15401 + {0x00016b8c, 0x00800700},
15402 + {0x00016b90, 0x00800700},
15403 + {0x00016b94, 0x00000000},
15404 + {0x00016b98, 0x00000000},
15405 + {0x00016b9c, 0x00000000},
15406 + {0x00016ba0, 0x00000001},
15407 + {0x00016ba4, 0x00000001},
15408 + {0x00016ba8, 0x00000000},
15409 + {0x00016bac, 0x00000000},
15410 + {0x00016bb0, 0x00000000},
15411 + {0x00016bb4, 0x00000000},
15412 + {0x00016bb8, 0x00000000},
15413 + {0x00016bbc, 0x00000000},
15414 + {0x00016bc0, 0x000000a0},
15415 + {0x00016bc4, 0x000c0000},
15416 + {0x00016bc8, 0x14021402},
15417 + {0x00016bcc, 0x00001402},
15418 + {0x00016bd0, 0x00000000},
15419 + {0x00016bd4, 0x00000000},
15420 +};
15421 +
15422 +static const u32 ar9300Common_rx_gain_table_merlin_2p0[][2] = {
15423 + /* Addr allmodes */
15424 + {0x0000a000, 0x02000101},
15425 + {0x0000a004, 0x02000102},
15426 + {0x0000a008, 0x02000103},
15427 + {0x0000a00c, 0x02000104},
15428 + {0x0000a010, 0x02000200},
15429 + {0x0000a014, 0x02000201},
15430 + {0x0000a018, 0x02000202},
15431 + {0x0000a01c, 0x02000203},
15432 + {0x0000a020, 0x02000204},
15433 + {0x0000a024, 0x02000205},
15434 + {0x0000a028, 0x02000208},
15435 + {0x0000a02c, 0x02000302},
15436 + {0x0000a030, 0x02000303},
15437 + {0x0000a034, 0x02000304},
15438 + {0x0000a038, 0x02000400},
15439 + {0x0000a03c, 0x02010300},
15440 + {0x0000a040, 0x02010301},
15441 + {0x0000a044, 0x02010302},
15442 + {0x0000a048, 0x02000500},
15443 + {0x0000a04c, 0x02010400},
15444 + {0x0000a050, 0x02020300},
15445 + {0x0000a054, 0x02020301},
15446 + {0x0000a058, 0x02020302},
15447 + {0x0000a05c, 0x02020303},
15448 + {0x0000a060, 0x02020400},
15449 + {0x0000a064, 0x02030300},
15450 + {0x0000a068, 0x02030301},
15451 + {0x0000a06c, 0x02030302},
15452 + {0x0000a070, 0x02030303},
15453 + {0x0000a074, 0x02030400},
15454 + {0x0000a078, 0x02040300},
15455 + {0x0000a07c, 0x02040301},
15456 + {0x0000a080, 0x02040302},
15457 + {0x0000a084, 0x02040303},
15458 + {0x0000a088, 0x02030500},
15459 + {0x0000a08c, 0x02040400},
15460 + {0x0000a090, 0x02050203},
15461 + {0x0000a094, 0x02050204},
15462 + {0x0000a098, 0x02050205},
15463 + {0x0000a09c, 0x02040500},
15464 + {0x0000a0a0, 0x02050301},
15465 + {0x0000a0a4, 0x02050302},
15466 + {0x0000a0a8, 0x02050303},
15467 + {0x0000a0ac, 0x02050400},
15468 + {0x0000a0b0, 0x02050401},
15469 + {0x0000a0b4, 0x02050402},
15470 + {0x0000a0b8, 0x02050403},
15471 + {0x0000a0bc, 0x02050500},
15472 + {0x0000a0c0, 0x02050501},
15473 + {0x0000a0c4, 0x02050502},
15474 + {0x0000a0c8, 0x02050503},
15475 + {0x0000a0cc, 0x02050504},
15476 + {0x0000a0d0, 0x02050600},
15477 + {0x0000a0d4, 0x02050601},
15478 + {0x0000a0d8, 0x02050602},
15479 + {0x0000a0dc, 0x02050603},
15480 + {0x0000a0e0, 0x02050604},
15481 + {0x0000a0e4, 0x02050700},
15482 + {0x0000a0e8, 0x02050701},
15483 + {0x0000a0ec, 0x02050702},
15484 + {0x0000a0f0, 0x02050703},
15485 + {0x0000a0f4, 0x02050704},
15486 + {0x0000a0f8, 0x02050705},
15487 + {0x0000a0fc, 0x02050708},
15488 + {0x0000a100, 0x02050709},
15489 + {0x0000a104, 0x0205070a},
15490 + {0x0000a108, 0x0205070b},
15491 + {0x0000a10c, 0x0205070c},
15492 + {0x0000a110, 0x0205070d},
15493 + {0x0000a114, 0x02050710},
15494 + {0x0000a118, 0x02050711},
15495 + {0x0000a11c, 0x02050712},
15496 + {0x0000a120, 0x02050713},
15497 + {0x0000a124, 0x02050714},
15498 + {0x0000a128, 0x02050715},
15499 + {0x0000a12c, 0x02050730},
15500 + {0x0000a130, 0x02050731},
15501 + {0x0000a134, 0x02050732},
15502 + {0x0000a138, 0x02050733},
15503 + {0x0000a13c, 0x02050734},
15504 + {0x0000a140, 0x02050735},
15505 + {0x0000a144, 0x02050750},
15506 + {0x0000a148, 0x02050751},
15507 + {0x0000a14c, 0x02050752},
15508 + {0x0000a150, 0x02050753},
15509 + {0x0000a154, 0x02050754},
15510 + {0x0000a158, 0x02050755},
15511 + {0x0000a15c, 0x02050770},
15512 + {0x0000a160, 0x02050771},
15513 + {0x0000a164, 0x02050772},
15514 + {0x0000a168, 0x02050773},
15515 + {0x0000a16c, 0x02050774},
15516 + {0x0000a170, 0x02050775},
15517 + {0x0000a174, 0x00000776},
15518 + {0x0000a178, 0x00000776},
15519 + {0x0000a17c, 0x00000776},
15520 + {0x0000a180, 0x00000776},
15521 + {0x0000a184, 0x00000776},
15522 + {0x0000a188, 0x00000776},
15523 + {0x0000a18c, 0x00000776},
15524 + {0x0000a190, 0x00000776},
15525 + {0x0000a194, 0x00000776},
15526 + {0x0000a198, 0x00000776},
15527 + {0x0000a19c, 0x00000776},
15528 + {0x0000a1a0, 0x00000776},
15529 + {0x0000a1a4, 0x00000776},
15530 + {0x0000a1a8, 0x00000776},
15531 + {0x0000a1ac, 0x00000776},
15532 + {0x0000a1b0, 0x00000776},
15533 + {0x0000a1b4, 0x00000776},
15534 + {0x0000a1b8, 0x00000776},
15535 + {0x0000a1bc, 0x00000776},
15536 + {0x0000a1c0, 0x00000776},
15537 + {0x0000a1c4, 0x00000776},
15538 + {0x0000a1c8, 0x00000776},
15539 + {0x0000a1cc, 0x00000776},
15540 + {0x0000a1d0, 0x00000776},
15541 + {0x0000a1d4, 0x00000776},
15542 + {0x0000a1d8, 0x00000776},
15543 + {0x0000a1dc, 0x00000776},
15544 + {0x0000a1e0, 0x00000776},
15545 + {0x0000a1e4, 0x00000776},
15546 + {0x0000a1e8, 0x00000776},
15547 + {0x0000a1ec, 0x00000776},
15548 + {0x0000a1f0, 0x00000776},
15549 + {0x0000a1f4, 0x00000776},
15550 + {0x0000a1f8, 0x00000776},
15551 + {0x0000a1fc, 0x00000776},
15552 + {0x0000b000, 0x02000101},
15553 + {0x0000b004, 0x02000102},
15554 + {0x0000b008, 0x02000103},
15555 + {0x0000b00c, 0x02000104},
15556 + {0x0000b010, 0x02000200},
15557 + {0x0000b014, 0x02000201},
15558 + {0x0000b018, 0x02000202},
15559 + {0x0000b01c, 0x02000203},
15560 + {0x0000b020, 0x02000204},
15561 + {0x0000b024, 0x02000205},
15562 + {0x0000b028, 0x02000208},
15563 + {0x0000b02c, 0x02000302},
15564 + {0x0000b030, 0x02000303},
15565 + {0x0000b034, 0x02000304},
15566 + {0x0000b038, 0x02000400},
15567 + {0x0000b03c, 0x02010300},
15568 + {0x0000b040, 0x02010301},
15569 + {0x0000b044, 0x02010302},
15570 + {0x0000b048, 0x02000500},
15571 + {0x0000b04c, 0x02010400},
15572 + {0x0000b050, 0x02020300},
15573 + {0x0000b054, 0x02020301},
15574 + {0x0000b058, 0x02020302},
15575 + {0x0000b05c, 0x02020303},
15576 + {0x0000b060, 0x02020400},
15577 + {0x0000b064, 0x02030300},
15578 + {0x0000b068, 0x02030301},
15579 + {0x0000b06c, 0x02030302},
15580 + {0x0000b070, 0x02030303},
15581 + {0x0000b074, 0x02030400},
15582 + {0x0000b078, 0x02040300},
15583 + {0x0000b07c, 0x02040301},
15584 + {0x0000b080, 0x02040302},
15585 + {0x0000b084, 0x02040303},
15586 + {0x0000b088, 0x02030500},
15587 + {0x0000b08c, 0x02040400},
15588 + {0x0000b090, 0x02050203},
15589 + {0x0000b094, 0x02050204},
15590 + {0x0000b098, 0x02050205},
15591 + {0x0000b09c, 0x02040500},
15592 + {0x0000b0a0, 0x02050301},
15593 + {0x0000b0a4, 0x02050302},
15594 + {0x0000b0a8, 0x02050303},
15595 + {0x0000b0ac, 0x02050400},
15596 + {0x0000b0b0, 0x02050401},
15597 + {0x0000b0b4, 0x02050402},
15598 + {0x0000b0b8, 0x02050403},
15599 + {0x0000b0bc, 0x02050500},
15600 + {0x0000b0c0, 0x02050501},
15601 + {0x0000b0c4, 0x02050502},
15602 + {0x0000b0c8, 0x02050503},
15603 + {0x0000b0cc, 0x02050504},
15604 + {0x0000b0d0, 0x02050600},
15605 + {0x0000b0d4, 0x02050601},
15606 + {0x0000b0d8, 0x02050602},
15607 + {0x0000b0dc, 0x02050603},
15608 + {0x0000b0e0, 0x02050604},
15609 + {0x0000b0e4, 0x02050700},
15610 + {0x0000b0e8, 0x02050701},
15611 + {0x0000b0ec, 0x02050702},
15612 + {0x0000b0f0, 0x02050703},
15613 + {0x0000b0f4, 0x02050704},
15614 + {0x0000b0f8, 0x02050705},
15615 + {0x0000b0fc, 0x02050708},
15616 + {0x0000b100, 0x02050709},
15617 + {0x0000b104, 0x0205070a},
15618 + {0x0000b108, 0x0205070b},
15619 + {0x0000b10c, 0x0205070c},
15620 + {0x0000b110, 0x0205070d},
15621 + {0x0000b114, 0x02050710},
15622 + {0x0000b118, 0x02050711},
15623 + {0x0000b11c, 0x02050712},
15624 + {0x0000b120, 0x02050713},
15625 + {0x0000b124, 0x02050714},
15626 + {0x0000b128, 0x02050715},
15627 + {0x0000b12c, 0x02050730},
15628 + {0x0000b130, 0x02050731},
15629 + {0x0000b134, 0x02050732},
15630 + {0x0000b138, 0x02050733},
15631 + {0x0000b13c, 0x02050734},
15632 + {0x0000b140, 0x02050735},
15633 + {0x0000b144, 0x02050750},
15634 + {0x0000b148, 0x02050751},
15635 + {0x0000b14c, 0x02050752},
15636 + {0x0000b150, 0x02050753},
15637 + {0x0000b154, 0x02050754},
15638 + {0x0000b158, 0x02050755},
15639 + {0x0000b15c, 0x02050770},
15640 + {0x0000b160, 0x02050771},
15641 + {0x0000b164, 0x02050772},
15642 + {0x0000b168, 0x02050773},
15643 + {0x0000b16c, 0x02050774},
15644 + {0x0000b170, 0x02050775},
15645 + {0x0000b174, 0x00000776},
15646 + {0x0000b178, 0x00000776},
15647 + {0x0000b17c, 0x00000776},
15648 + {0x0000b180, 0x00000776},
15649 + {0x0000b184, 0x00000776},
15650 + {0x0000b188, 0x00000776},
15651 + {0x0000b18c, 0x00000776},
15652 + {0x0000b190, 0x00000776},
15653 + {0x0000b194, 0x00000776},
15654 + {0x0000b198, 0x00000776},
15655 + {0x0000b19c, 0x00000776},
15656 + {0x0000b1a0, 0x00000776},
15657 + {0x0000b1a4, 0x00000776},
15658 + {0x0000b1a8, 0x00000776},
15659 + {0x0000b1ac, 0x00000776},
15660 + {0x0000b1b0, 0x00000776},
15661 + {0x0000b1b4, 0x00000776},
15662 + {0x0000b1b8, 0x00000776},
15663 + {0x0000b1bc, 0x00000776},
15664 + {0x0000b1c0, 0x00000776},
15665 + {0x0000b1c4, 0x00000776},
15666 + {0x0000b1c8, 0x00000776},
15667 + {0x0000b1cc, 0x00000776},
15668 + {0x0000b1d0, 0x00000776},
15669 + {0x0000b1d4, 0x00000776},
15670 + {0x0000b1d8, 0x00000776},
15671 + {0x0000b1dc, 0x00000776},
15672 + {0x0000b1e0, 0x00000776},
15673 + {0x0000b1e4, 0x00000776},
15674 + {0x0000b1e8, 0x00000776},
15675 + {0x0000b1ec, 0x00000776},
15676 + {0x0000b1f0, 0x00000776},
15677 + {0x0000b1f4, 0x00000776},
15678 + {0x0000b1f8, 0x00000776},
15679 + {0x0000b1fc, 0x00000776},
15680 +};
15681 +
15682 +static const u32 ar9300_2p0_mac_postamble[][5] = {
15683 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
15684 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
15685 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
15686 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
15687 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
15688 + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
15689 + {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
15690 + {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
15691 + {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
15692 +};
15693 +
15694 +static const u32 ar9300_2p0_soc_postamble[][5] = {
15695 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
15696 + {0x00007010, 0x00000023, 0x00000023, 0x00000022, 0x00000022},
15697 +};
15698 +
15699 +static const u32 ar9200_merlin_2p0_radio_core[][2] = {
15700 + /* Addr common */
15701 + {0x00007800, 0x00040000},
15702 + {0x00007804, 0xdb005012},
15703 + {0x00007808, 0x04924914},
15704 + {0x0000780c, 0x21084210},
15705 + {0x00007810, 0x6d801300},
15706 + {0x00007814, 0x0019beff},
15707 + {0x00007818, 0x07e41000},
15708 + {0x0000781c, 0x00392000},
15709 + {0x00007820, 0x92592480},
15710 + {0x00007824, 0x00040000},
15711 + {0x00007828, 0xdb005012},
15712 + {0x0000782c, 0x04924914},
15713 + {0x00007830, 0x21084210},
15714 + {0x00007834, 0x6d801300},
15715 + {0x00007838, 0x0019beff},
15716 + {0x0000783c, 0x07e40000},
15717 + {0x00007840, 0x00392000},
15718 + {0x00007844, 0x92592480},
15719 + {0x00007848, 0x00100000},
15720 + {0x0000784c, 0x773f0567},
15721 + {0x00007850, 0x54214514},
15722 + {0x00007854, 0x12035828},
15723 + {0x00007858, 0x92592692},
15724 + {0x0000785c, 0x00000000},
15725 + {0x00007860, 0x56400000},
15726 + {0x00007864, 0x0a8e370e},
15727 + {0x00007868, 0xc0102850},
15728 + {0x0000786c, 0x812d4000},
15729 + {0x00007870, 0x807ec400},
15730 + {0x00007874, 0x001b6db0},
15731 + {0x00007878, 0x00376b63},
15732 + {0x0000787c, 0x06db6db6},
15733 + {0x00007880, 0x006d8000},
15734 + {0x00007884, 0xffeffffe},
15735 + {0x00007888, 0xffeffffe},
15736 + {0x0000788c, 0x00010000},
15737 + {0x00007890, 0x02060aeb},
15738 + {0x00007894, 0x5a108000},
15739 +};
15740 +
15741 +static const u32 ar9300_2p0_baseband_postamble[][5] = {
15742 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
15743 + {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
15744 + {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
15745 + {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
15746 + {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
15747 + {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
15748 + {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
15749 + {0x00009c00, 0x00000044, 0x000000c4, 0x000000c4, 0x00000044},
15750 + {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
15751 + {0x00009e04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
15752 + {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
15753 + {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e},
15754 + {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
15755 + {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
15756 + {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
15757 + {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
15758 + {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
15759 + {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
15760 + {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
15761 + {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
15762 + {0x0000a204, 0x000037c0, 0x000037c4, 0x000037c4, 0x000037c0},
15763 + {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
15764 + {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
15765 + {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
15766 + {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
15767 + {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
15768 + {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
15769 + {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
15770 + {0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501},
15771 + {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
15772 + {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
15773 + {0x0000a284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
15774 + {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
15775 + {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
15776 + {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
15777 + {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
15778 + {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
15779 + {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
15780 + {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
15781 + {0x0000ae04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
15782 + {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
15783 + {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
15784 + {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
15785 + {0x0000b284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
15786 + {0x0000b830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
15787 + {0x0000be04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
15788 + {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
15789 + {0x0000be1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
15790 + {0x0000be20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
15791 + {0x0000c284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
15792 +};
15793 +
15794 +static const u32 ar9300_2p0_baseband_core[][2] = {
15795 + /* Addr allmodes */
15796 + {0x00009800, 0xafe68e30},
15797 + {0x00009804, 0xfd14e000},
15798 + {0x00009808, 0x9c0a9f6b},
15799 + {0x0000980c, 0x04900000},
15800 + {0x00009814, 0x9280c00a},
15801 + {0x00009818, 0x00000000},
15802 + {0x0000981c, 0x00020028},
15803 + {0x00009834, 0x5f3ca3de},
15804 + {0x00009838, 0x0108ecff},
15805 + {0x0000983c, 0x14750600},
15806 + {0x00009880, 0x201fff00},
15807 + {0x00009884, 0x00001042},
15808 + {0x000098a4, 0x00200400},
15809 + {0x000098b0, 0x52440bbe},
15810 + {0x000098d0, 0x004b6a8e},
15811 + {0x000098d4, 0x00000820},
15812 + {0x000098dc, 0x00000000},
15813 + {0x000098f0, 0x00000000},
15814 + {0x000098f4, 0x00000000},
15815 + {0x00009c04, 0xff55ff55},
15816 + {0x00009c08, 0x0320ff55},
15817 + {0x00009c0c, 0x00000000},
15818 + {0x00009c10, 0x00000000},
15819 + {0x00009c14, 0x00046384},
15820 + {0x00009c18, 0x05b6b440},
15821 + {0x00009c1c, 0x00b6b440},
15822 + {0x00009d00, 0xc080a333},
15823 + {0x00009d04, 0x40206c10},
15824 + {0x00009d08, 0x009c4060},
15825 + {0x00009d0c, 0x9883800a},
15826 + {0x00009d10, 0x01834061},
15827 + {0x00009d14, 0x00c0040b},
15828 + {0x00009d18, 0x00000000},
15829 + {0x00009e08, 0x0038233c},
15830 + {0x00009e24, 0x990bb515},
15831 + {0x00009e28, 0x0c6f0000},
15832 + {0x00009e30, 0x06336f77},
15833 + {0x00009e34, 0x6af6532f},
15834 + {0x00009e38, 0x0cc80c00},
15835 + {0x00009e3c, 0xcf946222},
15836 + {0x00009e40, 0x0d261820},
15837 + {0x00009e4c, 0x00001004},
15838 + {0x00009e50, 0x00ff03f1},
15839 + {0x00009e54, 0x00000000},
15840 + {0x00009fc0, 0x803e4788},
15841 + {0x00009fc4, 0x0001efb5},
15842 + {0x00009fcc, 0x40000014},
15843 + {0x00009fd0, 0x01193b93},
15844 + {0x0000a20c, 0x00000000},
15845 + {0x0000a220, 0x00000000},
15846 + {0x0000a224, 0x00000000},
15847 + {0x0000a228, 0x10002310},
15848 + {0x0000a22c, 0x01036a1e},
15849 + {0x0000a234, 0x10000fff},
15850 + {0x0000a23c, 0x00000000},
15851 + {0x0000a244, 0x0c000000},
15852 + {0x0000a2a0, 0x00000001},
15853 + {0x0000a2c0, 0x00000001},
15854 + {0x0000a2c8, 0x00000000},
15855 + {0x0000a2cc, 0x18c43433},
15856 + {0x0000a2d4, 0x00000000},
15857 + {0x0000a2dc, 0x00000000},
15858 + {0x0000a2e0, 0x00000000},
15859 + {0x0000a2e4, 0x00000000},
15860 + {0x0000a2e8, 0x00000000},
15861 + {0x0000a2ec, 0x00000000},
15862 + {0x0000a2f0, 0x00000000},
15863 + {0x0000a2f4, 0x00000000},
15864 + {0x0000a2f8, 0x00000000},
15865 + {0x0000a344, 0x00000000},
15866 + {0x0000a34c, 0x00000000},
15867 + {0x0000a350, 0x0000a000},
15868 + {0x0000a364, 0x00000000},
15869 + {0x0000a370, 0x00000000},
15870 + {0x0000a390, 0x00000001},
15871 + {0x0000a394, 0x00000444},
15872 + {0x0000a398, 0x001f0e0f},
15873 + {0x0000a39c, 0x0075393f},
15874 + {0x0000a3a0, 0xb79f6427},
15875 + {0x0000a3a4, 0x00000000},
15876 + {0x0000a3a8, 0xaaaaaaaa},
15877 + {0x0000a3ac, 0x3c466478},
15878 + {0x0000a3c0, 0x20202020},
15879 + {0x0000a3c4, 0x22222220},
15880 + {0x0000a3c8, 0x20200020},
15881 + {0x0000a3cc, 0x20202020},
15882 + {0x0000a3d0, 0x20202020},
15883 + {0x0000a3d4, 0x20202020},
15884 + {0x0000a3d8, 0x20202020},
15885 + {0x0000a3dc, 0x20202020},
15886 + {0x0000a3e0, 0x20202020},
15887 + {0x0000a3e4, 0x20202020},
15888 + {0x0000a3e8, 0x20202020},
15889 + {0x0000a3ec, 0x20202020},
15890 + {0x0000a3f0, 0x00000000},
15891 + {0x0000a3f4, 0x00000246},
15892 + {0x0000a3f8, 0x0cdbd380},
15893 + {0x0000a3fc, 0x000f0f01},
15894 + {0x0000a400, 0x8fa91f01},
15895 + {0x0000a404, 0x00000000},
15896 + {0x0000a408, 0x0e79e5c6},
15897 + {0x0000a40c, 0x00820820},
15898 + {0x0000a414, 0x1ce739ce},
15899 + {0x0000a418, 0x7d001dce},
15900 + {0x0000a41c, 0x1ce739ce},
15901 + {0x0000a420, 0x000001ce},
15902 + {0x0000a424, 0x1ce739ce},
15903 + {0x0000a428, 0x000001ce},
15904 + {0x0000a42c, 0x1ce739ce},
15905 + {0x0000a430, 0x1ce739ce},
15906 + {0x0000a434, 0x00000000},
15907 + {0x0000a438, 0x00001801},
15908 + {0x0000a43c, 0x00000000},
15909 + {0x0000a440, 0x00000000},
15910 + {0x0000a444, 0x00000000},
15911 + {0x0000a448, 0x07000080},
15912 + {0x0000a44c, 0x00000001},
15913 + {0x0000a450, 0x00010000},
15914 + {0x0000a458, 0x00000000},
15915 + {0x0000a600, 0x00000000},
15916 + {0x0000a604, 0x00000000},
15917 + {0x0000a608, 0x00000000},
15918 + {0x0000a60c, 0x00000000},
15919 + {0x0000a610, 0x00000000},
15920 + {0x0000a614, 0x00000000},
15921 + {0x0000a618, 0x00000000},
15922 + {0x0000a61c, 0x00000000},
15923 + {0x0000a620, 0x00000000},
15924 + {0x0000a624, 0x00000000},
15925 + {0x0000a628, 0x00000000},
15926 + {0x0000a62c, 0x00000000},
15927 + {0x0000a630, 0x00000000},
15928 + {0x0000a634, 0x00000000},
15929 + {0x0000a638, 0x00000000},
15930 + {0x0000a63c, 0x00000000},
15931 + {0x0000a640, 0x00000000},
15932 + {0x0000a644, 0x3ffd9d74},
15933 + {0x0000a648, 0x0048060a},
15934 + {0x0000a64c, 0x00000637},
15935 + {0x0000a670, 0x03020100},
15936 + {0x0000a674, 0x09080504},
15937 + {0x0000a678, 0x0d0c0b0a},
15938 + {0x0000a67c, 0x13121110},
15939 + {0x0000a680, 0x31301514},
15940 + {0x0000a684, 0x35343332},
15941 + {0x0000a688, 0x00000036},
15942 + {0x0000a690, 0x00000838},
15943 + {0x0000a7c0, 0x00000000},
15944 + {0x0000a7c4, 0xfffffffc},
15945 + {0x0000a7c8, 0x00000000},
15946 + {0x0000a7cc, 0x00000000},
15947 + {0x0000a7d0, 0x00000000},
15948 + {0x0000a7d4, 0x00000004},
15949 + {0x0000a7dc, 0x00000001},
15950 + {0x0000a8d0, 0x004b6a8e},
15951 + {0x0000a8d4, 0x00000820},
15952 + {0x0000a8dc, 0x00000000},
15953 + {0x0000a8f0, 0x00000000},
15954 + {0x0000a8f4, 0x00000000},
15955 + {0x0000b2d0, 0x00000080},
15956 + {0x0000b2d4, 0x00000000},
15957 + {0x0000b2dc, 0x00000000},
15958 + {0x0000b2e0, 0x00000000},
15959 + {0x0000b2e4, 0x00000000},
15960 + {0x0000b2e8, 0x00000000},
15961 + {0x0000b2ec, 0x00000000},
15962 + {0x0000b2f0, 0x00000000},
15963 + {0x0000b2f4, 0x00000000},
15964 + {0x0000b2f8, 0x00000000},
15965 + {0x0000b408, 0x0e79e5c0},
15966 + {0x0000b40c, 0x00820820},
15967 + {0x0000b420, 0x00000000},
15968 + {0x0000b8d0, 0x004b6a8e},
15969 + {0x0000b8d4, 0x00000820},
15970 + {0x0000b8dc, 0x00000000},
15971 + {0x0000b8f0, 0x00000000},
15972 + {0x0000b8f4, 0x00000000},
15973 + {0x0000c2d0, 0x00000080},
15974 + {0x0000c2d4, 0x00000000},
15975 + {0x0000c2dc, 0x00000000},
15976 + {0x0000c2e0, 0x00000000},
15977 + {0x0000c2e4, 0x00000000},
15978 + {0x0000c2e8, 0x00000000},
15979 + {0x0000c2ec, 0x00000000},
15980 + {0x0000c2f0, 0x00000000},
15981 + {0x0000c2f4, 0x00000000},
15982 + {0x0000c2f8, 0x00000000},
15983 + {0x0000c408, 0x0e79e5c0},
15984 + {0x0000c40c, 0x00820820},
15985 + {0x0000c420, 0x00000000},
15986 +};
15987 +
15988 +static const u32 ar9300Modes_high_power_tx_gain_table_2p0[][5] = {
15989 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
15990 + {0x0000a410, 0x000050d9, 0x000050d9, 0x000050da, 0x000050da},
15991 + {0x0000a500, 0x00020220, 0x00020220, 0x00000000, 0x00000000},
15992 + {0x0000a504, 0x06020223, 0x06020223, 0x04000002, 0x04000002},
15993 + {0x0000a508, 0x0b022220, 0x0b022220, 0x08000004, 0x08000004},
15994 + {0x0000a50c, 0x10022223, 0x10022223, 0x0b000200, 0x0b000200},
15995 + {0x0000a510, 0x17022620, 0x17022620, 0x0f000202, 0x0f000202},
15996 + {0x0000a514, 0x1b022622, 0x1b022622, 0x11000400, 0x11000400},
15997 + {0x0000a518, 0x1f022822, 0x1f022822, 0x15000402, 0x15000402},
15998 + {0x0000a51c, 0x24022842, 0x24022842, 0x19000404, 0x19000404},
15999 + {0x0000a520, 0x28042840, 0x28042840, 0x1b000603, 0x1b000603},
16000 + {0x0000a524, 0x2c042842, 0x2c042842, 0x1f000a02, 0x1f000a02},
16001 + {0x0000a528, 0x30042844, 0x30042844, 0x23000a04, 0x23000a04},
16002 + {0x0000a52c, 0x34042846, 0x34042846, 0x26000a20, 0x26000a20},
16003 + {0x0000a530, 0x39042869, 0x39042869, 0x2a000e20, 0x2a000e20},
16004 + {0x0000a534, 0x3d062869, 0x3d062869, 0x2e000e22, 0x2e000e22},
16005 + {0x0000a538, 0x44062c69, 0x44062c69, 0x31000e24, 0x31000e24},
16006 + {0x0000a53c, 0x48063069, 0x48063069, 0x34001640, 0x34001640},
16007 + {0x0000a540, 0x4c0a3065, 0x4c0a3065, 0x38001660, 0x38001660},
16008 + {0x0000a544, 0x500a3069, 0x500a3069, 0x3b001861, 0x3b001861},
16009 + {0x0000a548, 0x530a3469, 0x530a3469, 0x3e001a81, 0x3e001a81},
16010 + {0x0000a54c, 0x590a7464, 0x590a7464, 0x42001a83, 0x42001a83},
16011 + {0x0000a550, 0x5e0a7865, 0x5e0a7865, 0x44001c84, 0x44001c84},
16012 + {0x0000a554, 0x630a7e66, 0x630a7e66, 0x48001ce3, 0x48001ce3},
16013 + {0x0000a558, 0x680a7e89, 0x680a7e89, 0x4c001ce5, 0x4c001ce5},
16014 + {0x0000a55c, 0x6e0a7e8c, 0x6e0a7e8c, 0x50001ce9, 0x50001ce9},
16015 + {0x0000a560, 0x730e7e8c, 0x730e7e8c, 0x54001ceb, 0x54001ceb},
16016 + {0x0000a564, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16017 + {0x0000a568, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16018 + {0x0000a56c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16019 + {0x0000a570, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16020 + {0x0000a574, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16021 + {0x0000a578, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16022 + {0x0000a57c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16023 + {0x0000a580, 0x00820220, 0x00820220, 0x00800000, 0x00800000},
16024 + {0x0000a584, 0x06820223, 0x06820223, 0x04800002, 0x04800002},
16025 + {0x0000a588, 0x0b822220, 0x0b822220, 0x08800004, 0x08800004},
16026 + {0x0000a58c, 0x10822223, 0x10822223, 0x0b800200, 0x0b800200},
16027 + {0x0000a590, 0x17822620, 0x17822620, 0x0f800202, 0x0f800202},
16028 + {0x0000a594, 0x1b822622, 0x1b822622, 0x11800400, 0x11800400},
16029 + {0x0000a598, 0x1f822822, 0x1f822822, 0x15800402, 0x15800402},
16030 + {0x0000a59c, 0x24822842, 0x24822842, 0x19800404, 0x19800404},
16031 + {0x0000a5a0, 0x28842840, 0x28842840, 0x1b800603, 0x1b800603},
16032 + {0x0000a5a4, 0x2c842842, 0x2c842842, 0x1f800a02, 0x1f800a02},
16033 + {0x0000a5a8, 0x30842844, 0x30842844, 0x23800a04, 0x23800a04},
16034 + {0x0000a5ac, 0x34842846, 0x34842846, 0x26800a20, 0x26800a20},
16035 + {0x0000a5b0, 0x39842869, 0x39842869, 0x2a800e20, 0x2a800e20},
16036 + {0x0000a5b4, 0x3d862869, 0x3d862869, 0x2e800e22, 0x2e800e22},
16037 + {0x0000a5b8, 0x44862c69, 0x44862c69, 0x31800e24, 0x31800e24},
16038 + {0x0000a5bc, 0x48863069, 0x48863069, 0x34801640, 0x34801640},
16039 + {0x0000a5c0, 0x4c8a3065, 0x4c8a3065, 0x38801660, 0x38801660},
16040 + {0x0000a5c4, 0x508a3069, 0x508a3069, 0x3b801861, 0x3b801861},
16041 + {0x0000a5c8, 0x538a3469, 0x538a3469, 0x3e801a81, 0x3e801a81},
16042 + {0x0000a5cc, 0x598a7464, 0x598a7464, 0x42801a83, 0x42801a83},
16043 + {0x0000a5d0, 0x5e8a7865, 0x5e8a7865, 0x44801c84, 0x44801c84},
16044 + {0x0000a5d4, 0x638a7e66, 0x638a7e66, 0x48801ce3, 0x48801ce3},
16045 + {0x0000a5d8, 0x688a7e89, 0x688a7e89, 0x4c801ce5, 0x4c801ce5},
16046 + {0x0000a5dc, 0x6e8a7e8c, 0x6e8a7e8c, 0x50801ce9, 0x50801ce9},
16047 + {0x0000a5e0, 0x738e7e8c, 0x738e7e8c, 0x54801ceb, 0x54801ceb},
16048 + {0x0000a5e4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16049 + {0x0000a5e8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16050 + {0x0000a5ec, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16051 + {0x0000a5f0, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16052 + {0x0000a5f4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16053 + {0x0000a5f8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16054 + {0x0000a5fc, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16055 + {0x00016044, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
16056 + {0x00016048, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
16057 + {0x00016068, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
16058 + {0x00016444, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
16059 + {0x00016448, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
16060 + {0x00016468, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
16061 + {0x00016844, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
16062 + {0x00016848, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
16063 + {0x00016868, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
16064 +};
16065 +
16066 +static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p0[][5] = {
16067 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
16068 + {0x0000a410, 0x000050d9, 0x000050d9, 0x000050da, 0x000050da},
16069 + {0x0000a500, 0x00020220, 0x00020220, 0x00000000, 0x00000000},
16070 + {0x0000a504, 0x06020223, 0x06020223, 0x04000002, 0x04000002},
16071 + {0x0000a508, 0x0b022220, 0x0b022220, 0x08000004, 0x08000004},
16072 + {0x0000a50c, 0x10022223, 0x10022223, 0x0b000200, 0x0b000200},
16073 + {0x0000a510, 0x17022620, 0x17022620, 0x0f000202, 0x0f000202},
16074 + {0x0000a514, 0x1b022622, 0x1b022622, 0x11000400, 0x11000400},
16075 + {0x0000a518, 0x1f022822, 0x1f022822, 0x15000402, 0x15000402},
16076 + {0x0000a51c, 0x24022842, 0x24022842, 0x19000404, 0x19000404},
16077 + {0x0000a520, 0x28042840, 0x28042840, 0x1b000603, 0x1b000603},
16078 + {0x0000a524, 0x2c042842, 0x2c042842, 0x1f000a02, 0x1f000a02},
16079 + {0x0000a528, 0x30042844, 0x30042844, 0x23000a04, 0x23000a04},
16080 + {0x0000a52c, 0x34042846, 0x34042846, 0x26000a20, 0x26000a20},
16081 + {0x0000a530, 0x39042869, 0x39042869, 0x2a000e20, 0x2a000e20},
16082 + {0x0000a534, 0x3d062869, 0x3d062869, 0x2e000e22, 0x2e000e22},
16083 + {0x0000a538, 0x44062c69, 0x44062c69, 0x31000e24, 0x31000e24},
16084 + {0x0000a53c, 0x48063069, 0x48063069, 0x34001640, 0x34001640},
16085 + {0x0000a540, 0x4c0a3065, 0x4c0a3065, 0x38001660, 0x38001660},
16086 + {0x0000a544, 0x500a3069, 0x500a3069, 0x3b001861, 0x3b001861},
16087 + {0x0000a548, 0x530a3469, 0x530a3469, 0x3e001a81, 0x3e001a81},
16088 + {0x0000a54c, 0x590a7464, 0x590a7464, 0x42001a83, 0x42001a83},
16089 + {0x0000a550, 0x5e0a7865, 0x5e0a7865, 0x44001c84, 0x44001c84},
16090 + {0x0000a554, 0x630a7e66, 0x630a7e66, 0x48001ce3, 0x48001ce3},
16091 + {0x0000a558, 0x680a7e89, 0x680a7e89, 0x4c001ce5, 0x4c001ce5},
16092 + {0x0000a55c, 0x6e0a7e8c, 0x6e0a7e8c, 0x50001ce9, 0x50001ce9},
16093 + {0x0000a560, 0x730e7e8c, 0x730e7e8c, 0x54001ceb, 0x54001ceb},
16094 + {0x0000a564, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16095 + {0x0000a568, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16096 + {0x0000a56c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16097 + {0x0000a570, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16098 + {0x0000a574, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16099 + {0x0000a578, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16100 + {0x0000a57c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16101 + {0x0000a580, 0x00820220, 0x00820220, 0x00800000, 0x00800000},
16102 + {0x0000a584, 0x06820223, 0x06820223, 0x04800002, 0x04800002},
16103 + {0x0000a588, 0x0b822220, 0x0b822220, 0x08800004, 0x08800004},
16104 + {0x0000a58c, 0x10822223, 0x10822223, 0x0b800200, 0x0b800200},
16105 + {0x0000a590, 0x17822620, 0x17822620, 0x0f800202, 0x0f800202},
16106 + {0x0000a594, 0x1b822622, 0x1b822622, 0x11800400, 0x11800400},
16107 + {0x0000a598, 0x1f822822, 0x1f822822, 0x15800402, 0x15800402},
16108 + {0x0000a59c, 0x24822842, 0x24822842, 0x19800404, 0x19800404},
16109 + {0x0000a5a0, 0x28842840, 0x28842840, 0x1b800603, 0x1b800603},
16110 + {0x0000a5a4, 0x2c842842, 0x2c842842, 0x1f800a02, 0x1f800a02},
16111 + {0x0000a5a8, 0x30842844, 0x30842844, 0x23800a04, 0x23800a04},
16112 + {0x0000a5ac, 0x34842846, 0x34842846, 0x26800a20, 0x26800a20},
16113 + {0x0000a5b0, 0x39842869, 0x39842869, 0x2a800e20, 0x2a800e20},
16114 + {0x0000a5b4, 0x3d862869, 0x3d862869, 0x2e800e22, 0x2e800e22},
16115 + {0x0000a5b8, 0x44862c69, 0x44862c69, 0x31800e24, 0x31800e24},
16116 + {0x0000a5bc, 0x48863069, 0x48863069, 0x34801640, 0x34801640},
16117 + {0x0000a5c0, 0x4c8a3065, 0x4c8a3065, 0x38801660, 0x38801660},
16118 + {0x0000a5c4, 0x508a3069, 0x508a3069, 0x3b801861, 0x3b801861},
16119 + {0x0000a5c8, 0x538a3469, 0x538a3469, 0x3e801a81, 0x3e801a81},
16120 + {0x0000a5cc, 0x598a7464, 0x598a7464, 0x42801a83, 0x42801a83},
16121 + {0x0000a5d0, 0x5e8a7865, 0x5e8a7865, 0x44801c84, 0x44801c84},
16122 + {0x0000a5d4, 0x638a7e66, 0x638a7e66, 0x48801ce3, 0x48801ce3},
16123 + {0x0000a5d8, 0x688a7e89, 0x688a7e89, 0x4c801ce5, 0x4c801ce5},
16124 + {0x0000a5dc, 0x6e8a7e8c, 0x6e8a7e8c, 0x50801ce9, 0x50801ce9},
16125 + {0x0000a5e0, 0x738e7e8c, 0x738e7e8c, 0x54801ceb, 0x54801ceb},
16126 + {0x0000a5e4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16127 + {0x0000a5e8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16128 + {0x0000a5ec, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16129 + {0x0000a5f0, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16130 + {0x0000a5f4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16131 + {0x0000a5f8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16132 + {0x0000a5fc, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16133 + {0x00016044, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
16134 + {0x00016048, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
16135 + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
16136 + {0x00016444, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
16137 + {0x00016448, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
16138 + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
16139 + {0x00016844, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
16140 + {0x00016848, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
16141 + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
16142 +};
16143 +
16144 +static const u32 ar9300Common_rx_gain_table_2p0[][2] = {
16145 + /* Addr allmodes */
16146 + {0x0000a000, 0x00010000},
16147 + {0x0000a004, 0x00030002},
16148 + {0x0000a008, 0x00050004},
16149 + {0x0000a00c, 0x00810080},
16150 + {0x0000a010, 0x01800082},
16151 + {0x0000a014, 0x01820181},
16152 + {0x0000a018, 0x01840183},
16153 + {0x0000a01c, 0x01880185},
16154 + {0x0000a020, 0x018a0189},
16155 + {0x0000a024, 0x02850284},
16156 + {0x0000a028, 0x02890288},
16157 + {0x0000a02c, 0x028b028a},
16158 + {0x0000a030, 0x028d028c},
16159 + {0x0000a034, 0x02910290},
16160 + {0x0000a038, 0x02930292},
16161 + {0x0000a03c, 0x03910390},
16162 + {0x0000a040, 0x03930392},
16163 + {0x0000a044, 0x03950394},
16164 + {0x0000a048, 0x00000396},
16165 + {0x0000a04c, 0x00000000},
16166 + {0x0000a050, 0x00000000},
16167 + {0x0000a054, 0x00000000},
16168 + {0x0000a058, 0x00000000},
16169 + {0x0000a05c, 0x00000000},
16170 + {0x0000a060, 0x00000000},
16171 + {0x0000a064, 0x00000000},
16172 + {0x0000a068, 0x00000000},
16173 + {0x0000a06c, 0x00000000},
16174 + {0x0000a070, 0x00000000},
16175 + {0x0000a074, 0x00000000},
16176 + {0x0000a078, 0x00000000},
16177 + {0x0000a07c, 0x00000000},
16178 + {0x0000a080, 0x28282828},
16179 + {0x0000a084, 0x21212128},
16180 + {0x0000a088, 0x21212121},
16181 + {0x0000a08c, 0x1c1c1c21},
16182 + {0x0000a090, 0x1c1c1c1c},
16183 + {0x0000a094, 0x17171c1c},
16184 + {0x0000a098, 0x02020212},
16185 + {0x0000a09c, 0x02020202},
16186 + {0x0000a0a0, 0x00000000},
16187 + {0x0000a0a4, 0x00000000},
16188 + {0x0000a0a8, 0x00000000},
16189 + {0x0000a0ac, 0x00000000},
16190 + {0x0000a0b0, 0x00000000},
16191 + {0x0000a0b4, 0x00000000},
16192 + {0x0000a0b8, 0x00000000},
16193 + {0x0000a0bc, 0x00000000},
16194 + {0x0000a0c0, 0x001f0000},
16195 + {0x0000a0c4, 0x011f0100},
16196 + {0x0000a0c8, 0x011d011e},
16197 + {0x0000a0cc, 0x011b011c},
16198 + {0x0000a0d0, 0x02030204},
16199 + {0x0000a0d4, 0x02010202},
16200 + {0x0000a0d8, 0x021f0200},
16201 + {0x0000a0dc, 0x021d021e},
16202 + {0x0000a0e0, 0x03010302},
16203 + {0x0000a0e4, 0x031f0300},
16204 + {0x0000a0e8, 0x0402031e},
16205 + {0x0000a0ec, 0x04000401},
16206 + {0x0000a0f0, 0x041e041f},
16207 + {0x0000a0f4, 0x05010502},
16208 + {0x0000a0f8, 0x051f0500},
16209 + {0x0000a0fc, 0x0602051e},
16210 + {0x0000a100, 0x06000601},
16211 + {0x0000a104, 0x061e061f},
16212 + {0x0000a108, 0x0703061d},
16213 + {0x0000a10c, 0x07010702},
16214 + {0x0000a110, 0x00000700},
16215 + {0x0000a114, 0x00000000},
16216 + {0x0000a118, 0x00000000},
16217 + {0x0000a11c, 0x00000000},
16218 + {0x0000a120, 0x00000000},
16219 + {0x0000a124, 0x00000000},
16220 + {0x0000a128, 0x00000000},
16221 + {0x0000a12c, 0x00000000},
16222 + {0x0000a130, 0x00000000},
16223 + {0x0000a134, 0x00000000},
16224 + {0x0000a138, 0x00000000},
16225 + {0x0000a13c, 0x00000000},
16226 + {0x0000a140, 0x001f0000},
16227 + {0x0000a144, 0x011f0100},
16228 + {0x0000a148, 0x011d011e},
16229 + {0x0000a14c, 0x011b011c},
16230 + {0x0000a150, 0x02030204},
16231 + {0x0000a154, 0x02010202},
16232 + {0x0000a158, 0x021f0200},
16233 + {0x0000a15c, 0x021d021e},
16234 + {0x0000a160, 0x03010302},
16235 + {0x0000a164, 0x031f0300},
16236 + {0x0000a168, 0x0402031e},
16237 + {0x0000a16c, 0x04000401},
16238 + {0x0000a170, 0x041e041f},
16239 + {0x0000a174, 0x05010502},
16240 + {0x0000a178, 0x051f0500},
16241 + {0x0000a17c, 0x0602051e},
16242 + {0x0000a180, 0x06000601},
16243 + {0x0000a184, 0x061e061f},
16244 + {0x0000a188, 0x0703061d},
16245 + {0x0000a18c, 0x07010702},
16246 + {0x0000a190, 0x00000700},
16247 + {0x0000a194, 0x00000000},
16248 + {0x0000a198, 0x00000000},
16249 + {0x0000a19c, 0x00000000},
16250 + {0x0000a1a0, 0x00000000},
16251 + {0x0000a1a4, 0x00000000},
16252 + {0x0000a1a8, 0x00000000},
16253 + {0x0000a1ac, 0x00000000},
16254 + {0x0000a1b0, 0x00000000},
16255 + {0x0000a1b4, 0x00000000},
16256 + {0x0000a1b8, 0x00000000},
16257 + {0x0000a1bc, 0x00000000},
16258 + {0x0000a1c0, 0x00000000},
16259 + {0x0000a1c4, 0x00000000},
16260 + {0x0000a1c8, 0x00000000},
16261 + {0x0000a1cc, 0x00000000},
16262 + {0x0000a1d0, 0x00000000},
16263 + {0x0000a1d4, 0x00000000},
16264 + {0x0000a1d8, 0x00000000},
16265 + {0x0000a1dc, 0x00000000},
16266 + {0x0000a1e0, 0x00000000},
16267 + {0x0000a1e4, 0x00000000},
16268 + {0x0000a1e8, 0x00000000},
16269 + {0x0000a1ec, 0x00000000},
16270 + {0x0000a1f0, 0x00000396},
16271 + {0x0000a1f4, 0x00000396},
16272 + {0x0000a1f8, 0x00000396},
16273 + {0x0000a1fc, 0x00000196},
16274 + {0x0000b000, 0x00010000},
16275 + {0x0000b004, 0x00030002},
16276 + {0x0000b008, 0x00050004},
16277 + {0x0000b00c, 0x00810080},
16278 + {0x0000b010, 0x00830082},
16279 + {0x0000b014, 0x01810180},
16280 + {0x0000b018, 0x01830182},
16281 + {0x0000b01c, 0x01850184},
16282 + {0x0000b020, 0x02810280},
16283 + {0x0000b024, 0x02830282},
16284 + {0x0000b028, 0x02850284},
16285 + {0x0000b02c, 0x02890288},
16286 + {0x0000b030, 0x028b028a},
16287 + {0x0000b034, 0x0388028c},
16288 + {0x0000b038, 0x038a0389},
16289 + {0x0000b03c, 0x038c038b},
16290 + {0x0000b040, 0x0390038d},
16291 + {0x0000b044, 0x03920391},
16292 + {0x0000b048, 0x03940393},
16293 + {0x0000b04c, 0x03960395},
16294 + {0x0000b050, 0x00000000},
16295 + {0x0000b054, 0x00000000},
16296 + {0x0000b058, 0x00000000},
16297 + {0x0000b05c, 0x00000000},
16298 + {0x0000b060, 0x00000000},
16299 + {0x0000b064, 0x00000000},
16300 + {0x0000b068, 0x00000000},
16301 + {0x0000b06c, 0x00000000},
16302 + {0x0000b070, 0x00000000},
16303 + {0x0000b074, 0x00000000},
16304 + {0x0000b078, 0x00000000},
16305 + {0x0000b07c, 0x00000000},
16306 + {0x0000b080, 0x32323232},
16307 + {0x0000b084, 0x2f2f3232},
16308 + {0x0000b088, 0x23282a2d},
16309 + {0x0000b08c, 0x1c1e2123},
16310 + {0x0000b090, 0x14171919},
16311 + {0x0000b094, 0x0e0e1214},
16312 + {0x0000b098, 0x03050707},
16313 + {0x0000b09c, 0x00030303},
16314 + {0x0000b0a0, 0x00000000},
16315 + {0x0000b0a4, 0x00000000},
16316 + {0x0000b0a8, 0x00000000},
16317 + {0x0000b0ac, 0x00000000},
16318 + {0x0000b0b0, 0x00000000},
16319 + {0x0000b0b4, 0x00000000},
16320 + {0x0000b0b8, 0x00000000},
16321 + {0x0000b0bc, 0x00000000},
16322 + {0x0000b0c0, 0x003f0020},
16323 + {0x0000b0c4, 0x00400041},
16324 + {0x0000b0c8, 0x0140005f},
16325 + {0x0000b0cc, 0x0160015f},
16326 + {0x0000b0d0, 0x017e017f},
16327 + {0x0000b0d4, 0x02410242},
16328 + {0x0000b0d8, 0x025f0240},
16329 + {0x0000b0dc, 0x027f0260},
16330 + {0x0000b0e0, 0x0341027e},
16331 + {0x0000b0e4, 0x035f0340},
16332 + {0x0000b0e8, 0x037f0360},
16333 + {0x0000b0ec, 0x04400441},
16334 + {0x0000b0f0, 0x0460045f},
16335 + {0x0000b0f4, 0x0541047f},
16336 + {0x0000b0f8, 0x055f0540},
16337 + {0x0000b0fc, 0x057f0560},
16338 + {0x0000b100, 0x06400641},
16339 + {0x0000b104, 0x0660065f},
16340 + {0x0000b108, 0x067e067f},
16341 + {0x0000b10c, 0x07410742},
16342 + {0x0000b110, 0x075f0740},
16343 + {0x0000b114, 0x077f0760},
16344 + {0x0000b118, 0x07800781},
16345 + {0x0000b11c, 0x07a0079f},
16346 + {0x0000b120, 0x07c107bf},
16347 + {0x0000b124, 0x000007c0},
16348 + {0x0000b128, 0x00000000},
16349 + {0x0000b12c, 0x00000000},
16350 + {0x0000b130, 0x00000000},
16351 + {0x0000b134, 0x00000000},
16352 + {0x0000b138, 0x00000000},
16353 + {0x0000b13c, 0x00000000},
16354 + {0x0000b140, 0x003f0020},
16355 + {0x0000b144, 0x00400041},
16356 + {0x0000b148, 0x0140005f},
16357 + {0x0000b14c, 0x0160015f},
16358 + {0x0000b150, 0x017e017f},
16359 + {0x0000b154, 0x02410242},
16360 + {0x0000b158, 0x025f0240},
16361 + {0x0000b15c, 0x027f0260},
16362 + {0x0000b160, 0x0341027e},
16363 + {0x0000b164, 0x035f0340},
16364 + {0x0000b168, 0x037f0360},
16365 + {0x0000b16c, 0x04400441},
16366 + {0x0000b170, 0x0460045f},
16367 + {0x0000b174, 0x0541047f},
16368 + {0x0000b178, 0x055f0540},
16369 + {0x0000b17c, 0x057f0560},
16370 + {0x0000b180, 0x06400641},
16371 + {0x0000b184, 0x0660065f},
16372 + {0x0000b188, 0x067e067f},
16373 + {0x0000b18c, 0x07410742},
16374 + {0x0000b190, 0x075f0740},
16375 + {0x0000b194, 0x077f0760},
16376 + {0x0000b198, 0x07800781},
16377 + {0x0000b19c, 0x07a0079f},
16378 + {0x0000b1a0, 0x07c107bf},
16379 + {0x0000b1a4, 0x000007c0},
16380 + {0x0000b1a8, 0x00000000},
16381 + {0x0000b1ac, 0x00000000},
16382 + {0x0000b1b0, 0x00000000},
16383 + {0x0000b1b4, 0x00000000},
16384 + {0x0000b1b8, 0x00000000},
16385 + {0x0000b1bc, 0x00000000},
16386 + {0x0000b1c0, 0x00000000},
16387 + {0x0000b1c4, 0x00000000},
16388 + {0x0000b1c8, 0x00000000},
16389 + {0x0000b1cc, 0x00000000},
16390 + {0x0000b1d0, 0x00000000},
16391 + {0x0000b1d4, 0x00000000},
16392 + {0x0000b1d8, 0x00000000},
16393 + {0x0000b1dc, 0x00000000},
16394 + {0x0000b1e0, 0x00000000},
16395 + {0x0000b1e4, 0x00000000},
16396 + {0x0000b1e8, 0x00000000},
16397 + {0x0000b1ec, 0x00000000},
16398 + {0x0000b1f0, 0x00000396},
16399 + {0x0000b1f4, 0x00000396},
16400 + {0x0000b1f8, 0x00000396},
16401 + {0x0000b1fc, 0x00000196},
16402 +};
16403 +
16404 +static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p0[][5] = {
16405 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
16406 + {0x0000a410, 0x000050da, 0x000050da, 0x000050da, 0x000050da},
16407 + {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
16408 + {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
16409 + {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
16410 + {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
16411 + {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
16412 + {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
16413 + {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
16414 + {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
16415 + {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
16416 + {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
16417 + {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
16418 + {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
16419 + {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
16420 + {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
16421 + {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
16422 + {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
16423 + {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
16424 + {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
16425 + {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
16426 + {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
16427 + {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
16428 + {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
16429 + {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
16430 + {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
16431 + {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
16432 + {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
16433 + {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
16434 + {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
16435 + {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
16436 + {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
16437 + {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
16438 + {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
16439 + {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
16440 + {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
16441 + {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
16442 + {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
16443 + {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
16444 + {0x0000a594, 0x1c800223, 0x1c800223, 0x12800400, 0x12800400},
16445 + {0x0000a598, 0x21820220, 0x21820220, 0x16800402, 0x16800402},
16446 + {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
16447 + {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1c800603, 0x1c800603},
16448 + {0x0000a5a4, 0x2f822222, 0x2f822222, 0x21800a02, 0x21800a02},
16449 + {0x0000a5a8, 0x34822225, 0x34822225, 0x25800a04, 0x25800a04},
16450 + {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x28800a20, 0x28800a20},
16451 + {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2c800e20, 0x2c800e20},
16452 + {0x0000a5b4, 0x4282242a, 0x4282242a, 0x30800e22, 0x30800e22},
16453 + {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
16454 + {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
16455 + {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
16456 + {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
16457 + {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
16458 + {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x47801a83, 0x47801a83},
16459 + {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x4a801c84, 0x4a801c84},
16460 + {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x4e801ce3, 0x4e801ce3},
16461 + {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x52801ce5, 0x52801ce5},
16462 + {0x0000a5dc, 0x7086308c, 0x7086308c, 0x56801ce9, 0x56801ce9},
16463 + {0x0000a5e0, 0x738a308a, 0x738a308a, 0x5a801ceb, 0x5a801ceb},
16464 + {0x0000a5e4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
16465 + {0x0000a5e8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
16466 + {0x0000a5ec, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
16467 + {0x0000a5f0, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
16468 + {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
16469 + {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
16470 + {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
16471 + {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
16472 + {0x00016048, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
16473 + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
16474 + {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
16475 + {0x00016448, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
16476 + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
16477 + {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
16478 + {0x00016848, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
16479 + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
16480 +};
16481 +
16482 +static const u32 ar9300_2p0_mac_core[][2] = {
16483 + /* Addr allmodes */
16484 + {0x00000008, 0x00000000},
16485 + {0x00000030, 0x00020085},
16486 + {0x00000034, 0x00000005},
16487 + {0x00000040, 0x00000000},
16488 + {0x00000044, 0x00000000},
16489 + {0x00000048, 0x00000008},
16490 + {0x0000004c, 0x00000010},
16491 + {0x00000050, 0x00000000},
16492 + {0x00001040, 0x002ffc0f},
16493 + {0x00001044, 0x002ffc0f},
16494 + {0x00001048, 0x002ffc0f},
16495 + {0x0000104c, 0x002ffc0f},
16496 + {0x00001050, 0x002ffc0f},
16497 + {0x00001054, 0x002ffc0f},
16498 + {0x00001058, 0x002ffc0f},
16499 + {0x0000105c, 0x002ffc0f},
16500 + {0x00001060, 0x002ffc0f},
16501 + {0x00001064, 0x002ffc0f},
16502 + {0x000010f0, 0x00000100},
16503 + {0x00001270, 0x00000000},
16504 + {0x000012b0, 0x00000000},
16505 + {0x000012f0, 0x00000000},
16506 + {0x0000143c, 0x00000000},
16507 + {0x0000147c, 0x00000000},
16508 + {0x00008000, 0x00000000},
16509 + {0x00008004, 0x00000000},
16510 + {0x00008008, 0x00000000},
16511 + {0x0000800c, 0x00000000},
16512 + {0x00008018, 0x00000000},
16513 + {0x00008020, 0x00000000},
16514 + {0x00008038, 0x00000000},
16515 + {0x0000803c, 0x00000000},
16516 + {0x00008040, 0x00000000},
16517 + {0x00008044, 0x00000000},
16518 + {0x00008048, 0x00000000},
16519 + {0x0000804c, 0xffffffff},
16520 + {0x00008054, 0x00000000},
16521 + {0x00008058, 0x00000000},
16522 + {0x0000805c, 0x000fc78f},
16523 + {0x00008060, 0x0000000f},
16524 + {0x00008064, 0x00000000},
16525 + {0x00008070, 0x00000310},
16526 + {0x00008074, 0x00000020},
16527 + {0x00008078, 0x00000000},
16528 + {0x0000809c, 0x0000000f},
16529 + {0x000080a0, 0x00000000},
16530 + {0x000080a4, 0x02ff0000},
16531 + {0x000080a8, 0x0e070605},
16532 + {0x000080ac, 0x0000000d},
16533 + {0x000080b0, 0x00000000},
16534 + {0x000080b4, 0x00000000},
16535 + {0x000080b8, 0x00000000},
16536 + {0x000080bc, 0x00000000},
16537 + {0x000080c0, 0x2a800000},
16538 + {0x000080c4, 0x06900168},
16539 + {0x000080c8, 0x13881c20},
16540 + {0x000080cc, 0x01f40000},
16541 + {0x000080d0, 0x00252500},
16542 + {0x000080d4, 0x00a00000},
16543 + {0x000080d8, 0x00400000},
16544 + {0x000080dc, 0x00000000},
16545 + {0x000080e0, 0xffffffff},
16546 + {0x000080e4, 0x0000ffff},
16547 + {0x000080e8, 0x3f3f3f3f},
16548 + {0x000080ec, 0x00000000},
16549 + {0x000080f0, 0x00000000},
16550 + {0x000080f4, 0x00000000},
16551 + {0x000080fc, 0x00020000},
16552 + {0x00008100, 0x00000000},
16553 + {0x00008108, 0x00000052},
16554 + {0x0000810c, 0x00000000},
16555 + {0x00008110, 0x00000000},
16556 + {0x00008114, 0x000007ff},
16557 + {0x00008118, 0x000000aa},
16558 + {0x0000811c, 0x00003210},
16559 + {0x00008124, 0x00000000},
16560 + {0x00008128, 0x00000000},
16561 + {0x0000812c, 0x00000000},
16562 + {0x00008130, 0x00000000},
16563 + {0x00008134, 0x00000000},
16564 + {0x00008138, 0x00000000},
16565 + {0x0000813c, 0x0000ffff},
16566 + {0x00008144, 0xffffffff},
16567 + {0x00008168, 0x00000000},
16568 + {0x0000816c, 0x00000000},
16569 + {0x00008170, 0x18486200},
16570 + {0x00008174, 0x33332210},
16571 + {0x00008178, 0x00000000},
16572 + {0x0000817c, 0x00020000},
16573 + {0x000081c0, 0x00000000},
16574 + {0x000081c4, 0x33332210},
16575 + {0x000081c8, 0x00000000},
16576 + {0x000081cc, 0x00000000},
16577 + {0x000081d4, 0x00000000},
16578 + {0x000081ec, 0x00000000},
16579 + {0x000081f0, 0x00000000},
16580 + {0x000081f4, 0x00000000},
16581 + {0x000081f8, 0x00000000},
16582 + {0x000081fc, 0x00000000},
16583 + {0x00008240, 0x00100000},
16584 + {0x00008244, 0x0010f424},
16585 + {0x00008248, 0x00000800},
16586 + {0x0000824c, 0x0001e848},
16587 + {0x00008250, 0x00000000},
16588 + {0x00008254, 0x00000000},
16589 + {0x00008258, 0x00000000},
16590 + {0x0000825c, 0x40000000},
16591 + {0x00008260, 0x00080922},
16592 + {0x00008264, 0x98a00010},
16593 + {0x00008268, 0xffffffff},
16594 + {0x0000826c, 0x0000ffff},
16595 + {0x00008270, 0x00000000},
16596 + {0x00008274, 0x40000000},
16597 + {0x00008278, 0x003e4180},
16598 + {0x0000827c, 0x00000004},
16599 + {0x00008284, 0x0000002c},
16600 + {0x00008288, 0x0000002c},
16601 + {0x0000828c, 0x000000ff},
16602 + {0x00008294, 0x00000000},
16603 + {0x00008298, 0x00000000},
16604 + {0x0000829c, 0x00000000},
16605 + {0x00008300, 0x00000140},
16606 + {0x00008314, 0x00000000},
16607 + {0x0000831c, 0x0000010d},
16608 + {0x00008328, 0x00000000},
16609 + {0x0000832c, 0x00000007},
16610 + {0x00008330, 0x00000302},
16611 + {0x00008334, 0x00000700},
16612 + {0x00008338, 0x00ff0000},
16613 + {0x0000833c, 0x02400000},
16614 + {0x00008340, 0x000107ff},
16615 + {0x00008344, 0xaa48105b},
16616 + {0x00008348, 0x008f0000},
16617 + {0x0000835c, 0x00000000},
16618 + {0x00008360, 0xffffffff},
16619 + {0x00008364, 0xffffffff},
16620 + {0x00008368, 0x00000000},
16621 + {0x00008370, 0x00000000},
16622 + {0x00008374, 0x000000ff},
16623 + {0x00008378, 0x00000000},
16624 + {0x0000837c, 0x00000000},
16625 + {0x00008380, 0xffffffff},
16626 + {0x00008384, 0xffffffff},
16627 + {0x00008390, 0xffffffff},
16628 + {0x00008394, 0xffffffff},
16629 + {0x00008398, 0x00000000},
16630 + {0x0000839c, 0x00000000},
16631 + {0x000083a0, 0x00000000},
16632 + {0x000083a4, 0x0000fa14},
16633 + {0x000083a8, 0x000f0c00},
16634 + {0x000083ac, 0x33332210},
16635 + {0x000083b0, 0x33332210},
16636 + {0x000083b4, 0x33332210},
16637 + {0x000083b8, 0x33332210},
16638 + {0x000083bc, 0x00000000},
16639 + {0x000083c0, 0x00000000},
16640 + {0x000083c4, 0x00000000},
16641 + {0x000083c8, 0x00000000},
16642 + {0x000083cc, 0x00000200},
16643 + {0x000083d0, 0x000301ff},
16644 +};
16645 +
16646 +static const u32 ar9300Common_wo_xlna_rx_gain_table_2p0[][2] = {
16647 + /* Addr allmodes */
16648 + {0x0000a000, 0x00010000},
16649 + {0x0000a004, 0x00030002},
16650 + {0x0000a008, 0x00050004},
16651 + {0x0000a00c, 0x00810080},
16652 + {0x0000a010, 0x01800082},
16653 + {0x0000a014, 0x01820181},
16654 + {0x0000a018, 0x01840183},
16655 + {0x0000a01c, 0x01880185},
16656 + {0x0000a020, 0x018a0189},
16657 + {0x0000a024, 0x02850284},
16658 + {0x0000a028, 0x02890288},
16659 + {0x0000a02c, 0x03850384},
16660 + {0x0000a030, 0x03890388},
16661 + {0x0000a034, 0x038b038a},
16662 + {0x0000a038, 0x038d038c},
16663 + {0x0000a03c, 0x03910390},
16664 + {0x0000a040, 0x03930392},
16665 + {0x0000a044, 0x03950394},
16666 + {0x0000a048, 0x00000396},
16667 + {0x0000a04c, 0x00000000},
16668 + {0x0000a050, 0x00000000},
16669 + {0x0000a054, 0x00000000},
16670 + {0x0000a058, 0x00000000},
16671 + {0x0000a05c, 0x00000000},
16672 + {0x0000a060, 0x00000000},
16673 + {0x0000a064, 0x00000000},
16674 + {0x0000a068, 0x00000000},
16675 + {0x0000a06c, 0x00000000},
16676 + {0x0000a070, 0x00000000},
16677 + {0x0000a074, 0x00000000},
16678 + {0x0000a078, 0x00000000},
16679 + {0x0000a07c, 0x00000000},
16680 + {0x0000a080, 0x28282828},
16681 + {0x0000a084, 0x28282828},
16682 + {0x0000a088, 0x28282828},
16683 + {0x0000a08c, 0x28282828},
16684 + {0x0000a090, 0x28282828},
16685 + {0x0000a094, 0x21212128},
16686 + {0x0000a098, 0x171c1c1c},
16687 + {0x0000a09c, 0x02020212},
16688 + {0x0000a0a0, 0x00000202},
16689 + {0x0000a0a4, 0x00000000},
16690 + {0x0000a0a8, 0x00000000},
16691 + {0x0000a0ac, 0x00000000},
16692 + {0x0000a0b0, 0x00000000},
16693 + {0x0000a0b4, 0x00000000},
16694 + {0x0000a0b8, 0x00000000},
16695 + {0x0000a0bc, 0x00000000},
16696 + {0x0000a0c0, 0x001f0000},
16697 + {0x0000a0c4, 0x011f0100},
16698 + {0x0000a0c8, 0x011d011e},
16699 + {0x0000a0cc, 0x011b011c},
16700 + {0x0000a0d0, 0x02030204},
16701 + {0x0000a0d4, 0x02010202},
16702 + {0x0000a0d8, 0x021f0200},
16703 + {0x0000a0dc, 0x021d021e},
16704 + {0x0000a0e0, 0x03010302},
16705 + {0x0000a0e4, 0x031f0300},
16706 + {0x0000a0e8, 0x0402031e},
16707 + {0x0000a0ec, 0x04000401},
16708 + {0x0000a0f0, 0x041e041f},
16709 + {0x0000a0f4, 0x05010502},
16710 + {0x0000a0f8, 0x051f0500},
16711 + {0x0000a0fc, 0x0602051e},
16712 + {0x0000a100, 0x06000601},
16713 + {0x0000a104, 0x061e061f},
16714 + {0x0000a108, 0x0703061d},
16715 + {0x0000a10c, 0x07010702},
16716 + {0x0000a110, 0x00000700},
16717 + {0x0000a114, 0x00000000},
16718 + {0x0000a118, 0x00000000},
16719 + {0x0000a11c, 0x00000000},
16720 + {0x0000a120, 0x00000000},
16721 + {0x0000a124, 0x00000000},
16722 + {0x0000a128, 0x00000000},
16723 + {0x0000a12c, 0x00000000},
16724 + {0x0000a130, 0x00000000},
16725 + {0x0000a134, 0x00000000},
16726 + {0x0000a138, 0x00000000},
16727 + {0x0000a13c, 0x00000000},
16728 + {0x0000a140, 0x001f0000},
16729 + {0x0000a144, 0x011f0100},
16730 + {0x0000a148, 0x011d011e},
16731 + {0x0000a14c, 0x011b011c},
16732 + {0x0000a150, 0x02030204},
16733 + {0x0000a154, 0x02010202},
16734 + {0x0000a158, 0x021f0200},
16735 + {0x0000a15c, 0x021d021e},
16736 + {0x0000a160, 0x03010302},
16737 + {0x0000a164, 0x031f0300},
16738 + {0x0000a168, 0x0402031e},
16739 + {0x0000a16c, 0x04000401},
16740 + {0x0000a170, 0x041e041f},
16741 + {0x0000a174, 0x05010502},
16742 + {0x0000a178, 0x051f0500},
16743 + {0x0000a17c, 0x0602051e},
16744 + {0x0000a180, 0x06000601},
16745 + {0x0000a184, 0x061e061f},
16746 + {0x0000a188, 0x0703061d},
16747 + {0x0000a18c, 0x07010702},
16748 + {0x0000a190, 0x00000700},
16749 + {0x0000a194, 0x00000000},
16750 + {0x0000a198, 0x00000000},
16751 + {0x0000a19c, 0x00000000},
16752 + {0x0000a1a0, 0x00000000},
16753 + {0x0000a1a4, 0x00000000},
16754 + {0x0000a1a8, 0x00000000},
16755 + {0x0000a1ac, 0x00000000},
16756 + {0x0000a1b0, 0x00000000},
16757 + {0x0000a1b4, 0x00000000},
16758 + {0x0000a1b8, 0x00000000},
16759 + {0x0000a1bc, 0x00000000},
16760 + {0x0000a1c0, 0x00000000},
16761 + {0x0000a1c4, 0x00000000},
16762 + {0x0000a1c8, 0x00000000},
16763 + {0x0000a1cc, 0x00000000},
16764 + {0x0000a1d0, 0x00000000},
16765 + {0x0000a1d4, 0x00000000},
16766 + {0x0000a1d8, 0x00000000},
16767 + {0x0000a1dc, 0x00000000},
16768 + {0x0000a1e0, 0x00000000},
16769 + {0x0000a1e4, 0x00000000},
16770 + {0x0000a1e8, 0x00000000},
16771 + {0x0000a1ec, 0x00000000},
16772 + {0x0000a1f0, 0x00000396},
16773 + {0x0000a1f4, 0x00000396},
16774 + {0x0000a1f8, 0x00000396},
16775 + {0x0000a1fc, 0x00000296},
16776 + {0x0000b000, 0x00010000},
16777 + {0x0000b004, 0x00030002},
16778 + {0x0000b008, 0x00050004},
16779 + {0x0000b00c, 0x00810080},
16780 + {0x0000b010, 0x00830082},
16781 + {0x0000b014, 0x01810180},
16782 + {0x0000b018, 0x01830182},
16783 + {0x0000b01c, 0x01850184},
16784 + {0x0000b020, 0x02810280},
16785 + {0x0000b024, 0x02830282},
16786 + {0x0000b028, 0x02850284},
16787 + {0x0000b02c, 0x02890288},
16788 + {0x0000b030, 0x028b028a},
16789 + {0x0000b034, 0x0388028c},
16790 + {0x0000b038, 0x038a0389},
16791 + {0x0000b03c, 0x038c038b},
16792 + {0x0000b040, 0x0390038d},
16793 + {0x0000b044, 0x03920391},
16794 + {0x0000b048, 0x03940393},
16795 + {0x0000b04c, 0x03960395},
16796 + {0x0000b050, 0x00000000},
16797 + {0x0000b054, 0x00000000},
16798 + {0x0000b058, 0x00000000},
16799 + {0x0000b05c, 0x00000000},
16800 + {0x0000b060, 0x00000000},
16801 + {0x0000b064, 0x00000000},
16802 + {0x0000b068, 0x00000000},
16803 + {0x0000b06c, 0x00000000},
16804 + {0x0000b070, 0x00000000},
16805 + {0x0000b074, 0x00000000},
16806 + {0x0000b078, 0x00000000},
16807 + {0x0000b07c, 0x00000000},
16808 + {0x0000b080, 0x32323232},
16809 + {0x0000b084, 0x2f2f3232},
16810 + {0x0000b088, 0x23282a2d},
16811 + {0x0000b08c, 0x1c1e2123},
16812 + {0x0000b090, 0x14171919},
16813 + {0x0000b094, 0x0e0e1214},
16814 + {0x0000b098, 0x03050707},
16815 + {0x0000b09c, 0x00030303},
16816 + {0x0000b0a0, 0x00000000},
16817 + {0x0000b0a4, 0x00000000},
16818 + {0x0000b0a8, 0x00000000},
16819 + {0x0000b0ac, 0x00000000},
16820 + {0x0000b0b0, 0x00000000},
16821 + {0x0000b0b4, 0x00000000},
16822 + {0x0000b0b8, 0x00000000},
16823 + {0x0000b0bc, 0x00000000},
16824 + {0x0000b0c0, 0x003f0020},
16825 + {0x0000b0c4, 0x00400041},
16826 + {0x0000b0c8, 0x0140005f},
16827 + {0x0000b0cc, 0x0160015f},
16828 + {0x0000b0d0, 0x017e017f},
16829 + {0x0000b0d4, 0x02410242},
16830 + {0x0000b0d8, 0x025f0240},
16831 + {0x0000b0dc, 0x027f0260},
16832 + {0x0000b0e0, 0x0341027e},
16833 + {0x0000b0e4, 0x035f0340},
16834 + {0x0000b0e8, 0x037f0360},
16835 + {0x0000b0ec, 0x04400441},
16836 + {0x0000b0f0, 0x0460045f},
16837 + {0x0000b0f4, 0x0541047f},
16838 + {0x0000b0f8, 0x055f0540},
16839 + {0x0000b0fc, 0x057f0560},
16840 + {0x0000b100, 0x06400641},
16841 + {0x0000b104, 0x0660065f},
16842 + {0x0000b108, 0x067e067f},
16843 + {0x0000b10c, 0x07410742},
16844 + {0x0000b110, 0x075f0740},
16845 + {0x0000b114, 0x077f0760},
16846 + {0x0000b118, 0x07800781},
16847 + {0x0000b11c, 0x07a0079f},
16848 + {0x0000b120, 0x07c107bf},
16849 + {0x0000b124, 0x000007c0},
16850 + {0x0000b128, 0x00000000},
16851 + {0x0000b12c, 0x00000000},
16852 + {0x0000b130, 0x00000000},
16853 + {0x0000b134, 0x00000000},
16854 + {0x0000b138, 0x00000000},
16855 + {0x0000b13c, 0x00000000},
16856 + {0x0000b140, 0x003f0020},
16857 + {0x0000b144, 0x00400041},
16858 + {0x0000b148, 0x0140005f},
16859 + {0x0000b14c, 0x0160015f},
16860 + {0x0000b150, 0x017e017f},
16861 + {0x0000b154, 0x02410242},
16862 + {0x0000b158, 0x025f0240},
16863 + {0x0000b15c, 0x027f0260},
16864 + {0x0000b160, 0x0341027e},
16865 + {0x0000b164, 0x035f0340},
16866 + {0x0000b168, 0x037f0360},
16867 + {0x0000b16c, 0x04400441},
16868 + {0x0000b170, 0x0460045f},
16869 + {0x0000b174, 0x0541047f},
16870 + {0x0000b178, 0x055f0540},
16871 + {0x0000b17c, 0x057f0560},
16872 + {0x0000b180, 0x06400641},
16873 + {0x0000b184, 0x0660065f},
16874 + {0x0000b188, 0x067e067f},
16875 + {0x0000b18c, 0x07410742},
16876 + {0x0000b190, 0x075f0740},
16877 + {0x0000b194, 0x077f0760},
16878 + {0x0000b198, 0x07800781},
16879 + {0x0000b19c, 0x07a0079f},
16880 + {0x0000b1a0, 0x07c107bf},
16881 + {0x0000b1a4, 0x000007c0},
16882 + {0x0000b1a8, 0x00000000},
16883 + {0x0000b1ac, 0x00000000},
16884 + {0x0000b1b0, 0x00000000},
16885 + {0x0000b1b4, 0x00000000},
16886 + {0x0000b1b8, 0x00000000},
16887 + {0x0000b1bc, 0x00000000},
16888 + {0x0000b1c0, 0x00000000},
16889 + {0x0000b1c4, 0x00000000},
16890 + {0x0000b1c8, 0x00000000},
16891 + {0x0000b1cc, 0x00000000},
16892 + {0x0000b1d0, 0x00000000},
16893 + {0x0000b1d4, 0x00000000},
16894 + {0x0000b1d8, 0x00000000},
16895 + {0x0000b1dc, 0x00000000},
16896 + {0x0000b1e0, 0x00000000},
16897 + {0x0000b1e4, 0x00000000},
16898 + {0x0000b1e8, 0x00000000},
16899 + {0x0000b1ec, 0x00000000},
16900 + {0x0000b1f0, 0x00000396},
16901 + {0x0000b1f4, 0x00000396},
16902 + {0x0000b1f8, 0x00000396},
16903 + {0x0000b1fc, 0x00000196},
16904 +};
16905 +
16906 +static const u32 ar9300_2p0_soc_preamble[][2] = {
16907 + /* Addr allmodes */
16908 + {0x000040a4, 0x00a0c1c9},
16909 + {0x00007008, 0x00000000},
16910 + {0x00007020, 0x00000000},
16911 + {0x00007034, 0x00000002},
16912 + {0x00007038, 0x000004c2},
16913 +};
16914 +
16915 +/*
16916 + * PCIE-PHY programming array, to be used prior to entering
16917 + * full sleep (holding RTC in reset, PLL is ON in L1 mode)
16918 + */
16919 +static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0[][2] = {
16920 + {0x00004040, 0x08212e5e},
16921 + {0x00004040, 0x0008003b},
16922 + {0x00004044, 0x00000000},
16923 +};
16924 +
16925 +/*
16926 + * PCIE-PHY programming array, to be used when not in
16927 + * full sleep (holding RTC in reset)
16928 + */
16929 +static const u32 ar9300PciePhy_clkreq_enable_L1_2p0[][2] = {
16930 + {0x00004040, 0x08253e5e},
16931 + {0x00004040, 0x0008003b},
16932 + {0x00004044, 0x00000000},
16933 +};
16934 +
16935 +/*
16936 + * PCIE-PHY programming array, to be used prior to entering
16937 + * full sleep (holding RTC in reset)
16938 + */
16939 +static const u32 ar9300PciePhy_clkreq_disable_L1_2p0[][2] = {
16940 + {0x00004040, 0x08213e5e},
16941 + {0x00004040, 0x0008003b},
16942 + {0x00004044, 0x00000000},
16943 +};
16944 +
16945 +#endif /* INITVALS_9003_H */
16946 --- /dev/null
16947 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
16948 @@ -0,0 +1,610 @@
16949 +/*
16950 + * Copyright (c) 2010 Atheros Communications Inc.
16951 + *
16952 + * Permission to use, copy, modify, and/or distribute this software for any
16953 + * purpose with or without fee is hereby granted, provided that the above
16954 + * copyright notice and this permission notice appear in all copies.
16955 + *
16956 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
16957 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16958 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16959 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16960 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16961 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16962 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16963 + */
16964 +#include "hw.h"
16965 +
16966 +static void ar9003_hw_rx_enable(struct ath_hw *hw)
16967 +{
16968 + REG_WRITE(hw, AR_CR, 0);
16969 +}
16970 +
16971 +static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
16972 +{
16973 + int checksum;
16974 +
16975 + checksum = ads->info + ads->link
16976 + + ads->data0 + ads->ctl3
16977 + + ads->data1 + ads->ctl5
16978 + + ads->data2 + ads->ctl7
16979 + + ads->data3 + ads->ctl9;
16980 +
16981 + return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
16982 +}
16983 +
16984 +static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
16985 +{
16986 + struct ar9003_txc *ads = ds;
16987 +
16988 + ads->link = ds_link;
16989 + ads->ctl10 &= ~AR_TxPtrChkSum;
16990 + ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
16991 +}
16992 +
16993 +static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
16994 +{
16995 + struct ar9003_txc *ads = ds;
16996 +
16997 + *ds_link = &ads->link;
16998 +}
16999 +
17000 +static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
17001 +{
17002 + u32 isr = 0;
17003 + u32 mask2 = 0;
17004 + struct ath9k_hw_capabilities *pCap = &ah->caps;
17005 + u32 sync_cause = 0;
17006 + struct ath_common *common = ath9k_hw_common(ah);
17007 +
17008 + if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
17009 + if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
17010 + == AR_RTC_STATUS_ON)
17011 + isr = REG_READ(ah, AR_ISR);
17012 + }
17013 +
17014 + sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
17015 +
17016 + *masked = 0;
17017 +
17018 + if (!isr && !sync_cause)
17019 + return false;
17020 +
17021 + if (isr) {
17022 + if (isr & AR_ISR_BCNMISC) {
17023 + u32 isr2;
17024 + isr2 = REG_READ(ah, AR_ISR_S2);
17025 +
17026 + mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
17027 + MAP_ISR_S2_TIM);
17028 + mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
17029 + MAP_ISR_S2_DTIM);
17030 + mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
17031 + MAP_ISR_S2_DTIMSYNC);
17032 + mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
17033 + MAP_ISR_S2_CABEND);
17034 + mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
17035 + MAP_ISR_S2_GTT);
17036 + mask2 |= ((isr2 & AR_ISR_S2_CST) <<
17037 + MAP_ISR_S2_CST);
17038 + mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
17039 + MAP_ISR_S2_TSFOOR);
17040 +
17041 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
17042 + REG_WRITE(ah, AR_ISR_S2, isr2);
17043 + isr &= ~AR_ISR_BCNMISC;
17044 + }
17045 + }
17046 +
17047 + if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
17048 + isr = REG_READ(ah, AR_ISR_RAC);
17049 +
17050 + if (isr == 0xffffffff) {
17051 + *masked = 0;
17052 + return false;
17053 + }
17054 +
17055 + *masked = isr & ATH9K_INT_COMMON;
17056 +
17057 + if (ah->config.rx_intr_mitigation)
17058 + if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
17059 + *masked |= ATH9K_INT_RXLP;
17060 +
17061 + if (ah->config.tx_intr_mitigation)
17062 + if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
17063 + *masked |= ATH9K_INT_TX;
17064 +
17065 + if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
17066 + *masked |= ATH9K_INT_RXLP;
17067 +
17068 + if (isr & AR_ISR_HP_RXOK)
17069 + *masked |= ATH9K_INT_RXHP;
17070 +
17071 + if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
17072 + *masked |= ATH9K_INT_TX;
17073 +
17074 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
17075 + u32 s0, s1;
17076 + s0 = REG_READ(ah, AR_ISR_S0);
17077 + REG_WRITE(ah, AR_ISR_S0, s0);
17078 + s1 = REG_READ(ah, AR_ISR_S1);
17079 + REG_WRITE(ah, AR_ISR_S1, s1);
17080 +
17081 + isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
17082 + AR_ISR_TXEOL);
17083 + }
17084 + }
17085 +
17086 + if (isr & AR_ISR_GENTMR) {
17087 + u32 s5;
17088 +
17089 + if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
17090 + s5 = REG_READ(ah, AR_ISR_S5_S);
17091 + else
17092 + s5 = REG_READ(ah, AR_ISR_S5);
17093 +
17094 + ah->intr_gen_timer_trigger =
17095 + MS(s5, AR_ISR_S5_GENTIMER_TRIG);
17096 +
17097 + ah->intr_gen_timer_thresh =
17098 + MS(s5, AR_ISR_S5_GENTIMER_THRESH);
17099 +
17100 + if (ah->intr_gen_timer_trigger)
17101 + *masked |= ATH9K_INT_GENTIMER;
17102 +
17103 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
17104 + REG_WRITE(ah, AR_ISR_S5, s5);
17105 + isr &= ~AR_ISR_GENTMR;
17106 + }
17107 +
17108 + }
17109 +
17110 + *masked |= mask2;
17111 +
17112 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
17113 + REG_WRITE(ah, AR_ISR, isr);
17114 +
17115 + (void) REG_READ(ah, AR_ISR);
17116 + }
17117 + }
17118 +
17119 + if (sync_cause) {
17120 + if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
17121 + REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
17122 + REG_WRITE(ah, AR_RC, 0);
17123 + *masked |= ATH9K_INT_FATAL;
17124 + }
17125 +
17126 + if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
17127 + ath_print(common, ATH_DBG_INTERRUPT,
17128 + "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
17129 +
17130 + REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
17131 + (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
17132 +
17133 + }
17134 + return true;
17135 +}
17136 +
17137 +static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
17138 + bool is_firstseg, bool is_lastseg,
17139 + const void *ds0, dma_addr_t buf_addr,
17140 + unsigned int qcu)
17141 +{
17142 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17143 + unsigned int descid = 0;
17144 +
17145 + ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) |
17146 + (1 << AR_TxRxDesc_S) |
17147 + (1 << AR_CtrlStat_S) |
17148 + (qcu << AR_TxQcuNum_S) | 0x17;
17149 +
17150 + ads->data0 = buf_addr;
17151 + ads->data1 = 0;
17152 + ads->data2 = 0;
17153 + ads->data3 = 0;
17154 +
17155 + ads->ctl3 = (seglen << AR_BufLen_S);
17156 + ads->ctl3 &= AR_BufLen;
17157 +
17158 + /* Fill in pointer checksum and descriptor id */
17159 + ads->ctl10 = ar9003_calc_ptr_chksum(ads);
17160 + ads->ctl10 |= (descid << AR_TxDescId_S);
17161 +
17162 + if (is_firstseg) {
17163 + ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore);
17164 + } else if (is_lastseg) {
17165 + ads->ctl11 = 0;
17166 + ads->ctl12 = 0;
17167 + ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13;
17168 + ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14;
17169 + } else {
17170 + /* XXX Intermediate descriptor in a multi-descriptor frame.*/
17171 + ads->ctl11 = 0;
17172 + ads->ctl12 = AR_TxMore;
17173 + ads->ctl13 = 0;
17174 + ads->ctl14 = 0;
17175 + }
17176 +}
17177 +
17178 +static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
17179 + struct ath_tx_status *ts)
17180 +{
17181 + struct ar9003_txs *ads;
17182 +
17183 + ads = &ah->ts_ring[ah->ts_tail];
17184 +
17185 + if ((ads->status8 & AR_TxDone) == 0)
17186 + return -EINPROGRESS;
17187 +
17188 + ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
17189 +
17190 + if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
17191 + (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
17192 + ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
17193 + "Tx Descriptor error %x\n", ads->ds_info);
17194 + memset(ads, 0, sizeof(*ads));
17195 + return -EIO;
17196 + }
17197 +
17198 + ts->qid = MS(ads->ds_info, AR_TxQcuNum);
17199 + ts->desc_id = MS(ads->status1, AR_TxDescId);
17200 + ts->ts_seqnum = MS(ads->status8, AR_SeqNum);
17201 + ts->ts_tstamp = ads->status4;
17202 + ts->ts_status = 0;
17203 + ts->ts_flags = 0;
17204 +
17205 + if (ads->status3 & AR_ExcessiveRetries)
17206 + ts->ts_status |= ATH9K_TXERR_XRETRY;
17207 + if (ads->status3 & AR_Filtered)
17208 + ts->ts_status |= ATH9K_TXERR_FILT;
17209 + if (ads->status3 & AR_FIFOUnderrun) {
17210 + ts->ts_status |= ATH9K_TXERR_FIFO;
17211 + ath9k_hw_updatetxtriglevel(ah, true);
17212 + }
17213 + if (ads->status8 & AR_TxOpExceeded)
17214 + ts->ts_status |= ATH9K_TXERR_XTXOP;
17215 + if (ads->status3 & AR_TxTimerExpired)
17216 + ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
17217 +
17218 + if (ads->status3 & AR_DescCfgErr)
17219 + ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
17220 + if (ads->status3 & AR_TxDataUnderrun) {
17221 + ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
17222 + ath9k_hw_updatetxtriglevel(ah, true);
17223 + }
17224 + if (ads->status3 & AR_TxDelimUnderrun) {
17225 + ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
17226 + ath9k_hw_updatetxtriglevel(ah, true);
17227 + }
17228 + if (ads->status2 & AR_TxBaStatus) {
17229 + ts->ts_flags |= ATH9K_TX_BA;
17230 + ts->ba_low = ads->status5;
17231 + ts->ba_high = ads->status6;
17232 + }
17233 +
17234 + ts->ts_rateindex = MS(ads->status8, AR_FinalTxIdx);
17235 +
17236 + ts->ts_rssi = MS(ads->status7, AR_TxRSSICombined);
17237 + ts->ts_rssi_ctl0 = MS(ads->status2, AR_TxRSSIAnt00);
17238 + ts->ts_rssi_ctl1 = MS(ads->status2, AR_TxRSSIAnt01);
17239 + ts->ts_rssi_ctl2 = MS(ads->status2, AR_TxRSSIAnt02);
17240 + ts->ts_rssi_ext0 = MS(ads->status7, AR_TxRSSIAnt10);
17241 + ts->ts_rssi_ext1 = MS(ads->status7, AR_TxRSSIAnt11);
17242 + ts->ts_rssi_ext2 = MS(ads->status7, AR_TxRSSIAnt12);
17243 + ts->ts_shortretry = MS(ads->status3, AR_RTSFailCnt);
17244 + ts->ts_longretry = MS(ads->status3, AR_DataFailCnt);
17245 + ts->ts_virtcol = MS(ads->status3, AR_VirtRetryCnt);
17246 + ts->ts_antenna = 0;
17247 +
17248 + ts->tid = MS(ads->status8, AR_TxTid);
17249 +
17250 + memset(ads, 0, sizeof(*ads));
17251 +
17252 + return 0;
17253 +}
17254 +
17255 +static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
17256 + u32 pktlen, enum ath9k_pkt_type type, u32 txpower,
17257 + u32 keyIx, enum ath9k_key_type keyType, u32 flags)
17258 +{
17259 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17260 +
17261 + txpower += ah->txpower_indexoffset;
17262 + if (txpower > 63)
17263 + txpower = 63;
17264 +
17265 + ads->ctl11 = (pktlen & AR_FrameLen)
17266 + | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
17267 + | SM(txpower, AR_XmitPower)
17268 + | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
17269 + | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
17270 + | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
17271 + | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
17272 +
17273 + ads->ctl12 =
17274 + (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
17275 + | SM(type, AR_FrameType)
17276 + | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
17277 + | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
17278 + | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
17279 +
17280 + ads->ctl17 = SM(keyType, AR_EncrType) |
17281 + (flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
17282 + ads->ctl18 = 0;
17283 + ads->ctl19 = AR_Not_Sounding;
17284 +
17285 + ads->ctl20 = 0;
17286 + ads->ctl21 = 0;
17287 + ads->ctl22 = 0;
17288 +}
17289 +
17290 +static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
17291 + void *lastds,
17292 + u32 durUpdateEn, u32 rtsctsRate,
17293 + u32 rtsctsDuration,
17294 + struct ath9k_11n_rate_series series[],
17295 + u32 nseries, u32 flags)
17296 +{
17297 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17298 + struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds;
17299 + u_int32_t ctl11;
17300 +
17301 + if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
17302 + ctl11 = ads->ctl11;
17303 +
17304 + if (flags & ATH9K_TXDESC_RTSENA) {
17305 + ctl11 &= ~AR_CTSEnable;
17306 + ctl11 |= AR_RTSEnable;
17307 + } else {
17308 + ctl11 &= ~AR_RTSEnable;
17309 + ctl11 |= AR_CTSEnable;
17310 + }
17311 +
17312 + ads->ctl11 = ctl11;
17313 + } else {
17314 + ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable));
17315 + }
17316 +
17317 + ads->ctl13 = set11nTries(series, 0)
17318 + | set11nTries(series, 1)
17319 + | set11nTries(series, 2)
17320 + | set11nTries(series, 3)
17321 + | (durUpdateEn ? AR_DurUpdateEna : 0)
17322 + | SM(0, AR_BurstDur);
17323 +
17324 + ads->ctl14 = set11nRate(series, 0)
17325 + | set11nRate(series, 1)
17326 + | set11nRate(series, 2)
17327 + | set11nRate(series, 3);
17328 +
17329 + ads->ctl15 = set11nPktDurRTSCTS(series, 0)
17330 + | set11nPktDurRTSCTS(series, 1);
17331 +
17332 + ads->ctl16 = set11nPktDurRTSCTS(series, 2)
17333 + | set11nPktDurRTSCTS(series, 3);
17334 +
17335 + ads->ctl18 = set11nRateFlags(series, 0)
17336 + | set11nRateFlags(series, 1)
17337 + | set11nRateFlags(series, 2)
17338 + | set11nRateFlags(series, 3)
17339 + | SM(rtsctsRate, AR_RTSCTSRate);
17340 + ads->ctl19 = AR_Not_Sounding;
17341 +
17342 + last_ads->ctl13 = ads->ctl13;
17343 + last_ads->ctl14 = ads->ctl14;
17344 +}
17345 +
17346 +static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
17347 + u32 aggrLen)
17348 +{
17349 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17350 +
17351 + ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
17352 +
17353 + ads->ctl17 &= ~AR_AggrLen;
17354 + ads->ctl17 |= SM(aggrLen, AR_AggrLen);
17355 +}
17356 +
17357 +static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
17358 + u32 numDelims)
17359 +{
17360 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17361 + unsigned int ctl17;
17362 +
17363 + ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
17364 +
17365 + /*
17366 + * We use a stack variable to manipulate ctl6 to reduce uncached
17367 + * read modify, modfiy, write.
17368 + */
17369 + ctl17 = ads->ctl17;
17370 + ctl17 &= ~AR_PadDelim;
17371 + ctl17 |= SM(numDelims, AR_PadDelim);
17372 + ads->ctl17 = ctl17;
17373 +}
17374 +
17375 +static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
17376 +{
17377 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17378 +
17379 + ads->ctl12 |= AR_IsAggr;
17380 + ads->ctl12 &= ~AR_MoreAggr;
17381 + ads->ctl17 &= ~AR_PadDelim;
17382 +}
17383 +
17384 +static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
17385 +{
17386 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17387 +
17388 + ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
17389 +}
17390 +
17391 +static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
17392 + u32 burstDuration)
17393 +{
17394 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17395 +
17396 + ads->ctl13 &= ~AR_BurstDur;
17397 + ads->ctl13 |= SM(burstDuration, AR_BurstDur);
17398 +
17399 +}
17400 +
17401 +static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
17402 + u32 vmf)
17403 +{
17404 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17405 +
17406 + if (vmf)
17407 + ads->ctl11 |= AR_VirtMoreFrag;
17408 + else
17409 + ads->ctl11 &= ~AR_VirtMoreFrag;
17410 +}
17411 +
17412 +void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
17413 +{
17414 + struct ath_hw_ops *ops = ath9k_hw_ops(hw);
17415 +
17416 + ops->rx_enable = ar9003_hw_rx_enable;
17417 + ops->set_desc_link = ar9003_hw_set_desc_link;
17418 + ops->get_desc_link = ar9003_hw_get_desc_link;
17419 + ops->get_isr = ar9003_hw_get_isr;
17420 + ops->fill_txdesc = ar9003_hw_fill_txdesc;
17421 + ops->proc_txdesc = ar9003_hw_proc_txdesc;
17422 + ops->set11n_txdesc = ar9003_hw_set11n_txdesc;
17423 + ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario;
17424 + ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first;
17425 + ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
17426 + ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
17427 + ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
17428 + ops->set11n_burstduration = ar9003_hw_set11n_burstduration;
17429 + ops->set11n_virtualmorefrag = ar9003_hw_set11n_virtualmorefrag;
17430 +}
17431 +
17432 +void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
17433 +{
17434 + REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
17435 +}
17436 +EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize);
17437 +
17438 +void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
17439 + enum ath9k_rx_qtype qtype)
17440 +{
17441 + if (qtype == ATH9K_RX_QUEUE_HP)
17442 + REG_WRITE(ah, AR_HP_RXDP, rxdp);
17443 + else
17444 + REG_WRITE(ah, AR_LP_RXDP, rxdp);
17445 +}
17446 +EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma);
17447 +
17448 +int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
17449 + void *buf_addr)
17450 +{
17451 + struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
17452 + unsigned int phyerr;
17453 +
17454 + /* TODO: byte swap on big endian for ar9300_10 */
17455 +
17456 + if ((rxsp->status11 & AR_RxDone) == 0)
17457 + return -EINPROGRESS;
17458 +
17459 + if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
17460 + return -EINVAL;
17461 +
17462 + if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
17463 + return -EINPROGRESS;
17464 +
17465 + if (!rxs)
17466 + return 0;
17467 +
17468 + rxs->rs_status = 0;
17469 + rxs->rs_flags = 0;
17470 +
17471 + rxs->rs_datalen = rxsp->status2 & AR_DataLen;
17472 + rxs->rs_tstamp = rxsp->status3;
17473 +
17474 + /* XXX: Keycache */
17475 + rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
17476 + rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
17477 + rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
17478 + rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
17479 + rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
17480 + rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
17481 + rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
17482 +
17483 + if (rxsp->status11 & AR_RxKeyIdxValid)
17484 + rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
17485 + else
17486 + rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
17487 +
17488 + rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
17489 + rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
17490 +
17491 + rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
17492 + rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
17493 + rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
17494 + rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
17495 + rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
17496 +
17497 + rxs->evm0 = rxsp->status6;
17498 + rxs->evm1 = rxsp->status7;
17499 + rxs->evm2 = rxsp->status8;
17500 + rxs->evm3 = rxsp->status9;
17501 + rxs->evm4 = (rxsp->status10 & 0xffff);
17502 +
17503 + if (rxsp->status11 & AR_PreDelimCRCErr)
17504 + rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
17505 +
17506 + if (rxsp->status11 & AR_PostDelimCRCErr)
17507 + rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
17508 +
17509 + if (rxsp->status11 & AR_DecryptBusyErr)
17510 + rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
17511 +
17512 + if ((rxsp->status11 & AR_RxFrameOK) == 0) {
17513 + if (rxsp->status11 & AR_CRCErr) {
17514 + rxs->rs_status |= ATH9K_RXERR_CRC;
17515 + } else if (rxsp->status11 & AR_PHYErr) {
17516 + rxs->rs_status |= ATH9K_RXERR_PHY;
17517 + phyerr = MS(rxsp->status11, AR_PHYErrCode);
17518 + rxs->rs_phyerr = phyerr;
17519 + } else if (rxsp->status11 & AR_DecryptCRCErr) {
17520 + rxs->rs_status |= ATH9K_RXERR_DECRYPT;
17521 + } else if (rxsp->status11 & AR_MichaelErr) {
17522 + rxs->rs_status |= ATH9K_RXERR_MIC;
17523 + }
17524 + }
17525 +
17526 + return 0;
17527 +}
17528 +EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);
17529 +
17530 +void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
17531 +{
17532 + ah->ts_tail = 0;
17533 +
17534 + memset((void *) ah->ts_ring, 0,
17535 + ah->ts_size * sizeof(struct ar9003_txs));
17536 +
17537 + ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
17538 + "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
17539 + ah->ts_paddr_start, ah->ts_paddr_end,
17540 + ah->ts_ring, ah->ts_size);
17541 +
17542 + REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
17543 + REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
17544 +}
17545 +
17546 +void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
17547 + u32 ts_paddr_start,
17548 + u8 size)
17549 +{
17550 +
17551 + ah->ts_paddr_start = ts_paddr_start;
17552 + ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
17553 + ah->ts_size = size;
17554 + ah->ts_ring = (struct ar9003_txs *) ts_start;
17555 +
17556 + ath9k_hw_reset_txstatus_ring(ah);
17557 +}
17558 +EXPORT_SYMBOL(ath9k_hw_setup_statusring);
17559 --- /dev/null
17560 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
17561 @@ -0,0 +1,124 @@
17562 +/*
17563 + * Copyright (c) 2010 Atheros Communications Inc.
17564 + *
17565 + * Permission to use, copy, modify, and/or distribute this software for any
17566 + * purpose with or without fee is hereby granted, provided that the above
17567 + * copyright notice and this permission notice appear in all copies.
17568 + *
17569 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17570 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17571 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17572 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17573 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17574 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17575 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17576 + */
17577 +
17578 +#ifndef AR9003_MAC_H
17579 +#define AR9003_MAC_H
17580 +
17581 +#define AR_DescId 0xffff0000
17582 +#define AR_DescId_S 16
17583 +#define AR_CtrlStat 0x00004000
17584 +#define AR_CtrlStat_S 14
17585 +#define AR_TxRxDesc 0x00008000
17586 +#define AR_TxRxDesc_S 15
17587 +#define AR_TxQcuNum 0x00000f00
17588 +#define AR_TxQcuNum_S 8
17589 +#define AR_BufLen_S 16
17590 +
17591 +#define AR_TxDescId 0xffff0000
17592 +#define AR_TxDescId_S 16
17593 +#define AR_TxPtrChkSum 0x0000ffff
17594 +
17595 +#define AR_TxTid 0xf0000000
17596 +#define AR_TxTid_S 28
17597 +
17598 +#define AR_LowRxChain 0x00004000
17599 +
17600 +#define AR_Not_Sounding 0x20000000
17601 +
17602 +#define MAP_ISR_S2_CST 6
17603 +#define MAP_ISR_S2_GTT 6
17604 +#define MAP_ISR_S2_TIM 3
17605 +#define MAP_ISR_S2_CABEND 0
17606 +#define MAP_ISR_S2_DTIMSYNC 7
17607 +#define MAP_ISR_S2_DTIM 7
17608 +#define MAP_ISR_S2_TSFOOR 4
17609 +
17610 +#define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds)
17611 +
17612 +enum ath9k_rx_qtype {
17613 + ATH9K_RX_QUEUE_HP,
17614 + ATH9K_RX_QUEUE_LP,
17615 + ATH9K_RX_QUEUE_MAX,
17616 +};
17617 +
17618 +struct ar9003_rxs {
17619 + u32 ds_info;
17620 + u32 status1;
17621 + u32 status2;
17622 + u32 status3;
17623 + u32 status4;
17624 + u32 status5;
17625 + u32 status6;
17626 + u32 status7;
17627 + u32 status8;
17628 + u32 status9;
17629 + u32 status10;
17630 + u32 status11;
17631 +} __packed;
17632 +
17633 +/* Transmit Control Descriptor */
17634 +struct ar9003_txc {
17635 + u32 info; /* descriptor information */
17636 + u32 link; /* link pointer */
17637 + u32 data0; /* data pointer to 1st buffer */
17638 + u32 ctl3; /* DMA control 3 */
17639 + u32 data1; /* data pointer to 2nd buffer */
17640 + u32 ctl5; /* DMA control 5 */
17641 + u32 data2; /* data pointer to 3rd buffer */
17642 + u32 ctl7; /* DMA control 7 */
17643 + u32 data3; /* data pointer to 4th buffer */
17644 + u32 ctl9; /* DMA control 9 */
17645 + u32 ctl10; /* DMA control 10 */
17646 + u32 ctl11; /* DMA control 11 */
17647 + u32 ctl12; /* DMA control 12 */
17648 + u32 ctl13; /* DMA control 13 */
17649 + u32 ctl14; /* DMA control 14 */
17650 + u32 ctl15; /* DMA control 15 */
17651 + u32 ctl16; /* DMA control 16 */
17652 + u32 ctl17; /* DMA control 17 */
17653 + u32 ctl18; /* DMA control 18 */
17654 + u32 ctl19; /* DMA control 19 */
17655 + u32 ctl20; /* DMA control 20 */
17656 + u32 ctl21; /* DMA control 21 */
17657 + u32 ctl22; /* DMA control 22 */
17658 + u32 pad[9]; /* pad to cache line (128 bytes/32 dwords) */
17659 +} __packed;
17660 +
17661 +struct ar9003_txs {
17662 + u32 ds_info;
17663 + u32 status1;
17664 + u32 status2;
17665 + u32 status3;
17666 + u32 status4;
17667 + u32 status5;
17668 + u32 status6;
17669 + u32 status7;
17670 + u32 status8;
17671 +} __packed;
17672 +
17673 +void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
17674 +void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
17675 +void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
17676 + enum ath9k_rx_qtype qtype);
17677 +
17678 +int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah,
17679 + struct ath_rx_status *rxs,
17680 + void *buf_addr);
17681 +void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah);
17682 +void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
17683 + u32 ts_paddr_start,
17684 + u8 size);
17685 +#endif
17686 --- /dev/null
17687 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
17688 @@ -0,0 +1,1138 @@
17689 +/*
17690 + * Copyright (c) 2010 Atheros Communications Inc.
17691 + *
17692 + * Permission to use, copy, modify, and/or distribute this software for any
17693 + * purpose with or without fee is hereby granted, provided that the above
17694 + * copyright notice and this permission notice appear in all copies.
17695 + *
17696 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17697 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17698 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17699 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17700 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17701 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17702 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17703 + */
17704 +
17705 +#include "hw.h"
17706 +#include "ar9003_phy.h"
17707 +
17708 +/**
17709 + * ar9003_hw_set_channel - set channel on single-chip device
17710 + * @ah: atheros hardware structure
17711 + * @chan:
17712 + *
17713 + * This is the function to change channel on single-chip devices, that is
17714 + * all devices after ar9280.
17715 + *
17716 + * This function takes the channel value in MHz and sets
17717 + * hardware channel value. Assumes writes have been enabled to analog bus.
17718 + *
17719 + * Actual Expression,
17720 + *
17721 + * For 2GHz channel,
17722 + * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
17723 + * (freq_ref = 40MHz)
17724 + *
17725 + * For 5GHz channel,
17726 + * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
17727 + * (freq_ref = 40MHz/(24>>amodeRefSel))
17728 + *
17729 + * For 5GHz channels which are 5MHz spaced,
17730 + * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
17731 + * (freq_ref = 40MHz)
17732 + */
17733 +static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
17734 +{
17735 + u16 bMode, fracMode = 0, aModeRefSel = 0;
17736 + u32 freq, channelSel = 0, reg32 = 0;
17737 + struct chan_centers centers;
17738 + int loadSynthChannel;
17739 +
17740 + ath9k_hw_get_channel_centers(ah, chan, &centers);
17741 + freq = centers.synth_center;
17742 +
17743 + if (freq < 4800) { /* 2 GHz, fractional mode */
17744 + channelSel = CHANSEL_2G(freq);
17745 + /* Set to 2G mode */
17746 + bMode = 1;
17747 + } else {
17748 + channelSel = CHANSEL_5G(freq);
17749 + /* Doubler is ON, so, divide channelSel by 2. */
17750 + channelSel >>= 1;
17751 + /* Set to 5G mode */
17752 + bMode = 0;
17753 + }
17754 +
17755 + /* Enable fractional mode for all channels */
17756 + fracMode = 1;
17757 + aModeRefSel = 0;
17758 + loadSynthChannel = 0;
17759 +
17760 + reg32 = (bMode << 29);
17761 + REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
17762 +
17763 + /* Enable Long shift Select for Synthesizer */
17764 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
17765 + AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
17766 +
17767 + /* Program Synth. setting */
17768 + reg32 = (channelSel << 2 ) | (fracMode << 30) |
17769 + (aModeRefSel << 28) | (loadSynthChannel << 31);
17770 + REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
17771 +
17772 + /* Toggle Load Synth channel bit */
17773 + loadSynthChannel = 1;
17774 + reg32 = (channelSel << 2 ) | (fracMode << 30) |
17775 + (aModeRefSel << 28) | (loadSynthChannel << 31);
17776 + REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
17777 +
17778 + ah->curchan = chan;
17779 + ah->curchan_rad_index = -1;
17780 +
17781 + return 0;
17782 +}
17783 +
17784 +/**
17785 + * ar9003_hw_spur_mitigate - convert baseband spur frequency
17786 + * @ah: atheros hardware structure
17787 + * @chan:
17788 + *
17789 + * For single-chip solutions. Converts to baseband spur frequency given the
17790 + * input channel frequency and compute register settings below.
17791 + *
17792 + * Spur mitigation for MRC CCK
17793 + */
17794 +static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
17795 + struct ath9k_channel *chan)
17796 +{
17797 + u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
17798 + int cur_bb_spur, negative = 0, cck_spur_freq;
17799 + int i;
17800 +
17801 + /*
17802 + * Need to verify range +/- 10 MHz in control channel, otherwise spur
17803 + * is out-of-band and can be ignored.
17804 + */
17805 +
17806 + for (i = 0; i < 4; i++) {
17807 + negative = 0;
17808 + cur_bb_spur = spur_freq[i] - chan->channel;
17809 +
17810 + if(cur_bb_spur < 0) {
17811 + negative = 1;
17812 + cur_bb_spur = -cur_bb_spur;
17813 + }
17814 + if (cur_bb_spur < 10) {
17815 + cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
17816 +
17817 + if (negative == 1)
17818 + cck_spur_freq = -cck_spur_freq;
17819 +
17820 + cck_spur_freq = cck_spur_freq & 0xfffff;
17821 +
17822 + REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
17823 + AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
17824 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
17825 + AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
17826 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
17827 + AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 0x2);
17828 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
17829 + AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x1);
17830 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
17831 + AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, cck_spur_freq);
17832 +
17833 + return;
17834 + }
17835 + }
17836 +
17837 + REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
17838 + AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
17839 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
17840 + AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
17841 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
17842 + AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
17843 +}
17844 +
17845 +/* Clean all spur register fields */
17846 +static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
17847 +{
17848 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17849 + AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
17850 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17851 + AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
17852 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17853 + AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
17854 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
17855 + AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
17856 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17857 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
17858 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17859 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
17860 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17861 + AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
17862 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17863 + AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
17864 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17865 + AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
17866 +
17867 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17868 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
17869 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17870 + AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
17871 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17872 + AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
17873 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
17874 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
17875 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
17876 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
17877 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
17878 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
17879 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
17880 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
17881 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
17882 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
17883 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
17884 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
17885 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17886 + AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
17887 +}
17888 +
17889 +static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
17890 + int freq_offset,
17891 + int spur_freq_sd,
17892 + int spur_delta_phase,
17893 + int spur_subchannel_sd)
17894 +{
17895 + int mask_index = 0;
17896 +
17897 + /* OFDM Spur mitigation */
17898 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17899 + AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
17900 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17901 + AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
17902 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17903 + AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
17904 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
17905 + AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
17906 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17907 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
17908 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17909 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
17910 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17911 + AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
17912 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17913 + AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
17914 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17915 + AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
17916 +
17917 + if (REG_READ_FIELD(ah, AR_PHY_MODE,
17918 + AR_PHY_MODE_DYNAMIC) == 0x1)
17919 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17920 + AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
17921 +
17922 + mask_index = (freq_offset << 4) / 5;
17923 + if (mask_index < 0)
17924 + mask_index = mask_index - 1;
17925 +
17926 + mask_index = mask_index & 0x7f;
17927 +
17928 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17929 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
17930 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17931 + AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
17932 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17933 + AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
17934 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
17935 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
17936 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
17937 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
17938 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
17939 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
17940 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
17941 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
17942 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
17943 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
17944 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
17945 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
17946 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17947 + AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
17948 +}
17949 +
17950 +static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
17951 + struct ath9k_channel *chan,
17952 + int freq_offset)
17953 +{
17954 + int spur_freq_sd = 0;
17955 + int spur_subchannel_sd = 0;
17956 + int spur_delta_phase = 0;
17957 +
17958 + if (IS_CHAN_HT40(chan)) {
17959 + if (freq_offset < 0) {
17960 + if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
17961 + AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
17962 + spur_subchannel_sd = 1;
17963 + else
17964 + spur_subchannel_sd = 0;
17965 +
17966 + spur_freq_sd = ((freq_offset + 10) << 9) / 11;
17967 +
17968 + } else {
17969 + if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
17970 + AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
17971 + spur_subchannel_sd = 0;
17972 + else
17973 + spur_subchannel_sd = 1;
17974 +
17975 + spur_freq_sd = ((freq_offset - 10) << 9) / 11;
17976 +
17977 + }
17978 +
17979 + spur_delta_phase = (freq_offset << 17) / 5;
17980 +
17981 + } else {
17982 + spur_subchannel_sd = 0;
17983 + spur_freq_sd = (freq_offset << 9) /11;
17984 + spur_delta_phase = (freq_offset << 18) / 5;
17985 + }
17986 +
17987 + spur_freq_sd = spur_freq_sd & 0x3ff;
17988 + spur_delta_phase = spur_delta_phase & 0xfffff;
17989 +
17990 + ar9003_hw_spur_ofdm(ah,
17991 + freq_offset,
17992 + spur_freq_sd,
17993 + spur_delta_phase,
17994 + spur_subchannel_sd);
17995 +}
17996 +
17997 +/* Spur mitigation for OFDM */
17998 +static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
17999 + struct ath9k_channel *chan)
18000 +{
18001 + int synth_freq;
18002 + int range = 10;
18003 + int freq_offset = 0;
18004 + int mode;
18005 + u8* spurChansPtr;
18006 + unsigned int i;
18007 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
18008 +
18009 + if (IS_CHAN_5GHZ(chan)) {
18010 + spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
18011 + mode = 0;
18012 + }
18013 + else {
18014 + spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
18015 + mode = 1;
18016 + }
18017 +
18018 + if (spurChansPtr[0] == 0)
18019 + return; /* No spur in the mode */
18020 +
18021 + if (IS_CHAN_HT40(chan)) {
18022 + range = 19;
18023 + if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
18024 + AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
18025 + synth_freq = chan->channel - 10;
18026 + else
18027 + synth_freq = chan->channel + 10;
18028 + } else {
18029 + range = 10;
18030 + synth_freq = chan->channel;
18031 + }
18032 +
18033 + ar9003_hw_spur_ofdm_clear(ah);
18034 +
18035 + for (i = 0; spurChansPtr[i] && i < 5; i++) {
18036 + freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
18037 + if (abs(freq_offset) < range) {
18038 + ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
18039 + break;
18040 + }
18041 + }
18042 +}
18043 +
18044 +static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
18045 + struct ath9k_channel *chan)
18046 +{
18047 + ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
18048 + ar9003_hw_spur_mitigate_ofdm(ah, chan);
18049 +}
18050 +
18051 +static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
18052 + struct ath9k_channel *chan)
18053 +{
18054 + u32 pll;
18055 +
18056 + pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
18057 +
18058 + if (chan && IS_CHAN_HALF_RATE(chan))
18059 + pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
18060 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
18061 + pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
18062 +
18063 + if (chan && IS_CHAN_5GHZ(chan)) {
18064 + pll |= SM(0x28, AR_RTC_9300_PLL_DIV);
18065 +
18066 + /*
18067 + * When doing fast clock, set PLL to 0x142c
18068 + */
18069 + if (IS_CHAN_A_5MHZ_SPACED(chan))
18070 + pll = 0x142c;
18071 + } else
18072 + pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
18073 +
18074 + return pll;
18075 +}
18076 +
18077 +static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
18078 + struct ath9k_channel *chan)
18079 +{
18080 + u32 phymode;
18081 + u32 enableDacFifo = 0;
18082 +
18083 + enableDacFifo =
18084 + (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
18085 +
18086 + /* Enable 11n HT, 20 MHz */
18087 + phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
18088 + AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
18089 +
18090 + /* Configure baseband for dynamic 20/40 operation */
18091 + if (IS_CHAN_HT40(chan)) {
18092 + phymode |= AR_PHY_GC_DYN2040_EN;
18093 + /* Configure control (primary) channel at +-10MHz */
18094 + if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
18095 + (chan->chanmode == CHANNEL_G_HT40PLUS))
18096 + phymode |= AR_PHY_GC_DYN2040_PRI_CH;
18097 +
18098 + }
18099 +
18100 + /* make sure we preserve INI settings */
18101 + phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
18102 + /* turn off Green Field detection for STA for now */
18103 + phymode &= ~AR_PHY_GC_GF_DETECT_EN;
18104 +
18105 + REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
18106 +
18107 + /* Configure MAC for 20/40 operation */
18108 + ath9k_hw_set11nmac2040(ah);
18109 +
18110 + /* global transmit timeout (25 TUs default)*/
18111 + REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
18112 + /* carrier sense timeout */
18113 + REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
18114 +}
18115 +
18116 +static void ar9003_hw_init_bb(struct ath_hw *ah,
18117 + struct ath9k_channel *chan)
18118 +{
18119 + u32 synthDelay;
18120 +
18121 + /*
18122 + * Wait for the frequency synth to settle (synth goes on
18123 + * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
18124 + * Value is in 100ns increments.
18125 + */
18126 + synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
18127 + if (IS_CHAN_B(chan))
18128 + synthDelay = (4 * synthDelay) / 22;
18129 + else
18130 + synthDelay /= 10;
18131 +
18132 + /* Activate the PHY (includes baseband activate + synthesizer on) */
18133 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
18134 +
18135 + /*
18136 + * There is an issue if the AP starts the calibration before
18137 + * the base band timeout completes. This could result in the
18138 + * rx_clear false triggering. As a workaround we add delay an
18139 + * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
18140 + * does not happen.
18141 + */
18142 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
18143 +}
18144 +
18145 +void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
18146 +{
18147 + switch (rx) {
18148 + case 0x5:
18149 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
18150 + AR_PHY_SWAP_ALT_CHAIN);
18151 + case 0x3:
18152 + case 0x1:
18153 + case 0x2:
18154 + case 0x7:
18155 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
18156 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
18157 + break;
18158 + default:
18159 + break;
18160 + }
18161 +
18162 + REG_WRITE(ah, AR_SELFGEN_MASK, tx);
18163 + if (tx == 0x5) {
18164 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
18165 + AR_PHY_SWAP_ALT_CHAIN);
18166 + }
18167 +}
18168 +
18169 +/*
18170 + * Override INI values with chip specific configuration.
18171 + */
18172 +static void ar9003_hw_override_ini(struct ath_hw *ah)
18173 +{
18174 + u32 val;
18175 +
18176 + /*
18177 + * Set the RX_ABORT and RX_DIS and clear it only after
18178 + * RXE is set for MAC. This prevents frames with
18179 + * corrupted descriptor status.
18180 + */
18181 + REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
18182 +
18183 + /*
18184 + * For AR9280 and above, there is a new feature that allows
18185 + * Multicast search based on both MAC Address and Key ID. By default,
18186 + * this feature is enabled. But since the driver is not using this
18187 + * feature, we switch it off; otherwise multicast search based on
18188 + * MAC addr only will fail.
18189 + */
18190 + val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
18191 + REG_WRITE(ah, AR_PCU_MISC_MODE2, val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
18192 +}
18193 +
18194 +static void ar9003_hw_prog_ini(struct ath_hw *ah,
18195 + struct ar5416IniArray *iniArr,
18196 + int column)
18197 +{
18198 + unsigned int i, regWrites = 0;
18199 +
18200 + /* New INI format: Array may be undefined (pre, core, post arrays) */
18201 + if (!iniArr->ia_array)
18202 + return;
18203 +
18204 + /*
18205 + * New INI format: Pre, core, and post arrays for a given subsystem
18206 + * may be modal (> 2 columns) or non-modal (2 columns). Determine if
18207 + * the array is non-modal and force the column to 1.
18208 + */
18209 + if (column >= iniArr->ia_columns)
18210 + column = 1;
18211 +
18212 + for (i = 0; i < iniArr->ia_rows; i++) {
18213 + u32 reg = INI_RA(iniArr, i, 0);
18214 + u32 val = INI_RA(iniArr, i, column);
18215 +
18216 + REG_WRITE(ah, reg, val);
18217 +
18218 + /*
18219 + * Determine if this is a shift register value, and insert the
18220 + * configured delay if so.
18221 + */
18222 + if (reg >= 0x16000 && reg < 0x17000
18223 + && ah->config.analog_shiftreg)
18224 + udelay(100);
18225 +
18226 + DO_DELAY(regWrites);
18227 + }
18228 +}
18229 +
18230 +static int ar9003_hw_process_ini(struct ath_hw *ah,
18231 + struct ath9k_channel *chan)
18232 +{
18233 + struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
18234 + unsigned int regWrites = 0, i;
18235 + struct ieee80211_channel *channel = chan->chan;
18236 + u32 modesIndex, freqIndex;
18237 +
18238 + switch (chan->chanmode) {
18239 + case CHANNEL_A:
18240 + case CHANNEL_A_HT20:
18241 + modesIndex = 1;
18242 + freqIndex = 1;
18243 + break;
18244 + case CHANNEL_A_HT40PLUS:
18245 + case CHANNEL_A_HT40MINUS:
18246 + modesIndex = 2;
18247 + freqIndex = 1;
18248 + break;
18249 + case CHANNEL_G:
18250 + case CHANNEL_G_HT20:
18251 + case CHANNEL_B:
18252 + modesIndex = 4;
18253 + freqIndex = 2;
18254 + break;
18255 + case CHANNEL_G_HT40PLUS:
18256 + case CHANNEL_G_HT40MINUS:
18257 + modesIndex = 3;
18258 + freqIndex = 2;
18259 + break;
18260 +
18261 + default:
18262 + return -EINVAL;
18263 + }
18264 +
18265 + for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
18266 + ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
18267 + ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
18268 + ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
18269 + ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
18270 + }
18271 +
18272 + REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
18273 + REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
18274 +
18275 + /*
18276 + * For 5GHz channels requiring Fast Clock, apply
18277 + * different modal values.
18278 + */
18279 + if (IS_CHAN_A_5MHZ_SPACED(chan))
18280 + REG_WRITE_ARRAY(&ah->iniModesAdditional,
18281 + modesIndex, regWrites);
18282 +
18283 + ar9003_hw_override_ini(ah);
18284 + ar9003_hw_set_channel_regs(ah, chan);
18285 + ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
18286 +
18287 + /* Set TX power */
18288 + ah->eep_ops->set_txpower(ah, chan,
18289 + ath9k_regd_get_ctl(regulatory, chan),
18290 + channel->max_antenna_gain * 2,
18291 + channel->max_power * 2,
18292 + min((u32) MAX_RATE_POWER,
18293 + (u32) regulatory->power_limit));
18294 +
18295 + return 0;
18296 +}
18297 +
18298 +static void ar9003_hw_set_rfmode(struct ath_hw *ah,
18299 + struct ath9k_channel *chan)
18300 +{
18301 + u32 rfMode = 0;
18302 +
18303 + if (chan == NULL)
18304 + return;
18305 +
18306 + rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
18307 + ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
18308 +
18309 + if (IS_CHAN_A_5MHZ_SPACED(chan))
18310 + rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
18311 +
18312 + REG_WRITE(ah, AR_PHY_MODE, rfMode);
18313 +}
18314 +
18315 +static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
18316 +{
18317 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
18318 +}
18319 +
18320 +static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
18321 + struct ath9k_channel *chan)
18322 +{
18323 + u32 coef_scaled, ds_coef_exp, ds_coef_man;
18324 + u32 clockMhzScaled = 0x64000000;
18325 + struct chan_centers centers;
18326 +
18327 + /*
18328 + * half and quarter rate can divide the scaled clock by 2 or 4
18329 + * scale for selected channel bandwidth
18330 + */
18331 + if (IS_CHAN_HALF_RATE(chan))
18332 + clockMhzScaled = clockMhzScaled >> 1;
18333 + else if (IS_CHAN_QUARTER_RATE(chan))
18334 + clockMhzScaled = clockMhzScaled >> 2;
18335 +
18336 + /*
18337 + * ALGO -> coef = 1e8/fcarrier*fclock/40;
18338 + * scaled coef to provide precision for this floating calculation
18339 + */
18340 + ath9k_hw_get_channel_centers(ah, chan, &centers);
18341 + coef_scaled = clockMhzScaled / centers.synth_center;
18342 +
18343 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
18344 + &ds_coef_exp);
18345 +
18346 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
18347 + AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
18348 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
18349 + AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
18350 +
18351 + /*
18352 + * For Short GI,
18353 + * scaled coeff is 9/10 that of normal coeff
18354 + */
18355 + coef_scaled = (9 * coef_scaled) / 10;
18356 +
18357 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
18358 + &ds_coef_exp);
18359 +
18360 + /* for short gi */
18361 + REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
18362 + AR_PHY_SGI_DSC_MAN, ds_coef_man);
18363 + REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
18364 + AR_PHY_SGI_DSC_EXP, ds_coef_exp);
18365 +}
18366 +
18367 +static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
18368 +{
18369 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
18370 + return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
18371 + AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
18372 +}
18373 +
18374 +/*
18375 + * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
18376 + * Read the phy active delay register. Value is in 100ns increments.
18377 + */
18378 +static void ar9003_hw_rfbus_done(struct ath_hw *ah)
18379 +{
18380 + u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
18381 + if (IS_CHAN_B(ah->curchan))
18382 + synthDelay = (4 * synthDelay) / 22;
18383 + else
18384 + synthDelay /= 10;
18385 +
18386 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
18387 +
18388 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
18389 +}
18390 +
18391 +/*
18392 + * Set the interrupt and GPIO values so the ISR can disable RF
18393 + * on a switch signal. Assumes GPIO port and interrupt polarity
18394 + * are set prior to call.
18395 + */
18396 +static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
18397 +{
18398 + /* Connect rfsilent_bb_l to baseband */
18399 + REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
18400 + AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
18401 + /* Set input mux for rfsilent_bb_l to GPIO #0 */
18402 + REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
18403 + AR_GPIO_INPUT_MUX2_RFSILENT);
18404 +
18405 + /*
18406 + * Configure the desired GPIO port for input and
18407 + * enable baseband rf silence.
18408 + */
18409 + ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
18410 + REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
18411 +}
18412 +
18413 +static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
18414 +{
18415 + u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
18416 + if (value)
18417 + v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
18418 + else
18419 + v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
18420 + REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
18421 +}
18422 +
18423 +static bool ar9003_hw_ani_control(struct ath_hw *ah,
18424 + enum ath9k_ani_cmd cmd, int param)
18425 +{
18426 + struct ar5416AniState *aniState = ah->curani;
18427 + struct ath_common *common = ath9k_hw_common(ah);
18428 +
18429 + switch (cmd & ah->ani_function) {
18430 + case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
18431 + u32 level = param;
18432 +
18433 + if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
18434 + ath_print(common, ATH_DBG_ANI,
18435 + "level out of range (%u > %u)\n",
18436 + level,
18437 + (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
18438 + return false;
18439 + }
18440 +
18441 + REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
18442 + AR_PHY_DESIRED_SZ_TOT_DES,
18443 + ah->totalSizeDesired[level]);
18444 + REG_RMW_FIELD(ah, AR_PHY_AGC,
18445 + AR_PHY_AGC_COARSE_LOW,
18446 + ah->coarse_low[level]);
18447 + REG_RMW_FIELD(ah, AR_PHY_AGC,
18448 + AR_PHY_AGC_COARSE_HIGH,
18449 + ah->coarse_high[level]);
18450 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
18451 + AR_PHY_FIND_SIG_FIRPWR, ah->firpwr[level]);
18452 +
18453 + if (level > aniState->noiseImmunityLevel)
18454 + ah->stats.ast_ani_niup++;
18455 + else if (level < aniState->noiseImmunityLevel)
18456 + ah->stats.ast_ani_nidown++;
18457 + aniState->noiseImmunityLevel = level;
18458 + break;
18459 + }
18460 + case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
18461 + const int m1ThreshLow[] = { 127, 50 };
18462 + const int m2ThreshLow[] = { 127, 40 };
18463 + const int m1Thresh[] = { 127, 0x4d };
18464 + const int m2Thresh[] = { 127, 0x40 };
18465 + const int m2CountThr[] = { 31, 16 };
18466 + const int m2CountThrLow[] = { 63, 48 };
18467 + u32 on = param ? 1 : 0;
18468 +
18469 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
18470 + AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
18471 + m1ThreshLow[on]);
18472 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
18473 + AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
18474 + m2ThreshLow[on]);
18475 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
18476 + AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
18477 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
18478 + AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
18479 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
18480 + AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
18481 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
18482 + AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2CountThrLow[on]);
18483 +
18484 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
18485 + AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);
18486 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
18487 + AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);
18488 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
18489 + AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);
18490 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
18491 + AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);
18492 +
18493 + if (on)
18494 + REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
18495 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
18496 + else
18497 + REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
18498 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
18499 +
18500 + if (!on != aniState->ofdmWeakSigDetectOff) {
18501 + if (on)
18502 + ah->stats.ast_ani_ofdmon++;
18503 + else
18504 + ah->stats.ast_ani_ofdmoff++;
18505 + aniState->ofdmWeakSigDetectOff = !on;
18506 + }
18507 + break;
18508 + }
18509 + case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
18510 + const int weakSigThrCck[] = { 8, 6 };
18511 + u32 high = param ? 1 : 0;
18512 +
18513 + REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
18514 + AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
18515 + weakSigThrCck[high]);
18516 + if (high != aniState->cckWeakSigThreshold) {
18517 + if (high)
18518 + ah->stats.ast_ani_cckhigh++;
18519 + else
18520 + ah->stats.ast_ani_ccklow++;
18521 + aniState->cckWeakSigThreshold = high;
18522 + }
18523 + break;
18524 + }
18525 + case ATH9K_ANI_FIRSTEP_LEVEL:{
18526 + const int firstep[] = { 0, 4, 8 };
18527 + u32 level = param;
18528 +
18529 + if (level >= ARRAY_SIZE(firstep)) {
18530 + ath_print(common, ATH_DBG_ANI,
18531 + "level out of range (%u > %u)\n",
18532 + level,
18533 + (unsigned) ARRAY_SIZE(firstep));
18534 + return false;
18535 + }
18536 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
18537 + AR_PHY_FIND_SIG_FIRSTEP,
18538 + firstep[level]);
18539 + if (level > aniState->firstepLevel)
18540 + ah->stats.ast_ani_stepup++;
18541 + else if (level < aniState->firstepLevel)
18542 + ah->stats.ast_ani_stepdown++;
18543 + aniState->firstepLevel = level;
18544 + break;
18545 + }
18546 + case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
18547 + const int cycpwrThr1[] =
18548 + { 2, 4, 6, 8, 10, 12, 14, 16 };
18549 + u32 level = param;
18550 +
18551 + if (level >= ARRAY_SIZE(cycpwrThr1)) {
18552 + ath_print(common, ATH_DBG_ANI,
18553 + "level out of range (%u > %u)\n",
18554 + level,
18555 + (unsigned) ARRAY_SIZE(cycpwrThr1));
18556 + return false;
18557 + }
18558 + REG_RMW_FIELD(ah, AR_PHY_TIMING5,
18559 + AR_PHY_TIMING5_CYCPWR_THR1,
18560 + cycpwrThr1[level]);
18561 + if (level > aniState->spurImmunityLevel)
18562 + ah->stats.ast_ani_spurup++;
18563 + else if (level < aniState->spurImmunityLevel)
18564 + ah->stats.ast_ani_spurdown++;
18565 + aniState->spurImmunityLevel = level;
18566 + break;
18567 + }
18568 + case ATH9K_ANI_PRESENT:
18569 + break;
18570 + default:
18571 + ath_print(common, ATH_DBG_ANI,
18572 + "invalid cmd %u\n", cmd);
18573 + return false;
18574 + }
18575 +
18576 + ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
18577 + ath_print(common, ATH_DBG_ANI,
18578 + "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
18579 + "ofdmWeakSigDetectOff=%d\n",
18580 + aniState->noiseImmunityLevel,
18581 + aniState->spurImmunityLevel,
18582 + !aniState->ofdmWeakSigDetectOff);
18583 + ath_print(common, ATH_DBG_ANI,
18584 + "cckWeakSigThreshold=%d, "
18585 + "firstepLevel=%d, listenTime=%d\n",
18586 + aniState->cckWeakSigThreshold,
18587 + aniState->firstepLevel,
18588 + aniState->listenTime);
18589 + ath_print(common, ATH_DBG_ANI,
18590 + "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
18591 + aniState->cycleCount,
18592 + aniState->ofdmPhyErrCount,
18593 + aniState->cckPhyErrCount);
18594 +
18595 + return true;
18596 +}
18597 +
18598 +static void ar9003_hw_nf_sanitize_2g(struct ath_hw *ah, s16 *nf)
18599 +{
18600 + struct ath_common *common = ath9k_hw_common(ah);
18601 +
18602 + if (*nf > ah->nf_2g_max) {
18603 + ath_print(common, ATH_DBG_CALIBRATE,
18604 + "2 GHz NF (%d) > MAX (%d), "
18605 + "correcting to MAX",
18606 + *nf, ah->nf_2g_max);
18607 + *nf = ah->nf_2g_max;
18608 + } else if (*nf < ah->nf_2g_min) {
18609 + ath_print(common, ATH_DBG_CALIBRATE,
18610 + "2 GHz NF (%d) < MIN (%d), "
18611 + "correcting to MIN",
18612 + *nf, ah->nf_2g_min);
18613 + *nf = ah->nf_2g_min;
18614 + }
18615 +}
18616 +
18617 +static void ar9003_hw_nf_sanitize_5g(struct ath_hw *ah, s16 *nf)
18618 +{
18619 + struct ath_common *common = ath9k_hw_common(ah);
18620 +
18621 + if (*nf > ah->nf_5g_max) {
18622 + ath_print(common, ATH_DBG_CALIBRATE,
18623 + "5 GHz NF (%d) > MAX (%d), "
18624 + "correcting to MAX",
18625 + *nf, ah->nf_5g_max);
18626 + *nf = ah->nf_5g_max;
18627 + } else if (*nf < ah->nf_5g_min) {
18628 + ath_print(common, ATH_DBG_CALIBRATE,
18629 + "5 GHz NF (%d) < MIN (%d), "
18630 + "correcting to MIN",
18631 + *nf, ah->nf_5g_min);
18632 + *nf = ah->nf_5g_min;
18633 + }
18634 +}
18635 +
18636 +static void ar9003_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
18637 +{
18638 + if (IS_CHAN_2GHZ(ah->curchan))
18639 + ar9003_hw_nf_sanitize_2g(ah, nf);
18640 + else
18641 + ar9003_hw_nf_sanitize_5g(ah, nf);
18642 +}
18643 +
18644 +static void ar9003_hw_do_getnf(struct ath_hw *ah,
18645 + int16_t nfarray[NUM_NF_READINGS])
18646 +{
18647 + struct ath_common *common = ath9k_hw_common(ah);
18648 + int16_t nf;
18649 +
18650 + nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
18651 + if (nf & 0x100)
18652 + nf = 0 - ((nf ^ 0x1ff) + 1);
18653 + ar9003_hw_nf_sanitize(ah, &nf);
18654 + ath_print(common, ATH_DBG_CALIBRATE,
18655 + "NF calibrated [ctl] [chain 0] is %d\n", nf);
18656 + nfarray[0] = nf;
18657 +
18658 + nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
18659 + if (nf & 0x100)
18660 + nf = 0 - ((nf ^ 0x1ff) + 1);
18661 + ar9003_hw_nf_sanitize(ah, &nf);
18662 + ath_print(common, ATH_DBG_CALIBRATE,
18663 + "NF calibrated [ctl] [chain 1] is %d\n", nf);
18664 + nfarray[1] = nf;
18665 +
18666 + nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
18667 + if (nf & 0x100)
18668 + nf = 0 - ((nf ^ 0x1ff) + 1);
18669 + ar9003_hw_nf_sanitize(ah, &nf);
18670 + ath_print(common, ATH_DBG_CALIBRATE,
18671 + "NF calibrated [ctl] [chain 2] is %d\n", nf);
18672 + nfarray[2] = nf;
18673 +
18674 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
18675 + if (nf & 0x100)
18676 + nf = 0 - ((nf ^ 0x1ff) + 1);
18677 + ar9003_hw_nf_sanitize(ah, &nf);
18678 + ath_print(common, ATH_DBG_CALIBRATE,
18679 + "NF calibrated [ext] [chain 0] is %d\n", nf);
18680 + nfarray[3] = nf;
18681 +
18682 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
18683 + if (nf & 0x100)
18684 + nf = 0 - ((nf ^ 0x1ff) + 1);
18685 + ar9003_hw_nf_sanitize(ah, &nf);
18686 + ath_print(common, ATH_DBG_CALIBRATE,
18687 + "NF calibrated [ext] [chain 1] is %d\n", nf);
18688 + nfarray[4] = nf;
18689 +
18690 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
18691 + if (nf & 0x100)
18692 + nf = 0 - ((nf ^ 0x1ff) + 1);
18693 + ar9003_hw_nf_sanitize(ah, &nf);
18694 + ath_print(common, ATH_DBG_CALIBRATE,
18695 + "NF calibrated [ext] [chain 2] is %d\n", nf);
18696 + nfarray[5] = nf;
18697 +}
18698 +
18699 +void ar9003_hw_set_nf_limits(struct ath_hw *ah)
18700 +{
18701 + ah->nf_2g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
18702 + ah->nf_2g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
18703 + ah->nf_5g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
18704 + ah->nf_5g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
18705 +}
18706 +
18707 +/*
18708 + * Find out which of the RX chains are enabled
18709 + */
18710 +static u32 ar9003_hw_get_rx_chainmask(struct ath_hw *ah)
18711 +{
18712 + u32 chain = REG_READ(ah, AR_PHY_RX_CHAINMASK);
18713 + /*
18714 + * The bits [2:0] indicate the rx chain mask and are to be
18715 + * interpreted as follows:
18716 + * 00x => Only chain 0 is enabled
18717 + * 01x => Chain 1 and 0 enabled
18718 + * 1xx => Chain 2,1 and 0 enabled
18719 + */
18720 + return (chain & 0x7);
18721 +}
18722 +
18723 +static void ar9003_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
18724 +{
18725 + struct ath9k_nfcal_hist *h;
18726 + unsigned i, j;
18727 + int32_t val;
18728 + const u32 ar9300_cca_regs[6] = {
18729 + AR_PHY_CCA_0,
18730 + AR_PHY_CCA_1,
18731 + AR_PHY_CCA_2,
18732 + AR_PHY_EXT_CCA,
18733 + AR_PHY_EXT_CCA_1,
18734 + AR_PHY_EXT_CCA_2,
18735 + };
18736 + u8 chainmask, rx_chain_status;
18737 + struct ath_common *common = ath9k_hw_common(ah);
18738 +
18739 + rx_chain_status = ar9003_hw_get_rx_chainmask(ah);
18740 +
18741 + chainmask = 0x3F;
18742 + h = ah->nfCalHist;
18743 +
18744 + for (i = 0; i < NUM_NF_READINGS; i++) {
18745 + if (chainmask & (1 << i)) {
18746 + val = REG_READ(ah, ar9300_cca_regs[i]);
18747 + val &= 0xFFFFFE00;
18748 + val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
18749 + REG_WRITE(ah, ar9300_cca_regs[i], val);
18750 + }
18751 + }
18752 +
18753 + /*
18754 + * Load software filtered NF value into baseband internal minCCApwr
18755 + * variable.
18756 + */
18757 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
18758 + AR_PHY_AGC_CONTROL_ENABLE_NF);
18759 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
18760 + AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
18761 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
18762 +
18763 + /*
18764 + * Wait for load to complete, should be fast, a few 10s of us.
18765 + * The max delay was changed from an original 250us to 10000us
18766 + * since 250us often results in NF load timeout and causes deaf
18767 + * condition during stress testing 12/12/2009
18768 + */
18769 + for (j = 0; j < 1000; j++) {
18770 + if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
18771 + AR_PHY_AGC_CONTROL_NF) == 0)
18772 + break;
18773 + udelay(10);
18774 + }
18775 +
18776 + /*
18777 + * We timed out waiting for the noisefloor to load, probably due to an
18778 + * in-progress rx. Simply return here and allow the load plenty of time
18779 + * to complete before the next calibration interval. We need to avoid
18780 + * trying to load -50 (which happens below) while the previous load is
18781 + * still in progress as this can cause rx deafness. Instead by returning
18782 + * here, the baseband nf cal will just be capped by our present
18783 + * noisefloor until the next calibration timer.
18784 + */
18785 + if (j == 1000) {
18786 + ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf "
18787 + "to load: AR_PHY_AGC_CONTROL=0x%x\n",
18788 + REG_READ(ah, AR_PHY_AGC_CONTROL));
18789 + }
18790 +
18791 + /*
18792 + * Restore maxCCAPower register parameter again so that we're not capped
18793 + * by the median we just loaded. This will be initial (and max) value
18794 + * of next noise floor calibration the baseband does.
18795 + */
18796 + for (i = 0; i < NUM_NF_READINGS; i++) {
18797 + if (chainmask & (1 << i)) {
18798 + val = REG_READ(ah, ar9300_cca_regs[i]);
18799 + val &= 0xFFFFFE00;
18800 + val |= (((u32) (-50) << 1) & 0x1ff);
18801 + REG_WRITE(ah, ar9300_cca_regs[i], val);
18802 + }
18803 + }
18804 +}
18805 +
18806 +void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
18807 +{
18808 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
18809 +
18810 + priv_ops->rf_set_freq = ar9003_hw_set_channel;
18811 + priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
18812 + priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
18813 + priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
18814 + priv_ops->init_bb = ar9003_hw_init_bb;
18815 + priv_ops->process_ini = ar9003_hw_process_ini;
18816 + priv_ops->set_rfmode = ar9003_hw_set_rfmode;
18817 + priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
18818 + priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
18819 + priv_ops->rfbus_req = ar9003_hw_rfbus_req;
18820 + priv_ops->rfbus_done = ar9003_hw_rfbus_done;
18821 + priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
18822 + priv_ops->set_diversity = ar9003_hw_set_diversity;
18823 + priv_ops->ani_control = ar9003_hw_ani_control;
18824 + priv_ops->do_getnf = ar9003_hw_do_getnf;
18825 + priv_ops->loadnf = ar9003_hw_loadnf;
18826 +}
18827 --- /dev/null
18828 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
18829 @@ -0,0 +1,847 @@
18830 +/*
18831 + * Copyright (c) 2002-2010 Atheros Communications, Inc.
18832 + *
18833 + * Permission to use, copy, modify, and/or distribute this software for any
18834 + * purpose with or without fee is hereby granted, provided that the above
18835 + * copyright notice and this permission notice appear in all copies.
18836 + *
18837 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
18838 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
18839 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
18840 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18841 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18842 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18843 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18844 + */
18845 +
18846 +#ifndef AR9003_PHY_H
18847 +#define AR9003_PHY_H
18848 +
18849 +/*
18850 + * Channel Register Map
18851 + */
18852 +#define AR_CHAN_BASE 0x9800
18853 +
18854 +#define AR_PHY_TIMING1 AR_CHAN_BASE + 0x0
18855 +#define AR_PHY_TIMING2 AR_CHAN_BASE + 0x4
18856 +#define AR_PHY_TIMING3 AR_CHAN_BASE + 0x8
18857 +#define AR_PHY_TIMING4 AR_CHAN_BASE + 0xc
18858 +#define AR_PHY_TIMING5 AR_CHAN_BASE + 0x10
18859 +#define AR_PHY_TIMING6 AR_CHAN_BASE + 0x14
18860 +#define AR_PHY_TIMING11 AR_CHAN_BASE + 0x18
18861 +#define AR_PHY_SPUR_REG AR_CHAN_BASE + 0x1c
18862 +#define AR_PHY_RX_IQCAL_CORR_B0 AR_CHAN_BASE + 0xdc
18863 +#define AR_PHY_TX_IQCAL_CONTROL_3 AR_CHAN_BASE + 0xb0
18864 +
18865 +#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
18866 +#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
18867 +
18868 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
18869 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
18870 +
18871 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
18872 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30
18873 +
18874 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
18875 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31
18876 +
18877 +#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
18878 +#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 26
18879 +
18880 +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
18881 +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 17
18882 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
18883 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
18884 +#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
18885 +#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 8
18886 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000
18887 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
18888 +
18889 +#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000
18890 +#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29
18891 +
18892 +#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000
18893 +#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31
18894 +
18895 +#define AR_PHY_FIND_SIG_LOW AR_CHAN_BASE + 0x20
18896 +
18897 +#define AR_PHY_SFCORR AR_CHAN_BASE + 0x24
18898 +#define AR_PHY_SFCORR_LOW AR_CHAN_BASE + 0x28
18899 +#define AR_PHY_SFCORR_EXT AR_CHAN_BASE + 0x2c
18900 +
18901 +#define AR_PHY_EXT_CCA AR_CHAN_BASE + 0x30
18902 +#define AR_PHY_RADAR_0 AR_CHAN_BASE + 0x34
18903 +#define AR_PHY_RADAR_1 AR_CHAN_BASE + 0x38
18904 +#define AR_PHY_RADAR_EXT AR_CHAN_BASE + 0x3c
18905 +#define AR_PHY_MULTICHAIN_CTRL AR_CHAN_BASE + 0x80
18906 +#define AR_PHY_PERCHAIN_CSD AR_CHAN_BASE + 0x84
18907 +
18908 +#define AR_PHY_TX_PHASE_RAMP_0 AR_CHAN_BASE + 0xd0
18909 +#define AR_PHY_ADC_GAIN_DC_CORR_0 AR_CHAN_BASE + 0xd4
18910 +#define AR_PHY_IQ_ADC_MEAS_0_B0 AR_CHAN_BASE + 0xc0
18911 +#define AR_PHY_IQ_ADC_MEAS_1_B0 AR_CHAN_BASE + 0xc4
18912 +#define AR_PHY_IQ_ADC_MEAS_2_B0 AR_CHAN_BASE + 0xc8
18913 +#define AR_PHY_IQ_ADC_MEAS_3_B0 AR_CHAN_BASE + 0xcc
18914 +
18915 +/* The following registers changed position from AR9300 1.0 to AR9300 2.0 */
18916 +#define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10)
18917 +#define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 (AR_CHAN_BASE + 0xd4 - 0x10)
18918 +#define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 (AR_CHAN_BASE + 0xc0 + 0x8)
18919 +#define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 (AR_CHAN_BASE + 0xc4 + 0x8)
18920 +#define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 (AR_CHAN_BASE + 0xc8 + 0x8)
18921 +#define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 (AR_CHAN_BASE + 0xcc + 0x8)
18922 +
18923 +#define AR_PHY_TX_CRC AR_CHAN_BASE + 0xa0
18924 +#define AR_PHY_TST_DAC_CONST AR_CHAN_BASE + 0xa4
18925 +#define AR_PHY_SPUR_REPORT_0 AR_CHAN_BASE + 0xa8
18926 +#define AR_PHY_CHAN_INFO_TAB_0 AR_CHAN_BASE + 0x300
18927 +
18928 +/*
18929 + * Channel Field Definitions
18930 + */
18931 +#define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000
18932 +#define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff
18933 +#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
18934 +#define AR_PHY_TIMING3_DSC_MAN_S 17
18935 +#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
18936 +#define AR_PHY_TIMING3_DSC_EXP_S 13
18937 +#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000
18938 +#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12
18939 +#define AR_PHY_TIMING4_DO_CAL 0x10000
18940 +
18941 +#define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000
18942 +#define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28
18943 +#define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000
18944 +#define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29
18945 +
18946 +#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
18947 +#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30
18948 +#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
18949 +#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31
18950 +
18951 +#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
18952 +#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
18953 +#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
18954 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
18955 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
18956 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
18957 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
18958 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
18959 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
18960 +#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
18961 +#define AR_PHY_SFCORR_M2COUNT_THR_S 0
18962 +#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
18963 +#define AR_PHY_SFCORR_M1_THRESH_S 17
18964 +#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
18965 +#define AR_PHY_SFCORR_M2_THRESH_S 24
18966 +#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
18967 +#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
18968 +#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
18969 +#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
18970 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
18971 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
18972 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
18973 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
18974 +#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
18975 +#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28
18976 +#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
18977 +#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
18978 +#define AR_PHY_EXT_CCA_THRESH62_S 16
18979 +#define AR_PHY_EXT_MINCCA_PWR 0x01FF0000
18980 +#define AR_PHY_EXT_MINCCA_PWR_S 16
18981 +#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
18982 +#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
18983 +#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001
18984 +#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0
18985 +#define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000
18986 +#define AR_PHY_TIMING5_CYCPWR_THR1A_S 16
18987 +#define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16)
18988 +#define AR_PHY_TIMING5_RSSI_THR1A_S 16
18989 +#define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)
18990 +#define AR_PHY_RADAR_0_ENA 0x00000001
18991 +#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
18992 +#define AR_PHY_RADAR_0_INBAND 0x0000003e
18993 +#define AR_PHY_RADAR_0_INBAND_S 1
18994 +#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
18995 +#define AR_PHY_RADAR_0_PRSSI_S 6
18996 +#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
18997 +#define AR_PHY_RADAR_0_HEIGHT_S 12
18998 +#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
18999 +#define AR_PHY_RADAR_0_RRSSI_S 18
19000 +#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
19001 +#define AR_PHY_RADAR_0_FIRPWR_S 24
19002 +#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
19003 +#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
19004 +#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
19005 +#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
19006 +#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
19007 +#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
19008 +#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
19009 +#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
19010 +#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
19011 +#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
19012 +#define AR_PHY_RADAR_1_MAXLEN_S 0
19013 +#define AR_PHY_RADAR_EXT_ENA 0x00004000
19014 +#define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000
19015 +#define AR_PHY_RADAR_DC_PWR_THRESH_S 15
19016 +#define AR_PHY_RADAR_LB_DC_CAP 0x7f800000
19017 +#define AR_PHY_RADAR_LB_DC_CAP_S 23
19018 +#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)
19019 +#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6
19020 +#define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12)
19021 +#define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12
19022 +#define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19
19023 +#define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f
19024 +#define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0
19025 +#define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5
19026 +#define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008
19027 +#define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3
19028 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F
19029 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0
19030 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80
19031 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7
19032 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000
19033 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000
19034 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15
19035 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000
19036 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22
19037 +
19038 +/*
19039 + * MRC Register Map
19040 + */
19041 +#define AR_MRC_BASE 0x9c00
19042 +
19043 +#define AR_PHY_TIMING_3A AR_MRC_BASE + 0x0
19044 +#define AR_PHY_LDPC_CNTL1 AR_MRC_BASE + 0x4
19045 +#define AR_PHY_LDPC_CNTL2 AR_MRC_BASE + 0x8
19046 +#define AR_PHY_PILOT_SPUR_MASK AR_MRC_BASE + 0xc
19047 +#define AR_PHY_CHAN_SPUR_MASK AR_MRC_BASE + 0x10
19048 +#define AR_PHY_SGI_DELTA AR_MRC_BASE + 0x14
19049 +#define AR_PHY_ML_CNTL_1 AR_MRC_BASE + 0x18
19050 +#define AR_PHY_ML_CNTL_2 AR_MRC_BASE + 0x1c
19051 +#define AR_PHY_TST_ADC AR_MRC_BASE + 0x20
19052 +
19053 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0
19054 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5
19055 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F
19056 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0
19057 +
19058 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0
19059 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5
19060 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F
19061 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0
19062 +
19063 +/*
19064 + * MRC Feild Definitions
19065 + */
19066 +#define AR_PHY_SGI_DSC_MAN 0x0007FFF0
19067 +#define AR_PHY_SGI_DSC_MAN_S 4
19068 +#define AR_PHY_SGI_DSC_EXP 0x0000000F
19069 +#define AR_PHY_SGI_DSC_EXP_S 0
19070 +/*
19071 + * BBB Register Map
19072 + */
19073 +#define AR_BBB_BASE 0x9d00
19074 +
19075 +/*
19076 + * AGC Register Map
19077 + */
19078 +#define AR_AGC_BASE 0x9e00
19079 +
19080 +#define AR_PHY_SETTLING AR_AGC_BASE + 0x0
19081 +#define AR_PHY_FORCEMAX_GAINS_0 AR_AGC_BASE + 0x4
19082 +#define AR_PHY_GAINS_MINOFF0 AR_AGC_BASE + 0x8
19083 +#define AR_PHY_DESIRED_SZ AR_AGC_BASE + 0xc
19084 +#define AR_PHY_FIND_SIG AR_AGC_BASE + 0x10
19085 +#define AR_PHY_AGC AR_AGC_BASE + 0x14
19086 +#define AR_PHY_EXT_ATTEN_CTL_0 AR_AGC_BASE + 0x18
19087 +#define AR_PHY_CCA_0 AR_AGC_BASE + 0x1c
19088 +#define AR_PHY_EXT_CCA0 AR_AGC_BASE + 0x20
19089 +#define AR_PHY_RESTART AR_AGC_BASE + 0x24
19090 +#define AR_PHY_MC_GAIN_CTRL AR_AGC_BASE + 0x28
19091 +#define AR_PHY_EXTCHN_PWRTHR1 AR_AGC_BASE + 0x2c
19092 +#define AR_PHY_EXT_CHN_WIN AR_AGC_BASE + 0x30
19093 +#define AR_PHY_20_40_DET_THR AR_AGC_BASE + 0x34
19094 +#define AR_PHY_RIFS_SRCH AR_AGC_BASE + 0x38
19095 +#define AR_PHY_PEAK_DET_CTRL_1 AR_AGC_BASE + 0x3c
19096 +#define AR_PHY_PEAK_DET_CTRL_2 AR_AGC_BASE + 0x40
19097 +#define AR_PHY_RX_GAIN_BOUNDS_1 AR_AGC_BASE + 0x44
19098 +#define AR_PHY_RX_GAIN_BOUNDS_2 AR_AGC_BASE + 0x48
19099 +#define AR_PHY_RSSI_0 AR_AGC_BASE + 0x180
19100 +#define AR_PHY_SPUR_CCK_REP0 AR_AGC_BASE + 0x184
19101 +#define AR_PHY_CCK_DETECT AR_AGC_BASE + 0x1c0
19102 +#define AR_PHY_DAG_CTRLCCK AR_AGC_BASE + 0x1c4
19103 +#define AR_PHY_IQCORR_CTRL_CCK AR_AGC_BASE + 0x1c8
19104 +
19105 +#define AR_PHY_CCK_SPUR_MIT AR_AGC_BASE + 0x1cc
19106 +#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe
19107 +#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1
19108 +#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000
19109 +#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29
19110 +#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001
19111 +#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0
19112 +#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00
19113 +#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9
19114 +
19115 +#define AR_PHY_RX_OCGAIN AR_AGC_BASE + 0x200
19116 +
19117 +#define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110
19118 +#define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115
19119 +#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125
19120 +#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125
19121 +#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
19122 +#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
19123 +
19124 +/*
19125 + * AGC Field Definitions
19126 + */
19127 +#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000
19128 +#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18
19129 +#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00
19130 +#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10
19131 +#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F
19132 +#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0
19133 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000
19134 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17
19135 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000
19136 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12
19137 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0
19138 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6
19139 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F
19140 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0
19141 +#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
19142 +#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
19143 +#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
19144 +#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
19145 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
19146 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
19147 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
19148 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
19149 +#define AR_PHY_SETTLING_SWITCH 0x00003F80
19150 +#define AR_PHY_SETTLING_SWITCH_S 7
19151 +#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
19152 +#define AR_PHY_DESIRED_SZ_ADC_S 0
19153 +#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
19154 +#define AR_PHY_DESIRED_SZ_PGA_S 8
19155 +#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
19156 +#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
19157 +#define AR_PHY_MINCCA_PWR 0x1FF00000
19158 +#define AR_PHY_MINCCA_PWR_S 20
19159 +#define AR_PHY_CCA_THRESH62 0x0007F000
19160 +#define AR_PHY_CCA_THRESH62_S 12
19161 +#define AR9280_PHY_MINCCA_PWR 0x1FF00000
19162 +#define AR9280_PHY_MINCCA_PWR_S 20
19163 +#define AR9280_PHY_CCA_THRESH62 0x000FF000
19164 +#define AR9280_PHY_CCA_THRESH62_S 12
19165 +#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
19166 +#define AR_PHY_EXT_CCA0_THRESH62_S 0
19167 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
19168 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
19169 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
19170 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
19171 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
19172 +
19173 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
19174 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9
19175 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
19176 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
19177 +
19178 +#define AR_PHY_RIFS_INIT_DELAY 0x3ff0000
19179 +#define AR_PHY_AGC_COARSE_LOW 0x00007F80
19180 +#define AR_PHY_AGC_COARSE_LOW_S 7
19181 +#define AR_PHY_AGC_COARSE_HIGH 0x003F8000
19182 +#define AR_PHY_AGC_COARSE_HIGH_S 15
19183 +#define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F
19184 +#define AR_PHY_AGC_COARSE_PWR_CONST_S 0
19185 +#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
19186 +#define AR_PHY_FIND_SIG_FIRSTEP_S 12
19187 +#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
19188 +#define AR_PHY_FIND_SIG_FIRPWR_S 18
19189 +#define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25
19190 +#define AR_PHY_FIND_SIG_RELPWR (0x1f << 6)
19191 +#define AR_PHY_FIND_SIG_RELPWR_S 6
19192 +#define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11
19193 +#define AR_PHY_FIND_SIG_RELSTEP 0x1f
19194 +#define AR_PHY_FIND_SIG_RELSTEP_S 0
19195 +#define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5
19196 +#define AR_PHY_RESTART_DIV_GC 0x001C0000
19197 +#define AR_PHY_RESTART_DIV_GC_S 18
19198 +#define AR_PHY_RESTART_ENA 0x01
19199 +#define AR_PHY_DC_RESTART_DIS 0x40000000
19200 +
19201 +#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000
19202 +#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24
19203 +#define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000
19204 +#define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16
19205 +
19206 +#define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000
19207 +#define AR_PHY_TPC_6_ERROR_EST_MODE_S 24
19208 +
19209 +/*
19210 + * SM Register Map
19211 + */
19212 +#define AR_SM_BASE 0xa200
19213 +
19214 +#define AR_PHY_D2_CHIP_ID AR_SM_BASE + 0x0
19215 +#define AR_PHY_GEN_CTRL AR_SM_BASE + 0x4
19216 +#define AR_PHY_MODE AR_SM_BASE + 0x8
19217 +#define AR_PHY_ACTIVE AR_SM_BASE + 0xc
19218 +#define AR_PHY_SPUR_MASK_A AR_SM_BASE + 0x20
19219 +#define AR_PHY_SPUR_MASK_B AR_SM_BASE + 0x24
19220 +#define AR_PHY_SPECTRAL_SCAN AR_SM_BASE + 0x28
19221 +#define AR_PHY_RADAR_BW_FILTER AR_SM_BASE + 0x2c
19222 +#define AR_PHY_SEARCH_START_DELAY AR_SM_BASE + 0x30
19223 +#define AR_PHY_MAX_RX_LEN AR_SM_BASE + 0x34
19224 +#define AR_PHY_FRAME_CTL AR_SM_BASE + 0x38
19225 +#define AR_PHY_RFBUS_REQ AR_SM_BASE + 0x3c
19226 +#define AR_PHY_RFBUS_GRANT AR_SM_BASE + 0x40
19227 +#define AR_PHY_RIFS AR_SM_BASE + 0x44
19228 +#define AR_PHY_RX_CLR_DELAY AR_SM_BASE + 0x50
19229 +#define AR_PHY_RX_DELAY AR_SM_BASE + 0x54
19230 +
19231 +#define AR_PHY_XPA_TIMING_CTL AR_SM_BASE + 0x64
19232 +#define AR_PHY_MISC_PA_CTL AR_SM_BASE + 0x80
19233 +#define AR_PHY_SWITCH_CHAIN_0 AR_SM_BASE + 0x84
19234 +#define AR_PHY_SWITCH_COM AR_SM_BASE + 0x88
19235 +#define AR_PHY_SWITCH_COM_2 AR_SM_BASE + 0x8c
19236 +#define AR_PHY_RX_CHAINMASK AR_SM_BASE + 0xa0
19237 +#define AR_PHY_CAL_CHAINMASK AR_SM_BASE + 0xc0
19238 +#define AR_PHY_CALMODE AR_SM_BASE + 0xc8
19239 +#define AR_PHY_FCAL_1 AR_SM_BASE + 0xcc
19240 +#define AR_PHY_FCAL_2_0 AR_SM_BASE + 0xd0
19241 +#define AR_PHY_DFT_TONE_CTL_0 AR_SM_BASE + 0xd4
19242 +#define AR_PHY_CL_CAL_CTL AR_SM_BASE + 0xd8
19243 +#define AR_PHY_CL_TAB_0 AR_SM_BASE + 0x100
19244 +#define AR_PHY_SYNTH_CONTROL AR_SM_BASE + 0x140
19245 +#define AR_PHY_ADDAC_CLK_SEL AR_SM_BASE + 0x144
19246 +#define AR_PHY_PLL_CTL AR_SM_BASE + 0x148
19247 +#define AR_PHY_ANALOG_SWAP AR_SM_BASE + 0x14c
19248 +#define AR_PHY_ADDAC_PARA_CTL AR_SM_BASE + 0x150
19249 +#define AR_PHY_XPA_CFG AR_SM_BASE + 0x158
19250 +
19251 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00
19252 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10
19253 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF
19254 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0
19255 +
19256 +#define AR_PHY_TEST AR_SM_BASE + 0x160
19257 +
19258 +#define AR_PHY_TEST_BBB_OBS_SEL 0x780000
19259 +#define AR_PHY_TEST_BBB_OBS_SEL_S 19
19260 +
19261 +#define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23
19262 +#define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)
19263 +
19264 +#define AR_PHY_TEST_CHAIN_SEL 0xC0000000
19265 +#define AR_PHY_TEST_CHAIN_SEL_S 30
19266 +
19267 +#define AR_PHY_TEST_CTL_STATUS AR_SM_BASE + 0x164
19268 +#define AR_PHY_TEST_CTL_TSTDAC_EN 0x1
19269 +#define AR_PHY_TEST_CTL_TSTDAC_EN_S 0
19270 +#define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C
19271 +#define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2
19272 +#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60
19273 +#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5
19274 +#define AR_PHY_TEST_CTL_TSTADC_EN 0x100
19275 +#define AR_PHY_TEST_CTL_TSTADC_EN_S 8
19276 +#define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00
19277 +#define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10
19278 +
19279 +
19280 +#define AR_PHY_TSTDAC AR_SM_BASE + 0x168
19281 +
19282 +#define AR_PHY_CHAN_STATUS AR_SM_BASE + 0x16c
19283 +#define AR_PHY_CHAN_INFO_MEMORY AR_SM_BASE + 0x170
19284 +#define AR_PHY_CHNINFO_NOISEPWR AR_SM_BASE + 0x174
19285 +#define AR_PHY_CHNINFO_GAINDIFF AR_SM_BASE + 0x178
19286 +#define AR_PHY_CHNINFO_FINETIM AR_SM_BASE + 0x17c
19287 +#define AR_PHY_CHAN_INFO_GAIN_0 AR_SM_BASE + 0x180
19288 +#define AR_PHY_SCRAMBLER_SEED AR_SM_BASE + 0x190
19289 +#define AR_PHY_CCK_TX_CTRL AR_SM_BASE + 0x194
19290 +
19291 +#define AR_PHY_HEAVYCLIP_CTL AR_SM_BASE + 0x1a4
19292 +#define AR_PHY_HEAVYCLIP_20 AR_SM_BASE + 0x1a8
19293 +#define AR_PHY_HEAVYCLIP_40 AR_SM_BASE + 0x1ac
19294 +#define AR_PHY_ILLEGAL_TXRATE AR_SM_BASE + 0x1b0
19295 +
19296 +#define AR_PHY_PWRTX_MAX AR_SM_BASE + 0x1f0
19297 +#define AR_PHY_POWER_TX_SUB AR_SM_BASE + 0x1f4
19298 +
19299 +#define AR_PHY_TPC_4_B0 AR_SM_BASE + 0x204
19300 +#define AR_PHY_TPC_5_B0 AR_SM_BASE + 0x208
19301 +#define AR_PHY_TPC_6_B0 AR_SM_BASE + 0x20c
19302 +#define AR_PHY_TPC_11_B0 AR_SM_BASE + 0x220
19303 +#define AR_PHY_TPC_18 AR_SM_BASE + 0x23c
19304 +#define AR_PHY_TPC_19 AR_SM_BASE + 0x240
19305 +
19306 +#define AR_PHY_TX_FORCED_GAIN AR_SM_BASE + 0x258
19307 +
19308 +#define AR_PHY_PDADC_TAB_0 AR_SM_BASE + 0x280
19309 +
19310 +#define AR_PHY_TX_IQCAL_CONTROL_1 AR_SM_BASE + 0x448
19311 +#define AR_PHY_TX_IQCAL_START AR_SM_BASE + 0x440
19312 +#define AR_PHY_TX_IQCAL_STATUS_B0 AR_SM_BASE + 0x48c
19313 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 AR_SM_BASE + 0x450
19314 +
19315 +#define AR_PHY_PANIC_WD_STATUS AR_SM_BASE + 0x5c0
19316 +#define AR_PHY_PANIC_WD_CTL_1 AR_SM_BASE + 0x5c4
19317 +#define AR_PHY_PANIC_WD_CTL_2 AR_SM_BASE + 0x5c8
19318 +#define AR_PHY_BT_CTL AR_SM_BASE + 0x5cc
19319 +#define AR_PHY_ONLY_WARMRESET AR_SM_BASE + 0x5d0
19320 +#define AR_PHY_ONLY_CTL AR_SM_BASE + 0x5d4
19321 +#define AR_PHY_ECO_CTRL AR_SM_BASE + 0x5dc
19322 +#define AR_PHY_BB_THERM_ADC_1 AR_SM_BASE + 0x248
19323 +
19324 +#define AR_PHY_65NM_CH0_SYNTH4 0x1608c
19325 +#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002
19326 +#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1
19327 +#define AR_PHY_65NM_CH0_SYNTH7 0x16098
19328 +#define AR_PHY_65NM_CH0_BIAS1 0x160c0
19329 +#define AR_PHY_65NM_CH0_BIAS2 0x160c4
19330 +#define AR_PHY_65NM_CH0_BIAS4 0x160cc
19331 +#define AR_PHY_65NM_CH0_RXTX4 0x1610c
19332 +#define AR_PHY_65NM_CH0_THERM 0x16290
19333 +
19334 +#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
19335 +#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
19336 +#define AR_PHY_65NM_CH0_THERM_START 0x20000000
19337 +#define AR_PHY_65NM_CH0_THERM_START_S 29
19338 +#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00
19339 +#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8
19340 +
19341 +#define AR_PHY_65NM_CH0_RXTX1 0x16100
19342 +#define AR_PHY_65NM_CH0_RXTX2 0x16104
19343 +#define AR_PHY_65NM_CH1_RXTX1 0x16500
19344 +#define AR_PHY_65NM_CH1_RXTX2 0x16504
19345 +#define AR_PHY_65NM_CH2_RXTX1 0x16900
19346 +#define AR_PHY_65NM_CH2_RXTX2 0x16904
19347 +
19348 +#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000
19349 +#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19
19350 +#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000
19351 +#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22
19352 +#define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000
19353 +#define AR_PHY_LNAGAIN_LONG_SHIFT_S 29
19354 +#define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000
19355 +#define AR_PHY_MXRGAIN_LONG_SHIFT_S 24
19356 +#define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000
19357 +#define AR_PHY_VGAGAIN_LONG_SHIFT_S 26
19358 +#define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001
19359 +#define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0
19360 +#define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002
19361 +#define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1
19362 +
19363 +/*
19364 + * SM Field Definitions
19365 + */
19366 +#define AR_PHY_CL_CAL_ENABLE 0x00000002
19367 +#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
19368 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
19369 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
19370 +
19371 +#define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
19372 +
19373 +#define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000
19374 +#define AR_PHY_FCAL20_CAP_STATUS_0_S 20
19375 +
19376 +#define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */
19377 +#define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */
19378 +#define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */
19379 +#define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */
19380 +#define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */
19381 +#define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
19382 +#define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
19383 +#define AR_PHY_GC_DYN2040_PRI_CH_S 4
19384 +#define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
19385 +#define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */
19386 +#define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
19387 +#define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
19388 +#define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
19389 +#define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */
19390 +#define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */
19391 +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
19392 +
19393 +#define AR_PHY_CALMODE_IQ 0x00000000
19394 +#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
19395 +#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
19396 +#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
19397 +#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
19398 +#define AR_PHY_MODE_OFDM 0x00000000
19399 +#define AR_PHY_MODE_CCK 0x00000001
19400 +#define AR_PHY_MODE_DYNAMIC 0x00000004
19401 +#define AR_PHY_MODE_DYNAMIC_S 2
19402 +#define AR_PHY_MODE_HALF 0x00000020
19403 +#define AR_PHY_MODE_QUARTER 0x00000040
19404 +#define AR_PHY_MAC_CLK_MODE 0x00000080
19405 +#define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
19406 +#define AR_PHY_MODE_SVD_HALF 0x00000200
19407 +#define AR_PHY_ACTIVE_EN 0x00000001
19408 +#define AR_PHY_ACTIVE_DIS 0x00000000
19409 +#define AR_PHY_FORCE_XPA_CFG 0x000000001
19410 +#define AR_PHY_FORCE_XPA_CFG_S 0
19411 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000
19412 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24
19413 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000
19414 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16
19415 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00
19416 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8
19417 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF
19418 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0
19419 +#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
19420 +#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
19421 +#define AR_PHY_TX_END_DATA_START 0x000000FF
19422 +#define AR_PHY_TX_END_DATA_START_S 0
19423 +#define AR_PHY_TX_END_PA_ON 0x0000FF00
19424 +#define AR_PHY_TX_END_PA_ON_S 8
19425 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
19426 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
19427 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
19428 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
19429 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
19430 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
19431 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
19432 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
19433 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
19434 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
19435 +#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
19436 +#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
19437 +#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
19438 +#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
19439 +#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
19440 +#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
19441 +#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
19442 +#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
19443 +#define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e
19444 +#define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
19445 +#define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001
19446 +#define AR_PHY_TXGAIN_FORCE 0x00000001
19447 +#define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00
19448 +#define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10
19449 +#define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000
19450 +#define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14
19451 +#define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000
19452 +#define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22
19453 +#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0
19454 +#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6
19455 +#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e
19456 +#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1
19457 +
19458 +#define AR_PHY_POWER_TX_RATE1 0x9934
19459 +#define AR_PHY_POWER_TX_RATE2 0x9938
19460 +#define AR_PHY_POWER_TX_RATE_MAX 0x993c
19461 +#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
19462 +#define PHY_AGC_CLR 0x10000000
19463 +#define RFSILENT_BB 0x00002000
19464 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF
19465 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800
19466 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
19467 +#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
19468 +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
19469 +#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
19470 +#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001
19471 +#define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0
19472 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002
19473 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1
19474 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0
19475 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
19476 +#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00
19477 +#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
19478 +#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000
19479 +#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
19480 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000
19481 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
19482 +#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
19483 +#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
19484 +#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18
19485 +#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
19486 +#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
19487 +
19488 +#define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
19489 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x00003fff
19490 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0
19491 +
19492 +#define AR_PHY_TPC_18_THERM_CAL_VALUE 0xff
19493 +#define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
19494 +#define AR_PHY_TPC_19_ALPHA_THERM 0xff
19495 +#define AR_PHY_TPC_19_ALPHA_THERM_S 0
19496 +
19497 +#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
19498 +#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
19499 +
19500 +#define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
19501 +#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
19502 +
19503 +/*
19504 + * Channel 1 Register Map
19505 + */
19506 +#define AR_CHAN1_BASE 0xa800
19507 +
19508 +#define AR_PHY_EXT_CCA_1 AR_CHAN1_BASE + 0x30
19509 +#define AR_PHY_TX_PHASE_RAMP_1 AR_CHAN1_BASE + 0xd0
19510 +#define AR_PHY_ADC_GAIN_DC_CORR_1 AR_CHAN1_BASE + 0xd4
19511 +
19512 +#define AR_PHY_SPUR_REPORT_1 AR_CHAN1_BASE + 0xa8
19513 +#define AR_PHY_CHAN_INFO_TAB_1 AR_CHAN1_BASE + 0x300
19514 +#define AR_PHY_RX_IQCAL_CORR_B1 AR_CHAN1_BASE + 0xdc
19515 +
19516 +/*
19517 + * Channel 1 Field Definitions
19518 + */
19519 +#define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
19520 +#define AR_PHY_CH1_EXT_MINCCA_PWR_S 16
19521 +
19522 +/*
19523 + * AGC 1 Register Map
19524 + */
19525 +#define AR_AGC1_BASE 0xae00
19526 +
19527 +#define AR_PHY_FORCEMAX_GAINS_1 AR_AGC1_BASE + 0x4
19528 +#define AR_PHY_EXT_ATTEN_CTL_1 AR_AGC1_BASE + 0x18
19529 +#define AR_PHY_CCA_1 AR_AGC1_BASE + 0x1c
19530 +#define AR_PHY_CCA_CTRL_1 AR_AGC1_BASE + 0x20
19531 +#define AR_PHY_RSSI_1 AR_AGC1_BASE + 0x180
19532 +#define AR_PHY_SPUR_CCK_REP_1 AR_AGC1_BASE + 0x184
19533 +#define AR_PHY_RX_OCGAIN_2 AR_AGC1_BASE + 0x200
19534 +
19535 +/*
19536 + * AGC 1 Field Definitions
19537 + */
19538 +#define AR_PHY_CH1_MINCCA_PWR 0x1FF00000
19539 +#define AR_PHY_CH1_MINCCA_PWR_S 20
19540 +
19541 +/*
19542 + * SM 1 Register Map
19543 + */
19544 +#define AR_SM1_BASE 0xb200
19545 +
19546 +#define AR_PHY_SWITCH_CHAIN_1 AR_SM1_BASE + 0x84
19547 +#define AR_PHY_FCAL_2_1 AR_SM1_BASE + 0xd0
19548 +#define AR_PHY_DFT_TONE_CTL_1 AR_SM1_BASE + 0xd4
19549 +#define AR_PHY_CL_TAB_1 AR_SM1_BASE + 0x100
19550 +#define AR_PHY_CHAN_INFO_GAIN_1 AR_SM1_BASE + 0x180
19551 +#define AR_PHY_TPC_4_B1 AR_SM1_BASE + 0x204
19552 +#define AR_PHY_TPC_5_B1 AR_SM1_BASE + 0x208
19553 +#define AR_PHY_TPC_6_B1 AR_SM1_BASE + 0x20c
19554 +#define AR_PHY_TPC_11_B1 AR_SM1_BASE + 0x220
19555 +#define AR_PHY_PDADC_TAB_1 AR_SM1_BASE + 0x240
19556 +#define AR_PHY_TX_IQCAL_STATUS_B1 AR_SM1_BASE + 0x48c
19557 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1 AR_SM1_BASE + 0x450
19558 +
19559 +/*
19560 + * Channel 2 Register Map
19561 + */
19562 +#define AR_CHAN2_BASE 0xb800
19563 +
19564 +#define AR_PHY_EXT_CCA_2 AR_CHAN2_BASE + 0x30
19565 +#define AR_PHY_TX_PHASE_RAMP_2 AR_CHAN2_BASE + 0xd0
19566 +#define AR_PHY_ADC_GAIN_DC_CORR_2 AR_CHAN2_BASE + 0xd4
19567 +
19568 +#define AR_PHY_SPUR_REPORT_2 AR_CHAN2_BASE + 0xa8
19569 +#define AR_PHY_CHAN_INFO_TAB_2 AR_CHAN2_BASE + 0x300
19570 +#define AR_PHY_RX_IQCAL_CORR_B2 AR_CHAN2_BASE + 0xdc
19571 +
19572 +/*
19573 + * Channel 2 Field Definitions
19574 + */
19575 +#define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000
19576 +#define AR_PHY_CH2_EXT_MINCCA_PWR_S 16
19577 +/*
19578 + * AGC 2 Register Map
19579 + */
19580 +#define AR_AGC2_BASE 0xbe00
19581 +
19582 +#define AR_PHY_FORCEMAX_GAINS_2 AR_AGC2_BASE + 0x4
19583 +#define AR_PHY_EXT_ATTEN_CTL_2 AR_AGC2_BASE + 0x18
19584 +#define AR_PHY_CCA_2 AR_AGC2_BASE + 0x1c
19585 +#define AR_PHY_CCA_CTRL_2 AR_AGC2_BASE + 0x20
19586 +#define AR_PHY_RSSI_2 AR_AGC2_BASE + 0x180
19587 +
19588 +/*
19589 + * AGC 2 Field Definitions
19590 + */
19591 +#define AR_PHY_CH2_MINCCA_PWR 0x1FF00000
19592 +#define AR_PHY_CH2_MINCCA_PWR_S 20
19593 +
19594 +/*
19595 + * SM 2 Register Map
19596 + */
19597 +#define AR_SM2_BASE 0xc200
19598 +
19599 +#define AR_PHY_SWITCH_CHAIN_2 AR_SM2_BASE + 0x84
19600 +#define AR_PHY_FCAL_2_2 AR_SM2_BASE + 0xd0
19601 +#define AR_PHY_DFT_TONE_CTL_2 AR_SM2_BASE + 0xd4
19602 +#define AR_PHY_CL_TAB_2 AR_SM2_BASE + 0x100
19603 +#define AR_PHY_CHAN_INFO_GAIN_2 AR_SM2_BASE + 0x180
19604 +#define AR_PHY_TPC_4_B2 AR_SM2_BASE + 0x204
19605 +#define AR_PHY_TPC_5_B2 AR_SM2_BASE + 0x208
19606 +#define AR_PHY_TPC_6_B2 AR_SM2_BASE + 0x20c
19607 +#define AR_PHY_TPC_11_B2 AR_SM2_BASE + 0x220
19608 +#define AR_PHY_PDADC_TAB_2 AR_SM2_BASE + 0x240
19609 +#define AR_PHY_TX_IQCAL_STATUS_B2 AR_SM2_BASE + 0x48c
19610 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2 AR_SM2_BASE + 0x450
19611 +
19612 +#define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001
19613 +
19614 +/*
19615 + * AGC 3 Register Map
19616 + */
19617 +#define AR_AGC3_BASE 0xce00
19618 +
19619 +#define AR_PHY_RSSI_3 AR_AGC3_BASE + 0x180
19620 +
19621 +/*
19622 + * Misc helper defines
19623 + */
19624 +#define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE)
19625 +
19626 +#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19627 +#define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
19628 +#define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19629 +#define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19630 +
19631 +#define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19632 +#define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19633 +#define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19634 +
19635 +#define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19636 +#define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19637 +#define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19638 +#define AR_PHY_CAL_MEAS_3(_i) (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19639 +#define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
19640 +#define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
19641 +#define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
19642 +#define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
19643 +
19644 +#define AR_PHY_BB_PANIC_NON_IDLE_ENABLE 0x00000001
19645 +#define AR_PHY_BB_PANIC_IDLE_ENABLE 0x00000002
19646 +#define AR_PHY_BB_PANIC_IDLE_MASK 0xFFFF0000
19647 +#define AR_PHY_BB_PANIC_NON_IDLE_MASK 0x0000FFFC
19648 +
19649 +#define AR_PHY_BB_PANIC_RST_ENABLE 0x00000002
19650 +#define AR_PHY_BB_PANIC_IRQ_ENABLE 0x00000004
19651 +#define AR_PHY_BB_PANIC_CNTL2_MASK 0xFFFFFFF9
19652 +
19653 +#define AR_PHY_BB_WD_STATUS 0x00000007
19654 +#define AR_PHY_BB_WD_STATUS_S 0
19655 +#define AR_PHY_BB_WD_DET_HANG 0x00000008
19656 +#define AR_PHY_BB_WD_DET_HANG_S 3
19657 +#define AR_PHY_BB_WD_RADAR_SM 0x000000F0
19658 +#define AR_PHY_BB_WD_RADAR_SM_S 4
19659 +#define AR_PHY_BB_WD_RX_OFDM_SM 0x00000F00
19660 +#define AR_PHY_BB_WD_RX_OFDM_SM_S 8
19661 +#define AR_PHY_BB_WD_RX_CCK_SM 0x0000F000
19662 +#define AR_PHY_BB_WD_RX_CCK_SM_S 12
19663 +#define AR_PHY_BB_WD_TX_OFDM_SM 0x000F0000
19664 +#define AR_PHY_BB_WD_TX_OFDM_SM_S 16
19665 +#define AR_PHY_BB_WD_TX_CCK_SM 0x00F00000
19666 +#define AR_PHY_BB_WD_TX_CCK_SM_S 20
19667 +#define AR_PHY_BB_WD_AGC_SM 0x0F000000
19668 +#define AR_PHY_BB_WD_AGC_SM_S 24
19669 +#define AR_PHY_BB_WD_SRCH_SM 0xF0000000
19670 +#define AR_PHY_BB_WD_SRCH_SM_S 28
19671 +
19672 +#define AR_PHY_BB_WD_STATUS_CLR 0x00000008
19673 +
19674 +void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
19675 +
19676 +#endif /* AR9003_PHY_H */
19677 --- a/drivers/net/wireless/ath/ath9k/ath9k.h
19678 +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
19679 @@ -114,8 +114,10 @@ enum buffer_type {
19680 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
19681 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
19682
19683 +#define ATH_TXSTATUS_RING_SIZE 64
19684 +
19685 struct ath_descdma {
19686 - struct ath_desc *dd_desc;
19687 + void *dd_desc;
19688 dma_addr_t dd_desc_paddr;
19689 u32 dd_desc_len;
19690 struct ath_buf *dd_bufptr;
19691 @@ -123,7 +125,7 @@ struct ath_descdma {
19692
19693 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
19694 struct list_head *head, const char *name,
19695 - int nbuf, int ndesc);
19696 + int nbuf, int ndesc, bool is_tx);
19697 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
19698 struct list_head *head);
19699
19700 @@ -188,6 +190,7 @@ enum ATH_AGGR_STATUS {
19701 ATH_AGGR_LIMITED,
19702 };
19703
19704 +#define ATH_TXFIFO_DEPTH 8
19705 struct ath_txq {
19706 u32 axq_qnum;
19707 u32 *axq_link;
19708 @@ -197,6 +200,10 @@ struct ath_txq {
19709 bool stopped;
19710 bool axq_tx_inprogress;
19711 struct list_head axq_acq;
19712 + struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
19713 + struct list_head txq_fifo_pending;
19714 + u8 txq_headidx;
19715 + u8 txq_tailidx;
19716 };
19717
19718 #define AGGR_CLEANUP BIT(1)
19719 @@ -223,6 +230,12 @@ struct ath_tx {
19720 struct ath_descdma txdma;
19721 };
19722
19723 +struct ath_rx_edma {
19724 + struct sk_buff_head rx_fifo;
19725 + struct sk_buff_head rx_buffers;
19726 + u32 rx_fifo_hwsize;
19727 +};
19728 +
19729 struct ath_rx {
19730 u8 defant;
19731 u8 rxotherant;
19732 @@ -232,6 +245,8 @@ struct ath_rx {
19733 spinlock_t rxbuflock;
19734 struct list_head rxbuf;
19735 struct ath_descdma rxdma;
19736 + struct ath_buf *rx_bufptr;
19737 + struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
19738 };
19739
19740 int ath_startrecv(struct ath_softc *sc);
19741 @@ -240,7 +255,7 @@ void ath_flushrecv(struct ath_softc *sc)
19742 u32 ath_calcrxfilter(struct ath_softc *sc);
19743 int ath_rx_init(struct ath_softc *sc, int nbufs);
19744 void ath_rx_cleanup(struct ath_softc *sc);
19745 -int ath_rx_tasklet(struct ath_softc *sc, int flush);
19746 +int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
19747 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
19748 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
19749 int ath_tx_setup(struct ath_softc *sc, int haltype);
19750 @@ -258,6 +273,7 @@ int ath_txq_update(struct ath_softc *sc,
19751 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
19752 struct ath_tx_control *txctl);
19753 void ath_tx_tasklet(struct ath_softc *sc);
19754 +void ath_tx_edma_tasklet(struct ath_softc *sc);
19755 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
19756 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
19757 void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
19758 @@ -507,6 +523,8 @@ struct ath_softc {
19759 struct ath_beacon_config cur_beacon_conf;
19760 struct delayed_work tx_complete_work;
19761 struct ath_btcoex btcoex;
19762 +
19763 + struct ath_descdma txsdma;
19764 };
19765
19766 struct ath_wiphy {
19767 --- a/drivers/net/wireless/ath/ath9k/beacon.c
19768 +++ b/drivers/net/wireless/ath/ath9k/beacon.c
19769 @@ -93,8 +93,6 @@ static void ath_beacon_setup(struct ath_
19770 antenna = ((sc->beacon.ast_be_xmit / sc->nbcnvifs) & 1 ? 2 : 1);
19771 }
19772
19773 - ds->ds_data = bf->bf_buf_addr;
19774 -
19775 sband = &sc->sbands[common->hw->conf.channel->band];
19776 rate = sband->bitrates[rateidx].hw_value;
19777 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
19778 @@ -109,7 +107,8 @@ static void ath_beacon_setup(struct ath_
19779
19780 /* NB: beacon's BufLen must be a multiple of 4 bytes */
19781 ath9k_hw_filltxdesc(ah, ds, roundup(skb->len, 4),
19782 - true, true, ds);
19783 + true, true, ds, bf->bf_buf_addr,
19784 + sc->beacon.beaconq);
19785
19786 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
19787 series[0].Tries = 1;
19788 --- a/drivers/net/wireless/ath/ath9k/calib.c
19789 +++ b/drivers/net/wireless/ath/ath9k/calib.c
19790 @@ -15,10 +15,12 @@
19791 */
19792
19793 #include "hw.h"
19794 +#include "hw-ops.h"
19795 +
19796 +/* Common calibration code */
19797
19798 /* We can tune this as we go by monitoring really low values */
19799 #define ATH9K_NF_TOO_LOW -60
19800 -#define AR9285_CLCAL_REDO_THRESH 1
19801
19802 /* AR5416 may return very high value (like -31 dBm), in those cases the nf
19803 * is incorrect and we should use the static NF value. Later we can try to
19804 @@ -87,98 +89,9 @@ static void ath9k_hw_update_nfcal_hist_b
19805 return;
19806 }
19807
19808 -static void ath9k_hw_do_getnf(struct ath_hw *ah,
19809 - int16_t nfarray[NUM_NF_READINGS])
19810 -{
19811 - struct ath_common *common = ath9k_hw_common(ah);
19812 - int16_t nf;
19813 -
19814 - if (AR_SREV_9280_10_OR_LATER(ah))
19815 - nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
19816 - else
19817 - nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
19818 -
19819 - if (nf & 0x100)
19820 - nf = 0 - ((nf ^ 0x1ff) + 1);
19821 - ath_print(common, ATH_DBG_CALIBRATE,
19822 - "NF calibrated [ctl] [chain 0] is %d\n", nf);
19823 -
19824 - if (AR_SREV_9271(ah) && (nf >= -114))
19825 - nf = -116;
19826 -
19827 - nfarray[0] = nf;
19828 -
19829 - if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
19830 - if (AR_SREV_9280_10_OR_LATER(ah))
19831 - nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
19832 - AR9280_PHY_CH1_MINCCA_PWR);
19833 - else
19834 - nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
19835 - AR_PHY_CH1_MINCCA_PWR);
19836 -
19837 - if (nf & 0x100)
19838 - nf = 0 - ((nf ^ 0x1ff) + 1);
19839 - ath_print(common, ATH_DBG_CALIBRATE,
19840 - "NF calibrated [ctl] [chain 1] is %d\n", nf);
19841 - nfarray[1] = nf;
19842 -
19843 - if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
19844 - nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
19845 - AR_PHY_CH2_MINCCA_PWR);
19846 - if (nf & 0x100)
19847 - nf = 0 - ((nf ^ 0x1ff) + 1);
19848 - ath_print(common, ATH_DBG_CALIBRATE,
19849 - "NF calibrated [ctl] [chain 2] is %d\n", nf);
19850 - nfarray[2] = nf;
19851 - }
19852 - }
19853 -
19854 - if (AR_SREV_9280_10_OR_LATER(ah))
19855 - nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
19856 - AR9280_PHY_EXT_MINCCA_PWR);
19857 - else
19858 - nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
19859 - AR_PHY_EXT_MINCCA_PWR);
19860 -
19861 - if (nf & 0x100)
19862 - nf = 0 - ((nf ^ 0x1ff) + 1);
19863 - ath_print(common, ATH_DBG_CALIBRATE,
19864 - "NF calibrated [ext] [chain 0] is %d\n", nf);
19865 -
19866 - if (AR_SREV_9271(ah) && (nf >= -114))
19867 - nf = -116;
19868 -
19869 - nfarray[3] = nf;
19870 -
19871 - if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
19872 - if (AR_SREV_9280_10_OR_LATER(ah))
19873 - nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
19874 - AR9280_PHY_CH1_EXT_MINCCA_PWR);
19875 - else
19876 - nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
19877 - AR_PHY_CH1_EXT_MINCCA_PWR);
19878 -
19879 - if (nf & 0x100)
19880 - nf = 0 - ((nf ^ 0x1ff) + 1);
19881 - ath_print(common, ATH_DBG_CALIBRATE,
19882 - "NF calibrated [ext] [chain 1] is %d\n", nf);
19883 - nfarray[4] = nf;
19884 -
19885 - if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
19886 - nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
19887 - AR_PHY_CH2_EXT_MINCCA_PWR);
19888 - if (nf & 0x100)
19889 - nf = 0 - ((nf ^ 0x1ff) + 1);
19890 - ath_print(common, ATH_DBG_CALIBRATE,
19891 - "NF calibrated [ext] [chain 2] is %d\n", nf);
19892 - nfarray[5] = nf;
19893 - }
19894 - }
19895 -}
19896 -
19897 -static bool getNoiseFloorThresh(struct ath_hw *ah,
19898 - enum ieee80211_band band,
19899 - int16_t *nft)
19900 +static bool ath9k_hw_get_nf_thresh(struct ath_hw *ah,
19901 + enum ieee80211_band band,
19902 + int16_t *nft)
19903 {
19904 switch (band) {
19905 case IEEE80211_BAND_5GHZ:
19906 @@ -195,44 +108,8 @@ static bool getNoiseFloorThresh(struct a
19907 return true;
19908 }
19909
19910 -static void ath9k_hw_setup_calibration(struct ath_hw *ah,
19911 - struct ath9k_cal_list *currCal)
19912 -{
19913 - struct ath_common *common = ath9k_hw_common(ah);
19914 -
19915 - REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
19916 - AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
19917 - currCal->calData->calCountMax);
19918 -
19919 - switch (currCal->calData->calType) {
19920 - case IQ_MISMATCH_CAL:
19921 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
19922 - ath_print(common, ATH_DBG_CALIBRATE,
19923 - "starting IQ Mismatch Calibration\n");
19924 - break;
19925 - case ADC_GAIN_CAL:
19926 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
19927 - ath_print(common, ATH_DBG_CALIBRATE,
19928 - "starting ADC Gain Calibration\n");
19929 - break;
19930 - case ADC_DC_CAL:
19931 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
19932 - ath_print(common, ATH_DBG_CALIBRATE,
19933 - "starting ADC DC Calibration\n");
19934 - break;
19935 - case ADC_DC_INIT_CAL:
19936 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
19937 - ath_print(common, ATH_DBG_CALIBRATE,
19938 - "starting Init ADC DC Calibration\n");
19939 - break;
19940 - }
19941 -
19942 - REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
19943 - AR_PHY_TIMING_CTRL4_DO_CAL);
19944 -}
19945 -
19946 -static void ath9k_hw_reset_calibration(struct ath_hw *ah,
19947 - struct ath9k_cal_list *currCal)
19948 +void ath9k_hw_reset_calibration(struct ath_hw *ah,
19949 + struct ath9k_cal_list *currCal)
19950 {
19951 int i;
19952
19953 @@ -250,324 +127,6 @@ static void ath9k_hw_reset_calibration(s
19954 ah->cal_samples = 0;
19955 }
19956
19957 -static bool ath9k_hw_per_calibration(struct ath_hw *ah,
19958 - struct ath9k_channel *ichan,
19959 - u8 rxchainmask,
19960 - struct ath9k_cal_list *currCal)
19961 -{
19962 - bool iscaldone = false;
19963 -
19964 - if (currCal->calState == CAL_RUNNING) {
19965 - if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
19966 - AR_PHY_TIMING_CTRL4_DO_CAL)) {
19967 -
19968 - currCal->calData->calCollect(ah);
19969 - ah->cal_samples++;
19970 -
19971 - if (ah->cal_samples >= currCal->calData->calNumSamples) {
19972 - int i, numChains = 0;
19973 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
19974 - if (rxchainmask & (1 << i))
19975 - numChains++;
19976 - }
19977 -
19978 - currCal->calData->calPostProc(ah, numChains);
19979 - ichan->CalValid |= currCal->calData->calType;
19980 - currCal->calState = CAL_DONE;
19981 - iscaldone = true;
19982 - } else {
19983 - ath9k_hw_setup_calibration(ah, currCal);
19984 - }
19985 - }
19986 - } else if (!(ichan->CalValid & currCal->calData->calType)) {
19987 - ath9k_hw_reset_calibration(ah, currCal);
19988 - }
19989 -
19990 - return iscaldone;
19991 -}
19992 -
19993 -/* Assumes you are talking about the currently configured channel */
19994 -static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
19995 - enum ath9k_cal_types calType)
19996 -{
19997 - struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
19998 -
19999 - switch (calType & ah->supp_cals) {
20000 - case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
20001 - return true;
20002 - case ADC_GAIN_CAL:
20003 - case ADC_DC_CAL:
20004 - if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
20005 - conf_is_ht20(conf)))
20006 - return true;
20007 - break;
20008 - }
20009 - return false;
20010 -}
20011 -
20012 -static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
20013 -{
20014 - int i;
20015 -
20016 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
20017 - ah->totalPowerMeasI[i] +=
20018 - REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
20019 - ah->totalPowerMeasQ[i] +=
20020 - REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
20021 - ah->totalIqCorrMeas[i] +=
20022 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
20023 - ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
20024 - "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
20025 - ah->cal_samples, i, ah->totalPowerMeasI[i],
20026 - ah->totalPowerMeasQ[i],
20027 - ah->totalIqCorrMeas[i]);
20028 - }
20029 -}
20030 -
20031 -static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
20032 -{
20033 - int i;
20034 -
20035 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
20036 - ah->totalAdcIOddPhase[i] +=
20037 - REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
20038 - ah->totalAdcIEvenPhase[i] +=
20039 - REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
20040 - ah->totalAdcQOddPhase[i] +=
20041 - REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
20042 - ah->totalAdcQEvenPhase[i] +=
20043 - REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
20044 -
20045 - ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
20046 - "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
20047 - "oddq=0x%08x; evenq=0x%08x;\n",
20048 - ah->cal_samples, i,
20049 - ah->totalAdcIOddPhase[i],
20050 - ah->totalAdcIEvenPhase[i],
20051 - ah->totalAdcQOddPhase[i],
20052 - ah->totalAdcQEvenPhase[i]);
20053 - }
20054 -}
20055 -
20056 -static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
20057 -{
20058 - int i;
20059 -
20060 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
20061 - ah->totalAdcDcOffsetIOddPhase[i] +=
20062 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
20063 - ah->totalAdcDcOffsetIEvenPhase[i] +=
20064 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
20065 - ah->totalAdcDcOffsetQOddPhase[i] +=
20066 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
20067 - ah->totalAdcDcOffsetQEvenPhase[i] +=
20068 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
20069 -
20070 - ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
20071 - "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
20072 - "oddq=0x%08x; evenq=0x%08x;\n",
20073 - ah->cal_samples, i,
20074 - ah->totalAdcDcOffsetIOddPhase[i],
20075 - ah->totalAdcDcOffsetIEvenPhase[i],
20076 - ah->totalAdcDcOffsetQOddPhase[i],
20077 - ah->totalAdcDcOffsetQEvenPhase[i]);
20078 - }
20079 -}
20080 -
20081 -static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
20082 -{
20083 - struct ath_common *common = ath9k_hw_common(ah);
20084 - u32 powerMeasQ, powerMeasI, iqCorrMeas;
20085 - u32 qCoffDenom, iCoffDenom;
20086 - int32_t qCoff, iCoff;
20087 - int iqCorrNeg, i;
20088 -
20089 - for (i = 0; i < numChains; i++) {
20090 - powerMeasI = ah->totalPowerMeasI[i];
20091 - powerMeasQ = ah->totalPowerMeasQ[i];
20092 - iqCorrMeas = ah->totalIqCorrMeas[i];
20093 -
20094 - ath_print(common, ATH_DBG_CALIBRATE,
20095 - "Starting IQ Cal and Correction for Chain %d\n",
20096 - i);
20097 -
20098 - ath_print(common, ATH_DBG_CALIBRATE,
20099 - "Orignal: Chn %diq_corr_meas = 0x%08x\n",
20100 - i, ah->totalIqCorrMeas[i]);
20101 -
20102 - iqCorrNeg = 0;
20103 -
20104 - if (iqCorrMeas > 0x80000000) {
20105 - iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
20106 - iqCorrNeg = 1;
20107 - }
20108 -
20109 - ath_print(common, ATH_DBG_CALIBRATE,
20110 - "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
20111 - ath_print(common, ATH_DBG_CALIBRATE,
20112 - "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
20113 - ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
20114 - iqCorrNeg);
20115 -
20116 - iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
20117 - qCoffDenom = powerMeasQ / 64;
20118 -
20119 - if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
20120 - (qCoffDenom != 0)) {
20121 - iCoff = iqCorrMeas / iCoffDenom;
20122 - qCoff = powerMeasI / qCoffDenom - 64;
20123 - ath_print(common, ATH_DBG_CALIBRATE,
20124 - "Chn %d iCoff = 0x%08x\n", i, iCoff);
20125 - ath_print(common, ATH_DBG_CALIBRATE,
20126 - "Chn %d qCoff = 0x%08x\n", i, qCoff);
20127 -
20128 - iCoff = iCoff & 0x3f;
20129 - ath_print(common, ATH_DBG_CALIBRATE,
20130 - "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
20131 - if (iqCorrNeg == 0x0)
20132 - iCoff = 0x40 - iCoff;
20133 -
20134 - if (qCoff > 15)
20135 - qCoff = 15;
20136 - else if (qCoff <= -16)
20137 - qCoff = 16;
20138 -
20139 - ath_print(common, ATH_DBG_CALIBRATE,
20140 - "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
20141 - i, iCoff, qCoff);
20142 -
20143 - REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
20144 - AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
20145 - iCoff);
20146 - REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
20147 - AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
20148 - qCoff);
20149 - ath_print(common, ATH_DBG_CALIBRATE,
20150 - "IQ Cal and Correction done for Chain %d\n",
20151 - i);
20152 - }
20153 - }
20154 -
20155 - REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
20156 - AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
20157 -}
20158 -
20159 -static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
20160 -{
20161 - struct ath_common *common = ath9k_hw_common(ah);
20162 - u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
20163 - u32 qGainMismatch, iGainMismatch, val, i;
20164 -
20165 - for (i = 0; i < numChains; i++) {
20166 - iOddMeasOffset = ah->totalAdcIOddPhase[i];
20167 - iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
20168 - qOddMeasOffset = ah->totalAdcQOddPhase[i];
20169 - qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
20170 -
20171 - ath_print(common, ATH_DBG_CALIBRATE,
20172 - "Starting ADC Gain Cal for Chain %d\n", i);
20173 -
20174 - ath_print(common, ATH_DBG_CALIBRATE,
20175 - "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
20176 - iOddMeasOffset);
20177 - ath_print(common, ATH_DBG_CALIBRATE,
20178 - "Chn %d pwr_meas_even_i = 0x%08x\n", i,
20179 - iEvenMeasOffset);
20180 - ath_print(common, ATH_DBG_CALIBRATE,
20181 - "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
20182 - qOddMeasOffset);
20183 - ath_print(common, ATH_DBG_CALIBRATE,
20184 - "Chn %d pwr_meas_even_q = 0x%08x\n", i,
20185 - qEvenMeasOffset);
20186 -
20187 - if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
20188 - iGainMismatch =
20189 - ((iEvenMeasOffset * 32) /
20190 - iOddMeasOffset) & 0x3f;
20191 - qGainMismatch =
20192 - ((qOddMeasOffset * 32) /
20193 - qEvenMeasOffset) & 0x3f;
20194 -
20195 - ath_print(common, ATH_DBG_CALIBRATE,
20196 - "Chn %d gain_mismatch_i = 0x%08x\n", i,
20197 - iGainMismatch);
20198 - ath_print(common, ATH_DBG_CALIBRATE,
20199 - "Chn %d gain_mismatch_q = 0x%08x\n", i,
20200 - qGainMismatch);
20201 -
20202 - val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
20203 - val &= 0xfffff000;
20204 - val |= (qGainMismatch) | (iGainMismatch << 6);
20205 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
20206 -
20207 - ath_print(common, ATH_DBG_CALIBRATE,
20208 - "ADC Gain Cal done for Chain %d\n", i);
20209 - }
20210 - }
20211 -
20212 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
20213 - REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
20214 - AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
20215 -}
20216 -
20217 -static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
20218 -{
20219 - struct ath_common *common = ath9k_hw_common(ah);
20220 - u32 iOddMeasOffset, iEvenMeasOffset, val, i;
20221 - int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
20222 - const struct ath9k_percal_data *calData =
20223 - ah->cal_list_curr->calData;
20224 - u32 numSamples =
20225 - (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
20226 -
20227 - for (i = 0; i < numChains; i++) {
20228 - iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
20229 - iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
20230 - qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
20231 - qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
20232 -
20233 - ath_print(common, ATH_DBG_CALIBRATE,
20234 - "Starting ADC DC Offset Cal for Chain %d\n", i);
20235 -
20236 - ath_print(common, ATH_DBG_CALIBRATE,
20237 - "Chn %d pwr_meas_odd_i = %d\n", i,
20238 - iOddMeasOffset);
20239 - ath_print(common, ATH_DBG_CALIBRATE,
20240 - "Chn %d pwr_meas_even_i = %d\n", i,
20241 - iEvenMeasOffset);
20242 - ath_print(common, ATH_DBG_CALIBRATE,
20243 - "Chn %d pwr_meas_odd_q = %d\n", i,
20244 - qOddMeasOffset);
20245 - ath_print(common, ATH_DBG_CALIBRATE,
20246 - "Chn %d pwr_meas_even_q = %d\n", i,
20247 - qEvenMeasOffset);
20248 -
20249 - iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
20250 - numSamples) & 0x1ff;
20251 - qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
20252 - numSamples) & 0x1ff;
20253 -
20254 - ath_print(common, ATH_DBG_CALIBRATE,
20255 - "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
20256 - iDcMismatch);
20257 - ath_print(common, ATH_DBG_CALIBRATE,
20258 - "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
20259 - qDcMismatch);
20260 -
20261 - val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
20262 - val &= 0xc0000fff;
20263 - val |= (qDcMismatch << 12) | (iDcMismatch << 21);
20264 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
20265 -
20266 - ath_print(common, ATH_DBG_CALIBRATE,
20267 - "ADC DC Offset Cal done for Chain %d\n", i);
20268 - }
20269 -
20270 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
20271 - REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
20272 - AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
20273 -}
20274 -
20275 /* This is done for the currently configured channel */
20276 bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
20277 {
20278 @@ -614,72 +173,6 @@ void ath9k_hw_start_nfcal(struct ath_hw
20279 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
20280 }
20281
20282 -void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
20283 -{
20284 - struct ath9k_nfcal_hist *h;
20285 - int i, j;
20286 - int32_t val;
20287 - const u32 ar5416_cca_regs[6] = {
20288 - AR_PHY_CCA,
20289 - AR_PHY_CH1_CCA,
20290 - AR_PHY_CH2_CCA,
20291 - AR_PHY_EXT_CCA,
20292 - AR_PHY_CH1_EXT_CCA,
20293 - AR_PHY_CH2_EXT_CCA
20294 - };
20295 - u8 chainmask, rx_chain_status;
20296 -
20297 - rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
20298 - if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
20299 - chainmask = 0x9;
20300 - else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
20301 - if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
20302 - chainmask = 0x1B;
20303 - else
20304 - chainmask = 0x09;
20305 - } else {
20306 - if (rx_chain_status & 0x4)
20307 - chainmask = 0x3F;
20308 - else if (rx_chain_status & 0x2)
20309 - chainmask = 0x1B;
20310 - else
20311 - chainmask = 0x09;
20312 - }
20313 -
20314 - h = ah->nfCalHist;
20315 -
20316 - for (i = 0; i < NUM_NF_READINGS; i++) {
20317 - if (chainmask & (1 << i)) {
20318 - val = REG_READ(ah, ar5416_cca_regs[i]);
20319 - val &= 0xFFFFFE00;
20320 - val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
20321 - REG_WRITE(ah, ar5416_cca_regs[i], val);
20322 - }
20323 - }
20324 -
20325 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
20326 - AR_PHY_AGC_CONTROL_ENABLE_NF);
20327 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
20328 - AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
20329 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
20330 -
20331 - for (j = 0; j < 5; j++) {
20332 - if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
20333 - AR_PHY_AGC_CONTROL_NF) == 0)
20334 - break;
20335 - udelay(50);
20336 - }
20337 -
20338 - for (i = 0; i < NUM_NF_READINGS; i++) {
20339 - if (chainmask & (1 << i)) {
20340 - val = REG_READ(ah, ar5416_cca_regs[i]);
20341 - val &= 0xFFFFFE00;
20342 - val |= (((u32) (-50) << 1) & 0x1ff);
20343 - REG_WRITE(ah, ar5416_cca_regs[i], val);
20344 - }
20345 - }
20346 -}
20347 -
20348 int16_t ath9k_hw_getnf(struct ath_hw *ah,
20349 struct ath9k_channel *chan)
20350 {
20351 @@ -699,7 +192,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah
20352 } else {
20353 ath9k_hw_do_getnf(ah, nfarray);
20354 nf = nfarray[0];
20355 - if (getNoiseFloorThresh(ah, c->band, &nfThresh)
20356 + if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
20357 && nf > nfThresh) {
20358 ath_print(common, ATH_DBG_CALIBRATE,
20359 "noise floor failed detected; "
20360 @@ -757,567 +250,3 @@ s16 ath9k_hw_getchan_noise(struct ath_hw
20361 return nf;
20362 }
20363 EXPORT_SYMBOL(ath9k_hw_getchan_noise);
20364 -
20365 -static void ath9k_olc_temp_compensation_9287(struct ath_hw *ah)
20366 -{
20367 - u32 rddata;
20368 - int32_t delta, currPDADC, slope;
20369 -
20370 - rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
20371 - currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
20372 -
20373 - if (ah->initPDADC == 0 || currPDADC == 0) {
20374 - /*
20375 - * Zero value indicates that no frames have been transmitted yet,
20376 - * can't do temperature compensation until frames are transmitted.
20377 - */
20378 - return;
20379 - } else {
20380 - slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
20381 -
20382 - if (slope == 0) { /* to avoid divide by zero case */
20383 - delta = 0;
20384 - } else {
20385 - delta = ((currPDADC - ah->initPDADC)*4) / slope;
20386 - }
20387 - REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
20388 - AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
20389 - REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
20390 - AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
20391 - }
20392 -}
20393 -
20394 -static void ath9k_olc_temp_compensation(struct ath_hw *ah)
20395 -{
20396 - u32 rddata, i;
20397 - int delta, currPDADC, regval;
20398 -
20399 - if (OLC_FOR_AR9287_10_LATER) {
20400 - ath9k_olc_temp_compensation_9287(ah);
20401 - } else {
20402 - rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
20403 - currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
20404 -
20405 - if (ah->initPDADC == 0 || currPDADC == 0) {
20406 - return;
20407 - } else {
20408 - if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
20409 - delta = (currPDADC - ah->initPDADC + 4) / 8;
20410 - else
20411 - delta = (currPDADC - ah->initPDADC + 5) / 10;
20412 -
20413 - if (delta != ah->PDADCdelta) {
20414 - ah->PDADCdelta = delta;
20415 - for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
20416 - regval = ah->originalGain[i] - delta;
20417 - if (regval < 0)
20418 - regval = 0;
20419 -
20420 - REG_RMW_FIELD(ah,
20421 - AR_PHY_TX_GAIN_TBL1 + i * 4,
20422 - AR_PHY_TX_GAIN, regval);
20423 - }
20424 - }
20425 - }
20426 - }
20427 -}
20428 -
20429 -static void ath9k_hw_9271_pa_cal(struct ath_hw *ah, bool is_reset)
20430 -{
20431 - u32 regVal;
20432 - unsigned int i;
20433 - u32 regList [][2] = {
20434 - { 0x786c, 0 },
20435 - { 0x7854, 0 },
20436 - { 0x7820, 0 },
20437 - { 0x7824, 0 },
20438 - { 0x7868, 0 },
20439 - { 0x783c, 0 },
20440 - { 0x7838, 0 } ,
20441 - { 0x7828, 0 } ,
20442 - };
20443 -
20444 - for (i = 0; i < ARRAY_SIZE(regList); i++)
20445 - regList[i][1] = REG_READ(ah, regList[i][0]);
20446 -
20447 - regVal = REG_READ(ah, 0x7834);
20448 - regVal &= (~(0x1));
20449 - REG_WRITE(ah, 0x7834, regVal);
20450 - regVal = REG_READ(ah, 0x9808);
20451 - regVal |= (0x1 << 27);
20452 - REG_WRITE(ah, 0x9808, regVal);
20453 -
20454 - /* 786c,b23,1, pwddac=1 */
20455 - REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
20456 - /* 7854, b5,1, pdrxtxbb=1 */
20457 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
20458 - /* 7854, b7,1, pdv2i=1 */
20459 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
20460 - /* 7854, b8,1, pddacinterface=1 */
20461 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
20462 - /* 7824,b12,0, offcal=0 */
20463 - REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
20464 - /* 7838, b1,0, pwddb=0 */
20465 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
20466 - /* 7820,b11,0, enpacal=0 */
20467 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
20468 - /* 7820,b25,1, pdpadrv1=0 */
20469 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
20470 - /* 7820,b24,0, pdpadrv2=0 */
20471 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0);
20472 - /* 7820,b23,0, pdpaout=0 */
20473 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
20474 - /* 783c,b14-16,7, padrvgn2tab_0=7 */
20475 - REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
20476 - /*
20477 - * 7838,b29-31,0, padrvgn1tab_0=0
20478 - * does not matter since we turn it off
20479 - */
20480 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
20481 -
20482 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
20483 -
20484 - /* Set:
20485 - * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
20486 - * txon=1,paon=1,oscon=1,synthon_force=1
20487 - */
20488 - REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
20489 - udelay(30);
20490 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
20491 -
20492 - /* find off_6_1; */
20493 - for (i = 6; i > 0; i--) {
20494 - regVal = REG_READ(ah, 0x7834);
20495 - regVal |= (1 << (20 + i));
20496 - REG_WRITE(ah, 0x7834, regVal);
20497 - udelay(1);
20498 - //regVal = REG_READ(ah, 0x7834);
20499 - regVal &= (~(0x1 << (20 + i)));
20500 - regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
20501 - << (20 + i));
20502 - REG_WRITE(ah, 0x7834, regVal);
20503 - }
20504 -
20505 - regVal = (regVal >>20) & 0x7f;
20506 -
20507 - /* Update PA cal info */
20508 - if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
20509 - if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
20510 - ah->pacal_info.max_skipcount =
20511 - 2 * ah->pacal_info.max_skipcount;
20512 - ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
20513 - } else {
20514 - ah->pacal_info.max_skipcount = 1;
20515 - ah->pacal_info.skipcount = 0;
20516 - ah->pacal_info.prev_offset = regVal;
20517 - }
20518 -
20519 - regVal = REG_READ(ah, 0x7834);
20520 - regVal |= 0x1;
20521 - REG_WRITE(ah, 0x7834, regVal);
20522 - regVal = REG_READ(ah, 0x9808);
20523 - regVal &= (~(0x1 << 27));
20524 - REG_WRITE(ah, 0x9808, regVal);
20525 -
20526 - for (i = 0; i < ARRAY_SIZE(regList); i++)
20527 - REG_WRITE(ah, regList[i][0], regList[i][1]);
20528 -}
20529 -
20530 -static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
20531 -{
20532 - struct ath_common *common = ath9k_hw_common(ah);
20533 - u32 regVal;
20534 - int i, offset, offs_6_1, offs_0;
20535 - u32 ccomp_org, reg_field;
20536 - u32 regList[][2] = {
20537 - { 0x786c, 0 },
20538 - { 0x7854, 0 },
20539 - { 0x7820, 0 },
20540 - { 0x7824, 0 },
20541 - { 0x7868, 0 },
20542 - { 0x783c, 0 },
20543 - { 0x7838, 0 },
20544 - };
20545 -
20546 - ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
20547 -
20548 - /* PA CAL is not needed for high power solution */
20549 - if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
20550 - AR5416_EEP_TXGAIN_HIGH_POWER)
20551 - return;
20552 -
20553 - if (AR_SREV_9285_11(ah)) {
20554 - REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
20555 - udelay(10);
20556 - }
20557 -
20558 - for (i = 0; i < ARRAY_SIZE(regList); i++)
20559 - regList[i][1] = REG_READ(ah, regList[i][0]);
20560 -
20561 - regVal = REG_READ(ah, 0x7834);
20562 - regVal &= (~(0x1));
20563 - REG_WRITE(ah, 0x7834, regVal);
20564 - regVal = REG_READ(ah, 0x9808);
20565 - regVal |= (0x1 << 27);
20566 - REG_WRITE(ah, 0x9808, regVal);
20567 -
20568 - REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
20569 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
20570 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
20571 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
20572 - REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
20573 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
20574 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
20575 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
20576 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
20577 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
20578 - REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
20579 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
20580 - ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
20581 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
20582 -
20583 - REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
20584 - udelay(30);
20585 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
20586 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
20587 -
20588 - for (i = 6; i > 0; i--) {
20589 - regVal = REG_READ(ah, 0x7834);
20590 - regVal |= (1 << (19 + i));
20591 - REG_WRITE(ah, 0x7834, regVal);
20592 - udelay(1);
20593 - regVal = REG_READ(ah, 0x7834);
20594 - regVal &= (~(0x1 << (19 + i)));
20595 - reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
20596 - regVal |= (reg_field << (19 + i));
20597 - REG_WRITE(ah, 0x7834, regVal);
20598 - }
20599 -
20600 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
20601 - udelay(1);
20602 - reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
20603 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
20604 - offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
20605 - offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
20606 -
20607 - offset = (offs_6_1<<1) | offs_0;
20608 - offset = offset - 0;
20609 - offs_6_1 = offset>>1;
20610 - offs_0 = offset & 1;
20611 -
20612 - if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
20613 - if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
20614 - ah->pacal_info.max_skipcount =
20615 - 2 * ah->pacal_info.max_skipcount;
20616 - ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
20617 - } else {
20618 - ah->pacal_info.max_skipcount = 1;
20619 - ah->pacal_info.skipcount = 0;
20620 - ah->pacal_info.prev_offset = offset;
20621 - }
20622 -
20623 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
20624 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
20625 -
20626 - regVal = REG_READ(ah, 0x7834);
20627 - regVal |= 0x1;
20628 - REG_WRITE(ah, 0x7834, regVal);
20629 - regVal = REG_READ(ah, 0x9808);
20630 - regVal &= (~(0x1 << 27));
20631 - REG_WRITE(ah, 0x9808, regVal);
20632 -
20633 - for (i = 0; i < ARRAY_SIZE(regList); i++)
20634 - REG_WRITE(ah, regList[i][0], regList[i][1]);
20635 -
20636 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
20637 -
20638 - if (AR_SREV_9285_11(ah))
20639 - REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
20640 -
20641 -}
20642 -
20643 -bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
20644 - u8 rxchainmask, bool longcal)
20645 -{
20646 - bool iscaldone = true;
20647 - struct ath9k_cal_list *currCal = ah->cal_list_curr;
20648 -
20649 - if (currCal &&
20650 - (currCal->calState == CAL_RUNNING ||
20651 - currCal->calState == CAL_WAITING)) {
20652 - iscaldone = ath9k_hw_per_calibration(ah, chan,
20653 - rxchainmask, currCal);
20654 - if (iscaldone) {
20655 - ah->cal_list_curr = currCal = currCal->calNext;
20656 -
20657 - if (currCal->calState == CAL_WAITING) {
20658 - iscaldone = false;
20659 - ath9k_hw_reset_calibration(ah, currCal);
20660 - }
20661 - }
20662 - }
20663 -
20664 - /* Do NF cal only at longer intervals */
20665 - if (longcal) {
20666 - /* Do periodic PAOffset Cal */
20667 - if (AR_SREV_9271(ah)) {
20668 - if (!ah->pacal_info.skipcount)
20669 - ath9k_hw_9271_pa_cal(ah, false);
20670 - else
20671 - ah->pacal_info.skipcount--;
20672 - } else if (AR_SREV_9285_11_OR_LATER(ah)) {
20673 - if (!ah->pacal_info.skipcount)
20674 - ath9k_hw_9285_pa_cal(ah, false);
20675 - else
20676 - ah->pacal_info.skipcount--;
20677 - }
20678 -
20679 - if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER)
20680 - ath9k_olc_temp_compensation(ah);
20681 -
20682 - /* Get the value from the previous NF cal and update history buffer */
20683 - ath9k_hw_getnf(ah, chan);
20684 -
20685 - /*
20686 - * Load the NF from history buffer of the current channel.
20687 - * NF is slow time-variant, so it is OK to use a historical value.
20688 - */
20689 - ath9k_hw_loadnf(ah, ah->curchan);
20690 -
20691 - ath9k_hw_start_nfcal(ah);
20692 - }
20693 -
20694 - return iscaldone;
20695 -}
20696 -EXPORT_SYMBOL(ath9k_hw_calibrate);
20697 -
20698 -/* Carrier leakage Calibration fix */
20699 -static bool ar9285_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
20700 -{
20701 - struct ath_common *common = ath9k_hw_common(ah);
20702 -
20703 - REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
20704 - if (IS_CHAN_HT20(chan)) {
20705 - REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
20706 - REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
20707 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
20708 - AR_PHY_AGC_CONTROL_FLTR_CAL);
20709 - REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
20710 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
20711 - if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
20712 - AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
20713 - ath_print(common, ATH_DBG_CALIBRATE, "offset "
20714 - "calibration failed to complete in "
20715 - "1ms; noisy ??\n");
20716 - return false;
20717 - }
20718 - REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
20719 - REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
20720 - REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
20721 - }
20722 - REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
20723 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
20724 - REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
20725 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
20726 - if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
20727 - 0, AH_WAIT_TIMEOUT)) {
20728 - ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
20729 - "failed to complete in 1ms; noisy ??\n");
20730 - return false;
20731 - }
20732 -
20733 - REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
20734 - REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
20735 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
20736 -
20737 - return true;
20738 -}
20739 -
20740 -static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
20741 -{
20742 - int i;
20743 - u_int32_t txgain_max;
20744 - u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
20745 - u_int32_t reg_clc_I0, reg_clc_Q0;
20746 - u_int32_t i0_num = 0;
20747 - u_int32_t q0_num = 0;
20748 - u_int32_t total_num = 0;
20749 - u_int32_t reg_rf2g5_org;
20750 - bool retv = true;
20751 -
20752 - if (!(ar9285_cl_cal(ah, chan)))
20753 - return false;
20754 -
20755 - txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
20756 - AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
20757 -
20758 - for (i = 0; i < (txgain_max+1); i++) {
20759 - clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
20760 - AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
20761 - if (!(gain_mask & (1 << clc_gain))) {
20762 - gain_mask |= (1 << clc_gain);
20763 - clc_num++;
20764 - }
20765 - }
20766 -
20767 - for (i = 0; i < clc_num; i++) {
20768 - reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
20769 - & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
20770 - reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
20771 - & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
20772 - if (reg_clc_I0 == 0)
20773 - i0_num++;
20774 -
20775 - if (reg_clc_Q0 == 0)
20776 - q0_num++;
20777 - }
20778 - total_num = i0_num + q0_num;
20779 - if (total_num > AR9285_CLCAL_REDO_THRESH) {
20780 - reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
20781 - if (AR_SREV_9285E_20(ah)) {
20782 - REG_WRITE(ah, AR9285_RF2G5,
20783 - (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
20784 - AR9285_RF2G5_IC50TX_XE_SET);
20785 - } else {
20786 - REG_WRITE(ah, AR9285_RF2G5,
20787 - (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
20788 - AR9285_RF2G5_IC50TX_SET);
20789 - }
20790 - retv = ar9285_cl_cal(ah, chan);
20791 - REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
20792 - }
20793 - return retv;
20794 -}
20795 -
20796 -bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
20797 -{
20798 - struct ath_common *common = ath9k_hw_common(ah);
20799 -
20800 - if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
20801 - if (!ar9285_clc(ah, chan))
20802 - return false;
20803 - } else {
20804 - if (AR_SREV_9280_10_OR_LATER(ah)) {
20805 - if (!AR_SREV_9287_10_OR_LATER(ah))
20806 - REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
20807 - AR_PHY_ADC_CTL_OFF_PWDADC);
20808 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
20809 - AR_PHY_AGC_CONTROL_FLTR_CAL);
20810 - }
20811 -
20812 - /* Calibrate the AGC */
20813 - REG_WRITE(ah, AR_PHY_AGC_CONTROL,
20814 - REG_READ(ah, AR_PHY_AGC_CONTROL) |
20815 - AR_PHY_AGC_CONTROL_CAL);
20816 -
20817 - /* Poll for offset calibration complete */
20818 - if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
20819 - 0, AH_WAIT_TIMEOUT)) {
20820 - ath_print(common, ATH_DBG_CALIBRATE,
20821 - "offset calibration failed to "
20822 - "complete in 1ms; noisy environment?\n");
20823 - return false;
20824 - }
20825 -
20826 - if (AR_SREV_9280_10_OR_LATER(ah)) {
20827 - if (!AR_SREV_9287_10_OR_LATER(ah))
20828 - REG_SET_BIT(ah, AR_PHY_ADC_CTL,
20829 - AR_PHY_ADC_CTL_OFF_PWDADC);
20830 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
20831 - AR_PHY_AGC_CONTROL_FLTR_CAL);
20832 - }
20833 - }
20834 -
20835 - /* Do PA Calibration */
20836 - if (AR_SREV_9271(ah))
20837 - ath9k_hw_9271_pa_cal(ah, true);
20838 - else if (AR_SREV_9285_11_OR_LATER(ah))
20839 - ath9k_hw_9285_pa_cal(ah, true);
20840 -
20841 - /* Do NF Calibration after DC offset and other calibrations */
20842 - REG_WRITE(ah, AR_PHY_AGC_CONTROL,
20843 - REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
20844 -
20845 - ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
20846 -
20847 - /* Enable IQ, ADC Gain and ADC DC offset CALs */
20848 - if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
20849 - if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
20850 - INIT_CAL(&ah->adcgain_caldata);
20851 - INSERT_CAL(ah, &ah->adcgain_caldata);
20852 - ath_print(common, ATH_DBG_CALIBRATE,
20853 - "enabling ADC Gain Calibration.\n");
20854 - }
20855 - if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
20856 - INIT_CAL(&ah->adcdc_caldata);
20857 - INSERT_CAL(ah, &ah->adcdc_caldata);
20858 - ath_print(common, ATH_DBG_CALIBRATE,
20859 - "enabling ADC DC Calibration.\n");
20860 - }
20861 - if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
20862 - INIT_CAL(&ah->iq_caldata);
20863 - INSERT_CAL(ah, &ah->iq_caldata);
20864 - ath_print(common, ATH_DBG_CALIBRATE,
20865 - "enabling IQ Calibration.\n");
20866 - }
20867 -
20868 - ah->cal_list_curr = ah->cal_list;
20869 -
20870 - if (ah->cal_list_curr)
20871 - ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
20872 - }
20873 -
20874 - chan->CalValid = 0;
20875 -
20876 - return true;
20877 -}
20878 -
20879 -const struct ath9k_percal_data iq_cal_multi_sample = {
20880 - IQ_MISMATCH_CAL,
20881 - MAX_CAL_SAMPLES,
20882 - PER_MIN_LOG_COUNT,
20883 - ath9k_hw_iqcal_collect,
20884 - ath9k_hw_iqcalibrate
20885 -};
20886 -const struct ath9k_percal_data iq_cal_single_sample = {
20887 - IQ_MISMATCH_CAL,
20888 - MIN_CAL_SAMPLES,
20889 - PER_MAX_LOG_COUNT,
20890 - ath9k_hw_iqcal_collect,
20891 - ath9k_hw_iqcalibrate
20892 -};
20893 -const struct ath9k_percal_data adc_gain_cal_multi_sample = {
20894 - ADC_GAIN_CAL,
20895 - MAX_CAL_SAMPLES,
20896 - PER_MIN_LOG_COUNT,
20897 - ath9k_hw_adc_gaincal_collect,
20898 - ath9k_hw_adc_gaincal_calibrate
20899 -};
20900 -const struct ath9k_percal_data adc_gain_cal_single_sample = {
20901 - ADC_GAIN_CAL,
20902 - MIN_CAL_SAMPLES,
20903 - PER_MAX_LOG_COUNT,
20904 - ath9k_hw_adc_gaincal_collect,
20905 - ath9k_hw_adc_gaincal_calibrate
20906 -};
20907 -const struct ath9k_percal_data adc_dc_cal_multi_sample = {
20908 - ADC_DC_CAL,
20909 - MAX_CAL_SAMPLES,
20910 - PER_MIN_LOG_COUNT,
20911 - ath9k_hw_adc_dccal_collect,
20912 - ath9k_hw_adc_dccal_calibrate
20913 -};
20914 -const struct ath9k_percal_data adc_dc_cal_single_sample = {
20915 - ADC_DC_CAL,
20916 - MIN_CAL_SAMPLES,
20917 - PER_MAX_LOG_COUNT,
20918 - ath9k_hw_adc_dccal_collect,
20919 - ath9k_hw_adc_dccal_calibrate
20920 -};
20921 -const struct ath9k_percal_data adc_init_dc_cal = {
20922 - ADC_DC_INIT_CAL,
20923 - MIN_CAL_SAMPLES,
20924 - INIT_LOG_COUNT,
20925 - ath9k_hw_adc_dccal_collect,
20926 - ath9k_hw_adc_dccal_calibrate
20927 -};
20928 --- a/drivers/net/wireless/ath/ath9k/calib.h
20929 +++ b/drivers/net/wireless/ath/ath9k/calib.h
20930 @@ -19,14 +19,6 @@
20931
20932 #include "hw.h"
20933
20934 -extern const struct ath9k_percal_data iq_cal_multi_sample;
20935 -extern const struct ath9k_percal_data iq_cal_single_sample;
20936 -extern const struct ath9k_percal_data adc_gain_cal_multi_sample;
20937 -extern const struct ath9k_percal_data adc_gain_cal_single_sample;
20938 -extern const struct ath9k_percal_data adc_dc_cal_multi_sample;
20939 -extern const struct ath9k_percal_data adc_dc_cal_single_sample;
20940 -extern const struct ath9k_percal_data adc_init_dc_cal;
20941 -
20942 #define AR_PHY_CCA_MAX_AR5416_GOOD_VALUE -85
20943 #define AR_PHY_CCA_MAX_AR9280_GOOD_VALUE -112
20944 #define AR_PHY_CCA_MAX_AR9285_GOOD_VALUE -118
20945 @@ -76,7 +68,8 @@ enum ath9k_cal_types {
20946 ADC_DC_INIT_CAL = 0x1,
20947 ADC_GAIN_CAL = 0x2,
20948 ADC_DC_CAL = 0x4,
20949 - IQ_MISMATCH_CAL = 0x8
20950 + IQ_MISMATCH_CAL = 0x8,
20951 + TEMP_COMP_CAL = 0x10,
20952 };
20953
20954 enum ath9k_cal_state {
20955 @@ -122,14 +115,12 @@ struct ath9k_pacal_info{
20956
20957 bool ath9k_hw_reset_calvalid(struct ath_hw *ah);
20958 void ath9k_hw_start_nfcal(struct ath_hw *ah);
20959 -void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan);
20960 int16_t ath9k_hw_getnf(struct ath_hw *ah,
20961 struct ath9k_channel *chan);
20962 void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah);
20963 s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan);
20964 -bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
20965 - u8 rxchainmask, bool longcal);
20966 -bool ath9k_hw_init_cal(struct ath_hw *ah,
20967 - struct ath9k_channel *chan);
20968 +void ath9k_hw_reset_calibration(struct ath_hw *ah,
20969 + struct ath9k_cal_list *currCal);
20970 +
20971
20972 #endif /* CALIB_H */
20973 --- a/drivers/net/wireless/ath/ath9k/common.h
20974 +++ b/drivers/net/wireless/ath/ath9k/common.h
20975 @@ -20,6 +20,7 @@
20976 #include "../debug.h"
20977
20978 #include "hw.h"
20979 +#include "hw-ops.h"
20980
20981 /* Common header for Atheros 802.11n base driver cores */
20982
20983 @@ -76,11 +77,12 @@ struct ath_buf {
20984 an aggregate) */
20985 struct ath_buf *bf_next; /* next subframe in the aggregate */
20986 struct sk_buff *bf_mpdu; /* enclosing frame structure */
20987 - struct ath_desc *bf_desc; /* virtual addr of desc */
20988 + void *bf_desc; /* virtual addr of desc */
20989 dma_addr_t bf_daddr; /* physical addr of desc */
20990 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
20991 bool bf_stale;
20992 bool bf_isnullfunc;
20993 + bool bf_tx_aborted;
20994 u16 bf_flags;
20995 struct ath_buf_state bf_state;
20996 dma_addr_t bf_dmacontext;
20997 --- a/drivers/net/wireless/ath/ath9k/debug.c
20998 +++ b/drivers/net/wireless/ath/ath9k/debug.c
20999 @@ -180,8 +180,15 @@ void ath_debug_stat_interrupt(struct ath
21000 {
21001 if (status)
21002 sc->debug.stats.istats.total++;
21003 - if (status & ATH9K_INT_RX)
21004 - sc->debug.stats.istats.rxok++;
21005 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
21006 + if (status & ATH9K_INT_RXLP)
21007 + sc->debug.stats.istats.rxlp++;
21008 + if (status & ATH9K_INT_RXHP)
21009 + sc->debug.stats.istats.rxhp++;
21010 + } else {
21011 + if (status & ATH9K_INT_RX)
21012 + sc->debug.stats.istats.rxok++;
21013 + }
21014 if (status & ATH9K_INT_RXEOL)
21015 sc->debug.stats.istats.rxeol++;
21016 if (status & ATH9K_INT_RXORN)
21017 @@ -223,8 +230,15 @@ static ssize_t read_file_interrupt(struc
21018 char buf[512];
21019 unsigned int len = 0;
21020
21021 - len += snprintf(buf + len, sizeof(buf) - len,
21022 - "%8s: %10u\n", "RX", sc->debug.stats.istats.rxok);
21023 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
21024 + len += snprintf(buf + len, sizeof(buf) - len,
21025 + "%8s: %10u\n", "RXLP", sc->debug.stats.istats.rxlp);
21026 + len += snprintf(buf + len, sizeof(buf) - len,
21027 + "%8s: %10u\n", "RXHP", sc->debug.stats.istats.rxhp);
21028 + } else {
21029 + len += snprintf(buf + len, sizeof(buf) - len,
21030 + "%8s: %10u\n", "RX", sc->debug.stats.istats.rxok);
21031 + }
21032 len += snprintf(buf + len, sizeof(buf) - len,
21033 "%8s: %10u\n", "RXEOL", sc->debug.stats.istats.rxeol);
21034 len += snprintf(buf + len, sizeof(buf) - len,
21035 --- a/drivers/net/wireless/ath/ath9k/debug.h
21036 +++ b/drivers/net/wireless/ath/ath9k/debug.h
21037 @@ -35,6 +35,8 @@ struct ath_buf;
21038 * struct ath_interrupt_stats - Contains statistics about interrupts
21039 * @total: Total no. of interrupts generated so far
21040 * @rxok: RX with no errors
21041 + * @rxlp: RX with low priority RX
21042 + * @rxhp: RX with high priority, uapsd only
21043 * @rxeol: RX with no more RXDESC available
21044 * @rxorn: RX FIFO overrun
21045 * @txok: TX completed at the requested rate
21046 @@ -55,6 +57,8 @@ struct ath_buf;
21047 struct ath_interrupt_stats {
21048 u32 total;
21049 u32 rxok;
21050 + u32 rxlp;
21051 + u32 rxhp;
21052 u32 rxeol;
21053 u32 rxorn;
21054 u32 txok;
21055 --- a/drivers/net/wireless/ath/ath9k/eeprom.c
21056 +++ b/drivers/net/wireless/ath/ath9k/eeprom.c
21057 @@ -256,14 +256,13 @@ int ath9k_hw_eeprom_init(struct ath_hw *
21058 {
21059 int status;
21060
21061 - if (AR_SREV_9287(ah)) {
21062 - ah->eep_map = EEP_MAP_AR9287;
21063 - ah->eep_ops = &eep_AR9287_ops;
21064 + if (AR_SREV_9300_20_OR_LATER(ah))
21065 + ah->eep_ops = &eep_ar9300_ops;
21066 + else if (AR_SREV_9287(ah)) {
21067 + ah->eep_ops = &eep_ar9287_ops;
21068 } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
21069 - ah->eep_map = EEP_MAP_4KBITS;
21070 ah->eep_ops = &eep_4k_ops;
21071 } else {
21072 - ah->eep_map = EEP_MAP_DEFAULT;
21073 ah->eep_ops = &eep_def_ops;
21074 }
21075
21076 --- a/drivers/net/wireless/ath/ath9k/eeprom.h
21077 +++ b/drivers/net/wireless/ath/ath9k/eeprom.h
21078 @@ -19,6 +19,7 @@
21079
21080 #include "../ath.h"
21081 #include <net/cfg80211.h>
21082 +#include "ar9003_eeprom.h"
21083
21084 #define AH_USE_EEPROM 0x1
21085
21086 @@ -93,7 +94,6 @@
21087 */
21088 #define AR9285_RDEXT_DEFAULT 0x1F
21089
21090 -#define AR_EEPROM_MAC(i) (0x1d+(i))
21091 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
21092 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
21093 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
21094 @@ -155,6 +155,7 @@
21095 #define AR5416_BCHAN_UNUSED 0xFF
21096 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
21097 #define AR5416_MAX_CHAINS 3
21098 +#define AR9300_MAX_CHAINS 3
21099 #define AR5416_PWR_TABLE_OFFSET_DB -5
21100
21101 /* Rx gain type values */
21102 @@ -249,16 +250,20 @@ enum eeprom_param {
21103 EEP_MINOR_REV,
21104 EEP_TX_MASK,
21105 EEP_RX_MASK,
21106 + EEP_FSTCLK_5G,
21107 EEP_RXGAIN_TYPE,
21108 - EEP_TXGAIN_TYPE,
21109 EEP_OL_PWRCTRL,
21110 + EEP_TXGAIN_TYPE,
21111 EEP_RC_CHAIN_MASK,
21112 EEP_DAC_HPWR_5G,
21113 EEP_FRAC_N_5G,
21114 EEP_DEV_TYPE,
21115 EEP_TEMPSENSE_SLOPE,
21116 EEP_TEMPSENSE_SLOPE_PAL_ON,
21117 - EEP_PWR_TABLE_OFFSET
21118 + EEP_PWR_TABLE_OFFSET,
21119 + EEP_DRIVE_STRENGTH,
21120 + EEP_INTERNAL_REGULATOR,
21121 + EEP_SWREG
21122 };
21123
21124 enum ar5416_rates {
21125 @@ -656,13 +661,6 @@ struct ath9k_country_entry {
21126 u8 iso[3];
21127 };
21128
21129 -enum ath9k_eep_map {
21130 - EEP_MAP_DEFAULT = 0x0,
21131 - EEP_MAP_4KBITS,
21132 - EEP_MAP_AR9287,
21133 - EEP_MAP_MAX
21134 -};
21135 -
21136 struct eeprom_ops {
21137 int (*check_eeprom)(struct ath_hw *hw);
21138 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
21139 @@ -713,6 +711,8 @@ int ath9k_hw_eeprom_init(struct ath_hw *
21140
21141 extern const struct eeprom_ops eep_def_ops;
21142 extern const struct eeprom_ops eep_4k_ops;
21143 -extern const struct eeprom_ops eep_AR9287_ops;
21144 +extern const struct eeprom_ops eep_ar9287_ops;
21145 +extern const struct eeprom_ops eep_ar9287_ops;
21146 +extern const struct eeprom_ops eep_ar9300_ops;
21147
21148 #endif /* EEPROM_H */
21149 --- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
21150 +++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
21151 @@ -15,6 +15,7 @@
21152 */
21153
21154 #include "hw.h"
21155 +#include "ar9002_phy.h"
21156
21157 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
21158 {
21159 @@ -182,11 +183,11 @@ static u32 ath9k_hw_4k_get_eeprom(struct
21160 switch (param) {
21161 case EEP_NFTHRESH_2:
21162 return pModal->noiseFloorThreshCh[0];
21163 - case AR_EEPROM_MAC(0):
21164 + case EEP_MAC_LSW:
21165 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
21166 - case AR_EEPROM_MAC(1):
21167 + case EEP_MAC_MID:
21168 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
21169 - case AR_EEPROM_MAC(2):
21170 + case EEP_MAC_MSW:
21171 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
21172 case EEP_REG_0:
21173 return pBase->regDmn[0];
21174 --- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
21175 +++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
21176 @@ -15,6 +15,7 @@
21177 */
21178
21179 #include "hw.h"
21180 +#include "ar9002_phy.h"
21181
21182 static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
21183 {
21184 @@ -172,11 +173,11 @@ static u32 ath9k_hw_AR9287_get_eeprom(st
21185 switch (param) {
21186 case EEP_NFTHRESH_2:
21187 return pModal->noiseFloorThreshCh[0];
21188 - case AR_EEPROM_MAC(0):
21189 + case EEP_MAC_LSW:
21190 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
21191 - case AR_EEPROM_MAC(1):
21192 + case EEP_MAC_MID:
21193 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
21194 - case AR_EEPROM_MAC(2):
21195 + case EEP_MAC_MSW:
21196 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
21197 case EEP_REG_0:
21198 return pBase->regDmn[0];
21199 @@ -1169,7 +1170,7 @@ static u16 ath9k_hw_AR9287_get_spur_chan
21200 #undef EEP_MAP9287_SPURCHAN
21201 }
21202
21203 -const struct eeprom_ops eep_AR9287_ops = {
21204 +const struct eeprom_ops eep_ar9287_ops = {
21205 .check_eeprom = ath9k_hw_AR9287_check_eeprom,
21206 .get_eeprom = ath9k_hw_AR9287_get_eeprom,
21207 .fill_eeprom = ath9k_hw_AR9287_fill_eeprom,
21208 --- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
21209 +++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
21210 @@ -15,6 +15,7 @@
21211 */
21212
21213 #include "hw.h"
21214 +#include "ar9002_phy.h"
21215
21216 static void ath9k_get_txgain_index(struct ath_hw *ah,
21217 struct ath9k_channel *chan,
21218 @@ -222,6 +223,12 @@ static int ath9k_hw_def_check_eeprom(str
21219 return -EINVAL;
21220 }
21221
21222 + /* Enable fixup for AR_AN_TOP2 if necessary */
21223 + if (AR_SREV_9280_10_OR_LATER(ah) &&
21224 + (eep->baseEepHeader.version & 0xff) > 0x0a &&
21225 + eep->baseEepHeader.pwdclkind == 0)
21226 + ah->need_an_top2_fixup = 1;
21227 +
21228 return 0;
21229 }
21230
21231 @@ -237,11 +244,11 @@ static u32 ath9k_hw_def_get_eeprom(struc
21232 return pModal[0].noiseFloorThreshCh[0];
21233 case EEP_NFTHRESH_2:
21234 return pModal[1].noiseFloorThreshCh[0];
21235 - case AR_EEPROM_MAC(0):
21236 + case EEP_MAC_LSW:
21237 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
21238 - case AR_EEPROM_MAC(1):
21239 + case EEP_MAC_MID:
21240 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
21241 - case AR_EEPROM_MAC(2):
21242 + case EEP_MAC_MSW:
21243 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
21244 case EEP_REG_0:
21245 return pBase->regDmn[0];
21246 --- /dev/null
21247 +++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
21248 @@ -0,0 +1,279 @@
21249 +/*
21250 + * Copyright (c) 2010 Atheros Communications Inc.
21251 + *
21252 + * Permission to use, copy, modify, and/or distribute this software for any
21253 + * purpose with or without fee is hereby granted, provided that the above
21254 + * copyright notice and this permission notice appear in all copies.
21255 + *
21256 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
21257 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
21258 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
21259 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
21260 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
21261 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
21262 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21263 + */
21264 +
21265 +#ifndef ATH9K_HW_OPS_H
21266 +#define ATH9K_HW_OPS_H
21267 +
21268 +#include "hw.h"
21269 +
21270 +/* Hardware core and driver accessible callbacks */
21271 +
21272 +static inline void ath9k_hw_configpcipowersave(struct ath_hw *ah,
21273 + int restore,
21274 + int power_off)
21275 +{
21276 + ath9k_hw_ops(ah)->config_pci_powersave(ah, restore, power_off);
21277 +}
21278 +
21279 +static inline void ath9k_hw_rxena(struct ath_hw *ah)
21280 +{
21281 + ath9k_hw_ops(ah)->rx_enable(ah);
21282 +}
21283 +
21284 +static inline void ath9k_hw_set_desc_link(struct ath_hw *ah, void *ds,
21285 + u32 link)
21286 +{
21287 + ath9k_hw_ops(ah)->set_desc_link(ds, link);
21288 +}
21289 +
21290 +static inline void ath9k_hw_get_desc_link(struct ath_hw *ah, void *ds,
21291 + u32 **link)
21292 +{
21293 + ath9k_hw_ops(ah)->get_desc_link(ds, link);
21294 +}
21295 +static inline bool ath9k_hw_calibrate(struct ath_hw *ah,
21296 + struct ath9k_channel *chan,
21297 + u8 rxchainmask,
21298 + bool longcal)
21299 +{
21300 + return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal);
21301 +}
21302 +
21303 +static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
21304 +{
21305 + return ath9k_hw_ops(ah)->get_isr(ah, masked);
21306 +}
21307 +
21308 +static inline void ath9k_hw_filltxdesc(struct ath_hw *ah, void *ds, u32 seglen,
21309 + bool is_firstseg, bool is_lastseg,
21310 + const void *ds0, dma_addr_t buf_addr,
21311 + unsigned int qcu)
21312 +{
21313 + ath9k_hw_ops(ah)->fill_txdesc(ah, ds, seglen, is_firstseg, is_lastseg,
21314 + ds0, buf_addr, qcu);
21315 +}
21316 +
21317 +static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds,
21318 + struct ath_tx_status *ts)
21319 +{
21320 + return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts);
21321 +}
21322 +
21323 +static inline void ath9k_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
21324 + u32 pktLen, enum ath9k_pkt_type type,
21325 + u32 txPower, u32 keyIx,
21326 + enum ath9k_key_type keyType,
21327 + u32 flags)
21328 +{
21329 + ath9k_hw_ops(ah)->set11n_txdesc(ah, ds, pktLen, type, txPower, keyIx,
21330 + keyType, flags);
21331 +}
21332 +
21333 +static inline void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
21334 + void *lastds,
21335 + u32 durUpdateEn, u32 rtsctsRate,
21336 + u32 rtsctsDuration,
21337 + struct ath9k_11n_rate_series series[],
21338 + u32 nseries, u32 flags)
21339 +{
21340 + ath9k_hw_ops(ah)->set11n_ratescenario(ah, ds, lastds, durUpdateEn,
21341 + rtsctsRate, rtsctsDuration, series,
21342 + nseries, flags);
21343 +}
21344 +
21345 +static inline void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
21346 + u32 aggrLen)
21347 +{
21348 + ath9k_hw_ops(ah)->set11n_aggr_first(ah, ds, aggrLen);
21349 +}
21350 +
21351 +static inline void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
21352 + u32 numDelims)
21353 +{
21354 + ath9k_hw_ops(ah)->set11n_aggr_middle(ah, ds, numDelims);
21355 +}
21356 +
21357 +static inline void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
21358 +{
21359 + ath9k_hw_ops(ah)->set11n_aggr_last(ah, ds);
21360 +}
21361 +
21362 +static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
21363 +{
21364 + ath9k_hw_ops(ah)->clr11n_aggr(ah, ds);
21365 +}
21366 +
21367 +static inline void ath9k_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
21368 + u32 burstDuration)
21369 +{
21370 + ath9k_hw_ops(ah)->set11n_burstduration(ah, ds, burstDuration);
21371 +}
21372 +
21373 +static inline void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
21374 + u32 vmf)
21375 +{
21376 + ath9k_hw_ops(ah)->set11n_virtualmorefrag(ah, ds, vmf);
21377 +}
21378 +
21379 +/* Private hardware call ops */
21380 +
21381 +/* PHY ops */
21382 +
21383 +static inline int ath9k_hw_rf_set_freq(struct ath_hw *ah,
21384 + struct ath9k_channel *chan)
21385 +{
21386 + return ath9k_hw_private_ops(ah)->rf_set_freq(ah, chan);
21387 +}
21388 +
21389 +static inline void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah,
21390 + struct ath9k_channel *chan)
21391 +{
21392 + ath9k_hw_private_ops(ah)->spur_mitigate_freq(ah, chan);
21393 +}
21394 +
21395 +static inline int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
21396 +{
21397 + if (!ath9k_hw_private_ops(ah)->rf_alloc_ext_banks)
21398 + return 0;
21399 +
21400 + return ath9k_hw_private_ops(ah)->rf_alloc_ext_banks(ah);
21401 +}
21402 +
21403 +static inline void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
21404 +{
21405 + if (!ath9k_hw_private_ops(ah)->rf_free_ext_banks)
21406 + return;
21407 +
21408 + ath9k_hw_private_ops(ah)->rf_free_ext_banks(ah);
21409 +}
21410 +
21411 +static inline bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
21412 + struct ath9k_channel *chan,
21413 + u16 modesIndex)
21414 +{
21415 + if (!ath9k_hw_private_ops(ah)->set_rf_regs)
21416 + return true;
21417 +
21418 + return ath9k_hw_private_ops(ah)->set_rf_regs(ah, chan, modesIndex);
21419 +}
21420 +
21421 +static inline void ath9k_hw_init_bb(struct ath_hw *ah,
21422 + struct ath9k_channel *chan)
21423 +{
21424 + return ath9k_hw_private_ops(ah)->init_bb(ah, chan);
21425 +}
21426 +
21427 +static inline void ath9k_hw_set_channel_regs(struct ath_hw *ah,
21428 + struct ath9k_channel *chan)
21429 +{
21430 + return ath9k_hw_private_ops(ah)->set_channel_regs(ah, chan);
21431 +}
21432 +
21433 +static inline int ath9k_hw_process_ini(struct ath_hw *ah,
21434 + struct ath9k_channel *chan)
21435 +{
21436 + return ath9k_hw_private_ops(ah)->process_ini(ah, chan);
21437 +}
21438 +
21439 +static inline void ath9k_olc_init(struct ath_hw *ah)
21440 +{
21441 + if (!ath9k_hw_private_ops(ah)->olc_init)
21442 + return;
21443 +
21444 + return ath9k_hw_private_ops(ah)->olc_init(ah);
21445 +}
21446 +
21447 +static inline void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
21448 +{
21449 + return ath9k_hw_private_ops(ah)->set_rfmode(ah, chan);
21450 +}
21451 +
21452 +static inline void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
21453 +{
21454 + return ath9k_hw_private_ops(ah)->mark_phy_inactive(ah);
21455 +}
21456 +
21457 +static inline void ath9k_hw_set_delta_slope(struct ath_hw *ah,
21458 + struct ath9k_channel *chan)
21459 +{
21460 + return ath9k_hw_private_ops(ah)->set_delta_slope(ah, chan);
21461 +}
21462 +
21463 +static inline bool ath9k_hw_rfbus_req(struct ath_hw *ah)
21464 +{
21465 + return ath9k_hw_private_ops(ah)->rfbus_req(ah);
21466 +}
21467 +
21468 +static inline void ath9k_hw_rfbus_done(struct ath_hw *ah)
21469 +{
21470 + return ath9k_hw_private_ops(ah)->rfbus_done(ah);
21471 +}
21472 +
21473 +static inline void ath9k_enable_rfkill(struct ath_hw *ah)
21474 +{
21475 + return ath9k_hw_private_ops(ah)->enable_rfkill(ah);
21476 +}
21477 +
21478 +static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah)
21479 +{
21480 + if (!ath9k_hw_private_ops(ah)->restore_chainmask)
21481 + return;
21482 +
21483 + return ath9k_hw_private_ops(ah)->restore_chainmask(ah);
21484 +}
21485 +
21486 +static inline void ath9k_hw_set_diversity(struct ath_hw *ah, bool value)
21487 +{
21488 + return ath9k_hw_private_ops(ah)->set_diversity(ah, value);
21489 +}
21490 +
21491 +static inline bool ath9k_hw_ani_control(struct ath_hw *ah,
21492 + enum ath9k_ani_cmd cmd, int param)
21493 +{
21494 + return ath9k_hw_private_ops(ah)->ani_control(ah, cmd, param);
21495 +}
21496 +
21497 +static inline void ath9k_hw_do_getnf(struct ath_hw *ah,
21498 + int16_t nfarray[NUM_NF_READINGS])
21499 +{
21500 + ath9k_hw_private_ops(ah)->do_getnf(ah, nfarray);
21501 +}
21502 +
21503 +static inline void ath9k_hw_loadnf(struct ath_hw *ah,
21504 + struct ath9k_channel *chan)
21505 +{
21506 + ath9k_hw_private_ops(ah)->loadnf(ah, chan);
21507 +}
21508 +
21509 +static inline bool ath9k_hw_init_cal(struct ath_hw *ah,
21510 + struct ath9k_channel *chan)
21511 +{
21512 + return ath9k_hw_private_ops(ah)->init_cal(ah, chan);
21513 +}
21514 +
21515 +static inline void ath9k_hw_setup_calibration(struct ath_hw *ah,
21516 + struct ath9k_cal_list *currCal)
21517 +{
21518 + ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal);
21519 +}
21520 +
21521 +static inline bool ath9k_hw_iscal_supported(struct ath_hw *ah,
21522 + enum ath9k_cal_types calType)
21523 +{
21524 + return ath9k_hw_private_ops(ah)->iscal_supported(ah, calType);
21525 +}
21526 +
21527 +#endif /* ATH9K_HW_OPS_H */
21528 --- a/drivers/net/wireless/ath/ath9k/hw.c
21529 +++ b/drivers/net/wireless/ath/ath9k/hw.c
21530 @@ -1,5 +1,5 @@
21531 /*
21532 - * Copyright (c) 2008-2009 Atheros Communications Inc.
21533 + * Copyright (c) 2008-2010 Atheros Communications Inc.
21534 *
21535 * Permission to use, copy, modify, and/or distribute this software for any
21536 * purpose with or without fee is hereby granted, provided that the above
21537 @@ -19,15 +19,14 @@
21538 #include <asm/unaligned.h>
21539
21540 #include "hw.h"
21541 +#include "hw-ops.h"
21542 #include "rc.h"
21543 -#include "initvals.h"
21544
21545 #define ATH9K_CLOCK_RATE_CCK 22
21546 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
21547 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
21548
21549 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
21550 -static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
21551
21552 MODULE_AUTHOR("Atheros Communications");
21553 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
21554 @@ -46,6 +45,37 @@ static void __exit ath9k_exit(void)
21555 }
21556 module_exit(ath9k_exit);
21557
21558 +/* Private hardware callbacks */
21559 +
21560 +static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
21561 +{
21562 + ath9k_hw_private_ops(ah)->init_cal_settings(ah);
21563 +}
21564 +
21565 +static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
21566 +{
21567 + ath9k_hw_private_ops(ah)->init_mode_regs(ah);
21568 +}
21569 +
21570 +static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
21571 +{
21572 + return ath9k_hw_private_ops(ah)->macversion_supported(ah->hw_version.macVersion);
21573 +}
21574 +
21575 +static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
21576 + struct ath9k_channel *chan)
21577 +{
21578 + return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
21579 +}
21580 +
21581 +static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
21582 +{
21583 + if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
21584 + return;
21585 +
21586 + ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
21587 +}
21588 +
21589 /********************/
21590 /* Helper Functions */
21591 /********************/
21592 @@ -233,21 +263,6 @@ static void ath9k_hw_read_revisions(stru
21593 }
21594 }
21595
21596 -static int ath9k_hw_get_radiorev(struct ath_hw *ah)
21597 -{
21598 - u32 val;
21599 - int i;
21600 -
21601 - REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
21602 -
21603 - for (i = 0; i < 8; i++)
21604 - REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
21605 - val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
21606 - val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
21607 -
21608 - return ath9k_hw_reverse_bits(val, 8);
21609 -}
21610 -
21611 /************************************/
21612 /* HW Attach, Detach, Init Routines */
21613 /************************************/
21614 @@ -270,18 +285,25 @@ static void ath9k_hw_disablepcie(struct
21615 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
21616 }
21617
21618 +/* This should work for all families including legacy */
21619 static bool ath9k_hw_chip_test(struct ath_hw *ah)
21620 {
21621 struct ath_common *common = ath9k_hw_common(ah);
21622 - u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
21623 + u32 regAddr[2] = { AR_STA_ID0 };
21624 u32 regHold[2];
21625 u32 patternData[4] = { 0x55555555,
21626 0xaaaaaaaa,
21627 0x66666666,
21628 0x99999999 };
21629 - int i, j;
21630 + int i, j, loop_max;
21631 +
21632 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
21633 + loop_max = 2;
21634 + regAddr[1] = AR_PHY_BASE + (8 << 2);
21635 + } else
21636 + loop_max = 1;
21637
21638 - for (i = 0; i < 2; i++) {
21639 + for (i = 0; i < loop_max; i++) {
21640 u32 addr = regAddr[i];
21641 u32 wrData, rdData;
21642
21643 @@ -369,7 +391,6 @@ static void ath9k_hw_init_config(struct
21644 if (num_possible_cpus() > 1)
21645 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
21646 }
21647 -EXPORT_SYMBOL(ath9k_hw_init);
21648
21649 static void ath9k_hw_init_defaults(struct ath_hw *ah)
21650 {
21651 @@ -383,8 +404,6 @@ static void ath9k_hw_init_defaults(struc
21652 ah->hw_version.subvendorid = 0;
21653
21654 ah->ah_flags = 0;
21655 - if (ah->hw_version.devid == AR5416_AR9100_DEVID)
21656 - ah->hw_version.macVersion = AR_SREV_VERSION_9100;
21657 if (!AR_SREV_9100(ah))
21658 ah->ah_flags = AH_USE_EEPROM;
21659
21660 @@ -397,44 +416,17 @@ static void ath9k_hw_init_defaults(struc
21661 ah->power_mode = ATH9K_PM_UNDEFINED;
21662 }
21663
21664 -static int ath9k_hw_rf_claim(struct ath_hw *ah)
21665 -{
21666 - u32 val;
21667 -
21668 - REG_WRITE(ah, AR_PHY(0), 0x00000007);
21669 -
21670 - val = ath9k_hw_get_radiorev(ah);
21671 - switch (val & AR_RADIO_SREV_MAJOR) {
21672 - case 0:
21673 - val = AR_RAD5133_SREV_MAJOR;
21674 - break;
21675 - case AR_RAD5133_SREV_MAJOR:
21676 - case AR_RAD5122_SREV_MAJOR:
21677 - case AR_RAD2133_SREV_MAJOR:
21678 - case AR_RAD2122_SREV_MAJOR:
21679 - break;
21680 - default:
21681 - ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
21682 - "Radio Chip Rev 0x%02X not supported\n",
21683 - val & AR_RADIO_SREV_MAJOR);
21684 - return -EOPNOTSUPP;
21685 - }
21686 -
21687 - ah->hw_version.analog5GhzRev = val;
21688 -
21689 - return 0;
21690 -}
21691 -
21692 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
21693 {
21694 struct ath_common *common = ath9k_hw_common(ah);
21695 u32 sum;
21696 int i;
21697 u16 eeval;
21698 + u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
21699
21700 sum = 0;
21701 for (i = 0; i < 3; i++) {
21702 - eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
21703 + eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
21704 sum += eeval;
21705 common->macaddr[2 * i] = eeval >> 8;
21706 common->macaddr[2 * i + 1] = eeval & 0xff;
21707 @@ -445,54 +437,6 @@ static int ath9k_hw_init_macaddr(struct
21708 return 0;
21709 }
21710
21711 -static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
21712 -{
21713 - u32 rxgain_type;
21714 -
21715 - if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
21716 - rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
21717 -
21718 - if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
21719 - INIT_INI_ARRAY(&ah->iniModesRxGain,
21720 - ar9280Modes_backoff_13db_rxgain_9280_2,
21721 - ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
21722 - else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
21723 - INIT_INI_ARRAY(&ah->iniModesRxGain,
21724 - ar9280Modes_backoff_23db_rxgain_9280_2,
21725 - ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
21726 - else
21727 - INIT_INI_ARRAY(&ah->iniModesRxGain,
21728 - ar9280Modes_original_rxgain_9280_2,
21729 - ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
21730 - } else {
21731 - INIT_INI_ARRAY(&ah->iniModesRxGain,
21732 - ar9280Modes_original_rxgain_9280_2,
21733 - ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
21734 - }
21735 -}
21736 -
21737 -static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
21738 -{
21739 - u32 txgain_type;
21740 -
21741 - if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
21742 - txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
21743 -
21744 - if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
21745 - INIT_INI_ARRAY(&ah->iniModesTxGain,
21746 - ar9280Modes_high_power_tx_gain_9280_2,
21747 - ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
21748 - else
21749 - INIT_INI_ARRAY(&ah->iniModesTxGain,
21750 - ar9280Modes_original_tx_gain_9280_2,
21751 - ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
21752 - } else {
21753 - INIT_INI_ARRAY(&ah->iniModesTxGain,
21754 - ar9280Modes_original_tx_gain_9280_2,
21755 - ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
21756 - }
21757 -}
21758 -
21759 static int ath9k_hw_post_init(struct ath_hw *ah)
21760 {
21761 int ecode;
21762 @@ -502,9 +446,11 @@ static int ath9k_hw_post_init(struct ath
21763 return -ENODEV;
21764 }
21765
21766 - ecode = ath9k_hw_rf_claim(ah);
21767 - if (ecode != 0)
21768 - return ecode;
21769 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
21770 + ecode = ar9002_hw_rf_claim(ah);
21771 + if (ecode != 0)
21772 + return ecode;
21773 + }
21774
21775 ecode = ath9k_hw_eeprom_init(ah);
21776 if (ecode != 0)
21777 @@ -515,14 +461,12 @@ static int ath9k_hw_post_init(struct ath
21778 ah->eep_ops->get_eeprom_ver(ah),
21779 ah->eep_ops->get_eeprom_rev(ah));
21780
21781 - if (!AR_SREV_9280_10_OR_LATER(ah)) {
21782 - ecode = ath9k_hw_rf_alloc_ext_banks(ah);
21783 - if (ecode) {
21784 - ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
21785 - "Failed allocating banks for "
21786 - "external radio\n");
21787 - return ecode;
21788 - }
21789 + ecode = ath9k_hw_rf_alloc_ext_banks(ah);
21790 + if (ecode) {
21791 + ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
21792 + "Failed allocating banks for "
21793 + "external radio\n");
21794 + return ecode;
21795 }
21796
21797 if (!AR_SREV_9100(ah)) {
21798 @@ -533,344 +477,22 @@ static int ath9k_hw_post_init(struct ath
21799 return 0;
21800 }
21801
21802 -static bool ath9k_hw_devid_supported(u16 devid)
21803 -{
21804 - switch (devid) {
21805 - case AR5416_DEVID_PCI:
21806 - case AR5416_DEVID_PCIE:
21807 - case AR5416_AR9100_DEVID:
21808 - case AR9160_DEVID_PCI:
21809 - case AR9280_DEVID_PCI:
21810 - case AR9280_DEVID_PCIE:
21811 - case AR9285_DEVID_PCIE:
21812 - case AR5416_DEVID_AR9287_PCI:
21813 - case AR5416_DEVID_AR9287_PCIE:
21814 - case AR2427_DEVID_PCIE:
21815 - return true;
21816 - default:
21817 - break;
21818 - }
21819 - return false;
21820 -}
21821 -
21822 -static bool ath9k_hw_macversion_supported(u32 macversion)
21823 -{
21824 - switch (macversion) {
21825 - case AR_SREV_VERSION_5416_PCI:
21826 - case AR_SREV_VERSION_5416_PCIE:
21827 - case AR_SREV_VERSION_9160:
21828 - case AR_SREV_VERSION_9100:
21829 - case AR_SREV_VERSION_9280:
21830 - case AR_SREV_VERSION_9285:
21831 - case AR_SREV_VERSION_9287:
21832 - case AR_SREV_VERSION_9271:
21833 - return true;
21834 - default:
21835 - break;
21836 - }
21837 - return false;
21838 -}
21839 -
21840 -static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
21841 -{
21842 - if (AR_SREV_9160_10_OR_LATER(ah)) {
21843 - if (AR_SREV_9280_10_OR_LATER(ah)) {
21844 - ah->iq_caldata.calData = &iq_cal_single_sample;
21845 - ah->adcgain_caldata.calData =
21846 - &adc_gain_cal_single_sample;
21847 - ah->adcdc_caldata.calData =
21848 - &adc_dc_cal_single_sample;
21849 - ah->adcdc_calinitdata.calData =
21850 - &adc_init_dc_cal;
21851 - } else {
21852 - ah->iq_caldata.calData = &iq_cal_multi_sample;
21853 - ah->adcgain_caldata.calData =
21854 - &adc_gain_cal_multi_sample;
21855 - ah->adcdc_caldata.calData =
21856 - &adc_dc_cal_multi_sample;
21857 - ah->adcdc_calinitdata.calData =
21858 - &adc_init_dc_cal;
21859 - }
21860 - ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
21861 - }
21862 -}
21863 -
21864 -static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
21865 -{
21866 - if (AR_SREV_9271(ah)) {
21867 - INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
21868 - ARRAY_SIZE(ar9271Modes_9271), 6);
21869 - INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
21870 - ARRAY_SIZE(ar9271Common_9271), 2);
21871 - INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
21872 - ar9271Common_normal_cck_fir_coeff_9271,
21873 - ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
21874 - INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
21875 - ar9271Common_japan_2484_cck_fir_coeff_9271,
21876 - ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
21877 - INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
21878 - ar9271Modes_9271_1_0_only,
21879 - ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
21880 - INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
21881 - ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
21882 - INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
21883 - ar9271Modes_high_power_tx_gain_9271,
21884 - ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
21885 - INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
21886 - ar9271Modes_normal_power_tx_gain_9271,
21887 - ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
21888 - return;
21889 - }
21890 -
21891 - if (AR_SREV_9287_11_OR_LATER(ah)) {
21892 - INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
21893 - ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
21894 - INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
21895 - ARRAY_SIZE(ar9287Common_9287_1_1), 2);
21896 - if (ah->config.pcie_clock_req)
21897 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
21898 - ar9287PciePhy_clkreq_off_L1_9287_1_1,
21899 - ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
21900 - else
21901 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
21902 - ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
21903 - ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
21904 - 2);
21905 - } else if (AR_SREV_9287_10_OR_LATER(ah)) {
21906 - INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
21907 - ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
21908 - INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
21909 - ARRAY_SIZE(ar9287Common_9287_1_0), 2);
21910 -
21911 - if (ah->config.pcie_clock_req)
21912 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
21913 - ar9287PciePhy_clkreq_off_L1_9287_1_0,
21914 - ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
21915 - else
21916 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
21917 - ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
21918 - ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
21919 - 2);
21920 - } else if (AR_SREV_9285_12_OR_LATER(ah)) {
21921 -
21922 -
21923 - INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
21924 - ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
21925 - INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
21926 - ARRAY_SIZE(ar9285Common_9285_1_2), 2);
21927 -
21928 - if (ah->config.pcie_clock_req) {
21929 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
21930 - ar9285PciePhy_clkreq_off_L1_9285_1_2,
21931 - ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
21932 - } else {
21933 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
21934 - ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
21935 - ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
21936 - 2);
21937 - }
21938 - } else if (AR_SREV_9285_10_OR_LATER(ah)) {
21939 - INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
21940 - ARRAY_SIZE(ar9285Modes_9285), 6);
21941 - INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
21942 - ARRAY_SIZE(ar9285Common_9285), 2);
21943 -
21944 - if (ah->config.pcie_clock_req) {
21945 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
21946 - ar9285PciePhy_clkreq_off_L1_9285,
21947 - ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
21948 - } else {
21949 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
21950 - ar9285PciePhy_clkreq_always_on_L1_9285,
21951 - ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
21952 - }
21953 - } else if (AR_SREV_9280_20_OR_LATER(ah)) {
21954 - INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
21955 - ARRAY_SIZE(ar9280Modes_9280_2), 6);
21956 - INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
21957 - ARRAY_SIZE(ar9280Common_9280_2), 2);
21958 -
21959 - if (ah->config.pcie_clock_req) {
21960 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
21961 - ar9280PciePhy_clkreq_off_L1_9280,
21962 - ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
21963 - } else {
21964 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
21965 - ar9280PciePhy_clkreq_always_on_L1_9280,
21966 - ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
21967 - }
21968 - INIT_INI_ARRAY(&ah->iniModesAdditional,
21969 - ar9280Modes_fast_clock_9280_2,
21970 - ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
21971 - } else if (AR_SREV_9280_10_OR_LATER(ah)) {
21972 - INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
21973 - ARRAY_SIZE(ar9280Modes_9280), 6);
21974 - INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
21975 - ARRAY_SIZE(ar9280Common_9280), 2);
21976 - } else if (AR_SREV_9160_10_OR_LATER(ah)) {
21977 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
21978 - ARRAY_SIZE(ar5416Modes_9160), 6);
21979 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
21980 - ARRAY_SIZE(ar5416Common_9160), 2);
21981 - INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
21982 - ARRAY_SIZE(ar5416Bank0_9160), 2);
21983 - INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
21984 - ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
21985 - INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
21986 - ARRAY_SIZE(ar5416Bank1_9160), 2);
21987 - INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
21988 - ARRAY_SIZE(ar5416Bank2_9160), 2);
21989 - INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
21990 - ARRAY_SIZE(ar5416Bank3_9160), 3);
21991 - INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
21992 - ARRAY_SIZE(ar5416Bank6_9160), 3);
21993 - INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
21994 - ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
21995 - INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
21996 - ARRAY_SIZE(ar5416Bank7_9160), 2);
21997 - if (AR_SREV_9160_11(ah)) {
21998 - INIT_INI_ARRAY(&ah->iniAddac,
21999 - ar5416Addac_91601_1,
22000 - ARRAY_SIZE(ar5416Addac_91601_1), 2);
22001 - } else {
22002 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
22003 - ARRAY_SIZE(ar5416Addac_9160), 2);
22004 - }
22005 - } else if (AR_SREV_9100_OR_LATER(ah)) {
22006 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
22007 - ARRAY_SIZE(ar5416Modes_9100), 6);
22008 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
22009 - ARRAY_SIZE(ar5416Common_9100), 2);
22010 - INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
22011 - ARRAY_SIZE(ar5416Bank0_9100), 2);
22012 - INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
22013 - ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
22014 - INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
22015 - ARRAY_SIZE(ar5416Bank1_9100), 2);
22016 - INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
22017 - ARRAY_SIZE(ar5416Bank2_9100), 2);
22018 - INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
22019 - ARRAY_SIZE(ar5416Bank3_9100), 3);
22020 - INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
22021 - ARRAY_SIZE(ar5416Bank6_9100), 3);
22022 - INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
22023 - ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
22024 - INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
22025 - ARRAY_SIZE(ar5416Bank7_9100), 2);
22026 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
22027 - ARRAY_SIZE(ar5416Addac_9100), 2);
22028 - } else {
22029 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
22030 - ARRAY_SIZE(ar5416Modes), 6);
22031 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
22032 - ARRAY_SIZE(ar5416Common), 2);
22033 - INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
22034 - ARRAY_SIZE(ar5416Bank0), 2);
22035 - INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
22036 - ARRAY_SIZE(ar5416BB_RfGain), 3);
22037 - INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
22038 - ARRAY_SIZE(ar5416Bank1), 2);
22039 - INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
22040 - ARRAY_SIZE(ar5416Bank2), 2);
22041 - INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
22042 - ARRAY_SIZE(ar5416Bank3), 3);
22043 - INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
22044 - ARRAY_SIZE(ar5416Bank6), 3);
22045 - INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
22046 - ARRAY_SIZE(ar5416Bank6TPC), 3);
22047 - INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
22048 - ARRAY_SIZE(ar5416Bank7), 2);
22049 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
22050 - ARRAY_SIZE(ar5416Addac), 2);
22051 - }
22052 -}
22053 -
22054 -static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
22055 -{
22056 - if (AR_SREV_9287_11_OR_LATER(ah))
22057 - INIT_INI_ARRAY(&ah->iniModesRxGain,
22058 - ar9287Modes_rx_gain_9287_1_1,
22059 - ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
22060 - else if (AR_SREV_9287_10(ah))
22061 - INIT_INI_ARRAY(&ah->iniModesRxGain,
22062 - ar9287Modes_rx_gain_9287_1_0,
22063 - ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
22064 - else if (AR_SREV_9280_20(ah))
22065 - ath9k_hw_init_rxgain_ini(ah);
22066 -
22067 - if (AR_SREV_9287_11_OR_LATER(ah)) {
22068 - INIT_INI_ARRAY(&ah->iniModesTxGain,
22069 - ar9287Modes_tx_gain_9287_1_1,
22070 - ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
22071 - } else if (AR_SREV_9287_10(ah)) {
22072 - INIT_INI_ARRAY(&ah->iniModesTxGain,
22073 - ar9287Modes_tx_gain_9287_1_0,
22074 - ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
22075 - } else if (AR_SREV_9280_20(ah)) {
22076 - ath9k_hw_init_txgain_ini(ah);
22077 - } else if (AR_SREV_9285_12_OR_LATER(ah)) {
22078 - u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
22079 -
22080 - /* txgain table */
22081 - if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
22082 - if (AR_SREV_9285E_20(ah)) {
22083 - INIT_INI_ARRAY(&ah->iniModesTxGain,
22084 - ar9285Modes_XE2_0_high_power,
22085 - ARRAY_SIZE(
22086 - ar9285Modes_XE2_0_high_power), 6);
22087 - } else {
22088 - INIT_INI_ARRAY(&ah->iniModesTxGain,
22089 - ar9285Modes_high_power_tx_gain_9285_1_2,
22090 - ARRAY_SIZE(
22091 - ar9285Modes_high_power_tx_gain_9285_1_2), 6);
22092 - }
22093 - } else {
22094 - if (AR_SREV_9285E_20(ah)) {
22095 - INIT_INI_ARRAY(&ah->iniModesTxGain,
22096 - ar9285Modes_XE2_0_normal_power,
22097 - ARRAY_SIZE(
22098 - ar9285Modes_XE2_0_normal_power), 6);
22099 - } else {
22100 - INIT_INI_ARRAY(&ah->iniModesTxGain,
22101 - ar9285Modes_original_tx_gain_9285_1_2,
22102 - ARRAY_SIZE(
22103 - ar9285Modes_original_tx_gain_9285_1_2), 6);
22104 - }
22105 - }
22106 - }
22107 -}
22108 -
22109 -static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
22110 +static void ath9k_hw_attach_ops(struct ath_hw *ah)
22111 {
22112 - struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
22113 - struct ath_common *common = ath9k_hw_common(ah);
22114 -
22115 - ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
22116 - (ah->eep_map != EEP_MAP_4KBITS) &&
22117 - ((pBase->version & 0xff) > 0x0a) &&
22118 - (pBase->pwdclkind == 0);
22119 -
22120 - if (ah->need_an_top2_fixup)
22121 - ath_print(common, ATH_DBG_EEPROM,
22122 - "needs fixup for AR_AN_TOP2 register\n");
22123 + if (AR_SREV_9300_20_OR_LATER(ah))
22124 + ar9003_hw_attach_ops(ah);
22125 + else
22126 + ar9002_hw_attach_ops(ah);
22127 }
22128
22129 -int ath9k_hw_init(struct ath_hw *ah)
22130 +/* Called for all hardware families */
22131 +static int __ath9k_hw_init(struct ath_hw *ah)
22132 {
22133 struct ath_common *common = ath9k_hw_common(ah);
22134 int r = 0;
22135
22136 - if (common->bus_ops->ath_bus_type != ATH_USB) {
22137 - if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
22138 - ath_print(common, ATH_DBG_FATAL,
22139 - "Unsupported device ID: 0x%0x\n",
22140 - ah->hw_version.devid);
22141 - return -EOPNOTSUPP;
22142 - }
22143 - }
22144 -
22145 - ath9k_hw_init_defaults(ah);
22146 - ath9k_hw_init_config(ah);
22147 + if (ah->hw_version.devid == AR5416_AR9100_DEVID)
22148 + ah->hw_version.macVersion = AR_SREV_VERSION_9100;
22149
22150 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
22151 ath_print(common, ATH_DBG_FATAL,
22152 @@ -878,6 +500,11 @@ int ath9k_hw_init(struct ath_hw *ah)
22153 return -EIO;
22154 }
22155
22156 + ath9k_hw_init_defaults(ah);
22157 + ath9k_hw_init_config(ah);
22158 +
22159 + ath9k_hw_attach_ops(ah);
22160 +
22161 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
22162 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
22163 return -EIO;
22164 @@ -902,7 +529,7 @@ int ath9k_hw_init(struct ath_hw *ah)
22165 else
22166 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
22167
22168 - if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
22169 + if (!ath9k_hw_macversion_supported(ah)) {
22170 ath_print(common, ATH_DBG_FATAL,
22171 "Mac Chip Rev 0x%02x.%x is not supported by "
22172 "this driver\n", ah->hw_version.macVersion,
22173 @@ -910,28 +537,19 @@ int ath9k_hw_init(struct ath_hw *ah)
22174 return -EOPNOTSUPP;
22175 }
22176
22177 - if (AR_SREV_9100(ah)) {
22178 - ah->iq_caldata.calData = &iq_cal_multi_sample;
22179 - ah->supp_cals = IQ_MISMATCH_CAL;
22180 - ah->is_pciexpress = false;
22181 - }
22182 -
22183 - if (AR_SREV_9271(ah))
22184 + if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
22185 ah->is_pciexpress = false;
22186
22187 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
22188 -
22189 ath9k_hw_init_cal_settings(ah);
22190
22191 ah->ani_function = ATH9K_ANI_ALL;
22192 - if (AR_SREV_9280_10_OR_LATER(ah)) {
22193 + if (AR_SREV_9280_10_OR_LATER(ah))
22194 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
22195 - ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
22196 - ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
22197 - } else {
22198 - ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
22199 - ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
22200 - }
22201 +
22202 + /* this is still being tested */
22203 + if (AR_SREV_9300_20_OR_LATER(ah))
22204 + ah->ani_function = 0;
22205
22206 ath9k_hw_init_mode_regs(ah);
22207
22208 @@ -940,15 +558,8 @@ int ath9k_hw_init(struct ath_hw *ah)
22209 else
22210 ath9k_hw_disablepcie(ah);
22211
22212 - /* Support for Japan ch.14 (2484) spread */
22213 - if (AR_SREV_9287_11_OR_LATER(ah)) {
22214 - INIT_INI_ARRAY(&ah->iniCckfirNormal,
22215 - ar9287Common_normal_cck_fir_coeff_92871_1,
22216 - ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
22217 - INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
22218 - ar9287Common_japan_2484_cck_fir_coeff_92871_1,
22219 - ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
22220 - }
22221 + if (!AR_SREV_9300_20_OR_LATER(ah))
22222 + ar9002_hw_cck_chan14_spread(ah);
22223
22224 r = ath9k_hw_post_init(ah);
22225 if (r)
22226 @@ -959,8 +570,6 @@ int ath9k_hw_init(struct ath_hw *ah)
22227 if (r)
22228 return r;
22229
22230 - ath9k_hw_init_eeprom_fix(ah);
22231 -
22232 r = ath9k_hw_init_macaddr(ah);
22233 if (r) {
22234 ath_print(common, ATH_DBG_FATAL,
22235 @@ -973,6 +582,9 @@ int ath9k_hw_init(struct ath_hw *ah)
22236 else
22237 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
22238
22239 + if (AR_SREV_9300_20_OR_LATER(ah))
22240 + ar9003_hw_set_nf_limits(ah);
22241 +
22242 ath9k_init_nfcal_hist_buffer(ah);
22243
22244 common->state = ATH_HW_INITIALIZED;
22245 @@ -980,21 +592,45 @@ int ath9k_hw_init(struct ath_hw *ah)
22246 return 0;
22247 }
22248
22249 -static void ath9k_hw_init_bb(struct ath_hw *ah,
22250 - struct ath9k_channel *chan)
22251 +int ath9k_hw_init(struct ath_hw *ah)
22252 {
22253 - u32 synthDelay;
22254 + int ret;
22255 + struct ath_common *common = ath9k_hw_common(ah);
22256
22257 - synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
22258 - if (IS_CHAN_B(chan))
22259 - synthDelay = (4 * synthDelay) / 22;
22260 - else
22261 - synthDelay /= 10;
22262 + /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
22263 + switch (ah->hw_version.devid) {
22264 + case AR5416_DEVID_PCI:
22265 + case AR5416_DEVID_PCIE:
22266 + case AR5416_AR9100_DEVID:
22267 + case AR9160_DEVID_PCI:
22268 + case AR9280_DEVID_PCI:
22269 + case AR9280_DEVID_PCIE:
22270 + case AR9285_DEVID_PCIE:
22271 + case AR9287_DEVID_PCI:
22272 + case AR9287_DEVID_PCIE:
22273 + case AR2427_DEVID_PCIE:
22274 + case AR9300_DEVID_PCIE:
22275 + break;
22276 + default:
22277 + if (common->bus_ops->ath_bus_type == ATH_USB)
22278 + break;
22279 + ath_print(common, ATH_DBG_FATAL,
22280 + "Hardware device ID 0x%04x not supported\n",
22281 + ah->hw_version.devid);
22282 + return -EOPNOTSUPP;
22283 + }
22284
22285 - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
22286 + ret = __ath9k_hw_init(ah);
22287 + if (ret) {
22288 + ath_print(common, ATH_DBG_FATAL,
22289 + "Unable to initialize hardware; "
22290 + "initialization status: %d\n", ret);
22291 + return ret;
22292 + }
22293
22294 - udelay(synthDelay + BASE_ACTIVATE_DELAY);
22295 + return 0;
22296 }
22297 +EXPORT_SYMBOL(ath9k_hw_init);
22298
22299 static void ath9k_hw_init_qos(struct ath_hw *ah)
22300 {
22301 @@ -1016,64 +652,8 @@ static void ath9k_hw_init_qos(struct ath
22302 static void ath9k_hw_init_pll(struct ath_hw *ah,
22303 struct ath9k_channel *chan)
22304 {
22305 - u32 pll;
22306 + u32 pll = ath9k_hw_compute_pll_control(ah, chan);
22307
22308 - if (AR_SREV_9100(ah)) {
22309 - if (chan && IS_CHAN_5GHZ(chan))
22310 - pll = 0x1450;
22311 - else
22312 - pll = 0x1458;
22313 - } else {
22314 - if (AR_SREV_9280_10_OR_LATER(ah)) {
22315 - pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
22316 -
22317 - if (chan && IS_CHAN_HALF_RATE(chan))
22318 - pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
22319 - else if (chan && IS_CHAN_QUARTER_RATE(chan))
22320 - pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
22321 -
22322 - if (chan && IS_CHAN_5GHZ(chan)) {
22323 - pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
22324 -
22325 -
22326 - if (AR_SREV_9280_20(ah)) {
22327 - if (((chan->channel % 20) == 0)
22328 - || ((chan->channel % 10) == 0))
22329 - pll = 0x2850;
22330 - else
22331 - pll = 0x142c;
22332 - }
22333 - } else {
22334 - pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
22335 - }
22336 -
22337 - } else if (AR_SREV_9160_10_OR_LATER(ah)) {
22338 -
22339 - pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
22340 -
22341 - if (chan && IS_CHAN_HALF_RATE(chan))
22342 - pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
22343 - else if (chan && IS_CHAN_QUARTER_RATE(chan))
22344 - pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
22345 -
22346 - if (chan && IS_CHAN_5GHZ(chan))
22347 - pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
22348 - else
22349 - pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
22350 - } else {
22351 - pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
22352 -
22353 - if (chan && IS_CHAN_HALF_RATE(chan))
22354 - pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
22355 - else if (chan && IS_CHAN_QUARTER_RATE(chan))
22356 - pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
22357 -
22358 - if (chan && IS_CHAN_5GHZ(chan))
22359 - pll |= SM(0xa, AR_RTC_PLL_DIV);
22360 - else
22361 - pll |= SM(0xb, AR_RTC_PLL_DIV);
22362 - }
22363 - }
22364 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
22365
22366 /* Switch the core clock for ar9271 to 117Mhz */
22367 @@ -1087,43 +667,6 @@ static void ath9k_hw_init_pll(struct ath
22368 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
22369 }
22370
22371 -static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
22372 -{
22373 - int rx_chainmask, tx_chainmask;
22374 -
22375 - rx_chainmask = ah->rxchainmask;
22376 - tx_chainmask = ah->txchainmask;
22377 -
22378 - switch (rx_chainmask) {
22379 - case 0x5:
22380 - REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
22381 - AR_PHY_SWAP_ALT_CHAIN);
22382 - case 0x3:
22383 - if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
22384 - REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
22385 - REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
22386 - break;
22387 - }
22388 - case 0x1:
22389 - case 0x2:
22390 - case 0x7:
22391 - REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
22392 - REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
22393 - break;
22394 - default:
22395 - break;
22396 - }
22397 -
22398 - REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
22399 - if (tx_chainmask == 0x5) {
22400 - REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
22401 - AR_PHY_SWAP_ALT_CHAIN);
22402 - }
22403 - if (AR_SREV_9100(ah))
22404 - REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
22405 - REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
22406 -}
22407 -
22408 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
22409 enum nl80211_iftype opmode)
22410 {
22411 @@ -1133,12 +676,24 @@ static void ath9k_hw_init_interrupt_mask
22412 AR_IMR_RXORN |
22413 AR_IMR_BCNMISC;
22414
22415 - if (ah->config.rx_intr_mitigation)
22416 - imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
22417 - else
22418 - imr_reg |= AR_IMR_RXOK;
22419 + if (AR_SREV_9300_20_OR_LATER(ah)) {
22420 + imr_reg |= AR_IMR_RXOK_HP;
22421 + if (ah->config.rx_intr_mitigation)
22422 + imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
22423 + else
22424 + imr_reg |= AR_IMR_RXOK_LP;
22425
22426 - imr_reg |= AR_IMR_TXOK;
22427 + } else {
22428 + if (ah->config.rx_intr_mitigation)
22429 + imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
22430 + else
22431 + imr_reg |= AR_IMR_RXOK;
22432 + }
22433 +
22434 + if (ah->config.tx_intr_mitigation)
22435 + imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
22436 + else
22437 + imr_reg |= AR_IMR_TXOK;
22438
22439 if (opmode == NL80211_IFTYPE_AP)
22440 imr_reg |= AR_IMR_MIB;
22441 @@ -1152,6 +707,13 @@ static void ath9k_hw_init_interrupt_mask
22442 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
22443 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
22444 }
22445 +
22446 + if (AR_SREV_9300_20_OR_LATER(ah)) {
22447 + REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
22448 + REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
22449 + REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
22450 + REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
22451 + }
22452 }
22453
22454 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
22455 @@ -1220,305 +782,67 @@ void ath9k_hw_init_global_settings(struc
22456 * timeout issues in other cases as well.
22457 */
22458 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
22459 - acktimeout += 64 - sifstime - ah->slottime;
22460 -
22461 - ath9k_hw_setslottime(ah, slottime);
22462 - ath9k_hw_set_ack_timeout(ah, acktimeout);
22463 - ath9k_hw_set_cts_timeout(ah, acktimeout);
22464 - if (ah->globaltxtimeout != (u32) -1)
22465 - ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
22466 -}
22467 -EXPORT_SYMBOL(ath9k_hw_init_global_settings);
22468 -
22469 -void ath9k_hw_deinit(struct ath_hw *ah)
22470 -{
22471 - struct ath_common *common = ath9k_hw_common(ah);
22472 -
22473 - if (common->state < ATH_HW_INITIALIZED)
22474 - goto free_hw;
22475 -
22476 - if (!AR_SREV_9100(ah))
22477 - ath9k_hw_ani_disable(ah);
22478 -
22479 - ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
22480 -
22481 -free_hw:
22482 - if (!AR_SREV_9280_10_OR_LATER(ah))
22483 - ath9k_hw_rf_free_ext_banks(ah);
22484 -}
22485 -EXPORT_SYMBOL(ath9k_hw_deinit);
22486 -
22487 -/*******/
22488 -/* INI */
22489 -/*******/
22490 -
22491 -static void ath9k_hw_override_ini(struct ath_hw *ah,
22492 - struct ath9k_channel *chan)
22493 -{
22494 - u32 val;
22495 -
22496 - /*
22497 - * Set the RX_ABORT and RX_DIS and clear if off only after
22498 - * RXE is set for MAC. This prevents frames with corrupted
22499 - * descriptor status.
22500 - */
22501 - REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
22502 -
22503 - if (AR_SREV_9280_10_OR_LATER(ah)) {
22504 - val = REG_READ(ah, AR_PCU_MISC_MODE2);
22505 -
22506 - if (!AR_SREV_9271(ah))
22507 - val &= ~AR_PCU_MISC_MODE2_HWWAR1;
22508 -
22509 - if (AR_SREV_9287_10_OR_LATER(ah))
22510 - val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
22511 -
22512 - REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
22513 - }
22514 -
22515 - if (!AR_SREV_5416_20_OR_LATER(ah) ||
22516 - AR_SREV_9280_10_OR_LATER(ah))
22517 - return;
22518 - /*
22519 - * Disable BB clock gating
22520 - * Necessary to avoid issues on AR5416 2.0
22521 - */
22522 - REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
22523 -
22524 - /*
22525 - * Disable RIFS search on some chips to avoid baseband
22526 - * hang issues.
22527 - */
22528 - if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
22529 - val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
22530 - val &= ~AR_PHY_RIFS_INIT_DELAY;
22531 - REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
22532 - }
22533 -}
22534 -
22535 -static void ath9k_olc_init(struct ath_hw *ah)
22536 -{
22537 - u32 i;
22538 -
22539 - if (OLC_FOR_AR9287_10_LATER) {
22540 - REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
22541 - AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
22542 - ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
22543 - AR9287_AN_TXPC0_TXPCMODE,
22544 - AR9287_AN_TXPC0_TXPCMODE_S,
22545 - AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
22546 - udelay(100);
22547 - } else {
22548 - for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
22549 - ah->originalGain[i] =
22550 - MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
22551 - AR_PHY_TX_GAIN);
22552 - ah->PDADCdelta = 0;
22553 - }
22554 -}
22555 -
22556 -static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
22557 - struct ath9k_channel *chan)
22558 -{
22559 - u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
22560 -
22561 - if (IS_CHAN_B(chan))
22562 - ctl |= CTL_11B;
22563 - else if (IS_CHAN_G(chan))
22564 - ctl |= CTL_11G;
22565 - else
22566 - ctl |= CTL_11A;
22567 -
22568 - return ctl;
22569 -}
22570 -
22571 -static int ath9k_hw_process_ini(struct ath_hw *ah,
22572 - struct ath9k_channel *chan)
22573 -{
22574 - struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
22575 - int i, regWrites = 0;
22576 - struct ieee80211_channel *channel = chan->chan;
22577 - u32 modesIndex, freqIndex;
22578 -
22579 - switch (chan->chanmode) {
22580 - case CHANNEL_A:
22581 - case CHANNEL_A_HT20:
22582 - modesIndex = 1;
22583 - freqIndex = 1;
22584 - break;
22585 - case CHANNEL_A_HT40PLUS:
22586 - case CHANNEL_A_HT40MINUS:
22587 - modesIndex = 2;
22588 - freqIndex = 1;
22589 - break;
22590 - case CHANNEL_G:
22591 - case CHANNEL_G_HT20:
22592 - case CHANNEL_B:
22593 - modesIndex = 4;
22594 - freqIndex = 2;
22595 - break;
22596 - case CHANNEL_G_HT40PLUS:
22597 - case CHANNEL_G_HT40MINUS:
22598 - modesIndex = 3;
22599 - freqIndex = 2;
22600 - break;
22601 -
22602 - default:
22603 - return -EINVAL;
22604 - }
22605 -
22606 - /* Set correct baseband to analog shift setting to access analog chips */
22607 - REG_WRITE(ah, AR_PHY(0), 0x00000007);
22608 -
22609 - /* Write ADDAC shifts */
22610 - REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
22611 - ah->eep_ops->set_addac(ah, chan);
22612 -
22613 - if (AR_SREV_5416_22_OR_LATER(ah)) {
22614 - REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
22615 - } else {
22616 - struct ar5416IniArray temp;
22617 - u32 addacSize =
22618 - sizeof(u32) * ah->iniAddac.ia_rows *
22619 - ah->iniAddac.ia_columns;
22620 -
22621 - /* For AR5416 2.0/2.1 */
22622 - memcpy(ah->addac5416_21,
22623 - ah->iniAddac.ia_array, addacSize);
22624 -
22625 - /* override CLKDRV value at [row, column] = [31, 1] */
22626 - (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
22627 -
22628 - temp.ia_array = ah->addac5416_21;
22629 - temp.ia_columns = ah->iniAddac.ia_columns;
22630 - temp.ia_rows = ah->iniAddac.ia_rows;
22631 - REG_WRITE_ARRAY(&temp, 1, regWrites);
22632 - }
22633 -
22634 - REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
22635 -
22636 - for (i = 0; i < ah->iniModes.ia_rows; i++) {
22637 - u32 reg = INI_RA(&ah->iniModes, i, 0);
22638 - u32 val = INI_RA(&ah->iniModes, i, modesIndex);
22639 -
22640 - if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
22641 - val &= ~AR_AN_TOP2_PWDCLKIND;
22642 -
22643 - REG_WRITE(ah, reg, val);
22644 -
22645 - if (reg >= 0x7800 && reg < 0x78a0
22646 - && ah->config.analog_shiftreg) {
22647 - udelay(100);
22648 - }
22649 -
22650 - DO_DELAY(regWrites);
22651 - }
22652 -
22653 - if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
22654 - REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
22655 -
22656 - if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
22657 - AR_SREV_9287_10_OR_LATER(ah))
22658 - REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
22659 -
22660 - if (AR_SREV_9271_10(ah))
22661 - REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
22662 - modesIndex, regWrites);
22663 -
22664 - /* Write common array parameters */
22665 - for (i = 0; i < ah->iniCommon.ia_rows; i++) {
22666 - u32 reg = INI_RA(&ah->iniCommon, i, 0);
22667 - u32 val = INI_RA(&ah->iniCommon, i, 1);
22668 -
22669 - REG_WRITE(ah, reg, val);
22670 + acktimeout += 64 - sifstime - ah->slottime;
22671
22672 - if (reg >= 0x7800 && reg < 0x78a0
22673 - && ah->config.analog_shiftreg) {
22674 - udelay(100);
22675 - }
22676 + ath9k_hw_setslottime(ah, slottime);
22677 + ath9k_hw_set_ack_timeout(ah, acktimeout);
22678 + ath9k_hw_set_cts_timeout(ah, acktimeout);
22679 + if (ah->globaltxtimeout != (u32) -1)
22680 + ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
22681 +}
22682 +EXPORT_SYMBOL(ath9k_hw_init_global_settings);
22683
22684 - DO_DELAY(regWrites);
22685 - }
22686 +void ath9k_hw_deinit(struct ath_hw *ah)
22687 +{
22688 + struct ath_common *common = ath9k_hw_common(ah);
22689
22690 - if (AR_SREV_9271(ah)) {
22691 - if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
22692 - REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
22693 - modesIndex, regWrites);
22694 - else
22695 - REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
22696 - modesIndex, regWrites);
22697 - }
22698 + if (common->state < ATH_HW_INITIALIZED)
22699 + goto free_hw;
22700
22701 - ath9k_hw_write_regs(ah, freqIndex, regWrites);
22702 + if (!AR_SREV_9100(ah))
22703 + ath9k_hw_ani_disable(ah);
22704
22705 - if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
22706 - REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
22707 - regWrites);
22708 - }
22709 + ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
22710
22711 - ath9k_hw_override_ini(ah, chan);
22712 - ath9k_hw_set_regs(ah, chan);
22713 - ath9k_hw_init_chain_masks(ah);
22714 +free_hw:
22715 + ath9k_hw_rf_free_ext_banks(ah);
22716 +}
22717 +EXPORT_SYMBOL(ath9k_hw_deinit);
22718
22719 - if (OLC_FOR_AR9280_20_LATER)
22720 - ath9k_olc_init(ah);
22721 +/*******/
22722 +/* INI */
22723 +/*******/
22724
22725 - /* Set TX power */
22726 - ah->eep_ops->set_txpower(ah, chan,
22727 - ath9k_regd_get_ctl(regulatory, chan),
22728 - channel->max_antenna_gain * 2,
22729 - channel->max_power * 2,
22730 - min((u32) MAX_RATE_POWER,
22731 - (u32) regulatory->power_limit));
22732 +u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
22733 +{
22734 + u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
22735
22736 - /* Write analog registers */
22737 - if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
22738 - ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
22739 - "ar5416SetRfRegs failed\n");
22740 - return -EIO;
22741 - }
22742 + if (IS_CHAN_B(chan))
22743 + ctl |= CTL_11B;
22744 + else if (IS_CHAN_G(chan))
22745 + ctl |= CTL_11G;
22746 + else
22747 + ctl |= CTL_11A;
22748
22749 - return 0;
22750 + return ctl;
22751 }
22752
22753 /****************************************/
22754 /* Reset and Channel Switching Routines */
22755 /****************************************/
22756
22757 -static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
22758 -{
22759 - u32 rfMode = 0;
22760 -
22761 - if (chan == NULL)
22762 - return;
22763 -
22764 - rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
22765 - ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
22766 -
22767 - if (!AR_SREV_9280_10_OR_LATER(ah))
22768 - rfMode |= (IS_CHAN_5GHZ(chan)) ?
22769 - AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
22770 -
22771 - if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
22772 - rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
22773 -
22774 - REG_WRITE(ah, AR_PHY_MODE, rfMode);
22775 -}
22776 -
22777 -static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
22778 -{
22779 - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
22780 -}
22781 -
22782 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
22783 {
22784 + struct ath_common *common = ath9k_hw_common(ah);
22785 u32 regval;
22786
22787 /*
22788 * set AHB_MODE not to do cacheline prefetches
22789 */
22790 - regval = REG_READ(ah, AR_AHB_MODE);
22791 - REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
22792 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
22793 + regval = REG_READ(ah, AR_AHB_MODE);
22794 + REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
22795 + }
22796
22797 /*
22798 * let mac dma reads be in 128 byte chunks
22799 @@ -1531,7 +855,8 @@ static inline void ath9k_hw_set_dma(stru
22800 * The initial value depends on whether aggregation is enabled, and is
22801 * adjusted whenever underruns are detected.
22802 */
22803 - REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
22804 + if (!AR_SREV_9300_20_OR_LATER(ah))
22805 + REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
22806
22807 /*
22808 * let mac dma writes be in 128 byte chunks
22809 @@ -1544,6 +869,14 @@ static inline void ath9k_hw_set_dma(stru
22810 */
22811 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
22812
22813 + if (AR_SREV_9300_20_OR_LATER(ah)) {
22814 + REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
22815 + REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
22816 +
22817 + ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
22818 + ah->caps.rx_status_len);
22819 + }
22820 +
22821 /*
22822 * reduce the number of usable entries in PCU TXBUF to avoid
22823 * wrap around issues.
22824 @@ -1559,6 +892,9 @@ static inline void ath9k_hw_set_dma(stru
22825 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
22826 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
22827 }
22828 +
22829 + if (AR_SREV_9300_20_OR_LATER(ah))
22830 + ath9k_hw_reset_txstatus_ring(ah);
22831 }
22832
22833 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
22834 @@ -1586,10 +922,8 @@ static void ath9k_hw_set_operating_mode(
22835 }
22836 }
22837
22838 -static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
22839 - u32 coef_scaled,
22840 - u32 *coef_mantissa,
22841 - u32 *coef_exponent)
22842 +void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
22843 + u32 *coef_mantissa, u32 *coef_exponent)
22844 {
22845 u32 coef_exp, coef_man;
22846
22847 @@ -1605,40 +939,6 @@ static inline void ath9k_hw_get_delta_sl
22848 *coef_exponent = coef_exp - 16;
22849 }
22850
22851 -static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
22852 - struct ath9k_channel *chan)
22853 -{
22854 - u32 coef_scaled, ds_coef_exp, ds_coef_man;
22855 - u32 clockMhzScaled = 0x64000000;
22856 - struct chan_centers centers;
22857 -
22858 - if (IS_CHAN_HALF_RATE(chan))
22859 - clockMhzScaled = clockMhzScaled >> 1;
22860 - else if (IS_CHAN_QUARTER_RATE(chan))
22861 - clockMhzScaled = clockMhzScaled >> 2;
22862 -
22863 - ath9k_hw_get_channel_centers(ah, chan, &centers);
22864 - coef_scaled = clockMhzScaled / centers.synth_center;
22865 -
22866 - ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
22867 - &ds_coef_exp);
22868 -
22869 - REG_RMW_FIELD(ah, AR_PHY_TIMING3,
22870 - AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
22871 - REG_RMW_FIELD(ah, AR_PHY_TIMING3,
22872 - AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
22873 -
22874 - coef_scaled = (9 * coef_scaled) / 10;
22875 -
22876 - ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
22877 - &ds_coef_exp);
22878 -
22879 - REG_RMW_FIELD(ah, AR_PHY_HALFGI,
22880 - AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
22881 - REG_RMW_FIELD(ah, AR_PHY_HALFGI,
22882 - AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
22883 -}
22884 -
22885 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
22886 {
22887 u32 rst_flags;
22888 @@ -1663,11 +963,16 @@ static bool ath9k_hw_set_reset(struct at
22889 if (tmpReg &
22890 (AR_INTR_SYNC_LOCAL_TIMEOUT |
22891 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
22892 + u32 val;
22893 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
22894 - REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
22895 - } else {
22896 +
22897 + val = AR_RC_HOSTIF;
22898 + if (!AR_SREV_9300_20_OR_LATER(ah))
22899 + val |= AR_RC_AHB;
22900 + REG_WRITE(ah, AR_RC, val);
22901 +
22902 + } else if (!AR_SREV_9300_20_OR_LATER(ah))
22903 REG_WRITE(ah, AR_RC, AR_RC_AHB);
22904 - }
22905
22906 rst_flags = AR_RTC_RC_MAC_WARM;
22907 if (type == ATH9K_RESET_COLD)
22908 @@ -1698,13 +1003,15 @@ static bool ath9k_hw_set_reset_power_on(
22909 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
22910 AR_RTC_FORCE_WAKE_ON_INT);
22911
22912 - if (!AR_SREV_9100(ah))
22913 + if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
22914 REG_WRITE(ah, AR_RC, AR_RC_AHB);
22915
22916 REG_WRITE(ah, AR_RTC_RESET, 0);
22917 - udelay(2);
22918
22919 - if (!AR_SREV_9100(ah))
22920 + if (!AR_SREV_9300_20_OR_LATER(ah))
22921 + udelay(2);
22922 +
22923 + if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
22924 REG_WRITE(ah, AR_RC, 0);
22925
22926 REG_WRITE(ah, AR_RTC_RESET, 1);
22927 @@ -1740,34 +1047,6 @@ static bool ath9k_hw_set_reset_reg(struc
22928 }
22929 }
22930
22931 -static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
22932 -{
22933 - u32 phymode;
22934 - u32 enableDacFifo = 0;
22935 -
22936 - if (AR_SREV_9285_10_OR_LATER(ah))
22937 - enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
22938 - AR_PHY_FC_ENABLE_DAC_FIFO);
22939 -
22940 - phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
22941 - | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
22942 -
22943 - if (IS_CHAN_HT40(chan)) {
22944 - phymode |= AR_PHY_FC_DYN2040_EN;
22945 -
22946 - if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
22947 - (chan->chanmode == CHANNEL_G_HT40PLUS))
22948 - phymode |= AR_PHY_FC_DYN2040_PRI_CH;
22949 -
22950 - }
22951 - REG_WRITE(ah, AR_PHY_TURBO, phymode);
22952 -
22953 - ath9k_hw_set11nmac2040(ah);
22954 -
22955 - REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
22956 - REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
22957 -}
22958 -
22959 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
22960 struct ath9k_channel *chan)
22961 {
22962 @@ -1793,7 +1072,7 @@ static bool ath9k_hw_channel_change(stru
22963 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
22964 struct ath_common *common = ath9k_hw_common(ah);
22965 struct ieee80211_channel *channel = chan->chan;
22966 - u32 synthDelay, qnum;
22967 + u32 qnum;
22968 int r;
22969
22970 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
22971 @@ -1805,17 +1084,15 @@ static bool ath9k_hw_channel_change(stru
22972 }
22973 }
22974
22975 - REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
22976 - if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
22977 - AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
22978 + if (!ath9k_hw_rfbus_req(ah)) {
22979 ath_print(common, ATH_DBG_FATAL,
22980 "Could not kill baseband RX\n");
22981 return false;
22982 }
22983
22984 - ath9k_hw_set_regs(ah, chan);
22985 + ath9k_hw_set_channel_regs(ah, chan);
22986
22987 - r = ah->ath9k_hw_rf_set_freq(ah, chan);
22988 + r = ath9k_hw_rf_set_freq(ah, chan);
22989 if (r) {
22990 ath_print(common, ATH_DBG_FATAL,
22991 "Failed to set channel\n");
22992 @@ -1829,20 +1106,12 @@ static bool ath9k_hw_channel_change(stru
22993 min((u32) MAX_RATE_POWER,
22994 (u32) regulatory->power_limit));
22995
22996 - synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
22997 - if (IS_CHAN_B(chan))
22998 - synthDelay = (4 * synthDelay) / 22;
22999 - else
23000 - synthDelay /= 10;
23001 -
23002 - udelay(synthDelay + BASE_ACTIVATE_DELAY);
23003 -
23004 - REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
23005 + ath9k_hw_rfbus_done(ah);
23006
23007 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
23008 ath9k_hw_set_delta_slope(ah, chan);
23009
23010 - ah->ath9k_hw_spur_mitigate_freq(ah, chan);
23011 + ath9k_hw_spur_mitigate_freq(ah, chan);
23012
23013 if (!chan->oneTimeCalsDone)
23014 chan->oneTimeCalsDone = true;
23015 @@ -1850,18 +1119,6 @@ static bool ath9k_hw_channel_change(stru
23016 return true;
23017 }
23018
23019 -static void ath9k_enable_rfkill(struct ath_hw *ah)
23020 -{
23021 - REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
23022 - AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
23023 -
23024 - REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
23025 - AR_GPIO_INPUT_MUX2_RFSILENT);
23026 -
23027 - ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
23028 - REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
23029 -}
23030 -
23031 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
23032 bool bChannelChange)
23033 {
23034 @@ -1871,11 +1128,18 @@ int ath9k_hw_reset(struct ath_hw *ah, st
23035 u32 saveDefAntenna;
23036 u32 macStaId1;
23037 u64 tsf = 0;
23038 - int i, rx_chainmask, r;
23039 + int i, r;
23040
23041 ah->txchainmask = common->tx_chainmask;
23042 ah->rxchainmask = common->rx_chainmask;
23043
23044 + if (!ah->chip_fullsleep) {
23045 + ath9k_hw_abortpcurecv(ah);
23046 + if (!ath9k_hw_stopdmarecv(ah))
23047 + ath_print(common, ATH_DBG_XMIT,
23048 + "Failed to stop receive dma\n");
23049 + }
23050 +
23051 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
23052 return -EIO;
23053
23054 @@ -1943,16 +1207,6 @@ int ath9k_hw_reset(struct ath_hw *ah, st
23055 if (AR_SREV_9280_10_OR_LATER(ah))
23056 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
23057
23058 - if (AR_SREV_9287_12_OR_LATER(ah)) {
23059 - /* Enable ASYNC FIFO */
23060 - REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
23061 - AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
23062 - REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
23063 - REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
23064 - AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
23065 - REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
23066 - AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
23067 - }
23068 r = ath9k_hw_process_ini(ah, chan);
23069 if (r)
23070 return r;
23071 @@ -1977,7 +1231,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
23072 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
23073 ath9k_hw_set_delta_slope(ah, chan);
23074
23075 - ah->ath9k_hw_spur_mitigate_freq(ah, chan);
23076 + ath9k_hw_spur_mitigate_freq(ah, chan);
23077 ah->eep_ops->set_board_values(ah, chan);
23078
23079 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
23080 @@ -1999,7 +1253,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
23081
23082 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
23083
23084 - r = ah->ath9k_hw_rf_set_freq(ah, chan);
23085 + r = ath9k_hw_rf_set_freq(ah, chan);
23086 if (r)
23087 return r;
23088
23089 @@ -2018,25 +1272,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
23090
23091 ath9k_hw_init_global_settings(ah);
23092
23093 - if (AR_SREV_9287_12_OR_LATER(ah)) {
23094 - REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
23095 - AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
23096 - REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
23097 - AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
23098 - REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
23099 - AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
23100 -
23101 - REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
23102 - REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
23103 -
23104 - REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
23105 - AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
23106 - REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
23107 - AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
23108 - }
23109 - if (AR_SREV_9287_12_OR_LATER(ah)) {
23110 - REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
23111 - AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
23112 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
23113 + ar9002_hw_enable_async_fifo(ah);
23114 + ar9002_hw_enable_wep_aggregation(ah);
23115 }
23116
23117 REG_WRITE(ah, AR_STA_ID1,
23118 @@ -2051,17 +1289,17 @@ int ath9k_hw_reset(struct ath_hw *ah, st
23119 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
23120 }
23121
23122 + if (ah->config.tx_intr_mitigation) {
23123 + REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
23124 + REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
23125 + }
23126 +
23127 ath9k_hw_init_bb(ah, chan);
23128
23129 if (!ath9k_hw_init_cal(ah, chan))
23130 return -EIO;
23131
23132 - rx_chainmask = ah->rxchainmask;
23133 - if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
23134 - REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
23135 - REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
23136 - }
23137 -
23138 + ath9k_hw_restore_chainmask(ah);
23139 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
23140
23141 /*
23142 @@ -2093,6 +1331,11 @@ int ath9k_hw_reset(struct ath_hw *ah, st
23143 if (ah->btcoex_hw.enabled)
23144 ath9k_hw_btcoex_enable(ah);
23145
23146 + if (AR_SREV_9300_20_OR_LATER(ah)) {
23147 + ath9k_hw_loadnf(ah, curchan);
23148 + ath9k_hw_start_nfcal(ah);
23149 + }
23150 +
23151 return 0;
23152 }
23153 EXPORT_SYMBOL(ath9k_hw_reset);
23154 @@ -2379,21 +1622,32 @@ EXPORT_SYMBOL(ath9k_hw_keyisvalid);
23155 /* Power Management (Chipset) */
23156 /******************************/
23157
23158 +/*
23159 + * Notify Power Mgt is disabled in self-generated frames.
23160 + * If requested, force chip to sleep.
23161 + */
23162 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
23163 {
23164 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
23165 if (setChip) {
23166 + /* Clear the RTC force wake bit to allow the mac to go to sleep */
23167 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
23168 AR_RTC_FORCE_WAKE_EN);
23169 - if (!AR_SREV_9100(ah))
23170 + if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
23171 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
23172
23173 + /* Shutdown chip. Active low */
23174 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
23175 REG_CLR_BIT(ah, (AR_RTC_RESET),
23176 AR_RTC_RESET_EN);
23177 }
23178 }
23179
23180 +/*
23181 + * Notify Power Management is enabled in self-generating
23182 + * frames. If request, set power mode of chip to
23183 + * auto/normal. Duration in units of 128us (1/8 TU).
23184 + */
23185 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
23186 {
23187 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
23188 @@ -2401,9 +1655,14 @@ static void ath9k_set_power_network_slee
23189 struct ath9k_hw_capabilities *pCap = &ah->caps;
23190
23191 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
23192 + /* Set WakeOnInterrupt bit; clear ForceWake bit */
23193 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
23194 AR_RTC_FORCE_WAKE_ON_INT);
23195 } else {
23196 + /*
23197 + * Clear the RTC force wake bit to allow the
23198 + * mac to go to sleep.
23199 + */
23200 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
23201 AR_RTC_FORCE_WAKE_EN);
23202 }
23203 @@ -2422,7 +1681,8 @@ static bool ath9k_hw_set_power_awake(str
23204 ATH9K_RESET_POWER_ON) != true) {
23205 return false;
23206 }
23207 - ath9k_hw_init_pll(ah, NULL);
23208 + if (!AR_SREV_9300_20_OR_LATER(ah))
23209 + ath9k_hw_init_pll(ah, NULL);
23210 }
23211 if (AR_SREV_9100(ah))
23212 REG_SET_BIT(ah, AR_RTC_RESET,
23213 @@ -2492,420 +1752,6 @@ bool ath9k_hw_setpower(struct ath_hw *ah
23214 }
23215 EXPORT_SYMBOL(ath9k_hw_setpower);
23216
23217 -/*
23218 - * Helper for ASPM support.
23219 - *
23220 - * Disable PLL when in L0s as well as receiver clock when in L1.
23221 - * This power saving option must be enabled through the SerDes.
23222 - *
23223 - * Programming the SerDes must go through the same 288 bit serial shift
23224 - * register as the other analog registers. Hence the 9 writes.
23225 - */
23226 -void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
23227 -{
23228 - u8 i;
23229 - u32 val;
23230 -
23231 - if (ah->is_pciexpress != true)
23232 - return;
23233 -
23234 - /* Do not touch SerDes registers */
23235 - if (ah->config.pcie_powersave_enable == 2)
23236 - return;
23237 -
23238 - /* Nothing to do on restore for 11N */
23239 - if (!restore) {
23240 - if (AR_SREV_9280_20_OR_LATER(ah)) {
23241 - /*
23242 - * AR9280 2.0 or later chips use SerDes values from the
23243 - * initvals.h initialized depending on chipset during
23244 - * ath9k_hw_init()
23245 - */
23246 - for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
23247 - REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
23248 - INI_RA(&ah->iniPcieSerdes, i, 1));
23249 - }
23250 - } else if (AR_SREV_9280(ah) &&
23251 - (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
23252 - REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
23253 - REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
23254 -
23255 - /* RX shut off when elecidle is asserted */
23256 - REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
23257 - REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
23258 - REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
23259 -
23260 - /* Shut off CLKREQ active in L1 */
23261 - if (ah->config.pcie_clock_req)
23262 - REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
23263 - else
23264 - REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
23265 -
23266 - REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
23267 - REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
23268 - REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
23269 -
23270 - /* Load the new settings */
23271 - REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
23272 -
23273 - } else {
23274 - REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
23275 - REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
23276 -
23277 - /* RX shut off when elecidle is asserted */
23278 - REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
23279 - REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
23280 - REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
23281 -
23282 - /*
23283 - * Ignore ah->ah_config.pcie_clock_req setting for
23284 - * pre-AR9280 11n
23285 - */
23286 - REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
23287 -
23288 - REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
23289 - REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
23290 - REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
23291 -
23292 - /* Load the new settings */
23293 - REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
23294 - }
23295 -
23296 - udelay(1000);
23297 -
23298 - /* set bit 19 to allow forcing of pcie core into L1 state */
23299 - REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
23300 -
23301 - /* Several PCIe massages to ensure proper behaviour */
23302 - if (ah->config.pcie_waen) {
23303 - val = ah->config.pcie_waen;
23304 - if (!power_off)
23305 - val &= (~AR_WA_D3_L1_DISABLE);
23306 - } else {
23307 - if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
23308 - AR_SREV_9287(ah)) {
23309 - val = AR9285_WA_DEFAULT;
23310 - if (!power_off)
23311 - val &= (~AR_WA_D3_L1_DISABLE);
23312 - } else if (AR_SREV_9280(ah)) {
23313 - /*
23314 - * On AR9280 chips bit 22 of 0x4004 needs to be
23315 - * set otherwise card may disappear.
23316 - */
23317 - val = AR9280_WA_DEFAULT;
23318 - if (!power_off)
23319 - val &= (~AR_WA_D3_L1_DISABLE);
23320 - } else
23321 - val = AR_WA_DEFAULT;
23322 - }
23323 -
23324 - REG_WRITE(ah, AR_WA, val);
23325 - }
23326 -
23327 - if (power_off) {
23328 - /*
23329 - * Set PCIe workaround bits
23330 - * bit 14 in WA register (disable L1) should only
23331 - * be set when device enters D3 and be cleared
23332 - * when device comes back to D0.
23333 - */
23334 - if (ah->config.pcie_waen) {
23335 - if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
23336 - REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
23337 - } else {
23338 - if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
23339 - AR_SREV_9287(ah)) &&
23340 - (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
23341 - (AR_SREV_9280(ah) &&
23342 - (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
23343 - REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
23344 - }
23345 - }
23346 - }
23347 -}
23348 -EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
23349 -
23350 -/**********************/
23351 -/* Interrupt Handling */
23352 -/**********************/
23353 -
23354 -bool ath9k_hw_intrpend(struct ath_hw *ah)
23355 -{
23356 - u32 host_isr;
23357 -
23358 - if (AR_SREV_9100(ah))
23359 - return true;
23360 -
23361 - host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
23362 - if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
23363 - return true;
23364 -
23365 - host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
23366 - if ((host_isr & AR_INTR_SYNC_DEFAULT)
23367 - && (host_isr != AR_INTR_SPURIOUS))
23368 - return true;
23369 -
23370 - return false;
23371 -}
23372 -EXPORT_SYMBOL(ath9k_hw_intrpend);
23373 -
23374 -bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
23375 -{
23376 - u32 isr = 0;
23377 - u32 mask2 = 0;
23378 - struct ath9k_hw_capabilities *pCap = &ah->caps;
23379 - u32 sync_cause = 0;
23380 - bool fatal_int = false;
23381 - struct ath_common *common = ath9k_hw_common(ah);
23382 -
23383 - if (!AR_SREV_9100(ah)) {
23384 - if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
23385 - if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
23386 - == AR_RTC_STATUS_ON) {
23387 - isr = REG_READ(ah, AR_ISR);
23388 - }
23389 - }
23390 -
23391 - sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
23392 - AR_INTR_SYNC_DEFAULT;
23393 -
23394 - *masked = 0;
23395 -
23396 - if (!isr && !sync_cause)
23397 - return false;
23398 - } else {
23399 - *masked = 0;
23400 - isr = REG_READ(ah, AR_ISR);
23401 - }
23402 -
23403 - if (isr) {
23404 - if (isr & AR_ISR_BCNMISC) {
23405 - u32 isr2;
23406 - isr2 = REG_READ(ah, AR_ISR_S2);
23407 - if (isr2 & AR_ISR_S2_TIM)
23408 - mask2 |= ATH9K_INT_TIM;
23409 - if (isr2 & AR_ISR_S2_DTIM)
23410 - mask2 |= ATH9K_INT_DTIM;
23411 - if (isr2 & AR_ISR_S2_DTIMSYNC)
23412 - mask2 |= ATH9K_INT_DTIMSYNC;
23413 - if (isr2 & (AR_ISR_S2_CABEND))
23414 - mask2 |= ATH9K_INT_CABEND;
23415 - if (isr2 & AR_ISR_S2_GTT)
23416 - mask2 |= ATH9K_INT_GTT;
23417 - if (isr2 & AR_ISR_S2_CST)
23418 - mask2 |= ATH9K_INT_CST;
23419 - if (isr2 & AR_ISR_S2_TSFOOR)
23420 - mask2 |= ATH9K_INT_TSFOOR;
23421 - }
23422 -
23423 - isr = REG_READ(ah, AR_ISR_RAC);
23424 - if (isr == 0xffffffff) {
23425 - *masked = 0;
23426 - return false;
23427 - }
23428 -
23429 - *masked = isr & ATH9K_INT_COMMON;
23430 -
23431 - if (ah->config.rx_intr_mitigation) {
23432 - if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
23433 - *masked |= ATH9K_INT_RX;
23434 - }
23435 -
23436 - if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
23437 - *masked |= ATH9K_INT_RX;
23438 - if (isr &
23439 - (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
23440 - AR_ISR_TXEOL)) {
23441 - u32 s0_s, s1_s;
23442 -
23443 - *masked |= ATH9K_INT_TX;
23444 -
23445 - s0_s = REG_READ(ah, AR_ISR_S0_S);
23446 - ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
23447 - ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
23448 -
23449 - s1_s = REG_READ(ah, AR_ISR_S1_S);
23450 - ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
23451 - ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
23452 - }
23453 -
23454 - if (isr & AR_ISR_RXORN) {
23455 - ath_print(common, ATH_DBG_INTERRUPT,
23456 - "receive FIFO overrun interrupt\n");
23457 - }
23458 -
23459 - if (!AR_SREV_9100(ah)) {
23460 - if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
23461 - u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
23462 - if (isr5 & AR_ISR_S5_TIM_TIMER)
23463 - *masked |= ATH9K_INT_TIM_TIMER;
23464 - }
23465 - }
23466 -
23467 - *masked |= mask2;
23468 - }
23469 -
23470 - if (AR_SREV_9100(ah))
23471 - return true;
23472 -
23473 - if (isr & AR_ISR_GENTMR) {
23474 - u32 s5_s;
23475 -
23476 - s5_s = REG_READ(ah, AR_ISR_S5_S);
23477 - if (isr & AR_ISR_GENTMR) {
23478 - ah->intr_gen_timer_trigger =
23479 - MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
23480 -
23481 - ah->intr_gen_timer_thresh =
23482 - MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
23483 -
23484 - if (ah->intr_gen_timer_trigger)
23485 - *masked |= ATH9K_INT_GENTIMER;
23486 -
23487 - }
23488 - }
23489 -
23490 - if (sync_cause) {
23491 - fatal_int =
23492 - (sync_cause &
23493 - (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
23494 - ? true : false;
23495 -
23496 - if (fatal_int) {
23497 - if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
23498 - ath_print(common, ATH_DBG_ANY,
23499 - "received PCI FATAL interrupt\n");
23500 - }
23501 - if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
23502 - ath_print(common, ATH_DBG_ANY,
23503 - "received PCI PERR interrupt\n");
23504 - }
23505 - *masked |= ATH9K_INT_FATAL;
23506 - }
23507 - if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
23508 - ath_print(common, ATH_DBG_INTERRUPT,
23509 - "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
23510 - REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
23511 - REG_WRITE(ah, AR_RC, 0);
23512 - *masked |= ATH9K_INT_FATAL;
23513 - }
23514 - if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
23515 - ath_print(common, ATH_DBG_INTERRUPT,
23516 - "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
23517 - }
23518 -
23519 - REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
23520 - (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
23521 - }
23522 -
23523 - return true;
23524 -}
23525 -EXPORT_SYMBOL(ath9k_hw_getisr);
23526 -
23527 -enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
23528 -{
23529 - enum ath9k_int omask = ah->imask;
23530 - u32 mask, mask2;
23531 - struct ath9k_hw_capabilities *pCap = &ah->caps;
23532 - struct ath_common *common = ath9k_hw_common(ah);
23533 -
23534 - ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
23535 -
23536 - if (omask & ATH9K_INT_GLOBAL) {
23537 - ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
23538 - REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
23539 - (void) REG_READ(ah, AR_IER);
23540 - if (!AR_SREV_9100(ah)) {
23541 - REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
23542 - (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
23543 -
23544 - REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
23545 - (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
23546 - }
23547 - }
23548 -
23549 - mask = ints & ATH9K_INT_COMMON;
23550 - mask2 = 0;
23551 -
23552 - if (ints & ATH9K_INT_TX) {
23553 - if (ah->txok_interrupt_mask)
23554 - mask |= AR_IMR_TXOK;
23555 - if (ah->txdesc_interrupt_mask)
23556 - mask |= AR_IMR_TXDESC;
23557 - if (ah->txerr_interrupt_mask)
23558 - mask |= AR_IMR_TXERR;
23559 - if (ah->txeol_interrupt_mask)
23560 - mask |= AR_IMR_TXEOL;
23561 - }
23562 - if (ints & ATH9K_INT_RX) {
23563 - mask |= AR_IMR_RXERR;
23564 - if (ah->config.rx_intr_mitigation)
23565 - mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
23566 - else
23567 - mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
23568 - if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
23569 - mask |= AR_IMR_GENTMR;
23570 - }
23571 -
23572 - if (ints & (ATH9K_INT_BMISC)) {
23573 - mask |= AR_IMR_BCNMISC;
23574 - if (ints & ATH9K_INT_TIM)
23575 - mask2 |= AR_IMR_S2_TIM;
23576 - if (ints & ATH9K_INT_DTIM)
23577 - mask2 |= AR_IMR_S2_DTIM;
23578 - if (ints & ATH9K_INT_DTIMSYNC)
23579 - mask2 |= AR_IMR_S2_DTIMSYNC;
23580 - if (ints & ATH9K_INT_CABEND)
23581 - mask2 |= AR_IMR_S2_CABEND;
23582 - if (ints & ATH9K_INT_TSFOOR)
23583 - mask2 |= AR_IMR_S2_TSFOOR;
23584 - }
23585 -
23586 - if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
23587 - mask |= AR_IMR_BCNMISC;
23588 - if (ints & ATH9K_INT_GTT)
23589 - mask2 |= AR_IMR_S2_GTT;
23590 - if (ints & ATH9K_INT_CST)
23591 - mask2 |= AR_IMR_S2_CST;
23592 - }
23593 -
23594 - ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
23595 - REG_WRITE(ah, AR_IMR, mask);
23596 - ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
23597 - AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
23598 - AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
23599 - ah->imrs2_reg |= mask2;
23600 - REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
23601 -
23602 - if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
23603 - if (ints & ATH9K_INT_TIM_TIMER)
23604 - REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
23605 - else
23606 - REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
23607 - }
23608 -
23609 - if (ints & ATH9K_INT_GLOBAL) {
23610 - ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
23611 - REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
23612 - if (!AR_SREV_9100(ah)) {
23613 - REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
23614 - AR_INTR_MAC_IRQ);
23615 - REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
23616 -
23617 -
23618 - REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
23619 - AR_INTR_SYNC_DEFAULT);
23620 - REG_WRITE(ah, AR_INTR_SYNC_MASK,
23621 - AR_INTR_SYNC_DEFAULT);
23622 - }
23623 - ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
23624 - REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
23625 - }
23626 -
23627 - return omask;
23628 -}
23629 -EXPORT_SYMBOL(ath9k_hw_set_interrupts);
23630 -
23631 /*******************/
23632 /* Beacon Handling */
23633 /*******************/
23634 @@ -3241,6 +2087,20 @@ int ath9k_hw_fill_cap_info(struct ath_hw
23635 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
23636 }
23637
23638 + if (AR_SREV_9300_20_OR_LATER(ah)) {
23639 + pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC;
23640 + pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
23641 + pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
23642 + pCap->rx_status_len = sizeof(struct ar9003_rxs);
23643 + pCap->tx_desc_len = sizeof(struct ar9003_txc);
23644 + pCap->txs_len = sizeof(struct ar9003_txs);
23645 + } else {
23646 + pCap->tx_desc_len = sizeof(struct ath_desc);
23647 + }
23648 +
23649 + if (AR_SREV_9300_20_OR_LATER(ah))
23650 + pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
23651 +
23652 return 0;
23653 }
23654
23655 @@ -3273,10 +2133,6 @@ bool ath9k_hw_getcapability(struct ath_h
23656 case ATH9K_CAP_TKIP_SPLIT:
23657 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
23658 false : true;
23659 - case ATH9K_CAP_DIVERSITY:
23660 - return (REG_READ(ah, AR_PHY_CCK_DETECT) &
23661 - AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
23662 - true : false;
23663 case ATH9K_CAP_MCAST_KEYSRCH:
23664 switch (capability) {
23665 case 0:
23666 @@ -3319,8 +2175,6 @@ EXPORT_SYMBOL(ath9k_hw_getcapability);
23667 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
23668 u32 capability, u32 setting, int *status)
23669 {
23670 - u32 v;
23671 -
23672 switch (type) {
23673 case ATH9K_CAP_TKIP_MIC:
23674 if (setting)
23675 @@ -3330,14 +2184,6 @@ bool ath9k_hw_setcapability(struct ath_h
23676 ah->sta_id1_defaults &=
23677 ~AR_STA_ID1_CRPT_MIC_ENABLE;
23678 return true;
23679 - case ATH9K_CAP_DIVERSITY:
23680 - v = REG_READ(ah, AR_PHY_CCK_DETECT);
23681 - if (setting)
23682 - v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
23683 - else
23684 - v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
23685 - REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
23686 - return true;
23687 case ATH9K_CAP_MCAST_KEYSRCH:
23688 if (setting)
23689 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
23690 @@ -3405,7 +2251,9 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah,
23691 if (gpio >= ah->caps.num_gpio_pins)
23692 return 0xffffffff;
23693
23694 - if (AR_SREV_9271(ah))
23695 + if (AR_SREV_9300_20_OR_LATER(ah))
23696 + return MS_REG_READ(AR9300, gpio) != 0;
23697 + else if (AR_SREV_9271(ah))
23698 return MS_REG_READ(AR9271, gpio) != 0;
23699 else if (AR_SREV_9287_10_OR_LATER(ah))
23700 return MS_REG_READ(AR9287, gpio) != 0;
23701 @@ -3847,6 +2695,7 @@ static struct {
23702 { AR_SREV_VERSION_9285, "9285" },
23703 { AR_SREV_VERSION_9287, "9287" },
23704 { AR_SREV_VERSION_9271, "9271" },
23705 + { AR_SREV_VERSION_9300, "9300" },
23706 };
23707
23708 /* For devices with external radios */
23709 --- a/drivers/net/wireless/ath/ath9k/hw.h
23710 +++ b/drivers/net/wireless/ath/ath9k/hw.h
23711 @@ -1,5 +1,5 @@
23712 /*
23713 - * Copyright (c) 2008-2009 Atheros Communications Inc.
23714 + * Copyright (c) 2008-2010 Atheros Communications Inc.
23715 *
23716 * Permission to use, copy, modify, and/or distribute this software for any
23717 * purpose with or without fee is hereby granted, provided that the above
23718 @@ -28,6 +28,7 @@
23719 #include "reg.h"
23720 #include "phy.h"
23721 #include "btcoex.h"
23722 +#include "ar9003_mac.h"
23723
23724 #include "../regd.h"
23725 #include "../debug.h"
23726 @@ -41,6 +42,9 @@
23727 #define AR9280_DEVID_PCIE 0x002a
23728 #define AR9285_DEVID_PCIE 0x002b
23729 #define AR2427_DEVID_PCIE 0x002c
23730 +#define AR9287_DEVID_PCI 0x002d
23731 +#define AR9287_DEVID_PCIE 0x002e
23732 +#define AR9300_DEVID_PCIE 0x0030
23733
23734 #define AR5416_AR9100_DEVID 0x000b
23735
23736 @@ -48,9 +52,6 @@
23737 #define AR_SUBVENDOR_ID_NEW_A 0x7065
23738 #define AR5416_MAGIC 0x19641014
23739
23740 -#define AR5416_DEVID_AR9287_PCI 0x002D
23741 -#define AR5416_DEVID_AR9287_PCIE 0x002E
23742 -
23743 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
23744 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
23745 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
23746 @@ -75,6 +76,8 @@
23747 #define REG_RMW_FIELD(_a, _r, _f, _v) \
23748 REG_WRITE(_a, _r, \
23749 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
23750 +#define REG_READ_FIELD(_a, _r, _f) \
23751 + (((REG_READ(_a, _r) & _f) >> _f##_S))
23752 #define REG_SET_BIT(_a, _r, _f) \
23753 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
23754 #define REG_CLR_BIT(_a, _r, _f) \
23755 @@ -135,6 +138,16 @@
23756
23757 #define TU_TO_USEC(_tu) ((_tu) << 10)
23758
23759 +#define ATH9K_HW_RX_HP_QDEPTH 16
23760 +#define ATH9K_HW_RX_LP_QDEPTH 128
23761 +
23762 +enum ath_ini_subsys {
23763 + ATH_INI_PRE = 0,
23764 + ATH_INI_CORE,
23765 + ATH_INI_POST,
23766 + ATH_INI_NUM_SPLIT,
23767 +};
23768 +
23769 enum wireless_mode {
23770 ATH9K_MODE_11A = 0,
23771 ATH9K_MODE_11G,
23772 @@ -165,13 +178,15 @@ enum ath9k_hw_caps {
23773 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
23774 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
23775 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
23776 + ATH9K_HW_CAP_EDMA = BIT(17),
23777 + ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18),
23778 + ATH9K_HW_CAP_LDPC = BIT(19),
23779 };
23780
23781 enum ath9k_capability_type {
23782 ATH9K_CAP_CIPHER = 0,
23783 ATH9K_CAP_TKIP_MIC,
23784 ATH9K_CAP_TKIP_SPLIT,
23785 - ATH9K_CAP_DIVERSITY,
23786 ATH9K_CAP_TXPOW,
23787 ATH9K_CAP_MCAST_KEYSRCH,
23788 ATH9K_CAP_DS
23789 @@ -192,6 +207,11 @@ struct ath9k_hw_capabilities {
23790 u8 num_gpio_pins;
23791 u8 num_antcfg_2ghz;
23792 u8 num_antcfg_5ghz;
23793 + u8 rx_hp_qdepth;
23794 + u8 rx_lp_qdepth;
23795 + u8 rx_status_len;
23796 + u8 tx_desc_len;
23797 + u8 txs_len;
23798 };
23799
23800 struct ath9k_ops_config {
23801 @@ -212,6 +232,7 @@ struct ath9k_ops_config {
23802 u32 enable_ani;
23803 int serialize_regmode;
23804 bool rx_intr_mitigation;
23805 + bool tx_intr_mitigation;
23806 #define SPUR_DISABLE 0
23807 #define SPUR_ENABLE_IOCTL 1
23808 #define SPUR_ENABLE_EEPROM 2
23809 @@ -231,6 +252,8 @@ struct ath9k_ops_config {
23810 enum ath9k_int {
23811 ATH9K_INT_RX = 0x00000001,
23812 ATH9K_INT_RXDESC = 0x00000002,
23813 + ATH9K_INT_RXHP = 0x00000001,
23814 + ATH9K_INT_RXLP = 0x00000002,
23815 ATH9K_INT_RXNOFRM = 0x00000008,
23816 ATH9K_INT_RXEOL = 0x00000010,
23817 ATH9K_INT_RXORN = 0x00000020,
23818 @@ -440,6 +463,124 @@ struct ath_gen_timer_table {
23819 } timer_mask;
23820 };
23821
23822 +/**
23823 + * struct ath_hw_private_ops - callbacks used internally by hardware code
23824 + *
23825 + * This structure contains private callbacks designed to only be used internally
23826 + * by the hardware core.
23827 + *
23828 + * @init_cal_settings: setup types of calibrations supported
23829 + * @init_cal: starts actual calibration
23830 + *
23831 + * @init_mode_regs: Initializes mode registers
23832 + * @init_mode_gain_regs: Initialize TX/RX gain registers
23833 + * @macversion_supported: If this specific mac revision is supported
23834 + *
23835 + * @rf_set_freq: change frequency
23836 + * @spur_mitigate_freq: spur mitigation
23837 + * @rf_alloc_ext_banks:
23838 + * @rf_free_ext_banks:
23839 + * @set_rf_regs:
23840 + * @compute_pll_control: compute the PLL control value to use for
23841 + * AR_RTC_PLL_CONTROL for a given channel
23842 + * @setup_calibration: set up calibration
23843 + * @iscal_supported: used to query if a type of calibration is supported
23844 + * @loadnf: load noise floor read from each chain on the CCA registers
23845 + */
23846 +struct ath_hw_private_ops {
23847 + /* Calibration ops */
23848 + void (*init_cal_settings)(struct ath_hw *ah);
23849 + bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
23850 +
23851 + void (*init_mode_regs)(struct ath_hw *ah);
23852 + void (*init_mode_gain_regs)(struct ath_hw *ah);
23853 + bool (*macversion_supported)(u32 macversion);
23854 + void (*setup_calibration)(struct ath_hw *ah,
23855 + struct ath9k_cal_list *currCal);
23856 + bool (*iscal_supported)(struct ath_hw *ah,
23857 + enum ath9k_cal_types calType);
23858 +
23859 + /* PHY ops */
23860 + int (*rf_set_freq)(struct ath_hw *ah,
23861 + struct ath9k_channel *chan);
23862 + void (*spur_mitigate_freq)(struct ath_hw *ah,
23863 + struct ath9k_channel *chan);
23864 + int (*rf_alloc_ext_banks)(struct ath_hw *ah);
23865 + void (*rf_free_ext_banks)(struct ath_hw *ah);
23866 + bool (*set_rf_regs)(struct ath_hw *ah,
23867 + struct ath9k_channel *chan,
23868 + u16 modesIndex);
23869 + void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
23870 + void (*init_bb)(struct ath_hw *ah,
23871 + struct ath9k_channel *chan);
23872 + int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
23873 + void (*olc_init)(struct ath_hw *ah);
23874 + void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
23875 + void (*mark_phy_inactive)(struct ath_hw *ah);
23876 + void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
23877 + bool (*rfbus_req)(struct ath_hw *ah);
23878 + void (*rfbus_done)(struct ath_hw *ah);
23879 + void (*enable_rfkill)(struct ath_hw *ah);
23880 + void (*restore_chainmask)(struct ath_hw *ah);
23881 + void (*set_diversity)(struct ath_hw *ah, bool value);
23882 + u32 (*compute_pll_control)(struct ath_hw *ah,
23883 + struct ath9k_channel *chan);
23884 + bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
23885 + int param);
23886 + void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
23887 + void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
23888 +};
23889 +
23890 +/**
23891 + * struct ath_hw_ops - callbacks used by hardware code and driver code
23892 + *
23893 + * This structure contains callbacks designed to to be used internally by
23894 + * hardware code and also by the lower level driver.
23895 + *
23896 + * @config_pci_powersave:
23897 + * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
23898 + */
23899 +struct ath_hw_ops {
23900 + void (*config_pci_powersave)(struct ath_hw *ah,
23901 + int restore,
23902 + int power_off);
23903 + void (*rx_enable)(struct ath_hw *ah);
23904 + void (*set_desc_link)(void *ds, u32 link);
23905 + void (*get_desc_link)(void *ds, u32 **link);
23906 + bool (*calibrate)(struct ath_hw *ah,
23907 + struct ath9k_channel *chan,
23908 + u8 rxchainmask,
23909 + bool longcal);
23910 + bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
23911 + void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
23912 + bool is_firstseg, bool is_is_lastseg,
23913 + const void *ds0, dma_addr_t buf_addr,
23914 + unsigned int qcu);
23915 + int (*proc_txdesc)(struct ath_hw *ah, void *ds,
23916 + struct ath_tx_status *ts);
23917 + void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
23918 + u32 pktLen, enum ath9k_pkt_type type,
23919 + u32 txPower, u32 keyIx,
23920 + enum ath9k_key_type keyType,
23921 + u32 flags);
23922 + void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
23923 + void *lastds,
23924 + u32 durUpdateEn, u32 rtsctsRate,
23925 + u32 rtsctsDuration,
23926 + struct ath9k_11n_rate_series series[],
23927 + u32 nseries, u32 flags);
23928 + void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
23929 + u32 aggrLen);
23930 + void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
23931 + u32 numDelims);
23932 + void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
23933 + void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
23934 + void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
23935 + u32 burstDuration);
23936 + void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
23937 + u32 vmf);
23938 +};
23939 +
23940 struct ath_hw {
23941 struct ieee80211_hw *hw;
23942 struct ath_common common;
23943 @@ -453,14 +594,18 @@ struct ath_hw {
23944 struct ar5416_eeprom_def def;
23945 struct ar5416_eeprom_4k map4k;
23946 struct ar9287_eeprom map9287;
23947 + struct ar9300_eeprom ar9300_eep;
23948 } eeprom;
23949 const struct eeprom_ops *eep_ops;
23950 - enum ath9k_eep_map eep_map;
23951
23952 bool sw_mgmt_crypto;
23953 bool is_pciexpress;
23954 bool need_an_top2_fixup;
23955 u16 tx_trig_level;
23956 + s16 nf_2g_max;
23957 + s16 nf_2g_min;
23958 + s16 nf_5g_max;
23959 + s16 nf_5g_min;
23960 u16 rfsilent;
23961 u32 rfkill_gpio;
23962 u32 rfkill_polarity;
23963 @@ -493,6 +638,7 @@ struct ath_hw {
23964 struct ath9k_cal_list adcgain_caldata;
23965 struct ath9k_cal_list adcdc_calinitdata;
23966 struct ath9k_cal_list adcdc_caldata;
23967 + struct ath9k_cal_list tempCompCalData;
23968 struct ath9k_cal_list *cal_list;
23969 struct ath9k_cal_list *cal_list_last;
23970 struct ath9k_cal_list *cal_list_curr;
23971 @@ -533,12 +679,10 @@ struct ath_hw {
23972 DONT_USE_32KHZ,
23973 } enable_32kHz_clock;
23974
23975 - /* Callback for radio frequency change */
23976 - int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan);
23977 -
23978 - /* Callback for baseband spur frequency */
23979 - void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
23980 - struct ath9k_channel *chan);
23981 + /* Private to hardware code */
23982 + struct ath_hw_private_ops private_ops;
23983 + /* Accessed by the lower level driver */
23984 + struct ath_hw_ops ops;
23985
23986 /* Used to program the radio on non single-chip devices */
23987 u32 *analogBank0Data;
23988 @@ -592,6 +736,7 @@ struct ath_hw {
23989 struct ar5416IniArray iniBank7;
23990 struct ar5416IniArray iniAddac;
23991 struct ar5416IniArray iniPcieSerdes;
23992 + struct ar5416IniArray iniPcieSerdesLowPower;
23993 struct ar5416IniArray iniModesAdditional;
23994 struct ar5416IniArray iniModesRxGain;
23995 struct ar5416IniArray iniModesTxGain;
23996 @@ -604,9 +749,21 @@ struct ath_hw {
23997 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
23998 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
23999
24000 + struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
24001 + struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
24002 + struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
24003 + struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
24004 +
24005 u32 intr_gen_timer_trigger;
24006 u32 intr_gen_timer_thresh;
24007 struct ath_gen_timer_table hw_gen_timers;
24008 +
24009 + struct ar9003_txs *ts_ring;
24010 + void *ts_start;
24011 + u32 ts_paddr_start;
24012 + u32 ts_paddr_end;
24013 + u16 ts_tail;
24014 + u8 ts_size;
24015 };
24016
24017 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
24018 @@ -619,6 +776,16 @@ static inline struct ath_regulatory *ath
24019 return &(ath9k_hw_common(ah)->regulatory);
24020 }
24021
24022 +static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
24023 +{
24024 + return &ah->private_ops;
24025 +}
24026 +
24027 +static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
24028 +{
24029 + return &ah->ops;
24030 +}
24031 +
24032 /* Initialization, Detach, Reset */
24033 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
24034 void ath9k_hw_deinit(struct ath_hw *ah);
24035 @@ -630,6 +797,7 @@ bool ath9k_hw_getcapability(struct ath_h
24036 u32 capability, u32 *result);
24037 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
24038 u32 capability, u32 setting, int *status);
24039 +u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
24040
24041 /* Key Cache Management */
24042 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
24043 @@ -681,13 +849,6 @@ void ath9k_hw_set_sta_beacon_timers(stru
24044
24045 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
24046
24047 -void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
24048 -
24049 -/* Interrupt Handling */
24050 -bool ath9k_hw_intrpend(struct ath_hw *ah);
24051 -bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
24052 -enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
24053 -
24054 /* Generic hw timer primitives */
24055 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
24056 void (*trigger)(void *),
24057 @@ -709,6 +870,36 @@ void ath9k_hw_name(struct ath_hw *ah, ch
24058 /* HTC */
24059 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
24060
24061 +/* PHY */
24062 +void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
24063 + u32 *coef_mantissa, u32 *coef_exponent);
24064 +
24065 +/*
24066 + * Code Specific to AR5008, AR9001 or AR9002,
24067 + * we stuff these here to avoid callbacks for AR9003.
24068 + */
24069 +void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
24070 +int ar9002_hw_rf_claim(struct ath_hw *ah);
24071 +void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
24072 +void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
24073 +
24074 +/*
24075 + * Code specifric to AR9003, we stuff these here to avoid callbacks
24076 + * for older families
24077 + */
24078 +void ar9003_hw_set_nf_limits(struct ath_hw *ah);
24079 +
24080 +/* Hardware family op attach helpers */
24081 +void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
24082 +void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
24083 +void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
24084 +
24085 +void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
24086 +void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
24087 +
24088 +void ar9002_hw_attach_ops(struct ath_hw *ah);
24089 +void ar9003_hw_attach_ops(struct ath_hw *ah);
24090 +
24091 #define ATH_PCIE_CAP_LINK_CTRL 0x70
24092 #define ATH_PCIE_CAP_LINK_L0S 1
24093 #define ATH_PCIE_CAP_LINK_L1 2
24094 --- a/drivers/net/wireless/ath/ath9k/init.c
24095 +++ b/drivers/net/wireless/ath/ath9k/init.c
24096 @@ -191,6 +191,9 @@ static void setup_ht_cap(struct ath_soft
24097 IEEE80211_HT_CAP_SGI_40 |
24098 IEEE80211_HT_CAP_DSSSCCK40;
24099
24100 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
24101 + ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
24102 +
24103 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
24104 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
24105
24106 @@ -235,31 +238,37 @@ static int ath9k_reg_notifier(struct wip
24107 */
24108 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
24109 struct list_head *head, const char *name,
24110 - int nbuf, int ndesc)
24111 + int nbuf, int ndesc, bool is_tx)
24112 {
24113 #define DS2PHYS(_dd, _ds) \
24114 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
24115 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
24116 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
24117 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
24118 - struct ath_desc *ds;
24119 + u8 *ds;
24120 struct ath_buf *bf;
24121 - int i, bsize, error;
24122 + int i, bsize, error, desc_len;
24123
24124 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
24125 name, nbuf, ndesc);
24126
24127 INIT_LIST_HEAD(head);
24128 +
24129 + if (is_tx)
24130 + desc_len = sc->sc_ah->caps.tx_desc_len;
24131 + else
24132 + desc_len = sizeof(struct ath_desc);
24133 +
24134 /* ath_desc must be a multiple of DWORDs */
24135 - if ((sizeof(struct ath_desc) % 4) != 0) {
24136 + if ((desc_len % 4) != 0) {
24137 ath_print(common, ATH_DBG_FATAL,
24138 "ath_desc not DWORD aligned\n");
24139 - BUG_ON((sizeof(struct ath_desc) % 4) != 0);
24140 + BUG_ON((desc_len % 4) != 0);
24141 error = -ENOMEM;
24142 goto fail;
24143 }
24144
24145 - dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
24146 + dd->dd_desc_len = desc_len * nbuf * ndesc;
24147
24148 /*
24149 * Need additional DMA memory because we can't use
24150 @@ -272,7 +281,7 @@ int ath_descdma_setup(struct ath_softc *
24151 u32 dma_len;
24152
24153 while (ndesc_skipped) {
24154 - dma_len = ndesc_skipped * sizeof(struct ath_desc);
24155 + dma_len = ndesc_skipped * desc_len;
24156 dd->dd_desc_len += dma_len;
24157
24158 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
24159 @@ -286,7 +295,7 @@ int ath_descdma_setup(struct ath_softc *
24160 error = -ENOMEM;
24161 goto fail;
24162 }
24163 - ds = dd->dd_desc;
24164 + ds = (u8 *) dd->dd_desc;
24165 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
24166 name, ds, (u32) dd->dd_desc_len,
24167 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
24168 @@ -300,7 +309,7 @@ int ath_descdma_setup(struct ath_softc *
24169 }
24170 dd->dd_bufptr = bf;
24171
24172 - for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
24173 + for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
24174 bf->bf_desc = ds;
24175 bf->bf_daddr = DS2PHYS(dd, ds);
24176
24177 @@ -316,7 +325,7 @@ int ath_descdma_setup(struct ath_softc *
24178 ((caddr_t) dd->dd_desc +
24179 dd->dd_desc_len));
24180
24181 - ds += ndesc;
24182 + ds += (desc_len * ndesc);
24183 bf->bf_desc = ds;
24184 bf->bf_daddr = DS2PHYS(dd, ds);
24185 }
24186 @@ -514,7 +523,7 @@ static void ath9k_init_misc(struct ath_s
24187 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
24188 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
24189
24190 - ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
24191 + ath9k_hw_set_diversity(sc->sc_ah, true);
24192 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
24193
24194 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
24195 @@ -568,13 +577,10 @@ static int ath9k_init_softc(u16 devid, s
24196 ath_read_cachesize(common, &csz);
24197 common->cachelsz = csz << 2; /* convert to bytes */
24198
24199 + /* Initializes the hardware for all supported chipsets */
24200 ret = ath9k_hw_init(ah);
24201 - if (ret) {
24202 - ath_print(common, ATH_DBG_FATAL,
24203 - "Unable to initialize hardware; "
24204 - "initialization status: %d\n", ret);
24205 + if (ret)
24206 goto err_hw;
24207 - }
24208
24209 ret = ath9k_init_debug(ah);
24210 if (ret) {
24211 --- a/drivers/net/wireless/ath/ath9k/initvals.h
24212 +++ /dev/null
24213 @@ -1,7200 +0,0 @@
24214 -/*
24215 - * Copyright (c) 2008-2009 Atheros Communications Inc.
24216 - *
24217 - * Permission to use, copy, modify, and/or distribute this software for any
24218 - * purpose with or without fee is hereby granted, provided that the above
24219 - * copyright notice and this permission notice appear in all copies.
24220 - *
24221 - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
24222 - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
24223 - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
24224 - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
24225 - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
24226 - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
24227 - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24228 - */
24229 -
24230 -static const u32 ar5416Modes[][6] = {
24231 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
24232 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
24233 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
24234 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
24235 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
24236 - { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
24237 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
24238 - { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
24239 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
24240 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
24241 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
24242 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
24243 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
24244 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
24245 - { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
24246 - { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
24247 - { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
24248 - { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
24249 - { 0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de, 0x6c48b0de },
24250 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
24251 - { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
24252 - { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 },
24253 - { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
24254 - { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 },
24255 - { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
24256 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
24257 - { 0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134, 0x00000134 },
24258 - { 0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b },
24259 - { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
24260 - { 0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
24261 - { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
24262 - { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
24263 - { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 },
24264 - { 0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 },
24265 - { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
24266 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
24267 - { 0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c },
24268 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
24269 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
24270 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24271 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24272 - { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
24273 - { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
24274 - { 0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
24275 - { 0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
24276 - { 0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
24277 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
24278 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
24279 - { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
24280 - { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
24281 - { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
24282 - { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
24283 - { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
24284 - { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
24285 - { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
24286 - { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
24287 - { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
24288 - { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
24289 - { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
24290 - { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
24291 - { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24292 - { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24293 - { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24294 -};
24295 -
24296 -static const u32 ar5416Common[][2] = {
24297 - { 0x0000000c, 0x00000000 },
24298 - { 0x00000030, 0x00020015 },
24299 - { 0x00000034, 0x00000005 },
24300 - { 0x00000040, 0x00000000 },
24301 - { 0x00000044, 0x00000008 },
24302 - { 0x00000048, 0x00000008 },
24303 - { 0x0000004c, 0x00000010 },
24304 - { 0x00000050, 0x00000000 },
24305 - { 0x00000054, 0x0000001f },
24306 - { 0x00000800, 0x00000000 },
24307 - { 0x00000804, 0x00000000 },
24308 - { 0x00000808, 0x00000000 },
24309 - { 0x0000080c, 0x00000000 },
24310 - { 0x00000810, 0x00000000 },
24311 - { 0x00000814, 0x00000000 },
24312 - { 0x00000818, 0x00000000 },
24313 - { 0x0000081c, 0x00000000 },
24314 - { 0x00000820, 0x00000000 },
24315 - { 0x00000824, 0x00000000 },
24316 - { 0x00001040, 0x002ffc0f },
24317 - { 0x00001044, 0x002ffc0f },
24318 - { 0x00001048, 0x002ffc0f },
24319 - { 0x0000104c, 0x002ffc0f },
24320 - { 0x00001050, 0x002ffc0f },
24321 - { 0x00001054, 0x002ffc0f },
24322 - { 0x00001058, 0x002ffc0f },
24323 - { 0x0000105c, 0x002ffc0f },
24324 - { 0x00001060, 0x002ffc0f },
24325 - { 0x00001064, 0x002ffc0f },
24326 - { 0x00001230, 0x00000000 },
24327 - { 0x00001270, 0x00000000 },
24328 - { 0x00001038, 0x00000000 },
24329 - { 0x00001078, 0x00000000 },
24330 - { 0x000010b8, 0x00000000 },
24331 - { 0x000010f8, 0x00000000 },
24332 - { 0x00001138, 0x00000000 },
24333 - { 0x00001178, 0x00000000 },
24334 - { 0x000011b8, 0x00000000 },
24335 - { 0x000011f8, 0x00000000 },
24336 - { 0x00001238, 0x00000000 },
24337 - { 0x00001278, 0x00000000 },
24338 - { 0x000012b8, 0x00000000 },
24339 - { 0x000012f8, 0x00000000 },
24340 - { 0x00001338, 0x00000000 },
24341 - { 0x00001378, 0x00000000 },
24342 - { 0x000013b8, 0x00000000 },
24343 - { 0x000013f8, 0x00000000 },
24344 - { 0x00001438, 0x00000000 },
24345 - { 0x00001478, 0x00000000 },
24346 - { 0x000014b8, 0x00000000 },
24347 - { 0x000014f8, 0x00000000 },
24348 - { 0x00001538, 0x00000000 },
24349 - { 0x00001578, 0x00000000 },
24350 - { 0x000015b8, 0x00000000 },
24351 - { 0x000015f8, 0x00000000 },
24352 - { 0x00001638, 0x00000000 },
24353 - { 0x00001678, 0x00000000 },
24354 - { 0x000016b8, 0x00000000 },
24355 - { 0x000016f8, 0x00000000 },
24356 - { 0x00001738, 0x00000000 },
24357 - { 0x00001778, 0x00000000 },
24358 - { 0x000017b8, 0x00000000 },
24359 - { 0x000017f8, 0x00000000 },
24360 - { 0x0000103c, 0x00000000 },
24361 - { 0x0000107c, 0x00000000 },
24362 - { 0x000010bc, 0x00000000 },
24363 - { 0x000010fc, 0x00000000 },
24364 - { 0x0000113c, 0x00000000 },
24365 - { 0x0000117c, 0x00000000 },
24366 - { 0x000011bc, 0x00000000 },
24367 - { 0x000011fc, 0x00000000 },
24368 - { 0x0000123c, 0x00000000 },
24369 - { 0x0000127c, 0x00000000 },
24370 - { 0x000012bc, 0x00000000 },
24371 - { 0x000012fc, 0x00000000 },
24372 - { 0x0000133c, 0x00000000 },
24373 - { 0x0000137c, 0x00000000 },
24374 - { 0x000013bc, 0x00000000 },
24375 - { 0x000013fc, 0x00000000 },
24376 - { 0x0000143c, 0x00000000 },
24377 - { 0x0000147c, 0x00000000 },
24378 - { 0x00004030, 0x00000002 },
24379 - { 0x0000403c, 0x00000002 },
24380 - { 0x00007010, 0x00000000 },
24381 - { 0x00007038, 0x000004c2 },
24382 - { 0x00008004, 0x00000000 },
24383 - { 0x00008008, 0x00000000 },
24384 - { 0x0000800c, 0x00000000 },
24385 - { 0x00008018, 0x00000700 },
24386 - { 0x00008020, 0x00000000 },
24387 - { 0x00008038, 0x00000000 },
24388 - { 0x0000803c, 0x00000000 },
24389 - { 0x00008048, 0x40000000 },
24390 - { 0x00008054, 0x00000000 },
24391 - { 0x00008058, 0x00000000 },
24392 - { 0x0000805c, 0x000fc78f },
24393 - { 0x00008060, 0x0000000f },
24394 - { 0x00008064, 0x00000000 },
24395 - { 0x000080c0, 0x2a82301a },
24396 - { 0x000080c4, 0x05dc01e0 },
24397 - { 0x000080c8, 0x1f402710 },
24398 - { 0x000080cc, 0x01f40000 },
24399 - { 0x000080d0, 0x00001e00 },
24400 - { 0x000080d4, 0x00000000 },
24401 - { 0x000080d8, 0x00400000 },
24402 - { 0x000080e0, 0xffffffff },
24403 - { 0x000080e4, 0x0000ffff },
24404 - { 0x000080e8, 0x003f3f3f },
24405 - { 0x000080ec, 0x00000000 },
24406 - { 0x000080f0, 0x00000000 },
24407 - { 0x000080f4, 0x00000000 },
24408 - { 0x000080f8, 0x00000000 },
24409 - { 0x000080fc, 0x00020000 },
24410 - { 0x00008100, 0x00020000 },
24411 - { 0x00008104, 0x00000001 },
24412 - { 0x00008108, 0x00000052 },
24413 - { 0x0000810c, 0x00000000 },
24414 - { 0x00008110, 0x00000168 },
24415 - { 0x00008118, 0x000100aa },
24416 - { 0x0000811c, 0x00003210 },
24417 - { 0x00008124, 0x00000000 },
24418 - { 0x00008128, 0x00000000 },
24419 - { 0x0000812c, 0x00000000 },
24420 - { 0x00008130, 0x00000000 },
24421 - { 0x00008134, 0x00000000 },
24422 - { 0x00008138, 0x00000000 },
24423 - { 0x0000813c, 0x00000000 },
24424 - { 0x00008144, 0xffffffff },
24425 - { 0x00008168, 0x00000000 },
24426 - { 0x0000816c, 0x00000000 },
24427 - { 0x00008170, 0x32143320 },
24428 - { 0x00008174, 0xfaa4fa50 },
24429 - { 0x00008178, 0x00000100 },
24430 - { 0x0000817c, 0x00000000 },
24431 - { 0x000081c4, 0x00000000 },
24432 - { 0x000081ec, 0x00000000 },
24433 - { 0x000081f0, 0x00000000 },
24434 - { 0x000081f4, 0x00000000 },
24435 - { 0x000081f8, 0x00000000 },
24436 - { 0x000081fc, 0x00000000 },
24437 - { 0x00008200, 0x00000000 },
24438 - { 0x00008204, 0x00000000 },
24439 - { 0x00008208, 0x00000000 },
24440 - { 0x0000820c, 0x00000000 },
24441 - { 0x00008210, 0x00000000 },
24442 - { 0x00008214, 0x00000000 },
24443 - { 0x00008218, 0x00000000 },
24444 - { 0x0000821c, 0x00000000 },
24445 - { 0x00008220, 0x00000000 },
24446 - { 0x00008224, 0x00000000 },
24447 - { 0x00008228, 0x00000000 },
24448 - { 0x0000822c, 0x00000000 },
24449 - { 0x00008230, 0x00000000 },
24450 - { 0x00008234, 0x00000000 },
24451 - { 0x00008238, 0x00000000 },
24452 - { 0x0000823c, 0x00000000 },
24453 - { 0x00008240, 0x00100000 },
24454 - { 0x00008244, 0x0010f400 },
24455 - { 0x00008248, 0x00000100 },
24456 - { 0x0000824c, 0x0001e800 },
24457 - { 0x00008250, 0x00000000 },
24458 - { 0x00008254, 0x00000000 },
24459 - { 0x00008258, 0x00000000 },
24460 - { 0x0000825c, 0x400000ff },
24461 - { 0x00008260, 0x00080922 },
24462 - { 0x00008264, 0xa8000010 },
24463 - { 0x00008270, 0x00000000 },
24464 - { 0x00008274, 0x40000000 },
24465 - { 0x00008278, 0x003e4180 },
24466 - { 0x0000827c, 0x00000000 },
24467 - { 0x00008284, 0x0000002c },
24468 - { 0x00008288, 0x0000002c },
24469 - { 0x0000828c, 0x00000000 },
24470 - { 0x00008294, 0x00000000 },
24471 - { 0x00008298, 0x00000000 },
24472 - { 0x00008300, 0x00000000 },
24473 - { 0x00008304, 0x00000000 },
24474 - { 0x00008308, 0x00000000 },
24475 - { 0x0000830c, 0x00000000 },
24476 - { 0x00008310, 0x00000000 },
24477 - { 0x00008314, 0x00000000 },
24478 - { 0x00008318, 0x00000000 },
24479 - { 0x00008328, 0x00000000 },
24480 - { 0x0000832c, 0x00000007 },
24481 - { 0x00008330, 0x00000302 },
24482 - { 0x00008334, 0x00000e00 },
24483 - { 0x00008338, 0x00070000 },
24484 - { 0x0000833c, 0x00000000 },
24485 - { 0x00008340, 0x000107ff },
24486 - { 0x00009808, 0x00000000 },
24487 - { 0x0000980c, 0xad848e19 },
24488 - { 0x00009810, 0x7d14e000 },
24489 - { 0x00009814, 0x9c0a9f6b },
24490 - { 0x0000981c, 0x00000000 },
24491 - { 0x0000982c, 0x0000a000 },
24492 - { 0x00009830, 0x00000000 },
24493 - { 0x0000983c, 0x00200400 },
24494 - { 0x00009840, 0x206a002e },
24495 - { 0x0000984c, 0x1284233c },
24496 - { 0x00009854, 0x00000859 },
24497 - { 0x00009900, 0x00000000 },
24498 - { 0x00009904, 0x00000000 },
24499 - { 0x00009908, 0x00000000 },
24500 - { 0x0000990c, 0x00000000 },
24501 - { 0x0000991c, 0x10000fff },
24502 - { 0x00009920, 0x05100000 },
24503 - { 0x0000a920, 0x05100000 },
24504 - { 0x0000b920, 0x05100000 },
24505 - { 0x00009928, 0x00000001 },
24506 - { 0x0000992c, 0x00000004 },
24507 - { 0x00009934, 0x1e1f2022 },
24508 - { 0x00009938, 0x0a0b0c0d },
24509 - { 0x0000993c, 0x00000000 },
24510 - { 0x00009948, 0x9280b212 },
24511 - { 0x0000994c, 0x00020028 },
24512 - { 0x00009954, 0x5d50e188 },
24513 - { 0x00009958, 0x00081fff },
24514 - { 0x0000c95c, 0x004b6a8e },
24515 - { 0x0000c968, 0x000003ce },
24516 - { 0x00009970, 0x190fb515 },
24517 - { 0x00009974, 0x00000000 },
24518 - { 0x00009978, 0x00000001 },
24519 - { 0x0000997c, 0x00000000 },
24520 - { 0x00009980, 0x00000000 },
24521 - { 0x00009984, 0x00000000 },
24522 - { 0x00009988, 0x00000000 },
24523 - { 0x0000998c, 0x00000000 },
24524 - { 0x00009990, 0x00000000 },
24525 - { 0x00009994, 0x00000000 },
24526 - { 0x00009998, 0x00000000 },
24527 - { 0x0000999c, 0x00000000 },
24528 - { 0x000099a0, 0x00000000 },
24529 - { 0x000099a4, 0x00000001 },
24530 - { 0x000099a8, 0x001fff00 },
24531 - { 0x000099ac, 0x00000000 },
24532 - { 0x000099b0, 0x03051000 },
24533 - { 0x000099dc, 0x00000000 },
24534 - { 0x000099e0, 0x00000200 },
24535 - { 0x000099e4, 0xaaaaaaaa },
24536 - { 0x000099e8, 0x3c466478 },
24537 - { 0x000099ec, 0x000000aa },
24538 - { 0x000099fc, 0x00001042 },
24539 - { 0x00009b00, 0x00000000 },
24540 - { 0x00009b04, 0x00000001 },
24541 - { 0x00009b08, 0x00000002 },
24542 - { 0x00009b0c, 0x00000003 },
24543 - { 0x00009b10, 0x00000004 },
24544 - { 0x00009b14, 0x00000005 },
24545 - { 0x00009b18, 0x00000008 },
24546 - { 0x00009b1c, 0x00000009 },
24547 - { 0x00009b20, 0x0000000a },
24548 - { 0x00009b24, 0x0000000b },
24549 - { 0x00009b28, 0x0000000c },
24550 - { 0x00009b2c, 0x0000000d },
24551 - { 0x00009b30, 0x00000010 },
24552 - { 0x00009b34, 0x00000011 },
24553 - { 0x00009b38, 0x00000012 },
24554 - { 0x00009b3c, 0x00000013 },
24555 - { 0x00009b40, 0x00000014 },
24556 - { 0x00009b44, 0x00000015 },
24557 - { 0x00009b48, 0x00000018 },
24558 - { 0x00009b4c, 0x00000019 },
24559 - { 0x00009b50, 0x0000001a },
24560 - { 0x00009b54, 0x0000001b },
24561 - { 0x00009b58, 0x0000001c },
24562 - { 0x00009b5c, 0x0000001d },
24563 - { 0x00009b60, 0x00000020 },
24564 - { 0x00009b64, 0x00000021 },
24565 - { 0x00009b68, 0x00000022 },
24566 - { 0x00009b6c, 0x00000023 },
24567 - { 0x00009b70, 0x00000024 },
24568 - { 0x00009b74, 0x00000025 },
24569 - { 0x00009b78, 0x00000028 },
24570 - { 0x00009b7c, 0x00000029 },
24571 - { 0x00009b80, 0x0000002a },
24572 - { 0x00009b84, 0x0000002b },
24573 - { 0x00009b88, 0x0000002c },
24574 - { 0x00009b8c, 0x0000002d },
24575 - { 0x00009b90, 0x00000030 },
24576 - { 0x00009b94, 0x00000031 },
24577 - { 0x00009b98, 0x00000032 },
24578 - { 0x00009b9c, 0x00000033 },
24579 - { 0x00009ba0, 0x00000034 },
24580 - { 0x00009ba4, 0x00000035 },
24581 - { 0x00009ba8, 0x00000035 },
24582 - { 0x00009bac, 0x00000035 },
24583 - { 0x00009bb0, 0x00000035 },
24584 - { 0x00009bb4, 0x00000035 },
24585 - { 0x00009bb8, 0x00000035 },
24586 - { 0x00009bbc, 0x00000035 },
24587 - { 0x00009bc0, 0x00000035 },
24588 - { 0x00009bc4, 0x00000035 },
24589 - { 0x00009bc8, 0x00000035 },
24590 - { 0x00009bcc, 0x00000035 },
24591 - { 0x00009bd0, 0x00000035 },
24592 - { 0x00009bd4, 0x00000035 },
24593 - { 0x00009bd8, 0x00000035 },
24594 - { 0x00009bdc, 0x00000035 },
24595 - { 0x00009be0, 0x00000035 },
24596 - { 0x00009be4, 0x00000035 },
24597 - { 0x00009be8, 0x00000035 },
24598 - { 0x00009bec, 0x00000035 },
24599 - { 0x00009bf0, 0x00000035 },
24600 - { 0x00009bf4, 0x00000035 },
24601 - { 0x00009bf8, 0x00000010 },
24602 - { 0x00009bfc, 0x0000001a },
24603 - { 0x0000a210, 0x40806333 },
24604 - { 0x0000a214, 0x00106c10 },
24605 - { 0x0000a218, 0x009c4060 },
24606 - { 0x0000a220, 0x018830c6 },
24607 - { 0x0000a224, 0x00000400 },
24608 - { 0x0000a228, 0x00000bb5 },
24609 - { 0x0000a22c, 0x00000011 },
24610 - { 0x0000a234, 0x20202020 },
24611 - { 0x0000a238, 0x20202020 },
24612 - { 0x0000a23c, 0x13c889af },
24613 - { 0x0000a240, 0x38490a20 },
24614 - { 0x0000a244, 0x00007bb6 },
24615 - { 0x0000a248, 0x0fff3ffc },
24616 - { 0x0000a24c, 0x00000001 },
24617 - { 0x0000a250, 0x0000a000 },
24618 - { 0x0000a254, 0x00000000 },
24619 - { 0x0000a258, 0x0cc75380 },
24620 - { 0x0000a25c, 0x0f0f0f01 },
24621 - { 0x0000a260, 0xdfa91f01 },
24622 - { 0x0000a268, 0x00000000 },
24623 - { 0x0000a26c, 0x0e79e5c6 },
24624 - { 0x0000b26c, 0x0e79e5c6 },
24625 - { 0x0000c26c, 0x0e79e5c6 },
24626 - { 0x0000d270, 0x00820820 },
24627 - { 0x0000a278, 0x1ce739ce },
24628 - { 0x0000a27c, 0x051701ce },
24629 - { 0x0000a338, 0x00000000 },
24630 - { 0x0000a33c, 0x00000000 },
24631 - { 0x0000a340, 0x00000000 },
24632 - { 0x0000a344, 0x00000000 },
24633 - { 0x0000a348, 0x3fffffff },
24634 - { 0x0000a34c, 0x3fffffff },
24635 - { 0x0000a350, 0x3fffffff },
24636 - { 0x0000a354, 0x0003ffff },
24637 - { 0x0000a358, 0x79a8aa1f },
24638 - { 0x0000d35c, 0x07ffffef },
24639 - { 0x0000d360, 0x0fffffe7 },
24640 - { 0x0000d364, 0x17ffffe5 },
24641 - { 0x0000d368, 0x1fffffe4 },
24642 - { 0x0000d36c, 0x37ffffe3 },
24643 - { 0x0000d370, 0x3fffffe3 },
24644 - { 0x0000d374, 0x57ffffe3 },
24645 - { 0x0000d378, 0x5fffffe2 },
24646 - { 0x0000d37c, 0x7fffffe2 },
24647 - { 0x0000d380, 0x7f3c7bba },
24648 - { 0x0000d384, 0xf3307ff0 },
24649 - { 0x0000a388, 0x08000000 },
24650 - { 0x0000a38c, 0x20202020 },
24651 - { 0x0000a390, 0x20202020 },
24652 - { 0x0000a394, 0x1ce739ce },
24653 - { 0x0000a398, 0x000001ce },
24654 - { 0x0000a39c, 0x00000001 },
24655 - { 0x0000a3a0, 0x00000000 },
24656 - { 0x0000a3a4, 0x00000000 },
24657 - { 0x0000a3a8, 0x00000000 },
24658 - { 0x0000a3ac, 0x00000000 },
24659 - { 0x0000a3b0, 0x00000000 },
24660 - { 0x0000a3b4, 0x00000000 },
24661 - { 0x0000a3b8, 0x00000000 },
24662 - { 0x0000a3bc, 0x00000000 },
24663 - { 0x0000a3c0, 0x00000000 },
24664 - { 0x0000a3c4, 0x00000000 },
24665 - { 0x0000a3c8, 0x00000246 },
24666 - { 0x0000a3cc, 0x20202020 },
24667 - { 0x0000a3d0, 0x20202020 },
24668 - { 0x0000a3d4, 0x20202020 },
24669 - { 0x0000a3dc, 0x1ce739ce },
24670 - { 0x0000a3e0, 0x000001ce },
24671 -};
24672 -
24673 -static const u32 ar5416Bank0[][2] = {
24674 - { 0x000098b0, 0x1e5795e5 },
24675 - { 0x000098e0, 0x02008020 },
24676 -};
24677 -
24678 -static const u32 ar5416BB_RfGain[][3] = {
24679 - { 0x00009a00, 0x00000000, 0x00000000 },
24680 - { 0x00009a04, 0x00000040, 0x00000040 },
24681 - { 0x00009a08, 0x00000080, 0x00000080 },
24682 - { 0x00009a0c, 0x000001a1, 0x00000141 },
24683 - { 0x00009a10, 0x000001e1, 0x00000181 },
24684 - { 0x00009a14, 0x00000021, 0x000001c1 },
24685 - { 0x00009a18, 0x00000061, 0x00000001 },
24686 - { 0x00009a1c, 0x00000168, 0x00000041 },
24687 - { 0x00009a20, 0x000001a8, 0x000001a8 },
24688 - { 0x00009a24, 0x000001e8, 0x000001e8 },
24689 - { 0x00009a28, 0x00000028, 0x00000028 },
24690 - { 0x00009a2c, 0x00000068, 0x00000068 },
24691 - { 0x00009a30, 0x00000189, 0x000000a8 },
24692 - { 0x00009a34, 0x000001c9, 0x00000169 },
24693 - { 0x00009a38, 0x00000009, 0x000001a9 },
24694 - { 0x00009a3c, 0x00000049, 0x000001e9 },
24695 - { 0x00009a40, 0x00000089, 0x00000029 },
24696 - { 0x00009a44, 0x00000170, 0x00000069 },
24697 - { 0x00009a48, 0x000001b0, 0x00000190 },
24698 - { 0x00009a4c, 0x000001f0, 0x000001d0 },
24699 - { 0x00009a50, 0x00000030, 0x00000010 },
24700 - { 0x00009a54, 0x00000070, 0x00000050 },
24701 - { 0x00009a58, 0x00000191, 0x00000090 },
24702 - { 0x00009a5c, 0x000001d1, 0x00000151 },
24703 - { 0x00009a60, 0x00000011, 0x00000191 },
24704 - { 0x00009a64, 0x00000051, 0x000001d1 },
24705 - { 0x00009a68, 0x00000091, 0x00000011 },
24706 - { 0x00009a6c, 0x000001b8, 0x00000051 },
24707 - { 0x00009a70, 0x000001f8, 0x00000198 },
24708 - { 0x00009a74, 0x00000038, 0x000001d8 },
24709 - { 0x00009a78, 0x00000078, 0x00000018 },
24710 - { 0x00009a7c, 0x00000199, 0x00000058 },
24711 - { 0x00009a80, 0x000001d9, 0x00000098 },
24712 - { 0x00009a84, 0x00000019, 0x00000159 },
24713 - { 0x00009a88, 0x00000059, 0x00000199 },
24714 - { 0x00009a8c, 0x00000099, 0x000001d9 },
24715 - { 0x00009a90, 0x000000d9, 0x00000019 },
24716 - { 0x00009a94, 0x000000f9, 0x00000059 },
24717 - { 0x00009a98, 0x000000f9, 0x00000099 },
24718 - { 0x00009a9c, 0x000000f9, 0x000000d9 },
24719 - { 0x00009aa0, 0x000000f9, 0x000000f9 },
24720 - { 0x00009aa4, 0x000000f9, 0x000000f9 },
24721 - { 0x00009aa8, 0x000000f9, 0x000000f9 },
24722 - { 0x00009aac, 0x000000f9, 0x000000f9 },
24723 - { 0x00009ab0, 0x000000f9, 0x000000f9 },
24724 - { 0x00009ab4, 0x000000f9, 0x000000f9 },
24725 - { 0x00009ab8, 0x000000f9, 0x000000f9 },
24726 - { 0x00009abc, 0x000000f9, 0x000000f9 },
24727 - { 0x00009ac0, 0x000000f9, 0x000000f9 },
24728 - { 0x00009ac4, 0x000000f9, 0x000000f9 },
24729 - { 0x00009ac8, 0x000000f9, 0x000000f9 },
24730 - { 0x00009acc, 0x000000f9, 0x000000f9 },
24731 - { 0x00009ad0, 0x000000f9, 0x000000f9 },
24732 - { 0x00009ad4, 0x000000f9, 0x000000f9 },
24733 - { 0x00009ad8, 0x000000f9, 0x000000f9 },
24734 - { 0x00009adc, 0x000000f9, 0x000000f9 },
24735 - { 0x00009ae0, 0x000000f9, 0x000000f9 },
24736 - { 0x00009ae4, 0x000000f9, 0x000000f9 },
24737 - { 0x00009ae8, 0x000000f9, 0x000000f9 },
24738 - { 0x00009aec, 0x000000f9, 0x000000f9 },
24739 - { 0x00009af0, 0x000000f9, 0x000000f9 },
24740 - { 0x00009af4, 0x000000f9, 0x000000f9 },
24741 - { 0x00009af8, 0x000000f9, 0x000000f9 },
24742 - { 0x00009afc, 0x000000f9, 0x000000f9 },
24743 -};
24744 -
24745 -static const u32 ar5416Bank1[][2] = {
24746 - { 0x000098b0, 0x02108421 },
24747 - { 0x000098ec, 0x00000008 },
24748 -};
24749 -
24750 -static const u32 ar5416Bank2[][2] = {
24751 - { 0x000098b0, 0x0e73ff17 },
24752 - { 0x000098e0, 0x00000420 },
24753 -};
24754 -
24755 -static const u32 ar5416Bank3[][3] = {
24756 - { 0x000098f0, 0x01400018, 0x01c00018 },
24757 -};
24758 -
24759 -static const u32 ar5416Bank6[][3] = {
24760 -
24761 - { 0x0000989c, 0x00000000, 0x00000000 },
24762 - { 0x0000989c, 0x00000000, 0x00000000 },
24763 - { 0x0000989c, 0x00000000, 0x00000000 },
24764 - { 0x0000989c, 0x00e00000, 0x00e00000 },
24765 - { 0x0000989c, 0x005e0000, 0x005e0000 },
24766 - { 0x0000989c, 0x00120000, 0x00120000 },
24767 - { 0x0000989c, 0x00620000, 0x00620000 },
24768 - { 0x0000989c, 0x00020000, 0x00020000 },
24769 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24770 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24771 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24772 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
24773 - { 0x0000989c, 0x005f0000, 0x005f0000 },
24774 - { 0x0000989c, 0x00870000, 0x00870000 },
24775 - { 0x0000989c, 0x00f90000, 0x00f90000 },
24776 - { 0x0000989c, 0x007b0000, 0x007b0000 },
24777 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24778 - { 0x0000989c, 0x00f50000, 0x00f50000 },
24779 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
24780 - { 0x0000989c, 0x00110000, 0x00110000 },
24781 - { 0x0000989c, 0x006100a8, 0x006100a8 },
24782 - { 0x0000989c, 0x004210a2, 0x004210a2 },
24783 - { 0x0000989c, 0x0014008f, 0x0014008f },
24784 - { 0x0000989c, 0x00c40003, 0x00c40003 },
24785 - { 0x0000989c, 0x003000f2, 0x003000f2 },
24786 - { 0x0000989c, 0x00440016, 0x00440016 },
24787 - { 0x0000989c, 0x00410040, 0x00410040 },
24788 - { 0x0000989c, 0x0001805e, 0x0001805e },
24789 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
24790 - { 0x0000989c, 0x000000f1, 0x000000f1 },
24791 - { 0x0000989c, 0x00002081, 0x00002081 },
24792 - { 0x0000989c, 0x000000d4, 0x000000d4 },
24793 - { 0x000098d0, 0x0000000f, 0x0010000f },
24794 -};
24795 -
24796 -static const u32 ar5416Bank6TPC[][3] = {
24797 - { 0x0000989c, 0x00000000, 0x00000000 },
24798 - { 0x0000989c, 0x00000000, 0x00000000 },
24799 - { 0x0000989c, 0x00000000, 0x00000000 },
24800 - { 0x0000989c, 0x00e00000, 0x00e00000 },
24801 - { 0x0000989c, 0x005e0000, 0x005e0000 },
24802 - { 0x0000989c, 0x00120000, 0x00120000 },
24803 - { 0x0000989c, 0x00620000, 0x00620000 },
24804 - { 0x0000989c, 0x00020000, 0x00020000 },
24805 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24806 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24807 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24808 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
24809 - { 0x0000989c, 0x005f0000, 0x005f0000 },
24810 - { 0x0000989c, 0x00870000, 0x00870000 },
24811 - { 0x0000989c, 0x00f90000, 0x00f90000 },
24812 - { 0x0000989c, 0x007b0000, 0x007b0000 },
24813 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24814 - { 0x0000989c, 0x00f50000, 0x00f50000 },
24815 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
24816 - { 0x0000989c, 0x00110000, 0x00110000 },
24817 - { 0x0000989c, 0x006100a8, 0x006100a8 },
24818 - { 0x0000989c, 0x00423022, 0x00423022 },
24819 - { 0x0000989c, 0x201400df, 0x201400df },
24820 - { 0x0000989c, 0x00c40002, 0x00c40002 },
24821 - { 0x0000989c, 0x003000f2, 0x003000f2 },
24822 - { 0x0000989c, 0x00440016, 0x00440016 },
24823 - { 0x0000989c, 0x00410040, 0x00410040 },
24824 - { 0x0000989c, 0x0001805e, 0x0001805e },
24825 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
24826 - { 0x0000989c, 0x000000e1, 0x000000e1 },
24827 - { 0x0000989c, 0x00007081, 0x00007081 },
24828 - { 0x0000989c, 0x000000d4, 0x000000d4 },
24829 - { 0x000098d0, 0x0000000f, 0x0010000f },
24830 -};
24831 -
24832 -static const u32 ar5416Bank7[][2] = {
24833 - { 0x0000989c, 0x00000500 },
24834 - { 0x0000989c, 0x00000800 },
24835 - { 0x000098cc, 0x0000000e },
24836 -};
24837 -
24838 -static const u32 ar5416Addac[][2] = {
24839 - {0x0000989c, 0x00000000 },
24840 - {0x0000989c, 0x00000003 },
24841 - {0x0000989c, 0x00000000 },
24842 - {0x0000989c, 0x0000000c },
24843 - {0x0000989c, 0x00000000 },
24844 - {0x0000989c, 0x00000030 },
24845 - {0x0000989c, 0x00000000 },
24846 - {0x0000989c, 0x00000000 },
24847 - {0x0000989c, 0x00000000 },
24848 - {0x0000989c, 0x00000000 },
24849 - {0x0000989c, 0x00000000 },
24850 - {0x0000989c, 0x00000000 },
24851 - {0x0000989c, 0x00000000 },
24852 - {0x0000989c, 0x00000000 },
24853 - {0x0000989c, 0x00000000 },
24854 - {0x0000989c, 0x00000000 },
24855 - {0x0000989c, 0x00000000 },
24856 - {0x0000989c, 0x00000000 },
24857 - {0x0000989c, 0x00000060 },
24858 - {0x0000989c, 0x00000000 },
24859 - {0x0000989c, 0x00000000 },
24860 - {0x0000989c, 0x00000000 },
24861 - {0x0000989c, 0x00000000 },
24862 - {0x0000989c, 0x00000000 },
24863 - {0x0000989c, 0x00000000 },
24864 - {0x0000989c, 0x00000000 },
24865 - {0x0000989c, 0x00000000 },
24866 - {0x0000989c, 0x00000000 },
24867 - {0x0000989c, 0x00000000 },
24868 - {0x0000989c, 0x00000000 },
24869 - {0x0000989c, 0x00000000 },
24870 - {0x0000989c, 0x00000058 },
24871 - {0x0000989c, 0x00000000 },
24872 - {0x0000989c, 0x00000000 },
24873 - {0x0000989c, 0x00000000 },
24874 - {0x0000989c, 0x00000000 },
24875 - {0x000098cc, 0x00000000 },
24876 -};
24877 -
24878 -static const u32 ar5416Modes_9100[][6] = {
24879 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
24880 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
24881 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
24882 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
24883 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
24884 - { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
24885 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
24886 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
24887 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
24888 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
24889 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
24890 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
24891 - { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
24892 - { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
24893 - { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
24894 - { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
24895 - { 0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2, 0x6d48b0e2 },
24896 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec86d2e, 0x7ec84d2e, 0x7ec82d2e },
24897 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
24898 - { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
24899 - { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
24900 - { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
24901 - { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
24902 - { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
24903 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
24904 - { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a11, 0xd00a8a0d, 0xd00a8a0d },
24905 - { 0x00009940, 0x00754604, 0x00754604, 0xfff81204, 0xfff81204, 0xfff81204 },
24906 - { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },
24907 - { 0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e, 0xe250a51e },
24908 - { 0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff, 0x3388ffff },
24909 -#ifdef TB243
24910 - { 0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
24911 - { 0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
24912 - { 0x0000b960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
24913 - { 0x00009964, 0x00000000, 0x00000000, 0x00002210, 0x00002210, 0x00001120 },
24914 -#else
24915 - { 0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
24916 - { 0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
24917 - { 0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
24918 - { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
24919 -#endif
24920 - { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00, 0x001a0c00 },
24921 - { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
24922 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
24923 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
24924 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
24925 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
24926 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24927 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24928 - { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
24929 - { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
24930 - { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
24931 - { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
24932 - { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
24933 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
24934 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
24935 - { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
24936 - { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
24937 - { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
24938 - { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
24939 - { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
24940 - { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
24941 - { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
24942 - { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
24943 - { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
24944 - { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
24945 - { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
24946 - { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
24947 - { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24948 - { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24949 - { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24950 -};
24951 -
24952 -static const u32 ar5416Common_9100[][2] = {
24953 - { 0x0000000c, 0x00000000 },
24954 - { 0x00000030, 0x00020015 },
24955 - { 0x00000034, 0x00000005 },
24956 - { 0x00000040, 0x00000000 },
24957 - { 0x00000044, 0x00000008 },
24958 - { 0x00000048, 0x00000008 },
24959 - { 0x0000004c, 0x00000010 },
24960 - { 0x00000050, 0x00000000 },
24961 - { 0x00000054, 0x0000001f },
24962 - { 0x00000800, 0x00000000 },
24963 - { 0x00000804, 0x00000000 },
24964 - { 0x00000808, 0x00000000 },
24965 - { 0x0000080c, 0x00000000 },
24966 - { 0x00000810, 0x00000000 },
24967 - { 0x00000814, 0x00000000 },
24968 - { 0x00000818, 0x00000000 },
24969 - { 0x0000081c, 0x00000000 },
24970 - { 0x00000820, 0x00000000 },
24971 - { 0x00000824, 0x00000000 },
24972 - { 0x00001040, 0x002ffc0f },
24973 - { 0x00001044, 0x002ffc0f },
24974 - { 0x00001048, 0x002ffc0f },
24975 - { 0x0000104c, 0x002ffc0f },
24976 - { 0x00001050, 0x002ffc0f },
24977 - { 0x00001054, 0x002ffc0f },
24978 - { 0x00001058, 0x002ffc0f },
24979 - { 0x0000105c, 0x002ffc0f },
24980 - { 0x00001060, 0x002ffc0f },
24981 - { 0x00001064, 0x002ffc0f },
24982 - { 0x00001230, 0x00000000 },
24983 - { 0x00001270, 0x00000000 },
24984 - { 0x00001038, 0x00000000 },
24985 - { 0x00001078, 0x00000000 },
24986 - { 0x000010b8, 0x00000000 },
24987 - { 0x000010f8, 0x00000000 },
24988 - { 0x00001138, 0x00000000 },
24989 - { 0x00001178, 0x00000000 },
24990 - { 0x000011b8, 0x00000000 },
24991 - { 0x000011f8, 0x00000000 },
24992 - { 0x00001238, 0x00000000 },
24993 - { 0x00001278, 0x00000000 },
24994 - { 0x000012b8, 0x00000000 },
24995 - { 0x000012f8, 0x00000000 },
24996 - { 0x00001338, 0x00000000 },
24997 - { 0x00001378, 0x00000000 },
24998 - { 0x000013b8, 0x00000000 },
24999 - { 0x000013f8, 0x00000000 },
25000 - { 0x00001438, 0x00000000 },
25001 - { 0x00001478, 0x00000000 },
25002 - { 0x000014b8, 0x00000000 },
25003 - { 0x000014f8, 0x00000000 },
25004 - { 0x00001538, 0x00000000 },
25005 - { 0x00001578, 0x00000000 },
25006 - { 0x000015b8, 0x00000000 },
25007 - { 0x000015f8, 0x00000000 },
25008 - { 0x00001638, 0x00000000 },
25009 - { 0x00001678, 0x00000000 },
25010 - { 0x000016b8, 0x00000000 },
25011 - { 0x000016f8, 0x00000000 },
25012 - { 0x00001738, 0x00000000 },
25013 - { 0x00001778, 0x00000000 },
25014 - { 0x000017b8, 0x00000000 },
25015 - { 0x000017f8, 0x00000000 },
25016 - { 0x0000103c, 0x00000000 },
25017 - { 0x0000107c, 0x00000000 },
25018 - { 0x000010bc, 0x00000000 },
25019 - { 0x000010fc, 0x00000000 },
25020 - { 0x0000113c, 0x00000000 },
25021 - { 0x0000117c, 0x00000000 },
25022 - { 0x000011bc, 0x00000000 },
25023 - { 0x000011fc, 0x00000000 },
25024 - { 0x0000123c, 0x00000000 },
25025 - { 0x0000127c, 0x00000000 },
25026 - { 0x000012bc, 0x00000000 },
25027 - { 0x000012fc, 0x00000000 },
25028 - { 0x0000133c, 0x00000000 },
25029 - { 0x0000137c, 0x00000000 },
25030 - { 0x000013bc, 0x00000000 },
25031 - { 0x000013fc, 0x00000000 },
25032 - { 0x0000143c, 0x00000000 },
25033 - { 0x0000147c, 0x00000000 },
25034 - { 0x00020010, 0x00000003 },
25035 - { 0x00020038, 0x000004c2 },
25036 - { 0x00008004, 0x00000000 },
25037 - { 0x00008008, 0x00000000 },
25038 - { 0x0000800c, 0x00000000 },
25039 - { 0x00008018, 0x00000700 },
25040 - { 0x00008020, 0x00000000 },
25041 - { 0x00008038, 0x00000000 },
25042 - { 0x0000803c, 0x00000000 },
25043 - { 0x00008048, 0x40000000 },
25044 - { 0x00008054, 0x00004000 },
25045 - { 0x00008058, 0x00000000 },
25046 - { 0x0000805c, 0x000fc78f },
25047 - { 0x00008060, 0x0000000f },
25048 - { 0x00008064, 0x00000000 },
25049 - { 0x000080c0, 0x2a82301a },
25050 - { 0x000080c4, 0x05dc01e0 },
25051 - { 0x000080c8, 0x1f402710 },
25052 - { 0x000080cc, 0x01f40000 },
25053 - { 0x000080d0, 0x00001e00 },
25054 - { 0x000080d4, 0x00000000 },
25055 - { 0x000080d8, 0x00400000 },
25056 - { 0x000080e0, 0xffffffff },
25057 - { 0x000080e4, 0x0000ffff },
25058 - { 0x000080e8, 0x003f3f3f },
25059 - { 0x000080ec, 0x00000000 },
25060 - { 0x000080f0, 0x00000000 },
25061 - { 0x000080f4, 0x00000000 },
25062 - { 0x000080f8, 0x00000000 },
25063 - { 0x000080fc, 0x00020000 },
25064 - { 0x00008100, 0x00020000 },
25065 - { 0x00008104, 0x00000001 },
25066 - { 0x00008108, 0x00000052 },
25067 - { 0x0000810c, 0x00000000 },
25068 - { 0x00008110, 0x00000168 },
25069 - { 0x00008118, 0x000100aa },
25070 - { 0x0000811c, 0x00003210 },
25071 - { 0x00008120, 0x08f04800 },
25072 - { 0x00008124, 0x00000000 },
25073 - { 0x00008128, 0x00000000 },
25074 - { 0x0000812c, 0x00000000 },
25075 - { 0x00008130, 0x00000000 },
25076 - { 0x00008134, 0x00000000 },
25077 - { 0x00008138, 0x00000000 },
25078 - { 0x0000813c, 0x00000000 },
25079 - { 0x00008144, 0x00000000 },
25080 - { 0x00008168, 0x00000000 },
25081 - { 0x0000816c, 0x00000000 },
25082 - { 0x00008170, 0x32143320 },
25083 - { 0x00008174, 0xfaa4fa50 },
25084 - { 0x00008178, 0x00000100 },
25085 - { 0x0000817c, 0x00000000 },
25086 - { 0x000081c4, 0x00000000 },
25087 - { 0x000081d0, 0x00003210 },
25088 - { 0x000081ec, 0x00000000 },
25089 - { 0x000081f0, 0x00000000 },
25090 - { 0x000081f4, 0x00000000 },
25091 - { 0x000081f8, 0x00000000 },
25092 - { 0x000081fc, 0x00000000 },
25093 - { 0x00008200, 0x00000000 },
25094 - { 0x00008204, 0x00000000 },
25095 - { 0x00008208, 0x00000000 },
25096 - { 0x0000820c, 0x00000000 },
25097 - { 0x00008210, 0x00000000 },
25098 - { 0x00008214, 0x00000000 },
25099 - { 0x00008218, 0x00000000 },
25100 - { 0x0000821c, 0x00000000 },
25101 - { 0x00008220, 0x00000000 },
25102 - { 0x00008224, 0x00000000 },
25103 - { 0x00008228, 0x00000000 },
25104 - { 0x0000822c, 0x00000000 },
25105 - { 0x00008230, 0x00000000 },
25106 - { 0x00008234, 0x00000000 },
25107 - { 0x00008238, 0x00000000 },
25108 - { 0x0000823c, 0x00000000 },
25109 - { 0x00008240, 0x00100000 },
25110 - { 0x00008244, 0x0010f400 },
25111 - { 0x00008248, 0x00000100 },
25112 - { 0x0000824c, 0x0001e800 },
25113 - { 0x00008250, 0x00000000 },
25114 - { 0x00008254, 0x00000000 },
25115 - { 0x00008258, 0x00000000 },
25116 - { 0x0000825c, 0x400000ff },
25117 - { 0x00008260, 0x00080922 },
25118 - { 0x00008270, 0x00000000 },
25119 - { 0x00008274, 0x40000000 },
25120 - { 0x00008278, 0x003e4180 },
25121 - { 0x0000827c, 0x00000000 },
25122 - { 0x00008284, 0x0000002c },
25123 - { 0x00008288, 0x0000002c },
25124 - { 0x0000828c, 0x00000000 },
25125 - { 0x00008294, 0x00000000 },
25126 - { 0x00008298, 0x00000000 },
25127 - { 0x00008300, 0x00000000 },
25128 - { 0x00008304, 0x00000000 },
25129 - { 0x00008308, 0x00000000 },
25130 - { 0x0000830c, 0x00000000 },
25131 - { 0x00008310, 0x00000000 },
25132 - { 0x00008314, 0x00000000 },
25133 - { 0x00008318, 0x00000000 },
25134 - { 0x00008328, 0x00000000 },
25135 - { 0x0000832c, 0x00000007 },
25136 - { 0x00008330, 0x00000302 },
25137 - { 0x00008334, 0x00000e00 },
25138 - { 0x00008338, 0x00000000 },
25139 - { 0x0000833c, 0x00000000 },
25140 - { 0x00008340, 0x000107ff },
25141 - { 0x00009808, 0x00000000 },
25142 - { 0x0000980c, 0xad848e19 },
25143 - { 0x00009810, 0x7d14e000 },
25144 - { 0x00009814, 0x9c0a9f6b },
25145 - { 0x0000981c, 0x00000000 },
25146 - { 0x0000982c, 0x0000a000 },
25147 - { 0x00009830, 0x00000000 },
25148 - { 0x0000983c, 0x00200400 },
25149 - { 0x00009840, 0x206a01ae },
25150 - { 0x0000984c, 0x1284233c },
25151 - { 0x00009854, 0x00000859 },
25152 - { 0x00009900, 0x00000000 },
25153 - { 0x00009904, 0x00000000 },
25154 - { 0x00009908, 0x00000000 },
25155 - { 0x0000990c, 0x00000000 },
25156 - { 0x0000991c, 0x10000fff },
25157 - { 0x00009920, 0x05100000 },
25158 - { 0x0000a920, 0x05100000 },
25159 - { 0x0000b920, 0x05100000 },
25160 - { 0x00009928, 0x00000001 },
25161 - { 0x0000992c, 0x00000004 },
25162 - { 0x00009934, 0x1e1f2022 },
25163 - { 0x00009938, 0x0a0b0c0d },
25164 - { 0x0000993c, 0x00000000 },
25165 - { 0x00009948, 0x9280b212 },
25166 - { 0x0000994c, 0x00020028 },
25167 - { 0x0000c95c, 0x004b6a8e },
25168 - { 0x0000c968, 0x000003ce },
25169 - { 0x00009970, 0x190fb515 },
25170 - { 0x00009974, 0x00000000 },
25171 - { 0x00009978, 0x00000001 },
25172 - { 0x0000997c, 0x00000000 },
25173 - { 0x00009980, 0x00000000 },
25174 - { 0x00009984, 0x00000000 },
25175 - { 0x00009988, 0x00000000 },
25176 - { 0x0000998c, 0x00000000 },
25177 - { 0x00009990, 0x00000000 },
25178 - { 0x00009994, 0x00000000 },
25179 - { 0x00009998, 0x00000000 },
25180 - { 0x0000999c, 0x00000000 },
25181 - { 0x000099a0, 0x00000000 },
25182 - { 0x000099a4, 0x00000001 },
25183 - { 0x000099a8, 0x201fff00 },
25184 - { 0x000099ac, 0x006f0000 },
25185 - { 0x000099b0, 0x03051000 },
25186 - { 0x000099dc, 0x00000000 },
25187 - { 0x000099e0, 0x00000200 },
25188 - { 0x000099e4, 0xaaaaaaaa },
25189 - { 0x000099e8, 0x3c466478 },
25190 - { 0x000099ec, 0x0cc80caa },
25191 - { 0x000099fc, 0x00001042 },
25192 - { 0x00009b00, 0x00000000 },
25193 - { 0x00009b04, 0x00000001 },
25194 - { 0x00009b08, 0x00000002 },
25195 - { 0x00009b0c, 0x00000003 },
25196 - { 0x00009b10, 0x00000004 },
25197 - { 0x00009b14, 0x00000005 },
25198 - { 0x00009b18, 0x00000008 },
25199 - { 0x00009b1c, 0x00000009 },
25200 - { 0x00009b20, 0x0000000a },
25201 - { 0x00009b24, 0x0000000b },
25202 - { 0x00009b28, 0x0000000c },
25203 - { 0x00009b2c, 0x0000000d },
25204 - { 0x00009b30, 0x00000010 },
25205 - { 0x00009b34, 0x00000011 },
25206 - { 0x00009b38, 0x00000012 },
25207 - { 0x00009b3c, 0x00000013 },
25208 - { 0x00009b40, 0x00000014 },
25209 - { 0x00009b44, 0x00000015 },
25210 - { 0x00009b48, 0x00000018 },
25211 - { 0x00009b4c, 0x00000019 },
25212 - { 0x00009b50, 0x0000001a },
25213 - { 0x00009b54, 0x0000001b },
25214 - { 0x00009b58, 0x0000001c },
25215 - { 0x00009b5c, 0x0000001d },
25216 - { 0x00009b60, 0x00000020 },
25217 - { 0x00009b64, 0x00000021 },
25218 - { 0x00009b68, 0x00000022 },
25219 - { 0x00009b6c, 0x00000023 },
25220 - { 0x00009b70, 0x00000024 },
25221 - { 0x00009b74, 0x00000025 },
25222 - { 0x00009b78, 0x00000028 },
25223 - { 0x00009b7c, 0x00000029 },
25224 - { 0x00009b80, 0x0000002a },
25225 - { 0x00009b84, 0x0000002b },
25226 - { 0x00009b88, 0x0000002c },
25227 - { 0x00009b8c, 0x0000002d },
25228 - { 0x00009b90, 0x00000030 },
25229 - { 0x00009b94, 0x00000031 },
25230 - { 0x00009b98, 0x00000032 },
25231 - { 0x00009b9c, 0x00000033 },
25232 - { 0x00009ba0, 0x00000034 },
25233 - { 0x00009ba4, 0x00000035 },
25234 - { 0x00009ba8, 0x00000035 },
25235 - { 0x00009bac, 0x00000035 },
25236 - { 0x00009bb0, 0x00000035 },
25237 - { 0x00009bb4, 0x00000035 },
25238 - { 0x00009bb8, 0x00000035 },
25239 - { 0x00009bbc, 0x00000035 },
25240 - { 0x00009bc0, 0x00000035 },
25241 - { 0x00009bc4, 0x00000035 },
25242 - { 0x00009bc8, 0x00000035 },
25243 - { 0x00009bcc, 0x00000035 },
25244 - { 0x00009bd0, 0x00000035 },
25245 - { 0x00009bd4, 0x00000035 },
25246 - { 0x00009bd8, 0x00000035 },
25247 - { 0x00009bdc, 0x00000035 },
25248 - { 0x00009be0, 0x00000035 },
25249 - { 0x00009be4, 0x00000035 },
25250 - { 0x00009be8, 0x00000035 },
25251 - { 0x00009bec, 0x00000035 },
25252 - { 0x00009bf0, 0x00000035 },
25253 - { 0x00009bf4, 0x00000035 },
25254 - { 0x00009bf8, 0x00000010 },
25255 - { 0x00009bfc, 0x0000001a },
25256 - { 0x0000a210, 0x40806333 },
25257 - { 0x0000a214, 0x00106c10 },
25258 - { 0x0000a218, 0x009c4060 },
25259 - { 0x0000a220, 0x018830c6 },
25260 - { 0x0000a224, 0x00000400 },
25261 - { 0x0000a228, 0x001a0bb5 },
25262 - { 0x0000a22c, 0x00000000 },
25263 - { 0x0000a234, 0x20202020 },
25264 - { 0x0000a238, 0x20202020 },
25265 - { 0x0000a23c, 0x13c889ae },
25266 - { 0x0000a240, 0x38490a20 },
25267 - { 0x0000a244, 0x00007bb6 },
25268 - { 0x0000a248, 0x0fff3ffc },
25269 - { 0x0000a24c, 0x00000001 },
25270 - { 0x0000a250, 0x0000a000 },
25271 - { 0x0000a254, 0x00000000 },
25272 - { 0x0000a258, 0x0cc75380 },
25273 - { 0x0000a25c, 0x0f0f0f01 },
25274 - { 0x0000a260, 0xdfa91f01 },
25275 - { 0x0000a268, 0x00000001 },
25276 - { 0x0000a26c, 0x0ebae9c6 },
25277 - { 0x0000b26c, 0x0ebae9c6 },
25278 - { 0x0000c26c, 0x0ebae9c6 },
25279 - { 0x0000d270, 0x00820820 },
25280 - { 0x0000a278, 0x1ce739ce },
25281 - { 0x0000a27c, 0x050701ce },
25282 - { 0x0000a338, 0x00000000 },
25283 - { 0x0000a33c, 0x00000000 },
25284 - { 0x0000a340, 0x00000000 },
25285 - { 0x0000a344, 0x00000000 },
25286 - { 0x0000a348, 0x3fffffff },
25287 - { 0x0000a34c, 0x3fffffff },
25288 - { 0x0000a350, 0x3fffffff },
25289 - { 0x0000a354, 0x0003ffff },
25290 - { 0x0000a358, 0x79a8aa33 },
25291 - { 0x0000d35c, 0x07ffffef },
25292 - { 0x0000d360, 0x0fffffe7 },
25293 - { 0x0000d364, 0x17ffffe5 },
25294 - { 0x0000d368, 0x1fffffe4 },
25295 - { 0x0000d36c, 0x37ffffe3 },
25296 - { 0x0000d370, 0x3fffffe3 },
25297 - { 0x0000d374, 0x57ffffe3 },
25298 - { 0x0000d378, 0x5fffffe2 },
25299 - { 0x0000d37c, 0x7fffffe2 },
25300 - { 0x0000d380, 0x7f3c7bba },
25301 - { 0x0000d384, 0xf3307ff0 },
25302 - { 0x0000a388, 0x0c000000 },
25303 - { 0x0000a38c, 0x20202020 },
25304 - { 0x0000a390, 0x20202020 },
25305 - { 0x0000a394, 0x1ce739ce },
25306 - { 0x0000a398, 0x000001ce },
25307 - { 0x0000a39c, 0x00000001 },
25308 - { 0x0000a3a0, 0x00000000 },
25309 - { 0x0000a3a4, 0x00000000 },
25310 - { 0x0000a3a8, 0x00000000 },
25311 - { 0x0000a3ac, 0x00000000 },
25312 - { 0x0000a3b0, 0x00000000 },
25313 - { 0x0000a3b4, 0x00000000 },
25314 - { 0x0000a3b8, 0x00000000 },
25315 - { 0x0000a3bc, 0x00000000 },
25316 - { 0x0000a3c0, 0x00000000 },
25317 - { 0x0000a3c4, 0x00000000 },
25318 - { 0x0000a3c8, 0x00000246 },
25319 - { 0x0000a3cc, 0x20202020 },
25320 - { 0x0000a3d0, 0x20202020 },
25321 - { 0x0000a3d4, 0x20202020 },
25322 - { 0x0000a3dc, 0x1ce739ce },
25323 - { 0x0000a3e0, 0x000001ce },
25324 -};
25325 -
25326 -static const u32 ar5416Bank0_9100[][2] = {
25327 - { 0x000098b0, 0x1e5795e5 },
25328 - { 0x000098e0, 0x02008020 },
25329 -};
25330 -
25331 -static const u32 ar5416BB_RfGain_9100[][3] = {
25332 - { 0x00009a00, 0x00000000, 0x00000000 },
25333 - { 0x00009a04, 0x00000040, 0x00000040 },
25334 - { 0x00009a08, 0x00000080, 0x00000080 },
25335 - { 0x00009a0c, 0x000001a1, 0x00000141 },
25336 - { 0x00009a10, 0x000001e1, 0x00000181 },
25337 - { 0x00009a14, 0x00000021, 0x000001c1 },
25338 - { 0x00009a18, 0x00000061, 0x00000001 },
25339 - { 0x00009a1c, 0x00000168, 0x00000041 },
25340 - { 0x00009a20, 0x000001a8, 0x000001a8 },
25341 - { 0x00009a24, 0x000001e8, 0x000001e8 },
25342 - { 0x00009a28, 0x00000028, 0x00000028 },
25343 - { 0x00009a2c, 0x00000068, 0x00000068 },
25344 - { 0x00009a30, 0x00000189, 0x000000a8 },
25345 - { 0x00009a34, 0x000001c9, 0x00000169 },
25346 - { 0x00009a38, 0x00000009, 0x000001a9 },
25347 - { 0x00009a3c, 0x00000049, 0x000001e9 },
25348 - { 0x00009a40, 0x00000089, 0x00000029 },
25349 - { 0x00009a44, 0x00000170, 0x00000069 },
25350 - { 0x00009a48, 0x000001b0, 0x00000190 },
25351 - { 0x00009a4c, 0x000001f0, 0x000001d0 },
25352 - { 0x00009a50, 0x00000030, 0x00000010 },
25353 - { 0x00009a54, 0x00000070, 0x00000050 },
25354 - { 0x00009a58, 0x00000191, 0x00000090 },
25355 - { 0x00009a5c, 0x000001d1, 0x00000151 },
25356 - { 0x00009a60, 0x00000011, 0x00000191 },
25357 - { 0x00009a64, 0x00000051, 0x000001d1 },
25358 - { 0x00009a68, 0x00000091, 0x00000011 },
25359 - { 0x00009a6c, 0x000001b8, 0x00000051 },
25360 - { 0x00009a70, 0x000001f8, 0x00000198 },
25361 - { 0x00009a74, 0x00000038, 0x000001d8 },
25362 - { 0x00009a78, 0x00000078, 0x00000018 },
25363 - { 0x00009a7c, 0x00000199, 0x00000058 },
25364 - { 0x00009a80, 0x000001d9, 0x00000098 },
25365 - { 0x00009a84, 0x00000019, 0x00000159 },
25366 - { 0x00009a88, 0x00000059, 0x00000199 },
25367 - { 0x00009a8c, 0x00000099, 0x000001d9 },
25368 - { 0x00009a90, 0x000000d9, 0x00000019 },
25369 - { 0x00009a94, 0x000000f9, 0x00000059 },
25370 - { 0x00009a98, 0x000000f9, 0x00000099 },
25371 - { 0x00009a9c, 0x000000f9, 0x000000d9 },
25372 - { 0x00009aa0, 0x000000f9, 0x000000f9 },
25373 - { 0x00009aa4, 0x000000f9, 0x000000f9 },
25374 - { 0x00009aa8, 0x000000f9, 0x000000f9 },
25375 - { 0x00009aac, 0x000000f9, 0x000000f9 },
25376 - { 0x00009ab0, 0x000000f9, 0x000000f9 },
25377 - { 0x00009ab4, 0x000000f9, 0x000000f9 },
25378 - { 0x00009ab8, 0x000000f9, 0x000000f9 },
25379 - { 0x00009abc, 0x000000f9, 0x000000f9 },
25380 - { 0x00009ac0, 0x000000f9, 0x000000f9 },
25381 - { 0x00009ac4, 0x000000f9, 0x000000f9 },
25382 - { 0x00009ac8, 0x000000f9, 0x000000f9 },
25383 - { 0x00009acc, 0x000000f9, 0x000000f9 },
25384 - { 0x00009ad0, 0x000000f9, 0x000000f9 },
25385 - { 0x00009ad4, 0x000000f9, 0x000000f9 },
25386 - { 0x00009ad8, 0x000000f9, 0x000000f9 },
25387 - { 0x00009adc, 0x000000f9, 0x000000f9 },
25388 - { 0x00009ae0, 0x000000f9, 0x000000f9 },
25389 - { 0x00009ae4, 0x000000f9, 0x000000f9 },
25390 - { 0x00009ae8, 0x000000f9, 0x000000f9 },
25391 - { 0x00009aec, 0x000000f9, 0x000000f9 },
25392 - { 0x00009af0, 0x000000f9, 0x000000f9 },
25393 - { 0x00009af4, 0x000000f9, 0x000000f9 },
25394 - { 0x00009af8, 0x000000f9, 0x000000f9 },
25395 - { 0x00009afc, 0x000000f9, 0x000000f9 },
25396 -};
25397 -
25398 -static const u32 ar5416Bank1_9100[][2] = {
25399 - { 0x000098b0, 0x02108421},
25400 - { 0x000098ec, 0x00000008},
25401 -};
25402 -
25403 -static const u32 ar5416Bank2_9100[][2] = {
25404 - { 0x000098b0, 0x0e73ff17},
25405 - { 0x000098e0, 0x00000420},
25406 -};
25407 -
25408 -static const u32 ar5416Bank3_9100[][3] = {
25409 - { 0x000098f0, 0x01400018, 0x01c00018 },
25410 -};
25411 -
25412 -static const u32 ar5416Bank6_9100[][3] = {
25413 -
25414 - { 0x0000989c, 0x00000000, 0x00000000 },
25415 - { 0x0000989c, 0x00000000, 0x00000000 },
25416 - { 0x0000989c, 0x00000000, 0x00000000 },
25417 - { 0x0000989c, 0x00e00000, 0x00e00000 },
25418 - { 0x0000989c, 0x005e0000, 0x005e0000 },
25419 - { 0x0000989c, 0x00120000, 0x00120000 },
25420 - { 0x0000989c, 0x00620000, 0x00620000 },
25421 - { 0x0000989c, 0x00020000, 0x00020000 },
25422 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25423 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25424 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25425 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25426 - { 0x0000989c, 0x005f0000, 0x005f0000 },
25427 - { 0x0000989c, 0x00870000, 0x00870000 },
25428 - { 0x0000989c, 0x00f90000, 0x00f90000 },
25429 - { 0x0000989c, 0x007b0000, 0x007b0000 },
25430 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25431 - { 0x0000989c, 0x00f50000, 0x00f50000 },
25432 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
25433 - { 0x0000989c, 0x00110000, 0x00110000 },
25434 - { 0x0000989c, 0x006100a8, 0x006100a8 },
25435 - { 0x0000989c, 0x004210a2, 0x004210a2 },
25436 - { 0x0000989c, 0x0014000f, 0x0014000f },
25437 - { 0x0000989c, 0x00c40002, 0x00c40002 },
25438 - { 0x0000989c, 0x003000f2, 0x003000f2 },
25439 - { 0x0000989c, 0x00440016, 0x00440016 },
25440 - { 0x0000989c, 0x00410040, 0x00410040 },
25441 - { 0x0000989c, 0x000180d6, 0x000180d6 },
25442 - { 0x0000989c, 0x0000c0aa, 0x0000c0aa },
25443 - { 0x0000989c, 0x000000b1, 0x000000b1 },
25444 - { 0x0000989c, 0x00002000, 0x00002000 },
25445 - { 0x0000989c, 0x000000d4, 0x000000d4 },
25446 - { 0x000098d0, 0x0000000f, 0x0010000f },
25447 -};
25448 -
25449 -
25450 -static const u32 ar5416Bank6TPC_9100[][3] = {
25451 -
25452 - { 0x0000989c, 0x00000000, 0x00000000 },
25453 - { 0x0000989c, 0x00000000, 0x00000000 },
25454 - { 0x0000989c, 0x00000000, 0x00000000 },
25455 - { 0x0000989c, 0x00e00000, 0x00e00000 },
25456 - { 0x0000989c, 0x005e0000, 0x005e0000 },
25457 - { 0x0000989c, 0x00120000, 0x00120000 },
25458 - { 0x0000989c, 0x00620000, 0x00620000 },
25459 - { 0x0000989c, 0x00020000, 0x00020000 },
25460 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25461 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25462 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25463 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
25464 - { 0x0000989c, 0x005f0000, 0x005f0000 },
25465 - { 0x0000989c, 0x00870000, 0x00870000 },
25466 - { 0x0000989c, 0x00f90000, 0x00f90000 },
25467 - { 0x0000989c, 0x007b0000, 0x007b0000 },
25468 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25469 - { 0x0000989c, 0x00f50000, 0x00f50000 },
25470 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
25471 - { 0x0000989c, 0x00110000, 0x00110000 },
25472 - { 0x0000989c, 0x006100a8, 0x006100a8 },
25473 - { 0x0000989c, 0x00423022, 0x00423022 },
25474 - { 0x0000989c, 0x2014008f, 0x2014008f },
25475 - { 0x0000989c, 0x00c40002, 0x00c40002 },
25476 - { 0x0000989c, 0x003000f2, 0x003000f2 },
25477 - { 0x0000989c, 0x00440016, 0x00440016 },
25478 - { 0x0000989c, 0x00410040, 0x00410040 },
25479 - { 0x0000989c, 0x0001805e, 0x0001805e },
25480 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
25481 - { 0x0000989c, 0x000000e1, 0x000000e1 },
25482 - { 0x0000989c, 0x00007080, 0x00007080 },
25483 - { 0x0000989c, 0x000000d4, 0x000000d4 },
25484 - { 0x000098d0, 0x0000000f, 0x0010000f },
25485 -};
25486 -
25487 -static const u32 ar5416Bank7_9100[][2] = {
25488 - { 0x0000989c, 0x00000500 },
25489 - { 0x0000989c, 0x00000800 },
25490 - { 0x000098cc, 0x0000000e },
25491 -};
25492 -
25493 -static const u32 ar5416Addac_9100[][2] = {
25494 - {0x0000989c, 0x00000000 },
25495 - {0x0000989c, 0x00000000 },
25496 - {0x0000989c, 0x00000000 },
25497 - {0x0000989c, 0x00000000 },
25498 - {0x0000989c, 0x00000000 },
25499 - {0x0000989c, 0x00000000 },
25500 - {0x0000989c, 0x00000000 },
25501 - {0x0000989c, 0x00000010 },
25502 - {0x0000989c, 0x00000000 },
25503 - {0x0000989c, 0x00000000 },
25504 - {0x0000989c, 0x00000000 },
25505 - {0x0000989c, 0x00000000 },
25506 - {0x0000989c, 0x00000000 },
25507 - {0x0000989c, 0x00000000 },
25508 - {0x0000989c, 0x00000000 },
25509 - {0x0000989c, 0x00000000 },
25510 - {0x0000989c, 0x00000000 },
25511 - {0x0000989c, 0x00000000 },
25512 - {0x0000989c, 0x00000000 },
25513 - {0x0000989c, 0x00000000 },
25514 - {0x0000989c, 0x00000000 },
25515 - {0x0000989c, 0x000000c0 },
25516 - {0x0000989c, 0x00000015 },
25517 - {0x0000989c, 0x00000000 },
25518 - {0x0000989c, 0x00000000 },
25519 - {0x0000989c, 0x00000000 },
25520 - {0x0000989c, 0x00000000 },
25521 - {0x0000989c, 0x00000000 },
25522 - {0x0000989c, 0x00000000 },
25523 - {0x0000989c, 0x00000000 },
25524 - {0x0000989c, 0x00000000 },
25525 - {0x000098cc, 0x00000000 },
25526 -};
25527 -
25528 -static const u32 ar5416Modes_9160[][6] = {
25529 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
25530 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
25531 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
25532 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
25533 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
25534 - { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
25535 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
25536 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
25537 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
25538 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
25539 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
25540 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
25541 - { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
25542 - { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
25543 - { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
25544 - { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
25545 - { 0x00009850, 0x6c48b4e2, 0x6c48b4e2, 0x6c48b0e2, 0x6c48b0e2, 0x6c48b0e2 },
25546 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
25547 - { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e },
25548 - { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
25549 - { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
25550 - { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
25551 - { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
25552 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
25553 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
25554 - { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
25555 - { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
25556 - { 0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
25557 - { 0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
25558 - { 0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
25559 - { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
25560 - { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
25561 - { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00, 0x001a0c00 },
25562 - { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
25563 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
25564 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
25565 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
25566 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
25567 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25568 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25569 - { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
25570 - { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
25571 - { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
25572 - { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
25573 - { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
25574 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
25575 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
25576 - { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
25577 - { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
25578 - { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
25579 - { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
25580 - { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
25581 - { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
25582 - { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
25583 - { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
25584 - { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
25585 - { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
25586 - { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
25587 - { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
25588 - { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25589 - { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25590 - { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25591 -};
25592 -
25593 -static const u32 ar5416Common_9160[][2] = {
25594 - { 0x0000000c, 0x00000000 },
25595 - { 0x00000030, 0x00020015 },
25596 - { 0x00000034, 0x00000005 },
25597 - { 0x00000040, 0x00000000 },
25598 - { 0x00000044, 0x00000008 },
25599 - { 0x00000048, 0x00000008 },
25600 - { 0x0000004c, 0x00000010 },
25601 - { 0x00000050, 0x00000000 },
25602 - { 0x00000054, 0x0000001f },
25603 - { 0x00000800, 0x00000000 },
25604 - { 0x00000804, 0x00000000 },
25605 - { 0x00000808, 0x00000000 },
25606 - { 0x0000080c, 0x00000000 },
25607 - { 0x00000810, 0x00000000 },
25608 - { 0x00000814, 0x00000000 },
25609 - { 0x00000818, 0x00000000 },
25610 - { 0x0000081c, 0x00000000 },
25611 - { 0x00000820, 0x00000000 },
25612 - { 0x00000824, 0x00000000 },
25613 - { 0x00001040, 0x002ffc0f },
25614 - { 0x00001044, 0x002ffc0f },
25615 - { 0x00001048, 0x002ffc0f },
25616 - { 0x0000104c, 0x002ffc0f },
25617 - { 0x00001050, 0x002ffc0f },
25618 - { 0x00001054, 0x002ffc0f },
25619 - { 0x00001058, 0x002ffc0f },
25620 - { 0x0000105c, 0x002ffc0f },
25621 - { 0x00001060, 0x002ffc0f },
25622 - { 0x00001064, 0x002ffc0f },
25623 - { 0x00001230, 0x00000000 },
25624 - { 0x00001270, 0x00000000 },
25625 - { 0x00001038, 0x00000000 },
25626 - { 0x00001078, 0x00000000 },
25627 - { 0x000010b8, 0x00000000 },
25628 - { 0x000010f8, 0x00000000 },
25629 - { 0x00001138, 0x00000000 },
25630 - { 0x00001178, 0x00000000 },
25631 - { 0x000011b8, 0x00000000 },
25632 - { 0x000011f8, 0x00000000 },
25633 - { 0x00001238, 0x00000000 },
25634 - { 0x00001278, 0x00000000 },
25635 - { 0x000012b8, 0x00000000 },
25636 - { 0x000012f8, 0x00000000 },
25637 - { 0x00001338, 0x00000000 },
25638 - { 0x00001378, 0x00000000 },
25639 - { 0x000013b8, 0x00000000 },
25640 - { 0x000013f8, 0x00000000 },
25641 - { 0x00001438, 0x00000000 },
25642 - { 0x00001478, 0x00000000 },
25643 - { 0x000014b8, 0x00000000 },
25644 - { 0x000014f8, 0x00000000 },
25645 - { 0x00001538, 0x00000000 },
25646 - { 0x00001578, 0x00000000 },
25647 - { 0x000015b8, 0x00000000 },
25648 - { 0x000015f8, 0x00000000 },
25649 - { 0x00001638, 0x00000000 },
25650 - { 0x00001678, 0x00000000 },
25651 - { 0x000016b8, 0x00000000 },
25652 - { 0x000016f8, 0x00000000 },
25653 - { 0x00001738, 0x00000000 },
25654 - { 0x00001778, 0x00000000 },
25655 - { 0x000017b8, 0x00000000 },
25656 - { 0x000017f8, 0x00000000 },
25657 - { 0x0000103c, 0x00000000 },
25658 - { 0x0000107c, 0x00000000 },
25659 - { 0x000010bc, 0x00000000 },
25660 - { 0x000010fc, 0x00000000 },
25661 - { 0x0000113c, 0x00000000 },
25662 - { 0x0000117c, 0x00000000 },
25663 - { 0x000011bc, 0x00000000 },
25664 - { 0x000011fc, 0x00000000 },
25665 - { 0x0000123c, 0x00000000 },
25666 - { 0x0000127c, 0x00000000 },
25667 - { 0x000012bc, 0x00000000 },
25668 - { 0x000012fc, 0x00000000 },
25669 - { 0x0000133c, 0x00000000 },
25670 - { 0x0000137c, 0x00000000 },
25671 - { 0x000013bc, 0x00000000 },
25672 - { 0x000013fc, 0x00000000 },
25673 - { 0x0000143c, 0x00000000 },
25674 - { 0x0000147c, 0x00000000 },
25675 - { 0x00004030, 0x00000002 },
25676 - { 0x0000403c, 0x00000002 },
25677 - { 0x00007010, 0x00000020 },
25678 - { 0x00007038, 0x000004c2 },
25679 - { 0x00008004, 0x00000000 },
25680 - { 0x00008008, 0x00000000 },
25681 - { 0x0000800c, 0x00000000 },
25682 - { 0x00008018, 0x00000700 },
25683 - { 0x00008020, 0x00000000 },
25684 - { 0x00008038, 0x00000000 },
25685 - { 0x0000803c, 0x00000000 },
25686 - { 0x00008048, 0x40000000 },
25687 - { 0x00008054, 0x00000000 },
25688 - { 0x00008058, 0x00000000 },
25689 - { 0x0000805c, 0x000fc78f },
25690 - { 0x00008060, 0x0000000f },
25691 - { 0x00008064, 0x00000000 },
25692 - { 0x000080c0, 0x2a82301a },
25693 - { 0x000080c4, 0x05dc01e0 },
25694 - { 0x000080c8, 0x1f402710 },
25695 - { 0x000080cc, 0x01f40000 },
25696 - { 0x000080d0, 0x00001e00 },
25697 - { 0x000080d4, 0x00000000 },
25698 - { 0x000080d8, 0x00400000 },
25699 - { 0x000080e0, 0xffffffff },
25700 - { 0x000080e4, 0x0000ffff },
25701 - { 0x000080e8, 0x003f3f3f },
25702 - { 0x000080ec, 0x00000000 },
25703 - { 0x000080f0, 0x00000000 },
25704 - { 0x000080f4, 0x00000000 },
25705 - { 0x000080f8, 0x00000000 },
25706 - { 0x000080fc, 0x00020000 },
25707 - { 0x00008100, 0x00020000 },
25708 - { 0x00008104, 0x00000001 },
25709 - { 0x00008108, 0x00000052 },
25710 - { 0x0000810c, 0x00000000 },
25711 - { 0x00008110, 0x00000168 },
25712 - { 0x00008118, 0x000100aa },
25713 - { 0x0000811c, 0x00003210 },
25714 - { 0x00008120, 0x08f04800 },
25715 - { 0x00008124, 0x00000000 },
25716 - { 0x00008128, 0x00000000 },
25717 - { 0x0000812c, 0x00000000 },
25718 - { 0x00008130, 0x00000000 },
25719 - { 0x00008134, 0x00000000 },
25720 - { 0x00008138, 0x00000000 },
25721 - { 0x0000813c, 0x00000000 },
25722 - { 0x00008144, 0xffffffff },
25723 - { 0x00008168, 0x00000000 },
25724 - { 0x0000816c, 0x00000000 },
25725 - { 0x00008170, 0x32143320 },
25726 - { 0x00008174, 0xfaa4fa50 },
25727 - { 0x00008178, 0x00000100 },
25728 - { 0x0000817c, 0x00000000 },
25729 - { 0x000081c4, 0x00000000 },
25730 - { 0x000081d0, 0x00003210 },
25731 - { 0x000081ec, 0x00000000 },
25732 - { 0x000081f0, 0x00000000 },
25733 - { 0x000081f4, 0x00000000 },
25734 - { 0x000081f8, 0x00000000 },
25735 - { 0x000081fc, 0x00000000 },
25736 - { 0x00008200, 0x00000000 },
25737 - { 0x00008204, 0x00000000 },
25738 - { 0x00008208, 0x00000000 },
25739 - { 0x0000820c, 0x00000000 },
25740 - { 0x00008210, 0x00000000 },
25741 - { 0x00008214, 0x00000000 },
25742 - { 0x00008218, 0x00000000 },
25743 - { 0x0000821c, 0x00000000 },
25744 - { 0x00008220, 0x00000000 },
25745 - { 0x00008224, 0x00000000 },
25746 - { 0x00008228, 0x00000000 },
25747 - { 0x0000822c, 0x00000000 },
25748 - { 0x00008230, 0x00000000 },
25749 - { 0x00008234, 0x00000000 },
25750 - { 0x00008238, 0x00000000 },
25751 - { 0x0000823c, 0x00000000 },
25752 - { 0x00008240, 0x00100000 },
25753 - { 0x00008244, 0x0010f400 },
25754 - { 0x00008248, 0x00000100 },
25755 - { 0x0000824c, 0x0001e800 },
25756 - { 0x00008250, 0x00000000 },
25757 - { 0x00008254, 0x00000000 },
25758 - { 0x00008258, 0x00000000 },
25759 - { 0x0000825c, 0x400000ff },
25760 - { 0x00008260, 0x00080922 },
25761 - { 0x00008270, 0x00000000 },
25762 - { 0x00008274, 0x40000000 },
25763 - { 0x00008278, 0x003e4180 },
25764 - { 0x0000827c, 0x00000000 },
25765 - { 0x00008284, 0x0000002c },
25766 - { 0x00008288, 0x0000002c },
25767 - { 0x0000828c, 0x00000000 },
25768 - { 0x00008294, 0x00000000 },
25769 - { 0x00008298, 0x00000000 },
25770 - { 0x00008300, 0x00000000 },
25771 - { 0x00008304, 0x00000000 },
25772 - { 0x00008308, 0x00000000 },
25773 - { 0x0000830c, 0x00000000 },
25774 - { 0x00008310, 0x00000000 },
25775 - { 0x00008314, 0x00000000 },
25776 - { 0x00008318, 0x00000000 },
25777 - { 0x00008328, 0x00000000 },
25778 - { 0x0000832c, 0x00000007 },
25779 - { 0x00008330, 0x00000302 },
25780 - { 0x00008334, 0x00000e00 },
25781 - { 0x00008338, 0x00ff0000 },
25782 - { 0x0000833c, 0x00000000 },
25783 - { 0x00008340, 0x000107ff },
25784 - { 0x00009808, 0x00000000 },
25785 - { 0x0000980c, 0xad848e19 },
25786 - { 0x00009810, 0x7d14e000 },
25787 - { 0x00009814, 0x9c0a9f6b },
25788 - { 0x0000981c, 0x00000000 },
25789 - { 0x0000982c, 0x0000a000 },
25790 - { 0x00009830, 0x00000000 },
25791 - { 0x0000983c, 0x00200400 },
25792 - { 0x00009840, 0x206a01ae },
25793 - { 0x0000984c, 0x1284233c },
25794 - { 0x00009854, 0x00000859 },
25795 - { 0x00009900, 0x00000000 },
25796 - { 0x00009904, 0x00000000 },
25797 - { 0x00009908, 0x00000000 },
25798 - { 0x0000990c, 0x00000000 },
25799 - { 0x0000991c, 0x10000fff },
25800 - { 0x00009920, 0x05100000 },
25801 - { 0x0000a920, 0x05100000 },
25802 - { 0x0000b920, 0x05100000 },
25803 - { 0x00009928, 0x00000001 },
25804 - { 0x0000992c, 0x00000004 },
25805 - { 0x00009934, 0x1e1f2022 },
25806 - { 0x00009938, 0x0a0b0c0d },
25807 - { 0x0000993c, 0x00000000 },
25808 - { 0x00009948, 0x9280b212 },
25809 - { 0x0000994c, 0x00020028 },
25810 - { 0x00009954, 0x5f3ca3de },
25811 - { 0x00009958, 0x2108ecff },
25812 - { 0x00009940, 0x00750604 },
25813 - { 0x0000c95c, 0x004b6a8e },
25814 - { 0x00009970, 0x190fb515 },
25815 - { 0x00009974, 0x00000000 },
25816 - { 0x00009978, 0x00000001 },
25817 - { 0x0000997c, 0x00000000 },
25818 - { 0x00009980, 0x00000000 },
25819 - { 0x00009984, 0x00000000 },
25820 - { 0x00009988, 0x00000000 },
25821 - { 0x0000998c, 0x00000000 },
25822 - { 0x00009990, 0x00000000 },
25823 - { 0x00009994, 0x00000000 },
25824 - { 0x00009998, 0x00000000 },
25825 - { 0x0000999c, 0x00000000 },
25826 - { 0x000099a0, 0x00000000 },
25827 - { 0x000099a4, 0x00000001 },
25828 - { 0x000099a8, 0x201fff00 },
25829 - { 0x000099ac, 0x006f0000 },
25830 - { 0x000099b0, 0x03051000 },
25831 - { 0x000099dc, 0x00000000 },
25832 - { 0x000099e0, 0x00000200 },
25833 - { 0x000099e4, 0xaaaaaaaa },
25834 - { 0x000099e8, 0x3c466478 },
25835 - { 0x000099ec, 0x0cc80caa },
25836 - { 0x000099fc, 0x00001042 },
25837 - { 0x00009b00, 0x00000000 },
25838 - { 0x00009b04, 0x00000001 },
25839 - { 0x00009b08, 0x00000002 },
25840 - { 0x00009b0c, 0x00000003 },
25841 - { 0x00009b10, 0x00000004 },
25842 - { 0x00009b14, 0x00000005 },
25843 - { 0x00009b18, 0x00000008 },
25844 - { 0x00009b1c, 0x00000009 },
25845 - { 0x00009b20, 0x0000000a },
25846 - { 0x00009b24, 0x0000000b },
25847 - { 0x00009b28, 0x0000000c },
25848 - { 0x00009b2c, 0x0000000d },
25849 - { 0x00009b30, 0x00000010 },
25850 - { 0x00009b34, 0x00000011 },
25851 - { 0x00009b38, 0x00000012 },
25852 - { 0x00009b3c, 0x00000013 },
25853 - { 0x00009b40, 0x00000014 },
25854 - { 0x00009b44, 0x00000015 },
25855 - { 0x00009b48, 0x00000018 },
25856 - { 0x00009b4c, 0x00000019 },
25857 - { 0x00009b50, 0x0000001a },
25858 - { 0x00009b54, 0x0000001b },
25859 - { 0x00009b58, 0x0000001c },
25860 - { 0x00009b5c, 0x0000001d },
25861 - { 0x00009b60, 0x00000020 },
25862 - { 0x00009b64, 0x00000021 },
25863 - { 0x00009b68, 0x00000022 },
25864 - { 0x00009b6c, 0x00000023 },
25865 - { 0x00009b70, 0x00000024 },
25866 - { 0x00009b74, 0x00000025 },
25867 - { 0x00009b78, 0x00000028 },
25868 - { 0x00009b7c, 0x00000029 },
25869 - { 0x00009b80, 0x0000002a },
25870 - { 0x00009b84, 0x0000002b },
25871 - { 0x00009b88, 0x0000002c },
25872 - { 0x00009b8c, 0x0000002d },
25873 - { 0x00009b90, 0x00000030 },
25874 - { 0x00009b94, 0x00000031 },
25875 - { 0x00009b98, 0x00000032 },
25876 - { 0x00009b9c, 0x00000033 },
25877 - { 0x00009ba0, 0x00000034 },
25878 - { 0x00009ba4, 0x00000035 },
25879 - { 0x00009ba8, 0x00000035 },
25880 - { 0x00009bac, 0x00000035 },
25881 - { 0x00009bb0, 0x00000035 },
25882 - { 0x00009bb4, 0x00000035 },
25883 - { 0x00009bb8, 0x00000035 },
25884 - { 0x00009bbc, 0x00000035 },
25885 - { 0x00009bc0, 0x00000035 },
25886 - { 0x00009bc4, 0x00000035 },
25887 - { 0x00009bc8, 0x00000035 },
25888 - { 0x00009bcc, 0x00000035 },
25889 - { 0x00009bd0, 0x00000035 },
25890 - { 0x00009bd4, 0x00000035 },
25891 - { 0x00009bd8, 0x00000035 },
25892 - { 0x00009bdc, 0x00000035 },
25893 - { 0x00009be0, 0x00000035 },
25894 - { 0x00009be4, 0x00000035 },
25895 - { 0x00009be8, 0x00000035 },
25896 - { 0x00009bec, 0x00000035 },
25897 - { 0x00009bf0, 0x00000035 },
25898 - { 0x00009bf4, 0x00000035 },
25899 - { 0x00009bf8, 0x00000010 },
25900 - { 0x00009bfc, 0x0000001a },
25901 - { 0x0000a210, 0x40806333 },
25902 - { 0x0000a214, 0x00106c10 },
25903 - { 0x0000a218, 0x009c4060 },
25904 - { 0x0000a220, 0x018830c6 },
25905 - { 0x0000a224, 0x00000400 },
25906 - { 0x0000a228, 0x001a0bb5 },
25907 - { 0x0000a22c, 0x00000000 },
25908 - { 0x0000a234, 0x20202020 },
25909 - { 0x0000a238, 0x20202020 },
25910 - { 0x0000a23c, 0x13c889af },
25911 - { 0x0000a240, 0x38490a20 },
25912 - { 0x0000a244, 0x00007bb6 },
25913 - { 0x0000a248, 0x0fff3ffc },
25914 - { 0x0000a24c, 0x00000001 },
25915 - { 0x0000a250, 0x0000e000 },
25916 - { 0x0000a254, 0x00000000 },
25917 - { 0x0000a258, 0x0cc75380 },
25918 - { 0x0000a25c, 0x0f0f0f01 },
25919 - { 0x0000a260, 0xdfa91f01 },
25920 - { 0x0000a268, 0x00000001 },
25921 - { 0x0000a26c, 0x0ebae9c6 },
25922 - { 0x0000b26c, 0x0ebae9c6 },
25923 - { 0x0000c26c, 0x0ebae9c6 },
25924 - { 0x0000d270, 0x00820820 },
25925 - { 0x0000a278, 0x1ce739ce },
25926 - { 0x0000a27c, 0x050701ce },
25927 - { 0x0000a338, 0x00000000 },
25928 - { 0x0000a33c, 0x00000000 },
25929 - { 0x0000a340, 0x00000000 },
25930 - { 0x0000a344, 0x00000000 },
25931 - { 0x0000a348, 0x3fffffff },
25932 - { 0x0000a34c, 0x3fffffff },
25933 - { 0x0000a350, 0x3fffffff },
25934 - { 0x0000a354, 0x0003ffff },
25935 - { 0x0000a358, 0x79bfaa03 },
25936 - { 0x0000d35c, 0x07ffffef },
25937 - { 0x0000d360, 0x0fffffe7 },
25938 - { 0x0000d364, 0x17ffffe5 },
25939 - { 0x0000d368, 0x1fffffe4 },
25940 - { 0x0000d36c, 0x37ffffe3 },
25941 - { 0x0000d370, 0x3fffffe3 },
25942 - { 0x0000d374, 0x57ffffe3 },
25943 - { 0x0000d378, 0x5fffffe2 },
25944 - { 0x0000d37c, 0x7fffffe2 },
25945 - { 0x0000d380, 0x7f3c7bba },
25946 - { 0x0000d384, 0xf3307ff0 },
25947 - { 0x0000a388, 0x0c000000 },
25948 - { 0x0000a38c, 0x20202020 },
25949 - { 0x0000a390, 0x20202020 },
25950 - { 0x0000a394, 0x1ce739ce },
25951 - { 0x0000a398, 0x000001ce },
25952 - { 0x0000a39c, 0x00000001 },
25953 - { 0x0000a3a0, 0x00000000 },
25954 - { 0x0000a3a4, 0x00000000 },
25955 - { 0x0000a3a8, 0x00000000 },
25956 - { 0x0000a3ac, 0x00000000 },
25957 - { 0x0000a3b0, 0x00000000 },
25958 - { 0x0000a3b4, 0x00000000 },
25959 - { 0x0000a3b8, 0x00000000 },
25960 - { 0x0000a3bc, 0x00000000 },
25961 - { 0x0000a3c0, 0x00000000 },
25962 - { 0x0000a3c4, 0x00000000 },
25963 - { 0x0000a3c8, 0x00000246 },
25964 - { 0x0000a3cc, 0x20202020 },
25965 - { 0x0000a3d0, 0x20202020 },
25966 - { 0x0000a3d4, 0x20202020 },
25967 - { 0x0000a3dc, 0x1ce739ce },
25968 - { 0x0000a3e0, 0x000001ce },
25969 -};
25970 -
25971 -static const u32 ar5416Bank0_9160[][2] = {
25972 - { 0x000098b0, 0x1e5795e5 },
25973 - { 0x000098e0, 0x02008020 },
25974 -};
25975 -
25976 -static const u32 ar5416BB_RfGain_9160[][3] = {
25977 - { 0x00009a00, 0x00000000, 0x00000000 },
25978 - { 0x00009a04, 0x00000040, 0x00000040 },
25979 - { 0x00009a08, 0x00000080, 0x00000080 },
25980 - { 0x00009a0c, 0x000001a1, 0x00000141 },
25981 - { 0x00009a10, 0x000001e1, 0x00000181 },
25982 - { 0x00009a14, 0x00000021, 0x000001c1 },
25983 - { 0x00009a18, 0x00000061, 0x00000001 },
25984 - { 0x00009a1c, 0x00000168, 0x00000041 },
25985 - { 0x00009a20, 0x000001a8, 0x000001a8 },
25986 - { 0x00009a24, 0x000001e8, 0x000001e8 },
25987 - { 0x00009a28, 0x00000028, 0x00000028 },
25988 - { 0x00009a2c, 0x00000068, 0x00000068 },
25989 - { 0x00009a30, 0x00000189, 0x000000a8 },
25990 - { 0x00009a34, 0x000001c9, 0x00000169 },
25991 - { 0x00009a38, 0x00000009, 0x000001a9 },
25992 - { 0x00009a3c, 0x00000049, 0x000001e9 },
25993 - { 0x00009a40, 0x00000089, 0x00000029 },
25994 - { 0x00009a44, 0x00000170, 0x00000069 },
25995 - { 0x00009a48, 0x000001b0, 0x00000190 },
25996 - { 0x00009a4c, 0x000001f0, 0x000001d0 },
25997 - { 0x00009a50, 0x00000030, 0x00000010 },
25998 - { 0x00009a54, 0x00000070, 0x00000050 },
25999 - { 0x00009a58, 0x00000191, 0x00000090 },
26000 - { 0x00009a5c, 0x000001d1, 0x00000151 },
26001 - { 0x00009a60, 0x00000011, 0x00000191 },
26002 - { 0x00009a64, 0x00000051, 0x000001d1 },
26003 - { 0x00009a68, 0x00000091, 0x00000011 },
26004 - { 0x00009a6c, 0x000001b8, 0x00000051 },
26005 - { 0x00009a70, 0x000001f8, 0x00000198 },
26006 - { 0x00009a74, 0x00000038, 0x000001d8 },
26007 - { 0x00009a78, 0x00000078, 0x00000018 },
26008 - { 0x00009a7c, 0x00000199, 0x00000058 },
26009 - { 0x00009a80, 0x000001d9, 0x00000098 },
26010 - { 0x00009a84, 0x00000019, 0x00000159 },
26011 - { 0x00009a88, 0x00000059, 0x00000199 },
26012 - { 0x00009a8c, 0x00000099, 0x000001d9 },
26013 - { 0x00009a90, 0x000000d9, 0x00000019 },
26014 - { 0x00009a94, 0x000000f9, 0x00000059 },
26015 - { 0x00009a98, 0x000000f9, 0x00000099 },
26016 - { 0x00009a9c, 0x000000f9, 0x000000d9 },
26017 - { 0x00009aa0, 0x000000f9, 0x000000f9 },
26018 - { 0x00009aa4, 0x000000f9, 0x000000f9 },
26019 - { 0x00009aa8, 0x000000f9, 0x000000f9 },
26020 - { 0x00009aac, 0x000000f9, 0x000000f9 },
26021 - { 0x00009ab0, 0x000000f9, 0x000000f9 },
26022 - { 0x00009ab4, 0x000000f9, 0x000000f9 },
26023 - { 0x00009ab8, 0x000000f9, 0x000000f9 },
26024 - { 0x00009abc, 0x000000f9, 0x000000f9 },
26025 - { 0x00009ac0, 0x000000f9, 0x000000f9 },
26026 - { 0x00009ac4, 0x000000f9, 0x000000f9 },
26027 - { 0x00009ac8, 0x000000f9, 0x000000f9 },
26028 - { 0x00009acc, 0x000000f9, 0x000000f9 },
26029 - { 0x00009ad0, 0x000000f9, 0x000000f9 },
26030 - { 0x00009ad4, 0x000000f9, 0x000000f9 },
26031 - { 0x00009ad8, 0x000000f9, 0x000000f9 },
26032 - { 0x00009adc, 0x000000f9, 0x000000f9 },
26033 - { 0x00009ae0, 0x000000f9, 0x000000f9 },
26034 - { 0x00009ae4, 0x000000f9, 0x000000f9 },
26035 - { 0x00009ae8, 0x000000f9, 0x000000f9 },
26036 - { 0x00009aec, 0x000000f9, 0x000000f9 },
26037 - { 0x00009af0, 0x000000f9, 0x000000f9 },
26038 - { 0x00009af4, 0x000000f9, 0x000000f9 },
26039 - { 0x00009af8, 0x000000f9, 0x000000f9 },
26040 - { 0x00009afc, 0x000000f9, 0x000000f9 },
26041 -};
26042 -
26043 -static const u32 ar5416Bank1_9160[][2] = {
26044 - { 0x000098b0, 0x02108421 },
26045 - { 0x000098ec, 0x00000008 },
26046 -};
26047 -
26048 -static const u32 ar5416Bank2_9160[][2] = {
26049 - { 0x000098b0, 0x0e73ff17 },
26050 - { 0x000098e0, 0x00000420 },
26051 -};
26052 -
26053 -static const u32 ar5416Bank3_9160[][3] = {
26054 - { 0x000098f0, 0x01400018, 0x01c00018 },
26055 -};
26056 -
26057 -static const u32 ar5416Bank6_9160[][3] = {
26058 - { 0x0000989c, 0x00000000, 0x00000000 },
26059 - { 0x0000989c, 0x00000000, 0x00000000 },
26060 - { 0x0000989c, 0x00000000, 0x00000000 },
26061 - { 0x0000989c, 0x00e00000, 0x00e00000 },
26062 - { 0x0000989c, 0x005e0000, 0x005e0000 },
26063 - { 0x0000989c, 0x00120000, 0x00120000 },
26064 - { 0x0000989c, 0x00620000, 0x00620000 },
26065 - { 0x0000989c, 0x00020000, 0x00020000 },
26066 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26067 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26068 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26069 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
26070 - { 0x0000989c, 0x005f0000, 0x005f0000 },
26071 - { 0x0000989c, 0x00870000, 0x00870000 },
26072 - { 0x0000989c, 0x00f90000, 0x00f90000 },
26073 - { 0x0000989c, 0x007b0000, 0x007b0000 },
26074 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26075 - { 0x0000989c, 0x00f50000, 0x00f50000 },
26076 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
26077 - { 0x0000989c, 0x00110000, 0x00110000 },
26078 - { 0x0000989c, 0x006100a8, 0x006100a8 },
26079 - { 0x0000989c, 0x004210a2, 0x004210a2 },
26080 - { 0x0000989c, 0x0014008f, 0x0014008f },
26081 - { 0x0000989c, 0x00c40003, 0x00c40003 },
26082 - { 0x0000989c, 0x003000f2, 0x003000f2 },
26083 - { 0x0000989c, 0x00440016, 0x00440016 },
26084 - { 0x0000989c, 0x00410040, 0x00410040 },
26085 - { 0x0000989c, 0x0001805e, 0x0001805e },
26086 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
26087 - { 0x0000989c, 0x000000f1, 0x000000f1 },
26088 - { 0x0000989c, 0x00002081, 0x00002081 },
26089 - { 0x0000989c, 0x000000d4, 0x000000d4 },
26090 - { 0x000098d0, 0x0000000f, 0x0010000f },
26091 -};
26092 -
26093 -static const u32 ar5416Bank6TPC_9160[][3] = {
26094 - { 0x0000989c, 0x00000000, 0x00000000 },
26095 - { 0x0000989c, 0x00000000, 0x00000000 },
26096 - { 0x0000989c, 0x00000000, 0x00000000 },
26097 - { 0x0000989c, 0x00e00000, 0x00e00000 },
26098 - { 0x0000989c, 0x005e0000, 0x005e0000 },
26099 - { 0x0000989c, 0x00120000, 0x00120000 },
26100 - { 0x0000989c, 0x00620000, 0x00620000 },
26101 - { 0x0000989c, 0x00020000, 0x00020000 },
26102 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26103 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26104 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26105 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
26106 - { 0x0000989c, 0x005f0000, 0x005f0000 },
26107 - { 0x0000989c, 0x00870000, 0x00870000 },
26108 - { 0x0000989c, 0x00f90000, 0x00f90000 },
26109 - { 0x0000989c, 0x007b0000, 0x007b0000 },
26110 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26111 - { 0x0000989c, 0x00f50000, 0x00f50000 },
26112 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
26113 - { 0x0000989c, 0x00110000, 0x00110000 },
26114 - { 0x0000989c, 0x006100a8, 0x006100a8 },
26115 - { 0x0000989c, 0x00423022, 0x00423022 },
26116 - { 0x0000989c, 0x2014008f, 0x2014008f },
26117 - { 0x0000989c, 0x00c40002, 0x00c40002 },
26118 - { 0x0000989c, 0x003000f2, 0x003000f2 },
26119 - { 0x0000989c, 0x00440016, 0x00440016 },
26120 - { 0x0000989c, 0x00410040, 0x00410040 },
26121 - { 0x0000989c, 0x0001805e, 0x0001805e },
26122 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
26123 - { 0x0000989c, 0x000000e1, 0x000000e1 },
26124 - { 0x0000989c, 0x00007080, 0x00007080 },
26125 - { 0x0000989c, 0x000000d4, 0x000000d4 },
26126 - { 0x000098d0, 0x0000000f, 0x0010000f },
26127 -};
26128 -
26129 -static const u32 ar5416Bank7_9160[][2] = {
26130 - { 0x0000989c, 0x00000500 },
26131 - { 0x0000989c, 0x00000800 },
26132 - { 0x000098cc, 0x0000000e },
26133 -};
26134 -
26135 -static u32 ar5416Addac_9160[][2] = {
26136 - {0x0000989c, 0x00000000 },
26137 - {0x0000989c, 0x00000000 },
26138 - {0x0000989c, 0x00000000 },
26139 - {0x0000989c, 0x00000000 },
26140 - {0x0000989c, 0x00000000 },
26141 - {0x0000989c, 0x00000000 },
26142 - {0x0000989c, 0x000000c0 },
26143 - {0x0000989c, 0x00000018 },
26144 - {0x0000989c, 0x00000004 },
26145 - {0x0000989c, 0x00000000 },
26146 - {0x0000989c, 0x00000000 },
26147 - {0x0000989c, 0x00000000 },
26148 - {0x0000989c, 0x00000000 },
26149 - {0x0000989c, 0x00000000 },
26150 - {0x0000989c, 0x00000000 },
26151 - {0x0000989c, 0x00000000 },
26152 - {0x0000989c, 0x00000000 },
26153 - {0x0000989c, 0x00000000 },
26154 - {0x0000989c, 0x00000000 },
26155 - {0x0000989c, 0x00000000 },
26156 - {0x0000989c, 0x00000000 },
26157 - {0x0000989c, 0x000000c0 },
26158 - {0x0000989c, 0x00000019 },
26159 - {0x0000989c, 0x00000004 },
26160 - {0x0000989c, 0x00000000 },
26161 - {0x0000989c, 0x00000000 },
26162 - {0x0000989c, 0x00000000 },
26163 - {0x0000989c, 0x00000004 },
26164 - {0x0000989c, 0x00000003 },
26165 - {0x0000989c, 0x00000008 },
26166 - {0x0000989c, 0x00000000 },
26167 - {0x000098cc, 0x00000000 },
26168 -};
26169 -
26170 -static u32 ar5416Addac_91601_1[][2] = {
26171 - {0x0000989c, 0x00000000 },
26172 - {0x0000989c, 0x00000000 },
26173 - {0x0000989c, 0x00000000 },
26174 - {0x0000989c, 0x00000000 },
26175 - {0x0000989c, 0x00000000 },
26176 - {0x0000989c, 0x00000000 },
26177 - {0x0000989c, 0x000000c0 },
26178 - {0x0000989c, 0x00000018 },
26179 - {0x0000989c, 0x00000004 },
26180 - {0x0000989c, 0x00000000 },
26181 - {0x0000989c, 0x00000000 },
26182 - {0x0000989c, 0x00000000 },
26183 - {0x0000989c, 0x00000000 },
26184 - {0x0000989c, 0x00000000 },
26185 - {0x0000989c, 0x00000000 },
26186 - {0x0000989c, 0x00000000 },
26187 - {0x0000989c, 0x00000000 },
26188 - {0x0000989c, 0x00000000 },
26189 - {0x0000989c, 0x00000000 },
26190 - {0x0000989c, 0x00000000 },
26191 - {0x0000989c, 0x00000000 },
26192 - {0x0000989c, 0x000000c0 },
26193 - {0x0000989c, 0x00000019 },
26194 - {0x0000989c, 0x00000004 },
26195 - {0x0000989c, 0x00000000 },
26196 - {0x0000989c, 0x00000000 },
26197 - {0x0000989c, 0x00000000 },
26198 - {0x0000989c, 0x00000000 },
26199 - {0x0000989c, 0x00000000 },
26200 - {0x0000989c, 0x00000000 },
26201 - {0x0000989c, 0x00000000 },
26202 - {0x000098cc, 0x00000000 },
26203 -};
26204 -
26205 -/* XXX 9280 1 */
26206 -static const u32 ar9280Modes_9280[][6] = {
26207 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
26208 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
26209 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
26210 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
26211 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801080, 0x08400840, 0x06e006e0 },
26212 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
26213 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
26214 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
26215 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
26216 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
26217 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
26218 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
26219 - { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
26220 - { 0x00009848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 },
26221 - { 0x0000a848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 },
26222 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
26223 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
26224 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
26225 - { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d20, 0x00049d20, 0x00049d18 },
26226 - { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
26227 - { 0x00009868, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190 },
26228 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
26229 - { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
26230 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
26231 - { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
26232 - { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010 },
26233 - { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
26234 - { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
26235 - { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
26236 - { 0x0000c9b8, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a },
26237 - { 0x0000c9bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
26238 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
26239 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
26240 - { 0x000099c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c },
26241 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
26242 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
26243 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
26244 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
26245 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000214, 0x00000214, 0x00000214 },
26246 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000218, 0x00000218, 0x00000218 },
26247 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000224, 0x00000224, 0x00000224 },
26248 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000228, 0x00000228, 0x00000228 },
26249 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000022c, 0x0000022c, 0x0000022c },
26250 - { 0x00009a14, 0x00008200, 0x00008200, 0x00000230, 0x00000230, 0x00000230 },
26251 - { 0x00009a18, 0x00008204, 0x00008204, 0x000002a4, 0x000002a4, 0x000002a4 },
26252 - { 0x00009a1c, 0x00008208, 0x00008208, 0x000002a8, 0x000002a8, 0x000002a8 },
26253 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x000002ac, 0x000002ac, 0x000002ac },
26254 - { 0x00009a24, 0x00008210, 0x00008210, 0x000002b0, 0x000002b0, 0x000002b0 },
26255 - { 0x00009a28, 0x00008214, 0x00008214, 0x000002b4, 0x000002b4, 0x000002b4 },
26256 - { 0x00009a2c, 0x00008280, 0x00008280, 0x000002b8, 0x000002b8, 0x000002b8 },
26257 - { 0x00009a30, 0x00008284, 0x00008284, 0x00000390, 0x00000390, 0x00000390 },
26258 - { 0x00009a34, 0x00008288, 0x00008288, 0x00000394, 0x00000394, 0x00000394 },
26259 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00000398, 0x00000398, 0x00000398 },
26260 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00000334, 0x00000334, 0x00000334 },
26261 - { 0x00009a40, 0x00008300, 0x00008300, 0x00000338, 0x00000338, 0x00000338 },
26262 - { 0x00009a44, 0x00008304, 0x00008304, 0x000003ac, 0x000003ac, 0x000003ac },
26263 - { 0x00009a48, 0x00008308, 0x00008308, 0x000003b0, 0x000003b0, 0x000003b0 },
26264 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x000003b4, 0x000003b4, 0x000003b4 },
26265 - { 0x00009a50, 0x00008310, 0x00008310, 0x000003b8, 0x000003b8, 0x000003b8 },
26266 - { 0x00009a54, 0x00008314, 0x00008314, 0x000003a5, 0x000003a5, 0x000003a5 },
26267 - { 0x00009a58, 0x00008380, 0x00008380, 0x000003a9, 0x000003a9, 0x000003a9 },
26268 - { 0x00009a5c, 0x00008384, 0x00008384, 0x000003ad, 0x000003ad, 0x000003ad },
26269 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
26270 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
26271 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
26272 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
26273 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
26274 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
26275 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
26276 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
26277 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
26278 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
26279 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
26280 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
26281 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
26282 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
26283 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
26284 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
26285 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
26286 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
26287 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
26288 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
26289 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
26290 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
26291 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
26292 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
26293 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
26294 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
26295 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
26296 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
26297 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
26298 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
26299 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
26300 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
26301 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
26302 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
26303 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c },
26304 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 },
26305 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 },
26306 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 },
26307 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 },
26308 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 },
26309 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 },
26310 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 },
26311 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 },
26312 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 },
26313 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 },
26314 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 },
26315 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 },
26316 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c },
26317 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 },
26318 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 },
26319 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 },
26320 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 },
26321 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 },
26322 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 },
26323 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 },
26324 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 },
26325 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad },
26326 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 },
26327 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 },
26328 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 },
26329 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 },
26330 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 },
26331 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 },
26332 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 },
26333 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 },
26334 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 },
26335 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca },
26336 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce },
26337 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 },
26338 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 },
26339 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 },
26340 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 },
26341 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb },
26342 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf },
26343 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 },
26344 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db },
26345 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db },
26346 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db },
26347 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26348 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26349 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26350 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26351 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26352 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26353 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26354 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26355 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26356 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26357 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26358 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26359 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26360 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26361 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26362 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26363 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26364 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26365 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26366 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26367 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26368 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26369 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26370 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26371 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26372 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26373 - { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 },
26374 - { 0x0000a208, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788 },
26375 - { 0x0000a20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 },
26376 - { 0x0000b20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 },
26377 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
26378 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
26379 - { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
26380 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
26381 - { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
26382 - { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
26383 - { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b },
26384 - { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 },
26385 - { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 },
26386 - { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a },
26387 - { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 },
26388 - { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
26389 - { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b },
26390 - { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 },
26391 - { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 },
26392 - { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a },
26393 - { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 },
26394 - { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b },
26395 - { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 },
26396 - { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 },
26397 - { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a },
26398 - { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 },
26399 - { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a },
26400 - { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 },
26401 - { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 },
26402 - { 0x0000784c, 0x0e4f048c, 0x0e4f048c, 0x0e4d048c, 0x0e4d048c, 0x0e4d048c },
26403 - { 0x00007854, 0x12031828, 0x12031828, 0x12035828, 0x12035828, 0x12035828 },
26404 - { 0x00007870, 0x807ec400, 0x807ec400, 0x807ec000, 0x807ec000, 0x807ec000 },
26405 - { 0x0000788c, 0x00010000, 0x00010000, 0x00110000, 0x00110000, 0x00110000 },
26406 -};
26407 -
26408 -static const u32 ar9280Common_9280[][2] = {
26409 - { 0x0000000c, 0x00000000 },
26410 - { 0x00000030, 0x00020015 },
26411 - { 0x00000034, 0x00000005 },
26412 - { 0x00000040, 0x00000000 },
26413 - { 0x00000044, 0x00000008 },
26414 - { 0x00000048, 0x00000008 },
26415 - { 0x0000004c, 0x00000010 },
26416 - { 0x00000050, 0x00000000 },
26417 - { 0x00000054, 0x0000001f },
26418 - { 0x00000800, 0x00000000 },
26419 - { 0x00000804, 0x00000000 },
26420 - { 0x00000808, 0x00000000 },
26421 - { 0x0000080c, 0x00000000 },
26422 - { 0x00000810, 0x00000000 },
26423 - { 0x00000814, 0x00000000 },
26424 - { 0x00000818, 0x00000000 },
26425 - { 0x0000081c, 0x00000000 },
26426 - { 0x00000820, 0x00000000 },
26427 - { 0x00000824, 0x00000000 },
26428 - { 0x00001040, 0x002ffc0f },
26429 - { 0x00001044, 0x002ffc0f },
26430 - { 0x00001048, 0x002ffc0f },
26431 - { 0x0000104c, 0x002ffc0f },
26432 - { 0x00001050, 0x002ffc0f },
26433 - { 0x00001054, 0x002ffc0f },
26434 - { 0x00001058, 0x002ffc0f },
26435 - { 0x0000105c, 0x002ffc0f },
26436 - { 0x00001060, 0x002ffc0f },
26437 - { 0x00001064, 0x002ffc0f },
26438 - { 0x00001230, 0x00000000 },
26439 - { 0x00001270, 0x00000000 },
26440 - { 0x00001038, 0x00000000 },
26441 - { 0x00001078, 0x00000000 },
26442 - { 0x000010b8, 0x00000000 },
26443 - { 0x000010f8, 0x00000000 },
26444 - { 0x00001138, 0x00000000 },
26445 - { 0x00001178, 0x00000000 },
26446 - { 0x000011b8, 0x00000000 },
26447 - { 0x000011f8, 0x00000000 },
26448 - { 0x00001238, 0x00000000 },
26449 - { 0x00001278, 0x00000000 },
26450 - { 0x000012b8, 0x00000000 },
26451 - { 0x000012f8, 0x00000000 },
26452 - { 0x00001338, 0x00000000 },
26453 - { 0x00001378, 0x00000000 },
26454 - { 0x000013b8, 0x00000000 },
26455 - { 0x000013f8, 0x00000000 },
26456 - { 0x00001438, 0x00000000 },
26457 - { 0x00001478, 0x00000000 },
26458 - { 0x000014b8, 0x00000000 },
26459 - { 0x000014f8, 0x00000000 },
26460 - { 0x00001538, 0x00000000 },
26461 - { 0x00001578, 0x00000000 },
26462 - { 0x000015b8, 0x00000000 },
26463 - { 0x000015f8, 0x00000000 },
26464 - { 0x00001638, 0x00000000 },
26465 - { 0x00001678, 0x00000000 },
26466 - { 0x000016b8, 0x00000000 },
26467 - { 0x000016f8, 0x00000000 },
26468 - { 0x00001738, 0x00000000 },
26469 - { 0x00001778, 0x00000000 },
26470 - { 0x000017b8, 0x00000000 },
26471 - { 0x000017f8, 0x00000000 },
26472 - { 0x0000103c, 0x00000000 },
26473 - { 0x0000107c, 0x00000000 },
26474 - { 0x000010bc, 0x00000000 },
26475 - { 0x000010fc, 0x00000000 },
26476 - { 0x0000113c, 0x00000000 },
26477 - { 0x0000117c, 0x00000000 },
26478 - { 0x000011bc, 0x00000000 },
26479 - { 0x000011fc, 0x00000000 },
26480 - { 0x0000123c, 0x00000000 },
26481 - { 0x0000127c, 0x00000000 },
26482 - { 0x000012bc, 0x00000000 },
26483 - { 0x000012fc, 0x00000000 },
26484 - { 0x0000133c, 0x00000000 },
26485 - { 0x0000137c, 0x00000000 },
26486 - { 0x000013bc, 0x00000000 },
26487 - { 0x000013fc, 0x00000000 },
26488 - { 0x0000143c, 0x00000000 },
26489 - { 0x0000147c, 0x00000000 },
26490 - { 0x00004030, 0x00000002 },
26491 - { 0x0000403c, 0x00000002 },
26492 - { 0x00004024, 0x0000001f },
26493 - { 0x00007010, 0x00000033 },
26494 - { 0x00007038, 0x000004c2 },
26495 - { 0x00008004, 0x00000000 },
26496 - { 0x00008008, 0x00000000 },
26497 - { 0x0000800c, 0x00000000 },
26498 - { 0x00008018, 0x00000700 },
26499 - { 0x00008020, 0x00000000 },
26500 - { 0x00008038, 0x00000000 },
26501 - { 0x0000803c, 0x00000000 },
26502 - { 0x00008048, 0x40000000 },
26503 - { 0x00008054, 0x00000000 },
26504 - { 0x00008058, 0x00000000 },
26505 - { 0x0000805c, 0x000fc78f },
26506 - { 0x00008060, 0x0000000f },
26507 - { 0x00008064, 0x00000000 },
26508 - { 0x00008070, 0x00000000 },
26509 - { 0x000080c0, 0x2a82301a },
26510 - { 0x000080c4, 0x05dc01e0 },
26511 - { 0x000080c8, 0x1f402710 },
26512 - { 0x000080cc, 0x01f40000 },
26513 - { 0x000080d0, 0x00001e00 },
26514 - { 0x000080d4, 0x00000000 },
26515 - { 0x000080d8, 0x00400000 },
26516 - { 0x000080e0, 0xffffffff },
26517 - { 0x000080e4, 0x0000ffff },
26518 - { 0x000080e8, 0x003f3f3f },
26519 - { 0x000080ec, 0x00000000 },
26520 - { 0x000080f0, 0x00000000 },
26521 - { 0x000080f4, 0x00000000 },
26522 - { 0x000080f8, 0x00000000 },
26523 - { 0x000080fc, 0x00020000 },
26524 - { 0x00008100, 0x00020000 },
26525 - { 0x00008104, 0x00000001 },
26526 - { 0x00008108, 0x00000052 },
26527 - { 0x0000810c, 0x00000000 },
26528 - { 0x00008110, 0x00000168 },
26529 - { 0x00008118, 0x000100aa },
26530 - { 0x0000811c, 0x00003210 },
26531 - { 0x00008120, 0x08f04800 },
26532 - { 0x00008124, 0x00000000 },
26533 - { 0x00008128, 0x00000000 },
26534 - { 0x0000812c, 0x00000000 },
26535 - { 0x00008130, 0x00000000 },
26536 - { 0x00008134, 0x00000000 },
26537 - { 0x00008138, 0x00000000 },
26538 - { 0x0000813c, 0x00000000 },
26539 - { 0x00008144, 0x00000000 },
26540 - { 0x00008168, 0x00000000 },
26541 - { 0x0000816c, 0x00000000 },
26542 - { 0x00008170, 0x32143320 },
26543 - { 0x00008174, 0xfaa4fa50 },
26544 - { 0x00008178, 0x00000100 },
26545 - { 0x0000817c, 0x00000000 },
26546 - { 0x000081c4, 0x00000000 },
26547 - { 0x000081d0, 0x00003210 },
26548 - { 0x000081ec, 0x00000000 },
26549 - { 0x000081f0, 0x00000000 },
26550 - { 0x000081f4, 0x00000000 },
26551 - { 0x000081f8, 0x00000000 },
26552 - { 0x000081fc, 0x00000000 },
26553 - { 0x00008200, 0x00000000 },
26554 - { 0x00008204, 0x00000000 },
26555 - { 0x00008208, 0x00000000 },
26556 - { 0x0000820c, 0x00000000 },
26557 - { 0x00008210, 0x00000000 },
26558 - { 0x00008214, 0x00000000 },
26559 - { 0x00008218, 0x00000000 },
26560 - { 0x0000821c, 0x00000000 },
26561 - { 0x00008220, 0x00000000 },
26562 - { 0x00008224, 0x00000000 },
26563 - { 0x00008228, 0x00000000 },
26564 - { 0x0000822c, 0x00000000 },
26565 - { 0x00008230, 0x00000000 },
26566 - { 0x00008234, 0x00000000 },
26567 - { 0x00008238, 0x00000000 },
26568 - { 0x0000823c, 0x00000000 },
26569 - { 0x00008240, 0x00100000 },
26570 - { 0x00008244, 0x0010f400 },
26571 - { 0x00008248, 0x00000100 },
26572 - { 0x0000824c, 0x0001e800 },
26573 - { 0x00008250, 0x00000000 },
26574 - { 0x00008254, 0x00000000 },
26575 - { 0x00008258, 0x00000000 },
26576 - { 0x0000825c, 0x400000ff },
26577 - { 0x00008260, 0x00080922 },
26578 - { 0x00008270, 0x00000000 },
26579 - { 0x00008274, 0x40000000 },
26580 - { 0x00008278, 0x003e4180 },
26581 - { 0x0000827c, 0x00000000 },
26582 - { 0x00008284, 0x0000002c },
26583 - { 0x00008288, 0x0000002c },
26584 - { 0x0000828c, 0x00000000 },
26585 - { 0x00008294, 0x00000000 },
26586 - { 0x00008298, 0x00000000 },
26587 - { 0x00008300, 0x00000000 },
26588 - { 0x00008304, 0x00000000 },
26589 - { 0x00008308, 0x00000000 },
26590 - { 0x0000830c, 0x00000000 },
26591 - { 0x00008310, 0x00000000 },
26592 - { 0x00008314, 0x00000000 },
26593 - { 0x00008318, 0x00000000 },
26594 - { 0x00008328, 0x00000000 },
26595 - { 0x0000832c, 0x00000007 },
26596 - { 0x00008330, 0x00000302 },
26597 - { 0x00008334, 0x00000e00 },
26598 - { 0x00008338, 0x00000000 },
26599 - { 0x0000833c, 0x00000000 },
26600 - { 0x00008340, 0x000107ff },
26601 - { 0x00008344, 0x00000000 },
26602 - { 0x00009808, 0x00000000 },
26603 - { 0x0000980c, 0xaf268e30 },
26604 - { 0x00009810, 0xfd14e000 },
26605 - { 0x00009814, 0x9c0a9f6b },
26606 - { 0x0000981c, 0x00000000 },
26607 - { 0x0000982c, 0x0000a000 },
26608 - { 0x00009830, 0x00000000 },
26609 - { 0x0000983c, 0x00200400 },
26610 - { 0x00009840, 0x206a01ae },
26611 - { 0x0000984c, 0x0040233c },
26612 - { 0x0000a84c, 0x0040233c },
26613 - { 0x00009854, 0x00000044 },
26614 - { 0x00009900, 0x00000000 },
26615 - { 0x00009904, 0x00000000 },
26616 - { 0x00009908, 0x00000000 },
26617 - { 0x0000990c, 0x00000000 },
26618 - { 0x0000991c, 0x10000fff },
26619 - { 0x00009920, 0x04900000 },
26620 - { 0x0000a920, 0x04900000 },
26621 - { 0x00009928, 0x00000001 },
26622 - { 0x0000992c, 0x00000004 },
26623 - { 0x00009934, 0x1e1f2022 },
26624 - { 0x00009938, 0x0a0b0c0d },
26625 - { 0x0000993c, 0x00000000 },
26626 - { 0x00009948, 0x9280c00a },
26627 - { 0x0000994c, 0x00020028 },
26628 - { 0x00009954, 0xe250a51e },
26629 - { 0x00009958, 0x3388ffff },
26630 - { 0x00009940, 0x00781204 },
26631 - { 0x0000c95c, 0x004b6a8e },
26632 - { 0x0000c968, 0x000003ce },
26633 - { 0x00009970, 0x190fb514 },
26634 - { 0x00009974, 0x00000000 },
26635 - { 0x00009978, 0x00000001 },
26636 - { 0x0000997c, 0x00000000 },
26637 - { 0x00009980, 0x00000000 },
26638 - { 0x00009984, 0x00000000 },
26639 - { 0x00009988, 0x00000000 },
26640 - { 0x0000998c, 0x00000000 },
26641 - { 0x00009990, 0x00000000 },
26642 - { 0x00009994, 0x00000000 },
26643 - { 0x00009998, 0x00000000 },
26644 - { 0x0000999c, 0x00000000 },
26645 - { 0x000099a0, 0x00000000 },
26646 - { 0x000099a4, 0x00000001 },
26647 - { 0x000099a8, 0x201fff00 },
26648 - { 0x000099ac, 0x006f00c4 },
26649 - { 0x000099b0, 0x03051000 },
26650 - { 0x000099b4, 0x00000820 },
26651 - { 0x000099dc, 0x00000000 },
26652 - { 0x000099e0, 0x00000000 },
26653 - { 0x000099e4, 0xaaaaaaaa },
26654 - { 0x000099e8, 0x3c466478 },
26655 - { 0x000099ec, 0x0cc80caa },
26656 - { 0x000099fc, 0x00001042 },
26657 - { 0x0000a210, 0x4080a333 },
26658 - { 0x0000a214, 0x40206c10 },
26659 - { 0x0000a218, 0x009c4060 },
26660 - { 0x0000a220, 0x01834061 },
26661 - { 0x0000a224, 0x00000400 },
26662 - { 0x0000a228, 0x000003b5 },
26663 - { 0x0000a22c, 0x23277200 },
26664 - { 0x0000a234, 0x20202020 },
26665 - { 0x0000a238, 0x20202020 },
26666 - { 0x0000a23c, 0x13c889af },
26667 - { 0x0000a240, 0x38490a20 },
26668 - { 0x0000a244, 0x00007bb6 },
26669 - { 0x0000a248, 0x0fff3ffc },
26670 - { 0x0000a24c, 0x00000001 },
26671 - { 0x0000a250, 0x001da000 },
26672 - { 0x0000a254, 0x00000000 },
26673 - { 0x0000a258, 0x0cdbd380 },
26674 - { 0x0000a25c, 0x0f0f0f01 },
26675 - { 0x0000a260, 0xdfa91f01 },
26676 - { 0x0000a268, 0x00000000 },
26677 - { 0x0000a26c, 0x0ebae9c6 },
26678 - { 0x0000b26c, 0x0ebae9c6 },
26679 - { 0x0000d270, 0x00820820 },
26680 - { 0x0000a278, 0x1ce739ce },
26681 - { 0x0000a27c, 0x050701ce },
26682 - { 0x0000a358, 0x7999aa0f },
26683 - { 0x0000d35c, 0x07ffffef },
26684 - { 0x0000d360, 0x0fffffe7 },
26685 - { 0x0000d364, 0x17ffffe5 },
26686 - { 0x0000d368, 0x1fffffe4 },
26687 - { 0x0000d36c, 0x37ffffe3 },
26688 - { 0x0000d370, 0x3fffffe3 },
26689 - { 0x0000d374, 0x57ffffe3 },
26690 - { 0x0000d378, 0x5fffffe2 },
26691 - { 0x0000d37c, 0x7fffffe2 },
26692 - { 0x0000d380, 0x7f3c7bba },
26693 - { 0x0000d384, 0xf3307ff0 },
26694 - { 0x0000a388, 0x0c000000 },
26695 - { 0x0000a38c, 0x20202020 },
26696 - { 0x0000a390, 0x20202020 },
26697 - { 0x0000a394, 0x1ce739ce },
26698 - { 0x0000a398, 0x000001ce },
26699 - { 0x0000a39c, 0x00000001 },
26700 - { 0x0000a3a0, 0x00000000 },
26701 - { 0x0000a3a4, 0x00000000 },
26702 - { 0x0000a3a8, 0x00000000 },
26703 - { 0x0000a3ac, 0x00000000 },
26704 - { 0x0000a3b0, 0x00000000 },
26705 - { 0x0000a3b4, 0x00000000 },
26706 - { 0x0000a3b8, 0x00000000 },
26707 - { 0x0000a3bc, 0x00000000 },
26708 - { 0x0000a3c0, 0x00000000 },
26709 - { 0x0000a3c4, 0x00000000 },
26710 - { 0x0000a3c8, 0x00000246 },
26711 - { 0x0000a3cc, 0x20202020 },
26712 - { 0x0000a3d0, 0x20202020 },
26713 - { 0x0000a3d4, 0x20202020 },
26714 - { 0x0000a3dc, 0x1ce739ce },
26715 - { 0x0000a3e0, 0x000001ce },
26716 - { 0x0000a3e4, 0x00000000 },
26717 - { 0x0000a3e8, 0x18c43433 },
26718 - { 0x0000a3ec, 0x00f38081 },
26719 - { 0x00007800, 0x00040000 },
26720 - { 0x00007804, 0xdb005012 },
26721 - { 0x00007808, 0x04924914 },
26722 - { 0x0000780c, 0x21084210 },
26723 - { 0x00007810, 0x6d801300 },
26724 - { 0x00007814, 0x0019beff },
26725 - { 0x00007818, 0x07e40000 },
26726 - { 0x0000781c, 0x00492000 },
26727 - { 0x00007820, 0x92492480 },
26728 - { 0x00007824, 0x00040000 },
26729 - { 0x00007828, 0xdb005012 },
26730 - { 0x0000782c, 0x04924914 },
26731 - { 0x00007830, 0x21084210 },
26732 - { 0x00007834, 0x6d801300 },
26733 - { 0x00007838, 0x0019beff },
26734 - { 0x0000783c, 0x07e40000 },
26735 - { 0x00007840, 0x00492000 },
26736 - { 0x00007844, 0x92492480 },
26737 - { 0x00007848, 0x00120000 },
26738 - { 0x00007850, 0x54214514 },
26739 - { 0x00007858, 0x92592692 },
26740 - { 0x00007860, 0x52802000 },
26741 - { 0x00007864, 0x0a8e370e },
26742 - { 0x00007868, 0xc0102850 },
26743 - { 0x0000786c, 0x812d4000 },
26744 - { 0x00007874, 0x001b6db0 },
26745 - { 0x00007878, 0x00376b63 },
26746 - { 0x0000787c, 0x06db6db6 },
26747 - { 0x00007880, 0x006d8000 },
26748 - { 0x00007884, 0xffeffffe },
26749 - { 0x00007888, 0xffeffffe },
26750 - { 0x00007890, 0x00060aeb },
26751 - { 0x00007894, 0x5a108000 },
26752 - { 0x00007898, 0x2a850160 },
26753 -};
26754 -
26755 -/* XXX 9280 2 */
26756 -static const u32 ar9280Modes_9280_2[][6] = {
26757 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
26758 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
26759 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
26760 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
26761 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
26762 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
26763 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
26764 - { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
26765 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
26766 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
26767 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
26768 - { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
26769 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
26770 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
26771 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
26772 - { 0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e, 0x206a012e },
26773 - { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
26774 - { 0x00009850, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
26775 - { 0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
26776 - { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
26777 - { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
26778 - { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
26779 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
26780 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
26781 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
26782 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000268, 0x0000000b, 0x00000016 },
26783 - { 0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
26784 - { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010 },
26785 - { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
26786 - { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
26787 - { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
26788 - { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
26789 - { 0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c },
26790 - { 0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00, 0x00000c00 },
26791 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
26792 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
26793 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
26794 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
26795 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
26796 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
26797 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
26798 - { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 },
26799 - { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
26800 - { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
26801 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
26802 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
26803 - { 0x0000a23c, 0x13c88000, 0x13c88000, 0x13c88001, 0x13c88000, 0x13c88000 },
26804 - { 0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000, 0x0004a000 },
26805 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
26806 - { 0x0000a388, 0x0c000000, 0x0c000000, 0x08000000, 0x0c000000, 0x0c000000 },
26807 - { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
26808 - { 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 },
26809 -};
26810 -
26811 -static const u32 ar9280Common_9280_2[][2] = {
26812 - { 0x0000000c, 0x00000000 },
26813 - { 0x00000030, 0x00020015 },
26814 - { 0x00000034, 0x00000005 },
26815 - { 0x00000040, 0x00000000 },
26816 - { 0x00000044, 0x00000008 },
26817 - { 0x00000048, 0x00000008 },
26818 - { 0x0000004c, 0x00000010 },
26819 - { 0x00000050, 0x00000000 },
26820 - { 0x00000054, 0x0000001f },
26821 - { 0x00000800, 0x00000000 },
26822 - { 0x00000804, 0x00000000 },
26823 - { 0x00000808, 0x00000000 },
26824 - { 0x0000080c, 0x00000000 },
26825 - { 0x00000810, 0x00000000 },
26826 - { 0x00000814, 0x00000000 },
26827 - { 0x00000818, 0x00000000 },
26828 - { 0x0000081c, 0x00000000 },
26829 - { 0x00000820, 0x00000000 },
26830 - { 0x00000824, 0x00000000 },
26831 - { 0x00001040, 0x002ffc0f },
26832 - { 0x00001044, 0x002ffc0f },
26833 - { 0x00001048, 0x002ffc0f },
26834 - { 0x0000104c, 0x002ffc0f },
26835 - { 0x00001050, 0x002ffc0f },
26836 - { 0x00001054, 0x002ffc0f },
26837 - { 0x00001058, 0x002ffc0f },
26838 - { 0x0000105c, 0x002ffc0f },
26839 - { 0x00001060, 0x002ffc0f },
26840 - { 0x00001064, 0x002ffc0f },
26841 - { 0x00001230, 0x00000000 },
26842 - { 0x00001270, 0x00000000 },
26843 - { 0x00001038, 0x00000000 },
26844 - { 0x00001078, 0x00000000 },
26845 - { 0x000010b8, 0x00000000 },
26846 - { 0x000010f8, 0x00000000 },
26847 - { 0x00001138, 0x00000000 },
26848 - { 0x00001178, 0x00000000 },
26849 - { 0x000011b8, 0x00000000 },
26850 - { 0x000011f8, 0x00000000 },
26851 - { 0x00001238, 0x00000000 },
26852 - { 0x00001278, 0x00000000 },
26853 - { 0x000012b8, 0x00000000 },
26854 - { 0x000012f8, 0x00000000 },
26855 - { 0x00001338, 0x00000000 },
26856 - { 0x00001378, 0x00000000 },
26857 - { 0x000013b8, 0x00000000 },
26858 - { 0x000013f8, 0x00000000 },
26859 - { 0x00001438, 0x00000000 },
26860 - { 0x00001478, 0x00000000 },
26861 - { 0x000014b8, 0x00000000 },
26862 - { 0x000014f8, 0x00000000 },
26863 - { 0x00001538, 0x00000000 },
26864 - { 0x00001578, 0x00000000 },
26865 - { 0x000015b8, 0x00000000 },
26866 - { 0x000015f8, 0x00000000 },
26867 - { 0x00001638, 0x00000000 },
26868 - { 0x00001678, 0x00000000 },
26869 - { 0x000016b8, 0x00000000 },
26870 - { 0x000016f8, 0x00000000 },
26871 - { 0x00001738, 0x00000000 },
26872 - { 0x00001778, 0x00000000 },
26873 - { 0x000017b8, 0x00000000 },
26874 - { 0x000017f8, 0x00000000 },
26875 - { 0x0000103c, 0x00000000 },
26876 - { 0x0000107c, 0x00000000 },
26877 - { 0x000010bc, 0x00000000 },
26878 - { 0x000010fc, 0x00000000 },
26879 - { 0x0000113c, 0x00000000 },
26880 - { 0x0000117c, 0x00000000 },
26881 - { 0x000011bc, 0x00000000 },
26882 - { 0x000011fc, 0x00000000 },
26883 - { 0x0000123c, 0x00000000 },
26884 - { 0x0000127c, 0x00000000 },
26885 - { 0x000012bc, 0x00000000 },
26886 - { 0x000012fc, 0x00000000 },
26887 - { 0x0000133c, 0x00000000 },
26888 - { 0x0000137c, 0x00000000 },
26889 - { 0x000013bc, 0x00000000 },
26890 - { 0x000013fc, 0x00000000 },
26891 - { 0x0000143c, 0x00000000 },
26892 - { 0x0000147c, 0x00000000 },
26893 - { 0x00004030, 0x00000002 },
26894 - { 0x0000403c, 0x00000002 },
26895 - { 0x00004024, 0x0000001f },
26896 - { 0x00004060, 0x00000000 },
26897 - { 0x00004064, 0x00000000 },
26898 - { 0x00007010, 0x00000033 },
26899 - { 0x00007034, 0x00000002 },
26900 - { 0x00007038, 0x000004c2 },
26901 - { 0x00008004, 0x00000000 },
26902 - { 0x00008008, 0x00000000 },
26903 - { 0x0000800c, 0x00000000 },
26904 - { 0x00008018, 0x00000700 },
26905 - { 0x00008020, 0x00000000 },
26906 - { 0x00008038, 0x00000000 },
26907 - { 0x0000803c, 0x00000000 },
26908 - { 0x00008048, 0x40000000 },
26909 - { 0x00008054, 0x00000000 },
26910 - { 0x00008058, 0x00000000 },
26911 - { 0x0000805c, 0x000fc78f },
26912 - { 0x00008060, 0x0000000f },
26913 - { 0x00008064, 0x00000000 },
26914 - { 0x00008070, 0x00000000 },
26915 - { 0x000080c0, 0x2a80001a },
26916 - { 0x000080c4, 0x05dc01e0 },
26917 - { 0x000080c8, 0x1f402710 },
26918 - { 0x000080cc, 0x01f40000 },
26919 - { 0x000080d0, 0x00001e00 },
26920 - { 0x000080d4, 0x00000000 },
26921 - { 0x000080d8, 0x00400000 },
26922 - { 0x000080e0, 0xffffffff },
26923 - { 0x000080e4, 0x0000ffff },
26924 - { 0x000080e8, 0x003f3f3f },
26925 - { 0x000080ec, 0x00000000 },
26926 - { 0x000080f0, 0x00000000 },
26927 - { 0x000080f4, 0x00000000 },
26928 - { 0x000080f8, 0x00000000 },
26929 - { 0x000080fc, 0x00020000 },
26930 - { 0x00008100, 0x00020000 },
26931 - { 0x00008104, 0x00000001 },
26932 - { 0x00008108, 0x00000052 },
26933 - { 0x0000810c, 0x00000000 },
26934 - { 0x00008110, 0x00000168 },
26935 - { 0x00008118, 0x000100aa },
26936 - { 0x0000811c, 0x00003210 },
26937 - { 0x00008124, 0x00000000 },
26938 - { 0x00008128, 0x00000000 },
26939 - { 0x0000812c, 0x00000000 },
26940 - { 0x00008130, 0x00000000 },
26941 - { 0x00008134, 0x00000000 },
26942 - { 0x00008138, 0x00000000 },
26943 - { 0x0000813c, 0x00000000 },
26944 - { 0x00008144, 0xffffffff },
26945 - { 0x00008168, 0x00000000 },
26946 - { 0x0000816c, 0x00000000 },
26947 - { 0x00008170, 0x32143320 },
26948 - { 0x00008174, 0xfaa4fa50 },
26949 - { 0x00008178, 0x00000100 },
26950 - { 0x0000817c, 0x00000000 },
26951 - { 0x000081c0, 0x00000000 },
26952 - { 0x000081ec, 0x00000000 },
26953 - { 0x000081f0, 0x00000000 },
26954 - { 0x000081f4, 0x00000000 },
26955 - { 0x000081f8, 0x00000000 },
26956 - { 0x000081fc, 0x00000000 },
26957 - { 0x00008200, 0x00000000 },
26958 - { 0x00008204, 0x00000000 },
26959 - { 0x00008208, 0x00000000 },
26960 - { 0x0000820c, 0x00000000 },
26961 - { 0x00008210, 0x00000000 },
26962 - { 0x00008214, 0x00000000 },
26963 - { 0x00008218, 0x00000000 },
26964 - { 0x0000821c, 0x00000000 },
26965 - { 0x00008220, 0x00000000 },
26966 - { 0x00008224, 0x00000000 },
26967 - { 0x00008228, 0x00000000 },
26968 - { 0x0000822c, 0x00000000 },
26969 - { 0x00008230, 0x00000000 },
26970 - { 0x00008234, 0x00000000 },
26971 - { 0x00008238, 0x00000000 },
26972 - { 0x0000823c, 0x00000000 },
26973 - { 0x00008240, 0x00100000 },
26974 - { 0x00008244, 0x0010f400 },
26975 - { 0x00008248, 0x00000100 },
26976 - { 0x0000824c, 0x0001e800 },
26977 - { 0x00008250, 0x00000000 },
26978 - { 0x00008254, 0x00000000 },
26979 - { 0x00008258, 0x00000000 },
26980 - { 0x0000825c, 0x400000ff },
26981 - { 0x00008260, 0x00080922 },
26982 - { 0x00008264, 0xa8a00010 },
26983 - { 0x00008270, 0x00000000 },
26984 - { 0x00008274, 0x40000000 },
26985 - { 0x00008278, 0x003e4180 },
26986 - { 0x0000827c, 0x00000000 },
26987 - { 0x00008284, 0x0000002c },
26988 - { 0x00008288, 0x0000002c },
26989 - { 0x0000828c, 0x00000000 },
26990 - { 0x00008294, 0x00000000 },
26991 - { 0x00008298, 0x00000000 },
26992 - { 0x0000829c, 0x00000000 },
26993 - { 0x00008300, 0x00000040 },
26994 - { 0x00008314, 0x00000000 },
26995 - { 0x00008328, 0x00000000 },
26996 - { 0x0000832c, 0x00000007 },
26997 - { 0x00008330, 0x00000302 },
26998 - { 0x00008334, 0x00000e00 },
26999 - { 0x00008338, 0x00ff0000 },
27000 - { 0x0000833c, 0x00000000 },
27001 - { 0x00008340, 0x000107ff },
27002 - { 0x00008344, 0x00481043 },
27003 - { 0x00009808, 0x00000000 },
27004 - { 0x0000980c, 0xafa68e30 },
27005 - { 0x00009810, 0xfd14e000 },
27006 - { 0x00009814, 0x9c0a9f6b },
27007 - { 0x0000981c, 0x00000000 },
27008 - { 0x0000982c, 0x0000a000 },
27009 - { 0x00009830, 0x00000000 },
27010 - { 0x0000983c, 0x00200400 },
27011 - { 0x0000984c, 0x0040233c },
27012 - { 0x0000a84c, 0x0040233c },
27013 - { 0x00009854, 0x00000044 },
27014 - { 0x00009900, 0x00000000 },
27015 - { 0x00009904, 0x00000000 },
27016 - { 0x00009908, 0x00000000 },
27017 - { 0x0000990c, 0x00000000 },
27018 - { 0x00009910, 0x01002310 },
27019 - { 0x0000991c, 0x10000fff },
27020 - { 0x00009920, 0x04900000 },
27021 - { 0x0000a920, 0x04900000 },
27022 - { 0x00009928, 0x00000001 },
27023 - { 0x0000992c, 0x00000004 },
27024 - { 0x00009934, 0x1e1f2022 },
27025 - { 0x00009938, 0x0a0b0c0d },
27026 - { 0x0000993c, 0x00000000 },
27027 - { 0x00009948, 0x9280c00a },
27028 - { 0x0000994c, 0x00020028 },
27029 - { 0x00009954, 0x5f3ca3de },
27030 - { 0x00009958, 0x2108ecff },
27031 - { 0x00009940, 0x14750604 },
27032 - { 0x0000c95c, 0x004b6a8e },
27033 - { 0x00009970, 0x190fb515 },
27034 - { 0x00009974, 0x00000000 },
27035 - { 0x00009978, 0x00000001 },
27036 - { 0x0000997c, 0x00000000 },
27037 - { 0x00009980, 0x00000000 },
27038 - { 0x00009984, 0x00000000 },
27039 - { 0x00009988, 0x00000000 },
27040 - { 0x0000998c, 0x00000000 },
27041 - { 0x00009990, 0x00000000 },
27042 - { 0x00009994, 0x00000000 },
27043 - { 0x00009998, 0x00000000 },
27044 - { 0x0000999c, 0x00000000 },
27045 - { 0x000099a0, 0x00000000 },
27046 - { 0x000099a4, 0x00000001 },
27047 - { 0x000099a8, 0x201fff00 },
27048 - { 0x000099ac, 0x006f0000 },
27049 - { 0x000099b0, 0x03051000 },
27050 - { 0x000099b4, 0x00000820 },
27051 - { 0x000099dc, 0x00000000 },
27052 - { 0x000099e0, 0x00000000 },
27053 - { 0x000099e4, 0xaaaaaaaa },
27054 - { 0x000099e8, 0x3c466478 },
27055 - { 0x000099ec, 0x0cc80caa },
27056 - { 0x000099f0, 0x00000000 },
27057 - { 0x000099fc, 0x00001042 },
27058 - { 0x0000a208, 0x803e4788 },
27059 - { 0x0000a210, 0x4080a333 },
27060 - { 0x0000a214, 0x40206c10 },
27061 - { 0x0000a218, 0x009c4060 },
27062 - { 0x0000a220, 0x01834061 },
27063 - { 0x0000a224, 0x00000400 },
27064 - { 0x0000a228, 0x000003b5 },
27065 - { 0x0000a22c, 0x233f7180 },
27066 - { 0x0000a234, 0x20202020 },
27067 - { 0x0000a238, 0x20202020 },
27068 - { 0x0000a240, 0x38490a20 },
27069 - { 0x0000a244, 0x00007bb6 },
27070 - { 0x0000a248, 0x0fff3ffc },
27071 - { 0x0000a24c, 0x00000000 },
27072 - { 0x0000a254, 0x00000000 },
27073 - { 0x0000a258, 0x0cdbd380 },
27074 - { 0x0000a25c, 0x0f0f0f01 },
27075 - { 0x0000a260, 0xdfa91f01 },
27076 - { 0x0000a268, 0x00000000 },
27077 - { 0x0000a26c, 0x0e79e5c6 },
27078 - { 0x0000b26c, 0x0e79e5c6 },
27079 - { 0x0000d270, 0x00820820 },
27080 - { 0x0000a278, 0x1ce739ce },
27081 - { 0x0000d35c, 0x07ffffef },
27082 - { 0x0000d360, 0x0fffffe7 },
27083 - { 0x0000d364, 0x17ffffe5 },
27084 - { 0x0000d368, 0x1fffffe4 },
27085 - { 0x0000d36c, 0x37ffffe3 },
27086 - { 0x0000d370, 0x3fffffe3 },
27087 - { 0x0000d374, 0x57ffffe3 },
27088 - { 0x0000d378, 0x5fffffe2 },
27089 - { 0x0000d37c, 0x7fffffe2 },
27090 - { 0x0000d380, 0x7f3c7bba },
27091 - { 0x0000d384, 0xf3307ff0 },
27092 - { 0x0000a38c, 0x20202020 },
27093 - { 0x0000a390, 0x20202020 },
27094 - { 0x0000a394, 0x1ce739ce },
27095 - { 0x0000a398, 0x000001ce },
27096 - { 0x0000a39c, 0x00000001 },
27097 - { 0x0000a3a0, 0x00000000 },
27098 - { 0x0000a3a4, 0x00000000 },
27099 - { 0x0000a3a8, 0x00000000 },
27100 - { 0x0000a3ac, 0x00000000 },
27101 - { 0x0000a3b0, 0x00000000 },
27102 - { 0x0000a3b4, 0x00000000 },
27103 - { 0x0000a3b8, 0x00000000 },
27104 - { 0x0000a3bc, 0x00000000 },
27105 - { 0x0000a3c0, 0x00000000 },
27106 - { 0x0000a3c4, 0x00000000 },
27107 - { 0x0000a3c8, 0x00000246 },
27108 - { 0x0000a3cc, 0x20202020 },
27109 - { 0x0000a3d0, 0x20202020 },
27110 - { 0x0000a3d4, 0x20202020 },
27111 - { 0x0000a3dc, 0x1ce739ce },
27112 - { 0x0000a3e0, 0x000001ce },
27113 - { 0x0000a3e4, 0x00000000 },
27114 - { 0x0000a3e8, 0x18c43433 },
27115 - { 0x0000a3ec, 0x00f70081 },
27116 - { 0x00007800, 0x00040000 },
27117 - { 0x00007804, 0xdb005012 },
27118 - { 0x00007808, 0x04924914 },
27119 - { 0x0000780c, 0x21084210 },
27120 - { 0x00007810, 0x6d801300 },
27121 - { 0x00007818, 0x07e41000 },
27122 - { 0x00007824, 0x00040000 },
27123 - { 0x00007828, 0xdb005012 },
27124 - { 0x0000782c, 0x04924914 },
27125 - { 0x00007830, 0x21084210 },
27126 - { 0x00007834, 0x6d801300 },
27127 - { 0x0000783c, 0x07e40000 },
27128 - { 0x00007848, 0x00100000 },
27129 - { 0x0000784c, 0x773f0567 },
27130 - { 0x00007850, 0x54214514 },
27131 - { 0x00007854, 0x12035828 },
27132 - { 0x00007858, 0x9259269a },
27133 - { 0x00007860, 0x52802000 },
27134 - { 0x00007864, 0x0a8e370e },
27135 - { 0x00007868, 0xc0102850 },
27136 - { 0x0000786c, 0x812d4000 },
27137 - { 0x00007870, 0x807ec400 },
27138 - { 0x00007874, 0x001b6db0 },
27139 - { 0x00007878, 0x00376b63 },
27140 - { 0x0000787c, 0x06db6db6 },
27141 - { 0x00007880, 0x006d8000 },
27142 - { 0x00007884, 0xffeffffe },
27143 - { 0x00007888, 0xffeffffe },
27144 - { 0x0000788c, 0x00010000 },
27145 - { 0x00007890, 0x02060aeb },
27146 - { 0x00007898, 0x2a850160 },
27147 -};
27148 -
27149 -static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
27150 - { 0x00001030, 0x00000268, 0x000004d0 },
27151 - { 0x00001070, 0x0000018c, 0x00000318 },
27152 - { 0x000010b0, 0x00000fd0, 0x00001fa0 },
27153 - { 0x00008014, 0x044c044c, 0x08980898 },
27154 - { 0x0000801c, 0x148ec02b, 0x148ec057 },
27155 - { 0x00008318, 0x000044c0, 0x00008980 },
27156 - { 0x00009820, 0x02020200, 0x02020200 },
27157 - { 0x00009824, 0x01000f0f, 0x01000f0f },
27158 - { 0x00009828, 0x0b020001, 0x0b020001 },
27159 - { 0x00009834, 0x00000f0f, 0x00000f0f },
27160 - { 0x00009844, 0x03721821, 0x03721821 },
27161 - { 0x00009914, 0x00000898, 0x00001130 },
27162 - { 0x00009918, 0x0000000b, 0x00000016 },
27163 -};
27164 -
27165 -static const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = {
27166 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
27167 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
27168 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
27169 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
27170 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
27171 - { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
27172 - { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
27173 - { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
27174 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
27175 - { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
27176 - { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
27177 - { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
27178 - { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
27179 - { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
27180 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
27181 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
27182 - { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
27183 - { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
27184 - { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
27185 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
27186 - { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
27187 - { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
27188 - { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
27189 - { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
27190 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
27191 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
27192 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
27193 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
27194 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
27195 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
27196 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
27197 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
27198 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
27199 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
27200 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
27201 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
27202 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
27203 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
27204 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
27205 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
27206 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
27207 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
27208 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
27209 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
27210 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
27211 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
27212 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
27213 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
27214 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b10, 0x00008b10, 0x00008b10 },
27215 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b14, 0x00008b14, 0x00008b14 },
27216 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b01, 0x00008b01, 0x00008b01 },
27217 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b05, 0x00008b05, 0x00008b05 },
27218 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b09, 0x00008b09, 0x00008b09 },
27219 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008b0d, 0x00008b0d, 0x00008b0d },
27220 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008b11, 0x00008b11, 0x00008b11 },
27221 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008b15, 0x00008b15, 0x00008b15 },
27222 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008b02, 0x00008b02, 0x00008b02 },
27223 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008b06, 0x00008b06, 0x00008b06 },
27224 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x00008b0a, 0x00008b0a, 0x00008b0a },
27225 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00008b0e, 0x00008b0e, 0x00008b0e },
27226 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00008b12, 0x00008b12, 0x00008b12 },
27227 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00008b16, 0x00008b16, 0x00008b16 },
27228 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00008b03, 0x00008b03, 0x00008b03 },
27229 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x00008b07, 0x00008b07, 0x00008b07 },
27230 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x00008b0b, 0x00008b0b, 0x00008b0b },
27231 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x00008b0f, 0x00008b0f, 0x00008b0f },
27232 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00008b13, 0x00008b13, 0x00008b13 },
27233 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00008b17, 0x00008b17, 0x00008b17 },
27234 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00008b23, 0x00008b23, 0x00008b23 },
27235 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x00008b27, 0x00008b27, 0x00008b27 },
27236 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00008b2b, 0x00008b2b, 0x00008b2b },
27237 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x00008b2f, 0x00008b2f, 0x00008b2f },
27238 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x00008b33, 0x00008b33, 0x00008b33 },
27239 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x00008b37, 0x00008b37, 0x00008b37 },
27240 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x00008b43, 0x00008b43, 0x00008b43 },
27241 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x00008b47, 0x00008b47, 0x00008b47 },
27242 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00008b4b, 0x00008b4b, 0x00008b4b },
27243 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00008b4f, 0x00008b4f, 0x00008b4f },
27244 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00008b53, 0x00008b53, 0x00008b53 },
27245 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00008b57, 0x00008b57, 0x00008b57 },
27246 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27247 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27248 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27249 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27250 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27251 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27252 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27253 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27254 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27255 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27256 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27257 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27258 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27259 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27260 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27261 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27262 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27263 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27264 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27265 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27266 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27267 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27268 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27269 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27270 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27271 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27272 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27273 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27274 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27275 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27276 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27277 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27278 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27279 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27280 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27281 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27282 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27283 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27284 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27285 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27286 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27287 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27288 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27289 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27290 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27291 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27292 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27293 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27294 - { 0x00009848, 0x00001066, 0x00001066, 0x00001050, 0x00001050, 0x00001050 },
27295 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001050, 0x00001050, 0x00001050 },
27296 -};
27297 -
27298 -static const u32 ar9280Modes_original_rxgain_9280_2[][6] = {
27299 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
27300 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
27301 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
27302 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
27303 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
27304 - { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
27305 - { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
27306 - { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
27307 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
27308 - { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
27309 - { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
27310 - { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
27311 - { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
27312 - { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
27313 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
27314 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
27315 - { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
27316 - { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
27317 - { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
27318 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
27319 - { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
27320 - { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
27321 - { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
27322 - { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
27323 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
27324 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
27325 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
27326 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
27327 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
27328 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
27329 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
27330 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
27331 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
27332 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
27333 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
27334 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
27335 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
27336 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
27337 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
27338 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
27339 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
27340 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
27341 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
27342 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
27343 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
27344 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
27345 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
27346 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
27347 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
27348 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
27349 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
27350 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
27351 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
27352 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
27353 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
27354 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
27355 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
27356 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
27357 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c },
27358 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 },
27359 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 },
27360 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 },
27361 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 },
27362 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 },
27363 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 },
27364 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 },
27365 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 },
27366 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 },
27367 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 },
27368 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 },
27369 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 },
27370 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c },
27371 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 },
27372 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 },
27373 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 },
27374 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 },
27375 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 },
27376 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 },
27377 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 },
27378 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 },
27379 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad },
27380 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 },
27381 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 },
27382 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 },
27383 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 },
27384 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 },
27385 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 },
27386 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 },
27387 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 },
27388 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 },
27389 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca },
27390 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce },
27391 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 },
27392 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 },
27393 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 },
27394 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 },
27395 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb },
27396 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf },
27397 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 },
27398 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db },
27399 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db },
27400 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db },
27401 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27402 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27403 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27404 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27405 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27406 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27407 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27408 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27409 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27410 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27411 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27412 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27413 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27414 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27415 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27416 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27417 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27418 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27419 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27420 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27421 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27422 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27423 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27424 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27425 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27426 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27427 - { 0x00009848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 },
27428 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 },
27429 -};
27430 -
27431 -static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
27432 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
27433 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
27434 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
27435 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
27436 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
27437 - { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
27438 - { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
27439 - { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
27440 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
27441 - { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
27442 - { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
27443 - { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
27444 - { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
27445 - { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
27446 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
27447 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
27448 - { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
27449 - { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
27450 - { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
27451 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
27452 - { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
27453 - { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
27454 - { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
27455 - { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
27456 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
27457 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
27458 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
27459 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
27460 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
27461 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
27462 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
27463 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
27464 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
27465 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
27466 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
27467 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
27468 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
27469 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
27470 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
27471 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
27472 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
27473 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
27474 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
27475 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
27476 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
27477 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
27478 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
27479 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
27480 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
27481 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
27482 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
27483 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
27484 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
27485 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
27486 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
27487 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
27488 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
27489 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
27490 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x00009310, 0x00009310, 0x00009310 },
27491 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009314, 0x00009314, 0x00009314 },
27492 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009320, 0x00009320, 0x00009320 },
27493 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009324, 0x00009324, 0x00009324 },
27494 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009328, 0x00009328, 0x00009328 },
27495 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x0000932c, 0x0000932c, 0x0000932c },
27496 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x00009330, 0x00009330, 0x00009330 },
27497 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x00009334, 0x00009334, 0x00009334 },
27498 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009321, 0x00009321, 0x00009321 },
27499 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009325, 0x00009325, 0x00009325 },
27500 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009329, 0x00009329, 0x00009329 },
27501 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x0000932d, 0x0000932d, 0x0000932d },
27502 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009331, 0x00009331, 0x00009331 },
27503 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x00009335, 0x00009335, 0x00009335 },
27504 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x00009322, 0x00009322, 0x00009322 },
27505 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x00009326, 0x00009326, 0x00009326 },
27506 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x0000932a, 0x0000932a, 0x0000932a },
27507 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x0000932e, 0x0000932e, 0x0000932e },
27508 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00009332, 0x00009332, 0x00009332 },
27509 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00009336, 0x00009336, 0x00009336 },
27510 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00009323, 0x00009323, 0x00009323 },
27511 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00009327, 0x00009327, 0x00009327 },
27512 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x0000932b, 0x0000932b, 0x0000932b },
27513 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x0000932f, 0x0000932f, 0x0000932f },
27514 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00009333, 0x00009333, 0x00009333 },
27515 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00009337, 0x00009337, 0x00009337 },
27516 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00009343, 0x00009343, 0x00009343 },
27517 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00009347, 0x00009347, 0x00009347 },
27518 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x0000934b, 0x0000934b, 0x0000934b },
27519 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x0000934f, 0x0000934f, 0x0000934f },
27520 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00009353, 0x00009353, 0x00009353 },
27521 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00009357, 0x00009357, 0x00009357 },
27522 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x0000935b, 0x0000935b, 0x0000935b },
27523 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x0000935b, 0x0000935b, 0x0000935b },
27524 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x0000935b, 0x0000935b, 0x0000935b },
27525 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x0000935b, 0x0000935b, 0x0000935b },
27526 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x0000935b, 0x0000935b, 0x0000935b },
27527 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x0000935b, 0x0000935b, 0x0000935b },
27528 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x0000935b, 0x0000935b, 0x0000935b },
27529 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x0000935b, 0x0000935b, 0x0000935b },
27530 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x0000935b, 0x0000935b, 0x0000935b },
27531 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x0000935b, 0x0000935b, 0x0000935b },
27532 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x0000935b, 0x0000935b, 0x0000935b },
27533 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x0000935b, 0x0000935b, 0x0000935b },
27534 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27535 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27536 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27537 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27538 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27539 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27540 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27541 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27542 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27543 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27544 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27545 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27546 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27547 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27548 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27549 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27550 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27551 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27552 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27553 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27554 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27555 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27556 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27557 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27558 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27559 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27560 - { 0x00009848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a },
27561 - { 0x0000a848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a },
27562 -};
27563 -
27564 -static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
27565 - { 0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
27566 - { 0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce },
27567 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27568 - { 0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002, 0x00004002 },
27569 - { 0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008, 0x00007008 },
27570 - { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000c010, 0x0000c010, 0x0000c010 },
27571 - { 0x0000a310, 0x0000e012, 0x0000e012, 0x00010012, 0x00010012, 0x00010012 },
27572 - { 0x0000a314, 0x00011014, 0x00011014, 0x00013014, 0x00013014, 0x00013014 },
27573 - { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001820a, 0x0001820a, 0x0001820a },
27574 - { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001b211, 0x0001b211, 0x0001b211 },
27575 - { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
27576 - { 0x0000a324, 0x00021092, 0x00021092, 0x00022411, 0x00022411, 0x00022411 },
27577 - { 0x0000a328, 0x0002510a, 0x0002510a, 0x00025413, 0x00025413, 0x00025413 },
27578 - { 0x0000a32c, 0x0002910c, 0x0002910c, 0x00029811, 0x00029811, 0x00029811 },
27579 - { 0x0000a330, 0x0002c18b, 0x0002c18b, 0x0002c813, 0x0002c813, 0x0002c813 },
27580 - { 0x0000a334, 0x0002f1cc, 0x0002f1cc, 0x00030a14, 0x00030a14, 0x00030a14 },
27581 - { 0x0000a338, 0x000321eb, 0x000321eb, 0x00035a50, 0x00035a50, 0x00035a50 },
27582 - { 0x0000a33c, 0x000341ec, 0x000341ec, 0x00039c4c, 0x00039c4c, 0x00039c4c },
27583 - { 0x0000a340, 0x000341ec, 0x000341ec, 0x0003de8a, 0x0003de8a, 0x0003de8a },
27584 - { 0x0000a344, 0x000341ec, 0x000341ec, 0x00042e92, 0x00042e92, 0x00042e92 },
27585 - { 0x0000a348, 0x000341ec, 0x000341ec, 0x00046ed2, 0x00046ed2, 0x00046ed2 },
27586 - { 0x0000a34c, 0x000341ec, 0x000341ec, 0x0004bed5, 0x0004bed5, 0x0004bed5 },
27587 - { 0x0000a350, 0x000341ec, 0x000341ec, 0x0004ff54, 0x0004ff54, 0x0004ff54 },
27588 - { 0x0000a354, 0x000341ec, 0x000341ec, 0x00055fd5, 0x00055fd5, 0x00055fd5 },
27589 - { 0x00007814, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff },
27590 - { 0x00007838, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff },
27591 - { 0x0000781c, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 },
27592 - { 0x00007840, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 },
27593 - { 0x00007820, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
27594 - { 0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
27595 -};
27596 -
27597 -static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
27598 - { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
27599 - { 0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce },
27600 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27601 - { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
27602 - { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
27603 - { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b },
27604 - { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 },
27605 - { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 },
27606 - { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a },
27607 - { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 },
27608 - { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
27609 - { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b },
27610 - { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 },
27611 - { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 },
27612 - { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a },
27613 - { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 },
27614 - { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b },
27615 - { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 },
27616 - { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 },
27617 - { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a },
27618 - { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 },
27619 - { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a },
27620 - { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 },
27621 - { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 },
27622 - { 0x00007814, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff },
27623 - { 0x00007838, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff },
27624 - { 0x0000781c, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 },
27625 - { 0x00007840, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 },
27626 - { 0x00007820, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
27627 - { 0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
27628 -};
27629 -
27630 -static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
27631 - {0x00004040, 0x9248fd00 },
27632 - {0x00004040, 0x24924924 },
27633 - {0x00004040, 0xa8000019 },
27634 - {0x00004040, 0x13160820 },
27635 - {0x00004040, 0xe5980560 },
27636 - {0x00004040, 0xc01dcffc },
27637 - {0x00004040, 0x1aaabe41 },
27638 - {0x00004040, 0xbe105554 },
27639 - {0x00004040, 0x00043007 },
27640 - {0x00004044, 0x00000000 },
27641 -};
27642 -
27643 -static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
27644 - {0x00004040, 0x9248fd00 },
27645 - {0x00004040, 0x24924924 },
27646 - {0x00004040, 0xa8000019 },
27647 - {0x00004040, 0x13160820 },
27648 - {0x00004040, 0xe5980560 },
27649 - {0x00004040, 0xc01dcffd },
27650 - {0x00004040, 0x1aaabe41 },
27651 - {0x00004040, 0xbe105554 },
27652 - {0x00004040, 0x00043007 },
27653 - {0x00004044, 0x00000000 },
27654 -};
27655 -
27656 -/* AR9285 Revsion 10*/
27657 -static const u_int32_t ar9285Modes_9285[][6] = {
27658 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
27659 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
27660 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
27661 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
27662 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
27663 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
27664 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
27665 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
27666 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
27667 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
27668 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
27669 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
27670 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
27671 - { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
27672 - { 0x00009844, 0x0372161e, 0x0372161e, 0x03720020, 0x03720020, 0x037216a0 },
27673 - { 0x00009848, 0x00001066, 0x00001066, 0x0000004e, 0x0000004e, 0x00001059 },
27674 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
27675 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
27676 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3136605e, 0x3136605e, 0x3139605e },
27677 - { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
27678 - { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
27679 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
27680 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
27681 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
27682 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
27683 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
27684 - { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1020, 0xdfbc1020, 0xdfbc1010 },
27685 - { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27686 - { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27687 - { 0x000099b8, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c },
27688 - { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
27689 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
27690 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
27691 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
27692 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
27693 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
27694 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27695 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27696 - { 0x00009a00, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
27697 - { 0x00009a04, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
27698 - { 0x00009a08, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
27699 - { 0x00009a0c, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
27700 - { 0x00009a10, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
27701 - { 0x00009a14, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
27702 - { 0x00009a18, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
27703 - { 0x00009a1c, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
27704 - { 0x00009a20, 0x00000000, 0x00000000, 0x00068114, 0x00068114, 0x00000000 },
27705 - { 0x00009a24, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
27706 - { 0x00009a28, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
27707 - { 0x00009a2c, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
27708 - { 0x00009a30, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
27709 - { 0x00009a34, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
27710 - { 0x00009a38, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
27711 - { 0x00009a3c, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
27712 - { 0x00009a40, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
27713 - { 0x00009a44, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
27714 - { 0x00009a48, 0x00000000, 0x00000000, 0x00068284, 0x00068284, 0x00000000 },
27715 - { 0x00009a4c, 0x00000000, 0x00000000, 0x00068288, 0x00068288, 0x00000000 },
27716 - { 0x00009a50, 0x00000000, 0x00000000, 0x00068220, 0x00068220, 0x00000000 },
27717 - { 0x00009a54, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
27718 - { 0x00009a58, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
27719 - { 0x00009a5c, 0x00000000, 0x00000000, 0x00068304, 0x00068304, 0x00000000 },
27720 - { 0x00009a60, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
27721 - { 0x00009a64, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
27722 - { 0x00009a68, 0x00000000, 0x00000000, 0x00068380, 0x00068380, 0x00000000 },
27723 - { 0x00009a6c, 0x00000000, 0x00000000, 0x00068384, 0x00068384, 0x00000000 },
27724 - { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
27725 - { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
27726 - { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
27727 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
27728 - { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
27729 - { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
27730 - { 0x00009a88, 0x00000000, 0x00000000, 0x00068b04, 0x00068b04, 0x00000000 },
27731 - { 0x00009a8c, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
27732 - { 0x00009a90, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
27733 - { 0x00009a94, 0x00000000, 0x00000000, 0x00068b0c, 0x00068b0c, 0x00000000 },
27734 - { 0x00009a98, 0x00000000, 0x00000000, 0x00068b80, 0x00068b80, 0x00000000 },
27735 - { 0x00009a9c, 0x00000000, 0x00000000, 0x00068b84, 0x00068b84, 0x00000000 },
27736 - { 0x00009aa0, 0x00000000, 0x00000000, 0x00068b88, 0x00068b88, 0x00000000 },
27737 - { 0x00009aa4, 0x00000000, 0x00000000, 0x00068b8c, 0x00068b8c, 0x00000000 },
27738 - { 0x00009aa8, 0x00000000, 0x00000000, 0x000b8b90, 0x000b8b90, 0x00000000 },
27739 - { 0x00009aac, 0x00000000, 0x00000000, 0x000b8f80, 0x000b8f80, 0x00000000 },
27740 - { 0x00009ab0, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
27741 - { 0x00009ab4, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
27742 - { 0x00009ab8, 0x00000000, 0x00000000, 0x000b8f8c, 0x000b8f8c, 0x00000000 },
27743 - { 0x00009abc, 0x00000000, 0x00000000, 0x000b8f90, 0x000b8f90, 0x00000000 },
27744 - { 0x00009ac0, 0x00000000, 0x00000000, 0x000bb30c, 0x000bb30c, 0x00000000 },
27745 - { 0x00009ac4, 0x00000000, 0x00000000, 0x000bb310, 0x000bb310, 0x00000000 },
27746 - { 0x00009ac8, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
27747 - { 0x00009acc, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
27748 - { 0x00009ad0, 0x00000000, 0x00000000, 0x000bb324, 0x000bb324, 0x00000000 },
27749 - { 0x00009ad4, 0x00000000, 0x00000000, 0x000bb704, 0x000bb704, 0x00000000 },
27750 - { 0x00009ad8, 0x00000000, 0x00000000, 0x000f96a4, 0x000f96a4, 0x00000000 },
27751 - { 0x00009adc, 0x00000000, 0x00000000, 0x000f96a8, 0x000f96a8, 0x00000000 },
27752 - { 0x00009ae0, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
27753 - { 0x00009ae4, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
27754 - { 0x00009ae8, 0x00000000, 0x00000000, 0x000f9720, 0x000f9720, 0x00000000 },
27755 - { 0x00009aec, 0x00000000, 0x00000000, 0x000f9724, 0x000f9724, 0x00000000 },
27756 - { 0x00009af0, 0x00000000, 0x00000000, 0x000f9728, 0x000f9728, 0x00000000 },
27757 - { 0x00009af4, 0x00000000, 0x00000000, 0x000f972c, 0x000f972c, 0x00000000 },
27758 - { 0x00009af8, 0x00000000, 0x00000000, 0x000f97a0, 0x000f97a0, 0x00000000 },
27759 - { 0x00009afc, 0x00000000, 0x00000000, 0x000f97a4, 0x000f97a4, 0x00000000 },
27760 - { 0x00009b00, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
27761 - { 0x00009b04, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
27762 - { 0x00009b08, 0x00000000, 0x00000000, 0x000fb7b4, 0x000fb7b4, 0x00000000 },
27763 - { 0x00009b0c, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
27764 - { 0x00009b10, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
27765 - { 0x00009b14, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
27766 - { 0x00009b18, 0x00000000, 0x00000000, 0x000fb7ad, 0x000fb7ad, 0x00000000 },
27767 - { 0x00009b1c, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
27768 - { 0x00009b20, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
27769 - { 0x00009b24, 0x00000000, 0x00000000, 0x000fb7b9, 0x000fb7b9, 0x00000000 },
27770 - { 0x00009b28, 0x00000000, 0x00000000, 0x000fb7c5, 0x000fb7c5, 0x00000000 },
27771 - { 0x00009b2c, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
27772 - { 0x00009b30, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
27773 - { 0x00009b34, 0x00000000, 0x00000000, 0x000fb7d5, 0x000fb7d5, 0x00000000 },
27774 - { 0x00009b38, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
27775 - { 0x00009b3c, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
27776 - { 0x00009b40, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
27777 - { 0x00009b44, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
27778 - { 0x00009b48, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
27779 - { 0x00009b4c, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
27780 - { 0x00009b50, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
27781 - { 0x00009b54, 0x00000000, 0x00000000, 0x000fb7c7, 0x000fb7c7, 0x00000000 },
27782 - { 0x00009b58, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
27783 - { 0x00009b5c, 0x00000000, 0x00000000, 0x000fb7cf, 0x000fb7cf, 0x00000000 },
27784 - { 0x00009b60, 0x00000000, 0x00000000, 0x000fb7d7, 0x000fb7d7, 0x00000000 },
27785 - { 0x00009b64, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27786 - { 0x00009b68, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27787 - { 0x00009b6c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27788 - { 0x00009b70, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27789 - { 0x00009b74, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27790 - { 0x00009b78, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27791 - { 0x00009b7c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27792 - { 0x00009b80, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27793 - { 0x00009b84, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27794 - { 0x00009b88, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27795 - { 0x00009b8c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27796 - { 0x00009b90, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27797 - { 0x00009b94, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27798 - { 0x00009b98, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27799 - { 0x00009b9c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27800 - { 0x00009ba0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27801 - { 0x00009ba4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27802 - { 0x00009ba8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27803 - { 0x00009bac, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27804 - { 0x00009bb0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27805 - { 0x00009bb4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27806 - { 0x00009bb8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27807 - { 0x00009bbc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27808 - { 0x00009bc0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27809 - { 0x00009bc4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27810 - { 0x00009bc8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27811 - { 0x00009bcc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27812 - { 0x00009bd0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27813 - { 0x00009bd4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27814 - { 0x00009bd8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27815 - { 0x00009bdc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27816 - { 0x00009be0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27817 - { 0x00009be4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27818 - { 0x00009be8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27819 - { 0x00009bec, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27820 - { 0x00009bf0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27821 - { 0x00009bf4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27822 - { 0x00009bf8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27823 - { 0x00009bfc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27824 - { 0x0000aa00, 0x00000000, 0x00000000, 0x0006801c, 0x0006801c, 0x00000000 },
27825 - { 0x0000aa04, 0x00000000, 0x00000000, 0x00068080, 0x00068080, 0x00000000 },
27826 - { 0x0000aa08, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
27827 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
27828 - { 0x0000aa10, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
27829 - { 0x0000aa14, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
27830 - { 0x0000aa18, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
27831 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
27832 - { 0x0000aa20, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
27833 - { 0x0000aa24, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
27834 - { 0x0000aa28, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
27835 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
27836 - { 0x0000aa30, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
27837 - { 0x0000aa34, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
27838 - { 0x0000aa38, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
27839 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
27840 - { 0x0000aa40, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
27841 - { 0x0000aa44, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
27842 - { 0x0000aa48, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
27843 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
27844 - { 0x0000aa50, 0x00000000, 0x00000000, 0x000681ac, 0x000681ac, 0x00000000 },
27845 - { 0x0000aa54, 0x00000000, 0x00000000, 0x0006821c, 0x0006821c, 0x00000000 },
27846 - { 0x0000aa58, 0x00000000, 0x00000000, 0x00068224, 0x00068224, 0x00000000 },
27847 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
27848 - { 0x0000aa60, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
27849 - { 0x0000aa64, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
27850 - { 0x0000aa68, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
27851 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x00068310, 0x00068310, 0x00000000 },
27852 - { 0x0000aa70, 0x00000000, 0x00000000, 0x00068788, 0x00068788, 0x00000000 },
27853 - { 0x0000aa74, 0x00000000, 0x00000000, 0x0006878c, 0x0006878c, 0x00000000 },
27854 - { 0x0000aa78, 0x00000000, 0x00000000, 0x00068790, 0x00068790, 0x00000000 },
27855 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x00068794, 0x00068794, 0x00000000 },
27856 - { 0x0000aa80, 0x00000000, 0x00000000, 0x00068798, 0x00068798, 0x00000000 },
27857 - { 0x0000aa84, 0x00000000, 0x00000000, 0x0006879c, 0x0006879c, 0x00000000 },
27858 - { 0x0000aa88, 0x00000000, 0x00000000, 0x00068b89, 0x00068b89, 0x00000000 },
27859 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x00068b8d, 0x00068b8d, 0x00000000 },
27860 - { 0x0000aa90, 0x00000000, 0x00000000, 0x00068b91, 0x00068b91, 0x00000000 },
27861 - { 0x0000aa94, 0x00000000, 0x00000000, 0x00068b95, 0x00068b95, 0x00000000 },
27862 - { 0x0000aa98, 0x00000000, 0x00000000, 0x00068b99, 0x00068b99, 0x00000000 },
27863 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x00068ba5, 0x00068ba5, 0x00000000 },
27864 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x00068ba9, 0x00068ba9, 0x00000000 },
27865 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x00068bad, 0x00068bad, 0x00000000 },
27866 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x000b8b0c, 0x000b8b0c, 0x00000000 },
27867 - { 0x0000aaac, 0x00000000, 0x00000000, 0x000b8f10, 0x000b8f10, 0x00000000 },
27868 - { 0x0000aab0, 0x00000000, 0x00000000, 0x000b8f14, 0x000b8f14, 0x00000000 },
27869 - { 0x0000aab4, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
27870 - { 0x0000aab8, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
27871 - { 0x0000aabc, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
27872 - { 0x0000aac0, 0x00000000, 0x00000000, 0x000bb380, 0x000bb380, 0x00000000 },
27873 - { 0x0000aac4, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
27874 - { 0x0000aac8, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
27875 - { 0x0000aacc, 0x00000000, 0x00000000, 0x000bb38c, 0x000bb38c, 0x00000000 },
27876 - { 0x0000aad0, 0x00000000, 0x00000000, 0x000bb394, 0x000bb394, 0x00000000 },
27877 - { 0x0000aad4, 0x00000000, 0x00000000, 0x000bb798, 0x000bb798, 0x00000000 },
27878 - { 0x0000aad8, 0x00000000, 0x00000000, 0x000f970c, 0x000f970c, 0x00000000 },
27879 - { 0x0000aadc, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
27880 - { 0x0000aae0, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
27881 - { 0x0000aae4, 0x00000000, 0x00000000, 0x000f9718, 0x000f9718, 0x00000000 },
27882 - { 0x0000aae8, 0x00000000, 0x00000000, 0x000f9705, 0x000f9705, 0x00000000 },
27883 - { 0x0000aaec, 0x00000000, 0x00000000, 0x000f9709, 0x000f9709, 0x00000000 },
27884 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x000f970d, 0x000f970d, 0x00000000 },
27885 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x000f9711, 0x000f9711, 0x00000000 },
27886 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x000f9715, 0x000f9715, 0x00000000 },
27887 - { 0x0000aafc, 0x00000000, 0x00000000, 0x000f9719, 0x000f9719, 0x00000000 },
27888 - { 0x0000ab00, 0x00000000, 0x00000000, 0x000fb7a4, 0x000fb7a4, 0x00000000 },
27889 - { 0x0000ab04, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
27890 - { 0x0000ab08, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
27891 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
27892 - { 0x0000ab10, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
27893 - { 0x0000ab14, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
27894 - { 0x0000ab18, 0x00000000, 0x00000000, 0x000fb7bc, 0x000fb7bc, 0x00000000 },
27895 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x000fb7a1, 0x000fb7a1, 0x00000000 },
27896 - { 0x0000ab20, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
27897 - { 0x0000ab24, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
27898 - { 0x0000ab28, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
27899 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
27900 - { 0x0000ab30, 0x00000000, 0x00000000, 0x000fb7bd, 0x000fb7bd, 0x00000000 },
27901 - { 0x0000ab34, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
27902 - { 0x0000ab38, 0x00000000, 0x00000000, 0x000fb7cd, 0x000fb7cd, 0x00000000 },
27903 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
27904 - { 0x0000ab40, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
27905 - { 0x0000ab44, 0x00000000, 0x00000000, 0x000fb7c2, 0x000fb7c2, 0x00000000 },
27906 - { 0x0000ab48, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
27907 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
27908 - { 0x0000ab50, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
27909 - { 0x0000ab54, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
27910 - { 0x0000ab58, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
27911 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
27912 - { 0x0000ab60, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
27913 - { 0x0000ab64, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27914 - { 0x0000ab68, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27915 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27916 - { 0x0000ab70, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27917 - { 0x0000ab74, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27918 - { 0x0000ab78, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27919 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27920 - { 0x0000ab80, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27921 - { 0x0000ab84, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27922 - { 0x0000ab88, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27923 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27924 - { 0x0000ab90, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27925 - { 0x0000ab94, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27926 - { 0x0000ab98, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27927 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27928 - { 0x0000aba0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27929 - { 0x0000aba4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27930 - { 0x0000aba8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27931 - { 0x0000abac, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27932 - { 0x0000abb0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27933 - { 0x0000abb4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27934 - { 0x0000abb8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27935 - { 0x0000abbc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27936 - { 0x0000abc0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27937 - { 0x0000abc4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27938 - { 0x0000abc8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27939 - { 0x0000abcc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27940 - { 0x0000abd0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27941 - { 0x0000abd4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27942 - { 0x0000abd8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27943 - { 0x0000abdc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27944 - { 0x0000abe0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27945 - { 0x0000abe4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27946 - { 0x0000abe8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27947 - { 0x0000abec, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27948 - { 0x0000abf0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27949 - { 0x0000abf4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27950 - { 0x0000abf8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27951 - { 0x0000abfc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
27952 - { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
27953 - { 0x0000a20c, 0x00000014, 0x00000014, 0x00000000, 0x00000000, 0x0001f000 },
27954 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
27955 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
27956 - { 0x0000a250, 0x001ff000, 0x001ff000, 0x001ca000, 0x001ca000, 0x001da000 },
27957 - { 0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652, 0x0a82a652 },
27958 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27959 - { 0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
27960 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408, 0x00000000 },
27961 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a, 0x00000000 },
27962 - { 0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818, 0x00000000 },
27963 - { 0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858, 0x00000000 },
27964 - { 0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859, 0x00000000 },
27965 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b, 0x00000000 },
27966 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002c89a, 0x0002c89a, 0x00000000 },
27967 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002e89b, 0x0002e89b, 0x00000000 },
27968 - { 0x0000a328, 0x00000000, 0x00000000, 0x0003089c, 0x0003089c, 0x00000000 },
27969 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0003289d, 0x0003289d, 0x00000000 },
27970 - { 0x0000a330, 0x00000000, 0x00000000, 0x0003489e, 0x0003489e, 0x00000000 },
27971 - { 0x0000a334, 0x00000000, 0x00000000, 0x000388de, 0x000388de, 0x00000000 },
27972 - { 0x0000a338, 0x00000000, 0x00000000, 0x0003b91e, 0x0003b91e, 0x00000000 },
27973 - { 0x0000a33c, 0x00000000, 0x00000000, 0x0003d95e, 0x0003d95e, 0x00000000 },
27974 - { 0x0000a340, 0x00000000, 0x00000000, 0x000419df, 0x000419df, 0x00000000 },
27975 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
27976 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
27977 -};
27978 -
27979 -static const u_int32_t ar9285Common_9285[][2] = {
27980 - { 0x0000000c, 0x00000000 },
27981 - { 0x00000030, 0x00020045 },
27982 - { 0x00000034, 0x00000005 },
27983 - { 0x00000040, 0x00000000 },
27984 - { 0x00000044, 0x00000008 },
27985 - { 0x00000048, 0x00000008 },
27986 - { 0x0000004c, 0x00000010 },
27987 - { 0x00000050, 0x00000000 },
27988 - { 0x00000054, 0x0000001f },
27989 - { 0x00000800, 0x00000000 },
27990 - { 0x00000804, 0x00000000 },
27991 - { 0x00000808, 0x00000000 },
27992 - { 0x0000080c, 0x00000000 },
27993 - { 0x00000810, 0x00000000 },
27994 - { 0x00000814, 0x00000000 },
27995 - { 0x00000818, 0x00000000 },
27996 - { 0x0000081c, 0x00000000 },
27997 - { 0x00000820, 0x00000000 },
27998 - { 0x00000824, 0x00000000 },
27999 - { 0x00001040, 0x002ffc0f },
28000 - { 0x00001044, 0x002ffc0f },
28001 - { 0x00001048, 0x002ffc0f },
28002 - { 0x0000104c, 0x002ffc0f },
28003 - { 0x00001050, 0x002ffc0f },
28004 - { 0x00001054, 0x002ffc0f },
28005 - { 0x00001058, 0x002ffc0f },
28006 - { 0x0000105c, 0x002ffc0f },
28007 - { 0x00001060, 0x002ffc0f },
28008 - { 0x00001064, 0x002ffc0f },
28009 - { 0x00001230, 0x00000000 },
28010 - { 0x00001270, 0x00000000 },
28011 - { 0x00001038, 0x00000000 },
28012 - { 0x00001078, 0x00000000 },
28013 - { 0x000010b8, 0x00000000 },
28014 - { 0x000010f8, 0x00000000 },
28015 - { 0x00001138, 0x00000000 },
28016 - { 0x00001178, 0x00000000 },
28017 - { 0x000011b8, 0x00000000 },
28018 - { 0x000011f8, 0x00000000 },
28019 - { 0x00001238, 0x00000000 },
28020 - { 0x00001278, 0x00000000 },
28021 - { 0x000012b8, 0x00000000 },
28022 - { 0x000012f8, 0x00000000 },
28023 - { 0x00001338, 0x00000000 },
28024 - { 0x00001378, 0x00000000 },
28025 - { 0x000013b8, 0x00000000 },
28026 - { 0x000013f8, 0x00000000 },
28027 - { 0x00001438, 0x00000000 },
28028 - { 0x00001478, 0x00000000 },
28029 - { 0x000014b8, 0x00000000 },
28030 - { 0x000014f8, 0x00000000 },
28031 - { 0x00001538, 0x00000000 },
28032 - { 0x00001578, 0x00000000 },
28033 - { 0x000015b8, 0x00000000 },
28034 - { 0x000015f8, 0x00000000 },
28035 - { 0x00001638, 0x00000000 },
28036 - { 0x00001678, 0x00000000 },
28037 - { 0x000016b8, 0x00000000 },
28038 - { 0x000016f8, 0x00000000 },
28039 - { 0x00001738, 0x00000000 },
28040 - { 0x00001778, 0x00000000 },
28041 - { 0x000017b8, 0x00000000 },
28042 - { 0x000017f8, 0x00000000 },
28043 - { 0x0000103c, 0x00000000 },
28044 - { 0x0000107c, 0x00000000 },
28045 - { 0x000010bc, 0x00000000 },
28046 - { 0x000010fc, 0x00000000 },
28047 - { 0x0000113c, 0x00000000 },
28048 - { 0x0000117c, 0x00000000 },
28049 - { 0x000011bc, 0x00000000 },
28050 - { 0x000011fc, 0x00000000 },
28051 - { 0x0000123c, 0x00000000 },
28052 - { 0x0000127c, 0x00000000 },
28053 - { 0x000012bc, 0x00000000 },
28054 - { 0x000012fc, 0x00000000 },
28055 - { 0x0000133c, 0x00000000 },
28056 - { 0x0000137c, 0x00000000 },
28057 - { 0x000013bc, 0x00000000 },
28058 - { 0x000013fc, 0x00000000 },
28059 - { 0x0000143c, 0x00000000 },
28060 - { 0x0000147c, 0x00000000 },
28061 - { 0x00004030, 0x00000002 },
28062 - { 0x0000403c, 0x00000002 },
28063 - { 0x00004024, 0x0000001f },
28064 - { 0x00004060, 0x00000000 },
28065 - { 0x00004064, 0x00000000 },
28066 - { 0x00007010, 0x00000031 },
28067 - { 0x00007034, 0x00000002 },
28068 - { 0x00007038, 0x000004c2 },
28069 - { 0x00008004, 0x00000000 },
28070 - { 0x00008008, 0x00000000 },
28071 - { 0x0000800c, 0x00000000 },
28072 - { 0x00008018, 0x00000700 },
28073 - { 0x00008020, 0x00000000 },
28074 - { 0x00008038, 0x00000000 },
28075 - { 0x0000803c, 0x00000000 },
28076 - { 0x00008048, 0x00000000 },
28077 - { 0x00008054, 0x00000000 },
28078 - { 0x00008058, 0x00000000 },
28079 - { 0x0000805c, 0x000fc78f },
28080 - { 0x00008060, 0x0000000f },
28081 - { 0x00008064, 0x00000000 },
28082 - { 0x00008070, 0x00000000 },
28083 - { 0x000080c0, 0x2a80001a },
28084 - { 0x000080c4, 0x05dc01e0 },
28085 - { 0x000080c8, 0x1f402710 },
28086 - { 0x000080cc, 0x01f40000 },
28087 - { 0x000080d0, 0x00001e00 },
28088 - { 0x000080d4, 0x00000000 },
28089 - { 0x000080d8, 0x00400000 },
28090 - { 0x000080e0, 0xffffffff },
28091 - { 0x000080e4, 0x0000ffff },
28092 - { 0x000080e8, 0x003f3f3f },
28093 - { 0x000080ec, 0x00000000 },
28094 - { 0x000080f0, 0x00000000 },
28095 - { 0x000080f4, 0x00000000 },
28096 - { 0x000080f8, 0x00000000 },
28097 - { 0x000080fc, 0x00020000 },
28098 - { 0x00008100, 0x00020000 },
28099 - { 0x00008104, 0x00000001 },
28100 - { 0x00008108, 0x00000052 },
28101 - { 0x0000810c, 0x00000000 },
28102 - { 0x00008110, 0x00000168 },
28103 - { 0x00008118, 0x000100aa },
28104 - { 0x0000811c, 0x00003210 },
28105 - { 0x00008120, 0x08f04800 },
28106 - { 0x00008124, 0x00000000 },
28107 - { 0x00008128, 0x00000000 },
28108 - { 0x0000812c, 0x00000000 },
28109 - { 0x00008130, 0x00000000 },
28110 - { 0x00008134, 0x00000000 },
28111 - { 0x00008138, 0x00000000 },
28112 - { 0x0000813c, 0x00000000 },
28113 - { 0x00008144, 0x00000000 },
28114 - { 0x00008168, 0x00000000 },
28115 - { 0x0000816c, 0x00000000 },
28116 - { 0x00008170, 0x32143320 },
28117 - { 0x00008174, 0xfaa4fa50 },
28118 - { 0x00008178, 0x00000100 },
28119 - { 0x0000817c, 0x00000000 },
28120 - { 0x000081c0, 0x00000000 },
28121 - { 0x000081d0, 0x00003210 },
28122 - { 0x000081ec, 0x00000000 },
28123 - { 0x000081f0, 0x00000000 },
28124 - { 0x000081f4, 0x00000000 },
28125 - { 0x000081f8, 0x00000000 },
28126 - { 0x000081fc, 0x00000000 },
28127 - { 0x00008200, 0x00000000 },
28128 - { 0x00008204, 0x00000000 },
28129 - { 0x00008208, 0x00000000 },
28130 - { 0x0000820c, 0x00000000 },
28131 - { 0x00008210, 0x00000000 },
28132 - { 0x00008214, 0x00000000 },
28133 - { 0x00008218, 0x00000000 },
28134 - { 0x0000821c, 0x00000000 },
28135 - { 0x00008220, 0x00000000 },
28136 - { 0x00008224, 0x00000000 },
28137 - { 0x00008228, 0x00000000 },
28138 - { 0x0000822c, 0x00000000 },
28139 - { 0x00008230, 0x00000000 },
28140 - { 0x00008234, 0x00000000 },
28141 - { 0x00008238, 0x00000000 },
28142 - { 0x0000823c, 0x00000000 },
28143 - { 0x00008240, 0x00100000 },
28144 - { 0x00008244, 0x0010f400 },
28145 - { 0x00008248, 0x00000100 },
28146 - { 0x0000824c, 0x0001e800 },
28147 - { 0x00008250, 0x00000000 },
28148 - { 0x00008254, 0x00000000 },
28149 - { 0x00008258, 0x00000000 },
28150 - { 0x0000825c, 0x400000ff },
28151 - { 0x00008260, 0x00080922 },
28152 - { 0x00008264, 0xa8a00010 },
28153 - { 0x00008270, 0x00000000 },
28154 - { 0x00008274, 0x40000000 },
28155 - { 0x00008278, 0x003e4180 },
28156 - { 0x0000827c, 0x00000000 },
28157 - { 0x00008284, 0x0000002c },
28158 - { 0x00008288, 0x0000002c },
28159 - { 0x0000828c, 0x00000000 },
28160 - { 0x00008294, 0x00000000 },
28161 - { 0x00008298, 0x00000000 },
28162 - { 0x0000829c, 0x00000000 },
28163 - { 0x00008300, 0x00000040 },
28164 - { 0x00008314, 0x00000000 },
28165 - { 0x00008328, 0x00000000 },
28166 - { 0x0000832c, 0x00000001 },
28167 - { 0x00008330, 0x00000302 },
28168 - { 0x00008334, 0x00000e00 },
28169 - { 0x00008338, 0x00000000 },
28170 - { 0x0000833c, 0x00000000 },
28171 - { 0x00008340, 0x00010380 },
28172 - { 0x00008344, 0x00481043 },
28173 - { 0x00009808, 0x00000000 },
28174 - { 0x0000980c, 0xafe68e30 },
28175 - { 0x00009810, 0xfd14e000 },
28176 - { 0x00009814, 0x9c0a9f6b },
28177 - { 0x0000981c, 0x00000000 },
28178 - { 0x0000982c, 0x0000a000 },
28179 - { 0x00009830, 0x00000000 },
28180 - { 0x0000983c, 0x00200400 },
28181 - { 0x0000984c, 0x0040233c },
28182 - { 0x00009854, 0x00000044 },
28183 - { 0x00009900, 0x00000000 },
28184 - { 0x00009904, 0x00000000 },
28185 - { 0x00009908, 0x00000000 },
28186 - { 0x0000990c, 0x00000000 },
28187 - { 0x00009910, 0x01002310 },
28188 - { 0x0000991c, 0x10000fff },
28189 - { 0x00009920, 0x04900000 },
28190 - { 0x00009928, 0x00000001 },
28191 - { 0x0000992c, 0x00000004 },
28192 - { 0x00009934, 0x1e1f2022 },
28193 - { 0x00009938, 0x0a0b0c0d },
28194 - { 0x0000993c, 0x00000000 },
28195 - { 0x00009940, 0x14750604 },
28196 - { 0x00009948, 0x9280c00a },
28197 - { 0x0000994c, 0x00020028 },
28198 - { 0x00009954, 0x5f3ca3de },
28199 - { 0x00009958, 0x2108ecff },
28200 - { 0x00009968, 0x000003ce },
28201 - { 0x00009970, 0x1927b515 },
28202 - { 0x00009974, 0x00000000 },
28203 - { 0x00009978, 0x00000001 },
28204 - { 0x0000997c, 0x00000000 },
28205 - { 0x00009980, 0x00000000 },
28206 - { 0x00009984, 0x00000000 },
28207 - { 0x00009988, 0x00000000 },
28208 - { 0x0000998c, 0x00000000 },
28209 - { 0x00009990, 0x00000000 },
28210 - { 0x00009994, 0x00000000 },
28211 - { 0x00009998, 0x00000000 },
28212 - { 0x0000999c, 0x00000000 },
28213 - { 0x000099a0, 0x00000000 },
28214 - { 0x000099a4, 0x00000001 },
28215 - { 0x000099a8, 0x201fff00 },
28216 - { 0x000099ac, 0x2def0a00 },
28217 - { 0x000099b0, 0x03051000 },
28218 - { 0x000099b4, 0x00000820 },
28219 - { 0x000099dc, 0x00000000 },
28220 - { 0x000099e0, 0x00000000 },
28221 - { 0x000099e4, 0xaaaaaaaa },
28222 - { 0x000099e8, 0x3c466478 },
28223 - { 0x000099ec, 0x0cc80caa },
28224 - { 0x000099f0, 0x00000000 },
28225 - { 0x0000a208, 0x803e6788 },
28226 - { 0x0000a210, 0x4080a333 },
28227 - { 0x0000a214, 0x00206c10 },
28228 - { 0x0000a218, 0x009c4060 },
28229 - { 0x0000a220, 0x01834061 },
28230 - { 0x0000a224, 0x00000400 },
28231 - { 0x0000a228, 0x000003b5 },
28232 - { 0x0000a22c, 0x00000000 },
28233 - { 0x0000a234, 0x20202020 },
28234 - { 0x0000a238, 0x20202020 },
28235 - { 0x0000a244, 0x00000000 },
28236 - { 0x0000a248, 0xfffffffc },
28237 - { 0x0000a24c, 0x00000000 },
28238 - { 0x0000a254, 0x00000000 },
28239 - { 0x0000a258, 0x0ccb5380 },
28240 - { 0x0000a25c, 0x15151501 },
28241 - { 0x0000a260, 0xdfa90f01 },
28242 - { 0x0000a268, 0x00000000 },
28243 - { 0x0000a26c, 0x0ebae9e6 },
28244 - { 0x0000d270, 0x0d820820 },
28245 - { 0x0000a278, 0x39ce739c },
28246 - { 0x0000a27c, 0x050e039c },
28247 - { 0x0000d35c, 0x07ffffef },
28248 - { 0x0000d360, 0x0fffffe7 },
28249 - { 0x0000d364, 0x17ffffe5 },
28250 - { 0x0000d368, 0x1fffffe4 },
28251 - { 0x0000d36c, 0x37ffffe3 },
28252 - { 0x0000d370, 0x3fffffe3 },
28253 - { 0x0000d374, 0x57ffffe3 },
28254 - { 0x0000d378, 0x5fffffe2 },
28255 - { 0x0000d37c, 0x7fffffe2 },
28256 - { 0x0000d380, 0x7f3c7bba },
28257 - { 0x0000d384, 0xf3307ff0 },
28258 - { 0x0000a388, 0x0c000000 },
28259 - { 0x0000a38c, 0x20202020 },
28260 - { 0x0000a390, 0x20202020 },
28261 - { 0x0000a394, 0x39ce739c },
28262 - { 0x0000a398, 0x0000039c },
28263 - { 0x0000a39c, 0x00000001 },
28264 - { 0x0000a3a0, 0x00000000 },
28265 - { 0x0000a3a4, 0x00000000 },
28266 - { 0x0000a3a8, 0x00000000 },
28267 - { 0x0000a3ac, 0x00000000 },
28268 - { 0x0000a3b0, 0x00000000 },
28269 - { 0x0000a3b4, 0x00000000 },
28270 - { 0x0000a3b8, 0x00000000 },
28271 - { 0x0000a3bc, 0x00000000 },
28272 - { 0x0000a3c0, 0x00000000 },
28273 - { 0x0000a3c4, 0x00000000 },
28274 - { 0x0000a3cc, 0x20202020 },
28275 - { 0x0000a3d0, 0x20202020 },
28276 - { 0x0000a3d4, 0x20202020 },
28277 - { 0x0000a3dc, 0x39ce739c },
28278 - { 0x0000a3e0, 0x0000039c },
28279 - { 0x0000a3e4, 0x00000000 },
28280 - { 0x0000a3e8, 0x18c43433 },
28281 - { 0x0000a3ec, 0x00f70081 },
28282 - { 0x00007800, 0x00140000 },
28283 - { 0x00007804, 0x0e4548d8 },
28284 - { 0x00007808, 0x54214514 },
28285 - { 0x0000780c, 0x02025820 },
28286 - { 0x00007810, 0x71c0d388 },
28287 - { 0x00007814, 0x924934a8 },
28288 - { 0x0000781c, 0x00000000 },
28289 - { 0x00007820, 0x00000c04 },
28290 - { 0x00007824, 0x00d86fff },
28291 - { 0x00007828, 0x26d2491b },
28292 - { 0x0000782c, 0x6e36d97b },
28293 - { 0x00007830, 0xedb6d96c },
28294 - { 0x00007834, 0x71400086 },
28295 - { 0x00007838, 0xfac68800 },
28296 - { 0x0000783c, 0x0001fffe },
28297 - { 0x00007840, 0xffeb1a20 },
28298 - { 0x00007844, 0x000c0db6 },
28299 - { 0x00007848, 0x6db61b6f },
28300 - { 0x0000784c, 0x6d9b66db },
28301 - { 0x00007850, 0x6d8c6dba },
28302 - { 0x00007854, 0x00040000 },
28303 - { 0x00007858, 0xdb003012 },
28304 - { 0x0000785c, 0x04924914 },
28305 - { 0x00007860, 0x21084210 },
28306 - { 0x00007864, 0xf7d7ffde },
28307 - { 0x00007868, 0xc2034080 },
28308 - { 0x0000786c, 0x48609eb4 },
28309 - { 0x00007870, 0x10142c00 },
28310 -};
28311 -
28312 -static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
28313 - {0x00004040, 0x9248fd00 },
28314 - {0x00004040, 0x24924924 },
28315 - {0x00004040, 0xa8000019 },
28316 - {0x00004040, 0x13160820 },
28317 - {0x00004040, 0xe5980560 },
28318 - {0x00004040, 0xc01dcffd },
28319 - {0x00004040, 0x1aaabe41 },
28320 - {0x00004040, 0xbe105554 },
28321 - {0x00004040, 0x00043007 },
28322 - {0x00004044, 0x00000000 },
28323 -};
28324 -
28325 -static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285[][2] = {
28326 - {0x00004040, 0x9248fd00 },
28327 - {0x00004040, 0x24924924 },
28328 - {0x00004040, 0xa8000019 },
28329 - {0x00004040, 0x13160820 },
28330 - {0x00004040, 0xe5980560 },
28331 - {0x00004040, 0xc01dcffc },
28332 - {0x00004040, 0x1aaabe41 },
28333 - {0x00004040, 0xbe105554 },
28334 - {0x00004040, 0x00043007 },
28335 - {0x00004044, 0x00000000 },
28336 -};
28337 -
28338 -/* AR9285 v1_2 PCI Register Writes. Created: 04/13/09 */
28339 -static const u_int32_t ar9285Modes_9285_1_2[][6] = {
28340 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
28341 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
28342 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
28343 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
28344 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
28345 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
28346 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
28347 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
28348 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
28349 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
28350 - { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
28351 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
28352 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
28353 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
28354 - { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
28355 - { 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
28356 - { 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
28357 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
28358 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
28359 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
28360 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
28361 - { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
28362 - { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
28363 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
28364 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
28365 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
28366 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
28367 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
28368 - { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
28369 - { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28370 - { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28371 - { 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
28372 - { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
28373 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
28374 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
28375 - { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
28376 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
28377 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
28378 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28379 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28380 - { 0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
28381 - { 0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
28382 - { 0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
28383 - { 0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
28384 - { 0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
28385 - { 0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
28386 - { 0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
28387 - { 0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
28388 - { 0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
28389 - { 0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
28390 - { 0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
28391 - { 0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
28392 - { 0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
28393 - { 0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
28394 - { 0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
28395 - { 0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
28396 - { 0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
28397 - { 0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
28398 - { 0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
28399 - { 0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
28400 - { 0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
28401 - { 0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
28402 - { 0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
28403 - { 0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
28404 - { 0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
28405 - { 0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
28406 - { 0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
28407 - { 0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
28408 - { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
28409 - { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
28410 - { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
28411 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
28412 - { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
28413 - { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
28414 - { 0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
28415 - { 0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
28416 - { 0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
28417 - { 0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
28418 - { 0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
28419 - { 0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
28420 - { 0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
28421 - { 0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
28422 - { 0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
28423 - { 0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
28424 - { 0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
28425 - { 0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
28426 - { 0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
28427 - { 0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
28428 - { 0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
28429 - { 0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
28430 - { 0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
28431 - { 0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
28432 - { 0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
28433 - { 0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
28434 - { 0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
28435 - { 0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
28436 - { 0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
28437 - { 0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
28438 - { 0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
28439 - { 0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
28440 - { 0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
28441 - { 0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
28442 - { 0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
28443 - { 0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
28444 - { 0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
28445 - { 0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
28446 - { 0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
28447 - { 0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
28448 - { 0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
28449 - { 0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
28450 - { 0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
28451 - { 0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
28452 - { 0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
28453 - { 0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
28454 - { 0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
28455 - { 0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
28456 - { 0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
28457 - { 0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
28458 - { 0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
28459 - { 0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
28460 - { 0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
28461 - { 0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
28462 - { 0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
28463 - { 0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
28464 - { 0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
28465 - { 0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
28466 - { 0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
28467 - { 0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
28468 - { 0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
28469 - { 0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28470 - { 0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28471 - { 0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28472 - { 0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28473 - { 0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28474 - { 0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28475 - { 0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28476 - { 0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28477 - { 0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28478 - { 0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28479 - { 0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28480 - { 0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28481 - { 0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28482 - { 0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28483 - { 0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28484 - { 0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28485 - { 0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28486 - { 0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28487 - { 0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28488 - { 0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28489 - { 0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28490 - { 0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28491 - { 0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28492 - { 0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28493 - { 0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28494 - { 0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28495 - { 0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28496 - { 0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28497 - { 0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28498 - { 0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28499 - { 0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28500 - { 0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28501 - { 0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28502 - { 0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28503 - { 0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28504 - { 0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28505 - { 0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28506 - { 0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28507 - { 0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28508 - { 0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
28509 - { 0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
28510 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
28511 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
28512 - { 0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
28513 - { 0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
28514 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
28515 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
28516 - { 0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
28517 - { 0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
28518 - { 0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
28519 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
28520 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
28521 - { 0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
28522 - { 0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
28523 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
28524 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
28525 - { 0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
28526 - { 0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
28527 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
28528 - { 0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
28529 - { 0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
28530 - { 0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
28531 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
28532 - { 0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
28533 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
28534 - { 0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
28535 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
28536 - { 0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
28537 - { 0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
28538 - { 0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
28539 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
28540 - { 0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
28541 - { 0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
28542 - { 0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
28543 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
28544 - { 0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
28545 - { 0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
28546 - { 0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
28547 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
28548 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
28549 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
28550 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
28551 - { 0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
28552 - { 0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
28553 - { 0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
28554 - { 0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
28555 - { 0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
28556 - { 0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
28557 - { 0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
28558 - { 0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
28559 - { 0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
28560 - { 0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
28561 - { 0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
28562 - { 0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
28563 - { 0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
28564 - { 0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
28565 - { 0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
28566 - { 0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
28567 - { 0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
28568 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
28569 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
28570 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
28571 - { 0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
28572 - { 0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
28573 - { 0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
28574 - { 0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
28575 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
28576 - { 0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
28577 - { 0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
28578 - { 0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
28579 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
28580 - { 0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
28581 - { 0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
28582 - { 0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
28583 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
28584 - { 0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
28585 - { 0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
28586 - { 0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
28587 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
28588 - { 0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
28589 - { 0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
28590 - { 0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
28591 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
28592 - { 0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
28593 - { 0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
28594 - { 0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
28595 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
28596 - { 0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
28597 - { 0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28598 - { 0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28599 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28600 - { 0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28601 - { 0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28602 - { 0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28603 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28604 - { 0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28605 - { 0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28606 - { 0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28607 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28608 - { 0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28609 - { 0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28610 - { 0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28611 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28612 - { 0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28613 - { 0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28614 - { 0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28615 - { 0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28616 - { 0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28617 - { 0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28618 - { 0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28619 - { 0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28620 - { 0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28621 - { 0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28622 - { 0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28623 - { 0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28624 - { 0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28625 - { 0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28626 - { 0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28627 - { 0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28628 - { 0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28629 - { 0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28630 - { 0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28631 - { 0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28632 - { 0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28633 - { 0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28634 - { 0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28635 - { 0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28636 - { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
28637 - { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
28638 - { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
28639 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
28640 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
28641 - { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
28642 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
28643 -};
28644 -
28645 -static const u_int32_t ar9285Common_9285_1_2[][2] = {
28646 - { 0x0000000c, 0x00000000 },
28647 - { 0x00000030, 0x00020045 },
28648 - { 0x00000034, 0x00000005 },
28649 - { 0x00000040, 0x00000000 },
28650 - { 0x00000044, 0x00000008 },
28651 - { 0x00000048, 0x00000008 },
28652 - { 0x0000004c, 0x00000010 },
28653 - { 0x00000050, 0x00000000 },
28654 - { 0x00000054, 0x0000001f },
28655 - { 0x00000800, 0x00000000 },
28656 - { 0x00000804, 0x00000000 },
28657 - { 0x00000808, 0x00000000 },
28658 - { 0x0000080c, 0x00000000 },
28659 - { 0x00000810, 0x00000000 },
28660 - { 0x00000814, 0x00000000 },
28661 - { 0x00000818, 0x00000000 },
28662 - { 0x0000081c, 0x00000000 },
28663 - { 0x00000820, 0x00000000 },
28664 - { 0x00000824, 0x00000000 },
28665 - { 0x00001040, 0x002ffc0f },
28666 - { 0x00001044, 0x002ffc0f },
28667 - { 0x00001048, 0x002ffc0f },
28668 - { 0x0000104c, 0x002ffc0f },
28669 - { 0x00001050, 0x002ffc0f },
28670 - { 0x00001054, 0x002ffc0f },
28671 - { 0x00001058, 0x002ffc0f },
28672 - { 0x0000105c, 0x002ffc0f },
28673 - { 0x00001060, 0x002ffc0f },
28674 - { 0x00001064, 0x002ffc0f },
28675 - { 0x00001230, 0x00000000 },
28676 - { 0x00001270, 0x00000000 },
28677 - { 0x00001038, 0x00000000 },
28678 - { 0x00001078, 0x00000000 },
28679 - { 0x000010b8, 0x00000000 },
28680 - { 0x000010f8, 0x00000000 },
28681 - { 0x00001138, 0x00000000 },
28682 - { 0x00001178, 0x00000000 },
28683 - { 0x000011b8, 0x00000000 },
28684 - { 0x000011f8, 0x00000000 },
28685 - { 0x00001238, 0x00000000 },
28686 - { 0x00001278, 0x00000000 },
28687 - { 0x000012b8, 0x00000000 },
28688 - { 0x000012f8, 0x00000000 },
28689 - { 0x00001338, 0x00000000 },
28690 - { 0x00001378, 0x00000000 },
28691 - { 0x000013b8, 0x00000000 },
28692 - { 0x000013f8, 0x00000000 },
28693 - { 0x00001438, 0x00000000 },
28694 - { 0x00001478, 0x00000000 },
28695 - { 0x000014b8, 0x00000000 },
28696 - { 0x000014f8, 0x00000000 },
28697 - { 0x00001538, 0x00000000 },
28698 - { 0x00001578, 0x00000000 },
28699 - { 0x000015b8, 0x00000000 },
28700 - { 0x000015f8, 0x00000000 },
28701 - { 0x00001638, 0x00000000 },
28702 - { 0x00001678, 0x00000000 },
28703 - { 0x000016b8, 0x00000000 },
28704 - { 0x000016f8, 0x00000000 },
28705 - { 0x00001738, 0x00000000 },
28706 - { 0x00001778, 0x00000000 },
28707 - { 0x000017b8, 0x00000000 },
28708 - { 0x000017f8, 0x00000000 },
28709 - { 0x0000103c, 0x00000000 },
28710 - { 0x0000107c, 0x00000000 },
28711 - { 0x000010bc, 0x00000000 },
28712 - { 0x000010fc, 0x00000000 },
28713 - { 0x0000113c, 0x00000000 },
28714 - { 0x0000117c, 0x00000000 },
28715 - { 0x000011bc, 0x00000000 },
28716 - { 0x000011fc, 0x00000000 },
28717 - { 0x0000123c, 0x00000000 },
28718 - { 0x0000127c, 0x00000000 },
28719 - { 0x000012bc, 0x00000000 },
28720 - { 0x000012fc, 0x00000000 },
28721 - { 0x0000133c, 0x00000000 },
28722 - { 0x0000137c, 0x00000000 },
28723 - { 0x000013bc, 0x00000000 },
28724 - { 0x000013fc, 0x00000000 },
28725 - { 0x0000143c, 0x00000000 },
28726 - { 0x0000147c, 0x00000000 },
28727 - { 0x00004030, 0x00000002 },
28728 - { 0x0000403c, 0x00000002 },
28729 - { 0x00004024, 0x0000001f },
28730 - { 0x00004060, 0x00000000 },
28731 - { 0x00004064, 0x00000000 },
28732 - { 0x00007010, 0x00000031 },
28733 - { 0x00007034, 0x00000002 },
28734 - { 0x00007038, 0x000004c2 },
28735 - { 0x00008004, 0x00000000 },
28736 - { 0x00008008, 0x00000000 },
28737 - { 0x0000800c, 0x00000000 },
28738 - { 0x00008018, 0x00000700 },
28739 - { 0x00008020, 0x00000000 },
28740 - { 0x00008038, 0x00000000 },
28741 - { 0x0000803c, 0x00000000 },
28742 - { 0x00008048, 0x00000000 },
28743 - { 0x00008054, 0x00000000 },
28744 - { 0x00008058, 0x00000000 },
28745 - { 0x0000805c, 0x000fc78f },
28746 - { 0x00008060, 0x0000000f },
28747 - { 0x00008064, 0x00000000 },
28748 - { 0x00008070, 0x00000000 },
28749 - { 0x000080c0, 0x2a80001a },
28750 - { 0x000080c4, 0x05dc01e0 },
28751 - { 0x000080c8, 0x1f402710 },
28752 - { 0x000080cc, 0x01f40000 },
28753 - { 0x000080d0, 0x00001e00 },
28754 - { 0x000080d4, 0x00000000 },
28755 - { 0x000080d8, 0x00400000 },
28756 - { 0x000080e0, 0xffffffff },
28757 - { 0x000080e4, 0x0000ffff },
28758 - { 0x000080e8, 0x003f3f3f },
28759 - { 0x000080ec, 0x00000000 },
28760 - { 0x000080f0, 0x00000000 },
28761 - { 0x000080f4, 0x00000000 },
28762 - { 0x000080f8, 0x00000000 },
28763 - { 0x000080fc, 0x00020000 },
28764 - { 0x00008100, 0x00020000 },
28765 - { 0x00008104, 0x00000001 },
28766 - { 0x00008108, 0x00000052 },
28767 - { 0x0000810c, 0x00000000 },
28768 - { 0x00008110, 0x00000168 },
28769 - { 0x00008118, 0x000100aa },
28770 - { 0x0000811c, 0x00003210 },
28771 - { 0x00008120, 0x08f04810 },
28772 - { 0x00008124, 0x00000000 },
28773 - { 0x00008128, 0x00000000 },
28774 - { 0x0000812c, 0x00000000 },
28775 - { 0x00008130, 0x00000000 },
28776 - { 0x00008134, 0x00000000 },
28777 - { 0x00008138, 0x00000000 },
28778 - { 0x0000813c, 0x00000000 },
28779 - { 0x00008144, 0xffffffff },
28780 - { 0x00008168, 0x00000000 },
28781 - { 0x0000816c, 0x00000000 },
28782 - { 0x00008170, 0x32143320 },
28783 - { 0x00008174, 0xfaa4fa50 },
28784 - { 0x00008178, 0x00000100 },
28785 - { 0x0000817c, 0x00000000 },
28786 - { 0x000081c0, 0x00000000 },
28787 - { 0x000081d0, 0x0000320a },
28788 - { 0x000081ec, 0x00000000 },
28789 - { 0x000081f0, 0x00000000 },
28790 - { 0x000081f4, 0x00000000 },
28791 - { 0x000081f8, 0x00000000 },
28792 - { 0x000081fc, 0x00000000 },
28793 - { 0x00008200, 0x00000000 },
28794 - { 0x00008204, 0x00000000 },
28795 - { 0x00008208, 0x00000000 },
28796 - { 0x0000820c, 0x00000000 },
28797 - { 0x00008210, 0x00000000 },
28798 - { 0x00008214, 0x00000000 },
28799 - { 0x00008218, 0x00000000 },
28800 - { 0x0000821c, 0x00000000 },
28801 - { 0x00008220, 0x00000000 },
28802 - { 0x00008224, 0x00000000 },
28803 - { 0x00008228, 0x00000000 },
28804 - { 0x0000822c, 0x00000000 },
28805 - { 0x00008230, 0x00000000 },
28806 - { 0x00008234, 0x00000000 },
28807 - { 0x00008238, 0x00000000 },
28808 - { 0x0000823c, 0x00000000 },
28809 - { 0x00008240, 0x00100000 },
28810 - { 0x00008244, 0x0010f400 },
28811 - { 0x00008248, 0x00000100 },
28812 - { 0x0000824c, 0x0001e800 },
28813 - { 0x00008250, 0x00000000 },
28814 - { 0x00008254, 0x00000000 },
28815 - { 0x00008258, 0x00000000 },
28816 - { 0x0000825c, 0x400000ff },
28817 - { 0x00008260, 0x00080922 },
28818 - { 0x00008264, 0x88a00010 },
28819 - { 0x00008270, 0x00000000 },
28820 - { 0x00008274, 0x40000000 },
28821 - { 0x00008278, 0x003e4180 },
28822 - { 0x0000827c, 0x00000000 },
28823 - { 0x00008284, 0x0000002c },
28824 - { 0x00008288, 0x0000002c },
28825 - { 0x0000828c, 0x00000000 },
28826 - { 0x00008294, 0x00000000 },
28827 - { 0x00008298, 0x00000000 },
28828 - { 0x0000829c, 0x00000000 },
28829 - { 0x00008300, 0x00000040 },
28830 - { 0x00008314, 0x00000000 },
28831 - { 0x00008328, 0x00000000 },
28832 - { 0x0000832c, 0x00000001 },
28833 - { 0x00008330, 0x00000302 },
28834 - { 0x00008334, 0x00000e00 },
28835 - { 0x00008338, 0x00ff0000 },
28836 - { 0x0000833c, 0x00000000 },
28837 - { 0x00008340, 0x00010380 },
28838 - { 0x00008344, 0x00481043 },
28839 - { 0x00009808, 0x00000000 },
28840 - { 0x0000980c, 0xafe68e30 },
28841 - { 0x00009810, 0xfd14e000 },
28842 - { 0x00009814, 0x9c0a9f6b },
28843 - { 0x0000981c, 0x00000000 },
28844 - { 0x0000982c, 0x0000a000 },
28845 - { 0x00009830, 0x00000000 },
28846 - { 0x0000983c, 0x00200400 },
28847 - { 0x0000984c, 0x0040233c },
28848 - { 0x00009854, 0x00000044 },
28849 - { 0x00009900, 0x00000000 },
28850 - { 0x00009904, 0x00000000 },
28851 - { 0x00009908, 0x00000000 },
28852 - { 0x0000990c, 0x00000000 },
28853 - { 0x00009910, 0x01002310 },
28854 - { 0x0000991c, 0x10000fff },
28855 - { 0x00009920, 0x04900000 },
28856 - { 0x00009928, 0x00000001 },
28857 - { 0x0000992c, 0x00000004 },
28858 - { 0x00009934, 0x1e1f2022 },
28859 - { 0x00009938, 0x0a0b0c0d },
28860 - { 0x0000993c, 0x00000000 },
28861 - { 0x00009940, 0x14750604 },
28862 - { 0x00009948, 0x9280c00a },
28863 - { 0x0000994c, 0x00020028 },
28864 - { 0x00009954, 0x5f3ca3de },
28865 - { 0x00009958, 0x2108ecff },
28866 - { 0x00009968, 0x000003ce },
28867 - { 0x00009970, 0x192bb514 },
28868 - { 0x00009974, 0x00000000 },
28869 - { 0x00009978, 0x00000001 },
28870 - { 0x0000997c, 0x00000000 },
28871 - { 0x00009980, 0x00000000 },
28872 - { 0x00009984, 0x00000000 },
28873 - { 0x00009988, 0x00000000 },
28874 - { 0x0000998c, 0x00000000 },
28875 - { 0x00009990, 0x00000000 },
28876 - { 0x00009994, 0x00000000 },
28877 - { 0x00009998, 0x00000000 },
28878 - { 0x0000999c, 0x00000000 },
28879 - { 0x000099a0, 0x00000000 },
28880 - { 0x000099a4, 0x00000001 },
28881 - { 0x000099a8, 0x201fff00 },
28882 - { 0x000099ac, 0x2def0400 },
28883 - { 0x000099b0, 0x03051000 },
28884 - { 0x000099b4, 0x00000820 },
28885 - { 0x000099dc, 0x00000000 },
28886 - { 0x000099e0, 0x00000000 },
28887 - { 0x000099e4, 0xaaaaaaaa },
28888 - { 0x000099e8, 0x3c466478 },
28889 - { 0x000099ec, 0x0cc80caa },
28890 - { 0x000099f0, 0x00000000 },
28891 - { 0x0000a208, 0x803e68c8 },
28892 - { 0x0000a210, 0x4080a333 },
28893 - { 0x0000a214, 0x00206c10 },
28894 - { 0x0000a218, 0x009c4060 },
28895 - { 0x0000a220, 0x01834061 },
28896 - { 0x0000a224, 0x00000400 },
28897 - { 0x0000a228, 0x000003b5 },
28898 - { 0x0000a22c, 0x00000000 },
28899 - { 0x0000a234, 0x20202020 },
28900 - { 0x0000a238, 0x20202020 },
28901 - { 0x0000a244, 0x00000000 },
28902 - { 0x0000a248, 0xfffffffc },
28903 - { 0x0000a24c, 0x00000000 },
28904 - { 0x0000a254, 0x00000000 },
28905 - { 0x0000a258, 0x0ccb5380 },
28906 - { 0x0000a25c, 0x15151501 },
28907 - { 0x0000a260, 0xdfa90f01 },
28908 - { 0x0000a268, 0x00000000 },
28909 - { 0x0000a26c, 0x0ebae9e6 },
28910 - { 0x0000d270, 0x0d820820 },
28911 - { 0x0000d35c, 0x07ffffef },
28912 - { 0x0000d360, 0x0fffffe7 },
28913 - { 0x0000d364, 0x17ffffe5 },
28914 - { 0x0000d368, 0x1fffffe4 },
28915 - { 0x0000d36c, 0x37ffffe3 },
28916 - { 0x0000d370, 0x3fffffe3 },
28917 - { 0x0000d374, 0x57ffffe3 },
28918 - { 0x0000d378, 0x5fffffe2 },
28919 - { 0x0000d37c, 0x7fffffe2 },
28920 - { 0x0000d380, 0x7f3c7bba },
28921 - { 0x0000d384, 0xf3307ff0 },
28922 - { 0x0000a388, 0x0c000000 },
28923 - { 0x0000a38c, 0x20202020 },
28924 - { 0x0000a390, 0x20202020 },
28925 - { 0x0000a39c, 0x00000001 },
28926 - { 0x0000a3a0, 0x00000000 },
28927 - { 0x0000a3a4, 0x00000000 },
28928 - { 0x0000a3a8, 0x00000000 },
28929 - { 0x0000a3ac, 0x00000000 },
28930 - { 0x0000a3b0, 0x00000000 },
28931 - { 0x0000a3b4, 0x00000000 },
28932 - { 0x0000a3b8, 0x00000000 },
28933 - { 0x0000a3bc, 0x00000000 },
28934 - { 0x0000a3c0, 0x00000000 },
28935 - { 0x0000a3c4, 0x00000000 },
28936 - { 0x0000a3cc, 0x20202020 },
28937 - { 0x0000a3d0, 0x20202020 },
28938 - { 0x0000a3d4, 0x20202020 },
28939 - { 0x0000a3e4, 0x00000000 },
28940 - { 0x0000a3e8, 0x18c43433 },
28941 - { 0x0000a3ec, 0x00f70081 },
28942 - { 0x00007800, 0x00140000 },
28943 - { 0x00007804, 0x0e4548d8 },
28944 - { 0x00007808, 0x54214514 },
28945 - { 0x0000780c, 0x02025830 },
28946 - { 0x00007810, 0x71c0d388 },
28947 - { 0x0000781c, 0x00000000 },
28948 - { 0x00007824, 0x00d86fff },
28949 - { 0x0000782c, 0x6e36d97b },
28950 - { 0x00007834, 0x71400087 },
28951 - { 0x00007844, 0x000c0db6 },
28952 - { 0x00007848, 0x6db6246f },
28953 - { 0x0000784c, 0x6d9b66db },
28954 - { 0x00007850, 0x6d8c6dba },
28955 - { 0x00007854, 0x00040000 },
28956 - { 0x00007858, 0xdb003012 },
28957 - { 0x0000785c, 0x04924914 },
28958 - { 0x00007860, 0x21084210 },
28959 - { 0x00007864, 0xf7d7ffde },
28960 - { 0x00007868, 0xc2034080 },
28961 - { 0x00007870, 0x10142c00 },
28962 -};
28963 -
28964 -static const u_int32_t ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
28965 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
28966 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28967 - { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
28968 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
28969 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
28970 - { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
28971 - { 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
28972 - { 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
28973 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
28974 - { 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
28975 - { 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
28976 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
28977 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
28978 - { 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
28979 - { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
28980 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
28981 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
28982 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
28983 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
28984 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
28985 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
28986 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
28987 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
28988 - { 0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8 },
28989 - { 0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b },
28990 - { 0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e },
28991 - { 0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803 },
28992 - { 0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe },
28993 - { 0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20 },
28994 - { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
28995 - { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
28996 - { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
28997 - { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
28998 - { 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
28999 - { 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
29000 - { 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
29001 - { 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
29002 - { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
29003 -};
29004 -
29005 -static const u_int32_t ar9285Modes_original_tx_gain_9285_1_2[][6] = {
29006 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
29007 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29008 - { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
29009 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
29010 - { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
29011 - { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
29012 - { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
29013 - { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
29014 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
29015 - { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
29016 - { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
29017 - { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
29018 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
29019 - { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
29020 - { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
29021 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
29022 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
29023 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29024 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29025 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29026 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29027 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29028 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29029 - { 0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8 },
29030 - { 0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b },
29031 - { 0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e },
29032 - { 0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801 },
29033 - { 0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe },
29034 - { 0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20 },
29035 - { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
29036 - { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
29037 - { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
29038 - { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
29039 - { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
29040 - { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
29041 - { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
29042 - { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
29043 - { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
29044 -};
29045 -
29046 -static const u_int32_t ar9285Modes_XE2_0_normal_power[][6] = {
29047 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29048 - { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
29049 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
29050 - { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
29051 - { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
29052 - { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
29053 - { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
29054 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
29055 - { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
29056 - { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
29057 - { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
29058 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
29059 - { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
29060 - { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
29061 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
29062 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
29063 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29064 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29065 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29066 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29067 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29068 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29069 - { 0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8 },
29070 - { 0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b, 0x4ad2491b },
29071 - { 0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6dbae },
29072 - { 0x00007838, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441 },
29073 - { 0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe },
29074 - { 0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c },
29075 - { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
29076 - { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
29077 - { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
29078 - { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
29079 - { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
29080 - { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
29081 - { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
29082 - { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
29083 - { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
29084 -};
29085 -
29086 -static const u_int32_t ar9285Modes_XE2_0_high_power[][6] = {
29087 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29088 - { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
29089 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
29090 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
29091 - { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
29092 - { 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
29093 - { 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
29094 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
29095 - { 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
29096 - { 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
29097 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
29098 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
29099 - { 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
29100 - { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
29101 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
29102 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
29103 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29104 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29105 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29106 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29107 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29108 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29109 - { 0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8 },
29110 - { 0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b, 0x4ad2491b },
29111 - { 0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e },
29112 - { 0x00007838, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443 },
29113 - { 0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe },
29114 - { 0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c },
29115 - { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
29116 - { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
29117 - { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
29118 - { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
29119 - { 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
29120 - { 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
29121 - { 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
29122 - { 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
29123 - { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
29124 -};
29125 -
29126 -static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
29127 - {0x00004040, 0x9248fd00 },
29128 - {0x00004040, 0x24924924 },
29129 - {0x00004040, 0xa8000019 },
29130 - {0x00004040, 0x13160820 },
29131 - {0x00004040, 0xe5980560 },
29132 - {0x00004040, 0xc01dcffd },
29133 - {0x00004040, 0x1aaabe41 },
29134 - {0x00004040, 0xbe105554 },
29135 - {0x00004040, 0x00043007 },
29136 - {0x00004044, 0x00000000 },
29137 -};
29138 -
29139 -static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
29140 - {0x00004040, 0x9248fd00 },
29141 - {0x00004040, 0x24924924 },
29142 - {0x00004040, 0xa8000019 },
29143 - {0x00004040, 0x13160820 },
29144 - {0x00004040, 0xe5980560 },
29145 - {0x00004040, 0xc01dcffc },
29146 - {0x00004040, 0x1aaabe41 },
29147 - {0x00004040, 0xbe105554 },
29148 - {0x00004040, 0x00043007 },
29149 - {0x00004044, 0x00000000 },
29150 -};
29151 -
29152 -/* AR9287 Revision 10 */
29153 -static const u_int32_t ar9287Modes_9287_1_0[][6] = {
29154 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
29155 - { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 },
29156 - { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 },
29157 - { 0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180 },
29158 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
29159 - { 0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00, 0x06e006e0 },
29160 - { 0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b, 0x0988004f },
29161 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
29162 - { 0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a, 0x0000320a },
29163 - { 0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440, 0x00006880 },
29164 - { 0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300, 0x00000303 },
29165 - { 0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200, 0x02020200 },
29166 - { 0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e, 0x01000e0e },
29167 - { 0x00009828, 0x00000000, 0x00000000, 0x0a020001, 0x0a020001, 0x0a020001 },
29168 - { 0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e, 0x00000e0e },
29169 - { 0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007, 0x00000007 },
29170 - { 0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e, 0x206a012e },
29171 - { 0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0, 0x037216a0 },
29172 - { 0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
29173 - { 0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
29174 - { 0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e, 0x31395d5e },
29175 - { 0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20, 0x00058d18 },
29176 - { 0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
29177 - { 0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
29178 - { 0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881, 0x06903881 },
29179 - { 0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898, 0x000007d0 },
29180 - { 0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b, 0x00000016 },
29181 - { 0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
29182 - { 0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010, 0xefbc1010 },
29183 - { 0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
29184 - { 0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
29185 - { 0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210, 0x00000210 },
29186 - { 0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce, 0x000003ce },
29187 - { 0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c, 0x0000001c },
29188 - { 0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00, 0x00000c00 },
29189 - { 0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
29190 - { 0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444, 0x00000444 },
29191 - { 0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29192 - { 0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29193 - { 0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a, 0x1883800a },
29194 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
29195 - { 0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000, 0x0004a000 },
29196 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
29197 - { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29198 -};
29199 -
29200 -static const u_int32_t ar9287Common_9287_1_0[][2] = {
29201 - { 0x0000000c, 0x00000000 },
29202 - { 0x00000030, 0x00020015 },
29203 - { 0x00000034, 0x00000005 },
29204 - { 0x00000040, 0x00000000 },
29205 - { 0x00000044, 0x00000008 },
29206 - { 0x00000048, 0x00000008 },
29207 - { 0x0000004c, 0x00000010 },
29208 - { 0x00000050, 0x00000000 },
29209 - { 0x00000054, 0x0000001f },
29210 - { 0x00000800, 0x00000000 },
29211 - { 0x00000804, 0x00000000 },
29212 - { 0x00000808, 0x00000000 },
29213 - { 0x0000080c, 0x00000000 },
29214 - { 0x00000810, 0x00000000 },
29215 - { 0x00000814, 0x00000000 },
29216 - { 0x00000818, 0x00000000 },
29217 - { 0x0000081c, 0x00000000 },
29218 - { 0x00000820, 0x00000000 },
29219 - { 0x00000824, 0x00000000 },
29220 - { 0x00001040, 0x002ffc0f },
29221 - { 0x00001044, 0x002ffc0f },
29222 - { 0x00001048, 0x002ffc0f },
29223 - { 0x0000104c, 0x002ffc0f },
29224 - { 0x00001050, 0x002ffc0f },
29225 - { 0x00001054, 0x002ffc0f },
29226 - { 0x00001058, 0x002ffc0f },
29227 - { 0x0000105c, 0x002ffc0f },
29228 - { 0x00001060, 0x002ffc0f },
29229 - { 0x00001064, 0x002ffc0f },
29230 - { 0x00001230, 0x00000000 },
29231 - { 0x00001270, 0x00000000 },
29232 - { 0x00001038, 0x00000000 },
29233 - { 0x00001078, 0x00000000 },
29234 - { 0x000010b8, 0x00000000 },
29235 - { 0x000010f8, 0x00000000 },
29236 - { 0x00001138, 0x00000000 },
29237 - { 0x00001178, 0x00000000 },
29238 - { 0x000011b8, 0x00000000 },
29239 - { 0x000011f8, 0x00000000 },
29240 - { 0x00001238, 0x00000000 },
29241 - { 0x00001278, 0x00000000 },
29242 - { 0x000012b8, 0x00000000 },
29243 - { 0x000012f8, 0x00000000 },
29244 - { 0x00001338, 0x00000000 },
29245 - { 0x00001378, 0x00000000 },
29246 - { 0x000013b8, 0x00000000 },
29247 - { 0x000013f8, 0x00000000 },
29248 - { 0x00001438, 0x00000000 },
29249 - { 0x00001478, 0x00000000 },
29250 - { 0x000014b8, 0x00000000 },
29251 - { 0x000014f8, 0x00000000 },
29252 - { 0x00001538, 0x00000000 },
29253 - { 0x00001578, 0x00000000 },
29254 - { 0x000015b8, 0x00000000 },
29255 - { 0x000015f8, 0x00000000 },
29256 - { 0x00001638, 0x00000000 },
29257 - { 0x00001678, 0x00000000 },
29258 - { 0x000016b8, 0x00000000 },
29259 - { 0x000016f8, 0x00000000 },
29260 - { 0x00001738, 0x00000000 },
29261 - { 0x00001778, 0x00000000 },
29262 - { 0x000017b8, 0x00000000 },
29263 - { 0x000017f8, 0x00000000 },
29264 - { 0x0000103c, 0x00000000 },
29265 - { 0x0000107c, 0x00000000 },
29266 - { 0x000010bc, 0x00000000 },
29267 - { 0x000010fc, 0x00000000 },
29268 - { 0x0000113c, 0x00000000 },
29269 - { 0x0000117c, 0x00000000 },
29270 - { 0x000011bc, 0x00000000 },
29271 - { 0x000011fc, 0x00000000 },
29272 - { 0x0000123c, 0x00000000 },
29273 - { 0x0000127c, 0x00000000 },
29274 - { 0x000012bc, 0x00000000 },
29275 - { 0x000012fc, 0x00000000 },
29276 - { 0x0000133c, 0x00000000 },
29277 - { 0x0000137c, 0x00000000 },
29278 - { 0x000013bc, 0x00000000 },
29279 - { 0x000013fc, 0x00000000 },
29280 - { 0x0000143c, 0x00000000 },
29281 - { 0x0000147c, 0x00000000 },
29282 - { 0x00004030, 0x00000002 },
29283 - { 0x0000403c, 0x00000002 },
29284 - { 0x00004024, 0x0000001f },
29285 - { 0x00004060, 0x00000000 },
29286 - { 0x00004064, 0x00000000 },
29287 - { 0x00007010, 0x00000033 },
29288 - { 0x00007020, 0x00000000 },
29289 - { 0x00007034, 0x00000002 },
29290 - { 0x00007038, 0x000004c2 },
29291 - { 0x00008004, 0x00000000 },
29292 - { 0x00008008, 0x00000000 },
29293 - { 0x0000800c, 0x00000000 },
29294 - { 0x00008018, 0x00000700 },
29295 - { 0x00008020, 0x00000000 },
29296 - { 0x00008038, 0x00000000 },
29297 - { 0x0000803c, 0x00000000 },
29298 - { 0x00008048, 0x40000000 },
29299 - { 0x00008054, 0x00000000 },
29300 - { 0x00008058, 0x00000000 },
29301 - { 0x0000805c, 0x000fc78f },
29302 - { 0x00008060, 0x0000000f },
29303 - { 0x00008064, 0x00000000 },
29304 - { 0x00008070, 0x00000000 },
29305 - { 0x000080c0, 0x2a80001a },
29306 - { 0x000080c4, 0x05dc01e0 },
29307 - { 0x000080c8, 0x1f402710 },
29308 - { 0x000080cc, 0x01f40000 },
29309 - { 0x000080d0, 0x00001e00 },
29310 - { 0x000080d4, 0x00000000 },
29311 - { 0x000080d8, 0x00400000 },
29312 - { 0x000080e0, 0xffffffff },
29313 - { 0x000080e4, 0x0000ffff },
29314 - { 0x000080e8, 0x003f3f3f },
29315 - { 0x000080ec, 0x00000000 },
29316 - { 0x000080f0, 0x00000000 },
29317 - { 0x000080f4, 0x00000000 },
29318 - { 0x000080f8, 0x00000000 },
29319 - { 0x000080fc, 0x00020000 },
29320 - { 0x00008100, 0x00020000 },
29321 - { 0x00008104, 0x00000001 },
29322 - { 0x00008108, 0x00000052 },
29323 - { 0x0000810c, 0x00000000 },
29324 - { 0x00008110, 0x00000168 },
29325 - { 0x00008118, 0x000100aa },
29326 - { 0x0000811c, 0x00003210 },
29327 - { 0x00008124, 0x00000000 },
29328 - { 0x00008128, 0x00000000 },
29329 - { 0x0000812c, 0x00000000 },
29330 - { 0x00008130, 0x00000000 },
29331 - { 0x00008134, 0x00000000 },
29332 - { 0x00008138, 0x00000000 },
29333 - { 0x0000813c, 0x00000000 },
29334 - { 0x00008144, 0xffffffff },
29335 - { 0x00008168, 0x00000000 },
29336 - { 0x0000816c, 0x00000000 },
29337 - { 0x00008170, 0x18487320 },
29338 - { 0x00008174, 0xfaa4fa50 },
29339 - { 0x00008178, 0x00000100 },
29340 - { 0x0000817c, 0x00000000 },
29341 - { 0x000081c0, 0x00000000 },
29342 - { 0x000081c4, 0x00000000 },
29343 - { 0x000081d4, 0x00000000 },
29344 - { 0x000081ec, 0x00000000 },
29345 - { 0x000081f0, 0x00000000 },
29346 - { 0x000081f4, 0x00000000 },
29347 - { 0x000081f8, 0x00000000 },
29348 - { 0x000081fc, 0x00000000 },
29349 - { 0x00008200, 0x00000000 },
29350 - { 0x00008204, 0x00000000 },
29351 - { 0x00008208, 0x00000000 },
29352 - { 0x0000820c, 0x00000000 },
29353 - { 0x00008210, 0x00000000 },
29354 - { 0x00008214, 0x00000000 },
29355 - { 0x00008218, 0x00000000 },
29356 - { 0x0000821c, 0x00000000 },
29357 - { 0x00008220, 0x00000000 },
29358 - { 0x00008224, 0x00000000 },
29359 - { 0x00008228, 0x00000000 },
29360 - { 0x0000822c, 0x00000000 },
29361 - { 0x00008230, 0x00000000 },
29362 - { 0x00008234, 0x00000000 },
29363 - { 0x00008238, 0x00000000 },
29364 - { 0x0000823c, 0x00000000 },
29365 - { 0x00008240, 0x00100000 },
29366 - { 0x00008244, 0x0010f400 },
29367 - { 0x00008248, 0x00000100 },
29368 - { 0x0000824c, 0x0001e800 },
29369 - { 0x00008250, 0x00000000 },
29370 - { 0x00008254, 0x00000000 },
29371 - { 0x00008258, 0x00000000 },
29372 - { 0x0000825c, 0x400000ff },
29373 - { 0x00008260, 0x00080922 },
29374 - { 0x00008264, 0xa8a00010 },
29375 - { 0x00008270, 0x00000000 },
29376 - { 0x00008274, 0x40000000 },
29377 - { 0x00008278, 0x003e4180 },
29378 - { 0x0000827c, 0x00000000 },
29379 - { 0x00008284, 0x0000002c },
29380 - { 0x00008288, 0x0000002c },
29381 - { 0x0000828c, 0x000000ff },
29382 - { 0x00008294, 0x00000000 },
29383 - { 0x00008298, 0x00000000 },
29384 - { 0x0000829c, 0x00000000 },
29385 - { 0x00008300, 0x00000040 },
29386 - { 0x00008314, 0x00000000 },
29387 - { 0x00008328, 0x00000000 },
29388 - { 0x0000832c, 0x00000007 },
29389 - { 0x00008330, 0x00000302 },
29390 - { 0x00008334, 0x00000e00 },
29391 - { 0x00008338, 0x00ff0000 },
29392 - { 0x0000833c, 0x00000000 },
29393 - { 0x00008340, 0x000107ff },
29394 - { 0x00008344, 0x01c81043 },
29395 - { 0x00008360, 0xffffffff },
29396 - { 0x00008364, 0xffffffff },
29397 - { 0x00008368, 0x00000000 },
29398 - { 0x00008370, 0x00000000 },
29399 - { 0x00008374, 0x000000ff },
29400 - { 0x00008378, 0x00000000 },
29401 - { 0x0000837c, 0x00000000 },
29402 - { 0x00008380, 0xffffffff },
29403 - { 0x00008384, 0xffffffff },
29404 - { 0x00008390, 0x0fffffff },
29405 - { 0x00008394, 0x0fffffff },
29406 - { 0x00008398, 0x00000000 },
29407 - { 0x0000839c, 0x00000000 },
29408 - { 0x000083a0, 0x00000000 },
29409 - { 0x00009808, 0x00000000 },
29410 - { 0x0000980c, 0xafe68e30 },
29411 - { 0x00009810, 0xfd14e000 },
29412 - { 0x00009814, 0x9c0a9f6b },
29413 - { 0x0000981c, 0x00000000 },
29414 - { 0x0000982c, 0x0000a000 },
29415 - { 0x00009830, 0x00000000 },
29416 - { 0x0000983c, 0x00200400 },
29417 - { 0x0000984c, 0x0040233c },
29418 - { 0x0000a84c, 0x0040233c },
29419 - { 0x00009854, 0x00000044 },
29420 - { 0x00009900, 0x00000000 },
29421 - { 0x00009904, 0x00000000 },
29422 - { 0x00009908, 0x00000000 },
29423 - { 0x0000990c, 0x00000000 },
29424 - { 0x00009910, 0x10002310 },
29425 - { 0x0000991c, 0x10000fff },
29426 - { 0x00009920, 0x04900000 },
29427 - { 0x0000a920, 0x04900000 },
29428 - { 0x00009928, 0x00000001 },
29429 - { 0x0000992c, 0x00000004 },
29430 - { 0x00009930, 0x00000000 },
29431 - { 0x0000a930, 0x00000000 },
29432 - { 0x00009934, 0x1e1f2022 },
29433 - { 0x00009938, 0x0a0b0c0d },
29434 - { 0x0000993c, 0x00000000 },
29435 - { 0x00009948, 0x9280c00a },
29436 - { 0x0000994c, 0x00020028 },
29437 - { 0x00009954, 0x5f3ca3de },
29438 - { 0x00009958, 0x0108ecff },
29439 - { 0x00009940, 0x14750604 },
29440 - { 0x0000c95c, 0x004b6a8e },
29441 - { 0x00009970, 0x990bb515 },
29442 - { 0x00009974, 0x00000000 },
29443 - { 0x00009978, 0x00000001 },
29444 - { 0x0000997c, 0x00000000 },
29445 - { 0x000099a0, 0x00000000 },
29446 - { 0x000099a4, 0x00000001 },
29447 - { 0x000099a8, 0x201fff00 },
29448 - { 0x000099ac, 0x0c6f0000 },
29449 - { 0x000099b0, 0x03051000 },
29450 - { 0x000099b4, 0x00000820 },
29451 - { 0x000099c4, 0x06336f77 },
29452 - { 0x000099c8, 0x6af65329 },
29453 - { 0x000099cc, 0x08f186c8 },
29454 - { 0x000099d0, 0x00046384 },
29455 - { 0x000099dc, 0x00000000 },
29456 - { 0x000099e0, 0x00000000 },
29457 - { 0x000099e4, 0xaaaaaaaa },
29458 - { 0x000099e8, 0x3c466478 },
29459 - { 0x000099ec, 0x0cc80caa },
29460 - { 0x000099f0, 0x00000000 },
29461 - { 0x000099fc, 0x00001042 },
29462 - { 0x0000a1f4, 0x00fffeff },
29463 - { 0x0000a1f8, 0x00f5f9ff },
29464 - { 0x0000a1fc, 0xb79f6427 },
29465 - { 0x0000a208, 0x803e4788 },
29466 - { 0x0000a210, 0x4080a333 },
29467 - { 0x0000a214, 0x40206c10 },
29468 - { 0x0000a218, 0x009c4060 },
29469 - { 0x0000a220, 0x01834061 },
29470 - { 0x0000a224, 0x00000400 },
29471 - { 0x0000a228, 0x000003b5 },
29472 - { 0x0000a22c, 0x233f7180 },
29473 - { 0x0000a234, 0x20202020 },
29474 - { 0x0000a238, 0x20202020 },
29475 - { 0x0000a23c, 0x13c889af },
29476 - { 0x0000a240, 0x38490a20 },
29477 - { 0x0000a244, 0x00000000 },
29478 - { 0x0000a248, 0xfffffffc },
29479 - { 0x0000a24c, 0x00000000 },
29480 - { 0x0000a254, 0x00000000 },
29481 - { 0x0000a258, 0x0cdbd380 },
29482 - { 0x0000a25c, 0x0f0f0f01 },
29483 - { 0x0000a260, 0xdfa91f01 },
29484 - { 0x0000a264, 0x00418a11 },
29485 - { 0x0000b264, 0x00418a11 },
29486 - { 0x0000a268, 0x00000000 },
29487 - { 0x0000a26c, 0x0e79e5c6 },
29488 - { 0x0000b26c, 0x0e79e5c6 },
29489 - { 0x0000d270, 0x00820820 },
29490 - { 0x0000a278, 0x1ce739ce },
29491 - { 0x0000a27c, 0x050701ce },
29492 - { 0x0000d35c, 0x07ffffef },
29493 - { 0x0000d360, 0x0fffffe7 },
29494 - { 0x0000d364, 0x17ffffe5 },
29495 - { 0x0000d368, 0x1fffffe4 },
29496 - { 0x0000d36c, 0x37ffffe3 },
29497 - { 0x0000d370, 0x3fffffe3 },
29498 - { 0x0000d374, 0x57ffffe3 },
29499 - { 0x0000d378, 0x5fffffe2 },
29500 - { 0x0000d37c, 0x7fffffe2 },
29501 - { 0x0000d380, 0x7f3c7bba },
29502 - { 0x0000d384, 0xf3307ff0 },
29503 - { 0x0000a388, 0x0c000000 },
29504 - { 0x0000a38c, 0x20202020 },
29505 - { 0x0000a390, 0x20202020 },
29506 - { 0x0000a394, 0x1ce739ce },
29507 - { 0x0000a398, 0x000001ce },
29508 - { 0x0000b398, 0x000001ce },
29509 - { 0x0000a39c, 0x00000001 },
29510 - { 0x0000a3c8, 0x00000246 },
29511 - { 0x0000a3cc, 0x20202020 },
29512 - { 0x0000a3d0, 0x20202020 },
29513 - { 0x0000a3d4, 0x20202020 },
29514 - { 0x0000a3dc, 0x1ce739ce },
29515 - { 0x0000a3e0, 0x000001ce },
29516 - { 0x0000a3e4, 0x00000000 },
29517 - { 0x0000a3e8, 0x18c43433 },
29518 - { 0x0000a3ec, 0x00f70081 },
29519 - { 0x0000a3f0, 0x01036a1e },
29520 - { 0x0000a3f4, 0x00000000 },
29521 - { 0x0000b3f4, 0x00000000 },
29522 - { 0x0000a7d8, 0x00000001 },
29523 - { 0x00007800, 0x00000800 },
29524 - { 0x00007804, 0x6c35ffb0 },
29525 - { 0x00007808, 0x6db6c000 },
29526 - { 0x0000780c, 0x6db6cb30 },
29527 - { 0x00007810, 0x6db6cb6c },
29528 - { 0x00007814, 0x0501e200 },
29529 - { 0x00007818, 0x0094128d },
29530 - { 0x0000781c, 0x976ee392 },
29531 - { 0x00007820, 0xf75ff6fc },
29532 - { 0x00007824, 0x00040000 },
29533 - { 0x00007828, 0xdb003012 },
29534 - { 0x0000782c, 0x04924914 },
29535 - { 0x00007830, 0x21084210 },
29536 - { 0x00007834, 0x00140000 },
29537 - { 0x00007838, 0x0e4548d8 },
29538 - { 0x0000783c, 0x54214514 },
29539 - { 0x00007840, 0x02025820 },
29540 - { 0x00007844, 0x71c0d388 },
29541 - { 0x00007848, 0x934934a8 },
29542 - { 0x00007850, 0x00000000 },
29543 - { 0x00007854, 0x00000800 },
29544 - { 0x00007858, 0x6c35ffb0 },
29545 - { 0x0000785c, 0x6db6c000 },
29546 - { 0x00007860, 0x6db6cb2c },
29547 - { 0x00007864, 0x6db6cb6c },
29548 - { 0x00007868, 0x0501e200 },
29549 - { 0x0000786c, 0x0094128d },
29550 - { 0x00007870, 0x976ee392 },
29551 - { 0x00007874, 0xf75ff6fc },
29552 - { 0x00007878, 0x00040000 },
29553 - { 0x0000787c, 0xdb003012 },
29554 - { 0x00007880, 0x04924914 },
29555 - { 0x00007884, 0x21084210 },
29556 - { 0x00007888, 0x001b6db0 },
29557 - { 0x0000788c, 0x00376b63 },
29558 - { 0x00007890, 0x06db6db6 },
29559 - { 0x00007894, 0x006d8000 },
29560 - { 0x00007898, 0x48100000 },
29561 - { 0x0000789c, 0x00000000 },
29562 - { 0x000078a0, 0x08000000 },
29563 - { 0x000078a4, 0x0007ffd8 },
29564 - { 0x000078a8, 0x0007ffd8 },
29565 - { 0x000078ac, 0x001c0020 },
29566 - { 0x000078b0, 0x000611eb },
29567 - { 0x000078b4, 0x40008080 },
29568 - { 0x000078b8, 0x2a850160 },
29569 -};
29570 -
29571 -static const u_int32_t ar9287Modes_tx_gain_9287_1_0[][6] = {
29572 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
29573 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29574 - { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 },
29575 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004 },
29576 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a, 0x0000c00a },
29577 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c, 0x0001000c },
29578 - { 0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b, 0x0001420b },
29579 - { 0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a, 0x0001824a },
29580 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a, 0x0001c44a },
29581 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a, 0x0002064a },
29582 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a, 0x0002484a },
29583 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a, 0x00028a4a },
29584 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a },
29585 - { 0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a, 0x00030e4a },
29586 - { 0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a, 0x00034e8a },
29587 - { 0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c, 0x00038e8c },
29588 - { 0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc, 0x0003cecc },
29589 - { 0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4, 0x00040ed4 },
29590 - { 0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc, 0x00044edc },
29591 - { 0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede, 0x00048ede },
29592 - { 0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e },
29593 - { 0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e, 0x00050f5e },
29594 - { 0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e, 0x00054f9e },
29595 - { 0x0000a780, 0x00000000, 0x00000000, 0x00000060, 0x00000060, 0x00000060 },
29596 - { 0x0000a784, 0x00000000, 0x00000000, 0x00004062, 0x00004062, 0x00004062 },
29597 - { 0x0000a788, 0x00000000, 0x00000000, 0x00008064, 0x00008064, 0x00008064 },
29598 - { 0x0000a78c, 0x00000000, 0x00000000, 0x0000c0a4, 0x0000c0a4, 0x0000c0a4 },
29599 - { 0x0000a790, 0x00000000, 0x00000000, 0x000100b0, 0x000100b0, 0x000100b0 },
29600 - { 0x0000a794, 0x00000000, 0x00000000, 0x000140b2, 0x000140b2, 0x000140b2 },
29601 - { 0x0000a798, 0x00000000, 0x00000000, 0x000180b4, 0x000180b4, 0x000180b4 },
29602 - { 0x0000a79c, 0x00000000, 0x00000000, 0x0001c0f4, 0x0001c0f4, 0x0001c0f4 },
29603 - { 0x0000a7a0, 0x00000000, 0x00000000, 0x00020134, 0x00020134, 0x00020134 },
29604 - { 0x0000a7a4, 0x00000000, 0x00000000, 0x000240fe, 0x000240fe, 0x000240fe },
29605 - { 0x0000a7a8, 0x00000000, 0x00000000, 0x0002813e, 0x0002813e, 0x0002813e },
29606 - { 0x0000a7ac, 0x00000000, 0x00000000, 0x0002c17e, 0x0002c17e, 0x0002c17e },
29607 - { 0x0000a7b0, 0x00000000, 0x00000000, 0x000301be, 0x000301be, 0x000301be },
29608 - { 0x0000a7b4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29609 - { 0x0000a7b8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29610 - { 0x0000a7bc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29611 - { 0x0000a7c0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29612 - { 0x0000a7c4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29613 - { 0x0000a7c8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29614 - { 0x0000a7cc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29615 - { 0x0000a7d0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29616 - { 0x0000a7d4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29617 - { 0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000 },
29618 -};
29619 -
29620 -
29621 -static const u_int32_t ar9287Modes_rx_gain_9287_1_0[][6] = {
29622 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
29623 - { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
29624 - { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
29625 - { 0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
29626 - { 0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
29627 - { 0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
29628 - { 0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
29629 - { 0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
29630 - { 0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
29631 - { 0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
29632 - { 0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
29633 - { 0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
29634 - { 0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
29635 - { 0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
29636 - { 0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
29637 - { 0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
29638 - { 0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
29639 - { 0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
29640 - { 0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
29641 - { 0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
29642 - { 0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
29643 - { 0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
29644 - { 0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
29645 - { 0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
29646 - { 0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
29647 - { 0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
29648 - { 0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
29649 - { 0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
29650 - { 0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
29651 - { 0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
29652 - { 0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
29653 - { 0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
29654 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
29655 - { 0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
29656 - { 0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
29657 - { 0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
29658 - { 0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
29659 - { 0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
29660 - { 0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
29661 - { 0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
29662 - { 0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
29663 - { 0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
29664 - { 0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
29665 - { 0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
29666 - { 0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
29667 - { 0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
29668 - { 0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
29669 - { 0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
29670 - { 0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
29671 - { 0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
29672 - { 0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
29673 - { 0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
29674 - { 0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
29675 - { 0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
29676 - { 0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
29677 - { 0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
29678 - { 0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
29679 - { 0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
29680 - { 0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
29681 - { 0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
29682 - { 0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
29683 - { 0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
29684 - { 0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
29685 - { 0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
29686 - { 0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
29687 - { 0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
29688 - { 0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
29689 - { 0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
29690 - { 0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
29691 - { 0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
29692 - { 0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
29693 - { 0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
29694 - { 0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
29695 - { 0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
29696 - { 0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
29697 - { 0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
29698 - { 0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
29699 - { 0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
29700 - { 0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
29701 - { 0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
29702 - { 0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
29703 - { 0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
29704 - { 0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
29705 - { 0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
29706 - { 0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
29707 - { 0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
29708 - { 0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
29709 - { 0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
29710 - { 0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
29711 - { 0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
29712 - { 0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
29713 - { 0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
29714 - { 0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
29715 - { 0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
29716 - { 0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
29717 - { 0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
29718 - { 0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
29719 - { 0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
29720 - { 0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
29721 - { 0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
29722 - { 0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
29723 - { 0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
29724 - { 0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
29725 - { 0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
29726 - { 0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29727 - { 0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29728 - { 0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29729 - { 0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29730 - { 0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29731 - { 0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29732 - { 0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29733 - { 0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29734 - { 0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29735 - { 0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29736 - { 0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29737 - { 0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29738 - { 0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29739 - { 0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29740 - { 0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29741 - { 0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29742 - { 0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29743 - { 0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29744 - { 0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29745 - { 0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29746 - { 0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29747 - { 0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29748 - { 0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29749 - { 0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29750 - { 0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29751 - { 0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
29752 - { 0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
29753 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
29754 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
29755 - { 0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
29756 - { 0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
29757 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
29758 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
29759 - { 0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
29760 - { 0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
29761 - { 0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
29762 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
29763 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
29764 - { 0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
29765 - { 0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
29766 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
29767 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
29768 - { 0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
29769 - { 0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
29770 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
29771 - { 0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
29772 - { 0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
29773 - { 0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
29774 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
29775 - { 0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
29776 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
29777 - { 0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
29778 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
29779 - { 0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
29780 - { 0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
29781 - { 0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
29782 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
29783 - { 0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
29784 - { 0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
29785 - { 0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
29786 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
29787 - { 0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
29788 - { 0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
29789 - { 0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
29790 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
29791 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
29792 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
29793 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
29794 - { 0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
29795 - { 0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
29796 - { 0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
29797 - { 0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
29798 - { 0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
29799 - { 0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
29800 - { 0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
29801 - { 0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
29802 - { 0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
29803 - { 0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
29804 - { 0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
29805 - { 0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
29806 - { 0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
29807 - { 0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
29808 - { 0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
29809 - { 0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
29810 - { 0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
29811 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
29812 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
29813 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
29814 - { 0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
29815 - { 0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
29816 - { 0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
29817 - { 0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
29818 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
29819 - { 0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
29820 - { 0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
29821 - { 0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
29822 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
29823 - { 0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
29824 - { 0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
29825 - { 0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
29826 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
29827 - { 0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
29828 - { 0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
29829 - { 0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
29830 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
29831 - { 0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
29832 - { 0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
29833 - { 0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
29834 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
29835 - { 0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
29836 - { 0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
29837 - { 0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
29838 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
29839 - { 0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
29840 - { 0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
29841 - { 0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
29842 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
29843 - { 0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
29844 - { 0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
29845 - { 0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
29846 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
29847 - { 0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
29848 - { 0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
29849 - { 0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
29850 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
29851 - { 0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
29852 - { 0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
29853 - { 0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
29854 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29855 - { 0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29856 - { 0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29857 - { 0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29858 - { 0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29859 - { 0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29860 - { 0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29861 - { 0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29862 - { 0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29863 - { 0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29864 - { 0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29865 - { 0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29866 - { 0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29867 - { 0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29868 - { 0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29869 - { 0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29870 - { 0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29871 - { 0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29872 - { 0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29873 - { 0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29874 - { 0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29875 - { 0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29876 - { 0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29877 - { 0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29878 - { 0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29879 - { 0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
29880 - { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
29881 -};
29882 -
29883 -static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_0[][2] = {
29884 - {0x00004040, 0x9248fd00 },
29885 - {0x00004040, 0x24924924 },
29886 - {0x00004040, 0xa8000019 },
29887 - {0x00004040, 0x13160820 },
29888 - {0x00004040, 0xe5980560 },
29889 - {0x00004040, 0xc01dcffd },
29890 - {0x00004040, 0x1aaabe41 },
29891 - {0x00004040, 0xbe105554 },
29892 - {0x00004040, 0x00043007 },
29893 - {0x00004044, 0x00000000 },
29894 -};
29895 -
29896 -static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_0[][2] = {
29897 - {0x00004040, 0x9248fd00 },
29898 - {0x00004040, 0x24924924 },
29899 - {0x00004040, 0xa8000019 },
29900 - {0x00004040, 0x13160820 },
29901 - {0x00004040, 0xe5980560 },
29902 - {0x00004040, 0xc01dcffc },
29903 - {0x00004040, 0x1aaabe41 },
29904 - {0x00004040, 0xbe105554 },
29905 - {0x00004040, 0x00043007 },
29906 - {0x00004044, 0x00000000 },
29907 -};
29908 -
29909 -/* AR9287 Revision 11 */
29910 -
29911 -static const u_int32_t ar9287Modes_9287_1_1[][6] = {
29912 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
29913 - { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 },
29914 - { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 },
29915 - { 0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180 },
29916 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
29917 - { 0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00, 0x06e006e0 },
29918 - { 0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b, 0x0988004f },
29919 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
29920 - { 0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a, 0x0000320a },
29921 - { 0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440, 0x00006880 },
29922 - { 0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300, 0x00000303 },
29923 - { 0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200, 0x02020200 },
29924 - { 0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e, 0x01000e0e },
29925 - { 0x00009828, 0x00000000, 0x00000000, 0x3a020001, 0x3a020001, 0x3a020001 },
29926 - { 0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e, 0x00000e0e },
29927 - { 0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007, 0x00000007 },
29928 - { 0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e, 0x206a012e },
29929 - { 0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0, 0x037216a0 },
29930 - { 0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
29931 - { 0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
29932 - { 0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e, 0x31395d5e },
29933 - { 0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20, 0x00058d18 },
29934 - { 0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
29935 - { 0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
29936 - { 0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881, 0x06903881 },
29937 - { 0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898, 0x000007d0 },
29938 - { 0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b, 0x00000016 },
29939 - { 0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
29940 - { 0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010, 0xefbc1010 },
29941 - { 0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
29942 - { 0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
29943 - { 0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210, 0x00000210 },
29944 - { 0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce, 0x000003ce },
29945 - { 0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c, 0x0000001c },
29946 - { 0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00, 0x00000c00 },
29947 - { 0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
29948 - { 0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444, 0x00000444 },
29949 - { 0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29950 - { 0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29951 - { 0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a, 0x1883800a },
29952 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
29953 - { 0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000, 0x0004a000 },
29954 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
29955 - { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29956 -};
29957 -
29958 -static const u_int32_t ar9287Common_9287_1_1[][2] = {
29959 - { 0x0000000c, 0x00000000 },
29960 - { 0x00000030, 0x00020015 },
29961 - { 0x00000034, 0x00000005 },
29962 - { 0x00000040, 0x00000000 },
29963 - { 0x00000044, 0x00000008 },
29964 - { 0x00000048, 0x00000008 },
29965 - { 0x0000004c, 0x00000010 },
29966 - { 0x00000050, 0x00000000 },
29967 - { 0x00000054, 0x0000001f },
29968 - { 0x00000800, 0x00000000 },
29969 - { 0x00000804, 0x00000000 },
29970 - { 0x00000808, 0x00000000 },
29971 - { 0x0000080c, 0x00000000 },
29972 - { 0x00000810, 0x00000000 },
29973 - { 0x00000814, 0x00000000 },
29974 - { 0x00000818, 0x00000000 },
29975 - { 0x0000081c, 0x00000000 },
29976 - { 0x00000820, 0x00000000 },
29977 - { 0x00000824, 0x00000000 },
29978 - { 0x00001040, 0x002ffc0f },
29979 - { 0x00001044, 0x002ffc0f },
29980 - { 0x00001048, 0x002ffc0f },
29981 - { 0x0000104c, 0x002ffc0f },
29982 - { 0x00001050, 0x002ffc0f },
29983 - { 0x00001054, 0x002ffc0f },
29984 - { 0x00001058, 0x002ffc0f },
29985 - { 0x0000105c, 0x002ffc0f },
29986 - { 0x00001060, 0x002ffc0f },
29987 - { 0x00001064, 0x002ffc0f },
29988 - { 0x00001230, 0x00000000 },
29989 - { 0x00001270, 0x00000000 },
29990 - { 0x00001038, 0x00000000 },
29991 - { 0x00001078, 0x00000000 },
29992 - { 0x000010b8, 0x00000000 },
29993 - { 0x000010f8, 0x00000000 },
29994 - { 0x00001138, 0x00000000 },
29995 - { 0x00001178, 0x00000000 },
29996 - { 0x000011b8, 0x00000000 },
29997 - { 0x000011f8, 0x00000000 },
29998 - { 0x00001238, 0x00000000 },
29999 - { 0x00001278, 0x00000000 },
30000 - { 0x000012b8, 0x00000000 },
30001 - { 0x000012f8, 0x00000000 },
30002 - { 0x00001338, 0x00000000 },
30003 - { 0x00001378, 0x00000000 },
30004 - { 0x000013b8, 0x00000000 },
30005 - { 0x000013f8, 0x00000000 },
30006 - { 0x00001438, 0x00000000 },
30007 - { 0x00001478, 0x00000000 },
30008 - { 0x000014b8, 0x00000000 },
30009 - { 0x000014f8, 0x00000000 },
30010 - { 0x00001538, 0x00000000 },
30011 - { 0x00001578, 0x00000000 },
30012 - { 0x000015b8, 0x00000000 },
30013 - { 0x000015f8, 0x00000000 },
30014 - { 0x00001638, 0x00000000 },
30015 - { 0x00001678, 0x00000000 },
30016 - { 0x000016b8, 0x00000000 },
30017 - { 0x000016f8, 0x00000000 },
30018 - { 0x00001738, 0x00000000 },
30019 - { 0x00001778, 0x00000000 },
30020 - { 0x000017b8, 0x00000000 },
30021 - { 0x000017f8, 0x00000000 },
30022 - { 0x0000103c, 0x00000000 },
30023 - { 0x0000107c, 0x00000000 },
30024 - { 0x000010bc, 0x00000000 },
30025 - { 0x000010fc, 0x00000000 },
30026 - { 0x0000113c, 0x00000000 },
30027 - { 0x0000117c, 0x00000000 },
30028 - { 0x000011bc, 0x00000000 },
30029 - { 0x000011fc, 0x00000000 },
30030 - { 0x0000123c, 0x00000000 },
30031 - { 0x0000127c, 0x00000000 },
30032 - { 0x000012bc, 0x00000000 },
30033 - { 0x000012fc, 0x00000000 },
30034 - { 0x0000133c, 0x00000000 },
30035 - { 0x0000137c, 0x00000000 },
30036 - { 0x000013bc, 0x00000000 },
30037 - { 0x000013fc, 0x00000000 },
30038 - { 0x0000143c, 0x00000000 },
30039 - { 0x0000147c, 0x00000000 },
30040 - { 0x00004030, 0x00000002 },
30041 - { 0x0000403c, 0x00000002 },
30042 - { 0x00004024, 0x0000001f },
30043 - { 0x00004060, 0x00000000 },
30044 - { 0x00004064, 0x00000000 },
30045 - { 0x00007010, 0x00000033 },
30046 - { 0x00007020, 0x00000000 },
30047 - { 0x00007034, 0x00000002 },
30048 - { 0x00007038, 0x000004c2 },
30049 - { 0x00008004, 0x00000000 },
30050 - { 0x00008008, 0x00000000 },
30051 - { 0x0000800c, 0x00000000 },
30052 - { 0x00008018, 0x00000700 },
30053 - { 0x00008020, 0x00000000 },
30054 - { 0x00008038, 0x00000000 },
30055 - { 0x0000803c, 0x00000000 },
30056 - { 0x00008048, 0x40000000 },
30057 - { 0x00008054, 0x00000000 },
30058 - { 0x00008058, 0x00000000 },
30059 - { 0x0000805c, 0x000fc78f },
30060 - { 0x00008060, 0x0000000f },
30061 - { 0x00008064, 0x00000000 },
30062 - { 0x00008070, 0x00000000 },
30063 - { 0x000080c0, 0x2a80001a },
30064 - { 0x000080c4, 0x05dc01e0 },
30065 - { 0x000080c8, 0x1f402710 },
30066 - { 0x000080cc, 0x01f40000 },
30067 - { 0x000080d0, 0x00001e00 },
30068 - { 0x000080d4, 0x00000000 },
30069 - { 0x000080d8, 0x00400000 },
30070 - { 0x000080e0, 0xffffffff },
30071 - { 0x000080e4, 0x0000ffff },
30072 - { 0x000080e8, 0x003f3f3f },
30073 - { 0x000080ec, 0x00000000 },
30074 - { 0x000080f0, 0x00000000 },
30075 - { 0x000080f4, 0x00000000 },
30076 - { 0x000080f8, 0x00000000 },
30077 - { 0x000080fc, 0x00020000 },
30078 - { 0x00008100, 0x00020000 },
30079 - { 0x00008104, 0x00000001 },
30080 - { 0x00008108, 0x00000052 },
30081 - { 0x0000810c, 0x00000000 },
30082 - { 0x00008110, 0x00000168 },
30083 - { 0x00008118, 0x000100aa },
30084 - { 0x0000811c, 0x00003210 },
30085 - { 0x00008124, 0x00000000 },
30086 - { 0x00008128, 0x00000000 },
30087 - { 0x0000812c, 0x00000000 },
30088 - { 0x00008130, 0x00000000 },
30089 - { 0x00008134, 0x00000000 },
30090 - { 0x00008138, 0x00000000 },
30091 - { 0x0000813c, 0x00000000 },
30092 - { 0x00008144, 0xffffffff },
30093 - { 0x00008168, 0x00000000 },
30094 - { 0x0000816c, 0x00000000 },
30095 - { 0x00008170, 0x18487320 },
30096 - { 0x00008174, 0xfaa4fa50 },
30097 - { 0x00008178, 0x00000100 },
30098 - { 0x0000817c, 0x00000000 },
30099 - { 0x000081c0, 0x00000000 },
30100 - { 0x000081c4, 0x00000000 },
30101 - { 0x000081d4, 0x00000000 },
30102 - { 0x000081ec, 0x00000000 },
30103 - { 0x000081f0, 0x00000000 },
30104 - { 0x000081f4, 0x00000000 },
30105 - { 0x000081f8, 0x00000000 },
30106 - { 0x000081fc, 0x00000000 },
30107 - { 0x00008200, 0x00000000 },
30108 - { 0x00008204, 0x00000000 },
30109 - { 0x00008208, 0x00000000 },
30110 - { 0x0000820c, 0x00000000 },
30111 - { 0x00008210, 0x00000000 },
30112 - { 0x00008214, 0x00000000 },
30113 - { 0x00008218, 0x00000000 },
30114 - { 0x0000821c, 0x00000000 },
30115 - { 0x00008220, 0x00000000 },
30116 - { 0x00008224, 0x00000000 },
30117 - { 0x00008228, 0x00000000 },
30118 - { 0x0000822c, 0x00000000 },
30119 - { 0x00008230, 0x00000000 },
30120 - { 0x00008234, 0x00000000 },
30121 - { 0x00008238, 0x00000000 },
30122 - { 0x0000823c, 0x00000000 },
30123 - { 0x00008240, 0x00100000 },
30124 - { 0x00008244, 0x0010f400 },
30125 - { 0x00008248, 0x00000100 },
30126 - { 0x0000824c, 0x0001e800 },
30127 - { 0x00008250, 0x00000000 },
30128 - { 0x00008254, 0x00000000 },
30129 - { 0x00008258, 0x00000000 },
30130 - { 0x0000825c, 0x400000ff },
30131 - { 0x00008260, 0x00080922 },
30132 - { 0x00008264, 0x88a00010 },
30133 - { 0x00008270, 0x00000000 },
30134 - { 0x00008274, 0x40000000 },
30135 - { 0x00008278, 0x003e4180 },
30136 - { 0x0000827c, 0x00000000 },
30137 - { 0x00008284, 0x0000002c },
30138 - { 0x00008288, 0x0000002c },
30139 - { 0x0000828c, 0x000000ff },
30140 - { 0x00008294, 0x00000000 },
30141 - { 0x00008298, 0x00000000 },
30142 - { 0x0000829c, 0x00000000 },
30143 - { 0x00008300, 0x00000040 },
30144 - { 0x00008314, 0x00000000 },
30145 - { 0x00008328, 0x00000000 },
30146 - { 0x0000832c, 0x00000007 },
30147 - { 0x00008330, 0x00000302 },
30148 - { 0x00008334, 0x00000e00 },
30149 - { 0x00008338, 0x00ff0000 },
30150 - { 0x0000833c, 0x00000000 },
30151 - { 0x00008340, 0x000107ff },
30152 - { 0x00008344, 0x01c81043 },
30153 - { 0x00008360, 0xffffffff },
30154 - { 0x00008364, 0xffffffff },
30155 - { 0x00008368, 0x00000000 },
30156 - { 0x00008370, 0x00000000 },
30157 - { 0x00008374, 0x000000ff },
30158 - { 0x00008378, 0x00000000 },
30159 - { 0x0000837c, 0x00000000 },
30160 - { 0x00008380, 0xffffffff },
30161 - { 0x00008384, 0xffffffff },
30162 - { 0x00008390, 0x0fffffff },
30163 - { 0x00008394, 0x0fffffff },
30164 - { 0x00008398, 0x00000000 },
30165 - { 0x0000839c, 0x00000000 },
30166 - { 0x000083a0, 0x00000000 },
30167 - { 0x00009808, 0x00000000 },
30168 - { 0x0000980c, 0xafe68e30 },
30169 - { 0x00009810, 0xfd14e000 },
30170 - { 0x00009814, 0x9c0a9f6b },
30171 - { 0x0000981c, 0x00000000 },
30172 - { 0x0000982c, 0x0000a000 },
30173 - { 0x00009830, 0x00000000 },
30174 - { 0x0000983c, 0x00200400 },
30175 - { 0x0000984c, 0x0040233c },
30176 - { 0x0000a84c, 0x0040233c },
30177 - { 0x00009854, 0x00000044 },
30178 - { 0x00009900, 0x00000000 },
30179 - { 0x00009904, 0x00000000 },
30180 - { 0x00009908, 0x00000000 },
30181 - { 0x0000990c, 0x00000000 },
30182 - { 0x00009910, 0x10002310 },
30183 - { 0x0000991c, 0x10000fff },
30184 - { 0x00009920, 0x04900000 },
30185 - { 0x0000a920, 0x04900000 },
30186 - { 0x00009928, 0x00000001 },
30187 - { 0x0000992c, 0x00000004 },
30188 - { 0x00009930, 0x00000000 },
30189 - { 0x0000a930, 0x00000000 },
30190 - { 0x00009934, 0x1e1f2022 },
30191 - { 0x00009938, 0x0a0b0c0d },
30192 - { 0x0000993c, 0x00000000 },
30193 - { 0x00009948, 0x9280c00a },
30194 - { 0x0000994c, 0x00020028 },
30195 - { 0x00009954, 0x5f3ca3de },
30196 - { 0x00009958, 0x0108ecff },
30197 - { 0x00009940, 0x14750604 },
30198 - { 0x0000c95c, 0x004b6a8e },
30199 - { 0x00009970, 0x990bb514 },
30200 - { 0x00009974, 0x00000000 },
30201 - { 0x00009978, 0x00000001 },
30202 - { 0x0000997c, 0x00000000 },
30203 - { 0x000099a0, 0x00000000 },
30204 - { 0x000099a4, 0x00000001 },
30205 - { 0x000099a8, 0x201fff00 },
30206 - { 0x000099ac, 0x0c6f0000 },
30207 - { 0x000099b0, 0x03051000 },
30208 - { 0x000099b4, 0x00000820 },
30209 - { 0x000099c4, 0x06336f77 },
30210 - { 0x000099c8, 0x6af6532f },
30211 - { 0x000099cc, 0x08f186c8 },
30212 - { 0x000099d0, 0x00046384 },
30213 - { 0x000099dc, 0x00000000 },
30214 - { 0x000099e0, 0x00000000 },
30215 - { 0x000099e4, 0xaaaaaaaa },
30216 - { 0x000099e8, 0x3c466478 },
30217 - { 0x000099ec, 0x0cc80caa },
30218 - { 0x000099f0, 0x00000000 },
30219 - { 0x000099fc, 0x00001042 },
30220 - { 0x0000a208, 0x803e4788 },
30221 - { 0x0000a210, 0x4080a333 },
30222 - { 0x0000a214, 0x40206c10 },
30223 - { 0x0000a218, 0x009c4060 },
30224 - { 0x0000a220, 0x01834061 },
30225 - { 0x0000a224, 0x00000400 },
30226 - { 0x0000a228, 0x000003b5 },
30227 - { 0x0000a22c, 0x233f7180 },
30228 - { 0x0000a234, 0x20202020 },
30229 - { 0x0000a238, 0x20202020 },
30230 - { 0x0000a23c, 0x13c889af },
30231 - { 0x0000a240, 0x38490a20 },
30232 - { 0x0000a244, 0x00000000 },
30233 - { 0x0000a248, 0xfffffffc },
30234 - { 0x0000a24c, 0x00000000 },
30235 - { 0x0000a254, 0x00000000 },
30236 - { 0x0000a258, 0x0cdbd380 },
30237 - { 0x0000a25c, 0x0f0f0f01 },
30238 - { 0x0000a260, 0xdfa91f01 },
30239 - { 0x0000a264, 0x00418a11 },
30240 - { 0x0000b264, 0x00418a11 },
30241 - { 0x0000a268, 0x00000000 },
30242 - { 0x0000a26c, 0x0e79e5c6 },
30243 - { 0x0000b26c, 0x0e79e5c6 },
30244 - { 0x0000d270, 0x00820820 },
30245 - { 0x0000a278, 0x1ce739ce },
30246 - { 0x0000a27c, 0x050701ce },
30247 - { 0x0000d35c, 0x07ffffef },
30248 - { 0x0000d360, 0x0fffffe7 },
30249 - { 0x0000d364, 0x17ffffe5 },
30250 - { 0x0000d368, 0x1fffffe4 },
30251 - { 0x0000d36c, 0x37ffffe3 },
30252 - { 0x0000d370, 0x3fffffe3 },
30253 - { 0x0000d374, 0x57ffffe3 },
30254 - { 0x0000d378, 0x5fffffe2 },
30255 - { 0x0000d37c, 0x7fffffe2 },
30256 - { 0x0000d380, 0x7f3c7bba },
30257 - { 0x0000d384, 0xf3307ff0 },
30258 - { 0x0000a388, 0x0c000000 },
30259 - { 0x0000a38c, 0x20202020 },
30260 - { 0x0000a390, 0x20202020 },
30261 - { 0x0000a394, 0x1ce739ce },
30262 - { 0x0000a398, 0x000001ce },
30263 - { 0x0000b398, 0x000001ce },
30264 - { 0x0000a39c, 0x00000001 },
30265 - { 0x0000a3c8, 0x00000246 },
30266 - { 0x0000a3cc, 0x20202020 },
30267 - { 0x0000a3d0, 0x20202020 },
30268 - { 0x0000a3d4, 0x20202020 },
30269 - { 0x0000a3dc, 0x1ce739ce },
30270 - { 0x0000a3e0, 0x000001ce },
30271 - { 0x0000a3e4, 0x00000000 },
30272 - { 0x0000a3e8, 0x18c43433 },
30273 - { 0x0000a3ec, 0x00f70081 },
30274 - { 0x0000a3f0, 0x01036a1e },
30275 - { 0x0000a3f4, 0x00000000 },
30276 - { 0x0000b3f4, 0x00000000 },
30277 - { 0x0000a7d8, 0x000003f1 },
30278 - { 0x00007800, 0x00000800 },
30279 - { 0x00007804, 0x6c35ffd2 },
30280 - { 0x00007808, 0x6db6c000 },
30281 - { 0x0000780c, 0x6db6cb30 },
30282 - { 0x00007810, 0x6db6cb6c },
30283 - { 0x00007814, 0x0501e200 },
30284 - { 0x00007818, 0x0094128d },
30285 - { 0x0000781c, 0x976ee392 },
30286 - { 0x00007820, 0xf75ff6fc },
30287 - { 0x00007824, 0x00040000 },
30288 - { 0x00007828, 0xdb003012 },
30289 - { 0x0000782c, 0x04924914 },
30290 - { 0x00007830, 0x21084210 },
30291 - { 0x00007834, 0x00140000 },
30292 - { 0x00007838, 0x0e4548d8 },
30293 - { 0x0000783c, 0x54214514 },
30294 - { 0x00007840, 0x02025830 },
30295 - { 0x00007844, 0x71c0d388 },
30296 - { 0x00007848, 0x934934a8 },
30297 - { 0x00007850, 0x00000000 },
30298 - { 0x00007854, 0x00000800 },
30299 - { 0x00007858, 0x6c35ffd2 },
30300 - { 0x0000785c, 0x6db6c000 },
30301 - { 0x00007860, 0x6db6cb30 },
30302 - { 0x00007864, 0x6db6cb6c },
30303 - { 0x00007868, 0x0501e200 },
30304 - { 0x0000786c, 0x0094128d },
30305 - { 0x00007870, 0x976ee392 },
30306 - { 0x00007874, 0xf75ff6fc },
30307 - { 0x00007878, 0x00040000 },
30308 - { 0x0000787c, 0xdb003012 },
30309 - { 0x00007880, 0x04924914 },
30310 - { 0x00007884, 0x21084210 },
30311 - { 0x00007888, 0x001b6db0 },
30312 - { 0x0000788c, 0x00376b63 },
30313 - { 0x00007890, 0x06db6db6 },
30314 - { 0x00007894, 0x006d8000 },
30315 - { 0x00007898, 0x48100000 },
30316 - { 0x0000789c, 0x00000000 },
30317 - { 0x000078a0, 0x08000000 },
30318 - { 0x000078a4, 0x0007ffd8 },
30319 - { 0x000078a8, 0x0007ffd8 },
30320 - { 0x000078ac, 0x001c0020 },
30321 - { 0x000078b0, 0x00060aeb },
30322 - { 0x000078b4, 0x40008080 },
30323 - { 0x000078b8, 0x2a850160 },
30324 -};
30325 -
30326 -/*
30327 - * For Japanese regulatory requirements, 2484 MHz requires the following three
30328 - * registers be programmed differently from the channel between 2412 and 2472 MHz.
30329 - */
30330 -static const u_int32_t ar9287Common_normal_cck_fir_coeff_92871_1[][2] = {
30331 - { 0x0000a1f4, 0x00fffeff },
30332 - { 0x0000a1f8, 0x00f5f9ff },
30333 - { 0x0000a1fc, 0xb79f6427 },
30334 -};
30335 -
30336 -static const u_int32_t ar9287Common_japan_2484_cck_fir_coeff_92871_1[][2] = {
30337 - { 0x0000a1f4, 0x00000000 },
30338 - { 0x0000a1f8, 0xefff0301 },
30339 - { 0x0000a1fc, 0xca9228ee },
30340 -};
30341 -
30342 -static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = {
30343 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
30344 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30345 - { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 },
30346 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004 },
30347 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a, 0x0000c00a },
30348 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c, 0x0001000c },
30349 - { 0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b, 0x0001420b },
30350 - { 0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a, 0x0001824a },
30351 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a, 0x0001c44a },
30352 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a, 0x0002064a },
30353 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a, 0x0002484a },
30354 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a, 0x00028a4a },
30355 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a },
30356 - { 0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a, 0x00030e4a },
30357 - { 0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a, 0x00034e8a },
30358 - { 0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c, 0x00038e8c },
30359 - { 0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc, 0x0003cecc },
30360 - { 0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4, 0x00040ed4 },
30361 - { 0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc, 0x00044edc },
30362 - { 0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede, 0x00048ede },
30363 - { 0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e },
30364 - { 0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e, 0x00050f5e },
30365 - { 0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e, 0x00054f9e },
30366 - { 0x0000a780, 0x00000000, 0x00000000, 0x00000062, 0x00000062, 0x00000062 },
30367 - { 0x0000a784, 0x00000000, 0x00000000, 0x00004064, 0x00004064, 0x00004064 },
30368 - { 0x0000a788, 0x00000000, 0x00000000, 0x000080a4, 0x000080a4, 0x000080a4 },
30369 - { 0x0000a78c, 0x00000000, 0x00000000, 0x0000c0aa, 0x0000c0aa, 0x0000c0aa },
30370 - { 0x0000a790, 0x00000000, 0x00000000, 0x000100ac, 0x000100ac, 0x000100ac },
30371 - { 0x0000a794, 0x00000000, 0x00000000, 0x000140b4, 0x000140b4, 0x000140b4 },
30372 - { 0x0000a798, 0x00000000, 0x00000000, 0x000180f4, 0x000180f4, 0x000180f4 },
30373 - { 0x0000a79c, 0x00000000, 0x00000000, 0x0001c134, 0x0001c134, 0x0001c134 },
30374 - { 0x0000a7a0, 0x00000000, 0x00000000, 0x00020174, 0x00020174, 0x00020174 },
30375 - { 0x0000a7a4, 0x00000000, 0x00000000, 0x0002417c, 0x0002417c, 0x0002417c },
30376 - { 0x0000a7a8, 0x00000000, 0x00000000, 0x0002817e, 0x0002817e, 0x0002817e },
30377 - { 0x0000a7ac, 0x00000000, 0x00000000, 0x0002c1be, 0x0002c1be, 0x0002c1be },
30378 - { 0x0000a7b0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30379 - { 0x0000a7b4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30380 - { 0x0000a7b8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30381 - { 0x0000a7bc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30382 - { 0x0000a7c0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30383 - { 0x0000a7c4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30384 - { 0x0000a7c8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30385 - { 0x0000a7cc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30386 - { 0x0000a7d0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30387 - { 0x0000a7d4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30388 - { 0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000 },
30389 -};
30390 -
30391 -static const u_int32_t ar9287Modes_rx_gain_9287_1_1[][6] = {
30392 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
30393 - { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
30394 - { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
30395 - { 0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
30396 - { 0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
30397 - { 0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
30398 - { 0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
30399 - { 0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
30400 - { 0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
30401 - { 0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
30402 - { 0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
30403 - { 0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
30404 - { 0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
30405 - { 0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
30406 - { 0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
30407 - { 0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
30408 - { 0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
30409 - { 0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
30410 - { 0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
30411 - { 0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
30412 - { 0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
30413 - { 0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
30414 - { 0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
30415 - { 0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
30416 - { 0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
30417 - { 0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
30418 - { 0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
30419 - { 0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
30420 - { 0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
30421 - { 0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
30422 - { 0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
30423 - { 0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
30424 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
30425 - { 0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
30426 - { 0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
30427 - { 0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
30428 - { 0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
30429 - { 0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
30430 - { 0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
30431 - { 0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
30432 - { 0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
30433 - { 0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
30434 - { 0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
30435 - { 0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
30436 - { 0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
30437 - { 0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
30438 - { 0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
30439 - { 0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
30440 - { 0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
30441 - { 0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
30442 - { 0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
30443 - { 0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
30444 - { 0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
30445 - { 0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
30446 - { 0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
30447 - { 0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
30448 - { 0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
30449 - { 0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
30450 - { 0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
30451 - { 0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
30452 - { 0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
30453 - { 0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
30454 - { 0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
30455 - { 0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
30456 - { 0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
30457 - { 0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
30458 - { 0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
30459 - { 0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
30460 - { 0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
30461 - { 0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
30462 - { 0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
30463 - { 0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
30464 - { 0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
30465 - { 0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
30466 - { 0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
30467 - { 0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
30468 - { 0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
30469 - { 0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
30470 - { 0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
30471 - { 0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
30472 - { 0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
30473 - { 0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
30474 - { 0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
30475 - { 0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
30476 - { 0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
30477 - { 0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
30478 - { 0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
30479 - { 0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
30480 - { 0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
30481 - { 0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
30482 - { 0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
30483 - { 0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
30484 - { 0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
30485 - { 0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
30486 - { 0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
30487 - { 0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
30488 - { 0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
30489 - { 0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
30490 - { 0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
30491 - { 0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
30492 - { 0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
30493 - { 0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
30494 - { 0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
30495 - { 0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
30496 - { 0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30497 - { 0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30498 - { 0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30499 - { 0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30500 - { 0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30501 - { 0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30502 - { 0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30503 - { 0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30504 - { 0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30505 - { 0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30506 - { 0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30507 - { 0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30508 - { 0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30509 - { 0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30510 - { 0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30511 - { 0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30512 - { 0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30513 - { 0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30514 - { 0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30515 - { 0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30516 - { 0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30517 - { 0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30518 - { 0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30519 - { 0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30520 - { 0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30521 - { 0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
30522 - { 0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
30523 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
30524 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
30525 - { 0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
30526 - { 0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
30527 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
30528 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
30529 - { 0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
30530 - { 0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
30531 - { 0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
30532 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
30533 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
30534 - { 0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
30535 - { 0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
30536 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
30537 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
30538 - { 0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
30539 - { 0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
30540 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
30541 - { 0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
30542 - { 0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
30543 - { 0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
30544 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
30545 - { 0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
30546 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
30547 - { 0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
30548 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
30549 - { 0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
30550 - { 0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
30551 - { 0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
30552 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
30553 - { 0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
30554 - { 0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
30555 - { 0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
30556 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
30557 - { 0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
30558 - { 0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
30559 - { 0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
30560 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
30561 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
30562 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
30563 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
30564 - { 0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
30565 - { 0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
30566 - { 0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
30567 - { 0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
30568 - { 0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
30569 - { 0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
30570 - { 0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
30571 - { 0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
30572 - { 0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
30573 - { 0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
30574 - { 0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
30575 - { 0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
30576 - { 0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
30577 - { 0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
30578 - { 0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
30579 - { 0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
30580 - { 0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
30581 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
30582 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
30583 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
30584 - { 0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
30585 - { 0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
30586 - { 0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
30587 - { 0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
30588 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
30589 - { 0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
30590 - { 0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
30591 - { 0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
30592 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
30593 - { 0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
30594 - { 0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
30595 - { 0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
30596 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
30597 - { 0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
30598 - { 0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
30599 - { 0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
30600 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
30601 - { 0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
30602 - { 0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
30603 - { 0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
30604 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
30605 - { 0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
30606 - { 0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
30607 - { 0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
30608 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
30609 - { 0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
30610 - { 0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
30611 - { 0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
30612 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
30613 - { 0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
30614 - { 0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
30615 - { 0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
30616 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
30617 - { 0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
30618 - { 0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
30619 - { 0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
30620 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
30621 - { 0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
30622 - { 0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
30623 - { 0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
30624 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30625 - { 0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30626 - { 0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30627 - { 0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30628 - { 0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30629 - { 0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30630 - { 0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30631 - { 0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30632 - { 0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30633 - { 0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30634 - { 0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30635 - { 0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30636 - { 0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30637 - { 0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30638 - { 0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30639 - { 0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30640 - { 0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30641 - { 0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30642 - { 0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30643 - { 0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30644 - { 0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30645 - { 0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30646 - { 0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30647 - { 0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30648 - { 0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30649 - { 0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
30650 - { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
30651 -};
30652 -
30653 -static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
30654 - {0x00004040, 0x9248fd00 },
30655 - {0x00004040, 0x24924924 },
30656 - {0x00004040, 0xa8000019 },
30657 - {0x00004040, 0x13160820 },
30658 - {0x00004040, 0xe5980560 },
30659 - {0x00004040, 0xc01dcffd },
30660 - {0x00004040, 0x1aaabe41 },
30661 - {0x00004040, 0xbe105554 },
30662 - {0x00004040, 0x00043007 },
30663 - {0x00004044, 0x00000000 },
30664 -};
30665 -
30666 -static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
30667 - {0x00004040, 0x9248fd00 },
30668 - {0x00004040, 0x24924924 },
30669 - {0x00004040, 0xa8000019 },
30670 - {0x00004040, 0x13160820 },
30671 - {0x00004040, 0xe5980560 },
30672 - {0x00004040, 0xc01dcffc },
30673 - {0x00004040, 0x1aaabe41 },
30674 - {0x00004040, 0xbe105554 },
30675 - {0x00004040, 0x00043007 },
30676 - {0x00004044, 0x00000000 },
30677 -};
30678 -
30679 -
30680 -/* AR9271 initialization values automaticaly created: 06/04/09 */
30681 -static const u_int32_t ar9271Modes_9271[][6] = {
30682 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
30683 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
30684 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
30685 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
30686 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
30687 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
30688 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
30689 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
30690 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
30691 - { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
30692 - { 0x00009828, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001 },
30693 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
30694 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
30695 - { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
30696 - { 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
30697 - { 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
30698 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
30699 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
30700 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
30701 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
30702 - { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18 },
30703 - { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
30704 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
30705 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
30706 - { 0x00009910, 0x30002310, 0x30002310, 0x30002310, 0x30002310, 0x30002310 },
30707 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
30708 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
30709 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
30710 - { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
30711 - { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30712 - { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30713 - { 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
30714 - { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
30715 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
30716 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
30717 - { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
30718 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
30719 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
30720 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30721 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30722 - { 0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
30723 - { 0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
30724 - { 0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
30725 - { 0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
30726 - { 0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
30727 - { 0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
30728 - { 0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
30729 - { 0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
30730 - { 0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
30731 - { 0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
30732 - { 0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
30733 - { 0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
30734 - { 0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
30735 - { 0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
30736 - { 0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
30737 - { 0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
30738 - { 0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
30739 - { 0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
30740 - { 0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
30741 - { 0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
30742 - { 0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
30743 - { 0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
30744 - { 0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
30745 - { 0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
30746 - { 0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
30747 - { 0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
30748 - { 0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
30749 - { 0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
30750 - { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
30751 - { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
30752 - { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
30753 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
30754 - { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
30755 - { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
30756 - { 0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
30757 - { 0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
30758 - { 0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
30759 - { 0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
30760 - { 0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
30761 - { 0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
30762 - { 0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
30763 - { 0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
30764 - { 0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
30765 - { 0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
30766 - { 0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
30767 - { 0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
30768 - { 0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
30769 - { 0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
30770 - { 0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
30771 - { 0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
30772 - { 0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
30773 - { 0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
30774 - { 0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
30775 - { 0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
30776 - { 0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
30777 - { 0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
30778 - { 0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
30779 - { 0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
30780 - { 0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
30781 - { 0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
30782 - { 0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
30783 - { 0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
30784 - { 0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
30785 - { 0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
30786 - { 0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
30787 - { 0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
30788 - { 0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
30789 - { 0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
30790 - { 0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
30791 - { 0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
30792 - { 0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
30793 - { 0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
30794 - { 0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
30795 - { 0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
30796 - { 0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
30797 - { 0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
30798 - { 0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
30799 - { 0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
30800 - { 0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
30801 - { 0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
30802 - { 0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
30803 - { 0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
30804 - { 0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
30805 - { 0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
30806 - { 0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
30807 - { 0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
30808 - { 0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
30809 - { 0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
30810 - { 0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
30811 - { 0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30812 - { 0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30813 - { 0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30814 - { 0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30815 - { 0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30816 - { 0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30817 - { 0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30818 - { 0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30819 - { 0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30820 - { 0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30821 - { 0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30822 - { 0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30823 - { 0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30824 - { 0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30825 - { 0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30826 - { 0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30827 - { 0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30828 - { 0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30829 - { 0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30830 - { 0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30831 - { 0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30832 - { 0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30833 - { 0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30834 - { 0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30835 - { 0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30836 - { 0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30837 - { 0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30838 - { 0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30839 - { 0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30840 - { 0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30841 - { 0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30842 - { 0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30843 - { 0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30844 - { 0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30845 - { 0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30846 - { 0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30847 - { 0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30848 - { 0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30849 - { 0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30850 - { 0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
30851 - { 0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
30852 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
30853 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
30854 - { 0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
30855 - { 0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
30856 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
30857 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
30858 - { 0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
30859 - { 0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
30860 - { 0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
30861 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
30862 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
30863 - { 0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
30864 - { 0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
30865 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
30866 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
30867 - { 0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
30868 - { 0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
30869 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
30870 - { 0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
30871 - { 0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
30872 - { 0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
30873 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
30874 - { 0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
30875 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
30876 - { 0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
30877 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
30878 - { 0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
30879 - { 0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
30880 - { 0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
30881 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
30882 - { 0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
30883 - { 0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
30884 - { 0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
30885 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
30886 - { 0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
30887 - { 0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
30888 - { 0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
30889 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
30890 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
30891 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
30892 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
30893 - { 0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
30894 - { 0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
30895 - { 0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
30896 - { 0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
30897 - { 0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
30898 - { 0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
30899 - { 0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
30900 - { 0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
30901 - { 0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
30902 - { 0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
30903 - { 0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
30904 - { 0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
30905 - { 0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
30906 - { 0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
30907 - { 0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
30908 - { 0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
30909 - { 0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
30910 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
30911 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
30912 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
30913 - { 0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
30914 - { 0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
30915 - { 0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
30916 - { 0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
30917 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
30918 - { 0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
30919 - { 0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
30920 - { 0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
30921 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
30922 - { 0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
30923 - { 0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
30924 - { 0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
30925 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
30926 - { 0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
30927 - { 0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
30928 - { 0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
30929 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
30930 - { 0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
30931 - { 0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
30932 - { 0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
30933 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
30934 - { 0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
30935 - { 0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
30936 - { 0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
30937 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
30938 - { 0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
30939 - { 0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30940 - { 0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30941 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30942 - { 0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30943 - { 0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30944 - { 0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30945 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30946 - { 0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30947 - { 0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30948 - { 0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30949 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30950 - { 0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30951 - { 0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30952 - { 0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30953 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30954 - { 0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30955 - { 0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30956 - { 0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30957 - { 0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30958 - { 0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30959 - { 0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30960 - { 0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30961 - { 0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30962 - { 0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30963 - { 0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30964 - { 0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30965 - { 0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30966 - { 0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30967 - { 0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30968 - { 0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30969 - { 0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30970 - { 0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30971 - { 0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30972 - { 0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30973 - { 0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30974 - { 0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30975 - { 0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30976 - { 0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30977 - { 0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30978 - { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
30979 - { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
30980 - { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
30981 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
30982 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
30983 - { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
30984 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
30985 -};
30986 -
30987 -static const u_int32_t ar9271Common_9271[][2] = {
30988 - { 0x0000000c, 0x00000000 },
30989 - { 0x00000030, 0x00020045 },
30990 - { 0x00000034, 0x00000005 },
30991 - { 0x00000040, 0x00000000 },
30992 - { 0x00000044, 0x00000008 },
30993 - { 0x00000048, 0x00000008 },
30994 - { 0x0000004c, 0x00000010 },
30995 - { 0x00000050, 0x00000000 },
30996 - { 0x00000054, 0x0000001f },
30997 - { 0x00000800, 0x00000000 },
30998 - { 0x00000804, 0x00000000 },
30999 - { 0x00000808, 0x00000000 },
31000 - { 0x0000080c, 0x00000000 },
31001 - { 0x00000810, 0x00000000 },
31002 - { 0x00000814, 0x00000000 },
31003 - { 0x00000818, 0x00000000 },
31004 - { 0x0000081c, 0x00000000 },
31005 - { 0x00000820, 0x00000000 },
31006 - { 0x00000824, 0x00000000 },
31007 - { 0x00001040, 0x002ffc0f },
31008 - { 0x00001044, 0x002ffc0f },
31009 - { 0x00001048, 0x002ffc0f },
31010 - { 0x0000104c, 0x002ffc0f },
31011 - { 0x00001050, 0x002ffc0f },
31012 - { 0x00001054, 0x002ffc0f },
31013 - { 0x00001058, 0x002ffc0f },
31014 - { 0x0000105c, 0x002ffc0f },
31015 - { 0x00001060, 0x002ffc0f },
31016 - { 0x00001064, 0x002ffc0f },
31017 - { 0x00001230, 0x00000000 },
31018 - { 0x00001270, 0x00000000 },
31019 - { 0x00001038, 0x00000000 },
31020 - { 0x00001078, 0x00000000 },
31021 - { 0x000010b8, 0x00000000 },
31022 - { 0x000010f8, 0x00000000 },
31023 - { 0x00001138, 0x00000000 },
31024 - { 0x00001178, 0x00000000 },
31025 - { 0x000011b8, 0x00000000 },
31026 - { 0x000011f8, 0x00000000 },
31027 - { 0x00001238, 0x00000000 },
31028 - { 0x00001278, 0x00000000 },
31029 - { 0x000012b8, 0x00000000 },
31030 - { 0x000012f8, 0x00000000 },
31031 - { 0x00001338, 0x00000000 },
31032 - { 0x00001378, 0x00000000 },
31033 - { 0x000013b8, 0x00000000 },
31034 - { 0x000013f8, 0x00000000 },
31035 - { 0x00001438, 0x00000000 },
31036 - { 0x00001478, 0x00000000 },
31037 - { 0x000014b8, 0x00000000 },
31038 - { 0x000014f8, 0x00000000 },
31039 - { 0x00001538, 0x00000000 },
31040 - { 0x00001578, 0x00000000 },
31041 - { 0x000015b8, 0x00000000 },
31042 - { 0x000015f8, 0x00000000 },
31043 - { 0x00001638, 0x00000000 },
31044 - { 0x00001678, 0x00000000 },
31045 - { 0x000016b8, 0x00000000 },
31046 - { 0x000016f8, 0x00000000 },
31047 - { 0x00001738, 0x00000000 },
31048 - { 0x00001778, 0x00000000 },
31049 - { 0x000017b8, 0x00000000 },
31050 - { 0x000017f8, 0x00000000 },
31051 - { 0x0000103c, 0x00000000 },
31052 - { 0x0000107c, 0x00000000 },
31053 - { 0x000010bc, 0x00000000 },
31054 - { 0x000010fc, 0x00000000 },
31055 - { 0x0000113c, 0x00000000 },
31056 - { 0x0000117c, 0x00000000 },
31057 - { 0x000011bc, 0x00000000 },
31058 - { 0x000011fc, 0x00000000 },
31059 - { 0x0000123c, 0x00000000 },
31060 - { 0x0000127c, 0x00000000 },
31061 - { 0x000012bc, 0x00000000 },
31062 - { 0x000012fc, 0x00000000 },
31063 - { 0x0000133c, 0x00000000 },
31064 - { 0x0000137c, 0x00000000 },
31065 - { 0x000013bc, 0x00000000 },
31066 - { 0x000013fc, 0x00000000 },
31067 - { 0x0000143c, 0x00000000 },
31068 - { 0x0000147c, 0x00000000 },
31069 - { 0x00004030, 0x00000002 },
31070 - { 0x0000403c, 0x00000002 },
31071 - { 0x00004024, 0x0000001f },
31072 - { 0x00004060, 0x00000000 },
31073 - { 0x00004064, 0x00000000 },
31074 - { 0x00008004, 0x00000000 },
31075 - { 0x00008008, 0x00000000 },
31076 - { 0x0000800c, 0x00000000 },
31077 - { 0x00008018, 0x00000700 },
31078 - { 0x00008020, 0x00000000 },
31079 - { 0x00008038, 0x00000000 },
31080 - { 0x0000803c, 0x00000000 },
31081 - { 0x00008048, 0x00000000 },
31082 - { 0x00008054, 0x00000000 },
31083 - { 0x00008058, 0x00000000 },
31084 - { 0x0000805c, 0x000fc78f },
31085 - { 0x00008060, 0x0000000f },
31086 - { 0x00008064, 0x00000000 },
31087 - { 0x00008070, 0x00000000 },
31088 - { 0x000080b0, 0x00000000 },
31089 - { 0x000080b4, 0x00000000 },
31090 - { 0x000080b8, 0x00000000 },
31091 - { 0x000080bc, 0x00000000 },
31092 - { 0x000080c0, 0x2a80001a },
31093 - { 0x000080c4, 0x05dc01e0 },
31094 - { 0x000080c8, 0x1f402710 },
31095 - { 0x000080cc, 0x01f40000 },
31096 - { 0x000080d0, 0x00001e00 },
31097 - { 0x000080d4, 0x00000000 },
31098 - { 0x000080d8, 0x00400000 },
31099 - { 0x000080e0, 0xffffffff },
31100 - { 0x000080e4, 0x0000ffff },
31101 - { 0x000080e8, 0x003f3f3f },
31102 - { 0x000080ec, 0x00000000 },
31103 - { 0x000080f0, 0x00000000 },
31104 - { 0x000080f4, 0x00000000 },
31105 - { 0x000080f8, 0x00000000 },
31106 - { 0x000080fc, 0x00020000 },
31107 - { 0x00008100, 0x00020000 },
31108 - { 0x00008104, 0x00000001 },
31109 - { 0x00008108, 0x00000052 },
31110 - { 0x0000810c, 0x00000000 },
31111 - { 0x00008110, 0x00000168 },
31112 - { 0x00008118, 0x000100aa },
31113 - { 0x0000811c, 0x00003210 },
31114 - { 0x00008120, 0x08f04810 },
31115 - { 0x00008124, 0x00000000 },
31116 - { 0x00008128, 0x00000000 },
31117 - { 0x0000812c, 0x00000000 },
31118 - { 0x00008130, 0x00000000 },
31119 - { 0x00008134, 0x00000000 },
31120 - { 0x00008138, 0x00000000 },
31121 - { 0x0000813c, 0x00000000 },
31122 - { 0x00008144, 0xffffffff },
31123 - { 0x00008168, 0x00000000 },
31124 - { 0x0000816c, 0x00000000 },
31125 - { 0x00008170, 0x32143320 },
31126 - { 0x00008174, 0xfaa4fa50 },
31127 - { 0x00008178, 0x00000100 },
31128 - { 0x0000817c, 0x00000000 },
31129 - { 0x000081c0, 0x00000000 },
31130 - { 0x000081d0, 0x0000320a },
31131 - { 0x000081ec, 0x00000000 },
31132 - { 0x000081f0, 0x00000000 },
31133 - { 0x000081f4, 0x00000000 },
31134 - { 0x000081f8, 0x00000000 },
31135 - { 0x000081fc, 0x00000000 },
31136 - { 0x00008200, 0x00000000 },
31137 - { 0x00008204, 0x00000000 },
31138 - { 0x00008208, 0x00000000 },
31139 - { 0x0000820c, 0x00000000 },
31140 - { 0x00008210, 0x00000000 },
31141 - { 0x00008214, 0x00000000 },
31142 - { 0x00008218, 0x00000000 },
31143 - { 0x0000821c, 0x00000000 },
31144 - { 0x00008220, 0x00000000 },
31145 - { 0x00008224, 0x00000000 },
31146 - { 0x00008228, 0x00000000 },
31147 - { 0x0000822c, 0x00000000 },
31148 - { 0x00008230, 0x00000000 },
31149 - { 0x00008234, 0x00000000 },
31150 - { 0x00008238, 0x00000000 },
31151 - { 0x0000823c, 0x00000000 },
31152 - { 0x00008240, 0x00100000 },
31153 - { 0x00008244, 0x0010f400 },
31154 - { 0x00008248, 0x00000100 },
31155 - { 0x0000824c, 0x0001e800 },
31156 - { 0x00008250, 0x00000000 },
31157 - { 0x00008254, 0x00000000 },
31158 - { 0x00008258, 0x00000000 },
31159 - { 0x0000825c, 0x400000ff },
31160 - { 0x00008260, 0x00080922 },
31161 - { 0x00008264, 0xa8a00010 },
31162 - { 0x00008270, 0x00000000 },
31163 - { 0x00008274, 0x40000000 },
31164 - { 0x00008278, 0x003e4180 },
31165 - { 0x0000827c, 0x00000000 },
31166 - { 0x00008284, 0x0000002c },
31167 - { 0x00008288, 0x0000002c },
31168 - { 0x0000828c, 0x00000000 },
31169 - { 0x00008294, 0x00000000 },
31170 - { 0x00008298, 0x00000000 },
31171 - { 0x0000829c, 0x00000000 },
31172 - { 0x00008300, 0x00000040 },
31173 - { 0x00008314, 0x00000000 },
31174 - { 0x00008328, 0x00000000 },
31175 - { 0x0000832c, 0x00000001 },
31176 - { 0x00008330, 0x00000302 },
31177 - { 0x00008334, 0x00000e00 },
31178 - { 0x00008338, 0x00ff0000 },
31179 - { 0x0000833c, 0x00000000 },
31180 - { 0x00008340, 0x00010380 },
31181 - { 0x00008344, 0x00581043 },
31182 - { 0x00007010, 0x00000030 },
31183 - { 0x00007034, 0x00000002 },
31184 - { 0x00007038, 0x000004c2 },
31185 - { 0x00007800, 0x00140000 },
31186 - { 0x00007804, 0x0e4548d8 },
31187 - { 0x00007808, 0x54214514 },
31188 - { 0x0000780c, 0x02025820 },
31189 - { 0x00007810, 0x71c0d388 },
31190 - { 0x00007814, 0x924934a8 },
31191 - { 0x0000781c, 0x00000000 },
31192 - { 0x00007828, 0x66964300 },
31193 - { 0x0000782c, 0x8db6d961 },
31194 - { 0x00007830, 0x8db6d96c },
31195 - { 0x00007834, 0x6140008b },
31196 - { 0x0000783c, 0x72ee0a72 },
31197 - { 0x00007840, 0xbbfffffc },
31198 - { 0x00007844, 0x000c0db6 },
31199 - { 0x00007848, 0x6db61b6f },
31200 - { 0x0000784c, 0x6d9b66db },
31201 - { 0x00007850, 0x6d8c6dba },
31202 - { 0x00007854, 0x00040000 },
31203 - { 0x00007858, 0xdb003012 },
31204 - { 0x0000785c, 0x04924914 },
31205 - { 0x00007860, 0x21084210 },
31206 - { 0x00007864, 0xf7d7ffde },
31207 - { 0x00007868, 0xc2034080 },
31208 - { 0x00007870, 0x10142c00 },
31209 - { 0x00009808, 0x00000000 },
31210 - { 0x0000980c, 0xafe68e30 },
31211 - { 0x00009810, 0xfd14e000 },
31212 - { 0x00009814, 0x9c0a9f6b },
31213 - { 0x0000981c, 0x00000000 },
31214 - { 0x0000982c, 0x0000a000 },
31215 - { 0x00009830, 0x00000000 },
31216 - { 0x0000983c, 0x00200400 },
31217 - { 0x0000984c, 0x0040233c },
31218 - { 0x00009854, 0x00000044 },
31219 - { 0x00009900, 0x00000000 },
31220 - { 0x00009904, 0x00000000 },
31221 - { 0x00009908, 0x00000000 },
31222 - { 0x0000990c, 0x00000000 },
31223 - { 0x0000991c, 0x10000fff },
31224 - { 0x00009920, 0x04900000 },
31225 - { 0x00009928, 0x00000001 },
31226 - { 0x0000992c, 0x00000004 },
31227 - { 0x00009934, 0x1e1f2022 },
31228 - { 0x00009938, 0x0a0b0c0d },
31229 - { 0x0000993c, 0x00000000 },
31230 - { 0x00009940, 0x14750604 },
31231 - { 0x00009948, 0x9280c00a },
31232 - { 0x0000994c, 0x00020028 },
31233 - { 0x00009954, 0x5f3ca3de },
31234 - { 0x00009958, 0x0108ecff },
31235 - { 0x00009968, 0x000003ce },
31236 - { 0x00009970, 0x192bb514 },
31237 - { 0x00009974, 0x00000000 },
31238 - { 0x00009978, 0x00000001 },
31239 - { 0x0000997c, 0x00000000 },
31240 - { 0x00009980, 0x00000000 },
31241 - { 0x00009984, 0x00000000 },
31242 - { 0x00009988, 0x00000000 },
31243 - { 0x0000998c, 0x00000000 },
31244 - { 0x00009990, 0x00000000 },
31245 - { 0x00009994, 0x00000000 },
31246 - { 0x00009998, 0x00000000 },
31247 - { 0x0000999c, 0x00000000 },
31248 - { 0x000099a0, 0x00000000 },
31249 - { 0x000099a4, 0x00000001 },
31250 - { 0x000099a8, 0x201fff00 },
31251 - { 0x000099ac, 0x2def0400 },
31252 - { 0x000099b0, 0x03051000 },
31253 - { 0x000099b4, 0x00000820 },
31254 - { 0x000099dc, 0x00000000 },
31255 - { 0x000099e0, 0x00000000 },
31256 - { 0x000099e4, 0xaaaaaaaa },
31257 - { 0x000099e8, 0x3c466478 },
31258 - { 0x000099ec, 0x0cc80caa },
31259 - { 0x000099f0, 0x00000000 },
31260 - { 0x0000a208, 0x803e68c8 },
31261 - { 0x0000a210, 0x4080a333 },
31262 - { 0x0000a214, 0x00206c10 },
31263 - { 0x0000a218, 0x009c4060 },
31264 - { 0x0000a220, 0x01834061 },
31265 - { 0x0000a224, 0x00000400 },
31266 - { 0x0000a228, 0x000003b5 },
31267 - { 0x0000a22c, 0x00000000 },
31268 - { 0x0000a234, 0x20202020 },
31269 - { 0x0000a238, 0x20202020 },
31270 - { 0x0000a244, 0x00000000 },
31271 - { 0x0000a248, 0xfffffffc },
31272 - { 0x0000a24c, 0x00000000 },
31273 - { 0x0000a254, 0x00000000 },
31274 - { 0x0000a258, 0x0ccb5380 },
31275 - { 0x0000a25c, 0x15151501 },
31276 - { 0x0000a260, 0xdfa90f01 },
31277 - { 0x0000a268, 0x00000000 },
31278 - { 0x0000a26c, 0x0ebae9e6 },
31279 - { 0x0000a388, 0x0c000000 },
31280 - { 0x0000a38c, 0x20202020 },
31281 - { 0x0000a390, 0x20202020 },
31282 - { 0x0000a39c, 0x00000001 },
31283 - { 0x0000a3a0, 0x00000000 },
31284 - { 0x0000a3a4, 0x00000000 },
31285 - { 0x0000a3a8, 0x00000000 },
31286 - { 0x0000a3ac, 0x00000000 },
31287 - { 0x0000a3b0, 0x00000000 },
31288 - { 0x0000a3b4, 0x00000000 },
31289 - { 0x0000a3b8, 0x00000000 },
31290 - { 0x0000a3bc, 0x00000000 },
31291 - { 0x0000a3c0, 0x00000000 },
31292 - { 0x0000a3c4, 0x00000000 },
31293 - { 0x0000a3cc, 0x20202020 },
31294 - { 0x0000a3d0, 0x20202020 },
31295 - { 0x0000a3d4, 0x20202020 },
31296 - { 0x0000a3e4, 0x00000000 },
31297 - { 0x0000a3e8, 0x18c43433 },
31298 - { 0x0000a3ec, 0x00f70081 },
31299 - { 0x0000a3f0, 0x01036a2f },
31300 - { 0x0000a3f4, 0x00000000 },
31301 - { 0x0000d270, 0x0d820820 },
31302 - { 0x0000d35c, 0x07ffffef },
31303 - { 0x0000d360, 0x0fffffe7 },
31304 - { 0x0000d364, 0x17ffffe5 },
31305 - { 0x0000d368, 0x1fffffe4 },
31306 - { 0x0000d36c, 0x37ffffe3 },
31307 - { 0x0000d370, 0x3fffffe3 },
31308 - { 0x0000d374, 0x57ffffe3 },
31309 - { 0x0000d378, 0x5fffffe2 },
31310 - { 0x0000d37c, 0x7fffffe2 },
31311 - { 0x0000d380, 0x7f3c7bba },
31312 - { 0x0000d384, 0xf3307ff0 },
31313 -};
31314 -
31315 -static const u_int32_t ar9271Common_normal_cck_fir_coeff_9271[][2] = {
31316 - { 0x0000a1f4, 0x00fffeff },
31317 - { 0x0000a1f8, 0x00f5f9ff },
31318 - { 0x0000a1fc, 0xb79f6427 },
31319 -};
31320 -
31321 -static const u_int32_t ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = {
31322 - { 0x0000a1f4, 0x00000000 },
31323 - { 0x0000a1f8, 0xefff0301 },
31324 - { 0x0000a1fc, 0xca9228ee },
31325 -};
31326 -
31327 -static const u_int32_t ar9271Modes_9271_1_0_only[][6] = {
31328 - { 0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311 },
31329 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
31330 -};
31331 -
31332 -static const u_int32_t ar9271Modes_9271_ANI_reg[][6] = {
31333 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
31334 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
31335 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
31336 - { 0x0000986c, 0x06903881, 0x06903881, 0x06903881, 0x06903881, 0x06903881 },
31337 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
31338 - { 0x0000a208, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8 },
31339 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
31340 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
31341 -};
31342 -
31343 -static const u_int32_t ar9271Modes_normal_power_tx_gain_9271[][6] = {
31344 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31345 - { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
31346 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
31347 - { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
31348 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001e610, 0x0001e610, 0x00000000 },
31349 - { 0x0000a314, 0x00000000, 0x00000000, 0x0002d6d0, 0x0002d6d0, 0x00000000 },
31350 - { 0x0000a318, 0x00000000, 0x00000000, 0x00039758, 0x00039758, 0x00000000 },
31351 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0003b759, 0x0003b759, 0x00000000 },
31352 - { 0x0000a320, 0x00000000, 0x00000000, 0x0003d75a, 0x0003d75a, 0x00000000 },
31353 - { 0x0000a324, 0x00000000, 0x00000000, 0x0004175c, 0x0004175c, 0x00000000 },
31354 - { 0x0000a328, 0x00000000, 0x00000000, 0x0004575e, 0x0004575e, 0x00000000 },
31355 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0004979f, 0x0004979f, 0x00000000 },
31356 - { 0x0000a330, 0x00000000, 0x00000000, 0x0004d7df, 0x0004d7df, 0x00000000 },
31357 - { 0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de, 0x00000000 },
31358 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
31359 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
31360 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31361 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31362 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31363 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31364 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31365 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31366 - { 0x00007838, 0x00000029, 0x00000029, 0x00000029, 0x00000029, 0x00000029 },
31367 - { 0x00007824, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff },
31368 - { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
31369 - { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
31370 - { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a218652, 0x0a218652, 0x0a22a652 },
31371 - { 0x0000a278, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
31372 - { 0x0000a27c, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd },
31373 - { 0x0000a394, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
31374 - { 0x0000a398, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd },
31375 - { 0x0000a3dc, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
31376 - { 0x0000a3e0, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd },
31377 -};
31378 -
31379 -static const u_int32_t ar9271Modes_high_power_tx_gain_9271[][6] = {
31380 - { 0x0000a300, 0x00000000, 0x00000000, 0x00010000, 0x00010000, 0x00000000 },
31381 - { 0x0000a304, 0x00000000, 0x00000000, 0x00016200, 0x00016200, 0x00000000 },
31382 - { 0x0000a308, 0x00000000, 0x00000000, 0x00018201, 0x00018201, 0x00000000 },
31383 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0001b240, 0x0001b240, 0x00000000 },
31384 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001d241, 0x0001d241, 0x00000000 },
31385 - { 0x0000a314, 0x00000000, 0x00000000, 0x0001f600, 0x0001f600, 0x00000000 },
31386 - { 0x0000a318, 0x00000000, 0x00000000, 0x00022800, 0x00022800, 0x00000000 },
31387 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00026802, 0x00026802, 0x00000000 },
31388 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002b805, 0x0002b805, 0x00000000 },
31389 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002ea41, 0x0002ea41, 0x00000000 },
31390 - { 0x0000a328, 0x00000000, 0x00000000, 0x00038b00, 0x00038b00, 0x00000000 },
31391 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0003ab40, 0x0003ab40, 0x00000000 },
31392 - { 0x0000a330, 0x00000000, 0x00000000, 0x0003cd80, 0x0003cd80, 0x00000000 },
31393 - { 0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de, 0x00000000 },
31394 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
31395 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
31396 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31397 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31398 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31399 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31400 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31401 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31402 - { 0x00007838, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b },
31403 - { 0x00007824, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff },
31404 - { 0x0000786c, 0x08609eb6, 0x08609eb6, 0x08609eba, 0x08609eba, 0x08609eb6 },
31405 - { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
31406 - { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a212652, 0x0a212652, 0x0a22a652 },
31407 - { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
31408 - { 0x0000a27c, 0x05018063, 0x05038063, 0x05018063, 0x05018063, 0x05018063 },
31409 - { 0x0000a394, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63 },
31410 - { 0x0000a398, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063 },
31411 - { 0x0000a3dc, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63 },
31412 - { 0x0000a3e0, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063 },
31413 -};
31414 --- a/drivers/net/wireless/ath/ath9k/mac.c
31415 +++ b/drivers/net/wireless/ath/ath9k/mac.c
31416 @@ -57,6 +57,18 @@ void ath9k_hw_txstart(struct ath_hw *ah,
31417 }
31418 EXPORT_SYMBOL(ath9k_hw_txstart);
31419
31420 +void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
31421 +{
31422 + struct ar5416_desc *ads = AR5416DESC(ds);
31423 +
31424 + ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
31425 + ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
31426 + ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
31427 + ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
31428 + ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
31429 +}
31430 +EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
31431 +
31432 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
31433 {
31434 u32 npend;
31435 @@ -207,281 +219,6 @@ bool ath9k_hw_stoptxdma(struct ath_hw *a
31436 }
31437 EXPORT_SYMBOL(ath9k_hw_stoptxdma);
31438
31439 -void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
31440 - u32 segLen, bool firstSeg,
31441 - bool lastSeg, const struct ath_desc *ds0)
31442 -{
31443 - struct ar5416_desc *ads = AR5416DESC(ds);
31444 -
31445 - if (firstSeg) {
31446 - ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
31447 - } else if (lastSeg) {
31448 - ads->ds_ctl0 = 0;
31449 - ads->ds_ctl1 = segLen;
31450 - ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
31451 - ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
31452 - } else {
31453 - ads->ds_ctl0 = 0;
31454 - ads->ds_ctl1 = segLen | AR_TxMore;
31455 - ads->ds_ctl2 = 0;
31456 - ads->ds_ctl3 = 0;
31457 - }
31458 - ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
31459 - ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
31460 - ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
31461 - ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
31462 - ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
31463 -}
31464 -EXPORT_SYMBOL(ath9k_hw_filltxdesc);
31465 -
31466 -void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
31467 -{
31468 - struct ar5416_desc *ads = AR5416DESC(ds);
31469 -
31470 - ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
31471 - ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
31472 - ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
31473 - ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
31474 - ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
31475 -}
31476 -EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
31477 -
31478 -int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds,
31479 - struct ath_tx_status *ts)
31480 -{
31481 - struct ar5416_desc *ads = AR5416DESC(ds);
31482 -
31483 - if ((ads->ds_txstatus9 & AR_TxDone) == 0)
31484 - return -EINPROGRESS;
31485 -
31486 - ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
31487 - ts->ts_tstamp = ads->AR_SendTimestamp;
31488 - ts->ts_status = 0;
31489 - ts->ts_flags = 0;
31490 -
31491 - if (ads->ds_txstatus1 & AR_FrmXmitOK)
31492 - ts->ts_status |= ATH9K_TX_ACKED;
31493 - if (ads->ds_txstatus1 & AR_ExcessiveRetries)
31494 - ts->ts_status |= ATH9K_TXERR_XRETRY;
31495 - if (ads->ds_txstatus1 & AR_Filtered)
31496 - ts->ts_status |= ATH9K_TXERR_FILT;
31497 - if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
31498 - ts->ts_status |= ATH9K_TXERR_FIFO;
31499 - ath9k_hw_updatetxtriglevel(ah, true);
31500 - }
31501 - if (ads->ds_txstatus9 & AR_TxOpExceeded)
31502 - ts->ts_status |= ATH9K_TXERR_XTXOP;
31503 - if (ads->ds_txstatus1 & AR_TxTimerExpired)
31504 - ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
31505 -
31506 - if (ads->ds_txstatus1 & AR_DescCfgErr)
31507 - ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
31508 - if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
31509 - ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
31510 - ath9k_hw_updatetxtriglevel(ah, true);
31511 - }
31512 - if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
31513 - ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
31514 - ath9k_hw_updatetxtriglevel(ah, true);
31515 - }
31516 - if (ads->ds_txstatus0 & AR_TxBaStatus) {
31517 - ts->ts_flags |= ATH9K_TX_BA;
31518 - ts->ba_low = ads->AR_BaBitmapLow;
31519 - ts->ba_high = ads->AR_BaBitmapHigh;
31520 - }
31521 -
31522 - ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
31523 - switch (ts->ts_rateindex) {
31524 - case 0:
31525 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
31526 - break;
31527 - case 1:
31528 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
31529 - break;
31530 - case 2:
31531 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
31532 - break;
31533 - case 3:
31534 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
31535 - break;
31536 - }
31537 -
31538 - ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
31539 - ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
31540 - ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
31541 - ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
31542 - ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
31543 - ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
31544 - ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
31545 - ts->evm0 = ads->AR_TxEVM0;
31546 - ts->evm1 = ads->AR_TxEVM1;
31547 - ts->evm2 = ads->AR_TxEVM2;
31548 - ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
31549 - ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
31550 - ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
31551 - ts->ts_antenna = 0;
31552 -
31553 - return 0;
31554 -}
31555 -EXPORT_SYMBOL(ath9k_hw_txprocdesc);
31556 -
31557 -void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
31558 - u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
31559 - u32 keyIx, enum ath9k_key_type keyType, u32 flags)
31560 -{
31561 - struct ar5416_desc *ads = AR5416DESC(ds);
31562 -
31563 - txPower += ah->txpower_indexoffset;
31564 - if (txPower > 63)
31565 - txPower = 63;
31566 -
31567 - ads->ds_ctl0 = (pktLen & AR_FrameLen)
31568 - | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
31569 - | SM(txPower, AR_XmitPower)
31570 - | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
31571 - | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
31572 - | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
31573 - | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
31574 -
31575 - ads->ds_ctl1 =
31576 - (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
31577 - | SM(type, AR_FrameType)
31578 - | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
31579 - | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
31580 - | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
31581 -
31582 - ads->ds_ctl6 = SM(keyType, AR_EncrType);
31583 -
31584 - if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
31585 - ads->ds_ctl8 = 0;
31586 - ads->ds_ctl9 = 0;
31587 - ads->ds_ctl10 = 0;
31588 - ads->ds_ctl11 = 0;
31589 - }
31590 -}
31591 -EXPORT_SYMBOL(ath9k_hw_set11n_txdesc);
31592 -
31593 -void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
31594 - struct ath_desc *lastds,
31595 - u32 durUpdateEn, u32 rtsctsRate,
31596 - u32 rtsctsDuration,
31597 - struct ath9k_11n_rate_series series[],
31598 - u32 nseries, u32 flags)
31599 -{
31600 - struct ar5416_desc *ads = AR5416DESC(ds);
31601 - struct ar5416_desc *last_ads = AR5416DESC(lastds);
31602 - u32 ds_ctl0;
31603 -
31604 - if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
31605 - ds_ctl0 = ads->ds_ctl0;
31606 -
31607 - if (flags & ATH9K_TXDESC_RTSENA) {
31608 - ds_ctl0 &= ~AR_CTSEnable;
31609 - ds_ctl0 |= AR_RTSEnable;
31610 - } else {
31611 - ds_ctl0 &= ~AR_RTSEnable;
31612 - ds_ctl0 |= AR_CTSEnable;
31613 - }
31614 -
31615 - ads->ds_ctl0 = ds_ctl0;
31616 - } else {
31617 - ads->ds_ctl0 =
31618 - (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
31619 - }
31620 -
31621 - ads->ds_ctl2 = set11nTries(series, 0)
31622 - | set11nTries(series, 1)
31623 - | set11nTries(series, 2)
31624 - | set11nTries(series, 3)
31625 - | (durUpdateEn ? AR_DurUpdateEna : 0)
31626 - | SM(0, AR_BurstDur);
31627 -
31628 - ads->ds_ctl3 = set11nRate(series, 0)
31629 - | set11nRate(series, 1)
31630 - | set11nRate(series, 2)
31631 - | set11nRate(series, 3);
31632 -
31633 - ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
31634 - | set11nPktDurRTSCTS(series, 1);
31635 -
31636 - ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
31637 - | set11nPktDurRTSCTS(series, 3);
31638 -
31639 - ads->ds_ctl7 = set11nRateFlags(series, 0)
31640 - | set11nRateFlags(series, 1)
31641 - | set11nRateFlags(series, 2)
31642 - | set11nRateFlags(series, 3)
31643 - | SM(rtsctsRate, AR_RTSCTSRate);
31644 - last_ads->ds_ctl2 = ads->ds_ctl2;
31645 - last_ads->ds_ctl3 = ads->ds_ctl3;
31646 -}
31647 -EXPORT_SYMBOL(ath9k_hw_set11n_ratescenario);
31648 -
31649 -void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
31650 - u32 aggrLen)
31651 -{
31652 - struct ar5416_desc *ads = AR5416DESC(ds);
31653 -
31654 - ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
31655 - ads->ds_ctl6 &= ~AR_AggrLen;
31656 - ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
31657 -}
31658 -EXPORT_SYMBOL(ath9k_hw_set11n_aggr_first);
31659 -
31660 -void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
31661 - u32 numDelims)
31662 -{
31663 - struct ar5416_desc *ads = AR5416DESC(ds);
31664 - unsigned int ctl6;
31665 -
31666 - ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
31667 -
31668 - ctl6 = ads->ds_ctl6;
31669 - ctl6 &= ~AR_PadDelim;
31670 - ctl6 |= SM(numDelims, AR_PadDelim);
31671 - ads->ds_ctl6 = ctl6;
31672 -}
31673 -EXPORT_SYMBOL(ath9k_hw_set11n_aggr_middle);
31674 -
31675 -void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
31676 -{
31677 - struct ar5416_desc *ads = AR5416DESC(ds);
31678 -
31679 - ads->ds_ctl1 |= AR_IsAggr;
31680 - ads->ds_ctl1 &= ~AR_MoreAggr;
31681 - ads->ds_ctl6 &= ~AR_PadDelim;
31682 -}
31683 -EXPORT_SYMBOL(ath9k_hw_set11n_aggr_last);
31684 -
31685 -void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
31686 -{
31687 - struct ar5416_desc *ads = AR5416DESC(ds);
31688 -
31689 - ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
31690 -}
31691 -EXPORT_SYMBOL(ath9k_hw_clr11n_aggr);
31692 -
31693 -void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
31694 - u32 burstDuration)
31695 -{
31696 - struct ar5416_desc *ads = AR5416DESC(ds);
31697 -
31698 - ads->ds_ctl2 &= ~AR_BurstDur;
31699 - ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
31700 -}
31701 -EXPORT_SYMBOL(ath9k_hw_set11n_burstduration);
31702 -
31703 -void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
31704 - u32 vmf)
31705 -{
31706 - struct ar5416_desc *ads = AR5416DESC(ds);
31707 -
31708 - if (vmf)
31709 - ads->ds_ctl0 |= AR_VirtMoreFrag;
31710 - else
31711 - ads->ds_ctl0 &= ~AR_VirtMoreFrag;
31712 -}
31713 -
31714 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
31715 {
31716 *txqs &= ah->intr_txqs;
31717 @@ -796,6 +533,12 @@ bool ath9k_hw_resettxqueue(struct ath_hw
31718 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
31719 | AR_D_MISC_BEACON_USE
31720 | AR_D_MISC_POST_FR_BKOFF_DIS);
31721 + /* cwmin and cwmax should be 0 for beacon queue */
31722 + if (AR_SREV_9300_20_OR_LATER(ah)) {
31723 + REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
31724 + | SM(0, AR_D_LCL_IFS_CWMAX)
31725 + | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
31726 + }
31727 break;
31728 case ATH9K_TX_QUEUE_CAB:
31729 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
31730 @@ -832,6 +575,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw
31731 AR_D_MISC_POST_FR_BKOFF_DIS);
31732 }
31733
31734 + if (AR_SREV_9300_20_OR_LATER(ah))
31735 + REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
31736 +
31737 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
31738 ah->txok_interrupt_mask |= 1 << q;
31739 else
31740 @@ -999,12 +745,6 @@ void ath9k_hw_putrxbuf(struct ath_hw *ah
31741 }
31742 EXPORT_SYMBOL(ath9k_hw_putrxbuf);
31743
31744 -void ath9k_hw_rxena(struct ath_hw *ah)
31745 -{
31746 - REG_WRITE(ah, AR_CR, AR_CR_RXE);
31747 -}
31748 -EXPORT_SYMBOL(ath9k_hw_rxena);
31749 -
31750 void ath9k_hw_startpcureceive(struct ath_hw *ah)
31751 {
31752 ath9k_enable_mib_counters(ah);
31753 @@ -1023,6 +763,14 @@ void ath9k_hw_stoppcurecv(struct ath_hw
31754 }
31755 EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
31756
31757 +void ath9k_hw_abortpcurecv(struct ath_hw *ah)
31758 +{
31759 + REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
31760 +
31761 + ath9k_hw_disable_mib_counters(ah);
31762 +}
31763 +EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
31764 +
31765 bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
31766 {
31767 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
31768 @@ -1068,3 +816,140 @@ int ath9k_hw_beaconq_setup(struct ath_hw
31769 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
31770 }
31771 EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
31772 +
31773 +bool ath9k_hw_intrpend(struct ath_hw *ah)
31774 +{
31775 + u32 host_isr;
31776 +
31777 + if (AR_SREV_9100(ah))
31778 + return true;
31779 +
31780 + host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
31781 + if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
31782 + return true;
31783 +
31784 + host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
31785 + if ((host_isr & AR_INTR_SYNC_DEFAULT)
31786 + && (host_isr != AR_INTR_SPURIOUS))
31787 + return true;
31788 +
31789 + return false;
31790 +}
31791 +EXPORT_SYMBOL(ath9k_hw_intrpend);
31792 +
31793 +enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
31794 + enum ath9k_int ints)
31795 +{
31796 + enum ath9k_int omask = ah->imask;
31797 + u32 mask, mask2;
31798 + struct ath9k_hw_capabilities *pCap = &ah->caps;
31799 + struct ath_common *common = ath9k_hw_common(ah);
31800 +
31801 + ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
31802 +
31803 + if (omask & ATH9K_INT_GLOBAL) {
31804 + ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
31805 + REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
31806 + (void) REG_READ(ah, AR_IER);
31807 + if (!AR_SREV_9100(ah)) {
31808 + REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
31809 + (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
31810 +
31811 + REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
31812 + (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
31813 + }
31814 + }
31815 +
31816 + /* TODO: global int Ref count */
31817 + mask = ints & ATH9K_INT_COMMON;
31818 + mask2 = 0;
31819 +
31820 + if (ints & ATH9K_INT_TX) {
31821 + if (ah->config.tx_intr_mitigation)
31822 + mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
31823 + if (ah->txok_interrupt_mask)
31824 + mask |= AR_IMR_TXOK;
31825 + if (ah->txdesc_interrupt_mask)
31826 + mask |= AR_IMR_TXDESC;
31827 + if (ah->txerr_interrupt_mask)
31828 + mask |= AR_IMR_TXERR;
31829 + if (ah->txeol_interrupt_mask)
31830 + mask |= AR_IMR_TXEOL;
31831 + }
31832 + if (ints & ATH9K_INT_RX) {
31833 + if (AR_SREV_9300_20_OR_LATER(ah)) {
31834 + mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
31835 + if (ah->config.rx_intr_mitigation) {
31836 + mask &= ~AR_IMR_RXOK_LP;
31837 + mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
31838 + } else {
31839 + mask |= AR_IMR_RXOK_LP;
31840 + }
31841 + } else {
31842 + if (ah->config.rx_intr_mitigation)
31843 + mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
31844 + else
31845 + mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
31846 + }
31847 + if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
31848 + mask |= AR_IMR_GENTMR;
31849 + }
31850 +
31851 + if (ints & (ATH9K_INT_BMISC)) {
31852 + mask |= AR_IMR_BCNMISC;
31853 + if (ints & ATH9K_INT_TIM)
31854 + mask2 |= AR_IMR_S2_TIM;
31855 + if (ints & ATH9K_INT_DTIM)
31856 + mask2 |= AR_IMR_S2_DTIM;
31857 + if (ints & ATH9K_INT_DTIMSYNC)
31858 + mask2 |= AR_IMR_S2_DTIMSYNC;
31859 + if (ints & ATH9K_INT_CABEND)
31860 + mask2 |= AR_IMR_S2_CABEND;
31861 + if (ints & ATH9K_INT_TSFOOR)
31862 + mask2 |= AR_IMR_S2_TSFOOR;
31863 + }
31864 +
31865 + if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
31866 + mask |= AR_IMR_BCNMISC;
31867 + if (ints & ATH9K_INT_GTT)
31868 + mask2 |= AR_IMR_S2_GTT;
31869 + if (ints & ATH9K_INT_CST)
31870 + mask2 |= AR_IMR_S2_CST;
31871 + }
31872 +
31873 + ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
31874 + REG_WRITE(ah, AR_IMR, mask);
31875 + ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
31876 + AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
31877 + AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
31878 + ah->imrs2_reg |= mask2;
31879 + REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
31880 +
31881 + if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
31882 + if (ints & ATH9K_INT_TIM_TIMER)
31883 + REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
31884 + else
31885 + REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
31886 + }
31887 +
31888 + if (ints & ATH9K_INT_GLOBAL) {
31889 + ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
31890 + REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
31891 + if (!AR_SREV_9100(ah)) {
31892 + REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
31893 + AR_INTR_MAC_IRQ);
31894 + REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
31895 +
31896 +
31897 + REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
31898 + AR_INTR_SYNC_DEFAULT);
31899 + REG_WRITE(ah, AR_INTR_SYNC_MASK,
31900 + AR_INTR_SYNC_DEFAULT);
31901 + }
31902 + ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
31903 + REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
31904 + }
31905 +
31906 + return omask;
31907 +}
31908 +EXPORT_SYMBOL(ath9k_hw_set_interrupts);
31909 --- a/drivers/net/wireless/ath/ath9k/mac.h
31910 +++ b/drivers/net/wireless/ath/ath9k/mac.h
31911 @@ -86,7 +86,6 @@
31912 #define ATH9K_TX_DESC_CFG_ERR 0x04
31913 #define ATH9K_TX_DATA_UNDERRUN 0x08
31914 #define ATH9K_TX_DELIM_UNDERRUN 0x10
31915 -#define ATH9K_TX_SW_ABORTED 0x40
31916 #define ATH9K_TX_SW_FILTERED 0x80
31917
31918 /* 64 bytes */
31919 @@ -117,7 +116,10 @@ struct ath_tx_status {
31920 int8_t ts_rssi_ext0;
31921 int8_t ts_rssi_ext1;
31922 int8_t ts_rssi_ext2;
31923 - u8 pad[3];
31924 + u8 qid;
31925 + u16 desc_id;
31926 + u8 tid;
31927 + u8 pad[2];
31928 u32 ba_low;
31929 u32 ba_high;
31930 u32 evm0;
31931 @@ -148,6 +150,8 @@ struct ath_rx_status {
31932 u32 evm0;
31933 u32 evm1;
31934 u32 evm2;
31935 + u32 evm3;
31936 + u32 evm4;
31937 };
31938
31939 struct ath_htc_rx_status {
31940 @@ -259,7 +263,8 @@ struct ath_desc {
31941 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
31942 #define ATH9K_TXDESC_VMF 0x0100
31943 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
31944 -#define ATH9K_TXDESC_CAB 0x0400
31945 +#define ATH9K_TXDESC_LOWRXCHAIN 0x0400
31946 +#define ATH9K_TXDESC_LDPC 0x00010000
31947
31948 #define ATH9K_RXDESC_INTREQ 0x0020
31949
31950 @@ -353,7 +358,8 @@ struct ar5416_desc {
31951 #define AR_DestIdxValid 0x40000000
31952 #define AR_CTSEnable 0x80000000
31953
31954 -#define AR_BufLen 0x00000fff
31955 +#define AR_BufLen AR_SREV_9300_20_OR_LATER(ah) ? 0x0fff0000 : \
31956 + 0x00000fff
31957 #define AR_TxMore 0x00001000
31958 #define AR_DestIdx 0x000fe000
31959 #define AR_DestIdx_S 13
31960 @@ -410,6 +416,7 @@ struct ar5416_desc {
31961 #define AR_EncrType 0x0c000000
31962 #define AR_EncrType_S 26
31963 #define AR_TxCtlRsvd61 0xf0000000
31964 +#define AR_LDPC 0x80000000
31965
31966 #define AR_2040_0 0x00000001
31967 #define AR_GI0 0x00000002
31968 @@ -493,7 +500,6 @@ struct ar5416_desc {
31969
31970 #define AR_RxCTLRsvd00 0xffffffff
31971
31972 -#define AR_BufLen 0x00000fff
31973 #define AR_RxCtlRsvd00 0x00001000
31974 #define AR_RxIntrReq 0x00002000
31975 #define AR_RxCtlRsvd01 0xffffc000
31976 @@ -686,34 +692,10 @@ struct ath9k_channel;
31977 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
31978 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
31979 void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
31980 +void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds);
31981 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
31982 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
31983 bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
31984 -void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
31985 - u32 segLen, bool firstSeg,
31986 - bool lastSeg, const struct ath_desc *ds0);
31987 -void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds);
31988 -int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds,
31989 - struct ath_tx_status *ts);
31990 -void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
31991 - u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
31992 - u32 keyIx, enum ath9k_key_type keyType, u32 flags);
31993 -void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
31994 - struct ath_desc *lastds,
31995 - u32 durUpdateEn, u32 rtsctsRate,
31996 - u32 rtsctsDuration,
31997 - struct ath9k_11n_rate_series series[],
31998 - u32 nseries, u32 flags);
31999 -void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
32000 - u32 aggrLen);
32001 -void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
32002 - u32 numDelims);
32003 -void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds);
32004 -void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds);
32005 -void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
32006 - u32 burstDuration);
32007 -void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
32008 - u32 vmf);
32009 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
32010 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
32011 const struct ath9k_tx_queue_info *qinfo);
32012 @@ -729,10 +711,17 @@ void ath9k_hw_setuprxdesc(struct ath_hw
32013 u32 size, u32 flags);
32014 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
32015 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
32016 -void ath9k_hw_rxena(struct ath_hw *ah);
32017 void ath9k_hw_startpcureceive(struct ath_hw *ah);
32018 void ath9k_hw_stoppcurecv(struct ath_hw *ah);
32019 +void ath9k_hw_abortpcurecv(struct ath_hw *ah);
32020 bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
32021 int ath9k_hw_beaconq_setup(struct ath_hw *ah);
32022
32023 +/* Interrupt Handling */
32024 +bool ath9k_hw_intrpend(struct ath_hw *ah);
32025 +enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
32026 + enum ath9k_int ints);
32027 +
32028 +void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
32029 +
32030 #endif /* MAC_H */
32031 --- a/drivers/net/wireless/ath/ath9k/main.c
32032 +++ b/drivers/net/wireless/ath/ath9k/main.c
32033 @@ -401,6 +401,7 @@ void ath9k_tasklet(unsigned long data)
32034 struct ath_common *common = ath9k_hw_common(ah);
32035
32036 u32 status = sc->intrstatus;
32037 + u32 rxmask;
32038
32039 ath9k_ps_wakeup(sc);
32040
32041 @@ -410,14 +411,30 @@ void ath9k_tasklet(unsigned long data)
32042 return;
32043 }
32044
32045 - if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
32046 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
32047 + rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
32048 + ATH9K_INT_RXORN);
32049 + else
32050 + rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
32051 +
32052 + if (status & rxmask) {
32053 spin_lock_bh(&sc->rx.rxflushlock);
32054 - ath_rx_tasklet(sc, 0);
32055 +
32056 + /* Check for high priority Rx first */
32057 + if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
32058 + (status & ATH9K_INT_RXHP))
32059 + ath_rx_tasklet(sc, 0, true);
32060 +
32061 + ath_rx_tasklet(sc, 0, false);
32062 spin_unlock_bh(&sc->rx.rxflushlock);
32063 }
32064
32065 - if (status & ATH9K_INT_TX)
32066 - ath_tx_tasklet(sc);
32067 + if (status & ATH9K_INT_TX) {
32068 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
32069 + ath_tx_edma_tasklet(sc);
32070 + else
32071 + ath_tx_tasklet(sc);
32072 + }
32073
32074 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
32075 /*
32076 @@ -445,6 +462,8 @@ irqreturn_t ath_isr(int irq, void *dev)
32077 ATH9K_INT_RXORN | \
32078 ATH9K_INT_RXEOL | \
32079 ATH9K_INT_RX | \
32080 + ATH9K_INT_RXLP | \
32081 + ATH9K_INT_RXHP | \
32082 ATH9K_INT_TX | \
32083 ATH9K_INT_BMISS | \
32084 ATH9K_INT_CST | \
32085 @@ -496,7 +515,8 @@ irqreturn_t ath_isr(int irq, void *dev)
32086 * If a FATAL or RXORN interrupt is received, we have to reset the
32087 * chip immediately.
32088 */
32089 - if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
32090 + if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
32091 + !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
32092 goto chip_reset;
32093
32094 if (status & ATH9K_INT_SWBA)
32095 @@ -505,6 +525,13 @@ irqreturn_t ath_isr(int irq, void *dev)
32096 if (status & ATH9K_INT_TXURN)
32097 ath9k_hw_updatetxtriglevel(ah, true);
32098
32099 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
32100 + if (status & ATH9K_INT_RXEOL) {
32101 + ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
32102 + ath9k_hw_set_interrupts(ah, ah->imask);
32103 + }
32104 + }
32105 +
32106 if (status & ATH9K_INT_MIB) {
32107 /*
32108 * Disable interrupts until we service the MIB
32109 @@ -1162,9 +1189,14 @@ static int ath9k_start(struct ieee80211_
32110 }
32111
32112 /* Setup our intr mask. */
32113 - ah->imask = ATH9K_INT_RX | ATH9K_INT_TX
32114 - | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
32115 - | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
32116 + ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
32117 + ATH9K_INT_RXORN | ATH9K_INT_FATAL |
32118 + ATH9K_INT_GLOBAL;
32119 +
32120 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
32121 + ah->imask |= ATH9K_INT_RXHP | ATH9K_INT_RXLP;
32122 + else
32123 + ah->imask |= ATH9K_INT_RX;
32124
32125 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
32126 ah->imask |= ATH9K_INT_GTT;
32127 --- a/drivers/net/wireless/ath/ath9k/pci.c
32128 +++ b/drivers/net/wireless/ath/ath9k/pci.c
32129 @@ -28,6 +28,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_i
32130 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
32131 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
32132 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
32133 + { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
32134 { 0 }
32135 };
32136
32137 --- a/drivers/net/wireless/ath/ath9k/phy.c
32138 +++ /dev/null
32139 @@ -1,978 +0,0 @@
32140 -/*
32141 - * Copyright (c) 2008-2009 Atheros Communications Inc.
32142 - *
32143 - * Permission to use, copy, modify, and/or distribute this software for any
32144 - * purpose with or without fee is hereby granted, provided that the above
32145 - * copyright notice and this permission notice appear in all copies.
32146 - *
32147 - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
32148 - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
32149 - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
32150 - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
32151 - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
32152 - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
32153 - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
32154 - */
32155 -
32156 -/**
32157 - * DOC: Programming Atheros 802.11n analog front end radios
32158 - *
32159 - * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
32160 - * devices have either an external AR2133 analog front end radio for single
32161 - * band 2.4 GHz communication or an AR5133 analog front end radio for dual
32162 - * band 2.4 GHz / 5 GHz communication.
32163 - *
32164 - * All devices after the AR5416 and AR5418 family starting with the AR9280
32165 - * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
32166 - * into a single-chip and require less programming.
32167 - *
32168 - * The following single-chips exist with a respective embedded radio:
32169 - *
32170 - * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32171 - * AR9281 - 11n single-band 1x2 MIMO for PCIe
32172 - * AR9285 - 11n single-band 1x1 for PCIe
32173 - * AR9287 - 11n single-band 2x2 MIMO for PCIe
32174 - *
32175 - * AR9220 - 11n dual-band 2x2 MIMO for PCI
32176 - * AR9223 - 11n single-band 2x2 MIMO for PCI
32177 - *
32178 - * AR9287 - 11n single-band 1x1 MIMO for USB
32179 - */
32180 -
32181 -#include <linux/slab.h>
32182 -
32183 -#include "hw.h"
32184 -
32185 -/**
32186 - * ath9k_hw_write_regs - ??
32187 - *
32188 - * @ah: atheros hardware structure
32189 - * @freqIndex:
32190 - * @regWrites:
32191 - *
32192 - * Used for both the chipsets with an external AR2133/AR5133 radios and
32193 - * single-chip devices.
32194 - */
32195 -void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites)
32196 -{
32197 - REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
32198 -}
32199 -
32200 -/**
32201 - * ath9k_hw_ar9280_set_channel - set channel on single-chip device
32202 - * @ah: atheros hardware structure
32203 - * @chan:
32204 - *
32205 - * This is the function to change channel on single-chip devices, that is
32206 - * all devices after ar9280.
32207 - *
32208 - * This function takes the channel value in MHz and sets
32209 - * hardware channel value. Assumes writes have been enabled to analog bus.
32210 - *
32211 - * Actual Expression,
32212 - *
32213 - * For 2GHz channel,
32214 - * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
32215 - * (freq_ref = 40MHz)
32216 - *
32217 - * For 5GHz channel,
32218 - * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
32219 - * (freq_ref = 40MHz/(24>>amodeRefSel))
32220 - */
32221 -int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
32222 -{
32223 - u16 bMode, fracMode, aModeRefSel = 0;
32224 - u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
32225 - struct chan_centers centers;
32226 - u32 refDivA = 24;
32227 -
32228 - ath9k_hw_get_channel_centers(ah, chan, &centers);
32229 - freq = centers.synth_center;
32230 -
32231 - reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
32232 - reg32 &= 0xc0000000;
32233 -
32234 - if (freq < 4800) { /* 2 GHz, fractional mode */
32235 - u32 txctl;
32236 - int regWrites = 0;
32237 -
32238 - bMode = 1;
32239 - fracMode = 1;
32240 - aModeRefSel = 0;
32241 - channelSel = (freq * 0x10000) / 15;
32242 -
32243 - if (AR_SREV_9287_11_OR_LATER(ah)) {
32244 - if (freq == 2484) {
32245 - /* Enable channel spreading for channel 14 */
32246 - REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
32247 - 1, regWrites);
32248 - } else {
32249 - REG_WRITE_ARRAY(&ah->iniCckfirNormal,
32250 - 1, regWrites);
32251 - }
32252 - } else {
32253 - txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
32254 - if (freq == 2484) {
32255 - /* Enable channel spreading for channel 14 */
32256 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
32257 - txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
32258 - } else {
32259 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
32260 - txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
32261 - }
32262 - }
32263 - } else {
32264 - bMode = 0;
32265 - fracMode = 0;
32266 -
32267 - switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
32268 - case 0:
32269 - if ((freq % 20) == 0) {
32270 - aModeRefSel = 3;
32271 - } else if ((freq % 10) == 0) {
32272 - aModeRefSel = 2;
32273 - }
32274 - if (aModeRefSel)
32275 - break;
32276 - case 1:
32277 - default:
32278 - aModeRefSel = 0;
32279 - /*
32280 - * Enable 2G (fractional) mode for channels
32281 - * which are 5MHz spaced.
32282 - */
32283 - fracMode = 1;
32284 - refDivA = 1;
32285 - channelSel = (freq * 0x8000) / 15;
32286 -
32287 - /* RefDivA setting */
32288 - REG_RMW_FIELD(ah, AR_AN_SYNTH9,
32289 - AR_AN_SYNTH9_REFDIVA, refDivA);
32290 -
32291 - }
32292 -
32293 - if (!fracMode) {
32294 - ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
32295 - channelSel = ndiv & 0x1ff;
32296 - channelFrac = (ndiv & 0xfffffe00) * 2;
32297 - channelSel = (channelSel << 17) | channelFrac;
32298 - }
32299 - }
32300 -
32301 - reg32 = reg32 |
32302 - (bMode << 29) |
32303 - (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
32304 -
32305 - REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
32306 -
32307 - ah->curchan = chan;
32308 - ah->curchan_rad_index = -1;
32309 -
32310 - return 0;
32311 -}
32312 -
32313 -/**
32314 - * ath9k_hw_9280_spur_mitigate - convert baseband spur frequency
32315 - * @ah: atheros hardware structure
32316 - * @chan:
32317 - *
32318 - * For single-chip solutions. Converts to baseband spur frequency given the
32319 - * input channel frequency and compute register settings below.
32320 - */
32321 -void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
32322 -{
32323 - int bb_spur = AR_NO_SPUR;
32324 - int freq;
32325 - int bin, cur_bin;
32326 - int bb_spur_off, spur_subchannel_sd;
32327 - int spur_freq_sd;
32328 - int spur_delta_phase;
32329 - int denominator;
32330 - int upper, lower, cur_vit_mask;
32331 - int tmp, newVal;
32332 - int i;
32333 - int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
32334 - AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
32335 - };
32336 - int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
32337 - AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
32338 - };
32339 - int inc[4] = { 0, 100, 0, 0 };
32340 - struct chan_centers centers;
32341 -
32342 - int8_t mask_m[123];
32343 - int8_t mask_p[123];
32344 - int8_t mask_amt;
32345 - int tmp_mask;
32346 - int cur_bb_spur;
32347 - bool is2GHz = IS_CHAN_2GHZ(chan);
32348 -
32349 - memset(&mask_m, 0, sizeof(int8_t) * 123);
32350 - memset(&mask_p, 0, sizeof(int8_t) * 123);
32351 -
32352 - ath9k_hw_get_channel_centers(ah, chan, &centers);
32353 - freq = centers.synth_center;
32354 -
32355 - ah->config.spurmode = SPUR_ENABLE_EEPROM;
32356 - for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
32357 - cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
32358 -
32359 - if (is2GHz)
32360 - cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
32361 - else
32362 - cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
32363 -
32364 - if (AR_NO_SPUR == cur_bb_spur)
32365 - break;
32366 - cur_bb_spur = cur_bb_spur - freq;
32367 -
32368 - if (IS_CHAN_HT40(chan)) {
32369 - if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
32370 - (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
32371 - bb_spur = cur_bb_spur;
32372 - break;
32373 - }
32374 - } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
32375 - (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
32376 - bb_spur = cur_bb_spur;
32377 - break;
32378 - }
32379 - }
32380 -
32381 - if (AR_NO_SPUR == bb_spur) {
32382 - REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
32383 - AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
32384 - return;
32385 - } else {
32386 - REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
32387 - AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
32388 - }
32389 -
32390 - bin = bb_spur * 320;
32391 -
32392 - tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
32393 -
32394 - newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
32395 - AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
32396 - AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
32397 - AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
32398 - REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
32399 -
32400 - newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
32401 - AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
32402 - AR_PHY_SPUR_REG_MASK_RATE_SELECT |
32403 - AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
32404 - SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
32405 - REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
32406 -
32407 - if (IS_CHAN_HT40(chan)) {
32408 - if (bb_spur < 0) {
32409 - spur_subchannel_sd = 1;
32410 - bb_spur_off = bb_spur + 10;
32411 - } else {
32412 - spur_subchannel_sd = 0;
32413 - bb_spur_off = bb_spur - 10;
32414 - }
32415 - } else {
32416 - spur_subchannel_sd = 0;
32417 - bb_spur_off = bb_spur;
32418 - }
32419 -
32420 - if (IS_CHAN_HT40(chan))
32421 - spur_delta_phase =
32422 - ((bb_spur * 262144) /
32423 - 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
32424 - else
32425 - spur_delta_phase =
32426 - ((bb_spur * 524288) /
32427 - 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
32428 -
32429 - denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
32430 - spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
32431 -
32432 - newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
32433 - SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
32434 - SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
32435 - REG_WRITE(ah, AR_PHY_TIMING11, newVal);
32436 -
32437 - newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
32438 - REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
32439 -
32440 - cur_bin = -6000;
32441 - upper = bin + 100;
32442 - lower = bin - 100;
32443 -
32444 - for (i = 0; i < 4; i++) {
32445 - int pilot_mask = 0;
32446 - int chan_mask = 0;
32447 - int bp = 0;
32448 - for (bp = 0; bp < 30; bp++) {
32449 - if ((cur_bin > lower) && (cur_bin < upper)) {
32450 - pilot_mask = pilot_mask | 0x1 << bp;
32451 - chan_mask = chan_mask | 0x1 << bp;
32452 - }
32453 - cur_bin += 100;
32454 - }
32455 - cur_bin += inc[i];
32456 - REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
32457 - REG_WRITE(ah, chan_mask_reg[i], chan_mask);
32458 - }
32459 -
32460 - cur_vit_mask = 6100;
32461 - upper = bin + 120;
32462 - lower = bin - 120;
32463 -
32464 - for (i = 0; i < 123; i++) {
32465 - if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
32466 -
32467 - /* workaround for gcc bug #37014 */
32468 - volatile int tmp_v = abs(cur_vit_mask - bin);
32469 -
32470 - if (tmp_v < 75)
32471 - mask_amt = 1;
32472 - else
32473 - mask_amt = 0;
32474 - if (cur_vit_mask < 0)
32475 - mask_m[abs(cur_vit_mask / 100)] = mask_amt;
32476 - else
32477 - mask_p[cur_vit_mask / 100] = mask_amt;
32478 - }
32479 - cur_vit_mask -= 100;
32480 - }
32481 -
32482 - tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
32483 - | (mask_m[48] << 26) | (mask_m[49] << 24)
32484 - | (mask_m[50] << 22) | (mask_m[51] << 20)
32485 - | (mask_m[52] << 18) | (mask_m[53] << 16)
32486 - | (mask_m[54] << 14) | (mask_m[55] << 12)
32487 - | (mask_m[56] << 10) | (mask_m[57] << 8)
32488 - | (mask_m[58] << 6) | (mask_m[59] << 4)
32489 - | (mask_m[60] << 2) | (mask_m[61] << 0);
32490 - REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
32491 - REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
32492 -
32493 - tmp_mask = (mask_m[31] << 28)
32494 - | (mask_m[32] << 26) | (mask_m[33] << 24)
32495 - | (mask_m[34] << 22) | (mask_m[35] << 20)
32496 - | (mask_m[36] << 18) | (mask_m[37] << 16)
32497 - | (mask_m[48] << 14) | (mask_m[39] << 12)
32498 - | (mask_m[40] << 10) | (mask_m[41] << 8)
32499 - | (mask_m[42] << 6) | (mask_m[43] << 4)
32500 - | (mask_m[44] << 2) | (mask_m[45] << 0);
32501 - REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
32502 - REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
32503 -
32504 - tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
32505 - | (mask_m[18] << 26) | (mask_m[18] << 24)
32506 - | (mask_m[20] << 22) | (mask_m[20] << 20)
32507 - | (mask_m[22] << 18) | (mask_m[22] << 16)
32508 - | (mask_m[24] << 14) | (mask_m[24] << 12)
32509 - | (mask_m[25] << 10) | (mask_m[26] << 8)
32510 - | (mask_m[27] << 6) | (mask_m[28] << 4)
32511 - | (mask_m[29] << 2) | (mask_m[30] << 0);
32512 - REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
32513 - REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
32514 -
32515 - tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
32516 - | (mask_m[2] << 26) | (mask_m[3] << 24)
32517 - | (mask_m[4] << 22) | (mask_m[5] << 20)
32518 - | (mask_m[6] << 18) | (mask_m[7] << 16)
32519 - | (mask_m[8] << 14) | (mask_m[9] << 12)
32520 - | (mask_m[10] << 10) | (mask_m[11] << 8)
32521 - | (mask_m[12] << 6) | (mask_m[13] << 4)
32522 - | (mask_m[14] << 2) | (mask_m[15] << 0);
32523 - REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
32524 - REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
32525 -
32526 - tmp_mask = (mask_p[15] << 28)
32527 - | (mask_p[14] << 26) | (mask_p[13] << 24)
32528 - | (mask_p[12] << 22) | (mask_p[11] << 20)
32529 - | (mask_p[10] << 18) | (mask_p[9] << 16)
32530 - | (mask_p[8] << 14) | (mask_p[7] << 12)
32531 - | (mask_p[6] << 10) | (mask_p[5] << 8)
32532 - | (mask_p[4] << 6) | (mask_p[3] << 4)
32533 - | (mask_p[2] << 2) | (mask_p[1] << 0);
32534 - REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
32535 - REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
32536 -
32537 - tmp_mask = (mask_p[30] << 28)
32538 - | (mask_p[29] << 26) | (mask_p[28] << 24)
32539 - | (mask_p[27] << 22) | (mask_p[26] << 20)
32540 - | (mask_p[25] << 18) | (mask_p[24] << 16)
32541 - | (mask_p[23] << 14) | (mask_p[22] << 12)
32542 - | (mask_p[21] << 10) | (mask_p[20] << 8)
32543 - | (mask_p[19] << 6) | (mask_p[18] << 4)
32544 - | (mask_p[17] << 2) | (mask_p[16] << 0);
32545 - REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
32546 - REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
32547 -
32548 - tmp_mask = (mask_p[45] << 28)
32549 - | (mask_p[44] << 26) | (mask_p[43] << 24)
32550 - | (mask_p[42] << 22) | (mask_p[41] << 20)
32551 - | (mask_p[40] << 18) | (mask_p[39] << 16)
32552 - | (mask_p[38] << 14) | (mask_p[37] << 12)
32553 - | (mask_p[36] << 10) | (mask_p[35] << 8)
32554 - | (mask_p[34] << 6) | (mask_p[33] << 4)
32555 - | (mask_p[32] << 2) | (mask_p[31] << 0);
32556 - REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
32557 - REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
32558 -
32559 - tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
32560 - | (mask_p[59] << 26) | (mask_p[58] << 24)
32561 - | (mask_p[57] << 22) | (mask_p[56] << 20)
32562 - | (mask_p[55] << 18) | (mask_p[54] << 16)
32563 - | (mask_p[53] << 14) | (mask_p[52] << 12)
32564 - | (mask_p[51] << 10) | (mask_p[50] << 8)
32565 - | (mask_p[49] << 6) | (mask_p[48] << 4)
32566 - | (mask_p[47] << 2) | (mask_p[46] << 0);
32567 - REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
32568 - REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
32569 -}
32570 -
32571 -/* All code below is for non single-chip solutions */
32572 -
32573 -/**
32574 - * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters
32575 - * @rfbuf:
32576 - * @reg32:
32577 - * @numBits:
32578 - * @firstBit:
32579 - * @column:
32580 - *
32581 - * Performs analog "swizzling" of parameters into their location.
32582 - * Used on external AR2133/AR5133 radios.
32583 - */
32584 -static void ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
32585 - u32 numBits, u32 firstBit,
32586 - u32 column)
32587 -{
32588 - u32 tmp32, mask, arrayEntry, lastBit;
32589 - int32_t bitPosition, bitsLeft;
32590 -
32591 - tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
32592 - arrayEntry = (firstBit - 1) / 8;
32593 - bitPosition = (firstBit - 1) % 8;
32594 - bitsLeft = numBits;
32595 - while (bitsLeft > 0) {
32596 - lastBit = (bitPosition + bitsLeft > 8) ?
32597 - 8 : bitPosition + bitsLeft;
32598 - mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
32599 - (column * 8);
32600 - rfBuf[arrayEntry] &= ~mask;
32601 - rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
32602 - (column * 8)) & mask;
32603 - bitsLeft -= 8 - bitPosition;
32604 - tmp32 = tmp32 >> (8 - bitPosition);
32605 - bitPosition = 0;
32606 - arrayEntry++;
32607 - }
32608 -}
32609 -
32610 -/*
32611 - * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
32612 - * rf_pwd_icsyndiv.
32613 - *
32614 - * Theoretical Rules:
32615 - * if 2 GHz band
32616 - * if forceBiasAuto
32617 - * if synth_freq < 2412
32618 - * bias = 0
32619 - * else if 2412 <= synth_freq <= 2422
32620 - * bias = 1
32621 - * else // synth_freq > 2422
32622 - * bias = 2
32623 - * else if forceBias > 0
32624 - * bias = forceBias & 7
32625 - * else
32626 - * no change, use value from ini file
32627 - * else
32628 - * no change, invalid band
32629 - *
32630 - * 1st Mod:
32631 - * 2422 also uses value of 2
32632 - * <approved>
32633 - *
32634 - * 2nd Mod:
32635 - * Less than 2412 uses value of 0, 2412 and above uses value of 2
32636 - */
32637 -static void ath9k_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
32638 -{
32639 - struct ath_common *common = ath9k_hw_common(ah);
32640 - u32 tmp_reg;
32641 - int reg_writes = 0;
32642 - u32 new_bias = 0;
32643 -
32644 - if (!AR_SREV_5416(ah) || synth_freq >= 3000) {
32645 - return;
32646 - }
32647 -
32648 - BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
32649 -
32650 - if (synth_freq < 2412)
32651 - new_bias = 0;
32652 - else if (synth_freq < 2422)
32653 - new_bias = 1;
32654 - else
32655 - new_bias = 2;
32656 -
32657 - /* pre-reverse this field */
32658 - tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
32659 -
32660 - ath_print(common, ATH_DBG_CONFIG,
32661 - "Force rf_pwd_icsyndiv to %1d on %4d\n",
32662 - new_bias, synth_freq);
32663 -
32664 - /* swizzle rf_pwd_icsyndiv */
32665 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
32666 -
32667 - /* write Bank 6 with new params */
32668 - REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
32669 -}
32670 -
32671 -/**
32672 - * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
32673 - * @ah: atheros hardware stucture
32674 - * @chan:
32675 - *
32676 - * For the external AR2133/AR5133 radios, takes the MHz channel value and set
32677 - * the channel value. Assumes writes enabled to analog bus and bank6 register
32678 - * cache in ah->analogBank6Data.
32679 - */
32680 -int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
32681 -{
32682 - struct ath_common *common = ath9k_hw_common(ah);
32683 - u32 channelSel = 0;
32684 - u32 bModeSynth = 0;
32685 - u32 aModeRefSel = 0;
32686 - u32 reg32 = 0;
32687 - u16 freq;
32688 - struct chan_centers centers;
32689 -
32690 - ath9k_hw_get_channel_centers(ah, chan, &centers);
32691 - freq = centers.synth_center;
32692 -
32693 - if (freq < 4800) {
32694 - u32 txctl;
32695 -
32696 - if (((freq - 2192) % 5) == 0) {
32697 - channelSel = ((freq - 672) * 2 - 3040) / 10;
32698 - bModeSynth = 0;
32699 - } else if (((freq - 2224) % 5) == 0) {
32700 - channelSel = ((freq - 704) * 2 - 3040) / 10;
32701 - bModeSynth = 1;
32702 - } else {
32703 - ath_print(common, ATH_DBG_FATAL,
32704 - "Invalid channel %u MHz\n", freq);
32705 - return -EINVAL;
32706 - }
32707 -
32708 - channelSel = (channelSel << 2) & 0xff;
32709 - channelSel = ath9k_hw_reverse_bits(channelSel, 8);
32710 -
32711 - txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
32712 - if (freq == 2484) {
32713 -
32714 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
32715 - txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
32716 - } else {
32717 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
32718 - txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
32719 - }
32720 -
32721 - } else if ((freq % 20) == 0 && freq >= 5120) {
32722 - channelSel =
32723 - ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
32724 - aModeRefSel = ath9k_hw_reverse_bits(1, 2);
32725 - } else if ((freq % 10) == 0) {
32726 - channelSel =
32727 - ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
32728 - if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
32729 - aModeRefSel = ath9k_hw_reverse_bits(2, 2);
32730 - else
32731 - aModeRefSel = ath9k_hw_reverse_bits(1, 2);
32732 - } else if ((freq % 5) == 0) {
32733 - channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
32734 - aModeRefSel = ath9k_hw_reverse_bits(1, 2);
32735 - } else {
32736 - ath_print(common, ATH_DBG_FATAL,
32737 - "Invalid channel %u MHz\n", freq);
32738 - return -EINVAL;
32739 - }
32740 -
32741 - ath9k_hw_force_bias(ah, freq);
32742 -
32743 - reg32 =
32744 - (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
32745 - (1 << 5) | 0x1;
32746 -
32747 - REG_WRITE(ah, AR_PHY(0x37), reg32);
32748 -
32749 - ah->curchan = chan;
32750 - ah->curchan_rad_index = -1;
32751 -
32752 - return 0;
32753 -}
32754 -
32755 -/**
32756 - * ath9k_hw_spur_mitigate - convert baseband spur frequency for external radios
32757 - * @ah: atheros hardware structure
32758 - * @chan:
32759 - *
32760 - * For non single-chip solutions. Converts to baseband spur frequency given the
32761 - * input channel frequency and compute register settings below.
32762 - */
32763 -void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
32764 -{
32765 - int bb_spur = AR_NO_SPUR;
32766 - int bin, cur_bin;
32767 - int spur_freq_sd;
32768 - int spur_delta_phase;
32769 - int denominator;
32770 - int upper, lower, cur_vit_mask;
32771 - int tmp, new;
32772 - int i;
32773 - int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
32774 - AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
32775 - };
32776 - int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
32777 - AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
32778 - };
32779 - int inc[4] = { 0, 100, 0, 0 };
32780 -
32781 - int8_t mask_m[123];
32782 - int8_t mask_p[123];
32783 - int8_t mask_amt;
32784 - int tmp_mask;
32785 - int cur_bb_spur;
32786 - bool is2GHz = IS_CHAN_2GHZ(chan);
32787 -
32788 - memset(&mask_m, 0, sizeof(int8_t) * 123);
32789 - memset(&mask_p, 0, sizeof(int8_t) * 123);
32790 -
32791 - for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
32792 - cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
32793 - if (AR_NO_SPUR == cur_bb_spur)
32794 - break;
32795 - cur_bb_spur = cur_bb_spur - (chan->channel * 10);
32796 - if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
32797 - bb_spur = cur_bb_spur;
32798 - break;
32799 - }
32800 - }
32801 -
32802 - if (AR_NO_SPUR == bb_spur)
32803 - return;
32804 -
32805 - bin = bb_spur * 32;
32806 -
32807 - tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
32808 - new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
32809 - AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
32810 - AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
32811 - AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
32812 -
32813 - REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
32814 -
32815 - new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
32816 - AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
32817 - AR_PHY_SPUR_REG_MASK_RATE_SELECT |
32818 - AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
32819 - SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
32820 - REG_WRITE(ah, AR_PHY_SPUR_REG, new);
32821 -
32822 - spur_delta_phase = ((bb_spur * 524288) / 100) &
32823 - AR_PHY_TIMING11_SPUR_DELTA_PHASE;
32824 -
32825 - denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
32826 - spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
32827 -
32828 - new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
32829 - SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
32830 - SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
32831 - REG_WRITE(ah, AR_PHY_TIMING11, new);
32832 -
32833 - cur_bin = -6000;
32834 - upper = bin + 100;
32835 - lower = bin - 100;
32836 -
32837 - for (i = 0; i < 4; i++) {
32838 - int pilot_mask = 0;
32839 - int chan_mask = 0;
32840 - int bp = 0;
32841 - for (bp = 0; bp < 30; bp++) {
32842 - if ((cur_bin > lower) && (cur_bin < upper)) {
32843 - pilot_mask = pilot_mask | 0x1 << bp;
32844 - chan_mask = chan_mask | 0x1 << bp;
32845 - }
32846 - cur_bin += 100;
32847 - }
32848 - cur_bin += inc[i];
32849 - REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
32850 - REG_WRITE(ah, chan_mask_reg[i], chan_mask);
32851 - }
32852 -
32853 - cur_vit_mask = 6100;
32854 - upper = bin + 120;
32855 - lower = bin - 120;
32856 -
32857 - for (i = 0; i < 123; i++) {
32858 - if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
32859 -
32860 - /* workaround for gcc bug #37014 */
32861 - volatile int tmp_v = abs(cur_vit_mask - bin);
32862 -
32863 - if (tmp_v < 75)
32864 - mask_amt = 1;
32865 - else
32866 - mask_amt = 0;
32867 - if (cur_vit_mask < 0)
32868 - mask_m[abs(cur_vit_mask / 100)] = mask_amt;
32869 - else
32870 - mask_p[cur_vit_mask / 100] = mask_amt;
32871 - }
32872 - cur_vit_mask -= 100;
32873 - }
32874 -
32875 - tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
32876 - | (mask_m[48] << 26) | (mask_m[49] << 24)
32877 - | (mask_m[50] << 22) | (mask_m[51] << 20)
32878 - | (mask_m[52] << 18) | (mask_m[53] << 16)
32879 - | (mask_m[54] << 14) | (mask_m[55] << 12)
32880 - | (mask_m[56] << 10) | (mask_m[57] << 8)
32881 - | (mask_m[58] << 6) | (mask_m[59] << 4)
32882 - | (mask_m[60] << 2) | (mask_m[61] << 0);
32883 - REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
32884 - REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
32885 -
32886 - tmp_mask = (mask_m[31] << 28)
32887 - | (mask_m[32] << 26) | (mask_m[33] << 24)
32888 - | (mask_m[34] << 22) | (mask_m[35] << 20)
32889 - | (mask_m[36] << 18) | (mask_m[37] << 16)
32890 - | (mask_m[48] << 14) | (mask_m[39] << 12)
32891 - | (mask_m[40] << 10) | (mask_m[41] << 8)
32892 - | (mask_m[42] << 6) | (mask_m[43] << 4)
32893 - | (mask_m[44] << 2) | (mask_m[45] << 0);
32894 - REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
32895 - REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
32896 -
32897 - tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
32898 - | (mask_m[18] << 26) | (mask_m[18] << 24)
32899 - | (mask_m[20] << 22) | (mask_m[20] << 20)
32900 - | (mask_m[22] << 18) | (mask_m[22] << 16)
32901 - | (mask_m[24] << 14) | (mask_m[24] << 12)
32902 - | (mask_m[25] << 10) | (mask_m[26] << 8)
32903 - | (mask_m[27] << 6) | (mask_m[28] << 4)
32904 - | (mask_m[29] << 2) | (mask_m[30] << 0);
32905 - REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
32906 - REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
32907 -
32908 - tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
32909 - | (mask_m[2] << 26) | (mask_m[3] << 24)
32910 - | (mask_m[4] << 22) | (mask_m[5] << 20)
32911 - | (mask_m[6] << 18) | (mask_m[7] << 16)
32912 - | (mask_m[8] << 14) | (mask_m[9] << 12)
32913 - | (mask_m[10] << 10) | (mask_m[11] << 8)
32914 - | (mask_m[12] << 6) | (mask_m[13] << 4)
32915 - | (mask_m[14] << 2) | (mask_m[15] << 0);
32916 - REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
32917 - REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
32918 -
32919 - tmp_mask = (mask_p[15] << 28)
32920 - | (mask_p[14] << 26) | (mask_p[13] << 24)
32921 - | (mask_p[12] << 22) | (mask_p[11] << 20)
32922 - | (mask_p[10] << 18) | (mask_p[9] << 16)
32923 - | (mask_p[8] << 14) | (mask_p[7] << 12)
32924 - | (mask_p[6] << 10) | (mask_p[5] << 8)
32925 - | (mask_p[4] << 6) | (mask_p[3] << 4)
32926 - | (mask_p[2] << 2) | (mask_p[1] << 0);
32927 - REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
32928 - REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
32929 -
32930 - tmp_mask = (mask_p[30] << 28)
32931 - | (mask_p[29] << 26) | (mask_p[28] << 24)
32932 - | (mask_p[27] << 22) | (mask_p[26] << 20)
32933 - | (mask_p[25] << 18) | (mask_p[24] << 16)
32934 - | (mask_p[23] << 14) | (mask_p[22] << 12)
32935 - | (mask_p[21] << 10) | (mask_p[20] << 8)
32936 - | (mask_p[19] << 6) | (mask_p[18] << 4)
32937 - | (mask_p[17] << 2) | (mask_p[16] << 0);
32938 - REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
32939 - REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
32940 -
32941 - tmp_mask = (mask_p[45] << 28)
32942 - | (mask_p[44] << 26) | (mask_p[43] << 24)
32943 - | (mask_p[42] << 22) | (mask_p[41] << 20)
32944 - | (mask_p[40] << 18) | (mask_p[39] << 16)
32945 - | (mask_p[38] << 14) | (mask_p[37] << 12)
32946 - | (mask_p[36] << 10) | (mask_p[35] << 8)
32947 - | (mask_p[34] << 6) | (mask_p[33] << 4)
32948 - | (mask_p[32] << 2) | (mask_p[31] << 0);
32949 - REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
32950 - REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
32951 -
32952 - tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
32953 - | (mask_p[59] << 26) | (mask_p[58] << 24)
32954 - | (mask_p[57] << 22) | (mask_p[56] << 20)
32955 - | (mask_p[55] << 18) | (mask_p[54] << 16)
32956 - | (mask_p[53] << 14) | (mask_p[52] << 12)
32957 - | (mask_p[51] << 10) | (mask_p[50] << 8)
32958 - | (mask_p[49] << 6) | (mask_p[48] << 4)
32959 - | (mask_p[47] << 2) | (mask_p[46] << 0);
32960 - REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
32961 - REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
32962 -}
32963 -
32964 -/**
32965 - * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming
32966 - * @ah: atheros hardware structure
32967 - *
32968 - * Only required for older devices with external AR2133/AR5133 radios.
32969 - */
32970 -int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
32971 -{
32972 -#define ATH_ALLOC_BANK(bank, size) do { \
32973 - bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
32974 - if (!bank) { \
32975 - ath_print(common, ATH_DBG_FATAL, \
32976 - "Cannot allocate RF banks\n"); \
32977 - return -ENOMEM; \
32978 - } \
32979 - } while (0);
32980 -
32981 - struct ath_common *common = ath9k_hw_common(ah);
32982 -
32983 - BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
32984 -
32985 - ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
32986 - ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
32987 - ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
32988 - ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
32989 - ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
32990 - ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
32991 - ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
32992 - ATH_ALLOC_BANK(ah->addac5416_21,
32993 - ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
32994 - ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
32995 -
32996 - return 0;
32997 -#undef ATH_ALLOC_BANK
32998 -}
32999 -
33000 -
33001 -/**
33002 - * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
33003 - * @ah: atheros hardware struture
33004 - * For the external AR2133/AR5133 radios banks.
33005 - */
33006 -void
33007 -ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
33008 -{
33009 -#define ATH_FREE_BANK(bank) do { \
33010 - kfree(bank); \
33011 - bank = NULL; \
33012 - } while (0);
33013 -
33014 - BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
33015 -
33016 - ATH_FREE_BANK(ah->analogBank0Data);
33017 - ATH_FREE_BANK(ah->analogBank1Data);
33018 - ATH_FREE_BANK(ah->analogBank2Data);
33019 - ATH_FREE_BANK(ah->analogBank3Data);
33020 - ATH_FREE_BANK(ah->analogBank6Data);
33021 - ATH_FREE_BANK(ah->analogBank6TPCData);
33022 - ATH_FREE_BANK(ah->analogBank7Data);
33023 - ATH_FREE_BANK(ah->addac5416_21);
33024 - ATH_FREE_BANK(ah->bank6Temp);
33025 -
33026 -#undef ATH_FREE_BANK
33027 -}
33028 -
33029 -/* *
33030 - * ath9k_hw_set_rf_regs - programs rf registers based on EEPROM
33031 - * @ah: atheros hardware structure
33032 - * @chan:
33033 - * @modesIndex:
33034 - *
33035 - * Used for the external AR2133/AR5133 radios.
33036 - *
33037 - * Reads the EEPROM header info from the device structure and programs
33038 - * all rf registers. This routine requires access to the analog
33039 - * rf device. This is not required for single-chip devices.
33040 - */
33041 -bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33042 - u16 modesIndex)
33043 -{
33044 - u32 eepMinorRev;
33045 - u32 ob5GHz = 0, db5GHz = 0;
33046 - u32 ob2GHz = 0, db2GHz = 0;
33047 - int regWrites = 0;
33048 -
33049 - /*
33050 - * Software does not need to program bank data
33051 - * for single chip devices, that is AR9280 or anything
33052 - * after that.
33053 - */
33054 - if (AR_SREV_9280_10_OR_LATER(ah))
33055 - return true;
33056 -
33057 - /* Setup rf parameters */
33058 - eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
33059 -
33060 - /* Setup Bank 0 Write */
33061 - RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
33062 -
33063 - /* Setup Bank 1 Write */
33064 - RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
33065 -
33066 - /* Setup Bank 2 Write */
33067 - RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
33068 -
33069 - /* Setup Bank 6 Write */
33070 - RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
33071 - modesIndex);
33072 - {
33073 - int i;
33074 - for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
33075 - ah->analogBank6Data[i] =
33076 - INI_RA(&ah->iniBank6TPC, i, modesIndex);
33077 - }
33078 - }
33079 -
33080 - /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
33081 - if (eepMinorRev >= 2) {
33082 - if (IS_CHAN_2GHZ(chan)) {
33083 - ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
33084 - db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
33085 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
33086 - ob2GHz, 3, 197, 0);
33087 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
33088 - db2GHz, 3, 194, 0);
33089 - } else {
33090 - ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
33091 - db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
33092 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
33093 - ob5GHz, 3, 203, 0);
33094 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
33095 - db5GHz, 3, 200, 0);
33096 - }
33097 - }
33098 -
33099 - /* Setup Bank 7 Setup */
33100 - RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
33101 -
33102 - /* Write Analog registers */
33103 - REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
33104 - regWrites);
33105 - REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
33106 - regWrites);
33107 - REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
33108 - regWrites);
33109 - REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
33110 - regWrites);
33111 - REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
33112 - regWrites);
33113 - REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
33114 - regWrites);
33115 -
33116 - return true;
33117 -}
33118 --- a/drivers/net/wireless/ath/ath9k/phy.h
33119 +++ b/drivers/net/wireless/ath/ath9k/phy.h
33120 @@ -17,504 +17,15 @@
33121 #ifndef PHY_H
33122 #define PHY_H
33123
33124 -/* Common between single chip and non single-chip solutions */
33125 -void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites);
33126 -
33127 -/* Single chip radio settings */
33128 -int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
33129 -void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
33130 -
33131 -/* Routines below are for non single-chip solutions */
33132 -int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
33133 -void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
33134 -
33135 -int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);
33136 -void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);
33137 -
33138 -bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
33139 - struct ath9k_channel *chan,
33140 - u16 modesIndex);
33141 +#define CHANSEL_DIV 15
33142 +#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV)
33143 +#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV)
33144
33145 #define AR_PHY_BASE 0x9800
33146 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
33147
33148 -#define AR_PHY_TEST 0x9800
33149 -#define PHY_AGC_CLR 0x10000000
33150 -#define RFSILENT_BB 0x00002000
33151 -
33152 -#define AR_PHY_TURBO 0x9804
33153 -#define AR_PHY_FC_TURBO_MODE 0x00000001
33154 -#define AR_PHY_FC_TURBO_SHORT 0x00000002
33155 -#define AR_PHY_FC_DYN2040_EN 0x00000004
33156 -#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
33157 -#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
33158 -/* For 25 MHz channel spacing -- not used but supported by hw */
33159 -#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
33160 -#define AR_PHY_FC_HT_EN 0x00000040
33161 -#define AR_PHY_FC_SHORT_GI_40 0x00000080
33162 -#define AR_PHY_FC_WALSH 0x00000100
33163 -#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
33164 -#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
33165 -
33166 -#define AR_PHY_TEST2 0x9808
33167 -
33168 -#define AR_PHY_TIMING2 0x9810
33169 -#define AR_PHY_TIMING3 0x9814
33170 -#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
33171 -#define AR_PHY_TIMING3_DSC_MAN_S 17
33172 -#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
33173 -#define AR_PHY_TIMING3_DSC_EXP_S 13
33174 -
33175 -#define AR_PHY_CHIP_ID 0x9818
33176 -#define AR_PHY_CHIP_ID_REV_0 0x80
33177 -#define AR_PHY_CHIP_ID_REV_1 0x81
33178 -#define AR_PHY_CHIP_ID_9160_REV_0 0xb0
33179 -
33180 -#define AR_PHY_ACTIVE 0x981C
33181 -#define AR_PHY_ACTIVE_EN 0x00000001
33182 -#define AR_PHY_ACTIVE_DIS 0x00000000
33183 -
33184 -#define AR_PHY_RF_CTL2 0x9824
33185 -#define AR_PHY_TX_END_DATA_START 0x000000FF
33186 -#define AR_PHY_TX_END_DATA_START_S 0
33187 -#define AR_PHY_TX_END_PA_ON 0x0000FF00
33188 -#define AR_PHY_TX_END_PA_ON_S 8
33189 -
33190 -#define AR_PHY_RF_CTL3 0x9828
33191 -#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
33192 -#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
33193 -
33194 -#define AR_PHY_ADC_CTL 0x982C
33195 -#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
33196 -#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
33197 -#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
33198 -#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
33199 -#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
33200 -#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
33201 -#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
33202 -
33203 -#define AR_PHY_ADC_SERIAL_CTL 0x9830
33204 -#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
33205 -#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
33206 -
33207 -#define AR_PHY_RF_CTL4 0x9834
33208 -#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
33209 -#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
33210 -#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
33211 -#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
33212 -#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
33213 -#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
33214 -#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
33215 -#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
33216 -
33217 -#define AR_PHY_TSTDAC_CONST 0x983c
33218 -
33219 -#define AR_PHY_SETTLING 0x9844
33220 -#define AR_PHY_SETTLING_SWITCH 0x00003F80
33221 -#define AR_PHY_SETTLING_SWITCH_S 7
33222 -
33223 -#define AR_PHY_RXGAIN 0x9848
33224 -#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
33225 -#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
33226 -#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
33227 -#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
33228 -#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
33229 -#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
33230 -#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
33231 -#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
33232 -
33233 -#define AR_PHY_DESIRED_SZ 0x9850
33234 -#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
33235 -#define AR_PHY_DESIRED_SZ_ADC_S 0
33236 -#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
33237 -#define AR_PHY_DESIRED_SZ_PGA_S 8
33238 -#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
33239 -#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
33240 -
33241 -#define AR_PHY_FIND_SIG 0x9858
33242 -#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
33243 -#define AR_PHY_FIND_SIG_FIRSTEP_S 12
33244 -#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
33245 -#define AR_PHY_FIND_SIG_FIRPWR_S 18
33246 -
33247 -#define AR_PHY_AGC_CTL1 0x985C
33248 -#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
33249 -#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
33250 -#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
33251 -#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
33252 -
33253 -#define AR_PHY_AGC_CONTROL 0x9860
33254 -#define AR_PHY_AGC_CONTROL_CAL 0x00000001
33255 -#define AR_PHY_AGC_CONTROL_NF 0x00000002
33256 -#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
33257 -#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
33258 -#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
33259 -
33260 -#define AR_PHY_CCA 0x9864
33261 -#define AR_PHY_MINCCA_PWR 0x0FF80000
33262 -#define AR_PHY_MINCCA_PWR_S 19
33263 -#define AR_PHY_CCA_THRESH62 0x0007F000
33264 -#define AR_PHY_CCA_THRESH62_S 12
33265 -#define AR9280_PHY_MINCCA_PWR 0x1FF00000
33266 -#define AR9280_PHY_MINCCA_PWR_S 20
33267 -#define AR9280_PHY_CCA_THRESH62 0x000FF000
33268 -#define AR9280_PHY_CCA_THRESH62_S 12
33269 -
33270 -#define AR_PHY_SFCORR_LOW 0x986C
33271 -#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
33272 -#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
33273 -#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
33274 -#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
33275 -#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
33276 -#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
33277 -#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
33278 -
33279 -#define AR_PHY_SFCORR 0x9868
33280 -#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
33281 -#define AR_PHY_SFCORR_M2COUNT_THR_S 0
33282 -#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
33283 -#define AR_PHY_SFCORR_M1_THRESH_S 17
33284 -#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
33285 -#define AR_PHY_SFCORR_M2_THRESH_S 24
33286 -
33287 -#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
33288 -#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
33289 -#define AR_PHY_SYNTH_CONTROL 0x9874
33290 -#define AR_PHY_SLEEP_SCAL 0x9878
33291 -
33292 -#define AR_PHY_PLL_CTL 0x987c
33293 -#define AR_PHY_PLL_CTL_40 0xaa
33294 -#define AR_PHY_PLL_CTL_40_5413 0x04
33295 -#define AR_PHY_PLL_CTL_44 0xab
33296 -#define AR_PHY_PLL_CTL_44_2133 0xeb
33297 -#define AR_PHY_PLL_CTL_40_2133 0xea
33298 -
33299 -#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
33300 -#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
33301 -#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
33302 -#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
33303 -#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
33304 -#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
33305 -#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
33306 -#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
33307 -#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
33308 -#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
33309 -#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
33310 -#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
33311 -#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
33312 -#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
33313 -
33314 -#define AR_PHY_RX_DELAY 0x9914
33315 -#define AR_PHY_SEARCH_START_DELAY 0x9918
33316 -#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
33317 -
33318 -#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
33319 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
33320 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
33321 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
33322 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
33323 -#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
33324 -#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
33325 -#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
33326 -#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
33327 -
33328 -#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
33329 -#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
33330 -#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
33331 -#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
33332 -
33333 -#define AR_PHY_TIMING5 0x9924
33334 -#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
33335 -#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
33336 -
33337 -#define AR_PHY_POWER_TX_RATE1 0x9934
33338 -#define AR_PHY_POWER_TX_RATE2 0x9938
33339 -#define AR_PHY_POWER_TX_RATE_MAX 0x993c
33340 -#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
33341 -
33342 -#define AR_PHY_FRAME_CTL 0x9944
33343 -#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
33344 -#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
33345 -
33346 -#define AR_PHY_TXPWRADJ 0x994C
33347 -#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
33348 -#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
33349 -#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
33350 -#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
33351 -
33352 -#define AR_PHY_RADAR_EXT 0x9940
33353 -#define AR_PHY_RADAR_EXT_ENA 0x00004000
33354 -
33355 -#define AR_PHY_RADAR_0 0x9954
33356 -#define AR_PHY_RADAR_0_ENA 0x00000001
33357 -#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
33358 -#define AR_PHY_RADAR_0_INBAND 0x0000003e
33359 -#define AR_PHY_RADAR_0_INBAND_S 1
33360 -#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
33361 -#define AR_PHY_RADAR_0_PRSSI_S 6
33362 -#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
33363 -#define AR_PHY_RADAR_0_HEIGHT_S 12
33364 -#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
33365 -#define AR_PHY_RADAR_0_RRSSI_S 18
33366 -#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
33367 -#define AR_PHY_RADAR_0_FIRPWR_S 24
33368 -
33369 -#define AR_PHY_RADAR_1 0x9958
33370 -#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
33371 -#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
33372 -#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
33373 -#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
33374 -#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
33375 -#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
33376 -#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
33377 -#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
33378 -#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
33379 -#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
33380 -#define AR_PHY_RADAR_1_MAXLEN_S 0
33381 -
33382 -#define AR_PHY_SWITCH_CHAIN_0 0x9960
33383 -#define AR_PHY_SWITCH_COM 0x9964
33384 -
33385 -#define AR_PHY_SIGMA_DELTA 0x996C
33386 -#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
33387 -#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
33388 -#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
33389 -#define AR_PHY_SIGMA_DELTA_FILT2_S 3
33390 -#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
33391 -#define AR_PHY_SIGMA_DELTA_FILT1_S 8
33392 -#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
33393 -#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
33394 -
33395 -#define AR_PHY_RESTART 0x9970
33396 -#define AR_PHY_RESTART_DIV_GC 0x001C0000
33397 -#define AR_PHY_RESTART_DIV_GC_S 18
33398 -
33399 -#define AR_PHY_RFBUS_REQ 0x997C
33400 -#define AR_PHY_RFBUS_REQ_EN 0x00000001
33401 -
33402 -#define AR_PHY_TIMING7 0x9980
33403 -#define AR_PHY_TIMING8 0x9984
33404 -#define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
33405 -#define AR_PHY_TIMING8_PILOT_MASK_2_S 0
33406 -
33407 -#define AR_PHY_BIN_MASK2_1 0x9988
33408 -#define AR_PHY_BIN_MASK2_2 0x998c
33409 -#define AR_PHY_BIN_MASK2_3 0x9990
33410 -#define AR_PHY_BIN_MASK2_4 0x9994
33411 -
33412 -#define AR_PHY_BIN_MASK_1 0x9900
33413 -#define AR_PHY_BIN_MASK_2 0x9904
33414 -#define AR_PHY_BIN_MASK_3 0x9908
33415 -
33416 -#define AR_PHY_MASK_CTL 0x990c
33417 -
33418 -#define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
33419 -#define AR_PHY_BIN_MASK2_4_MASK_4_S 0
33420 -
33421 -#define AR_PHY_TIMING9 0x9998
33422 -#define AR_PHY_TIMING10 0x999c
33423 -#define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
33424 -#define AR_PHY_TIMING10_PILOT_MASK_2_S 0
33425 -
33426 -#define AR_PHY_TIMING11 0x99a0
33427 -#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
33428 -#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
33429 -#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
33430 -#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
33431 -#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
33432 -#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
33433 -
33434 -#define AR_PHY_RX_CHAINMASK 0x99a4
33435 -#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
33436 -#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
33437 -#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
33438 -
33439 -#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
33440 -#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
33441 -#define AR_PHY_9285_ANT_DIV_CTL 0x01000000
33442 -#define AR_PHY_9285_ANT_DIV_CTL_S 24
33443 -#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
33444 -#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
33445 -#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
33446 -#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
33447 -#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
33448 -#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
33449 -#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
33450 -#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
33451 -#define AR_PHY_9285_ANT_DIV_LNA1 2
33452 -#define AR_PHY_9285_ANT_DIV_LNA2 1
33453 -#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
33454 -#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
33455 -#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
33456 -#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
33457 -
33458 -#define AR_PHY_EXT_CCA0 0x99b8
33459 -#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
33460 -#define AR_PHY_EXT_CCA0_THRESH62_S 0
33461 -
33462 -#define AR_PHY_EXT_CCA 0x99bc
33463 -#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
33464 -#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
33465 -#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
33466 -#define AR_PHY_EXT_CCA_THRESH62_S 16
33467 -#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
33468 -#define AR_PHY_EXT_MINCCA_PWR_S 23
33469 -#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
33470 -#define AR9280_PHY_EXT_MINCCA_PWR_S 16
33471 -
33472 -#define AR_PHY_SFCORR_EXT 0x99c0
33473 -#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
33474 -#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
33475 -#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
33476 -#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
33477 -#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
33478 -#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
33479 -#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
33480 -#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
33481 -#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
33482 -
33483 -#define AR_PHY_HALFGI 0x99D0
33484 -#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
33485 -#define AR_PHY_HALFGI_DSC_MAN_S 4
33486 -#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
33487 -#define AR_PHY_HALFGI_DSC_EXP_S 0
33488 -
33489 -#define AR_PHY_CHAN_INFO_MEMORY 0x99DC
33490 -#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
33491 -
33492 -#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
33493 -
33494 -#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC
33495 -#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
33496 -
33497 -#define AR_PHY_M_SLEEP 0x99f0
33498 -#define AR_PHY_REFCLKDLY 0x99f4
33499 -#define AR_PHY_REFCLKPD 0x99f8
33500 -
33501 -#define AR_PHY_CALMODE 0x99f0
33502 -
33503 -#define AR_PHY_CALMODE_IQ 0x00000000
33504 -#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
33505 -#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
33506 -#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
33507 -
33508 -#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
33509 -#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
33510 -#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
33511 -#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
33512 -
33513 -#define AR_PHY_CURRENT_RSSI 0x9c1c
33514 -#define AR9280_PHY_CURRENT_RSSI 0x9c3c
33515 -
33516 -#define AR_PHY_RFBUS_GRANT 0x9C20
33517 -#define AR_PHY_RFBUS_GRANT_EN 0x00000001
33518 -
33519 -#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
33520 -#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
33521 -
33522 -#define AR_PHY_CHAN_INFO_GAIN 0x9CFC
33523 -
33524 -#define AR_PHY_MODE 0xA200
33525 -#define AR_PHY_MODE_ASYNCFIFO 0x80
33526 -#define AR_PHY_MODE_AR2133 0x08
33527 -#define AR_PHY_MODE_AR5111 0x00
33528 -#define AR_PHY_MODE_AR5112 0x08
33529 -#define AR_PHY_MODE_DYNAMIC 0x04
33530 -#define AR_PHY_MODE_RF2GHZ 0x02
33531 -#define AR_PHY_MODE_RF5GHZ 0x00
33532 -#define AR_PHY_MODE_CCK 0x01
33533 -#define AR_PHY_MODE_OFDM 0x00
33534 -#define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
33535 -
33536 -#define AR_PHY_CCK_TX_CTRL 0xA204
33537 -#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
33538 -#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
33539 -#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
33540 -
33541 -#define AR_PHY_CCK_DETECT 0xA208
33542 -#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
33543 -#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
33544 -/* [12:6] settling time for antenna switch */
33545 -#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
33546 -#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
33547 -#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
33548 -#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
33549 -
33550 -#define AR_PHY_GAIN_2GHZ 0xA20C
33551 -#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
33552 -#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
33553 -#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
33554 -#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
33555 -#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
33556 -#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
33557 -
33558 -#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
33559 -#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
33560 -#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
33561 -#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
33562 -#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
33563 -#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
33564 -#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
33565 -#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
33566 -
33567 -#define AR_PHY_CCK_RXCTRL4 0xA21C
33568 -#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
33569 -#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
33570 -
33571 -#define AR_PHY_DAG_CTRLCCK 0xA228
33572 -#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
33573 -#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
33574 -#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
33575 -
33576 -#define AR_PHY_FORCE_CLKEN_CCK 0xA22C
33577 -#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
33578 -
33579 -#define AR_PHY_POWER_TX_RATE3 0xA234
33580 -#define AR_PHY_POWER_TX_RATE4 0xA238
33581 -
33582 -#define AR_PHY_SCRM_SEQ_XR 0xA23C
33583 -#define AR_PHY_HEADER_DETECT_XR 0xA240
33584 -#define AR_PHY_CHIRP_DETECTED_XR 0xA244
33585 -#define AR_PHY_BLUETOOTH 0xA254
33586 -
33587 -#define AR_PHY_TPCRG1 0xA258
33588 -#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
33589 -#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
33590 -
33591 -#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
33592 -#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
33593 -#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
33594 -#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
33595 -#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
33596 -#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
33597 -
33598 -#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
33599 -#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
33600 -
33601 -#define AR_PHY_TX_PWRCTRL4 0xa264
33602 -#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
33603 -#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
33604 -#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
33605 -#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
33606 -
33607 -#define AR_PHY_TX_PWRCTRL6_0 0xa270
33608 -#define AR_PHY_TX_PWRCTRL6_1 0xb270
33609 -#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
33610 -#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
33611 -
33612 -#define AR_PHY_TX_PWRCTRL7 0xa274
33613 #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000
33614 #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13
33615 -#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
33616 -#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
33617 -
33618 -#define AR_PHY_TX_PWRCTRL9 0xa27C
33619 -#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
33620 -#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
33621 -#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
33622 -#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
33623 -
33624 -#define AR_PHY_TX_GAIN_TBL1 0xa300
33625 #define AR_PHY_TX_GAIN_CLC 0x0000001E
33626 #define AR_PHY_TX_GAIN_CLC_S 1
33627 #define AR_PHY_TX_GAIN 0x0007F000
33628 @@ -526,91 +37,6 @@ bool ath9k_hw_set_rf_regs(struct ath_hw
33629 #define AR_PHY_CLC_Q0 0x0000ffd0
33630 #define AR_PHY_CLC_Q0_S 5
33631
33632 -#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
33633 -#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
33634 -#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00
33635 -#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
33636 -
33637 -#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
33638 -#define AR_PHY_MASK2_M_31_45 0xa3a4
33639 -#define AR_PHY_MASK2_M_16_30 0xa3a8
33640 -#define AR_PHY_MASK2_M_00_15 0xa3ac
33641 -#define AR_PHY_MASK2_P_15_01 0xa3b8
33642 -#define AR_PHY_MASK2_P_30_16 0xa3bc
33643 -#define AR_PHY_MASK2_P_45_31 0xa3c0
33644 -#define AR_PHY_MASK2_P_61_45 0xa3c4
33645 -#define AR_PHY_SPUR_REG 0x994c
33646 -
33647 -#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
33648 -#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
33649 -
33650 -#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
33651 -#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
33652 -#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
33653 -#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
33654 -#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
33655 -#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
33656 -
33657 -#define AR_PHY_PILOT_MASK_01_30 0xa3b0
33658 -#define AR_PHY_PILOT_MASK_31_60 0xa3b4
33659 -
33660 -#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
33661 -#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
33662 -
33663 -#define AR_PHY_ANALOG_SWAP 0xa268
33664 -#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
33665 -
33666 -#define AR_PHY_TPCRG5 0xA26C
33667 -#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
33668 -#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
33669 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
33670 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
33671 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
33672 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
33673 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
33674 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
33675 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
33676 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
33677 -
33678 -/* Carrier leak calibration control, do it after AGC calibration */
33679 -#define AR_PHY_CL_CAL_CTL 0xA358
33680 -#define AR_PHY_CL_CAL_ENABLE 0x00000002
33681 -#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
33682 -
33683 -#define AR_PHY_POWER_TX_RATE5 0xA38C
33684 -#define AR_PHY_POWER_TX_RATE6 0xA390
33685 -
33686 -#define AR_PHY_CAL_CHAINMASK 0xA39C
33687 -
33688 -#define AR_PHY_POWER_TX_SUB 0xA3C8
33689 -#define AR_PHY_POWER_TX_RATE7 0xA3CC
33690 -#define AR_PHY_POWER_TX_RATE8 0xA3D0
33691 -#define AR_PHY_POWER_TX_RATE9 0xA3D4
33692 -
33693 -#define AR_PHY_XPA_CFG 0xA3D8
33694 -#define AR_PHY_FORCE_XPA_CFG 0x000000001
33695 -#define AR_PHY_FORCE_XPA_CFG_S 0
33696 -
33697 -#define AR_PHY_CH1_CCA 0xa864
33698 -#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
33699 -#define AR_PHY_CH1_MINCCA_PWR_S 19
33700 -#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
33701 -#define AR9280_PHY_CH1_MINCCA_PWR_S 20
33702 -
33703 -#define AR_PHY_CH2_CCA 0xb864
33704 -#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
33705 -#define AR_PHY_CH2_MINCCA_PWR_S 19
33706 -
33707 -#define AR_PHY_CH1_EXT_CCA 0xa9bc
33708 -#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
33709 -#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
33710 -#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
33711 -#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
33712 -
33713 -#define AR_PHY_CH2_EXT_CCA 0xb9bc
33714 -#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
33715 -#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
33716 -
33717 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \
33718 int r; \
33719 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
33720 @@ -625,6 +51,7 @@ bool ath9k_hw_set_rf_regs(struct ath_hw
33721 #define ANTSWAP_AB 0x0001
33722 #define REDUCE_CHAIN_0 0x00000050
33723 #define REDUCE_CHAIN_1 0x00000051
33724 +#define AR_PHY_CHIP_ID 0x9818
33725
33726 #define RF_BANK_SETUP(_bank, _iniarray, _col) do { \
33727 int i; \
33728 @@ -632,4 +59,7 @@ bool ath9k_hw_set_rf_regs(struct ath_hw
33729 (_bank)[i] = INI_RA((_iniarray), i, _col);; \
33730 } while (0)
33731
33732 +#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
33733 +#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
33734 +
33735 #endif
33736 --- a/drivers/net/wireless/ath/ath9k/rc.c
33737 +++ b/drivers/net/wireless/ath/ath9k/rc.c
33738 @@ -691,6 +691,15 @@ static void ath_get_rate(void *priv, str
33739 rate_table = sc->cur_rate_table;
33740 rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table, &is_probe);
33741
33742 + /*
33743 + * If we're in HT mode and both us and our peer supports LDPC.
33744 + * We don't need to check our own device's capabilities as our own
33745 + * ht capabilities would have already been intersected with our peer's.
33746 + */
33747 + if (conf_is_ht(&sc->hw->conf) &&
33748 + (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING))
33749 + tx_info->flags |= IEEE80211_TX_CTL_LDPC;
33750 +
33751 if (is_probe) {
33752 /* set one try for probe rates. For the
33753 * probes don't enable rts */
33754 --- a/drivers/net/wireless/ath/ath9k/recv.c
33755 +++ b/drivers/net/wireless/ath/ath9k/recv.c
33756 @@ -16,6 +16,8 @@
33757
33758 #include "ath9k.h"
33759
33760 +#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
33761 +
33762 static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
33763 struct ieee80211_hdr *hdr)
33764 {
33765 @@ -115,56 +117,246 @@ static void ath_opmode_init(struct ath_s
33766 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
33767 }
33768
33769 -int ath_rx_init(struct ath_softc *sc, int nbufs)
33770 +static bool ath_rx_edma_buf_link(struct ath_softc *sc,
33771 + enum ath9k_rx_qtype qtype)
33772 {
33773 - struct ath_common *common = ath9k_hw_common(sc->sc_ah);
33774 + struct ath_hw *ah = sc->sc_ah;
33775 + struct ath_rx_edma *rx_edma;
33776 struct sk_buff *skb;
33777 struct ath_buf *bf;
33778 - int error = 0;
33779
33780 - spin_lock_init(&sc->rx.rxflushlock);
33781 - sc->sc_flags &= ~SC_OP_RXFLUSH;
33782 - spin_lock_init(&sc->rx.rxbuflock);
33783 + rx_edma = &sc->rx.rx_edma[qtype];
33784 + if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
33785 + return false;
33786
33787 - common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
33788 - min(common->cachelsz, (u16)64));
33789 + bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
33790 + list_del_init(&bf->list);
33791 +
33792 + skb = bf->bf_mpdu;
33793
33794 - ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
33795 - common->cachelsz, common->rx_bufsize);
33796 + ATH_RXBUF_RESET(bf);
33797 + memset(skb->data, 0, ah->caps.rx_status_len);
33798 + dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
33799 + ah->caps.rx_status_len, DMA_TO_DEVICE);
33800 +
33801 + SKB_CB_ATHBUF(skb) = bf;
33802 + ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
33803 + skb_queue_tail(&rx_edma->rx_fifo, skb);
33804 +
33805 + return true;
33806 +}
33807
33808 - /* Initialize rx descriptors */
33809 +static void ath_rx_addbuffer_edma(struct ath_softc *sc,
33810 + enum ath9k_rx_qtype qtype, int size)
33811 +{
33812 + struct ath_rx_edma *rx_edma;
33813 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
33814 + u32 nbuf = 0;
33815
33816 - error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
33817 - "rx", nbufs, 1);
33818 - if (error != 0) {
33819 - ath_print(common, ATH_DBG_FATAL,
33820 - "failed to allocate rx descriptors: %d\n", error);
33821 - goto err;
33822 + rx_edma = &sc->rx.rx_edma[qtype];
33823 + if (list_empty(&sc->rx.rxbuf)) {
33824 + ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n");
33825 + return;
33826 }
33827
33828 + while (!list_empty(&sc->rx.rxbuf)) {
33829 + nbuf++;
33830 +
33831 + if (!ath_rx_edma_buf_link(sc, qtype))
33832 + break;
33833 +
33834 + if (nbuf >= size)
33835 + break;
33836 + }
33837 +}
33838 +
33839 +static void ath_rx_remove_buffer(struct ath_softc *sc,
33840 + enum ath9k_rx_qtype qtype)
33841 +{
33842 + struct ath_buf *bf;
33843 + struct ath_rx_edma *rx_edma;
33844 + struct sk_buff *skb;
33845 +
33846 + rx_edma = &sc->rx.rx_edma[qtype];
33847 +
33848 + while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
33849 + bf = SKB_CB_ATHBUF(skb);
33850 + BUG_ON(!bf);
33851 + list_add_tail(&bf->list, &sc->rx.rxbuf);
33852 + }
33853 +}
33854 +
33855 +static void ath_rx_edma_cleanup(struct ath_softc *sc)
33856 +{
33857 + struct ath_buf *bf;
33858 +
33859 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
33860 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
33861 +
33862 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
33863 + if (bf->bf_mpdu)
33864 + dev_kfree_skb_any(bf->bf_mpdu);
33865 + }
33866 +
33867 + INIT_LIST_HEAD(&sc->rx.rxbuf);
33868 +
33869 + kfree(sc->rx.rx_bufptr);
33870 + sc->rx.rx_bufptr = NULL;
33871 +}
33872 +
33873 +static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
33874 +{
33875 + skb_queue_head_init(&rx_edma->rx_fifo);
33876 + skb_queue_head_init(&rx_edma->rx_buffers);
33877 + rx_edma->rx_fifo_hwsize = size;
33878 +}
33879 +
33880 +static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
33881 +{
33882 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
33883 + struct ath_hw *ah = sc->sc_ah;
33884 + struct sk_buff *skb;
33885 + struct ath_buf *bf;
33886 + int error = 0, i;
33887 + u32 size;
33888 +
33889 +
33890 + common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN +
33891 + ah->caps.rx_status_len,
33892 + min(common->cachelsz, (u16)64));
33893 +
33894 + ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
33895 + ah->caps.rx_status_len);
33896 +
33897 + ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
33898 + ah->caps.rx_lp_qdepth);
33899 + ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
33900 + ah->caps.rx_hp_qdepth);
33901 +
33902 + size = sizeof(struct ath_buf) * nbufs;
33903 + bf = kzalloc(size, GFP_KERNEL);
33904 + if (!bf)
33905 + return -ENOMEM;
33906 +
33907 + INIT_LIST_HEAD(&sc->rx.rxbuf);
33908 + sc->rx.rx_bufptr = bf;
33909 +
33910 + for (i = 0; i < nbufs; i++, bf++) {
33911 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
33912 - if (skb == NULL) {
33913 + if (!skb) {
33914 error = -ENOMEM;
33915 - goto err;
33916 + goto rx_init_fail;
33917 }
33918
33919 + memset(skb->data, 0, common->rx_bufsize);
33920 bf->bf_mpdu = skb;
33921 +
33922 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
33923 common->rx_bufsize,
33924 - DMA_FROM_DEVICE);
33925 + DMA_BIDIRECTIONAL);
33926 if (unlikely(dma_mapping_error(sc->dev,
33927 - bf->bf_buf_addr))) {
33928 - dev_kfree_skb_any(skb);
33929 - bf->bf_mpdu = NULL;
33930 + bf->bf_buf_addr))) {
33931 + dev_kfree_skb_any(skb);
33932 + bf->bf_mpdu = NULL;
33933 + ath_print(common, ATH_DBG_FATAL,
33934 + "dma_mapping_error() on RX init\n");
33935 + error = -ENOMEM;
33936 + goto rx_init_fail;
33937 + }
33938 +
33939 + list_add_tail(&bf->list, &sc->rx.rxbuf);
33940 + }
33941 +
33942 + return 0;
33943 +
33944 +rx_init_fail:
33945 + ath_rx_edma_cleanup(sc);
33946 + return error;
33947 +}
33948 +
33949 +static void ath_edma_start_recv(struct ath_softc *sc)
33950 +{
33951 + spin_lock_bh(&sc->rx.rxbuflock);
33952 +
33953 + ath9k_hw_rxena(sc->sc_ah);
33954 +
33955 + ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
33956 + sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
33957 +
33958 + ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
33959 + sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
33960 +
33961 + spin_unlock_bh(&sc->rx.rxbuflock);
33962 +
33963 + ath_opmode_init(sc);
33964 +
33965 + ath9k_hw_startpcureceive(sc->sc_ah);
33966 +}
33967 +
33968 +static void ath_edma_stop_recv(struct ath_softc *sc)
33969 +{
33970 + spin_lock_bh(&sc->rx.rxbuflock);
33971 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
33972 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
33973 + spin_unlock_bh(&sc->rx.rxbuflock);
33974 +}
33975 +
33976 +int ath_rx_init(struct ath_softc *sc, int nbufs)
33977 +{
33978 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
33979 + struct sk_buff *skb;
33980 + struct ath_buf *bf;
33981 + int error = 0;
33982 +
33983 + spin_lock_init(&sc->rx.rxflushlock);
33984 + sc->sc_flags &= ~SC_OP_RXFLUSH;
33985 + spin_lock_init(&sc->rx.rxbuflock);
33986 +
33987 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
33988 + return ath_rx_edma_init(sc, nbufs);
33989 + } else {
33990 + common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
33991 + min(common->cachelsz, (u16)64));
33992 +
33993 + ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
33994 + common->cachelsz, common->rx_bufsize);
33995 +
33996 + /* Initialize rx descriptors */
33997 +
33998 + error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
33999 + "rx", nbufs, 1, 0);
34000 + if (error != 0) {
34001 ath_print(common, ATH_DBG_FATAL,
34002 - "dma_mapping_error() on RX init\n");
34003 - error = -ENOMEM;
34004 + "failed to allocate rx descriptors: %d\n",
34005 + error);
34006 goto err;
34007 }
34008 - bf->bf_dmacontext = bf->bf_buf_addr;
34009 +
34010 + list_for_each_entry(bf, &sc->rx.rxbuf, list) {
34011 + skb = ath_rxbuf_alloc(common, common->rx_bufsize,
34012 + GFP_KERNEL);
34013 + if (skb == NULL) {
34014 + error = -ENOMEM;
34015 + goto err;
34016 + }
34017 +
34018 + bf->bf_mpdu = skb;
34019 + bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
34020 + common->rx_bufsize,
34021 + DMA_FROM_DEVICE);
34022 + if (unlikely(dma_mapping_error(sc->dev,
34023 + bf->bf_buf_addr))) {
34024 + dev_kfree_skb_any(skb);
34025 + bf->bf_mpdu = NULL;
34026 + ath_print(common, ATH_DBG_FATAL,
34027 + "dma_mapping_error() on RX init\n");
34028 + error = -ENOMEM;
34029 + goto err;
34030 + }
34031 + bf->bf_dmacontext = bf->bf_buf_addr;
34032 + }
34033 + sc->rx.rxlink = NULL;
34034 }
34035 - sc->rx.rxlink = NULL;
34036
34037 err:
34038 if (error)
34039 @@ -180,17 +372,23 @@ void ath_rx_cleanup(struct ath_softc *sc
34040 struct sk_buff *skb;
34041 struct ath_buf *bf;
34042
34043 - list_for_each_entry(bf, &sc->rx.rxbuf, list) {
34044 - skb = bf->bf_mpdu;
34045 - if (skb) {
34046 - dma_unmap_single(sc->dev, bf->bf_buf_addr,
34047 - common->rx_bufsize, DMA_FROM_DEVICE);
34048 - dev_kfree_skb(skb);
34049 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
34050 + ath_rx_edma_cleanup(sc);
34051 + return;
34052 + } else {
34053 + list_for_each_entry(bf, &sc->rx.rxbuf, list) {
34054 + skb = bf->bf_mpdu;
34055 + if (skb) {
34056 + dma_unmap_single(sc->dev, bf->bf_buf_addr,
34057 + common->rx_bufsize,
34058 + DMA_FROM_DEVICE);
34059 + dev_kfree_skb(skb);
34060 + }
34061 }
34062 - }
34063
34064 - if (sc->rx.rxdma.dd_desc_len != 0)
34065 - ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
34066 + if (sc->rx.rxdma.dd_desc_len != 0)
34067 + ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
34068 + }
34069 }
34070
34071 /*
34072 @@ -273,6 +471,11 @@ int ath_startrecv(struct ath_softc *sc)
34073 struct ath_hw *ah = sc->sc_ah;
34074 struct ath_buf *bf, *tbf;
34075
34076 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
34077 + ath_edma_start_recv(sc);
34078 + return 0;
34079 + }
34080 +
34081 spin_lock_bh(&sc->rx.rxbuflock);
34082 if (list_empty(&sc->rx.rxbuf))
34083 goto start_recv;
34084 @@ -306,7 +509,12 @@ bool ath_stoprecv(struct ath_softc *sc)
34085 ath9k_hw_stoppcurecv(ah);
34086 ath9k_hw_setrxfilter(ah, 0);
34087 stopped = ath9k_hw_stopdmarecv(ah);
34088 - sc->rx.rxlink = NULL;
34089 +
34090 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
34091 + ath_edma_stop_recv(sc);
34092 + } else {
34093 + sc->rx.rxlink = NULL;
34094 + }
34095
34096 return stopped;
34097 }
34098 @@ -315,7 +523,9 @@ void ath_flushrecv(struct ath_softc *sc)
34099 {
34100 spin_lock_bh(&sc->rx.rxflushlock);
34101 sc->sc_flags |= SC_OP_RXFLUSH;
34102 - ath_rx_tasklet(sc, 1);
34103 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
34104 + ath_rx_tasklet(sc, 1, true);
34105 + ath_rx_tasklet(sc, 1, false);
34106 sc->sc_flags &= ~SC_OP_RXFLUSH;
34107 spin_unlock_bh(&sc->rx.rxflushlock);
34108 }
34109 @@ -469,14 +679,147 @@ static void ath_rx_send_to_mac80211(stru
34110 ieee80211_rx(hw, skb);
34111 }
34112
34113 -int ath_rx_tasklet(struct ath_softc *sc, int flush)
34114 +static bool ath_edma_get_buffers(struct ath_softc *sc,
34115 + enum ath9k_rx_qtype qtype)
34116 {
34117 -#define PA2DESC(_sc, _pa) \
34118 - ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \
34119 - ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr)))
34120 + struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
34121 + struct ath_hw *ah = sc->sc_ah;
34122 + struct ath_common *common = ath9k_hw_common(ah);
34123 + struct sk_buff *skb;
34124 + struct ath_buf *bf;
34125 + int ret;
34126 +
34127 + skb = skb_peek(&rx_edma->rx_fifo);
34128 + if (!skb)
34129 + return false;
34130 +
34131 + bf = SKB_CB_ATHBUF(skb);
34132 + BUG_ON(!bf);
34133 +
34134 + dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
34135 + common->rx_bufsize, DMA_FROM_DEVICE);
34136 +
34137 + ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
34138 + if (ret == -EINPROGRESS)
34139 + return false;
34140 +
34141 + __skb_unlink(skb, &rx_edma->rx_fifo);
34142 + if (ret == -EINVAL) {
34143 + /* corrupt descriptor, skip this one and the following one */
34144 + list_add_tail(&bf->list, &sc->rx.rxbuf);
34145 + ath_rx_edma_buf_link(sc, qtype);
34146 + skb = skb_peek(&rx_edma->rx_fifo);
34147 + if (!skb)
34148 + return true;
34149
34150 + bf = SKB_CB_ATHBUF(skb);
34151 + BUG_ON(!bf);
34152 +
34153 + __skb_unlink(skb, &rx_edma->rx_fifo);
34154 + list_add_tail(&bf->list, &sc->rx.rxbuf);
34155 + ath_rx_edma_buf_link(sc, qtype);
34156 + }
34157 + skb_queue_tail(&rx_edma->rx_buffers, skb);
34158 +
34159 + return true;
34160 +}
34161 +
34162 +static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
34163 + struct ath_rx_status *rs,
34164 + enum ath9k_rx_qtype qtype)
34165 +{
34166 + struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
34167 + struct sk_buff *skb;
34168 struct ath_buf *bf;
34169 +
34170 + while (ath_edma_get_buffers(sc, qtype));
34171 + skb = __skb_dequeue(&rx_edma->rx_buffers);
34172 + if (!skb)
34173 + return NULL;
34174 +
34175 + bf = SKB_CB_ATHBUF(skb);
34176 + ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
34177 + return bf;
34178 +}
34179 +
34180 +static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
34181 + struct ath_rx_status *rs)
34182 +{
34183 + struct ath_hw *ah = sc->sc_ah;
34184 + struct ath_common *common = ath9k_hw_common(ah);
34185 struct ath_desc *ds;
34186 + struct ath_buf *bf;
34187 + int ret;
34188 +
34189 + if (list_empty(&sc->rx.rxbuf)) {
34190 + sc->rx.rxlink = NULL;
34191 + return NULL;
34192 + }
34193 +
34194 + bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
34195 + ds = bf->bf_desc;
34196 +
34197 + /*
34198 + * Must provide the virtual address of the current
34199 + * descriptor, the physical address, and the virtual
34200 + * address of the next descriptor in the h/w chain.
34201 + * This allows the HAL to look ahead to see if the
34202 + * hardware is done with a descriptor by checking the
34203 + * done bit in the following descriptor and the address
34204 + * of the current descriptor the DMA engine is working
34205 + * on. All this is necessary because of our use of
34206 + * a self-linked list to avoid rx overruns.
34207 + */
34208 + ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
34209 + if (ret == -EINPROGRESS) {
34210 + struct ath_rx_status trs;
34211 + struct ath_buf *tbf;
34212 + struct ath_desc *tds;
34213 +
34214 + memset(&trs, 0, sizeof(trs));
34215 + if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
34216 + sc->rx.rxlink = NULL;
34217 + return NULL;
34218 + }
34219 +
34220 + tbf = list_entry(bf->list.next, struct ath_buf, list);
34221 +
34222 + /*
34223 + * On some hardware the descriptor status words could
34224 + * get corrupted, including the done bit. Because of
34225 + * this, check if the next descriptor's done bit is
34226 + * set or not.
34227 + *
34228 + * If the next descriptor's done bit is set, the current
34229 + * descriptor has been corrupted. Force s/w to discard
34230 + * this descriptor and continue...
34231 + */
34232 +
34233 + tds = tbf->bf_desc;
34234 + ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
34235 + if (ret == -EINPROGRESS)
34236 + return NULL;
34237 + }
34238 +
34239 + if (!bf->bf_mpdu)
34240 + return bf;
34241 +
34242 + /*
34243 + * Synchronize the DMA transfer with CPU before
34244 + * 1. accessing the frame
34245 + * 2. requeueing the same buffer to h/w
34246 + */
34247 + dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
34248 + common->rx_bufsize,
34249 + DMA_FROM_DEVICE);
34250 +
34251 + return bf;
34252 +}
34253 +
34254 +
34255 +int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
34256 +{
34257 + struct ath_buf *bf;
34258 struct sk_buff *skb = NULL, *requeue_skb;
34259 struct ieee80211_rx_status *rxs;
34260 struct ath_hw *ah = sc->sc_ah;
34261 @@ -491,7 +834,16 @@ int ath_rx_tasklet(struct ath_softc *sc,
34262 int retval;
34263 bool decrypt_error = false;
34264 struct ath_rx_status rs;
34265 + enum ath9k_rx_qtype qtype;
34266 + bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
34267 + int dma_type;
34268 +
34269 + if (edma)
34270 + dma_type = DMA_FROM_DEVICE;
34271 + else
34272 + dma_type = DMA_BIDIRECTIONAL;
34273
34274 + qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
34275 spin_lock_bh(&sc->rx.rxbuflock);
34276
34277 do {
34278 @@ -499,71 +851,19 @@ int ath_rx_tasklet(struct ath_softc *sc,
34279 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
34280 break;
34281
34282 - if (list_empty(&sc->rx.rxbuf)) {
34283 - sc->rx.rxlink = NULL;
34284 - break;
34285 - }
34286 -
34287 - bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
34288 - ds = bf->bf_desc;
34289 -
34290 - /*
34291 - * Must provide the virtual address of the current
34292 - * descriptor, the physical address, and the virtual
34293 - * address of the next descriptor in the h/w chain.
34294 - * This allows the HAL to look ahead to see if the
34295 - * hardware is done with a descriptor by checking the
34296 - * done bit in the following descriptor and the address
34297 - * of the current descriptor the DMA engine is working
34298 - * on. All this is necessary because of our use of
34299 - * a self-linked list to avoid rx overruns.
34300 - */
34301 memset(&rs, 0, sizeof(rs));
34302 - retval = ath9k_hw_rxprocdesc(ah, ds, &rs, 0);
34303 - if (retval == -EINPROGRESS) {
34304 - struct ath_rx_status trs;
34305 - struct ath_buf *tbf;
34306 - struct ath_desc *tds;
34307 -
34308 - memset(&trs, 0, sizeof(trs));
34309 - if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
34310 - sc->rx.rxlink = NULL;
34311 - break;
34312 - }
34313 + if (edma)
34314 + bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
34315 + else
34316 + bf = ath_get_next_rx_buf(sc, &rs);
34317
34318 - tbf = list_entry(bf->list.next, struct ath_buf, list);
34319 -
34320 - /*
34321 - * On some hardware the descriptor status words could
34322 - * get corrupted, including the done bit. Because of
34323 - * this, check if the next descriptor's done bit is
34324 - * set or not.
34325 - *
34326 - * If the next descriptor's done bit is set, the current
34327 - * descriptor has been corrupted. Force s/w to discard
34328 - * this descriptor and continue...
34329 - */
34330 -
34331 - tds = tbf->bf_desc;
34332 - retval = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
34333 - if (retval == -EINPROGRESS) {
34334 - break;
34335 - }
34336 - }
34337 + if (!bf)
34338 + break;
34339
34340 skb = bf->bf_mpdu;
34341 if (!skb)
34342 continue;
34343
34344 - /*
34345 - * Synchronize the DMA transfer with CPU before
34346 - * 1. accessing the frame
34347 - * 2. requeueing the same buffer to h/w
34348 - */
34349 - dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
34350 - common->rx_bufsize,
34351 - DMA_FROM_DEVICE);
34352 -
34353 hdr = (struct ieee80211_hdr *) skb->data;
34354 rxs = IEEE80211_SKB_RXCB(skb);
34355
34356 @@ -597,9 +897,11 @@ int ath_rx_tasklet(struct ath_softc *sc,
34357 /* Unmap the frame */
34358 dma_unmap_single(sc->dev, bf->bf_buf_addr,
34359 common->rx_bufsize,
34360 - DMA_FROM_DEVICE);
34361 + dma_type);
34362
34363 - skb_put(skb, rs.rs_datalen);
34364 + skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
34365 + if (ah->caps.rx_status_len)
34366 + skb_pull(skb, ah->caps.rx_status_len);
34367
34368 ath9k_cmn_rx_skb_postprocess(common, skb, &rs,
34369 rxs, decrypt_error);
34370 @@ -608,7 +910,7 @@ int ath_rx_tasklet(struct ath_softc *sc,
34371 bf->bf_mpdu = requeue_skb;
34372 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
34373 common->rx_bufsize,
34374 - DMA_FROM_DEVICE);
34375 + dma_type);
34376 if (unlikely(dma_mapping_error(sc->dev,
34377 bf->bf_buf_addr))) {
34378 dev_kfree_skb_any(requeue_skb);
34379 @@ -639,12 +941,16 @@ int ath_rx_tasklet(struct ath_softc *sc,
34380 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
34381
34382 requeue:
34383 - list_move_tail(&bf->list, &sc->rx.rxbuf);
34384 - ath_rx_buf_link(sc, bf);
34385 + if (edma) {
34386 + list_add_tail(&bf->list, &sc->rx.rxbuf);
34387 + ath_rx_edma_buf_link(sc, qtype);
34388 + } else {
34389 + list_move_tail(&bf->list, &sc->rx.rxbuf);
34390 + ath_rx_buf_link(sc, bf);
34391 + }
34392 } while (1);
34393
34394 spin_unlock_bh(&sc->rx.rxbuflock);
34395
34396 return 0;
34397 -#undef PA2DESC
34398 }
34399 --- a/drivers/net/wireless/ath/ath9k/reg.h
34400 +++ b/drivers/net/wireless/ath/ath9k/reg.h
34401 @@ -20,7 +20,7 @@
34402 #include "../reg.h"
34403
34404 #define AR_CR 0x0008
34405 -#define AR_CR_RXE 0x00000004
34406 +#define AR_CR_RXE (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004)
34407 #define AR_CR_RXD 0x00000020
34408 #define AR_CR_SWI 0x00000040
34409
34410 @@ -39,6 +39,12 @@
34411 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000
34412 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17
34413
34414 +#define AR_RXBP_THRESH 0x0018
34415 +#define AR_RXBP_THRESH_HP 0x0000000f
34416 +#define AR_RXBP_THRESH_HP_S 0
34417 +#define AR_RXBP_THRESH_LP 0x00003f00
34418 +#define AR_RXBP_THRESH_LP_S 8
34419 +
34420 #define AR_MIRT 0x0020
34421 #define AR_MIRT_VAL 0x0000ffff
34422 #define AR_MIRT_VAL_S 16
34423 @@ -144,6 +150,9 @@
34424 #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15
34425 #define AR_MACMISC_MISC_OBS_BUS_1 1
34426
34427 +#define AR_DATABUF_SIZE 0x0060
34428 +#define AR_DATABUF_SIZE_MASK 0x00000FFF
34429 +
34430 #define AR_GTXTO 0x0064
34431 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF
34432 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000
34433 @@ -160,9 +169,14 @@
34434 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000
34435 #define AR_CST_TIMEOUT_LIMIT_S 16
34436
34437 +#define AR_HP_RXDP 0x0074
34438 +#define AR_LP_RXDP 0x0078
34439 +
34440 #define AR_ISR 0x0080
34441 #define AR_ISR_RXOK 0x00000001
34442 #define AR_ISR_RXDESC 0x00000002
34443 +#define AR_ISR_HP_RXOK 0x00000001
34444 +#define AR_ISR_LP_RXOK 0x00000002
34445 #define AR_ISR_RXERR 0x00000004
34446 #define AR_ISR_RXNOPKT 0x00000008
34447 #define AR_ISR_RXEOL 0x00000010
34448 @@ -232,7 +246,6 @@
34449 #define AR_ISR_S5_TIMER_THRESH 0x0007FE00
34450 #define AR_ISR_S5_TIM_TIMER 0x00000010
34451 #define AR_ISR_S5_DTIM_TIMER 0x00000020
34452 -#define AR_ISR_S5_S 0x00d8
34453 #define AR_IMR_S5 0x00b8
34454 #define AR_IMR_S5_TIM_TIMER 0x00000010
34455 #define AR_IMR_S5_DTIM_TIMER 0x00000020
34456 @@ -240,7 +253,6 @@
34457 #define AR_ISR_S5_GENTIMER_TRIG_S 0
34458 #define AR_ISR_S5_GENTIMER_THRESH 0xFF800000
34459 #define AR_ISR_S5_GENTIMER_THRESH_S 16
34460 -#define AR_ISR_S5_S 0x00d8
34461 #define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80
34462 #define AR_IMR_S5_GENTIMER_TRIG_S 0
34463 #define AR_IMR_S5_GENTIMER_THRESH 0xFF800000
34464 @@ -249,6 +261,8 @@
34465 #define AR_IMR 0x00a0
34466 #define AR_IMR_RXOK 0x00000001
34467 #define AR_IMR_RXDESC 0x00000002
34468 +#define AR_IMR_RXOK_HP 0x00000001
34469 +#define AR_IMR_RXOK_LP 0x00000002
34470 #define AR_IMR_RXERR 0x00000004
34471 #define AR_IMR_RXNOPKT 0x00000008
34472 #define AR_IMR_RXEOL 0x00000010
34473 @@ -332,10 +346,10 @@
34474 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000
34475 #define AR_ISR_S1_QCU_TXEOL_S 16
34476
34477 -#define AR_ISR_S2_S 0x00cc
34478 -#define AR_ISR_S3_S 0x00d0
34479 -#define AR_ISR_S4_S 0x00d4
34480 -#define AR_ISR_S5_S 0x00d8
34481 +#define AR_ISR_S2_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d0 : 0x00cc)
34482 +#define AR_ISR_S3_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d4 : 0x00d0)
34483 +#define AR_ISR_S4_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d8 : 0x00d4)
34484 +#define AR_ISR_S5_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00dc : 0x00d8)
34485 #define AR_DMADBG_0 0x00e0
34486 #define AR_DMADBG_1 0x00e4
34487 #define AR_DMADBG_2 0x00e8
34488 @@ -369,6 +383,9 @@
34489 #define AR_Q9_TXDP 0x0824
34490 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2))
34491
34492 +#define AR_Q_STATUS_RING_START 0x830
34493 +#define AR_Q_STATUS_RING_END 0x834
34494 +
34495 #define AR_Q_TXE 0x0840
34496 #define AR_Q_TXE_M 0x000003FF
34497
34498 @@ -461,6 +478,9 @@
34499 #define AR_Q_RDYTIMESHDN 0x0a40
34500 #define AR_Q_RDYTIMESHDN_M 0x000003FF
34501
34502 +/* MAC Descriptor CRC check */
34503 +#define AR_Q_DESC_CRCCHK 0xa44
34504 +#define AR_Q_DESC_CRCCHK_EN 1 /* Enable CRC check on the descriptor fetched from host */
34505
34506 #define AR_NUM_DCU 10
34507 #define AR_DCU_0 0x0001
34508 @@ -759,6 +779,8 @@
34509 #define AR_SREV_VERSION_9271 0x140
34510 #define AR_SREV_REVISION_9271_10 0
34511 #define AR_SREV_REVISION_9271_11 1
34512 +#define AR_SREV_VERSION_9300 0x1c0
34513 +#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
34514
34515 #define AR_SREV_5416(_ah) \
34516 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
34517 @@ -844,6 +866,15 @@
34518 #define AR_SREV_9271_11(_ah) \
34519 (AR_SREV_9271(_ah) && \
34520 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11))
34521 +#define AR_SREV_9300(_ah) \
34522 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))
34523 +#define AR_SREV_9300_20(_ah) \
34524 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
34525 + ((_ah)->hw_version.macRev == AR_SREV_REVISION_9300_20))
34526 +#define AR_SREV_9300_20_OR_LATER(_ah) \
34527 + (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9300) || \
34528 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
34529 + ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9300_20)))
34530
34531 #define AR_SREV_9285E_20(_ah) \
34532 (AR_SREV_9285_12_OR_LATER(_ah) && \
34533 @@ -945,6 +976,7 @@ enum {
34534 #define AR9285_NUM_GPIO 12
34535 #define AR9287_NUM_GPIO 11
34536 #define AR9271_NUM_GPIO 16
34537 +#define AR9300_NUM_GPIO 17
34538
34539 #define AR_GPIO_IN_OUT 0x4048
34540 #define AR_GPIO_IN_VAL 0x0FFFC000
34541 @@ -957,19 +989,21 @@ enum {
34542 #define AR9287_GPIO_IN_VAL_S 11
34543 #define AR9271_GPIO_IN_VAL 0xFFFF0000
34544 #define AR9271_GPIO_IN_VAL_S 16
34545 +#define AR9300_GPIO_IN_VAL 0x0001FFFF
34546 +#define AR9300_GPIO_IN_VAL_S 0
34547
34548 -#define AR_GPIO_OE_OUT 0x404c
34549 +#define AR_GPIO_OE_OUT (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c)
34550 #define AR_GPIO_OE_OUT_DRV 0x3
34551 #define AR_GPIO_OE_OUT_DRV_NO 0x0
34552 #define AR_GPIO_OE_OUT_DRV_LOW 0x1
34553 #define AR_GPIO_OE_OUT_DRV_HI 0x2
34554 #define AR_GPIO_OE_OUT_DRV_ALL 0x3
34555
34556 -#define AR_GPIO_INTR_POL 0x4050
34557 -#define AR_GPIO_INTR_POL_VAL 0x00001FFF
34558 +#define AR_GPIO_INTR_POL (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050)
34559 +#define AR_GPIO_INTR_POL_VAL 0x0001FFFF
34560 #define AR_GPIO_INTR_POL_VAL_S 0
34561
34562 -#define AR_GPIO_INPUT_EN_VAL 0x4054
34563 +#define AR_GPIO_INPUT_EN_VAL (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054)
34564 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004
34565 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2
34566 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008
34567 @@ -987,13 +1021,13 @@ enum {
34568 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
34569 #define AR_GPIO_JTAG_DISABLE 0x00020000
34570
34571 -#define AR_GPIO_INPUT_MUX1 0x4058
34572 +#define AR_GPIO_INPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058)
34573 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000
34574 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16
34575 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00
34576 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8
34577
34578 -#define AR_GPIO_INPUT_MUX2 0x405c
34579 +#define AR_GPIO_INPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c)
34580 #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f
34581 #define AR_GPIO_INPUT_MUX2_CLK25_S 0
34582 #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0
34583 @@ -1001,13 +1035,13 @@ enum {
34584 #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00
34585 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8
34586
34587 -#define AR_GPIO_OUTPUT_MUX1 0x4060
34588 -#define AR_GPIO_OUTPUT_MUX2 0x4064
34589 -#define AR_GPIO_OUTPUT_MUX3 0x4068
34590 +#define AR_GPIO_OUTPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060)
34591 +#define AR_GPIO_OUTPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064)
34592 +#define AR_GPIO_OUTPUT_MUX3 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068)
34593
34594 -#define AR_INPUT_STATE 0x406c
34595 +#define AR_INPUT_STATE (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c)
34596
34597 -#define AR_EEPROM_STATUS_DATA 0x407c
34598 +#define AR_EEPROM_STATUS_DATA (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c)
34599 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
34600 #define AR_EEPROM_STATUS_DATA_VAL_S 0
34601 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
34602 @@ -1015,13 +1049,24 @@ enum {
34603 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
34604 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
34605
34606 -#define AR_OBS 0x4080
34607 +#define AR_OBS (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080)
34608
34609 -#define AR_GPIO_PDPU 0x4088
34610 +#define AR_GPIO_PDPU (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)
34611
34612 -#define AR_PCIE_MSI 0x4094
34613 +#define AR_PCIE_MSI (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094)
34614 #define AR_PCIE_MSI_ENABLE 0x00000001
34615
34616 +#define AR_INTR_PRIO_SYNC_ENABLE 0x40c4
34617 +#define AR_INTR_PRIO_ASYNC_MASK 0x40c8
34618 +#define AR_INTR_PRIO_SYNC_MASK 0x40cc
34619 +#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
34620 +
34621 +#define AR_RTC_9300_PLL_DIV 0x000003ff
34622 +#define AR_RTC_9300_PLL_DIV_S 0
34623 +#define AR_RTC_9300_PLL_REFDIV 0x00003C00
34624 +#define AR_RTC_9300_PLL_REFDIV_S 10
34625 +#define AR_RTC_9300_PLL_CLKSEL 0x0000C000
34626 +#define AR_RTC_9300_PLL_CLKSEL_S 14
34627
34628 #define AR_RTC_9160_PLL_DIV 0x000003ff
34629 #define AR_RTC_9160_PLL_DIV_S 0
34630 @@ -1039,6 +1084,16 @@ enum {
34631 #define AR_RTC_RC_COLD_RESET 0x00000004
34632 #define AR_RTC_RC_WARM_RESET 0x00000008
34633
34634 +/* Crystal Control */
34635 +#define AR_RTC_XTAL_CONTROL 0x7004
34636 +
34637 +/* Reg Control 0 */
34638 +#define AR_RTC_REG_CONTROL0 0x7008
34639 +
34640 +/* Reg Control 1 */
34641 +#define AR_RTC_REG_CONTROL1 0x700c
34642 +#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001
34643 +
34644 #define AR_RTC_PLL_CONTROL \
34645 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
34646
34647 @@ -1069,6 +1124,7 @@ enum {
34648 #define AR_RTC_SLEEP_CLK \
34649 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)
34650 #define AR_RTC_FORCE_DERIVED_CLK 0x2
34651 +#define AR_RTC_FORCE_SWREG_PRD 0x00000004
34652
34653 #define AR_RTC_FORCE_WAKE \
34654 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)
34655 @@ -1533,7 +1589,7 @@ enum {
34656 #define AR_TSFOOR_THRESHOLD 0x813c
34657 #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF
34658
34659 -#define AR_PHY_ERR_EIFS_MASK 8144
34660 +#define AR_PHY_ERR_EIFS_MASK 0x8144
34661
34662 #define AR_PHY_ERR_3 0x8168
34663 #define AR_PHY_ERR_3_COUNT 0x00FFFFFF
34664 @@ -1599,24 +1655,26 @@ enum {
34665 #define AR_FIRST_NDP_TIMER 7
34666 #define AR_NDP2_PERIOD 0x81a0
34667 #define AR_NDP2_TIMER_MODE 0x81c0
34668 -#define AR_NEXT_TBTT_TIMER 0x8200
34669 -#define AR_NEXT_DMA_BEACON_ALERT 0x8204
34670 -#define AR_NEXT_SWBA 0x8208
34671 -#define AR_NEXT_CFP 0x8208
34672 -#define AR_NEXT_HCF 0x820C
34673 -#define AR_NEXT_TIM 0x8210
34674 -#define AR_NEXT_DTIM 0x8214
34675 -#define AR_NEXT_QUIET_TIMER 0x8218
34676 -#define AR_NEXT_NDP_TIMER 0x821C
34677 -
34678 -#define AR_BEACON_PERIOD 0x8220
34679 -#define AR_DMA_BEACON_PERIOD 0x8224
34680 -#define AR_SWBA_PERIOD 0x8228
34681 -#define AR_HCF_PERIOD 0x822C
34682 -#define AR_TIM_PERIOD 0x8230
34683 -#define AR_DTIM_PERIOD 0x8234
34684 -#define AR_QUIET_PERIOD 0x8238
34685 -#define AR_NDP_PERIOD 0x823C
34686 +
34687 +#define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2))
34688 +#define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0)
34689 +#define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1)
34690 +#define AR_NEXT_SWBA AR_GEN_TIMERS(2)
34691 +#define AR_NEXT_CFP AR_GEN_TIMERS(2)
34692 +#define AR_NEXT_HCF AR_GEN_TIMERS(3)
34693 +#define AR_NEXT_TIM AR_GEN_TIMERS(4)
34694 +#define AR_NEXT_DTIM AR_GEN_TIMERS(5)
34695 +#define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6)
34696 +#define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7)
34697 +
34698 +#define AR_BEACON_PERIOD AR_GEN_TIMERS(8)
34699 +#define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9)
34700 +#define AR_SWBA_PERIOD AR_GEN_TIMERS(10)
34701 +#define AR_HCF_PERIOD AR_GEN_TIMERS(11)
34702 +#define AR_TIM_PERIOD AR_GEN_TIMERS(12)
34703 +#define AR_DTIM_PERIOD AR_GEN_TIMERS(13)
34704 +#define AR_QUIET_PERIOD AR_GEN_TIMERS(14)
34705 +#define AR_NDP_PERIOD AR_GEN_TIMERS(15)
34706
34707 #define AR_TIMER_MODE 0x8240
34708 #define AR_TBTT_TIMER_EN 0x00000001
34709 @@ -1730,4 +1788,32 @@ enum {
34710 #define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */
34711 #define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
34712
34713 +#define AR_AGG_WEP_ENABLE_FIX 0x00000008 /* This allows the use of AR_AGG_WEP_ENABLE */
34714 +#define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search
34715 + * based on both MAC Address and Key ID.
34716 + * If bit is 0, then Multicast search is
34717 + * based on MAC address only.
34718 + * For Merlin and above only.
34719 + */
34720 +#define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature,
34721 + * when it is enable, AGG_WEP would takes
34722 + * charge of the encryption interface of
34723 + * pcu_txsm.
34724 + */
34725 +
34726 +#define AR9300_SM_BASE 0xa200
34727 +#define AR9002_PHY_AGC_CONTROL 0x9860
34728 +#define AR9003_PHY_AGC_CONTROL AR9300_SM_BASE + 0xc4
34729 +#define AR_PHY_AGC_CONTROL (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL)
34730 +#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */
34731 +#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */
34732 +#define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */
34733 +#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */
34734 +#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */
34735 +#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */
34736 +#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */
34737 +#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */
34738 +#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0
34739 +#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6
34740 +
34741 #endif
34742 --- a/drivers/net/wireless/ath/ath9k/xmit.c
34743 +++ b/drivers/net/wireless/ath/ath9k/xmit.c
34744 @@ -91,7 +91,6 @@ static int ath_max_4ms_framelen[3][16] =
34745 }
34746 };
34747
34748 -
34749 /*********************/
34750 /* Aggregation logic */
34751 /*********************/
34752 @@ -279,7 +278,7 @@ static struct ath_buf* ath_clone_txbuf(s
34753 tbf->aphy = bf->aphy;
34754 tbf->bf_mpdu = bf->bf_mpdu;
34755 tbf->bf_buf_addr = bf->bf_buf_addr;
34756 - *(tbf->bf_desc) = *(bf->bf_desc);
34757 + memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
34758 tbf->bf_state = bf->bf_state;
34759 tbf->bf_dmacontext = bf->bf_dmacontext;
34760
34761 @@ -358,8 +357,7 @@ static void ath_tx_complete_aggr(struct
34762 /* transmit completion */
34763 acked_cnt++;
34764 } else {
34765 - if (!(tid->state & AGGR_CLEANUP) &&
34766 - ts->ts_flags != ATH9K_TX_SW_ABORTED) {
34767 + if (!(tid->state & AGGR_CLEANUP) && !bf_last->bf_tx_aborted) {
34768 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
34769 ath_tx_set_retry(sc, txq, bf);
34770 txpending = 1;
34771 @@ -378,7 +376,8 @@ static void ath_tx_complete_aggr(struct
34772 }
34773 }
34774
34775 - if (bf_next == NULL) {
34776 + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
34777 + bf_next == NULL) {
34778 /*
34779 * Make sure the last desc is reclaimed if it
34780 * not a holding desc.
34781 @@ -412,36 +411,38 @@ static void ath_tx_complete_aggr(struct
34782 !txfail, sendbar);
34783 } else {
34784 /* retry the un-acked ones */
34785 - if (bf->bf_next == NULL && bf_last->bf_stale) {
34786 - struct ath_buf *tbf;
34787 -
34788 - tbf = ath_clone_txbuf(sc, bf_last);
34789 - /*
34790 - * Update tx baw and complete the frame with
34791 - * failed status if we run out of tx buf
34792 - */
34793 - if (!tbf) {
34794 - spin_lock_bh(&txq->axq_lock);
34795 - ath_tx_update_baw(sc, tid,
34796 - bf->bf_seqno);
34797 - spin_unlock_bh(&txq->axq_lock);
34798 + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
34799 + if (bf->bf_next == NULL && bf_last->bf_stale) {
34800 + struct ath_buf *tbf;
34801 +
34802 + tbf = ath_clone_txbuf(sc, bf_last);
34803 + /*
34804 + * Update tx baw and complete the frame with
34805 + * failed status if we run out of tx buf
34806 + */
34807 + if (!tbf) {
34808 + spin_lock_bh(&txq->axq_lock);
34809 + ath_tx_update_baw(sc, tid,
34810 + bf->bf_seqno);
34811 + spin_unlock_bh(&txq->axq_lock);
34812 +
34813 + bf->bf_state.bf_type |= BUF_XRETRY;
34814 + ath_tx_rc_status(bf, ts, nbad,
34815 + 0, false);
34816 + ath_tx_complete_buf(sc, bf, txq,
34817 + &bf_head, ts, 0, 0);
34818 + break;
34819 + }
34820
34821 - bf->bf_state.bf_type |= BUF_XRETRY;
34822 - ath_tx_rc_status(bf, ts, nbad,
34823 - 0, false);
34824 - ath_tx_complete_buf(sc, bf, txq,
34825 - &bf_head, ts, 0, 0);
34826 - break;
34827 + ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
34828 + list_add_tail(&tbf->list, &bf_head);
34829 + } else {
34830 + /*
34831 + * Clear descriptor status words for
34832 + * software retry
34833 + */
34834 + ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
34835 }
34836 -
34837 - ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
34838 - list_add_tail(&tbf->list, &bf_head);
34839 - } else {
34840 - /*
34841 - * Clear descriptor status words for
34842 - * software retry
34843 - */
34844 - ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
34845 }
34846
34847 /*
34848 @@ -665,7 +666,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_
34849 bpad = PADBYTES(al_delta) + (ndelim << 2);
34850
34851 bf->bf_next = NULL;
34852 - bf->bf_desc->ds_link = 0;
34853 + ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
34854
34855 /* link buffers of this frame to the aggregate */
34856 ath_tx_addto_baw(sc, tid, bf);
34857 @@ -673,7 +674,8 @@ static enum ATH_AGGR_STATUS ath_tx_form_
34858 list_move_tail(&bf->list, bf_q);
34859 if (bf_prev) {
34860 bf_prev->bf_next = bf;
34861 - bf_prev->bf_desc->ds_link = bf->bf_daddr;
34862 + ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
34863 + bf->bf_daddr);
34864 }
34865 bf_prev = bf;
34866
34867 @@ -853,7 +855,7 @@ struct ath_txq *ath_txq_setup(struct ath
34868 struct ath_hw *ah = sc->sc_ah;
34869 struct ath_common *common = ath9k_hw_common(ah);
34870 struct ath9k_tx_queue_info qi;
34871 - int qnum;
34872 + int qnum, i;
34873
34874 memset(&qi, 0, sizeof(qi));
34875 qi.tqi_subtype = subtype;
34876 @@ -877,11 +879,16 @@ struct ath_txq *ath_txq_setup(struct ath
34877 * The UAPSD queue is an exception, since we take a desc-
34878 * based intr on the EOSP frames.
34879 */
34880 - if (qtype == ATH9K_TX_QUEUE_UAPSD)
34881 - qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
34882 - else
34883 - qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
34884 - TXQ_FLAG_TXDESCINT_ENABLE;
34885 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
34886 + qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
34887 + TXQ_FLAG_TXERRINT_ENABLE;
34888 + } else {
34889 + if (qtype == ATH9K_TX_QUEUE_UAPSD)
34890 + qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
34891 + else
34892 + qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
34893 + TXQ_FLAG_TXDESCINT_ENABLE;
34894 + }
34895 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
34896 if (qnum == -1) {
34897 /*
34898 @@ -908,6 +915,11 @@ struct ath_txq *ath_txq_setup(struct ath
34899 txq->axq_depth = 0;
34900 txq->axq_tx_inprogress = false;
34901 sc->tx.txqsetup |= 1<<qnum;
34902 +
34903 + txq->txq_headidx = txq->txq_tailidx = 0;
34904 + for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
34905 + INIT_LIST_HEAD(&txq->txq_fifo[i]);
34906 + INIT_LIST_HEAD(&txq->txq_fifo_pending);
34907 }
34908 return &sc->tx.txq[qnum];
34909 }
34910 @@ -1035,36 +1047,64 @@ void ath_draintxq(struct ath_softc *sc,
34911 struct ath_tx_status ts;
34912
34913 memset(&ts, 0, sizeof(ts));
34914 - if (!retry_tx)
34915 - ts.ts_flags = ATH9K_TX_SW_ABORTED;
34916 -
34917 INIT_LIST_HEAD(&bf_head);
34918
34919 for (;;) {
34920 spin_lock_bh(&txq->axq_lock);
34921
34922 - if (list_empty(&txq->axq_q)) {
34923 - txq->axq_link = NULL;
34924 - spin_unlock_bh(&txq->axq_lock);
34925 - break;
34926 - }
34927 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
34928 + if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
34929 + if (list_empty(&txq->txq_fifo_pending)) {
34930 + txq->txq_headidx = txq->txq_tailidx = 0;
34931 + spin_unlock_bh(&txq->axq_lock);
34932 + break;
34933 + }
34934
34935 - bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
34936 + bf = list_first_entry(&txq->txq_fifo_pending,
34937 + struct ath_buf, list);
34938
34939 - if (bf->bf_stale) {
34940 - list_del(&bf->list);
34941 - spin_unlock_bh(&txq->axq_lock);
34942 + list_cut_position(
34943 + &txq->txq_fifo[txq->txq_tailidx],
34944 + &txq->txq_fifo_pending,
34945 + &bf->bf_lastbf->list);
34946 + } else {
34947 + bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
34948 + struct ath_buf, list);
34949 + }
34950 + } else {
34951 + if (list_empty(&txq->axq_q)) {
34952 + txq->axq_link = NULL;
34953 + spin_unlock_bh(&txq->axq_lock);
34954 + break;
34955 + }
34956 + bf = list_first_entry(&txq->axq_q, struct ath_buf,
34957 + list);
34958
34959 - spin_lock_bh(&sc->tx.txbuflock);
34960 - list_add_tail(&bf->list, &sc->tx.txbuf);
34961 - spin_unlock_bh(&sc->tx.txbuflock);
34962 - continue;
34963 + if (bf->bf_stale) {
34964 + list_del(&bf->list);
34965 + spin_unlock_bh(&txq->axq_lock);
34966 +
34967 + spin_lock_bh(&sc->tx.txbuflock);
34968 + list_add_tail(&bf->list, &sc->tx.txbuf);
34969 + spin_unlock_bh(&sc->tx.txbuflock);
34970 + continue;
34971 + }
34972 }
34973
34974 lastbf = bf->bf_lastbf;
34975 + if (!retry_tx)
34976 + lastbf->bf_tx_aborted = true;
34977 +
34978 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
34979 + list_cut_position(&bf_head,
34980 + &txq->txq_fifo[txq->txq_tailidx],
34981 + &lastbf->list);
34982 + INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
34983 + } else {
34984 + /* remove ath_buf's of the same mpdu from txq */
34985 + list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
34986 + }
34987
34988 - /* remove ath_buf's of the same mpdu from txq */
34989 - list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
34990 txq->axq_depth--;
34991
34992 spin_unlock_bh(&txq->axq_lock);
34993 @@ -1224,25 +1264,46 @@ static void ath_tx_txqaddbuf(struct ath_
34994
34995 bf = list_first_entry(head, struct ath_buf, list);
34996
34997 - list_splice_tail_init(head, &txq->axq_q);
34998 - txq->axq_depth++;
34999 -
35000 ath_print(common, ATH_DBG_QUEUE,
35001 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
35002
35003 - if (txq->axq_link == NULL) {
35004 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
35005 + if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
35006 + list_splice_tail_init(head, &txq->txq_fifo_pending);
35007 + return;
35008 + }
35009 + if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
35010 + ath_print(common, ATH_DBG_XMIT,
35011 + "Initializing tx fifo %d which is non-empty\n",
35012 + txq->txq_headidx);
35013 + INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
35014 + list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
35015 + INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
35016 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
35017 ath_print(common, ATH_DBG_XMIT,
35018 "TXDP[%u] = %llx (%p)\n",
35019 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
35020 } else {
35021 - *txq->axq_link = bf->bf_daddr;
35022 - ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
35023 - txq->axq_qnum, txq->axq_link,
35024 - ito64(bf->bf_daddr), bf->bf_desc);
35025 + list_splice_tail_init(head, &txq->axq_q);
35026 +
35027 + if (txq->axq_link == NULL) {
35028 + ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
35029 + ath_print(common, ATH_DBG_XMIT,
35030 + "TXDP[%u] = %llx (%p)\n",
35031 + txq->axq_qnum, ito64(bf->bf_daddr),
35032 + bf->bf_desc);
35033 + } else {
35034 + *txq->axq_link = bf->bf_daddr;
35035 + ath_print(common, ATH_DBG_XMIT,
35036 + "link[%u] (%p)=%llx (%p)\n",
35037 + txq->axq_qnum, txq->axq_link,
35038 + ito64(bf->bf_daddr), bf->bf_desc);
35039 + }
35040 + ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
35041 + &txq->axq_link);
35042 + ath9k_hw_txstart(ah, txq->axq_qnum);
35043 }
35044 - txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
35045 - ath9k_hw_txstart(ah, txq->axq_qnum);
35046 + txq->axq_depth++;
35047 }
35048
35049 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
35050 @@ -1408,8 +1469,7 @@ static void assign_aggr_tid_seqno(struct
35051 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
35052 }
35053
35054 -static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
35055 - struct ath_txq *txq)
35056 +static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
35057 {
35058 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
35059 int flags = 0;
35060 @@ -1420,6 +1480,9 @@ static int setup_tx_flags(struct ath_sof
35061 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
35062 flags |= ATH9K_TXDESC_NOACK;
35063
35064 + if (use_ldpc)
35065 + flags |= ATH9K_TXDESC_LDPC;
35066 +
35067 return flags;
35068 }
35069
35070 @@ -1571,6 +1634,7 @@ static int ath_tx_setup_buffer(struct ie
35071 int hdrlen;
35072 __le16 fc;
35073 int padpos, padsize;
35074 + bool use_ldpc = false;
35075
35076 tx_info->pad[0] = 0;
35077 switch (txctl->frame_type) {
35078 @@ -1597,10 +1661,13 @@ static int ath_tx_setup_buffer(struct ie
35079 bf->bf_frmlen -= padsize;
35080 }
35081
35082 - if (conf_is_ht(&hw->conf))
35083 + if (conf_is_ht(&hw->conf)) {
35084 bf->bf_state.bf_type |= BUF_HT;
35085 + if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
35086 + use_ldpc = true;
35087 + }
35088
35089 - bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
35090 + bf->bf_flags = setup_tx_flags(skb, use_ldpc);
35091
35092 bf->bf_keytype = get_hw_crypto_keytype(skb);
35093 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
35094 @@ -1659,8 +1726,7 @@ static void ath_tx_start_dma(struct ath_
35095 list_add_tail(&bf->list, &bf_head);
35096
35097 ds = bf->bf_desc;
35098 - ds->ds_link = 0;
35099 - ds->ds_data = bf->bf_buf_addr;
35100 + ath9k_hw_set_desc_link(ah, ds, 0);
35101
35102 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
35103 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
35104 @@ -1669,7 +1735,9 @@ static void ath_tx_start_dma(struct ath_
35105 skb->len, /* segment length */
35106 true, /* first segment */
35107 true, /* last segment */
35108 - ds); /* first descriptor */
35109 + ds, /* first descriptor */
35110 + bf->bf_buf_addr,
35111 + txctl->txq->axq_qnum);
35112
35113 spin_lock_bh(&txctl->txq->axq_lock);
35114
35115 @@ -1896,7 +1964,7 @@ static int ath_tx_num_badfrms(struct ath
35116 int nbad = 0;
35117 int isaggr = 0;
35118
35119 - if (ts->ts_flags == ATH9K_TX_SW_ABORTED)
35120 + if (bf->bf_tx_aborted)
35121 return 0;
35122
35123 isaggr = bf_isaggr(bf);
35124 @@ -2138,10 +2206,119 @@ void ath_tx_tasklet(struct ath_softc *sc
35125 }
35126 }
35127
35128 +void ath_tx_edma_tasklet(struct ath_softc *sc)
35129 +{
35130 + struct ath_tx_status txs;
35131 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
35132 + struct ath_hw *ah = sc->sc_ah;
35133 + struct ath_txq *txq;
35134 + struct ath_buf *bf, *lastbf;
35135 + struct list_head bf_head;
35136 + int status;
35137 + int txok;
35138 +
35139 + for (;;) {
35140 + status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
35141 + if (status == -EINPROGRESS)
35142 + break;
35143 + if (status == -EIO) {
35144 + ath_print(common, ATH_DBG_XMIT,
35145 + "Error processing tx status\n");
35146 + break;
35147 + }
35148 +
35149 + /* Skip beacon completions */
35150 + if (txs.qid == sc->beacon.beaconq)
35151 + continue;
35152 +
35153 + txq = &sc->tx.txq[txs.qid];
35154 +
35155 + spin_lock_bh(&txq->axq_lock);
35156 + if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
35157 + spin_unlock_bh(&txq->axq_lock);
35158 + return;
35159 + }
35160 +
35161 + bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
35162 + struct ath_buf, list);
35163 + lastbf = bf->bf_lastbf;
35164 +
35165 + INIT_LIST_HEAD(&bf_head);
35166 + list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
35167 + &lastbf->list);
35168 + INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
35169 + txq->axq_depth--;
35170 + txq->axq_tx_inprogress = false;
35171 + spin_unlock_bh(&txq->axq_lock);
35172 +
35173 + txok = !(txs.ts_status & ATH9K_TXERR_MASK);
35174 +
35175 + if (!bf_isampdu(bf)) {
35176 + bf->bf_retries = txs.ts_longretry;
35177 + if (txs.ts_status & ATH9K_TXERR_XRETRY)
35178 + bf->bf_state.bf_type |= BUF_XRETRY;
35179 + ath_tx_rc_status(bf, &txs, 0, txok, true);
35180 + }
35181 +
35182 + if (bf_isampdu(bf))
35183 + ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok);
35184 + else
35185 + ath_tx_complete_buf(sc, bf, txq, &bf_head,
35186 + &txs, txok, 0);
35187 +
35188 + spin_lock_bh(&txq->axq_lock);
35189 + if (!list_empty(&txq->txq_fifo_pending)) {
35190 + INIT_LIST_HEAD(&bf_head);
35191 + bf = list_first_entry(&txq->txq_fifo_pending,
35192 + struct ath_buf, list);
35193 + list_cut_position(&bf_head, &txq->txq_fifo_pending,
35194 + &bf->bf_lastbf->list);
35195 + ath_tx_txqaddbuf(sc, txq, &bf_head);
35196 + } else if (sc->sc_flags & SC_OP_TXAGGR)
35197 + ath_txq_schedule(sc, txq);
35198 + spin_unlock_bh(&txq->axq_lock);
35199 + }
35200 +}
35201 +
35202 /*****************/
35203 /* Init, Cleanup */
35204 /*****************/
35205
35206 +static int ath_txstatus_setup(struct ath_softc *sc, int size)
35207 +{
35208 + struct ath_descdma *dd = &sc->txsdma;
35209 + u8 txs_len = sc->sc_ah->caps.txs_len;
35210 +
35211 + dd->dd_desc_len = size * txs_len;
35212 + dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
35213 + &dd->dd_desc_paddr, GFP_KERNEL);
35214 + if (!dd->dd_desc)
35215 + return -ENOMEM;
35216 +
35217 + return 0;
35218 +}
35219 +
35220 +static int ath_tx_edma_init(struct ath_softc *sc)
35221 +{
35222 + int err;
35223 +
35224 + err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
35225 + if (!err)
35226 + ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
35227 + sc->txsdma.dd_desc_paddr,
35228 + ATH_TXSTATUS_RING_SIZE);
35229 +
35230 + return err;
35231 +}
35232 +
35233 +static void ath_tx_edma_cleanup(struct ath_softc *sc)
35234 +{
35235 + struct ath_descdma *dd = &sc->txsdma;
35236 +
35237 + dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
35238 + dd->dd_desc_paddr);
35239 +}
35240 +
35241 int ath_tx_init(struct ath_softc *sc, int nbufs)
35242 {
35243 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
35244 @@ -2150,7 +2327,7 @@ int ath_tx_init(struct ath_softc *sc, in
35245 spin_lock_init(&sc->tx.txbuflock);
35246
35247 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
35248 - "tx", nbufs, 1);
35249 + "tx", nbufs, 1, 1);
35250 if (error != 0) {
35251 ath_print(common, ATH_DBG_FATAL,
35252 "Failed to allocate tx descriptors: %d\n", error);
35253 @@ -2158,7 +2335,7 @@ int ath_tx_init(struct ath_softc *sc, in
35254 }
35255
35256 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
35257 - "beacon", ATH_BCBUF, 1);
35258 + "beacon", ATH_BCBUF, 1, 1);
35259 if (error != 0) {
35260 ath_print(common, ATH_DBG_FATAL,
35261 "Failed to allocate beacon descriptors: %d\n", error);
35262 @@ -2167,6 +2344,12 @@ int ath_tx_init(struct ath_softc *sc, in
35263
35264 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
35265
35266 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
35267 + error = ath_tx_edma_init(sc);
35268 + if (error)
35269 + goto err;
35270 + }
35271 +
35272 err:
35273 if (error != 0)
35274 ath_tx_cleanup(sc);
35275 @@ -2181,6 +2364,9 @@ void ath_tx_cleanup(struct ath_softc *sc
35276
35277 if (sc->tx.txdma.dd_desc_len != 0)
35278 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
35279 +
35280 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
35281 + ath_tx_edma_cleanup(sc);
35282 }
35283
35284 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
35285 --- a/include/net/mac80211.h
35286 +++ b/include/net/mac80211.h
35287 @@ -274,6 +274,7 @@ struct ieee80211_bss_conf {
35288 * @IEEE80211_TX_INTFL_NL80211_FRAME_TX: Frame was requested through nl80211
35289 * MLME command (internal to mac80211 to figure out whether to send TX
35290 * status to user space)
35291 + * @IEEE80211_TX_CTL_LDPC: tells the driver to use LDPC for this frame
35292 */
35293 enum mac80211_tx_control_flags {
35294 IEEE80211_TX_CTL_REQ_TX_STATUS = BIT(0),
35295 @@ -297,6 +298,7 @@ enum mac80211_tx_control_flags {
35296 IEEE80211_TX_INTFL_RETRANSMISSION = BIT(19),
35297 IEEE80211_TX_INTFL_HAS_RADIOTAP = BIT(20),
35298 IEEE80211_TX_INTFL_NL80211_FRAME_TX = BIT(21),
35299 + IEEE80211_TX_CTL_LDPC = BIT(22),
35300 };
35301
35302 /**
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