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[openwrt/svn-archive/archive.git] / package / mac80211 / patches / 302-rt2x00-Implement-support-for-rt2800pci.patch
1 From a34c288f7214637f214ec17fb2b35dd5d20b0634 Mon Sep 17 00:00:00 2001
2 From: Ivo van Doorn <IvDoorn@gmail.com>
3 Date: Sat, 14 Mar 2009 20:41:58 +0100
4 Subject: [PATCH] rt2x00: Implement support for rt2800pci
5
6 Add support for the rt2800pci chipset.
7
8 Includes various patches from Mattias, Mark, Felix and Xose.
9
10 Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
11 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
12 Signed-off-by: Mark Asselstine <asselsm@gmail.com>
13 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
14 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
15 ---
16 drivers/net/wireless/rt2x00/Kconfig | 15 +
17 drivers/net/wireless/rt2x00/Makefile | 1 +
18 drivers/net/wireless/rt2x00/rt2800pci.c | 3035 +++++++++++++++++++++++++++++++
19 drivers/net/wireless/rt2x00/rt2800pci.h | 1880 +++++++++++++++++++
20 drivers/net/wireless/rt2x00/rt2x00.h | 6 +
21 5 files changed, 4937 insertions(+), 0 deletions(-)
22 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
23 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
24
25 --- a/drivers/net/wireless/rt2x00/Makefile
26 +++ b/drivers/net/wireless/rt2x00/Makefile
27 @@ -16,5 +16,6 @@ obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00u
28 obj-$(CONFIG_RT2400PCI) += rt2400pci.o
29 obj-$(CONFIG_RT2500PCI) += rt2500pci.o
30 obj-$(CONFIG_RT61PCI) += rt61pci.o
31 +obj-$(CONFIG_RT2800PCI) += rt2800pci.o
32 obj-$(CONFIG_RT2500USB) += rt2500usb.o
33 obj-$(CONFIG_RT73USB) += rt73usb.o
34 --- /dev/null
35 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
36 @@ -0,0 +1,3035 @@
37 +/*
38 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
39 + <http://rt2x00.serialmonkey.com>
40 +
41 + This program is free software; you can redistribute it and/or modify
42 + it under the terms of the GNU General Public License as published by
43 + the Free Software Foundation; either version 2 of the License, or
44 + (at your option) any later version.
45 +
46 + This program is distributed in the hope that it will be useful,
47 + but WITHOUT ANY WARRANTY; without even the implied warranty of
48 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
49 + GNU General Public License for more details.
50 +
51 + You should have received a copy of the GNU General Public License
52 + along with this program; if not, write to the
53 + Free Software Foundation, Inc.,
54 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
55 + */
56 +
57 +/*
58 + Module: rt2800pci
59 + Abstract: rt2800pci device specific routines.
60 + Supported chipsets: RT2800E & RT2800ED.
61 + */
62 +
63 +#include <linux/crc-ccitt.h>
64 +#include <linux/delay.h>
65 +#include <linux/etherdevice.h>
66 +#include <linux/init.h>
67 +#include <linux/kernel.h>
68 +#include <linux/module.h>
69 +#include <linux/pci.h>
70 +#include <linux/platform_device.h>
71 +#include <linux/eeprom_93cx6.h>
72 +
73 +#include "rt2x00.h"
74 +#include "rt2x00pci.h"
75 +#include "rt2800pci.h"
76 +
77 +/* FIXME: Make Kconfig dependent */
78 +#ifdef CONFIG_PCI
79 +#define CONFIG_RT2800PCI_PCI
80 +#endif
81 +#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
82 +#define CONFIG_RT2800PCI_WISOC
83 +#endif
84 +
85 +/*
86 + * Allow hardware encryption to be disabled.
87 + */
88 +static int modparam_nohwcrypt = 0;
89 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
90 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
91 +
92 +/*
93 + * Register access.
94 + * BBP and RF register require indirect register access,
95 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
96 + * These indirect registers work with busy bits,
97 + * and we will try maximal REGISTER_BUSY_COUNT times to access
98 + * the register while taking a REGISTER_BUSY_DELAY us delay
99 + * between each attampt. When the busy bit is still set at that time,
100 + * the access attempt is considered to have failed,
101 + * and we will print an error.
102 + */
103 +#define WAIT_FOR_BBP(__dev, __reg) \
104 + rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
105 +#define WAIT_FOR_RF(__dev, __reg) \
106 + rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
107 +#define WAIT_FOR_MCU(__dev, __reg) \
108 + rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
109 + H2M_MAILBOX_CSR_OWNER, (__reg))
110 +
111 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
112 + const unsigned int word, const u8 value)
113 +{
114 + u32 reg;
115 +
116 + mutex_lock(&rt2x00dev->csr_mutex);
117 +
118 + /*
119 + * Wait until the BBP becomes available, afterwards we
120 + * can safely write the new data into the register.
121 + */
122 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
123 + reg = 0;
124 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
125 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
126 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
127 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
128 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
129 +
130 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
131 + }
132 +
133 + mutex_unlock(&rt2x00dev->csr_mutex);
134 +}
135 +
136 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
137 + const unsigned int word, u8 *value)
138 +{
139 + u32 reg;
140 +
141 + mutex_lock(&rt2x00dev->csr_mutex);
142 +
143 + /*
144 + * Wait until the BBP becomes available, afterwards we
145 + * can safely write the read request into the register.
146 + * After the data has been written, we wait until hardware
147 + * returns the correct value, if at any time the register
148 + * doesn't become available in time, reg will be 0xffffffff
149 + * which means we return 0xff to the caller.
150 + */
151 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
152 + reg = 0;
153 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
154 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
155 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
156 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
157 +
158 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
159 +
160 + WAIT_FOR_BBP(rt2x00dev, &reg);
161 + }
162 +
163 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
164 +
165 + mutex_unlock(&rt2x00dev->csr_mutex);
166 +}
167 +
168 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
169 + const unsigned int word, const u32 value)
170 +{
171 + u32 reg;
172 +
173 + mutex_lock(&rt2x00dev->csr_mutex);
174 +
175 + /*
176 + * Wait until the RF becomes available, afterwards we
177 + * can safely write the new data into the register.
178 + */
179 + if (WAIT_FOR_RF(rt2x00dev, &reg)) {
180 + reg = 0;
181 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
182 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
183 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
184 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
185 +
186 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
187 + rt2x00_rf_write(rt2x00dev, word, value);
188 + }
189 +
190 + mutex_unlock(&rt2x00dev->csr_mutex);
191 +}
192 +
193 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
194 + const u8 command, const u8 token,
195 + const u8 arg0, const u8 arg1)
196 +{
197 + u32 reg;
198 +
199 + mutex_lock(&rt2x00dev->csr_mutex);
200 +
201 + /*
202 + * Wait until the MCU becomes available, afterwards we
203 + * can safely write the new data into the register.
204 + */
205 + if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
206 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
207 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
208 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
209 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
210 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
211 +
212 + reg = 0;
213 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
214 + rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
215 + }
216 +
217 + mutex_unlock(&rt2x00dev->csr_mutex);
218 +}
219 +
220 +static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
221 +{
222 + unsigned int i;
223 + u32 reg;
224 +
225 + for (i = 0; i < 200; i++) {
226 + rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
227 +
228 + if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
229 + (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
230 + (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
231 + (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
232 + break;
233 +
234 + udelay(REGISTER_BUSY_DELAY);
235 + }
236 +
237 + if (i == 200)
238 + ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
239 +
240 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
241 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
242 +}
243 +
244 +#ifdef CONFIG_RT2800PCI_WISOC
245 +static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
246 +{
247 + u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
248 +
249 + memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
250 +}
251 +#else
252 +static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
253 +{
254 +}
255 +#endif /* CONFIG_RT2800PCI_WISOC */
256 +
257 +#ifdef CONFIG_RT2800PCI_PCI
258 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
259 +{
260 + struct rt2x00_dev *rt2x00dev = eeprom->data;
261 + u32 reg;
262 +
263 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
264 +
265 + eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
266 + eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
267 + eeprom->reg_data_clock =
268 + !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
269 + eeprom->reg_chip_select =
270 + !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
271 +}
272 +
273 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
274 +{
275 + struct rt2x00_dev *rt2x00dev = eeprom->data;
276 + u32 reg = 0;
277 +
278 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
279 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
280 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
281 + !!eeprom->reg_data_clock);
282 + rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
283 + !!eeprom->reg_chip_select);
284 +
285 + rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
286 +}
287 +
288 +static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
289 +{
290 + struct eeprom_93cx6 eeprom;
291 + u32 reg;
292 +
293 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
294 +
295 + eeprom.data = rt2x00dev;
296 + eeprom.register_read = rt2800pci_eepromregister_read;
297 + eeprom.register_write = rt2800pci_eepromregister_write;
298 + eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
299 + PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
300 + eeprom.reg_data_in = 0;
301 + eeprom.reg_data_out = 0;
302 + eeprom.reg_data_clock = 0;
303 + eeprom.reg_chip_select = 0;
304 +
305 + eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
306 + EEPROM_SIZE / sizeof(u16));
307 +}
308 +#else
309 +static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
310 +{
311 +}
312 +#endif /* CONFIG_RT2800PCI_PCI */
313 +
314 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
315 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
316 + .owner = THIS_MODULE,
317 + .csr = {
318 + .read = rt2x00pci_register_read,
319 + .write = rt2x00pci_register_write,
320 + .flags = RT2X00DEBUGFS_OFFSET,
321 + .word_base = CSR_REG_BASE,
322 + .word_size = sizeof(u32),
323 + .word_count = CSR_REG_SIZE / sizeof(u32),
324 + },
325 + .eeprom = {
326 + .read = rt2x00_eeprom_read,
327 + .write = rt2x00_eeprom_write,
328 + .word_base = EEPROM_BASE,
329 + .word_size = sizeof(u16),
330 + .word_count = EEPROM_SIZE / sizeof(u16),
331 + },
332 + .bbp = {
333 + .read = rt2800pci_bbp_read,
334 + .write = rt2800pci_bbp_write,
335 + .word_base = BBP_BASE,
336 + .word_size = sizeof(u8),
337 + .word_count = BBP_SIZE / sizeof(u8),
338 + },
339 + .rf = {
340 + .read = rt2x00_rf_read,
341 + .write = rt2800pci_rf_write,
342 + .word_base = RF_BASE,
343 + .word_size = sizeof(u32),
344 + .word_count = RF_SIZE / sizeof(u32),
345 + },
346 +};
347 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
348 +
349 +#ifdef CONFIG_RT2X00_LIB_RFKILL
350 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
351 +{
352 + u32 reg;
353 +
354 + rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
355 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
356 +}
357 +#else
358 +#define rt2800pci_rfkill_poll NULL
359 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
360 +
361 +#ifdef CONFIG_RT2X00_LIB_LEDS
362 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
363 + enum led_brightness brightness)
364 +{
365 + struct rt2x00_led *led =
366 + container_of(led_cdev, struct rt2x00_led, led_dev);
367 + unsigned int enabled = brightness != LED_OFF;
368 + unsigned int bg_mode =
369 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
370 + unsigned int polarity =
371 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
372 + EEPROM_FREQ_LED_POLARITY);
373 + unsigned int ledmode =
374 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
375 + EEPROM_FREQ_LED_MODE);
376 +
377 + if (led->type == LED_TYPE_RADIO) {
378 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
379 + enabled ? 0x20 : 0);
380 + } else if (led->type == LED_TYPE_ASSOC) {
381 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
382 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
383 + } else if (led->type == LED_TYPE_QUALITY) {
384 + /*
385 + * The brightness is divided into 6 levels (0 - 5),
386 + * The specs tell us the following levels:
387 + * 0, 1 ,3, 7, 15, 31
388 + * to determine the level in a simple way we can simply
389 + * work with bitshifting:
390 + * (1 << level) - 1
391 + */
392 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
393 + (1 << brightness / (LED_FULL / 6)) - 1,
394 + polarity);
395 + }
396 +}
397 +
398 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
399 + unsigned long *delay_on,
400 + unsigned long *delay_off)
401 +{
402 + struct rt2x00_led *led =
403 + container_of(led_cdev, struct rt2x00_led, led_dev);
404 + u32 reg;
405 +
406 + rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
407 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
408 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
409 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
410 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
411 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
412 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
413 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
414 + rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
415 +
416 + return 0;
417 +}
418 +
419 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
420 + struct rt2x00_led *led,
421 + enum led_type type)
422 +{
423 + led->rt2x00dev = rt2x00dev;
424 + led->type = type;
425 + led->led_dev.brightness_set = rt2800pci_brightness_set;
426 + led->led_dev.blink_set = rt2800pci_blink_set;
427 + led->flags = LED_INITIALIZED;
428 +}
429 +#endif /* CONFIG_RT2X00_LIB_LEDS */
430 +
431 +/*
432 + * Configuration handlers.
433 + */
434 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
435 + struct rt2x00lib_crypto *crypto,
436 + struct ieee80211_key_conf *key)
437 +{
438 + struct mac_wcid_entry wcid_entry;
439 + struct mac_iveiv_entry iveiv_entry;
440 + u32 offset;
441 + u32 reg;
442 +
443 + offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
444 +
445 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
446 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
447 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
448 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
449 + (crypto->cmd == SET_KEY) * crypto->cipher);
450 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
451 + (crypto->cmd == SET_KEY) * crypto->bssidx);
452 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
453 + rt2x00pci_register_write(rt2x00dev, offset, reg);
454 +
455 + offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
456 +
457 + memset(&iveiv_entry, 0, sizeof(iveiv_entry));
458 + if ((crypto->cipher == CIPHER_TKIP) ||
459 + (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
460 + (crypto->cipher == CIPHER_AES))
461 + iveiv_entry.iv[3] |= 0x20;
462 + iveiv_entry.iv[3] |= key->keyidx << 6;
463 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
464 + &iveiv_entry, sizeof(iveiv_entry));
465 +
466 + offset = MAC_WCID_ENTRY(key->hw_key_idx);
467 +
468 + memset(&wcid_entry, 0, sizeof(wcid_entry));
469 + if (crypto->cmd == SET_KEY)
470 + memcpy(&wcid_entry, crypto->address, ETH_ALEN);
471 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
472 + &wcid_entry, sizeof(wcid_entry));
473 +}
474 +
475 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
476 + struct rt2x00lib_crypto *crypto,
477 + struct ieee80211_key_conf *key)
478 +{
479 + struct hw_key_entry key_entry;
480 + struct rt2x00_field32 field;
481 + u32 offset;
482 + u32 reg;
483 +
484 + if (crypto->cmd == SET_KEY) {
485 + key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
486 +
487 + memcpy(key_entry.key, crypto->key,
488 + sizeof(key_entry.key));
489 + memcpy(key_entry.tx_mic, crypto->tx_mic,
490 + sizeof(key_entry.tx_mic));
491 + memcpy(key_entry.rx_mic, crypto->rx_mic,
492 + sizeof(key_entry.rx_mic));
493 +
494 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
495 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
496 + &key_entry, sizeof(key_entry));
497 + }
498 +
499 + /*
500 + * The cipher types are stored over multiple registers
501 + * starting with SHARED_KEY_MODE_BASE each word will have
502 + * 32 bits and contains the cipher types for 2 bssidx each.
503 + * Using the correct defines correctly will cause overhead,
504 + * so just calculate the correct offset.
505 + */
506 + field.bit_offset = 4 * (key->hw_key_idx % 8);
507 + field.bit_mask = 0x7 << field.bit_offset;
508 +
509 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
510 +
511 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
512 + rt2x00_set_field32(&reg, field,
513 + (crypto->cmd == SET_KEY) * crypto->cipher);
514 + rt2x00pci_register_write(rt2x00dev, offset, reg);
515 +
516 + /*
517 + * Update WCID information
518 + */
519 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
520 +
521 + return 0;
522 +}
523 +
524 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
525 + struct rt2x00lib_crypto *crypto,
526 + struct ieee80211_key_conf *key)
527 +{
528 + struct hw_key_entry key_entry;
529 + u32 offset;
530 +
531 + if (crypto->cmd == SET_KEY) {
532 + /*
533 + * 1 pairwise key is possible per AID, this means that the AID
534 + * equals our hw_key_idx. Make sure the WCID starts _after_ the
535 + * last possible shared key entry.
536 + */
537 + if (crypto->aid > (256 - 32))
538 + return -ENOSPC;
539 +
540 + key->hw_key_idx = 32 + crypto->aid;
541 +
542 +
543 + memcpy(key_entry.key, crypto->key,
544 + sizeof(key_entry.key));
545 + memcpy(key_entry.tx_mic, crypto->tx_mic,
546 + sizeof(key_entry.tx_mic));
547 + memcpy(key_entry.rx_mic, crypto->rx_mic,
548 + sizeof(key_entry.rx_mic));
549 +
550 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
551 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
552 + &key_entry, sizeof(key_entry));
553 + }
554 +
555 + /*
556 + * Update WCID information
557 + */
558 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
559 +
560 + return 0;
561 +}
562 +
563 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
564 + const unsigned int filter_flags)
565 +{
566 + u32 reg;
567 +
568 + /*
569 + * Start configuration steps.
570 + * Note that the version error will always be dropped
571 + * and broadcast frames will always be accepted since
572 + * there is no filter for it at this time.
573 + */
574 + rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
575 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
576 + !(filter_flags & FIF_FCSFAIL));
577 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
578 + !(filter_flags & FIF_PLCPFAIL));
579 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
580 + !(filter_flags & FIF_PROMISC_IN_BSS));
581 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
582 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
583 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
584 + !(filter_flags & FIF_ALLMULTI));
585 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
586 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
587 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
588 + !(filter_flags & FIF_CONTROL));
589 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
590 + !(filter_flags & FIF_CONTROL));
591 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
592 + !(filter_flags & FIF_CONTROL));
593 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
594 + !(filter_flags & FIF_CONTROL));
595 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
596 + !(filter_flags & FIF_CONTROL));
597 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
598 + !(filter_flags & FIF_CONTROL));
599 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
600 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
601 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
602 + !(filter_flags & FIF_CONTROL));
603 + rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
604 +}
605 +
606 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
607 + struct rt2x00_intf *intf,
608 + struct rt2x00intf_conf *conf,
609 + const unsigned int flags)
610 +{
611 + unsigned int beacon_base;
612 + u32 reg;
613 +
614 + if (flags & CONFIG_UPDATE_TYPE) {
615 + /*
616 + * Clear current synchronisation setup.
617 + * For the Beacon base registers we only need to clear
618 + * the first byte since that byte contains the VALID and OWNER
619 + * bits which (when set to 0) will invalidate the entire beacon.
620 + */
621 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
622 + rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
623 +
624 + /*
625 + * Enable synchronisation.
626 + */
627 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
628 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
629 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
630 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
631 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
632 + }
633 +
634 + if (flags & CONFIG_UPDATE_MAC) {
635 + reg = le32_to_cpu(conf->mac[1]);
636 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
637 + conf->mac[1] = cpu_to_le32(reg);
638 +
639 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
640 + conf->mac, sizeof(conf->mac));
641 + }
642 +
643 + if (flags & CONFIG_UPDATE_BSSID) {
644 + reg = le32_to_cpu(conf->bssid[1]);
645 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
646 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
647 + conf->bssid[1] = cpu_to_le32(reg);
648 +
649 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
650 + conf->bssid, sizeof(conf->bssid));
651 + }
652 +}
653 +
654 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
655 + struct rt2x00lib_erp *erp)
656 +{
657 + u32 reg;
658 +
659 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
660 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
661 + DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
662 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
663 +
664 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
665 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
666 + !!erp->short_preamble);
667 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
668 + !!erp->short_preamble);
669 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
670 +
671 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
672 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
673 + erp->cts_protection ? 2 : 0);
674 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
675 +
676 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
677 + erp->basic_rates);
678 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
679 +
680 + rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
681 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
682 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
683 + rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
684 +
685 + rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
686 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
687 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
688 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
689 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
690 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
691 + rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
692 +}
693 +
694 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
695 + struct antenna_setup *ant)
696 +{
697 + u16 eeprom;
698 + u8 r1;
699 + u8 r3;
700 +
701 + /*
702 + * FIXME: Use requested antenna configuration.
703 + */
704 +
705 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
706 +
707 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
708 + rt2800pci_bbp_read(rt2x00dev, 3, &r3);
709 +
710 + /*
711 + * Configure the TX antenna.
712 + */
713 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
714 + case 1:
715 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
716 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
717 + break;
718 + case 2:
719 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
720 + break;
721 + case 3:
722 + /* Do nothing */
723 + break;
724 + }
725 +
726 + /*
727 + * Configure the RX antenna.
728 + */
729 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
730 + case 1:
731 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
732 + break;
733 + case 2:
734 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
735 + break;
736 + case 3:
737 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
738 + break;
739 + }
740 +
741 + rt2800pci_bbp_write(rt2x00dev, 3, r3);
742 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
743 +}
744 +
745 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
746 + struct rt2x00lib_conf *libconf)
747 +{
748 + u16 eeprom;
749 + short lna_gain;
750 +
751 + if (libconf->rf.channel <= 14) {
752 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
753 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
754 + } else if (libconf->rf.channel <= 64) {
755 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
756 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
757 + } else if (libconf->rf.channel <= 128) {
758 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
759 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
760 + } else {
761 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
762 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
763 + }
764 +
765 + rt2x00dev->lna_gain = lna_gain;
766 +}
767 +
768 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
769 + struct ieee80211_conf *conf,
770 + struct rf_channel *rf,
771 + struct channel_info *info)
772 +{
773 + u32 reg;
774 + unsigned int tx_pin;
775 + u16 eeprom;
776 +
777 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
778 +
779 + /*
780 + * Determine antenna settings from EEPROM
781 + */
782 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
783 +
784 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
785 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
786 + }
787 +
788 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
789 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
790 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
791 + } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
792 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
793 +
794 + if (rf->channel > 14) {
795 + /*
796 + * When TX power is below 0, we should increase it by 7 to
797 + * make it a positive value (Minumum value is -7).
798 + * However this means that values between 0 and 7 have
799 + * double meaning, and we should set a 7DBm boost flag.
800 + */
801 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
802 + (info->tx_power1 >= 0));
803 +
804 + if (info->tx_power1 < 0)
805 + info->tx_power1 += 7;
806 +
807 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
808 + TXPOWER_A_TO_DEV(info->tx_power1));
809 +
810 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
811 + (info->tx_power2 >= 0));
812 +
813 + if (info->tx_power2 < 0)
814 + info->tx_power2 += 7;
815 +
816 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
817 + TXPOWER_A_TO_DEV(info->tx_power2));
818 + } else {
819 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
820 + TXPOWER_G_TO_DEV(info->tx_power1));
821 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
822 + TXPOWER_G_TO_DEV(info->tx_power2));
823 + }
824 +
825 + rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
826 +
827 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
828 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
829 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
830 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
831 +
832 + udelay(200);
833 +
834 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
835 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
836 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
837 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
838 +
839 + udelay(200);
840 +
841 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
842 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
843 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
844 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
845 +
846 + /*
847 + * Change BBP settings
848 + */
849 + rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
850 + rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
851 + rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
852 + rt2800pci_bbp_write(rt2x00dev, 86, 0);
853 +
854 + if (rf->channel <= 14) {
855 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
856 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
857 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
858 + } else {
859 + rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
860 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
861 + }
862 + } else {
863 + rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
864 +
865 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
866 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
867 + else
868 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
869 + }
870 +
871 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
872 + rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
873 + rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
874 + rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
875 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
876 +
877 + tx_pin = 0;
878 +
879 + /* Turn on unused PA or LNA when not using 1T or 1R */
880 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) != 1) {
881 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
882 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
883 + }
884 +
885 + /* Turn on unused PA or LNA when not using 1T or 1R */
886 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) != 1) {
887 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
888 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
889 + }
890 +
891 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
892 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
893 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
894 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
895 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
896 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
897 +
898 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
899 +
900 + msleep(1);
901 +}
902 +
903 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
904 + const int txpower)
905 +{
906 + u32 reg;
907 + u32 value = TXPOWER_G_TO_DEV(txpower);
908 + u8 r1;
909 +
910 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
911 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
912 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
913 +
914 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
915 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
916 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
917 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
918 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
919 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
920 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
921 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
922 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
923 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
924 +
925 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
926 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
927 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
928 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
929 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
930 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
931 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
932 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
933 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
934 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
935 +
936 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
937 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
938 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
939 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
940 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
941 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
942 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
943 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
944 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
945 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
946 +
947 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
948 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
949 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
950 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
951 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
952 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
953 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
954 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
955 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
956 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
957 +
958 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
959 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
960 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
961 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
962 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
963 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
964 +}
965 +
966 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
967 + struct rt2x00lib_conf *libconf)
968 +{
969 + u32 reg;
970 +
971 + rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
972 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
973 + libconf->conf->short_frame_max_tx_count);
974 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
975 + libconf->conf->long_frame_max_tx_count);
976 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
977 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
978 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
979 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
980 + rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
981 +}
982 +
983 +static void rt2800pci_config_duration(struct rt2x00_dev *rt2x00dev,
984 + struct rt2x00lib_conf *libconf)
985 +{
986 + u32 reg;
987 +
988 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
989 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
990 + libconf->conf->beacon_int * 16);
991 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
992 +}
993 +
994 +static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
995 + struct rt2x00lib_conf *libconf)
996 +{
997 + enum dev_state state =
998 + (libconf->conf->flags & IEEE80211_CONF_PS) ?
999 + STATE_SLEEP : STATE_AWAKE;
1000 + u32 reg;
1001 +
1002 + if (state == STATE_SLEEP) {
1003 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1004 +
1005 + rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1006 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1007 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1008 + libconf->conf->listen_interval - 1);
1009 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1010 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1011 +
1012 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1013 + } else {
1014 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1015 +
1016 + rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1017 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1018 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1019 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1020 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1021 + }
1022 +}
1023 +
1024 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
1025 + struct rt2x00lib_conf *libconf,
1026 + const unsigned int flags)
1027 +{
1028 + /* Always recalculate LNA gain before changing configuration */
1029 + rt2800pci_config_lna_gain(rt2x00dev, libconf);
1030 +
1031 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1032 + rt2800pci_config_channel(rt2x00dev, libconf->conf,
1033 + &libconf->rf, &libconf->channel);
1034 + if (flags & IEEE80211_CONF_CHANGE_POWER)
1035 + rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1036 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1037 + rt2800pci_config_retry_limit(rt2x00dev, libconf);
1038 + if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1039 + rt2800pci_config_duration(rt2x00dev, libconf);
1040 + if (flags & IEEE80211_CONF_CHANGE_PS)
1041 + rt2800pci_config_ps(rt2x00dev, libconf);
1042 +}
1043 +
1044 +/*
1045 + * Link tuning
1046 + */
1047 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
1048 + struct link_qual *qual)
1049 +{
1050 + u32 reg;
1051 +
1052 + /*
1053 + * Update FCS error count from register.
1054 + */
1055 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1056 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1057 +}
1058 +
1059 +static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1060 +{
1061 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
1062 + return 0x2e + rt2x00dev->lna_gain;
1063 +
1064 + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1065 + return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1066 + else
1067 + return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1068 +}
1069 +
1070 +static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1071 + struct link_qual *qual, u8 vgc_level)
1072 +{
1073 + if (qual->vgc_level != vgc_level) {
1074 + rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
1075 + qual->vgc_level = vgc_level;
1076 + qual->vgc_level_reg = vgc_level;
1077 + }
1078 +}
1079 +
1080 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1081 + struct link_qual *qual)
1082 +{
1083 + rt2800pci_set_vgc(rt2x00dev, qual,
1084 + rt2800pci_get_default_vgc(rt2x00dev));
1085 +}
1086 +
1087 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1088 + struct link_qual *qual, const u32 count)
1089 +{
1090 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1091 + return;
1092 +
1093 + /*
1094 + * When RSSI is better then -80 increase VGC level with 0x10
1095 + */
1096 + rt2800pci_set_vgc(rt2x00dev, qual,
1097 + rt2800pci_get_default_vgc(rt2x00dev) +
1098 + ((qual->rssi > -80) * 0x10));
1099 +}
1100 +
1101 +/*
1102 + * Firmware functions
1103 + */
1104 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1105 +{
1106 + return FIRMWARE_RT2860;
1107 +}
1108 +
1109 +static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1110 + const u8 *data, const size_t len)
1111 +{
1112 + u16 fw_crc;
1113 + u16 crc;
1114 +
1115 + /*
1116 + * Only support 8kb firmware files.
1117 + */
1118 + if (len != 8192)
1119 + return FW_BAD_LENGTH;
1120 +
1121 + /*
1122 + * The last 2 bytes in the firmware array are the crc checksum itself,
1123 + * this means that we should never pass those 2 bytes to the crc
1124 + * algorithm.
1125 + */
1126 + fw_crc = (data[len - 2] << 8 | data[len - 1]);
1127 +
1128 + /*
1129 + * Use the crc ccitt algorithm.
1130 + * This will return the same value as the legacy driver which
1131 + * used bit ordering reversion on the both the firmware bytes
1132 + * before input input as well as on the final output.
1133 + * Obviously using crc ccitt directly is much more efficient.
1134 + */
1135 + crc = crc_ccitt(~0, data, len - 2);
1136 +
1137 + /*
1138 + * There is a small difference between the crc-itu-t + bitrev and
1139 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
1140 + * will be swapped, use swab16 to convert the crc to the correct
1141 + * value.
1142 + */
1143 + crc = swab16(crc);
1144 +
1145 + return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1146 +}
1147 +
1148 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1149 + const u8 *data, const size_t len)
1150 +{
1151 + unsigned int i;
1152 + u32 reg;
1153 +
1154 + /*
1155 + * Wait for stable hardware.
1156 + */
1157 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1158 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1159 + if (reg && reg != ~0)
1160 + break;
1161 + msleep(1);
1162 + }
1163 +
1164 + if (i == REGISTER_BUSY_COUNT) {
1165 + ERROR(rt2x00dev, "Unstable hardware.\n");
1166 + return -EBUSY;
1167 + }
1168 +
1169 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1170 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1171 +
1172 + /*
1173 + * Disable DMA, will be reenabled later when enabling
1174 + * the radio.
1175 + */
1176 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1177 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1178 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1179 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1180 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1181 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1182 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1183 +
1184 + /*
1185 + * enable Host program ram write selection
1186 + */
1187 + reg = 0;
1188 + rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1189 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1190 +
1191 + /*
1192 + * Write firmware to device.
1193 + */
1194 + rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1195 + data, len);
1196 +
1197 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1198 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1199 +
1200 + /*
1201 + * Wait for device to stabilize.
1202 + */
1203 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1204 + rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1205 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1206 + break;
1207 + msleep(1);
1208 + }
1209 +
1210 + if (i == REGISTER_BUSY_COUNT) {
1211 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1212 + return -EBUSY;
1213 + }
1214 +
1215 + /*
1216 + * Disable interrupts
1217 + */
1218 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
1219 +
1220 + /*
1221 + * Initialize BBP R/W access agent
1222 + */
1223 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1224 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1225 +
1226 + return 0;
1227 +}
1228 +
1229 +/*
1230 + * Initialization functions.
1231 + */
1232 +static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1233 +{
1234 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1235 + u32 word;
1236 +
1237 + if (entry->queue->qid == QID_RX) {
1238 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1239 +
1240 + return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1241 + } else {
1242 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1243 +
1244 + return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1245 + }
1246 +}
1247 +
1248 +static void rt2800pci_clear_entry(struct queue_entry *entry)
1249 +{
1250 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1251 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1252 + u32 word;
1253 +
1254 + if (entry->queue->qid == QID_RX) {
1255 + rt2x00_desc_read(entry_priv->desc, 0, &word);
1256 + rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1257 + rt2x00_desc_write(entry_priv->desc, 0, word);
1258 +
1259 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1260 + rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1261 + rt2x00_desc_write(entry_priv->desc, 1, word);
1262 + } else {
1263 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1264 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1265 + rt2x00_desc_write(entry_priv->desc, 1, word);
1266 + }
1267 +}
1268 +
1269 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1270 +{
1271 + struct queue_entry_priv_pci *entry_priv;
1272 + u32 reg;
1273 +
1274 + /*
1275 + * Initialize registers.
1276 + */
1277 + entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1278 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1279 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1280 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1281 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
1282 +
1283 + entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1284 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1285 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1286 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1287 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
1288 +
1289 + entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1290 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1291 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1292 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1293 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
1294 +
1295 + entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1296 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1297 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1298 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1299 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
1300 +
1301 + entry_priv = rt2x00dev->rx->entries[0].priv_data;
1302 + rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1303 + rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1304 + rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 0);
1305 + rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
1306 +
1307 + /*
1308 + * Enable global DMA configuration
1309 + */
1310 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1311 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1312 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1313 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1314 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1315 +
1316 + rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1317 +
1318 + return 0;
1319 +}
1320 +
1321 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1322 +{
1323 + u32 reg;
1324 + unsigned int i;
1325 +
1326 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1327 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1328 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1329 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1330 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1331 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1332 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1333 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1334 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1335 +
1336 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1337 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1338 +
1339 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1340 +
1341 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1342 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1343 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1344 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1345 +
1346 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1347 +
1348 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1349 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1350 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1351 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1352 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1353 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1354 +
1355 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1356 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1357 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1358 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1359 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1360 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1361 +
1362 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1363 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1364 +
1365 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1366 +
1367 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1368 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1369 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1370 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1371 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1372 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1373 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1374 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1375 +
1376 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1377 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1378 +
1379 + rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1380 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1381 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1382 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1383 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1384 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1385 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1386 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1387 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1388 + rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1389 +
1390 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1391 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1392 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1393 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1394 +
1395 + rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1396 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1397 + if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1398 + rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1399 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1400 + else
1401 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1402 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1403 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1404 + rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1405 +
1406 + rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1407 +
1408 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1409 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1410 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1411 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1412 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1413 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1414 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1415 +
1416 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1417 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1418 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1419 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1420 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1421 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1422 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1423 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1424 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1425 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1426 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1427 +
1428 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1429 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1430 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1431 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1432 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1433 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1434 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1435 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1436 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1437 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1438 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1439 +
1440 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1441 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1442 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1443 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1444 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1445 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1446 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1447 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1448 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1449 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1450 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1451 +
1452 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1453 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1454 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1455 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1456 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1457 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1458 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1459 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1460 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1461 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1462 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1463 +
1464 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1465 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1466 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1467 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1468 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1469 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1470 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1471 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1472 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1473 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1474 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1475 +
1476 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1477 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1478 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1479 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1480 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1481 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1482 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1483 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1484 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1485 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1486 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1487 +
1488 + rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1489 + rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1490 +
1491 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1492 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1493 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1494 + IEEE80211_MAX_RTS_THRESHOLD);
1495 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1496 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1497 +
1498 + rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1499 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1500 +
1501 + /*
1502 + * ASIC will keep garbage value after boot, clear encryption keys.
1503 + */
1504 + for (i = 0; i < 256; i++) {
1505 + u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1506 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1507 + wcid, sizeof(wcid));
1508 +
1509 + rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1510 + rt2x00pci_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1511 + }
1512 +
1513 + for (i = 0; i < 16; i++)
1514 + rt2x00pci_register_write(rt2x00dev,
1515 + SHARED_KEY_MODE_ENTRY(i), 0);
1516 +
1517 + /*
1518 + * Clear all beacons
1519 + * For the Beacon base registers we only need to clear
1520 + * the first byte since that byte contains the VALID and OWNER
1521 + * bits which (when set to 0) will invalidate the entire beacon.
1522 + */
1523 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1524 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1525 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1526 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1527 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1528 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1529 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1530 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1531 +
1532 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1533 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1534 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1535 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1536 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1537 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1538 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1539 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1540 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1541 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1542 +
1543 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1544 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1545 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1546 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1547 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1548 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1549 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1550 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1551 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1552 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1553 +
1554 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1555 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1556 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1557 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1558 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1559 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1560 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1561 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1562 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1563 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1564 +
1565 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1566 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1567 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1568 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1569 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1570 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1571 +
1572 + /*
1573 + * We must clear the error counters.
1574 + * These registers are cleared on read,
1575 + * so we may pass a useless variable to store the value.
1576 + */
1577 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1578 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1579 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1580 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1581 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1582 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1583 +
1584 + return 0;
1585 +}
1586 +
1587 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1588 +{
1589 + unsigned int i;
1590 + u32 reg;
1591 +
1592 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1593 + rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1594 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1595 + return 0;
1596 +
1597 + udelay(REGISTER_BUSY_DELAY);
1598 + }
1599 +
1600 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1601 + return -EACCES;
1602 +}
1603 +
1604 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1605 +{
1606 + unsigned int i;
1607 + u8 value;
1608 +
1609 + /*
1610 + * BBP was enabled after firmware was loaded,
1611 + * but we need to reactivate it now.
1612 + */
1613 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1614 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1615 + msleep(1);
1616 +
1617 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1618 + rt2800pci_bbp_read(rt2x00dev, 0, &value);
1619 + if ((value != 0xff) && (value != 0x00))
1620 + return 0;
1621 + udelay(REGISTER_BUSY_DELAY);
1622 + }
1623 +
1624 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1625 + return -EACCES;
1626 +}
1627 +
1628 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1629 +{
1630 + unsigned int i;
1631 + u16 eeprom;
1632 + u8 reg_id;
1633 + u8 value;
1634 +
1635 + if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1636 + rt2800pci_wait_bbp_ready(rt2x00dev)))
1637 + return -EACCES;
1638 +
1639 + rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1640 + rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1641 + rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1642 + rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1643 + rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1644 + rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1645 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1646 + rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1647 + rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1648 + rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1649 + rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1650 + rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1651 + rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1652 + rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1653 +
1654 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1655 + rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1656 + rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1657 + }
1658 +
1659 + if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1660 + rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1661 +
1662 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1663 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1664 +
1665 + if (eeprom != 0xffff && eeprom != 0x0000) {
1666 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1667 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1668 + rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1669 + }
1670 + }
1671 +
1672 + return 0;
1673 +}
1674 +
1675 +/*
1676 + * Device state switch handlers.
1677 + */
1678 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1679 + enum dev_state state)
1680 +{
1681 + u32 reg;
1682 +
1683 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1684 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1685 + (state == STATE_RADIO_RX_ON) ||
1686 + (state == STATE_RADIO_RX_ON_LINK));
1687 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1688 +}
1689 +
1690 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1691 + enum dev_state state)
1692 +{
1693 + int mask = (state == STATE_RADIO_IRQ_ON);
1694 + u32 reg;
1695 +
1696 + /*
1697 + * When interrupts are being enabled, the interrupt registers
1698 + * should clear the register to assure a clean state.
1699 + */
1700 + if (state == STATE_RADIO_IRQ_ON) {
1701 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1702 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1703 + }
1704 +
1705 + rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1706 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1707 + rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1708 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1709 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1710 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1711 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1712 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1713 + rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1714 + rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1715 + rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1716 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
1717 + rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
1718 + rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
1719 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
1720 + rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
1721 + rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1722 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1723 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1724 + rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1725 +}
1726 +
1727 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1728 +{
1729 + unsigned int i;
1730 + u32 reg;
1731 +
1732 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1733 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1734 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1735 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1736 + return 0;
1737 +
1738 + msleep(1);
1739 + }
1740 +
1741 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1742 + return -EACCES;
1743 +}
1744 +
1745 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1746 +{
1747 + u32 reg;
1748 + u16 word;
1749 +
1750 + /*
1751 + * Initialize all registers.
1752 + */
1753 + if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1754 + rt2800pci_init_queues(rt2x00dev) ||
1755 + rt2800pci_init_registers(rt2x00dev) ||
1756 + rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1757 + rt2800pci_init_bbp(rt2x00dev)))
1758 + return -EIO;
1759 +
1760 + /*
1761 + * Send signal to firmware during boot time.
1762 + */
1763 + rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1764 +
1765 + /*
1766 + * Enable RX.
1767 + */
1768 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1769 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1770 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
1771 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1772 +
1773 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1774 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1775 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1776 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
1777 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1778 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1779 +
1780 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1781 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1782 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1783 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1784 +
1785 + /*
1786 + * Initialize LED control
1787 + */
1788 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1789 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1790 + word & 0xff, (word >> 8) & 0xff);
1791 +
1792 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1793 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1794 + word & 0xff, (word >> 8) & 0xff);
1795 +
1796 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1797 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1798 + word & 0xff, (word >> 8) & 0xff);
1799 +
1800 + return 0;
1801 +}
1802 +
1803 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1804 +{
1805 + u32 reg;
1806 +
1807 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1808 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1809 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1810 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1811 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1812 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1813 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1814 +
1815 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1816 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1817 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
1818 +
1819 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
1820 +
1821 + /* Wait for DMA, ignore error */
1822 + rt2800pci_wait_wpdma_ready(rt2x00dev);
1823 +}
1824 +
1825 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
1826 + enum dev_state state)
1827 +{
1828 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1829 +
1830 + if (state == STATE_AWAKE) {
1831 + rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
1832 + rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
1833 + } else
1834 + rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1835 +
1836 + return 0;
1837 +}
1838 +
1839 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1840 + enum dev_state state)
1841 +{
1842 + int retval = 0;
1843 +
1844 + switch (state) {
1845 + case STATE_RADIO_ON:
1846 + /*
1847 + * Before the radio can be enabled, the device first has
1848 + * to be woken up. After that it needs a bit of time
1849 + * to be fully awake and the radio can be enabled.
1850 + */
1851 + rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
1852 + msleep(1);
1853 + retval = rt2800pci_enable_radio(rt2x00dev);
1854 + break;
1855 + case STATE_RADIO_OFF:
1856 + /*
1857 + * After the radio has been disablee, the device should
1858 + * be put to sleep for powersaving.
1859 + */
1860 + rt2800pci_disable_radio(rt2x00dev);
1861 + rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
1862 + break;
1863 + case STATE_RADIO_RX_ON:
1864 + case STATE_RADIO_RX_ON_LINK:
1865 + case STATE_RADIO_RX_OFF:
1866 + case STATE_RADIO_RX_OFF_LINK:
1867 + rt2800pci_toggle_rx(rt2x00dev, state);
1868 + break;
1869 + case STATE_RADIO_IRQ_ON:
1870 + case STATE_RADIO_IRQ_OFF:
1871 + rt2800pci_toggle_irq(rt2x00dev, state);
1872 + break;
1873 + case STATE_DEEP_SLEEP:
1874 + case STATE_SLEEP:
1875 + case STATE_STANDBY:
1876 + case STATE_AWAKE:
1877 + retval = rt2800pci_set_state(rt2x00dev, state);
1878 + break;
1879 + default:
1880 + retval = -ENOTSUPP;
1881 + break;
1882 + }
1883 +
1884 + if (unlikely(retval))
1885 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1886 + state, retval);
1887 +
1888 + return retval;
1889 +}
1890 +
1891 +/*
1892 + * TX descriptor initialization
1893 + */
1894 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1895 + struct sk_buff *skb,
1896 + struct txentry_desc *txdesc)
1897 +{
1898 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1899 + __le32 *txd = skbdesc->desc;
1900 + __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
1901 + u32 word;
1902 +
1903 + /*
1904 + * Initialize TX Info descriptor
1905 + */
1906 + rt2x00_desc_read(txwi, 0, &word);
1907 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
1908 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1909 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1910 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1911 + rt2x00_set_field32(&word, TXWI_W0_TS,
1912 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1913 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1914 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1915 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1916 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1917 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1918 + rt2x00_set_field32(&word, TXWI_W0_BW,
1919 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1920 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1921 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1922 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1923 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1924 + rt2x00_desc_write(txwi, 0, word);
1925 +
1926 + rt2x00_desc_read(txwi, 1, &word);
1927 + rt2x00_set_field32(&word, TXWI_W1_ACK,
1928 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1929 + rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1930 + test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1931 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1932 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
1933 + test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
1934 + txdesc->key_idx : 0xff);
1935 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
1936 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1937 + skbdesc->entry->queue->qid);
1938 + rt2x00_desc_write(txwi, 1, word);
1939 +
1940 + /*
1941 + * Always write 0 to IV/EIV fields, hardware will insert the IV
1942 + * from the IVEIV register when ENTRY_TXD_ENCRYPT_IV is set to 0.
1943 + * When ENTRY_TXD_ENCRYPT_IV is set to 1 it will use the IV data
1944 + * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
1945 + * crypto entry in the registers should be used to encrypt the frame.
1946 + */
1947 + _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
1948 + _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
1949 +
1950 + /*
1951 + * Initialize TX descriptor
1952 + */
1953 + rt2x00_desc_read(txd, 0, &word);
1954 + rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
1955 + rt2x00_desc_write(txd, 0, word);
1956 +
1957 + rt2x00_desc_read(txd, 1, &word);
1958 + rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
1959 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
1960 + rt2x00_set_field32(&word, TXD_W1_BURST,
1961 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1962 + rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
1963 + rt2x00dev->hw->extra_tx_headroom);
1964 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
1965 + !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1966 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
1967 + rt2x00_desc_write(txd, 1, word);
1968 +
1969 + rt2x00_desc_read(txd, 2, &word);
1970 + rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
1971 + skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
1972 + rt2x00_desc_write(txd, 2, word);
1973 +
1974 + rt2x00_desc_read(txd, 3, &word);
1975 + rt2x00_set_field32(&word, TXD_W3_WIV,
1976 + !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
1977 + rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
1978 + rt2x00_desc_write(txd, 3, word);
1979 +}
1980 +
1981 +/*
1982 + * TX data initialization
1983 + */
1984 +static void rt2800pci_write_beacon(struct queue_entry *entry)
1985 +{
1986 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1987 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1988 + unsigned int beacon_base;
1989 + u32 reg;
1990 +
1991 + /*
1992 + * Disable beaconing while we are reloading the beacon data,
1993 + * otherwise we might be sending out invalid data.
1994 + */
1995 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1996 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1997 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1998 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1999 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2000 +
2001 + /*
2002 + * Write entire beacon with descriptor to register.
2003 + */
2004 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2005 + rt2x00pci_register_multiwrite(rt2x00dev,
2006 + beacon_base,
2007 + skbdesc->desc, skbdesc->desc_len);
2008 + rt2x00pci_register_multiwrite(rt2x00dev,
2009 + beacon_base + skbdesc->desc_len,
2010 + entry->skb->data, entry->skb->len);
2011 +
2012 + /*
2013 + * Clean up beacon skb.
2014 + */
2015 + dev_kfree_skb_any(entry->skb);
2016 + entry->skb = NULL;
2017 +}
2018 +
2019 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2020 + const enum data_queue_qid queue_idx)
2021 +{
2022 + struct data_queue *queue;
2023 + unsigned int idx, qidx = 0;
2024 + u32 reg;
2025 +
2026 + if (queue_idx == QID_BEACON) {
2027 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2028 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2029 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2030 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2031 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2032 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2033 + }
2034 + return;
2035 + }
2036 +
2037 + if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
2038 + return;
2039 +
2040 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2041 + idx = queue->index[Q_INDEX];
2042 +
2043 + if (queue_idx == QID_MGMT)
2044 + qidx = 5;
2045 + else
2046 + qidx = queue_idx;
2047 +
2048 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
2049 +}
2050 +
2051 +static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
2052 + const enum data_queue_qid qid)
2053 +{
2054 + u32 reg;
2055 +
2056 + if (qid == QID_BEACON) {
2057 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, 0);
2058 + return;
2059 + }
2060 +
2061 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2062 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
2063 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
2064 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
2065 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
2066 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2067 +}
2068 +
2069 +/*
2070 + * RX control handlers
2071 + */
2072 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
2073 + struct rxdone_entry_desc *rxdesc)
2074 +{
2075 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2076 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
2077 + __le32 *rxd = entry_priv->desc;
2078 + __le32 *rxwi = (__le32 *)entry->skb->data;
2079 + u32 rxd3;
2080 + u32 rxwi0;
2081 + u32 rxwi1;
2082 + u32 rxwi2;
2083 + u32 rxwi3;
2084 +
2085 + rt2x00_desc_read(rxd, 3, &rxd3);
2086 + rt2x00_desc_read(rxwi, 0, &rxwi0);
2087 + rt2x00_desc_read(rxwi, 1, &rxwi1);
2088 + rt2x00_desc_read(rxwi, 2, &rxwi2);
2089 + rt2x00_desc_read(rxwi, 3, &rxwi3);
2090 +
2091 + if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
2092 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2093 +
2094 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2095 + /*
2096 + * Unfortunately we don't know the cipher type used during
2097 + * decryption. This prevents us from correct providing
2098 + * correct statistics through debugfs.
2099 + */
2100 + rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2101 + rxdesc->cipher_status =
2102 + rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
2103 + }
2104 +
2105 + if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
2106 + /*
2107 + * Hardware has stripped IV/EIV data from 802.11 frame during
2108 + * decryption. Unfortunately the descriptor doesn't contain
2109 + * any fields with the EIV/IV data either, so they can't
2110 + * be restored by rt2x00lib.
2111 + */
2112 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2113 +
2114 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2115 + rxdesc->flags |= RX_FLAG_DECRYPTED;
2116 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2117 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2118 + }
2119 +
2120 + if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
2121 + rxdesc->dev_flags |= RXDONE_MY_BSS;
2122 +
2123 + if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2124 + rxdesc->flags |= RX_FLAG_SHORT_GI;
2125 +
2126 + if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2127 + rxdesc->flags |= RX_FLAG_40MHZ;
2128 +
2129 + /*
2130 + * Detect RX rate, always use MCS as signal type.
2131 + */
2132 + rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2133 + rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2134 + rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2135 +
2136 + /*
2137 + * Mask of 0x8 bit to remove the short preamble flag.
2138 + */
2139 + if (rxdesc->rate_mode == RATE_MODE_CCK)
2140 + rxdesc->signal &= ~0x8;
2141 +
2142 + rxdesc->rssi =
2143 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2144 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2145 +
2146 + rxdesc->noise =
2147 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2148 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2149 +
2150 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2151 +
2152 + /*
2153 + * Remove TXWI descriptor from start of buffer.
2154 + */
2155 + skb_pull(entry->skb, RXWI_DESC_SIZE);
2156 + skb_trim(entry->skb, rxdesc->size);
2157 +}
2158 +
2159 +/*
2160 + * Interrupt functions.
2161 + */
2162 +static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2163 +{
2164 + struct data_queue *queue;
2165 + struct queue_entry *entry;
2166 + struct queue_entry *entry_done;
2167 + struct queue_entry_priv_pci *entry_priv;
2168 + struct txdone_entry_desc txdesc;
2169 + u32 word;
2170 + u32 reg;
2171 + u32 old_reg;
2172 + int type;
2173 + int index;
2174 +
2175 + /*
2176 + * During each loop we will compare the freshly read
2177 + * TX_STA_FIFO register value with the value read from
2178 + * the previous loop. If the 2 values are equal then
2179 + * we should stop processing because the chance it
2180 + * quite big that the device has been unplugged and
2181 + * we risk going into an endless loop.
2182 + */
2183 + old_reg = 0;
2184 +
2185 + while (1) {
2186 + rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2187 + if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2188 + break;
2189 +
2190 + if (old_reg == reg)
2191 + break;
2192 + old_reg = reg;
2193 +
2194 + /*
2195 + * Skip this entry when it contains an invalid
2196 + * queue identication number.
2197 + */
2198 + type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
2199 + queue = rt2x00queue_get_queue(rt2x00dev, type);
2200 + if (unlikely(!queue))
2201 + continue;
2202 +
2203 + /*
2204 + * Skip this entry when it contains an invalid
2205 + * index number.
2206 + */
2207 + index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
2208 + if (unlikely(index >= queue->limit))
2209 + continue;
2210 +
2211 + entry = &queue->entries[index];
2212 + entry_priv = entry->priv_data;
2213 + rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
2214 +
2215 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2216 + while (entry != entry_done) {
2217 + /*
2218 + * Catch up.
2219 + * Just report any entries we missed as failed.
2220 + */
2221 + WARNING(rt2x00dev,
2222 + "TX status report missed for entry %d\n",
2223 + entry_done->entry_idx);
2224 +
2225 + txdesc.flags = 0;
2226 + __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2227 + txdesc.retry = 0;
2228 +
2229 + rt2x00lib_txdone(entry_done, &txdesc);
2230 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2231 + }
2232 +
2233 + /*
2234 + * Obtain the status about this packet.
2235 + */
2236 + txdesc.flags = 0;
2237 + if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
2238 + __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2239 + else
2240 + __set_bit(TXDONE_FAILURE, &txdesc.flags);
2241 + txdesc.retry = rt2x00_get_field32(word, TXWI_W0_MCS);
2242 +
2243 + rt2x00lib_txdone(entry, &txdesc);
2244 + }
2245 +}
2246 +
2247 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2248 +{
2249 + struct rt2x00_dev *rt2x00dev = dev_instance;
2250 + u32 reg;
2251 +
2252 + /* Read status and ACK all interrupts */
2253 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2254 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2255 +
2256 + if (!reg)
2257 + return IRQ_NONE;
2258 +
2259 + if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2260 + return IRQ_HANDLED;
2261 +
2262 + /*
2263 + * 1 - Rx ring done interrupt.
2264 + */
2265 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
2266 + rt2x00pci_rxdone(rt2x00dev);
2267 +
2268 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
2269 + rt2800pci_txdone(rt2x00dev);
2270 +
2271 + return IRQ_HANDLED;
2272 +}
2273 +
2274 +/*
2275 + * Device probe functions.
2276 + */
2277 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2278 +{
2279 + u16 word;
2280 + u8 *mac;
2281 + u8 default_lna_gain;
2282 +
2283 + /*
2284 + * Read EEPROM into buffer
2285 + */
2286 + switch(rt2x00dev->chip.rt) {
2287 + case RT2880:
2288 + case RT3052:
2289 + rt2800pci_read_eeprom_soc(rt2x00dev);
2290 + break;
2291 + default:
2292 + rt2800pci_read_eeprom_pci(rt2x00dev);
2293 + break;
2294 + }
2295 +
2296 + /*
2297 + * Start validation of the data that has been read.
2298 + */
2299 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2300 + if (!is_valid_ether_addr(mac)) {
2301 + DECLARE_MAC_BUF(macbuf);
2302 +
2303 + random_ether_addr(mac);
2304 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2305 + }
2306 +
2307 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2308 + if (word == 0xffff) {
2309 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2310 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2311 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2312 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2313 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2314 + } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2315 + /*
2316 + * There is a max of 2 RX streams for RT2860 series
2317 + */
2318 + if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2319 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2320 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2321 + }
2322 +
2323 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2324 + if (word == 0xffff) {
2325 + rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2326 + rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2327 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2328 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2329 + rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2330 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2331 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2332 + rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2333 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2334 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2335 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2336 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2337 + }
2338 +
2339 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2340 + if ((word & 0x00ff) == 0x00ff) {
2341 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2342 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2343 + LED_MODE_TXRX_ACTIVITY);
2344 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2345 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2346 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2347 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2348 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2349 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2350 + }
2351 +
2352 + /*
2353 + * During the LNA validation we are going to use
2354 + * lna0 as correct value. Note that EEPROM_LNA
2355 + * is never validated.
2356 + */
2357 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2358 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2359 +
2360 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2361 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2362 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2363 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2364 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2365 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2366 +
2367 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2368 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2369 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2370 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2371 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2372 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2373 + default_lna_gain);
2374 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2375 +
2376 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2377 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2378 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2379 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2380 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2381 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2382 +
2383 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2384 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2385 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2386 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2387 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2388 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2389 + default_lna_gain);
2390 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2391 +
2392 + return 0;
2393 +}
2394 +
2395 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2396 +{
2397 + u32 reg;
2398 + u16 value;
2399 + u16 eeprom;
2400 +
2401 + /*
2402 + * Read EEPROM word for configuration.
2403 + */
2404 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2405 +
2406 + /*
2407 + * Identify RF chipset.
2408 + */
2409 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2410 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2411 + rt2x00_set_chip_rf(rt2x00dev, value, reg);
2412 +
2413 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2414 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2415 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2416 + !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2417 + !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2418 + !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
2419 + !rt2x00_rf(&rt2x00dev->chip, RF3052)) {
2420 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2421 + return -ENODEV;
2422 + }
2423 +
2424 + /*
2425 + * Read frequency offset and RF programming sequence.
2426 + */
2427 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2428 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2429 +
2430 + /*
2431 + * Read external LNA informations.
2432 + */
2433 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2434 +
2435 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2436 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2437 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2438 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2439 +
2440 + /*
2441 + * Detect if this device has an hardware controlled radio.
2442 + */
2443 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2444 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2445 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2446 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2447 +
2448 + /*
2449 + * Store led settings, for correct led behaviour.
2450 + */
2451 +#ifdef CONFIG_RT2X00_LIB_LEDS
2452 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2453 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2454 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2455 +
2456 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2457 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2458 +
2459 + return 0;
2460 +}
2461 +
2462 +/*
2463 + * RF value list for rt2860
2464 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2465 + */
2466 +static const struct rf_channel rf_vals[] = {
2467 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2468 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2469 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2470 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2471 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2472 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2473 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2474 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2475 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2476 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2477 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2478 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2479 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2480 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2481 +
2482 + /* 802.11 UNI / HyperLan 2 */
2483 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2484 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2485 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2486 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2487 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2488 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2489 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2490 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2491 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2492 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2493 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2494 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2495 +
2496 + /* 802.11 HyperLan 2 */
2497 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2498 + { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2499 + { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
2500 + { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
2501 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2502 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2503 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2504 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2505 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2506 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2507 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2508 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2509 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2510 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2511 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2512 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2513 +
2514 + /* 802.11 UNII */
2515 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2516 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2517 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2518 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2519 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2520 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2521 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2522 +
2523 + /* 802.11 Japan */
2524 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2525 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2526 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2527 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2528 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2529 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2530 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2531 +};
2532 +
2533 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2534 +{
2535 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2536 + struct channel_info *info;
2537 + char *tx_power1;
2538 + char *tx_power2;
2539 + unsigned int i;
2540 + u16 eeprom;
2541 +
2542 + /*
2543 + * Initialize all hw fields.
2544 + */
2545 + rt2x00dev->hw->flags =
2546 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2547 + IEEE80211_HW_SIGNAL_DBM |
2548 + IEEE80211_HW_SUPPORTS_PS |
2549 + IEEE80211_HW_PS_NULLFUNC_STACK;
2550 + rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2551 +
2552 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2553 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2554 + rt2x00_eeprom_addr(rt2x00dev,
2555 + EEPROM_MAC_ADDR_0));
2556 +
2557 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2558 +
2559 + /*
2560 + * Initialize hw_mode information.
2561 + */
2562 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2563 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2564 +
2565 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2566 + rt2x00_rf(&rt2x00dev->chip, RF2720) ||
2567 + rt2x00_rf(&rt2x00dev->chip, RF3052)) {
2568 + spec->num_channels = 14;
2569 + spec->channels = rf_vals;
2570 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2571 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2572 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2573 + spec->num_channels = ARRAY_SIZE(rf_vals);
2574 + spec->channels = rf_vals;
2575 + }
2576 +
2577 + /*
2578 + * Initialize HT information.
2579 + */
2580 + spec->ht.ht_supported = true;
2581 + spec->ht.cap =
2582 + IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2583 + IEEE80211_HT_CAP_GRN_FLD |
2584 + IEEE80211_HT_CAP_SGI_20 |
2585 + IEEE80211_HT_CAP_SGI_40 |
2586 + IEEE80211_HT_CAP_TX_STBC |
2587 + IEEE80211_HT_CAP_RX_STBC |
2588 + IEEE80211_HT_CAP_PSMP_SUPPORT;
2589 + spec->ht.ampdu_factor = 3;
2590 + spec->ht.ampdu_density = 4;
2591 + spec->ht.mcs.tx_params =
2592 + IEEE80211_HT_MCS_TX_DEFINED |
2593 + IEEE80211_HT_MCS_TX_RX_DIFF |
2594 + ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2595 + IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2596 +
2597 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2598 + case 3:
2599 + spec->ht.mcs.rx_mask[2] = 0xff;
2600 + case 2:
2601 + spec->ht.mcs.rx_mask[1] = 0xff;
2602 + case 1:
2603 + spec->ht.mcs.rx_mask[0] = 0xff;
2604 + spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2605 + break;
2606 + }
2607 +
2608 + /*
2609 + * Create channel information array
2610 + */
2611 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2612 + if (!info)
2613 + return -ENOMEM;
2614 +
2615 + spec->channels_info = info;
2616 +
2617 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2618 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2619 +
2620 + for (i = 0; i < 14; i++) {
2621 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2622 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2623 + }
2624 +
2625 + if (spec->num_channels > 14) {
2626 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2627 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2628 +
2629 + for (i = 14; i < spec->num_channels; i++) {
2630 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2631 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2632 + }
2633 + }
2634 +
2635 + return 0;
2636 +}
2637 +
2638 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2639 +{
2640 + int retval;
2641 +
2642 + /*
2643 + * Allocate eeprom data.
2644 + */
2645 + retval = rt2800pci_validate_eeprom(rt2x00dev);
2646 + if (retval)
2647 + return retval;
2648 +
2649 + retval = rt2800pci_init_eeprom(rt2x00dev);
2650 + if (retval)
2651 + return retval;
2652 +
2653 + /*
2654 + * Initialize hw specifications.
2655 + */
2656 + retval = rt2800pci_probe_hw_mode(rt2x00dev);
2657 + if (retval)
2658 + return retval;
2659 +
2660 + /*
2661 + * This device requires firmware.
2662 + */
2663 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2664 + if (!modparam_nohwcrypt)
2665 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2666 +
2667 + /*
2668 + * Set the rssi offset.
2669 + */
2670 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2671 +
2672 + return 0;
2673 +}
2674 +
2675 +/*
2676 + * IEEE80211 stack callback functions.
2677 + */
2678 +static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2679 + u32 *iv32, u16 *iv16)
2680 +{
2681 + struct rt2x00_dev *rt2x00dev = hw->priv;
2682 + struct mac_iveiv_entry iveiv_entry;
2683 + u32 offset;
2684 +
2685 + offset = MAC_IVEIV_ENTRY(hw_key_idx);
2686 + rt2x00pci_register_multiread(rt2x00dev, offset,
2687 + &iveiv_entry, sizeof(iveiv_entry));
2688 +
2689 + memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2690 + memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2691 +}
2692 +
2693 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2694 +{
2695 + struct rt2x00_dev *rt2x00dev = hw->priv;
2696 + u32 reg;
2697 + bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2698 +
2699 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2700 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2701 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2702 +
2703 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2704 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2705 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2706 +
2707 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2708 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2709 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2710 +
2711 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2712 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2713 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2714 +
2715 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2716 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2717 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2718 +
2719 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2720 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2721 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2722 +
2723 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2724 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2725 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2726 +
2727 + return 0;
2728 +}
2729 +
2730 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2731 + const struct ieee80211_tx_queue_params *params)
2732 +{
2733 + struct rt2x00_dev *rt2x00dev = hw->priv;
2734 + struct data_queue *queue;
2735 + struct rt2x00_field32 field;
2736 + int retval;
2737 + u32 reg;
2738 + u32 offset;
2739 +
2740 + /*
2741 + * First pass the configuration through rt2x00lib, that will
2742 + * update the queue settings and validate the input. After that
2743 + * we are free to update the registers based on the value
2744 + * in the queue parameter.
2745 + */
2746 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2747 + if (retval)
2748 + return retval;
2749 +
2750 + /*
2751 + * We only need to perform additional register initialization
2752 + * for WMM queues/
2753 + */
2754 + if (queue_idx >= 4)
2755 + return 0;
2756 +
2757 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2758 +
2759 + /* Update WMM TXOP register */
2760 + offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2761 + field.bit_offset = (queue_idx & 1) * 16;
2762 + field.bit_mask = 0xffff << field.bit_offset;
2763 +
2764 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
2765 + rt2x00_set_field32(&reg, field, queue->txop);
2766 + rt2x00pci_register_write(rt2x00dev, offset, reg);
2767 +
2768 + /* Update WMM registers */
2769 + field.bit_offset = queue_idx * 4;
2770 + field.bit_mask = 0xf << field.bit_offset;
2771 +
2772 + rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2773 + rt2x00_set_field32(&reg, field, queue->aifs);
2774 + rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2775 +
2776 + rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2777 + rt2x00_set_field32(&reg, field, queue->cw_min);
2778 + rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2779 +
2780 + rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2781 + rt2x00_set_field32(&reg, field, queue->cw_max);
2782 + rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2783 +
2784 + /* Update EDCA registers */
2785 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2786 +
2787 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
2788 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2789 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2790 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2791 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2792 + rt2x00pci_register_write(rt2x00dev, offset, reg);
2793 +
2794 + return 0;
2795 +}
2796 +
2797 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
2798 +{
2799 + struct rt2x00_dev *rt2x00dev = hw->priv;
2800 + u64 tsf;
2801 + u32 reg;
2802 +
2803 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2804 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2805 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2806 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2807 +
2808 + return tsf;
2809 +}
2810 +
2811 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
2812 + .tx = rt2x00mac_tx,
2813 + .start = rt2x00mac_start,
2814 + .stop = rt2x00mac_stop,
2815 + .add_interface = rt2x00mac_add_interface,
2816 + .remove_interface = rt2x00mac_remove_interface,
2817 + .config = rt2x00mac_config,
2818 + .config_interface = rt2x00mac_config_interface,
2819 + .configure_filter = rt2x00mac_configure_filter,
2820 + .set_key = rt2x00mac_set_key,
2821 + .get_stats = rt2x00mac_get_stats,
2822 + .get_tkip_seq = rt2800pci_get_tkip_seq,
2823 + .set_rts_threshold = rt2800pci_set_rts_threshold,
2824 + .bss_info_changed = rt2x00mac_bss_info_changed,
2825 + .conf_tx = rt2800pci_conf_tx,
2826 + .get_tx_stats = rt2x00mac_get_tx_stats,
2827 + .get_tsf = rt2800pci_get_tsf,
2828 +};
2829 +
2830 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
2831 + .irq_handler = rt2800pci_interrupt,
2832 + .probe_hw = rt2800pci_probe_hw,
2833 + .get_firmware_name = rt2800pci_get_firmware_name,
2834 + .check_firmware = rt2800pci_check_firmware,
2835 + .load_firmware = rt2800pci_load_firmware,
2836 + .initialize = rt2x00pci_initialize,
2837 + .uninitialize = rt2x00pci_uninitialize,
2838 + .get_entry_state = rt2800pci_get_entry_state,
2839 + .clear_entry = rt2800pci_clear_entry,
2840 + .set_device_state = rt2800pci_set_device_state,
2841 + .rfkill_poll = rt2800pci_rfkill_poll,
2842 + .link_stats = rt2800pci_link_stats,
2843 + .reset_tuner = rt2800pci_reset_tuner,
2844 + .link_tuner = rt2800pci_link_tuner,
2845 + .write_tx_desc = rt2800pci_write_tx_desc,
2846 + .write_tx_data = rt2x00pci_write_tx_data,
2847 + .write_beacon = rt2800pci_write_beacon,
2848 + .kick_tx_queue = rt2800pci_kick_tx_queue,
2849 + .kill_tx_queue = rt2800pci_kill_tx_queue,
2850 + .fill_rxdone = rt2800pci_fill_rxdone,
2851 + .config_shared_key = rt2800pci_config_shared_key,
2852 + .config_pairwise_key = rt2800pci_config_pairwise_key,
2853 + .config_filter = rt2800pci_config_filter,
2854 + .config_intf = rt2800pci_config_intf,
2855 + .config_erp = rt2800pci_config_erp,
2856 + .config_ant = rt2800pci_config_ant,
2857 + .config = rt2800pci_config,
2858 +};
2859 +
2860 +static const struct data_queue_desc rt2800pci_queue_rx = {
2861 + .entry_num = RX_ENTRIES,
2862 + .data_size = AGGREGATION_SIZE,
2863 + .desc_size = RXD_DESC_SIZE,
2864 + .priv_size = sizeof(struct queue_entry_priv_pci),
2865 +};
2866 +
2867 +static const struct data_queue_desc rt2800pci_queue_tx = {
2868 + .entry_num = TX_ENTRIES,
2869 + .data_size = AGGREGATION_SIZE,
2870 + .desc_size = TXD_DESC_SIZE,
2871 + .priv_size = sizeof(struct queue_entry_priv_pci),
2872 +};
2873 +
2874 +static const struct data_queue_desc rt2800pci_queue_bcn = {
2875 + .entry_num = 8 * BEACON_ENTRIES,
2876 + .data_size = 0, /* No DMA required for beacons */
2877 + .desc_size = TXWI_DESC_SIZE,
2878 + .priv_size = sizeof(struct queue_entry_priv_pci),
2879 +};
2880 +
2881 +static const struct rt2x00_ops rt2800pci_ops = {
2882 + .name = KBUILD_MODNAME,
2883 + .max_sta_intf = 1,
2884 + .max_ap_intf = 8,
2885 + .eeprom_size = EEPROM_SIZE,
2886 + .rf_size = RF_SIZE,
2887 + .tx_queues = NUM_TX_QUEUES,
2888 + .rx = &rt2800pci_queue_rx,
2889 + .tx = &rt2800pci_queue_tx,
2890 + .bcn = &rt2800pci_queue_bcn,
2891 + .lib = &rt2800pci_rt2x00_ops,
2892 + .hw = &rt2800pci_mac80211_ops,
2893 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2894 + .debugfs = &rt2800pci_rt2x00debug,
2895 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2896 +};
2897 +
2898 +/*
2899 + * RT2800pci module information.
2900 + */
2901 +#ifdef CONFIG_RT2800PCI_PCI
2902 +static struct pci_device_id rt2800pci_device_table[] = {
2903 + { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
2904 + { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
2905 + { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
2906 + { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
2907 + { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
2908 + { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
2909 + { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
2910 + { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
2911 + { 0, }
2912 +};
2913 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
2914 +#endif /* CONFIG_RT2800PCI_PCI */
2915 +
2916 +MODULE_AUTHOR(DRV_PROJECT);
2917 +MODULE_VERSION(DRV_VERSION);
2918 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
2919 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
2920 +MODULE_FIRMWARE(FIRMWARE_RT2860);
2921 +MODULE_LICENSE("GPL");
2922 +
2923 +#ifdef CONFIG_RT2800PCI_WISOC
2924 +
2925 +#ifdef CONFIG_RALINK_RT288X
2926 +#define WSOC_RT_CHIPSET RT2880
2927 +#endif /* CONFIG_RALINK_RT288X */
2928 +
2929 +#ifdef CONFIG_RALINK_RT305X
2930 +#define WSOC_RT_CHIPSET RT3052
2931 +#endif /* CONFIG_RALINK_RT305X */
2932 +
2933 +static void rt2800soc_free_reg(struct rt2x00_dev *rt2x00dev)
2934 +{
2935 + kfree(rt2x00dev->rf);
2936 + rt2x00dev->rf = NULL;
2937 +
2938 + kfree(rt2x00dev->eeprom);
2939 + rt2x00dev->eeprom = NULL;
2940 +}
2941 +
2942 +static int rt2800soc_alloc_reg(struct rt2x00_dev *rt2x00dev)
2943 +{
2944 + struct platform_device *pdev = to_platform_device(rt2x00dev->dev);
2945 + struct resource *res;
2946 +
2947 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2948 + if (!res) {
2949 + ERROR_PROBE("Failed to get MMIO resource\n");
2950 + return -ENODEV;
2951 + }
2952 +
2953 + rt2x00dev->csr.base = (void __iomem *) KSEG1ADDR(res->start);
2954 + rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
2955 + if (!rt2x00dev->eeprom)
2956 + goto exit;
2957 +
2958 + rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
2959 + if (!rt2x00dev->rf)
2960 + goto exit;
2961 +
2962 + return 0;
2963 +
2964 +exit:
2965 + ERROR_PROBE("Failed to allocate registers.\n");
2966 + rt2800soc_free_reg(rt2x00dev);
2967 +
2968 + return -ENOMEM;
2969 +}
2970 +
2971 +static int rt2800soc_probe(struct platform_device *pdev)
2972 +{
2973 + const struct rt2x00_ops *ops = &rt2800pci_ops;
2974 + struct ieee80211_hw *hw;
2975 + struct rt2x00_dev *rt2x00dev;
2976 + int retval;
2977 +
2978 + hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
2979 + if (!hw) {
2980 + ERROR_PROBE("Failed to allocate hardware.\n");
2981 + return -ENOMEM;
2982 + }
2983 +
2984 + platform_set_drvdata(pdev, hw);
2985 +
2986 + rt2x00dev = hw->priv;
2987 + rt2x00dev->dev = &pdev->dev;
2988 + rt2x00dev->ops = ops;
2989 + rt2x00dev->hw = hw;
2990 + rt2x00dev->irq = platform_get_irq(pdev, 0);
2991 + rt2x00dev->name = pdev->dev.driver->name;
2992 +
2993 + rt2x00_set_chip_rt(rt2x00dev, WSOC_RT_CHIPSET);
2994 +
2995 + retval = rt2800soc_alloc_reg(rt2x00dev);
2996 + if (retval)
2997 + goto exit_free_device;
2998 +
2999 + retval = rt2x00lib_probe_dev(rt2x00dev);
3000 + if (retval)
3001 + goto exit_free_reg;
3002 +
3003 + return 0;
3004 +
3005 +exit_free_reg:
3006 + rt2800soc_free_reg(rt2x00dev);
3007 +
3008 +exit_free_device:
3009 + ieee80211_free_hw(hw);
3010 +
3011 + return retval;
3012 +}
3013 +
3014 +static int rt2800soc_remove(struct platform_device *pdev)
3015 +{
3016 + struct ieee80211_hw *hw = platform_get_drvdata(pdev);
3017 + struct rt2x00_dev *rt2x00dev = hw->priv;
3018 +
3019 + /*
3020 + * Free all allocated data.
3021 + */
3022 + rt2x00lib_remove_dev(rt2x00dev);
3023 + rt2800soc_free_reg(rt2x00dev);
3024 + ieee80211_free_hw(hw);
3025 +
3026 + return 0;
3027 +}
3028 +
3029 +static struct platform_driver rt2800soc_driver = {
3030 + .driver.name = "rt2800_wmac",
3031 + .probe = rt2800soc_probe,
3032 + .remove = rt2800soc_remove,
3033 +};
3034 +#endif /* CONFIG_RT2800PCI_WISOC */
3035 +
3036 +#ifdef CONFIG_RT2800PCI_PCI
3037 +static struct pci_driver rt2800pci_driver = {
3038 + .name = KBUILD_MODNAME,
3039 + .id_table = rt2800pci_device_table,
3040 + .probe = rt2x00pci_probe,
3041 + .remove = __devexit_p(rt2x00pci_remove),
3042 + .suspend = rt2x00pci_suspend,
3043 + .resume = rt2x00pci_resume,
3044 +};
3045 +#endif /* CONFIG_RT2800PCI_PCI */
3046 +
3047 +static int __init rt2800pci_init(void)
3048 +{
3049 + int ret = 0;
3050 +
3051 +#ifdef CONFIG_RT2800PCI_WISOC
3052 + ret = platform_driver_register(&rt2800soc_driver);
3053 +#endif
3054 +#ifdef CONFIG_RT2800PCI_PCI
3055 + ret = pci_register_driver(&rt2800pci_driver);
3056 +#endif
3057 + return ret;
3058 +}
3059 +
3060 +static void __exit rt2800pci_exit(void)
3061 +{
3062 +#ifdef CONFIG_RT2800PCI_PCI
3063 + pci_unregister_driver(&rt2800pci_driver);
3064 +#endif
3065 +#ifdef CONFIG_RT2800PCI_WISOC
3066 + platform_driver_unregister(&rt2800soc_driver);
3067 +#endif
3068 +}
3069 +
3070 +module_init(rt2800pci_init);
3071 +module_exit(rt2800pci_exit);
3072 --- /dev/null
3073 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
3074 @@ -0,0 +1,1880 @@
3075 +/*
3076 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3077 + <http://rt2x00.serialmonkey.com>
3078 +
3079 + This program is free software; you can redistribute it and/or modify
3080 + it under the terms of the GNU General Public License as published by
3081 + the Free Software Foundation; either version 2 of the License, or
3082 + (at your option) any later version.
3083 +
3084 + This program is distributed in the hope that it will be useful,
3085 + but WITHOUT ANY WARRANTY; without even the implied warranty of
3086 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3087 + GNU General Public License for more details.
3088 +
3089 + You should have received a copy of the GNU General Public License
3090 + along with this program; if not, write to the
3091 + Free Software Foundation, Inc.,
3092 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
3093 + */
3094 +
3095 +/*
3096 + Module: rt2800pci
3097 + Abstract: Data structures and registers for the rt2800pci module.
3098 + Supported chipsets: RT2800E & RT2800ED.
3099 + */
3100 +
3101 +#ifndef RT2800PCI_H
3102 +#define RT2800PCI_H
3103 +
3104 +/*
3105 + * RF chip defines.
3106 + *
3107 + * RF2820 2.4G 2T3R
3108 + * RF2850 2.4G/5G 2T3R
3109 + * RF2720 2.4G 1T2R
3110 + * RF2750 2.4G/5G 1T2R
3111 + * RF3020 2.4G 1T1R
3112 + * RF2020 2.4G B/G
3113 + * RF3052 2.4G 2T2R
3114 + */
3115 +#define RF2820 0x0001
3116 +#define RF2850 0x0002
3117 +#define RF2720 0x0003
3118 +#define RF2750 0x0004
3119 +#define RF3020 0x0005
3120 +#define RF2020 0x0006
3121 +#define RF3052 0x0008
3122 +
3123 +/*
3124 + * RT2860 version
3125 + */
3126 +#define RT2860C_VERSION 0x28600100
3127 +#define RT2860D_VERSION 0x28600101
3128 +#define RT2880E_VERSION 0x28720200
3129 +#define RT2883_VERSION 0x28830300
3130 +#define RT3070_VERSION 0x30700200
3131 +
3132 +/*
3133 + * Signal information.
3134 + * Defaul offset is required for RSSI <-> dBm conversion.
3135 + */
3136 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
3137 +
3138 +/*
3139 + * Register layout information.
3140 + */
3141 +#define CSR_REG_BASE 0x1000
3142 +#define CSR_REG_SIZE 0x0800
3143 +#define EEPROM_BASE 0x0000
3144 +#define EEPROM_SIZE 0x0110
3145 +#define BBP_BASE 0x0000
3146 +#define BBP_SIZE 0x0080
3147 +#define RF_BASE 0x0004
3148 +#define RF_SIZE 0x0010
3149 +
3150 +/*
3151 + * Number of TX queues.
3152 + */
3153 +#define NUM_TX_QUEUES 4
3154 +
3155 +/*
3156 + * PCI registers.
3157 + */
3158 +
3159 +/*
3160 + * PCI Configuration Header
3161 + */
3162 +#define PCI_CONFIG_HEADER_VENDOR 0x0000
3163 +#define PCI_CONFIG_HEADER_DEVICE 0x0002
3164 +
3165 +/*
3166 + * E2PROM_CSR: EEPROM control register.
3167 + * RELOAD: Write 1 to reload eeprom content.
3168 + * TYPE: 0: 93c46, 1:93c66.
3169 + * LOAD_STATUS: 1:loading, 0:done.
3170 + */
3171 +#define E2PROM_CSR 0x0004
3172 +#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
3173 +#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
3174 +#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
3175 +#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
3176 +#define E2PROM_CSR_TYPE FIELD32(0x00000030)
3177 +#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
3178 +#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
3179 +
3180 +/*
3181 + * HOST-MCU shared memory
3182 + */
3183 +#define HOST_CMD_CSR 0x0404
3184 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
3185 +
3186 +/*
3187 + * INT_SOURCE_CSR: Interrupt source register.
3188 + * Write one to clear corresponding bit.
3189 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
3190 + */
3191 +#define INT_SOURCE_CSR 0x0200
3192 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
3193 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
3194 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
3195 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
3196 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
3197 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
3198 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
3199 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
3200 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
3201 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
3202 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
3203 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
3204 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
3205 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
3206 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
3207 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
3208 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
3209 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
3210 +
3211 +/*
3212 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
3213 + */
3214 +#define INT_MASK_CSR 0x0204
3215 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
3216 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
3217 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
3218 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
3219 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
3220 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
3221 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
3222 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
3223 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
3224 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
3225 +#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
3226 +#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
3227 +#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
3228 +#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
3229 +#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
3230 +#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
3231 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
3232 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
3233 +
3234 +/*
3235 + * WPDMA_GLO_CFG
3236 + */
3237 +#define WPDMA_GLO_CFG 0x0208
3238 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
3239 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
3240 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
3241 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
3242 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
3243 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
3244 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
3245 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
3246 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
3247 +
3248 +/*
3249 + * WPDMA_RST_IDX
3250 + */
3251 +#define WPDMA_RST_IDX 0x020c
3252 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
3253 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
3254 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
3255 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
3256 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
3257 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
3258 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
3259 +
3260 +/*
3261 + * DELAY_INT_CFG
3262 + */
3263 +#define DELAY_INT_CFG 0x0210
3264 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
3265 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
3266 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
3267 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
3268 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
3269 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
3270 +
3271 +/*
3272 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
3273 + * AIFSN0: AC_BE
3274 + * AIFSN1: AC_BK
3275 + * AIFSN1: AC_VI
3276 + * AIFSN1: AC_VO
3277 + */
3278 +#define WMM_AIFSN_CFG 0x0214
3279 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
3280 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
3281 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
3282 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
3283 +
3284 +/*
3285 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3286 + * CWMIN0: AC_BE
3287 + * CWMIN1: AC_BK
3288 + * CWMIN1: AC_VI
3289 + * CWMIN1: AC_VO
3290 + */
3291 +#define WMM_CWMIN_CFG 0x0218
3292 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
3293 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
3294 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
3295 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
3296 +
3297 +/*
3298 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3299 + * CWMAX0: AC_BE
3300 + * CWMAX1: AC_BK
3301 + * CWMAX1: AC_VI
3302 + * CWMAX1: AC_VO
3303 + */
3304 +#define WMM_CWMAX_CFG 0x021c
3305 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
3306 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
3307 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
3308 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
3309 +
3310 +/*
3311 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3312 + * AC0TXOP: AC_BK in unit of 32us
3313 + * AC1TXOP: AC_BE in unit of 32us
3314 + */
3315 +#define WMM_TXOP0_CFG 0x0220
3316 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
3317 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
3318 +
3319 +/*
3320 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3321 + * AC2TXOP: AC_VI in unit of 32us
3322 + * AC3TXOP: AC_VO in unit of 32us
3323 + */
3324 +#define WMM_TXOP1_CFG 0x0224
3325 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
3326 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
3327 +
3328 +/*
3329 + * GPIO_CTRL_CFG:
3330 + */
3331 +#define GPIO_CTRL_CFG 0x0228
3332 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
3333 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
3334 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
3335 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
3336 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
3337 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
3338 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
3339 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
3340 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
3341 +
3342 +/*
3343 + * MCU_CMD_CFG
3344 + */
3345 +#define MCU_CMD_CFG 0x022c
3346 +
3347 +/*
3348 + * AC_BK register offsets
3349 + */
3350 +#define TX_BASE_PTR0 0x0230
3351 +#define TX_MAX_CNT0 0x0234
3352 +#define TX_CTX_IDX0 0x0238
3353 +#define TX_DTX_IDX0 0x023c
3354 +
3355 +/*
3356 + * AC_BE register offsets
3357 + */
3358 +#define TX_BASE_PTR1 0x0240
3359 +#define TX_MAX_CNT1 0x0244
3360 +#define TX_CTX_IDX1 0x0248
3361 +#define TX_DTX_IDX1 0x024c
3362 +
3363 +/*
3364 + * AC_VI register offsets
3365 + */
3366 +#define TX_BASE_PTR2 0x0250
3367 +#define TX_MAX_CNT2 0x0254
3368 +#define TX_CTX_IDX2 0x0258
3369 +#define TX_DTX_IDX2 0x025c
3370 +
3371 +/*
3372 + * AC_VO register offsets
3373 + */
3374 +#define TX_BASE_PTR3 0x0260
3375 +#define TX_MAX_CNT3 0x0264
3376 +#define TX_CTX_IDX3 0x0268
3377 +#define TX_DTX_IDX3 0x026c
3378 +
3379 +/*
3380 + * HCCA register offsets
3381 + */
3382 +#define TX_BASE_PTR4 0x0270
3383 +#define TX_MAX_CNT4 0x0274
3384 +#define TX_CTX_IDX4 0x0278
3385 +#define TX_DTX_IDX4 0x027c
3386 +
3387 +/*
3388 + * MGMT register offsets
3389 + */
3390 +#define TX_BASE_PTR5 0x0280
3391 +#define TX_MAX_CNT5 0x0284
3392 +#define TX_CTX_IDX5 0x0288
3393 +#define TX_DTX_IDX5 0x028c
3394 +
3395 +/*
3396 + * Queue register offset macros
3397 + */
3398 +#define TX_QUEUE_REG_OFFSET 0x10
3399 +#define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
3400 +#define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
3401 +#define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3402 +#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3403 +
3404 +/*
3405 + * RX register offsets
3406 + */
3407 +#define RX_BASE_PTR 0x0290
3408 +#define RX_MAX_CNT 0x0294
3409 +#define RX_CRX_IDX 0x0298
3410 +#define RX_DRX_IDX 0x029c
3411 +
3412 +/*
3413 + * PBF_SYS_CTRL
3414 + * HOST_RAM_WRITE: enable Host program ram write selection
3415 + */
3416 +#define PBF_SYS_CTRL 0x0400
3417 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
3418 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
3419 +
3420 +/*
3421 + * PBF registers
3422 + * Most are for debug. Driver doesn't touch PBF register.
3423 + */
3424 +#define PBF_CFG 0x0408
3425 +#define PBF_MAX_PCNT 0x040c
3426 +#define PBF_CTRL 0x0410
3427 +#define PBF_INT_STA 0x0414
3428 +#define PBF_INT_ENA 0x0418
3429 +
3430 +/*
3431 + * BCN_OFFSET0:
3432 + */
3433 +#define BCN_OFFSET0 0x042c
3434 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
3435 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
3436 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
3437 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
3438 +
3439 +/*
3440 + * BCN_OFFSET1:
3441 + */
3442 +#define BCN_OFFSET1 0x0430
3443 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
3444 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
3445 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
3446 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
3447 +
3448 +/*
3449 + * PBF registers
3450 + * Most are for debug. Driver doesn't touch PBF register.
3451 + */
3452 +#define TXRXQ_PCNT 0x0438
3453 +#define PBF_DBG 0x043c
3454 +
3455 +/*
3456 + * MAC Control/Status Registers(CSR).
3457 + * Some values are set in TU, whereas 1 TU == 1024 us.
3458 + */
3459 +
3460 +/*
3461 + * MAC_CSR0: ASIC revision number.
3462 + * ASIC_REV: 0
3463 + * ASIC_VER: 2860
3464 + */
3465 +#define MAC_CSR0 0x1000
3466 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
3467 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
3468 +
3469 +/*
3470 + * MAC_SYS_CTRL:
3471 + */
3472 +#define MAC_SYS_CTRL 0x1004
3473 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
3474 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
3475 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
3476 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
3477 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
3478 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
3479 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
3480 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
3481 +
3482 +/*
3483 + * MAC_ADDR_DW0: STA MAC register 0
3484 + */
3485 +#define MAC_ADDR_DW0 0x1008
3486 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
3487 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
3488 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
3489 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
3490 +
3491 +/*
3492 + * MAC_ADDR_DW1: STA MAC register 1
3493 + * UNICAST_TO_ME_MASK:
3494 + * Used to mask off bits from byte 5 of the MAC address
3495 + * to determine the UNICAST_TO_ME bit for RX frames.
3496 + * The full mask is complemented by BSS_ID_MASK:
3497 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3498 + */
3499 +#define MAC_ADDR_DW1 0x100c
3500 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3501 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3502 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3503 +
3504 +/*
3505 + * MAC_BSSID_DW0: BSSID register 0
3506 + */
3507 +#define MAC_BSSID_DW0 0x1010
3508 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3509 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3510 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3511 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3512 +
3513 +/*
3514 + * MAC_BSSID_DW1: BSSID register 1
3515 + * BSS_ID_MASK:
3516 + * 0: 1-BSSID mode (BSS index = 0)
3517 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3518 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3519 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3520 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3521 + * BSSID. This will make sure that those bits will be ignored
3522 + * when determining the MY_BSS of RX frames.
3523 + */
3524 +#define MAC_BSSID_DW1 0x1014
3525 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3526 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3527 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3528 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3529 +
3530 +/*
3531 + * MAX_LEN_CFG: Maximum frame length register.
3532 + * MAX_MPDU: rt2860b max 16k bytes
3533 + * MAX_PSDU: Maximum PSDU length
3534 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3535 + */
3536 +#define MAX_LEN_CFG 0x1018
3537 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3538 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3539 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3540 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3541 +
3542 +/*
3543 + * BBP_CSR_CFG: BBP serial control register
3544 + * VALUE: Register value to program into BBP
3545 + * REG_NUM: Selected BBP register
3546 + * READ_CONTROL: 0 write BBP, 1 read BBP
3547 + * BUSY: ASIC is busy executing BBP commands
3548 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3549 + * BBP_RW_MODE: 0 serial, 1 paralell
3550 + */
3551 +#define BBP_CSR_CFG 0x101c
3552 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3553 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3554 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3555 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3556 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3557 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3558 +
3559 +/*
3560 + * RF_CSR_CFG0: RF control register
3561 + * REGID_AND_VALUE: Register value to program into RF
3562 + * BITWIDTH: Selected RF register
3563 + * STANDBYMODE: 0 high when standby, 1 low when standby
3564 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3565 + * BUSY: ASIC is busy executing RF commands
3566 + */
3567 +#define RF_CSR_CFG0 0x1020
3568 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3569 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3570 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3571 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3572 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3573 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3574 +
3575 +/*
3576 + * RF_CSR_CFG1: RF control register
3577 + * REGID_AND_VALUE: Register value to program into RF
3578 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3579 + * 0: 3 system clock cycle (37.5usec)
3580 + * 1: 5 system clock cycle (62.5usec)
3581 + */
3582 +#define RF_CSR_CFG1 0x1024
3583 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3584 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3585 +
3586 +/*
3587 + * RF_CSR_CFG2: RF control register
3588 + * VALUE: Register value to program into RF
3589 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3590 + * 0: 3 system clock cycle (37.5usec)
3591 + * 1: 5 system clock cycle (62.5usec)
3592 + */
3593 +#define RF_CSR_CFG2 0x1028
3594 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3595 +
3596 +/*
3597 + * LED_CFG: LED control
3598 + * color LED's:
3599 + * 0: off
3600 + * 1: blinking upon TX2
3601 + * 2: periodic slow blinking
3602 + * 3: always on
3603 + * LED polarity:
3604 + * 0: active low
3605 + * 1: active high
3606 + */
3607 +#define LED_CFG 0x102c
3608 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3609 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3610 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3611 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3612 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3613 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3614 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3615 +
3616 +/*
3617 + * XIFS_TIME_CFG: MAC timing
3618 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3619 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3620 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3621 + * when MAC doesn't reference BBP signal BBRXEND
3622 + * EIFS: unit 1us
3623 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3624 + *
3625 + */
3626 +#define XIFS_TIME_CFG 0x1100
3627 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3628 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3629 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3630 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3631 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3632 +
3633 +/*
3634 + * BKOFF_SLOT_CFG:
3635 + */
3636 +#define BKOFF_SLOT_CFG 0x1104
3637 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3638 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3639 +
3640 +/*
3641 + * NAV_TIME_CFG:
3642 + */
3643 +#define NAV_TIME_CFG 0x1108
3644 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3645 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3646 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3647 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3648 +
3649 +/*
3650 + * CH_TIME_CFG: count as channel busy
3651 + */
3652 +#define CH_TIME_CFG 0x110c
3653 +
3654 +/*
3655 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3656 + */
3657 +#define PBF_LIFE_TIMER 0x1110
3658 +
3659 +/*
3660 + * BCN_TIME_CFG:
3661 + * BEACON_INTERVAL: in unit of 1/16 TU
3662 + * TSF_TICKING: Enable TSF auto counting
3663 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3664 + * BEACON_GEN: Enable beacon generator
3665 + */
3666 +#define BCN_TIME_CFG 0x1114
3667 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3668 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3669 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3670 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3671 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3672 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3673 +
3674 +/*
3675 + * TBTT_SYNC_CFG:
3676 + */
3677 +#define TBTT_SYNC_CFG 0x1118
3678 +
3679 +/*
3680 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3681 + */
3682 +#define TSF_TIMER_DW0 0x111c
3683 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3684 +
3685 +/*
3686 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3687 + */
3688 +#define TSF_TIMER_DW1 0x1120
3689 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3690 +
3691 +/*
3692 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3693 + */
3694 +#define TBTT_TIMER 0x1124
3695 +
3696 +/*
3697 + * INT_TIMER_CFG:
3698 + */
3699 +#define INT_TIMER_CFG 0x1128
3700 +
3701 +/*
3702 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3703 + */
3704 +#define INT_TIMER_EN 0x112c
3705 +
3706 +/*
3707 + * CH_IDLE_STA: channel idle time
3708 + */
3709 +#define CH_IDLE_STA 0x1130
3710 +
3711 +/*
3712 + * CH_BUSY_STA: channel busy time
3713 + */
3714 +#define CH_BUSY_STA 0x1134
3715 +
3716 +/*
3717 + * MAC_STATUS_CFG:
3718 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3719 + * if 1 or higher one of the 2 registers is busy.
3720 + */
3721 +#define MAC_STATUS_CFG 0x1200
3722 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3723 +
3724 +/*
3725 + * PWR_PIN_CFG:
3726 + */
3727 +#define PWR_PIN_CFG 0x1204
3728 +
3729 +/*
3730 + * AUTOWAKEUP_CFG: Manual power control / status register
3731 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3732 + * AUTOWAKE: 0:sleep, 1:awake
3733 + */
3734 +#define AUTOWAKEUP_CFG 0x1208
3735 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3736 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3737 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3738 +
3739 +/*
3740 + * EDCA_AC0_CFG:
3741 + */
3742 +#define EDCA_AC0_CFG 0x1300
3743 +#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
3744 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3745 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3746 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3747 +
3748 +/*
3749 + * EDCA_AC1_CFG:
3750 + */
3751 +#define EDCA_AC1_CFG 0x1304
3752 +#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
3753 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3754 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3755 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3756 +
3757 +/*
3758 + * EDCA_AC2_CFG:
3759 + */
3760 +#define EDCA_AC2_CFG 0x1308
3761 +#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
3762 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3763 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3764 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3765 +
3766 +/*
3767 + * EDCA_AC3_CFG:
3768 + */
3769 +#define EDCA_AC3_CFG 0x130c
3770 +#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
3771 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3772 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3773 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3774 +
3775 +/*
3776 + * EDCA_TID_AC_MAP:
3777 + */
3778 +#define EDCA_TID_AC_MAP 0x1310
3779 +
3780 +/*
3781 + * TX_PWR_CFG_0:
3782 + */
3783 +#define TX_PWR_CFG_0 0x1314
3784 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3785 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
3786 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
3787 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
3788 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
3789 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
3790 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
3791 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
3792 +
3793 +/*
3794 + * TX_PWR_CFG_1:
3795 + */
3796 +#define TX_PWR_CFG_1 0x1318
3797 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
3798 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
3799 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
3800 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
3801 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
3802 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
3803 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
3804 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
3805 +
3806 +/*
3807 + * TX_PWR_CFG_2:
3808 + */
3809 +#define TX_PWR_CFG_2 0x131c
3810 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
3811 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
3812 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
3813 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
3814 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
3815 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
3816 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
3817 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
3818 +
3819 +/*
3820 + * TX_PWR_CFG_3:
3821 + */
3822 +#define TX_PWR_CFG_3 0x1320
3823 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
3824 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
3825 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
3826 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
3827 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
3828 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
3829 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
3830 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
3831 +
3832 +/*
3833 + * TX_PWR_CFG_4:
3834 + */
3835 +#define TX_PWR_CFG_4 0x1324
3836 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
3837 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
3838 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
3839 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
3840 +
3841 +/*
3842 + * TX_PIN_CFG:
3843 + */
3844 +#define TX_PIN_CFG 0x1328
3845 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
3846 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
3847 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
3848 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
3849 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
3850 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
3851 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
3852 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
3853 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
3854 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
3855 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
3856 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
3857 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
3858 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
3859 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
3860 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
3861 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
3862 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
3863 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
3864 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
3865 +
3866 +/*
3867 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3868 + */
3869 +#define TX_BAND_CFG 0x132c
3870 +#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
3871 +#define TX_BAND_CFG_A FIELD32(0x00000002)
3872 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
3873 +
3874 +/*
3875 + * TX_SW_CFG0:
3876 + */
3877 +#define TX_SW_CFG0 0x1330
3878 +
3879 +/*
3880 + * TX_SW_CFG1:
3881 + */
3882 +#define TX_SW_CFG1 0x1334
3883 +
3884 +/*
3885 + * TX_SW_CFG2:
3886 + */
3887 +#define TX_SW_CFG2 0x1338
3888 +
3889 +/*
3890 + * TXOP_THRES_CFG:
3891 + */
3892 +#define TXOP_THRES_CFG 0x133c
3893 +
3894 +/*
3895 + * TXOP_CTRL_CFG:
3896 + */
3897 +#define TXOP_CTRL_CFG 0x1340
3898 +
3899 +/*
3900 + * TX_RTS_CFG:
3901 + * RTS_THRES: unit:byte
3902 + * RTS_FBK_EN: enable rts rate fallback
3903 + */
3904 +#define TX_RTS_CFG 0x1344
3905 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
3906 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
3907 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
3908 +
3909 +/*
3910 + * TX_TIMEOUT_CFG:
3911 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3912 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3913 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3914 + * it is recommended that:
3915 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3916 + */
3917 +#define TX_TIMEOUT_CFG 0x1348
3918 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
3919 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
3920 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
3921 +
3922 +/*
3923 + * TX_RTY_CFG:
3924 + * SHORT_RTY_LIMIT: short retry limit
3925 + * LONG_RTY_LIMIT: long retry limit
3926 + * LONG_RTY_THRE: Long retry threshoold
3927 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3928 + * 0:expired by retry limit, 1: expired by mpdu life timer
3929 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3930 + * 0:expired by retry limit, 1: expired by mpdu life timer
3931 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3932 + */
3933 +#define TX_RTY_CFG 0x134c
3934 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
3935 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
3936 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
3937 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
3938 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
3939 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
3940 +
3941 +/*
3942 + * TX_LINK_CFG:
3943 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3944 + * MFB_ENABLE: TX apply remote MFB 1:enable
3945 + * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
3946 + * 0: not apply remote remote unsolicit (MFS=7)
3947 + * TX_MRQ_EN: MCS request TX enable
3948 + * TX_RDG_EN: RDG TX enable
3949 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3950 + * REMOTE_MFB: remote MCS feedback
3951 + * REMOTE_MFS: remote MCS feedback sequence number
3952 + */
3953 +#define TX_LINK_CFG 0x1350
3954 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
3955 +#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
3956 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3957 +#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
3958 +#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
3959 +#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
3960 +#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
3961 +#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
3962 +
3963 +/*
3964 + * HT_FBK_CFG0:
3965 + */
3966 +#define HT_FBK_CFG0 0x1354
3967 +#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
3968 +#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
3969 +#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
3970 +#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
3971 +#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
3972 +#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
3973 +#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
3974 +#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
3975 +
3976 +/*
3977 + * HT_FBK_CFG1:
3978 + */
3979 +#define HT_FBK_CFG1 0x1358
3980 +#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
3981 +#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
3982 +#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
3983 +#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
3984 +#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
3985 +#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
3986 +#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
3987 +#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
3988 +
3989 +/*
3990 + * LG_FBK_CFG0:
3991 + */
3992 +#define LG_FBK_CFG0 0x135c
3993 +#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
3994 +#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
3995 +#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
3996 +#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
3997 +#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
3998 +#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
3999 +#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
4000 +#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
4001 +
4002 +/*
4003 + * LG_FBK_CFG1:
4004 + */
4005 +#define LG_FBK_CFG1 0x1360
4006 +#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
4007 +#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
4008 +#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
4009 +#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
4010 +
4011 +/*
4012 + * CCK_PROT_CFG: CCK Protection
4013 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
4014 + * PROTECT_CTRL: Protection control frame type for CCK TX
4015 + * 0:none, 1:RTS/CTS, 2:CTS-to-self
4016 + * PROTECT_NAV: TXOP protection type for CCK TX
4017 + * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
4018 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
4019 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
4020 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
4021 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
4022 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
4023 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
4024 + * RTS_TH_EN: RTS threshold enable on CCK TX
4025 + */
4026 +#define CCK_PROT_CFG 0x1364
4027 +#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4028 +#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4029 +#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4030 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4031 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4032 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4033 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4034 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4035 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4036 +#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4037 +
4038 +/*
4039 + * OFDM_PROT_CFG: OFDM Protection
4040 + */
4041 +#define OFDM_PROT_CFG 0x1368
4042 +#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4043 +#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4044 +#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4045 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4046 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4047 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4048 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4049 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4050 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4051 +#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4052 +
4053 +/*
4054 + * MM20_PROT_CFG: MM20 Protection
4055 + */
4056 +#define MM20_PROT_CFG 0x136c
4057 +#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4058 +#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4059 +#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4060 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4061 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4062 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4063 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4064 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4065 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4066 +#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4067 +
4068 +/*
4069 + * MM40_PROT_CFG: MM40 Protection
4070 + */
4071 +#define MM40_PROT_CFG 0x1370
4072 +#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4073 +#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4074 +#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4075 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4076 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4077 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4078 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4079 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4080 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4081 +#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4082 +
4083 +/*
4084 + * GF20_PROT_CFG: GF20 Protection
4085 + */
4086 +#define GF20_PROT_CFG 0x1374
4087 +#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4088 +#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4089 +#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4090 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4091 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4092 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4093 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4094 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4095 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4096 +#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4097 +
4098 +/*
4099 + * GF40_PROT_CFG: GF40 Protection
4100 + */
4101 +#define GF40_PROT_CFG 0x1378
4102 +#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4103 +#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4104 +#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4105 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4106 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4107 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4108 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4109 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4110 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4111 +#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4112 +
4113 +/*
4114 + * EXP_CTS_TIME:
4115 + */
4116 +#define EXP_CTS_TIME 0x137c
4117 +
4118 +/*
4119 + * EXP_ACK_TIME:
4120 + */
4121 +#define EXP_ACK_TIME 0x1380
4122 +
4123 +/*
4124 + * RX_FILTER_CFG: RX configuration register.
4125 + */
4126 +#define RX_FILTER_CFG 0x1400
4127 +#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
4128 +#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
4129 +#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
4130 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
4131 +#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
4132 +#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
4133 +#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
4134 +#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
4135 +#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
4136 +#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
4137 +#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
4138 +#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
4139 +#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
4140 +#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
4141 +#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
4142 +#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
4143 +#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
4144 +
4145 +/*
4146 + * AUTO_RSP_CFG:
4147 + * AUTORESPONDER: 0: disable, 1: enable
4148 + * BAC_ACK_POLICY: 0:long, 1:short preamble
4149 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
4150 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
4151 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
4152 + * DUAL_CTS_EN: Power bit value in control frame
4153 + * ACK_CTS_PSM_BIT:Power bit value in control frame
4154 + */
4155 +#define AUTO_RSP_CFG 0x1404
4156 +#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
4157 +#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
4158 +#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
4159 +#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
4160 +#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
4161 +#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
4162 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
4163 +
4164 +/*
4165 + * LEGACY_BASIC_RATE:
4166 + */
4167 +#define LEGACY_BASIC_RATE 0x1408
4168 +
4169 +/*
4170 + * HT_BASIC_RATE:
4171 + */
4172 +#define HT_BASIC_RATE 0x140c
4173 +
4174 +/*
4175 + * HT_CTRL_CFG:
4176 + */
4177 +#define HT_CTRL_CFG 0x1410
4178 +
4179 +/*
4180 + * SIFS_COST_CFG:
4181 + */
4182 +#define SIFS_COST_CFG 0x1414
4183 +
4184 +/*
4185 + * RX_PARSER_CFG:
4186 + * Set NAV for all received frames
4187 + */
4188 +#define RX_PARSER_CFG 0x1418
4189 +
4190 +/*
4191 + * TX_SEC_CNT0:
4192 + */
4193 +#define TX_SEC_CNT0 0x1500
4194 +
4195 +/*
4196 + * RX_SEC_CNT0:
4197 + */
4198 +#define RX_SEC_CNT0 0x1504
4199 +
4200 +/*
4201 + * CCMP_FC_MUTE:
4202 + */
4203 +#define CCMP_FC_MUTE 0x1508
4204 +
4205 +/*
4206 + * TXOP_HLDR_ADDR0:
4207 + */
4208 +#define TXOP_HLDR_ADDR0 0x1600
4209 +
4210 +/*
4211 + * TXOP_HLDR_ADDR1:
4212 + */
4213 +#define TXOP_HLDR_ADDR1 0x1604
4214 +
4215 +/*
4216 + * TXOP_HLDR_ET:
4217 + */
4218 +#define TXOP_HLDR_ET 0x1608
4219 +
4220 +/*
4221 + * QOS_CFPOLL_RA_DW0:
4222 + */
4223 +#define QOS_CFPOLL_RA_DW0 0x160c
4224 +
4225 +/*
4226 + * QOS_CFPOLL_RA_DW1:
4227 + */
4228 +#define QOS_CFPOLL_RA_DW1 0x1610
4229 +
4230 +/*
4231 + * QOS_CFPOLL_QC:
4232 + */
4233 +#define QOS_CFPOLL_QC 0x1614
4234 +
4235 +/*
4236 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
4237 + */
4238 +#define RX_STA_CNT0 0x1700
4239 +#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
4240 +#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
4241 +
4242 +/*
4243 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
4244 + */
4245 +#define RX_STA_CNT1 0x1704
4246 +#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
4247 +#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
4248 +
4249 +/*
4250 + * RX_STA_CNT2:
4251 + */
4252 +#define RX_STA_CNT2 0x1708
4253 +#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
4254 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
4255 +
4256 +/*
4257 + * TX_STA_CNT0: TX Beacon count
4258 + */
4259 +#define TX_STA_CNT0 0x170c
4260 +#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
4261 +#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
4262 +
4263 +/*
4264 + * TX_STA_CNT1: TX tx count
4265 + */
4266 +#define TX_STA_CNT1 0x1710
4267 +#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
4268 +#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
4269 +
4270 +/*
4271 + * TX_STA_CNT2: TX tx count
4272 + */
4273 +#define TX_STA_CNT2 0x1714
4274 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
4275 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
4276 +
4277 +/*
4278 + * TX_STA_FIFO: TX Result for specific PID status fifo register
4279 + */
4280 +#define TX_STA_FIFO 0x1718
4281 +#define TX_STA_FIFO_VALID FIELD32(0x00000001)
4282 +#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
4283 +#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
4284 +#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
4285 +#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
4286 +#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
4287 +#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
4288 +
4289 +/*
4290 + * TX_AGG_CNT: Debug counter
4291 + */
4292 +#define TX_AGG_CNT 0x171c
4293 +#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
4294 +#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
4295 +
4296 +/*
4297 + * TX_AGG_CNT0:
4298 + */
4299 +#define TX_AGG_CNT0 0x1720
4300 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
4301 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
4302 +
4303 +/*
4304 + * TX_AGG_CNT1:
4305 + */
4306 +#define TX_AGG_CNT1 0x1724
4307 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
4308 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
4309 +
4310 +/*
4311 + * TX_AGG_CNT2:
4312 + */
4313 +#define TX_AGG_CNT2 0x1728
4314 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
4315 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
4316 +
4317 +/*
4318 + * TX_AGG_CNT3:
4319 + */
4320 +#define TX_AGG_CNT3 0x172c
4321 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
4322 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
4323 +
4324 +/*
4325 + * TX_AGG_CNT4:
4326 + */
4327 +#define TX_AGG_CNT4 0x1730
4328 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
4329 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
4330 +
4331 +/*
4332 + * TX_AGG_CNT5:
4333 + */
4334 +#define TX_AGG_CNT5 0x1734
4335 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
4336 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
4337 +
4338 +/*
4339 + * TX_AGG_CNT6:
4340 + */
4341 +#define TX_AGG_CNT6 0x1738
4342 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
4343 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
4344 +
4345 +/*
4346 + * TX_AGG_CNT7:
4347 + */
4348 +#define TX_AGG_CNT7 0x173c
4349 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
4350 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
4351 +
4352 +/*
4353 + * MPDU_DENSITY_CNT:
4354 + * TX_ZERO_DEL: TX zero length delimiter count
4355 + * RX_ZERO_DEL: RX zero length delimiter count
4356 + */
4357 +#define MPDU_DENSITY_CNT 0x1740
4358 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
4359 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
4360 +
4361 +/*
4362 + * Security key table memory.
4363 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4364 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4365 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4366 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4367 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4368 + * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
4369 + */
4370 +#define MAC_WCID_BASE 0x1800
4371 +#define PAIRWISE_KEY_TABLE_BASE 0x4000
4372 +#define MAC_IVEIV_TABLE_BASE 0x6000
4373 +#define MAC_WCID_ATTRIBUTE_BASE 0x6800
4374 +#define SHARED_KEY_TABLE_BASE 0x6c00
4375 +#define SHARED_KEY_MODE_BASE 0x7000
4376 +
4377 +#define MAC_WCID_ENTRY(__idx) \
4378 + ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
4379 +#define PAIRWISE_KEY_ENTRY(__idx) \
4380 + ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4381 +#define MAC_IVEIV_ENTRY(__idx) \
4382 + ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
4383 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4384 + ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4385 +#define SHARED_KEY_ENTRY(__idx) \
4386 + ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4387 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4388 + ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4389 +
4390 +struct mac_wcid_entry {
4391 + u8 mac[6];
4392 + u8 reserved[2];
4393 +} __attribute__ ((packed));
4394 +
4395 +struct hw_key_entry {
4396 + u8 key[16];
4397 + u8 tx_mic[8];
4398 + u8 rx_mic[8];
4399 +} __attribute__ ((packed));
4400 +
4401 +struct mac_iveiv_entry {
4402 + u8 iv[8];
4403 +} __attribute__ ((packed));
4404 +
4405 +/*
4406 + * MAC_WCID_ATTRIBUTE:
4407 + */
4408 +#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
4409 +#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
4410 +#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
4411 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
4412 +
4413 +/*
4414 + * SHARED_KEY_MODE:
4415 + */
4416 +#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
4417 +#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
4418 +#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
4419 +#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
4420 +#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
4421 +#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
4422 +#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
4423 +#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
4424 +
4425 +/*
4426 + * HOST-MCU communication
4427 + */
4428 +
4429 +/*
4430 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4431 + */
4432 +#define H2M_MAILBOX_CSR 0x7010
4433 +#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
4434 +#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
4435 +#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
4436 +#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
4437 +
4438 +/*
4439 + * H2M_MAILBOX_CID:
4440 + */
4441 +#define H2M_MAILBOX_CID 0x7014
4442 +#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
4443 +#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
4444 +#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
4445 +#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
4446 +
4447 +/*
4448 + * H2M_MAILBOX_STATUS:
4449 + */
4450 +#define H2M_MAILBOX_STATUS 0x701c
4451 +
4452 +/*
4453 + * H2M_INT_SRC:
4454 + */
4455 +#define H2M_INT_SRC 0x7024
4456 +
4457 +/*
4458 + * H2M_BBP_AGENT:
4459 + */
4460 +#define H2M_BBP_AGENT 0x7028
4461 +
4462 +/*
4463 + * MCU_LEDCS: LED control for MCU Mailbox.
4464 + */
4465 +#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
4466 +#define MCU_LEDCS_POLARITY FIELD8(0x01)
4467 +
4468 +/*
4469 + * HW_CS_CTS_BASE:
4470 + * Carrier-sense CTS frame base address.
4471 + * It's where mac stores carrier-sense frame for carrier-sense function.
4472 + */
4473 +#define HW_CS_CTS_BASE 0x7700
4474 +
4475 +/*
4476 + * HW_DFS_CTS_BASE:
4477 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4478 + */
4479 +#define HW_DFS_CTS_BASE 0x7780
4480 +
4481 +/*
4482 + * TXRX control registers - base address 0x3000
4483 + */
4484 +
4485 +/*
4486 + * TXRX_CSR1:
4487 + * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4488 + */
4489 +#define TXRX_CSR1 0x77d0
4490 +
4491 +/*
4492 + * HW_DEBUG_SETTING_BASE:
4493 + * since NULL frame won't be that long (256 byte)
4494 + * We steal 16 tail bytes to save debugging settings
4495 + */
4496 +#define HW_DEBUG_SETTING_BASE 0x77f0
4497 +#define HW_DEBUG_SETTING_BASE2 0x7770
4498 +
4499 +/*
4500 + * HW_BEACON_BASE
4501 + * In order to support maximum 8 MBSS and its maximum length
4502 + * is 512 bytes for each beacon
4503 + * Three section discontinue memory segments will be used.
4504 + * 1. The original region for BCN 0~3
4505 + * 2. Extract memory from FCE table for BCN 4~5
4506 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4507 + * It occupied those memory of wcid 238~253 for BCN 6
4508 + * and wcid 222~237 for BCN 7
4509 + *
4510 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4511 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4512 + */
4513 +#define HW_BEACON_BASE0 0x7800
4514 +#define HW_BEACON_BASE1 0x7a00
4515 +#define HW_BEACON_BASE2 0x7c00
4516 +#define HW_BEACON_BASE3 0x7e00
4517 +#define HW_BEACON_BASE4 0x7200
4518 +#define HW_BEACON_BASE5 0x7400
4519 +#define HW_BEACON_BASE6 0x5dc0
4520 +#define HW_BEACON_BASE7 0x5bc0
4521 +
4522 +#define HW_BEACON_OFFSET(__index) \
4523 + ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4524 + (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4525 + (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4526 +
4527 +/*
4528 + * 8051 firmware image.
4529 + */
4530 +#define FIRMWARE_RT2860 "rt2860.bin"
4531 +#define FIRMWARE_IMAGE_BASE 0x2000
4532 +
4533 +/*
4534 + * BBP registers.
4535 + * The wordsize of the BBP is 8 bits.
4536 + */
4537 +
4538 +/*
4539 + * BBP 1: TX Antenna
4540 + */
4541 +#define BBP1_TX_POWER FIELD8(0x07)
4542 +#define BBP1_TX_ANTENNA FIELD8(0x18)
4543 +
4544 +/*
4545 + * BBP 3: RX Antenna
4546 + */
4547 +#define BBP3_RX_ANTENNA FIELD8(0x18)
4548 +
4549 +/*
4550 + * RF registers
4551 + */
4552 +
4553 +/*
4554 + * RF 2
4555 + */
4556 +#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
4557 +#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
4558 +#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
4559 +
4560 +/*
4561 + * RF 3
4562 + */
4563 +#define RF3_TXPOWER_G FIELD32(0x00003e00)
4564 +#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
4565 +#define RF3_TXPOWER_A FIELD32(0x00003c00)
4566 +
4567 +/*
4568 + * RF 4
4569 + */
4570 +#define RF4_TXPOWER_G FIELD32(0x000007c0)
4571 +#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
4572 +#define RF4_TXPOWER_A FIELD32(0x00000780)
4573 +#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
4574 +#define RF4_HT40 FIELD32(0x00200000)
4575 +
4576 +/*
4577 + * EEPROM content.
4578 + * The wordsize of the EEPROM is 16 bits.
4579 + */
4580 +
4581 +/*
4582 + * EEPROM Version
4583 + */
4584 +#define EEPROM_VERSION 0x0001
4585 +#define EEPROM_VERSION_FAE FIELD16(0x00ff)
4586 +#define EEPROM_VERSION_VERSION FIELD16(0xff00)
4587 +
4588 +/*
4589 + * HW MAC address.
4590 + */
4591 +#define EEPROM_MAC_ADDR_0 0x0002
4592 +#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
4593 +#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
4594 +#define EEPROM_MAC_ADDR_1 0x0003
4595 +#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
4596 +#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
4597 +#define EEPROM_MAC_ADDR_2 0x0004
4598 +#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
4599 +#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
4600 +
4601 +/*
4602 + * EEPROM ANTENNA config
4603 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4604 + * TXPATH: 1: 1T, 2: 2T
4605 + */
4606 +#define EEPROM_ANTENNA 0x001a
4607 +#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
4608 +#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
4609 +#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
4610 +
4611 +/*
4612 + * EEPROM NIC config
4613 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4614 + */
4615 +#define EEPROM_NIC 0x001b
4616 +#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
4617 +#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
4618 +#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
4619 +#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
4620 +#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
4621 +#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
4622 +#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
4623 +#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
4624 +#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
4625 +#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
4626 +
4627 +/*
4628 + * EEPROM frequency
4629 + */
4630 +#define EEPROM_FREQ 0x001d
4631 +#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
4632 +#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
4633 +#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
4634 +
4635 +/*
4636 + * EEPROM LED
4637 + * POLARITY_RDY_G: Polarity RDY_G setting.
4638 + * POLARITY_RDY_A: Polarity RDY_A setting.
4639 + * POLARITY_ACT: Polarity ACT setting.
4640 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4641 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4642 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4643 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4644 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4645 + * LED_MODE: Led mode.
4646 + */
4647 +#define EEPROM_LED1 0x001e
4648 +#define EEPROM_LED2 0x001f
4649 +#define EEPROM_LED3 0x0020
4650 +#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
4651 +#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
4652 +#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
4653 +#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
4654 +#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
4655 +#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
4656 +#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
4657 +#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
4658 +#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
4659 +
4660 +/*
4661 + * EEPROM LNA
4662 + */
4663 +#define EEPROM_LNA 0x0022
4664 +#define EEPROM_LNA_BG FIELD16(0x00ff)
4665 +#define EEPROM_LNA_A0 FIELD16(0xff00)
4666 +
4667 +/*
4668 + * EEPROM RSSI BG offset
4669 + */
4670 +#define EEPROM_RSSI_BG 0x0023
4671 +#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
4672 +#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
4673 +
4674 +/*
4675 + * EEPROM RSSI BG2 offset
4676 + */
4677 +#define EEPROM_RSSI_BG2 0x0024
4678 +#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
4679 +#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
4680 +
4681 +/*
4682 + * EEPROM RSSI A offset
4683 + */
4684 +#define EEPROM_RSSI_A 0x0025
4685 +#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
4686 +#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
4687 +
4688 +/*
4689 + * EEPROM RSSI A2 offset
4690 + */
4691 +#define EEPROM_RSSI_A2 0x0026
4692 +#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
4693 +#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
4694 +
4695 +/*
4696 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4697 + * This is delta in 40MHZ.
4698 + * VALUE: Tx Power dalta value (MAX=4)
4699 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4700 + * TXPOWER: Enable:
4701 + */
4702 +#define EEPROM_TXPOWER_DELTA 0x0028
4703 +#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
4704 +#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
4705 +#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
4706 +
4707 +/*
4708 + * EEPROM TXPOWER 802.11BG
4709 + */
4710 +#define EEPROM_TXPOWER_BG1 0x0029
4711 +#define EEPROM_TXPOWER_BG2 0x0030
4712 +#define EEPROM_TXPOWER_BG_SIZE 7
4713 +#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
4714 +#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
4715 +
4716 +/*
4717 + * EEPROM TXPOWER 802.11A
4718 + */
4719 +#define EEPROM_TXPOWER_A1 0x003c
4720 +#define EEPROM_TXPOWER_A2 0x0053
4721 +#define EEPROM_TXPOWER_A_SIZE 6
4722 +#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
4723 +#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
4724 +
4725 +/*
4726 + * EEPROM TXpower byrate: 20MHZ power
4727 + */
4728 +#define EEPROM_TXPOWER_BYRATE 0x006f
4729 +
4730 +/*
4731 + * EEPROM BBP.
4732 + */
4733 +#define EEPROM_BBP_START 0x0078
4734 +#define EEPROM_BBP_SIZE 16
4735 +#define EEPROM_BBP_VALUE FIELD16(0x00ff)
4736 +#define EEPROM_BBP_REG_ID FIELD16(0xff00)
4737 +
4738 +/*
4739 + * MCU mailbox commands.
4740 + */
4741 +#define MCU_SLEEP 0x30
4742 +#define MCU_WAKEUP 0x31
4743 +#define MCU_RADIO_OFF 0x35
4744 +#define MCU_LED 0x50
4745 +#define MCU_LED_STRENGTH 0x51
4746 +#define MCU_LED_1 0x52
4747 +#define MCU_LED_2 0x53
4748 +#define MCU_LED_3 0x54
4749 +#define MCU_RADAR 0x60
4750 +#define MCU_BOOT_SIGNAL 0x72
4751 +#define MCU_BBP_SIGNAL 0x80
4752 +
4753 +/*
4754 + * MCU mailbox tokens
4755 + */
4756 +#define TOKEN_WAKUP 3
4757 +
4758 +/*
4759 + * DMA descriptor defines.
4760 + */
4761 +#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
4762 +#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4763 +#define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
4764 +#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4765 +
4766 +/*
4767 + * TX descriptor format for TX, PRIO and Beacon Ring.
4768 + */
4769 +
4770 +/*
4771 + * Word0
4772 + */
4773 +#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
4774 +
4775 +/*
4776 + * Word1
4777 + */
4778 +#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
4779 +#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
4780 +#define TXD_W1_BURST FIELD32(0x00008000)
4781 +#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
4782 +#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
4783 +#define TXD_W1_DMA_DONE FIELD32(0x80000000)
4784 +
4785 +/*
4786 + * Word2
4787 + */
4788 +#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
4789 +
4790 +/*
4791 + * Word3
4792 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
4793 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4794 + * 0:MGMT, 1:HCCA 2:EDCA
4795 + */
4796 +#define TXD_W3_WIV FIELD32(0x01000000)
4797 +#define TXD_W3_QSEL FIELD32(0x06000000)
4798 +#define TXD_W3_TCO FIELD32(0x20000000)
4799 +#define TXD_W3_UCO FIELD32(0x40000000)
4800 +#define TXD_W3_ICO FIELD32(0x80000000)
4801 +
4802 +/*
4803 + * TX WI structure
4804 + */
4805 +
4806 +/*
4807 + * Word0
4808 + * FRAG: 1 To inform TKIP engine this is a fragment.
4809 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4810 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4811 + * BW: Channel bandwidth 20MHz or 40 MHz
4812 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4813 + */
4814 +#define TXWI_W0_FRAG FIELD32(0x00000001)
4815 +#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
4816 +#define TXWI_W0_CF_ACK FIELD32(0x00000004)
4817 +#define TXWI_W0_TS FIELD32(0x00000008)
4818 +#define TXWI_W0_AMPDU FIELD32(0x00000010)
4819 +#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
4820 +#define TXWI_W0_TX_OP FIELD32(0x00000300)
4821 +#define TXWI_W0_MCS FIELD32(0x007f0000)
4822 +#define TXWI_W0_BW FIELD32(0x00800000)
4823 +#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
4824 +#define TXWI_W0_STBC FIELD32(0x06000000)
4825 +#define TXWI_W0_IFS FIELD32(0x08000000)
4826 +#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
4827 +
4828 +/*
4829 + * Word1
4830 + */
4831 +#define TXWI_W1_ACK FIELD32(0x00000001)
4832 +#define TXWI_W1_NSEQ FIELD32(0x00000002)
4833 +#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
4834 +#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
4835 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4836 +#define TXWI_W1_PACKETID FIELD32(0xf0000000)
4837 +
4838 +/*
4839 + * Word2
4840 + */
4841 +#define TXWI_W2_IV FIELD32(0xffffffff)
4842 +
4843 +/*
4844 + * Word3
4845 + */
4846 +#define TXWI_W3_EIV FIELD32(0xffffffff)
4847 +
4848 +/*
4849 + * RX descriptor format for RX Ring.
4850 + */
4851 +
4852 +/*
4853 + * Word0
4854 + */
4855 +#define RXD_W0_SDP0 FIELD32(0xffffffff)
4856 +
4857 +/*
4858 + * Word1
4859 + */
4860 +#define RXD_W1_SDL1 FIELD32(0x00003fff)
4861 +#define RXD_W1_SDL0 FIELD32(0x3fff0000)
4862 +#define RXD_W1_LS0 FIELD32(0x40000000)
4863 +#define RXD_W1_DMA_DONE FIELD32(0x80000000)
4864 +
4865 +/*
4866 + * Word2
4867 + */
4868 +#define RXD_W2_SDP1 FIELD32(0xffffffff)
4869 +
4870 +/*
4871 + * Word3
4872 + * AMSDU: RX with 802.3 header, not 802.11 header.
4873 + * DECRYPTED: This frame is being decrypted.
4874 + */
4875 +#define RXD_W3_BA FIELD32(0x00000001)
4876 +#define RXD_W3_DATA FIELD32(0x00000002)
4877 +#define RXD_W3_NULLDATA FIELD32(0x00000004)
4878 +#define RXD_W3_FRAG FIELD32(0x00000008)
4879 +#define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
4880 +#define RXD_W3_MULTICAST FIELD32(0x00000020)
4881 +#define RXD_W3_BROADCAST FIELD32(0x00000040)
4882 +#define RXD_W3_MY_BSS FIELD32(0x00000080)
4883 +#define RXD_W3_CRC_ERROR FIELD32(0x00000100)
4884 +#define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
4885 +#define RXD_W3_AMSDU FIELD32(0x00000800)
4886 +#define RXD_W3_HTC FIELD32(0x00001000)
4887 +#define RXD_W3_RSSI FIELD32(0x00002000)
4888 +#define RXD_W3_L2PAD FIELD32(0x00004000)
4889 +#define RXD_W3_AMPDU FIELD32(0x00008000)
4890 +#define RXD_W3_DECRYPTED FIELD32(0x00010000)
4891 +#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
4892 +#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
4893 +
4894 +/*
4895 + * RX WI structure
4896 + */
4897 +
4898 +/*
4899 + * Word0
4900 + */
4901 +#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
4902 +#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
4903 +#define RXWI_W0_BSSID FIELD32(0x00001c00)
4904 +#define RXWI_W0_UDF FIELD32(0x0000e000)
4905 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4906 +#define RXWI_W0_TID FIELD32(0xf0000000)
4907 +
4908 +/*
4909 + * Word1
4910 + */
4911 +#define RXWI_W1_FRAG FIELD32(0x0000000f)
4912 +#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
4913 +#define RXWI_W1_MCS FIELD32(0x007f0000)
4914 +#define RXWI_W1_BW FIELD32(0x00800000)
4915 +#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
4916 +#define RXWI_W1_STBC FIELD32(0x06000000)
4917 +#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
4918 +
4919 +/*
4920 + * Word2
4921 + */
4922 +#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
4923 +#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
4924 +#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
4925 +
4926 +/*
4927 + * Word3
4928 + */
4929 +#define RXWI_W3_SNR0 FIELD32(0x000000ff)
4930 +#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
4931 +
4932 +/*
4933 + * Macro's for converting txpower from EEPROM to mac80211 value
4934 + * and from mac80211 value to register value.
4935 + */
4936 +#define MIN_G_TXPOWER 0
4937 +#define MIN_A_TXPOWER -7
4938 +#define MAX_G_TXPOWER 31
4939 +#define MAX_A_TXPOWER 15
4940 +#define DEFAULT_TXPOWER 5
4941 +
4942 +#define TXPOWER_G_FROM_DEV(__txpower) \
4943 + ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4944 +
4945 +#define TXPOWER_G_TO_DEV(__txpower) \
4946 + clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4947 +
4948 +#define TXPOWER_A_FROM_DEV(__txpower) \
4949 + ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4950 +
4951 +#define TXPOWER_A_TO_DEV(__txpower) \
4952 + clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
4953 +
4954 +#endif /* RT2800PCI_H */
4955 --- a/drivers/net/wireless/rt2x00/rt2x00.h
4956 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
4957 @@ -138,6 +138,12 @@ struct rt2x00_chip {
4958 #define RT2561 0x0302
4959 #define RT2661 0x0401
4960 #define RT2571 0x1300
4961 +#define RT2860 0x0601 /* 2.4GHz PCI/CB */
4962 +#define RT2860D 0x0681 /* 2.4GHz, 5GHz PCI/CB */
4963 +#define RT2890 0x0701 /* 2.4GHz PCIe */
4964 +#define RT2890D 0x0781 /* 2.4GHz, 5GHz PCIe */
4965 +#define RT2880 0x2880 /* WSOC */
4966 +#define RT3052 0x3052 /* WSOC */
4967
4968 u16 rf;
4969 u32 rev;
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