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[package] mac80211/ath9k: enable debug stuff
[openwrt/svn-archive/archive.git] / package / mac80211 / patches / 303-rt2x00-Implement-support-for-rt2800usb.patch
1 From e380f1fa260d81cba1ebb1b6c333ef8c31f2a8c5 Mon Sep 17 00:00:00 2001
2 From: Ivo van Doorn <IvDoorn@gmail.com>
3 Date: Fri, 23 Jan 2009 17:16:11 +0100
4 Subject: [PATCH] rt2x00: Implement support for rt2800usb
5
6 Add support for the rt2800usb chipset.
7
8 Includes various patches from Mattias and Felix.
9
10 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
11 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
12 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
13 ---
14 drivers/net/wireless/rt2x00/Kconfig | 14 +
15 drivers/net/wireless/rt2x00/Makefile | 1 +
16 drivers/net/wireless/rt2x00/rt2800usb.c | 2905 +++++++++++++++++++++++++++++++
17 drivers/net/wireless/rt2x00/rt2800usb.h | 1944 +++++++++++++++++++++
18 drivers/net/wireless/rt2x00/rt2x00.h | 7 +
19 5 files changed, 4871 insertions(+), 0 deletions(-)
20 create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.c
21 create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.h
22
23 --- a/drivers/net/wireless/rt2x00/Makefile
24 +++ b/drivers/net/wireless/rt2x00/Makefile
25 @@ -19,3 +19,4 @@ obj-$(CONFIG_RT61PCI) += rt61pci.o
26 obj-$(CONFIG_RT2800PCI) += rt2800pci.o
27 obj-$(CONFIG_RT2500USB) += rt2500usb.o
28 obj-$(CONFIG_RT73USB) += rt73usb.o
29 +obj-$(CONFIG_RT2800USB) += rt2800usb.o
30 --- /dev/null
31 +++ b/drivers/net/wireless/rt2x00/rt2800usb.c
32 @@ -0,0 +1,2905 @@
33 +/*
34 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
35 + <http://rt2x00.serialmonkey.com>
36 +
37 + This program is free software; you can redistribute it and/or modify
38 + it under the terms of the GNU General Public License as published by
39 + the Free Software Foundation; either version 2 of the License, or
40 + (at your option) any later version.
41 +
42 + This program is distributed in the hope that it will be useful,
43 + but WITHOUT ANY WARRANTY; without even the implied warranty of
44 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
45 + GNU General Public License for more details.
46 +
47 + You should have received a copy of the GNU General Public License
48 + along with this program; if not, write to the
49 + Free Software Foundation, Inc.,
50 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 + */
52 +
53 +/*
54 + Module: rt2800usb
55 + Abstract: rt2800usb device specific routines.
56 + Supported chipsets: RT2800U.
57 + */
58 +
59 +#include <linux/crc-ccitt.h>
60 +#include <linux/delay.h>
61 +#include <linux/etherdevice.h>
62 +#include <linux/init.h>
63 +#include <linux/kernel.h>
64 +#include <linux/module.h>
65 +#include <linux/usb.h>
66 +
67 +#include "rt2x00.h"
68 +#include "rt2x00usb.h"
69 +#include "rt2800usb.h"
70 +
71 +/*
72 + * Allow hardware encryption to be disabled.
73 + */
74 +static int modparam_nohwcrypt = 0;
75 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
76 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
77 +
78 +/*
79 + * Register access.
80 + * All access to the CSR registers will go through the methods
81 + * rt2x00usb_register_read and rt2x00usb_register_write.
82 + * BBP and RF register require indirect register access,
83 + * and use the CSR registers BBPCSR and RFCSR to achieve this.
84 + * These indirect registers work with busy bits,
85 + * and we will try maximal REGISTER_BUSY_COUNT times to access
86 + * the register while taking a REGISTER_BUSY_DELAY us delay
87 + * between each attampt. When the busy bit is still set at that time,
88 + * the access attempt is considered to have failed,
89 + * and we will print an error.
90 + * The _lock versions must be used if you already hold the csr_mutex
91 + */
92 +#define WAIT_FOR_BBP(__dev, __reg) \
93 + rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
94 +#define WAIT_FOR_RFCSR(__dev, __reg) \
95 + rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
96 +#define WAIT_FOR_RF(__dev, __reg) \
97 + rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
98 +#define WAIT_FOR_MCU(__dev, __reg) \
99 + rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
100 + H2M_MAILBOX_CSR_OWNER, (__reg))
101 +
102 +static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
103 + const unsigned int word, const u8 value)
104 +{
105 + u32 reg;
106 +
107 + mutex_lock(&rt2x00dev->csr_mutex);
108 +
109 + /*
110 + * Wait until the BBP becomes available, afterwards we
111 + * can safely write the new data into the register.
112 + */
113 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
114 + reg = 0;
115 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
116 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
117 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
118 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
119 +
120 + rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
121 + }
122 +
123 + mutex_unlock(&rt2x00dev->csr_mutex);
124 +}
125 +
126 +static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
127 + const unsigned int word, u8 *value)
128 +{
129 + u32 reg;
130 +
131 + mutex_lock(&rt2x00dev->csr_mutex);
132 +
133 + /*
134 + * Wait until the BBP becomes available, afterwards we
135 + * can safely write the read request into the register.
136 + * After the data has been written, we wait until hardware
137 + * returns the correct value, if at any time the register
138 + * doesn't become available in time, reg will be 0xffffffff
139 + * which means we return 0xff to the caller.
140 + */
141 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
142 + reg = 0;
143 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
144 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
145 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
146 +
147 + rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
148 +
149 + WAIT_FOR_BBP(rt2x00dev, &reg);
150 + }
151 +
152 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
153 +
154 + mutex_unlock(&rt2x00dev->csr_mutex);
155 +}
156 +
157 +static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
158 + const unsigned int word, const u8 value)
159 +{
160 + u32 reg;
161 +
162 + mutex_lock(&rt2x00dev->csr_mutex);
163 +
164 + /*
165 + * Wait until the RFCSR becomes available, afterwards we
166 + * can safely write the new data into the register.
167 + */
168 + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
169 + reg = 0;
170 + rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
171 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
172 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
173 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
174 +
175 + rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
176 + }
177 +
178 + mutex_unlock(&rt2x00dev->csr_mutex);
179 +}
180 +
181 +static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
182 + const unsigned int word, u8 *value)
183 +{
184 + u32 reg;
185 +
186 + mutex_lock(&rt2x00dev->csr_mutex);
187 +
188 + /*
189 + * Wait until the RFCSR becomes available, afterwards we
190 + * can safely write the read request into the register.
191 + * After the data has been written, we wait until hardware
192 + * returns the correct value, if at any time the register
193 + * doesn't become available in time, reg will be 0xffffffff
194 + * which means we return 0xff to the caller.
195 + */
196 + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
197 + reg = 0;
198 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
199 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
200 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
201 +
202 + rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
203 +
204 + WAIT_FOR_RFCSR(rt2x00dev, &reg);
205 + }
206 +
207 + *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
208 +
209 + mutex_unlock(&rt2x00dev->csr_mutex);
210 +}
211 +
212 +static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
213 + const unsigned int word, const u32 value)
214 +{
215 + u32 reg;
216 +
217 + if (!word)
218 + return;
219 +
220 + mutex_lock(&rt2x00dev->csr_mutex);
221 +
222 + /*
223 + * Wait until the RF becomes available, afterwards we
224 + * can safely write the new data into the register.
225 + */
226 + if (WAIT_FOR_RF(rt2x00dev, &reg)) {
227 + reg = 0;
228 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
229 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
230 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
231 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
232 +
233 + rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
234 + rt2x00_rf_write(rt2x00dev, word, value);
235 + }
236 +
237 + mutex_unlock(&rt2x00dev->csr_mutex);
238 +}
239 +
240 +static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
241 + const u8 command, const u8 token,
242 + const u8 arg0, const u8 arg1)
243 +{
244 + u32 reg;
245 +
246 + mutex_lock(&rt2x00dev->csr_mutex);
247 +
248 + /*
249 + * Wait until the MCU becomes available, afterwards we
250 + * can safely write the new data into the register.
251 + */
252 + if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
253 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
254 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
255 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
256 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
257 + rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
258 +
259 + reg = 0;
260 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
261 + rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
262 + }
263 +
264 + mutex_unlock(&rt2x00dev->csr_mutex);
265 +}
266 +
267 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
268 +static const struct rt2x00debug rt2800usb_rt2x00debug = {
269 + .owner = THIS_MODULE,
270 + .csr = {
271 + .read = rt2x00usb_register_read,
272 + .write = rt2x00usb_register_write,
273 + .flags = RT2X00DEBUGFS_OFFSET,
274 + .word_base = CSR_REG_BASE,
275 + .word_size = sizeof(u32),
276 + .word_count = CSR_REG_SIZE / sizeof(u32),
277 + },
278 + .eeprom = {
279 + .read = rt2x00_eeprom_read,
280 + .write = rt2x00_eeprom_write,
281 + .word_base = EEPROM_BASE,
282 + .word_size = sizeof(u16),
283 + .word_count = EEPROM_SIZE / sizeof(u16),
284 + },
285 + .bbp = {
286 + .read = rt2800usb_bbp_read,
287 + .write = rt2800usb_bbp_write,
288 + .word_base = BBP_BASE,
289 + .word_size = sizeof(u8),
290 + .word_count = BBP_SIZE / sizeof(u8),
291 + },
292 + .rf = {
293 + .read = rt2x00_rf_read,
294 + .write = rt2800usb_rf_write,
295 + .word_base = RF_BASE,
296 + .word_size = sizeof(u32),
297 + .word_count = RF_SIZE / sizeof(u32),
298 + },
299 +};
300 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
301 +
302 +#ifdef CONFIG_RT2X00_LIB_RFKILL
303 +static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
304 +{
305 + u32 reg;
306 +
307 + rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
308 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
309 +}
310 +#else
311 +#define rt2800usb_rfkill_poll NULL
312 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
313 +
314 +#ifdef CONFIG_RT2X00_LIB_LEDS
315 +static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
316 + enum led_brightness brightness)
317 +{
318 + struct rt2x00_led *led =
319 + container_of(led_cdev, struct rt2x00_led, led_dev);
320 + unsigned int enabled = brightness != LED_OFF;
321 + unsigned int bg_mode =
322 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
323 + unsigned int polarity =
324 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
325 + EEPROM_FREQ_LED_POLARITY);
326 + unsigned int ledmode =
327 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
328 + EEPROM_FREQ_LED_MODE);
329 +
330 + if (led->type == LED_TYPE_RADIO) {
331 + rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
332 + enabled ? 0x20 : 0);
333 + } else if (led->type == LED_TYPE_ASSOC) {
334 + rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
335 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
336 + } else if (led->type == LED_TYPE_QUALITY) {
337 + /*
338 + * The brightness is divided into 6 levels (0 - 5),
339 + * The specs tell us the following levels:
340 + * 0, 1 ,3, 7, 15, 31
341 + * to determine the level in a simple way we can simply
342 + * work with bitshifting:
343 + * (1 << level) - 1
344 + */
345 + rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
346 + (1 << brightness / (LED_FULL / 6)) - 1,
347 + polarity);
348 + }
349 +}
350 +
351 +static int rt2800usb_blink_set(struct led_classdev *led_cdev,
352 + unsigned long *delay_on,
353 + unsigned long *delay_off)
354 +{
355 + struct rt2x00_led *led =
356 + container_of(led_cdev, struct rt2x00_led, led_dev);
357 + u32 reg;
358 +
359 + rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
360 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
361 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
362 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
363 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
364 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
365 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
366 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
367 + rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
368 +
369 + return 0;
370 +}
371 +
372 +static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
373 + struct rt2x00_led *led,
374 + enum led_type type)
375 +{
376 + led->rt2x00dev = rt2x00dev;
377 + led->type = type;
378 + led->led_dev.brightness_set = rt2800usb_brightness_set;
379 + led->led_dev.blink_set = rt2800usb_blink_set;
380 + led->flags = LED_INITIALIZED;
381 +}
382 +#endif /* CONFIG_RT2X00_LIB_LEDS */
383 +
384 +/*
385 + * Configuration handlers.
386 + */
387 +static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
388 + struct rt2x00lib_crypto *crypto,
389 + struct ieee80211_key_conf *key)
390 +{
391 + u32 offset;
392 + u32 reg;
393 +
394 + offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
395 +
396 + reg = 0;
397 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
398 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
399 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_PAIRKEY_MODE,
400 + crypto->cipher);
401 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
402 + (crypto->cmd == SET_KEY) ? crypto->bssidx : 0);
403 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
404 + rt2x00usb_register_write(rt2x00dev, offset, reg);
405 +}
406 +
407 +static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
408 + struct rt2x00lib_crypto *crypto,
409 + struct ieee80211_key_conf *key)
410 +{
411 + struct hw_key_entry key_entry;
412 + struct rt2x00_field32 field;
413 + int timeout;
414 + u32 offset;
415 + u32 mask;
416 + u32 reg;
417 +
418 + if (crypto->cmd == SET_KEY) {
419 + memcpy(key_entry.key, crypto->key,
420 + sizeof(key_entry.key));
421 + memcpy(key_entry.tx_mic, crypto->tx_mic,
422 + sizeof(key_entry.tx_mic));
423 + memcpy(key_entry.rx_mic, crypto->rx_mic,
424 + sizeof(key_entry.rx_mic));
425 +
426 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
427 + timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
428 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
429 + USB_VENDOR_REQUEST_OUT,
430 + offset, &key_entry,
431 + sizeof(key_entry),
432 + timeout);
433 +
434 + /*
435 + * The driver does not support the IV/EIV generation
436 + * in hardware. However it doesn't support the IV/EIV
437 + * inside the ieee80211 frame either, but requires it
438 + * to be provided seperately for the descriptor.
439 + * rt2x00lib will cut the IV/EIV data out of all frames
440 + * given to us by mac80211, but we must tell mac80211
441 + * to generate the IV/EIV data.
442 + */
443 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
444 + }
445 +
446 + /*
447 + * The cipher types are stored over multiple registers
448 + * starting with SHARED_KEY_MODE_BASE each word will have
449 + * 32 bits and contains the cipher types for 2 modes each.
450 + * Using the correct defines correctly will cause overhead,
451 + * so just calculate the correct offset.
452 + */
453 + mask = key->hw_key_idx % 8;
454 + field.bit_offset = (3 * mask);
455 + field.bit_mask = 0x7 << field.bit_offset;
456 +
457 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
458 + rt2x00usb_register_read(rt2x00dev, offset, &reg);
459 + rt2x00_set_field32(&reg, field,
460 + (crypto->cmd == SET_KEY) ? crypto->cipher : 0);
461 + rt2x00usb_register_write(rt2x00dev, offset, reg);
462 +
463 + /*
464 + * Update WCID information
465 + */
466 + rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
467 +
468 + return 0;
469 +}
470 +
471 +static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
472 + struct rt2x00lib_crypto *crypto,
473 + struct ieee80211_key_conf *key)
474 +{
475 + struct hw_key_entry key_entry;
476 + int timeout;
477 + u32 offset;
478 +
479 + /*
480 + * 1 pairwise key is possible per AID, this means that the AID
481 + * equals our hw_key_idx.
482 + */
483 + key->hw_key_idx = crypto->aid;
484 +
485 + if (crypto->cmd == SET_KEY) {
486 + memcpy(key_entry.key, crypto->key,
487 + sizeof(key_entry.key));
488 + memcpy(key_entry.tx_mic, crypto->tx_mic,
489 + sizeof(key_entry.tx_mic));
490 + memcpy(key_entry.rx_mic, crypto->rx_mic,
491 + sizeof(key_entry.rx_mic));
492 +
493 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
494 + timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
495 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
496 + USB_VENDOR_REQUEST_OUT,
497 + offset, &key_entry,
498 + sizeof(key_entry),
499 + timeout);
500 +
501 + /*
502 + * The driver does not support the IV/EIV generation
503 + * in hardware. However it doesn't support the IV/EIV
504 + * inside the ieee80211 frame either, but requires it
505 + * to be provided seperately for the descriptor.
506 + * rt2x00lib will cut the IV/EIV data out of all frames
507 + * given to us by mac80211, but we must tell mac80211
508 + * to generate the IV/EIV data.
509 + */
510 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
511 + }
512 +
513 + /*
514 + * Update WCID information
515 + */
516 + rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
517 +
518 + return 0;
519 +}
520 +
521 +static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
522 + const unsigned int filter_flags)
523 +{
524 + u32 reg;
525 +
526 + /*
527 + * Start configuration steps.
528 + * Note that the version error will always be dropped
529 + * and broadcast frames will always be accepted since
530 + * there is no filter for it at this time.
531 + */
532 + rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
533 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
534 + !(filter_flags & FIF_FCSFAIL));
535 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
536 + !(filter_flags & FIF_PLCPFAIL));
537 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
538 + !(filter_flags & FIF_PROMISC_IN_BSS));
539 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
540 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
541 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
542 + !(filter_flags & FIF_ALLMULTI));
543 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
544 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
545 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
546 + !(filter_flags & FIF_CONTROL));
547 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
548 + !(filter_flags & FIF_CONTROL));
549 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
550 + !(filter_flags & FIF_CONTROL));
551 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
552 + !(filter_flags & FIF_CONTROL));
553 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
554 + !(filter_flags & FIF_CONTROL));
555 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
556 + !(filter_flags & FIF_CONTROL));
557 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
558 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 1);
559 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
560 + !(filter_flags & FIF_CONTROL));
561 + rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
562 +}
563 +
564 +static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
565 + struct rt2x00_intf *intf,
566 + struct rt2x00intf_conf *conf,
567 + const unsigned int flags)
568 +{
569 + unsigned int beacon_base;
570 + u32 reg;
571 +
572 + if (flags & CONFIG_UPDATE_TYPE) {
573 + /*
574 + * Clear current synchronisation setup.
575 + * For the Beacon base registers we only need to clear
576 + * the first byte since that byte contains the VALID and OWNER
577 + * bits which (when set to 0) will invalidate the entire beacon.
578 + */
579 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
580 + rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
581 +
582 + /*
583 + * Enable synchronisation.
584 + */
585 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
586 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
587 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
588 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
589 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
590 + }
591 +
592 + if (flags & CONFIG_UPDATE_MAC) {
593 + reg = le32_to_cpu(conf->mac[1]);
594 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
595 + conf->mac[1] = cpu_to_le32(reg);
596 +
597 + rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
598 + conf->mac, sizeof(conf->mac));
599 + }
600 +
601 + if (flags & CONFIG_UPDATE_BSSID) {
602 + reg = le32_to_cpu(conf->bssid[1]);
603 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
604 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
605 + conf->bssid[1] = cpu_to_le32(reg);
606 +
607 + rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
608 + conf->bssid, sizeof(conf->bssid));
609 + }
610 +}
611 +
612 +static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
613 + struct rt2x00lib_erp *erp)
614 +{
615 + u32 reg;
616 +
617 + rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
618 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
619 + erp->ack_timeout);
620 + rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
621 +
622 + rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
623 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
624 + !!erp->short_preamble);
625 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
626 + !!erp->short_preamble);
627 + rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
628 +
629 + rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
630 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
631 + erp->cts_protection ? 2 : 0);
632 + rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
633 +
634 + rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
635 + erp->basic_rates);
636 + rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE,
637 + erp->basic_rates >> 32);
638 +
639 + rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
640 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
641 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
642 + rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
643 +
644 + rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
645 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
646 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
647 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
648 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
649 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
650 + rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
651 +}
652 +
653 +static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
654 + struct antenna_setup *ant)
655 +{
656 + u16 eeprom;
657 + u8 r1;
658 + u8 r3;
659 +
660 + /*
661 + * FIXME: Use requested antenna configuration.
662 + */
663 +
664 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
665 +
666 + rt2800usb_bbp_read(rt2x00dev, 1, &r1);
667 + rt2800usb_bbp_read(rt2x00dev, 3, &r3);
668 +
669 + /*
670 + * Configure the TX antenna.
671 + */
672 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
673 + case 1:
674 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
675 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
676 + break;
677 + case 2:
678 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 16);
679 + break;
680 + case 3:
681 + /* Do nothing */
682 + break;
683 + }
684 +
685 + /*
686 + * Configure the RX antenna.
687 + */
688 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
689 + case 1:
690 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
691 + break;
692 + case 2:
693 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
694 + break;
695 + case 3:
696 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
697 + break;
698 + }
699 +
700 + rt2800usb_bbp_write(rt2x00dev, 3, r3);
701 + rt2800usb_bbp_write(rt2x00dev, 1, r1);
702 +}
703 +
704 +static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
705 + struct rt2x00lib_conf *libconf)
706 +{
707 + u16 eeprom;
708 + short lna_gain;
709 +
710 + if (libconf->rf.channel <= 14) {
711 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
712 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
713 + } else if (libconf->rf.channel <= 64) {
714 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
715 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
716 + } else if (libconf->rf.channel <= 128) {
717 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
718 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
719 + } else {
720 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
721 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
722 + }
723 +
724 + rt2x00dev->lna_gain = lna_gain;
725 +}
726 +
727 +static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
728 + struct rf_channel *rf,
729 + struct channel_info *info)
730 +{
731 + u16 eeprom;
732 +
733 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
734 +
735 + /*
736 + * Determine antenna settings from EEPROM
737 + */
738 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
739 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
740 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
741 +
742 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
743 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
744 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
745 + } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
746 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
747 +
748 + if (rf->channel > 14) {
749 + /*
750 + * When TX power is below 0, we should increase it by 7 to
751 + * make it a positive value (Minumum value is -7).
752 + * However this means that values between 0 and 7 have
753 + * double meaning, and we should set a 7DBm boost flag.
754 + */
755 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
756 + (info->tx_power1 >= 0));
757 +
758 + if (info->tx_power1 < 0)
759 + info->tx_power1 += 7;
760 +
761 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
762 + TXPOWER_A_TO_DEV(info->tx_power1));
763 +
764 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
765 + (info->tx_power2 >= 0));
766 +
767 + if (info->tx_power2 < 0)
768 + info->tx_power2 += 7;
769 +
770 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
771 + TXPOWER_A_TO_DEV(info->tx_power2));
772 + } else {
773 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
774 + TXPOWER_G_TO_DEV(info->tx_power1));
775 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
776 + TXPOWER_G_TO_DEV(info->tx_power2));
777 + }
778 +
779 + rt2x00_set_field32(&rf->rf4, RF4_BW40,
780 + test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
781 +
782 + rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
783 + rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
784 + rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
785 + rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
786 +
787 + udelay(200);
788 +
789 + rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
790 + rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
791 + rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
792 + rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
793 +
794 + udelay(200);
795 +
796 + rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
797 + rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
798 + rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
799 + rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
800 +}
801 +
802 +static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
803 + struct rf_channel *rf,
804 + struct channel_info *info)
805 +{
806 + u8 rfcsr;
807 +
808 + rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
809 + rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
810 +
811 + rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
812 + rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
813 + rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
814 +
815 + rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
816 + rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
817 + TXPOWER_G_TO_DEV(info->tx_power1));
818 + rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
819 +
820 + rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
821 + rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
822 + rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
823 +
824 + if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
825 + rt2800usb_rfcsr_write(rt2x00dev, 24, rt2x00dev->calibration_bw40);
826 + else
827 + rt2800usb_rfcsr_write(rt2x00dev, 24, rt2x00dev->calibration_bw20);
828 +
829 + rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
830 + rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
831 + rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
832 +}
833 +
834 +static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
835 + struct rf_channel *rf,
836 + struct channel_info *info)
837 +{
838 + u32 reg;
839 + unsigned int tx_pin;
840 + u16 eeprom;
841 +
842 + if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
843 + rt2800usb_config_channel_rt2x(rt2x00dev, rf, info);
844 + else
845 + rt2800usb_config_channel_rt3x(rt2x00dev, rf, info);
846 +
847 + tx_pin = 0;
848 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
849 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
850 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
851 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
852 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
853 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
854 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
855 +
856 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
857 +
858 + /* Turn off unused PA or LNA when only 1T or 1R */
859 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
860 +
861 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
862 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
863 + }
864 +
865 + /* Turn off unused PA or LNA when only 1T or 1R */
866 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
867 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
868 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
869 + }
870 +
871 + if (rf->channel > 14)
872 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
873 + else
874 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
875 +
876 + /*
877 + * Change BBP settings
878 + */
879 + rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
880 + rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
881 + rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
882 + rt2800usb_bbp_write(rt2x00dev, 86, 0);
883 +
884 + if (rf->channel <= 14) {
885 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
886 + rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
887 + rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
888 + } else {
889 + rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
890 + rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
891 + }
892 +
893 + rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
894 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
895 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
896 + rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
897 + } else {
898 + rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
899 +
900 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
901 + rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
902 + else
903 + rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
904 +
905 + rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
906 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
907 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
908 + rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
909 + }
910 +
911 + rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
912 +
913 + msleep(1);
914 +}
915 +
916 +static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
917 + const int txpower)
918 +{
919 + u32 reg;
920 + u32 value = TXPOWER_G_TO_DEV(txpower);
921 + u8 r1;
922 +
923 + rt2800usb_bbp_read(rt2x00dev, 1, &r1);
924 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
925 + rt2800usb_bbp_write(rt2x00dev, 1, r1);
926 +
927 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
928 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
929 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
930 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
931 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
932 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
933 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
934 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
935 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
936 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
937 +
938 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
939 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
940 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
941 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
942 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
943 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
944 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
945 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
946 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
947 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
948 +
949 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
950 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
951 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
952 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
953 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
954 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
955 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
956 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
957 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
958 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
959 +
960 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
961 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
962 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
963 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
964 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
965 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
966 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
967 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
968 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
969 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
970 +
971 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
972 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
973 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
974 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
975 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
976 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
977 +}
978 +
979 +static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
980 + struct rt2x00lib_conf *libconf)
981 +{
982 + u32 reg;
983 +
984 + rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
985 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
986 + libconf->conf->short_frame_max_tx_count);
987 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
988 + libconf->conf->long_frame_max_tx_count);
989 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
990 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
991 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
992 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
993 + rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
994 +}
995 +
996 +static void rt2800usb_config_duration(struct rt2x00_dev *rt2x00dev,
997 + struct rt2x00lib_conf *libconf)
998 +{
999 + u32 reg;
1000 +
1001 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1002 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1003 + libconf->conf->beacon_int * 16);
1004 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1005 +}
1006 +
1007 +static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
1008 + struct rt2x00lib_conf *libconf)
1009 +{
1010 + enum dev_state state =
1011 + (libconf->conf->flags & IEEE80211_CONF_PS) ?
1012 + STATE_SLEEP : STATE_AWAKE;
1013 + u32 reg;
1014 +
1015 + if (state == STATE_SLEEP) {
1016 + rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1017 +
1018 + rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1019 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1020 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1021 + libconf->conf->listen_interval - 1);
1022 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1023 + rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1024 +
1025 + rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
1026 + } else {
1027 + rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1028 +
1029 + rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1030 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1031 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1032 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1033 + rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1034 + }
1035 +}
1036 +
1037 +static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
1038 + struct rt2x00lib_conf *libconf,
1039 + const unsigned int flags)
1040 +{
1041 + /* Always recalculate LNA gain before changing configuration */
1042 + rt2800usb_config_lna_gain(rt2x00dev, libconf);
1043 +
1044 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1045 + rt2800usb_config_channel(rt2x00dev, &libconf->rf,
1046 + &libconf->channel);
1047 + if (flags & IEEE80211_CONF_CHANGE_POWER)
1048 + rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1049 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1050 + rt2800usb_config_retry_limit(rt2x00dev, libconf);
1051 + if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1052 + rt2800usb_config_duration(rt2x00dev, libconf);
1053 + if (flags & IEEE80211_CONF_CHANGE_PS)
1054 + rt2800usb_config_ps(rt2x00dev, libconf);
1055 +}
1056 +
1057 +/*
1058 + * Link tuning
1059 + */
1060 +static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1061 + struct link_qual *qual)
1062 +{
1063 + u32 reg;
1064 +
1065 + /*
1066 + * Update FCS error count from register.
1067 + */
1068 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1069 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1070 +
1071 + /*
1072 + * Update False CCA count from register.
1073 + */
1074 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1075 + qual->false_cca = rt2x00_get_field32(reg, RX_STA_CNT1_FALSE_CCA);
1076 +}
1077 +
1078 +static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1079 +{
1080 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1081 + if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1082 + return 0x1c + (2 * rt2x00dev->lna_gain);
1083 + else
1084 + return 0x2e + rt2x00dev->lna_gain;
1085 + }
1086 +
1087 + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1088 + return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1089 + else
1090 + return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1091 +}
1092 +
1093 +static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1094 + struct link_qual *qual, u8 vgc_level)
1095 +{
1096 + if (qual->vgc_level != vgc_level) {
1097 + rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1098 + qual->vgc_level = vgc_level;
1099 + qual->vgc_level_reg = vgc_level;
1100 + }
1101 +}
1102 +
1103 +static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1104 + struct link_qual *qual)
1105 +{
1106 + rt2800usb_set_vgc(rt2x00dev, qual,
1107 + rt2800usb_get_default_vgc(rt2x00dev));
1108 +}
1109 +
1110 +static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1111 + struct link_qual *qual, const u32 count)
1112 +{
1113 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1114 + return;
1115 +
1116 + /*
1117 + * When RSSI is better then -80 increase VGC level with 0x10
1118 + */
1119 + rt2800usb_set_vgc(rt2x00dev, qual,
1120 + rt2800usb_get_default_vgc(rt2x00dev) +
1121 + ((qual->rssi > -80) * 0x10));
1122 +}
1123 +
1124 +/*
1125 + * Firmware functions
1126 + */
1127 +static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1128 +{
1129 + return FIRMWARE_RT2870;
1130 +}
1131 +
1132 +static u16 rt2800usb_get_firmware_crc(const void *data, const size_t len)
1133 +{
1134 + u16 crc;
1135 +
1136 + /*
1137 + * Use the crc ccitt algorithm.
1138 + * This will return the same value as the legacy driver which
1139 + * used bit ordering reversion on the both the firmware bytes
1140 + * before input input as well as on the final output.
1141 + * Obviously using crc ccitt directly is much more efficient.
1142 + * The last 2 bytes in the firmware array are the crc checksum itself,
1143 + * this means that we should never pass those 2 bytes to the crc
1144 + * algorithm.
1145 + */
1146 + crc = crc_ccitt(~0, data, len - 2);
1147 +
1148 + /*
1149 + * There is a small difference between the crc-itu-t + bitrev and
1150 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
1151 + * will be swapped, use swab16 to convert the crc to the correct
1152 + * value.
1153 + */
1154 + return swab16(crc);
1155 +}
1156 +
1157 +static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1158 + const void *data, const size_t len)
1159 +{
1160 + unsigned int i;
1161 + int status;
1162 + u32 reg;
1163 + u32 offset;
1164 + u32 length;
1165 + u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1166 +
1167 + /*
1168 + * Firmware files:
1169 + * There are 2 variations of the rt2870 firmware.
1170 + * a) size: 4kb
1171 + * b) size: 8kb
1172 + * Note that (b) contains 2 seperate firmware blobs of 4k
1173 + * within the file. The first blob is the same firmware as (a),
1174 + * but the second blob is for the additional chipsets.
1175 + */
1176 + if (len != 4096 && len != 8192) {
1177 + ERROR(rt2x00dev, "Invalid firmware file length (len=%zu)\n", len);
1178 + return -ENOENT;
1179 + }
1180 +
1181 + if ((chipset == 0x2860) || (chipset == 0x2872) || (chipset == 0x3070)) {
1182 + offset = 0;
1183 + length = 4096;
1184 + } else if (len == 8192) {
1185 + offset = 4096;
1186 + length = 4096;
1187 + } else {
1188 + ERROR(rt2x00dev,
1189 + "Current firmware does not support detected chipset %04x.\n",
1190 + chipset);
1191 + ERROR(rt2x00dev,
1192 + "Please upgrade to a more recent firmware version.\n");
1193 + return -ENOENT;
1194 + }
1195 +
1196 + /*
1197 + * Wait for stable hardware.
1198 + */
1199 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1200 + rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1201 + if (reg && reg != ~0)
1202 + break;
1203 + msleep(1);
1204 + }
1205 +
1206 + if (i == REGISTER_BUSY_COUNT) {
1207 + ERROR(rt2x00dev, "Unstable hardware.\n");
1208 + return -EBUSY;
1209 + }
1210 +
1211 + /*
1212 + * Write firmware to device.
1213 + */
1214 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1215 + USB_VENDOR_REQUEST_OUT,
1216 + FIRMWARE_IMAGE_BASE,
1217 + data + offset, length,
1218 + REGISTER_TIMEOUT32(length));
1219 +
1220 + rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1221 + rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1222 +
1223 + /*
1224 + * Send firmware request to device to load firmware,
1225 + * we need to specify a long timeout time.
1226 + */
1227 + status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1228 + 0, USB_MODE_FIRMWARE,
1229 + REGISTER_TIMEOUT_FIRMWARE);
1230 + if (status < 0) {
1231 + ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1232 + return status;
1233 + }
1234 +
1235 + /*
1236 + * Wait for device to stabilize.
1237 + */
1238 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1239 + rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1240 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1241 + break;
1242 + msleep(1);
1243 + }
1244 +
1245 + if (i == REGISTER_BUSY_COUNT) {
1246 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1247 + return -EBUSY;
1248 + }
1249 +
1250 + /*
1251 + * Initialize firmware.
1252 + */
1253 + rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1254 + rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1255 + msleep(1);
1256 +
1257 + return 0;
1258 +}
1259 +
1260 +/*
1261 + * Initialization functions.
1262 + */
1263 +static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1264 +{
1265 + u32 reg;
1266 + unsigned int i;
1267 +
1268 + /*
1269 + * Wait untill BBP and RF are ready.
1270 + */
1271 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1272 + rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1273 + if (reg && reg != ~0)
1274 + break;
1275 + msleep(1);
1276 + }
1277 +
1278 + if (i == REGISTER_BUSY_COUNT) {
1279 + ERROR(rt2x00dev, "Unstable hardware.\n");
1280 + return -EBUSY;
1281 + }
1282 +
1283 + rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1284 + rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1285 +
1286 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1287 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1288 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1289 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1290 +
1291 + rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1292 +
1293 + rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1294 + USB_MODE_RESET, REGISTER_TIMEOUT);
1295 +
1296 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1297 +
1298 + rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1299 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1300 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1301 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1302 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1303 + rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1304 +
1305 + rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1306 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1307 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1308 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1309 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1310 + rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1311 +
1312 + rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1313 + rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1314 +
1315 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1316 +
1317 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1318 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1319 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1320 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1321 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1322 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1323 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1324 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1325 +
1326 + if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1327 + rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1328 + rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1329 + rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1330 + } else {
1331 + rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00040a06);
1332 + rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1333 + }
1334 +
1335 + rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1336 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1337 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1338 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1339 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1340 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1341 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1342 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1343 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1344 + rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1345 +
1346 + rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1347 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1348 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1349 + rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1350 +
1351 + rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1352 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1353 + if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1354 + rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1355 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1356 + else
1357 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1358 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1359 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1360 + rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1361 +
1362 + rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1363 +
1364 + rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1365 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1366 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1367 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1368 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1369 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1370 + rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1371 +
1372 + rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1373 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1374 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1375 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1376 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1377 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1378 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1379 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1380 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1381 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1382 + rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1383 +
1384 + rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1385 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1386 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1387 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1388 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1389 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1390 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1391 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1392 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1393 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1394 + rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1395 +
1396 + rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1397 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1398 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1399 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1400 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1401 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1402 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1403 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1404 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1405 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1406 + rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1407 +
1408 + rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1409 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1410 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1411 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1412 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1413 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1414 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1415 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1416 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1417 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1418 + rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1419 +
1420 + rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1421 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1422 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1423 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1424 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1425 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1426 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1427 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1428 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1429 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1430 + rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1431 +
1432 + rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1433 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1434 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1435 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1436 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1437 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1438 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1439 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1440 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1441 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1442 + rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1443 +
1444 + rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1445 +
1446 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1447 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1448 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1449 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1450 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1451 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1452 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1453 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1454 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1455 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1456 + rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1457 +
1458 + rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1459 + rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1460 +
1461 + rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1462 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1463 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1464 + rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1465 +
1466 + rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1467 + rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1468 +
1469 + /*
1470 + * ASIC will keep garbage value after boot, clear encryption keys.
1471 + */
1472 + for (i = 0; i < 254; i++) {
1473 + u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1474 + rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1475 + wcid, sizeof(wcid));
1476 + }
1477 +
1478 + for (i = 0; i < 4; i++)
1479 + rt2x00usb_register_write(rt2x00dev,
1480 + SHARED_KEY_MODE_ENTRY(i), 0);
1481 +
1482 + for (i = 0; i < 256; i++)
1483 + rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1484 +
1485 + /*
1486 + * Clear all beacons
1487 + * For the Beacon base registers we only need to clear
1488 + * the first byte since that byte contains the VALID and OWNER
1489 + * bits which (when set to 0) will invalidate the entire beacon.
1490 + */
1491 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1492 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1493 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1494 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1495 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1496 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1497 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1498 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1499 +
1500 + rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1501 + rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1502 + rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1503 +
1504 + rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1505 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1506 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1507 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1508 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1509 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1510 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1511 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1512 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1513 + rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1514 +
1515 + rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1516 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1517 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1518 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1519 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1520 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1521 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1522 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1523 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1524 + rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1525 +
1526 + rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1527 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1528 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1529 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 10);
1530 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 11);
1531 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 12);
1532 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 13);
1533 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 14);
1534 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 15);
1535 + rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1536 +
1537 + rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1538 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1539 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1540 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1541 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1542 + rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1543 +
1544 + /*
1545 + * We must clear the error counters.
1546 + * These registers are cleared on read,
1547 + * so we may pass a useless variable to store the value.
1548 + */
1549 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1550 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1551 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1552 + rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1553 + rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1554 + rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1555 +
1556 + return 0;
1557 +}
1558 +
1559 +static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1560 +{
1561 + unsigned int i;
1562 + u32 reg;
1563 +
1564 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1565 + rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1566 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1567 + return 0;
1568 +
1569 + udelay(REGISTER_BUSY_DELAY);
1570 + }
1571 +
1572 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1573 + return -EACCES;
1574 +}
1575 +
1576 +static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1577 +{
1578 + unsigned int i;
1579 + u8 value;
1580 +
1581 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1582 + rt2800usb_bbp_read(rt2x00dev, 0, &value);
1583 + if ((value != 0xff) && (value != 0x00))
1584 + return 0;
1585 + udelay(REGISTER_BUSY_DELAY);
1586 + }
1587 +
1588 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1589 + return -EACCES;
1590 +}
1591 +
1592 +static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1593 +{
1594 + unsigned int i;
1595 + u16 eeprom;
1596 + u8 reg_id;
1597 + u8 value;
1598 +
1599 + if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1600 + rt2800usb_wait_bbp_ready(rt2x00dev)))
1601 + return -EACCES;
1602 +
1603 + rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1604 + rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1605 + rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1606 + rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1607 + rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1608 + rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1609 + rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1610 + rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1611 + rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1612 + rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1613 + rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1614 + rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1615 + rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1616 + rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1617 +
1618 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1619 + rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1620 + rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1621 + }
1622 +
1623 + if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1624 + rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1625 + rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1626 + rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1627 + }
1628 +
1629 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1630 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1631 +
1632 + if (eeprom != 0xffff && eeprom != 0x0000) {
1633 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1634 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1635 + rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1636 + }
1637 + }
1638 +
1639 + return 0;
1640 +}
1641 +
1642 +static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1643 + bool bw40, u8 rfcsr24, u8 filter_target)
1644 +{
1645 + unsigned int i;
1646 + u8 bbp;
1647 + u8 rfcsr;
1648 + u8 passband;
1649 + u8 stopband;
1650 + u8 overtuned = 0;
1651 +
1652 + rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1653 +
1654 + if (bw40) {
1655 + rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1656 + rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0x10);
1657 + rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1658 + }
1659 +
1660 + rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1661 + rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1662 + rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1663 +
1664 + /*
1665 + * Set power & frequency of passband test tone
1666 + */
1667 + rt2800usb_bbp_write(rt2x00dev, 24, 0);
1668 +
1669 + for (i = 0; i < 100; i++) {
1670 + rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1671 + msleep(1);
1672 +
1673 + rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1674 + if (passband)
1675 + break;
1676 + }
1677 +
1678 + /*
1679 + * Set power & frequency of stopband test tone
1680 + */
1681 + rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1682 +
1683 + for (i = 0; i < 100; i++) {
1684 + rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1685 + msleep(1);
1686 +
1687 + rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1688 +
1689 + if ((passband - stopband) <= filter_target) {
1690 + rfcsr24++;
1691 + overtuned += ((passband - stopband) == filter_target);
1692 + } else
1693 + break;
1694 +
1695 + rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1696 + }
1697 +
1698 + rfcsr24 -= !!overtuned;
1699 +
1700 + rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1701 + return rfcsr24;
1702 +}
1703 +
1704 +static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1705 +{
1706 + u8 rfcsr;
1707 + u8 bbp;
1708 +
1709 + if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1710 + return 0;
1711 +
1712 + /*
1713 + * Init RF calibration.
1714 + */
1715 + rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1716 + rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1717 + rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1718 + msleep(1);
1719 + rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1720 + rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1721 +
1722 + rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1723 + rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1724 + rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1725 + rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1726 + rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1727 + rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1728 + rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1729 + rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1730 + rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1731 + rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1732 + rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1733 + rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1734 + rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1735 + rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1736 + rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1737 + rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1738 + rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1739 + rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1740 + rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1741 + rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1742 +
1743 + /*
1744 + * Set RX Filter calibration for 20MHz and 40MHz
1745 + */
1746 + rt2x00dev->calibration_bw20 =
1747 + rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1748 + rt2x00dev->calibration_bw40 =
1749 + rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1750 +
1751 + /*
1752 + * Set back to initial state
1753 + */
1754 + rt2800usb_bbp_write(rt2x00dev, 24, 0);
1755 +
1756 + rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1757 + rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1758 + rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1759 +
1760 + /*
1761 + * set BBP back to BW20
1762 + */
1763 + rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1764 + rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1765 + rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1766 +
1767 + return 0;
1768 +}
1769 +
1770 +/*
1771 + * Device state switch handlers.
1772 + */
1773 +static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1774 + enum dev_state state)
1775 +{
1776 + u32 reg;
1777 +
1778 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1779 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1780 + (state == STATE_RADIO_RX_ON) ||
1781 + (state == STATE_RADIO_RX_ON_LINK));
1782 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1783 +}
1784 +
1785 +static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1786 +{
1787 + unsigned int i;
1788 + u32 reg;
1789 +
1790 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1791 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1792 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1793 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1794 + return 0;
1795 +
1796 + msleep(1);
1797 + }
1798 +
1799 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1800 + return -EACCES;
1801 +}
1802 +
1803 +static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1804 +{
1805 + u32 reg;
1806 + u16 word;
1807 +
1808 + /*
1809 + * Initialize all registers.
1810 + */
1811 + if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1812 + rt2800usb_init_registers(rt2x00dev) ||
1813 + rt2800usb_init_bbp(rt2x00dev) ||
1814 + rt2800usb_init_rfcsr(rt2x00dev)))
1815 + return -EIO;
1816 +
1817 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1818 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1819 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1820 +
1821 + udelay(50);
1822 +
1823 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1824 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1825 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1826 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1827 + rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1828 +
1829 +
1830 + rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1831 + rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1832 + /* Don't use bulk in aggregation when working with USB 1.1 */
1833 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1834 + (rt2x00dev->rx->usb_maxpacket == 512));
1835 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1836 + /* FIXME: Calculate this value based on Aggregation defines */
1837 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT, 21);
1838 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1839 + rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1840 + rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
1841 +
1842 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1843 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1844 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1845 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1846 +
1847 + /*
1848 + * Send signal to firmware during boot time.
1849 + */
1850 + rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1851 +
1852 + /*
1853 + * Initialize LED control
1854 + */
1855 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1856 + rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1857 + word & 0xff, (word >> 8) & 0xff);
1858 +
1859 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1860 + rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1861 + word & 0xff, (word >> 8) & 0xff);
1862 +
1863 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1864 + rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1865 + word & 0xff, (word >> 8) & 0xff);
1866 +
1867 + return 0;
1868 +}
1869 +
1870 +static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1871 +{
1872 + u32 reg;
1873 +
1874 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1875 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1876 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1877 + rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1878 +
1879 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1880 + rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1881 + rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
1882 +
1883 + /* Wait for DMA, ignore error */
1884 + rt2800usb_wait_wpdma_ready(rt2x00dev);
1885 +
1886 + rt2x00usb_disable_radio(rt2x00dev);
1887 +}
1888 +
1889 +static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1890 + enum dev_state state)
1891 +{
1892 + rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1893 +
1894 + if (state == STATE_AWAKE)
1895 + rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1896 + else
1897 + rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1898 +
1899 + return 0;
1900 +}
1901 +
1902 +static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1903 + enum dev_state state)
1904 +{
1905 + int retval = 0;
1906 +
1907 + switch (state) {
1908 + case STATE_RADIO_ON:
1909 + /*
1910 + * Before the radio can be enabled, the device first has
1911 + * to be woken up. After that it needs a bit of time
1912 + * to be fully awake and the radio can be enabled.
1913 + */
1914 + rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1915 + msleep(1);
1916 + retval = rt2800usb_enable_radio(rt2x00dev);
1917 + break;
1918 + case STATE_RADIO_OFF:
1919 + /*
1920 + * After the radio has been disablee, the device should
1921 + * be put to sleep for powersaving.
1922 + */
1923 + rt2800usb_disable_radio(rt2x00dev);
1924 + rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1925 + break;
1926 + case STATE_RADIO_RX_ON:
1927 + case STATE_RADIO_RX_ON_LINK:
1928 + case STATE_RADIO_RX_OFF:
1929 + case STATE_RADIO_RX_OFF_LINK:
1930 + rt2800usb_toggle_rx(rt2x00dev, state);
1931 + break;
1932 + case STATE_RADIO_IRQ_ON:
1933 + case STATE_RADIO_IRQ_OFF:
1934 + /* No support, but no error either */
1935 + break;
1936 + case STATE_DEEP_SLEEP:
1937 + case STATE_SLEEP:
1938 + case STATE_STANDBY:
1939 + case STATE_AWAKE:
1940 + retval = rt2800usb_set_state(rt2x00dev, state);
1941 + break;
1942 + default:
1943 + retval = -ENOTSUPP;
1944 + break;
1945 + }
1946 +
1947 + if (unlikely(retval))
1948 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1949 + state, retval);
1950 +
1951 + return retval;
1952 +}
1953 +
1954 +/*
1955 + * TX descriptor initialization
1956 + */
1957 +static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1958 + struct sk_buff *skb,
1959 + struct txentry_desc *txdesc)
1960 +{
1961 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1962 + __le32 *txi = skbdesc->desc;
1963 + __le32 *txwi = txi + TXINFO_DESC_SIZE;
1964 + u32 word;
1965 +
1966 + /*
1967 + * Initialize TX Info descriptor
1968 + */
1969 + rt2x00_desc_read(txwi, 0, &word);
1970 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
1971 + test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags) ||
1972 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1973 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1974 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1975 + rt2x00_set_field32(&word, TXWI_W0_TS,
1976 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1977 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1978 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1979 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1980 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1981 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1982 + rt2x00_set_field32(&word, TXWI_W0_BW,
1983 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1984 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1985 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1986 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1987 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1988 + rt2x00_desc_write(txwi, 0, word);
1989 +
1990 + rt2x00_desc_read(txwi, 1, &word);
1991 + rt2x00_set_field32(&word, TXWI_W1_ACK,
1992 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1993 + rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1994 + test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1995 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1996 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 0xff);
1997 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
1998 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1999 + skbdesc->entry->entry_idx);
2000 + rt2x00_desc_write(txwi, 1, word);
2001 +
2002 + if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
2003 + _rt2x00_desc_write(txwi, 2, skbdesc->iv[0]);
2004 + _rt2x00_desc_write(txwi, 3, skbdesc->iv[1]);
2005 + }
2006 +
2007 + /*
2008 + * Initialize TX descriptor
2009 + */
2010 + rt2x00_desc_read(txi, 0, &word);
2011 + rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2012 + roundup(skb->len + TXWI_DESC_SIZE, 4));
2013 + rt2x00_set_field32(&word, TXINFO_W0_WIV, 1);
2014 + rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2015 + rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2016 + rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2017 + rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2018 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2019 + rt2x00_desc_write(txi, 0, word);
2020 +}
2021 +
2022 +/*
2023 + * TX data initialization
2024 + */
2025 +static void rt2800usb_write_beacon(struct queue_entry *entry)
2026 +{
2027 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2028 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2029 + unsigned int beacon_base;
2030 + u32 reg;
2031 +
2032 + /*
2033 + * Add the descriptor in front of the skb.
2034 + */
2035 + skb_push(entry->skb, entry->queue->desc_size);
2036 + memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2037 + skbdesc->desc = entry->skb->data;
2038 +
2039 + /*
2040 + * Disable beaconing while we are reloading the beacon data,
2041 + * otherwise we might be sending out invalid data.
2042 + */
2043 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2044 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2045 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2046 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2047 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2048 +
2049 + /*
2050 + * Write entire beacon with descriptor to register.
2051 + */
2052 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2053 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2054 + USB_VENDOR_REQUEST_OUT, beacon_base,
2055 + entry->skb->data, entry->skb->len,
2056 + REGISTER_TIMEOUT32(entry->skb->len));
2057 +
2058 + /*
2059 + * Clean up the beacon skb.
2060 + */
2061 + dev_kfree_skb(entry->skb);
2062 + entry->skb = NULL;
2063 +}
2064 +
2065 +static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2066 +{
2067 + int length;
2068 +
2069 + /*
2070 + * The length _must_ be a multiple of 4,
2071 + * but it must _not_ be a multiple of the USB packet size.
2072 + */
2073 + length = roundup(entry->skb->len, 4);
2074 + length += (4 * !(length % entry->queue->usb_maxpacket));
2075 +
2076 + return length;
2077 +}
2078 +
2079 +static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2080 + const enum data_queue_qid queue)
2081 +{
2082 + u32 reg;
2083 +
2084 + if (queue != QID_BEACON) {
2085 + rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2086 + return;
2087 + }
2088 +
2089 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2090 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2091 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2092 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2093 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2094 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2095 + }
2096 +}
2097 +
2098 +/*
2099 + * RX control handlers
2100 + */
2101 +static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2102 + struct rxdone_entry_desc *rxdesc)
2103 +{
2104 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2105 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2106 + __le32 *rxd = (__le32 *)entry->skb->data;
2107 + __le32 *rxwi = (__le32 *)(entry->skb->data + skbdesc->desc_len);
2108 + u32 rxd0;
2109 + u32 rxwi0;
2110 + u32 rxwi1;
2111 + u32 rxwi2;
2112 + u32 rxwi3;
2113 +
2114 + /*
2115 + * Copy descriptor to the skbdesc->desc buffer, making it safe from
2116 + * moving of frame data in rt2x00usb.
2117 + */
2118 + memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2119 + rxd = (__le32 *)skbdesc->desc;
2120 +
2121 + /*
2122 + * It is now safe to read the descriptor on all architectures.
2123 + */
2124 + rt2x00_desc_read(rxd, 0, &rxd0);
2125 + rt2x00_desc_read(rxwi, 0, &rxwi0);
2126 + rt2x00_desc_read(rxwi, 1, &rxwi1);
2127 + rt2x00_desc_read(rxwi, 2, &rxwi2);
2128 + rt2x00_desc_read(rxwi, 3, &rxwi3);
2129 +
2130 + if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2131 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2132 +
2133 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2134 + /*
2135 + * Unfortunately we don't know the cipher type used during
2136 + * decryption. This prevents us from correct providing
2137 + * correct statistics through debugfs.
2138 + */
2139 + rxdesc->cipher = CIPHER_NONE;
2140 + rxdesc->cipher_status =
2141 + rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2142 + }
2143 +
2144 + if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2145 + /*
2146 + * Hardware has stripped IV/EIV data from 802.11 frame during
2147 + * decryption. Unfortunately the descriptor doesn't contain
2148 + * any fields with the EIV/IV data either, so they can't
2149 + * be restored by rt2x00lib.
2150 + */
2151 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2152 +
2153 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2154 + rxdesc->flags |= RX_FLAG_DECRYPTED;
2155 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2156 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2157 + }
2158 +
2159 + if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2160 + rxdesc->dev_flags |= RXDONE_MY_BSS;
2161 +
2162 + if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2163 + rxdesc->flags |= RX_FLAG_SHORT_GI;
2164 +
2165 + if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2166 + rxdesc->flags |= RX_FLAG_40MHZ;
2167 +
2168 + /*
2169 + * Detect RX rate, always use MCS as signal type.
2170 + */
2171 + rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2172 + rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2173 + rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2174 +
2175 + /*
2176 + * Mask of 0x8 bit to remove the short preamble flag.
2177 + */
2178 + if (rxdesc->dev_flags == RATE_MODE_CCK)
2179 + rxdesc->signal &= ~0x8;
2180 +
2181 + rxdesc->rssi =
2182 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2183 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1) +
2184 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI2)) / 3;
2185 +
2186 + rxdesc->noise =
2187 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2188 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2189 +
2190 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2191 +
2192 + /*
2193 + * Remove RXWI descriptor from start of buffer.
2194 + */
2195 + skb_pull(entry->skb, RXWI_DESC_SIZE + skbdesc->desc_len);
2196 + skb_trim(entry->skb, rxdesc->size);
2197 +}
2198 +
2199 +/*
2200 + * Device probe functions.
2201 + */
2202 +static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2203 +{
2204 + u16 word;
2205 + u8 *mac;
2206 + u8 default_lna_gain;
2207 +
2208 + rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2209 +
2210 + /*
2211 + * Start validation of the data that has been read.
2212 + */
2213 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2214 + if (!is_valid_ether_addr(mac)) {
2215 + DECLARE_MAC_BUF(macbuf);
2216 +
2217 + random_ether_addr(mac);
2218 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2219 + }
2220 +
2221 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2222 + if (word == 0xffff) {
2223 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2224 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2225 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2226 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2227 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2228 + }
2229 +
2230 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2231 + if (word == 0xffff) {
2232 + rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2233 + rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2234 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2235 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2236 + rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2237 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2238 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2239 + rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2240 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2241 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2242 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2243 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2244 + }
2245 +
2246 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2247 + if ((word & 0x00ff) == 0x00ff) {
2248 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2249 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2250 + LED_MODE_TXRX_ACTIVITY);
2251 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2252 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2253 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2254 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2255 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2256 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2257 + }
2258 +
2259 + /*
2260 + * During the LNA validation we are going to use
2261 + * lna0 as correct value. Note that EEPROM_LNA
2262 + * is never validated.
2263 + */
2264 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2265 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2266 +
2267 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2268 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2269 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2270 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2271 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2272 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2273 +
2274 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2275 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2276 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2277 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2278 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2279 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2280 + default_lna_gain);
2281 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2282 +
2283 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2284 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2285 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2286 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2287 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2288 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2289 +
2290 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2291 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2292 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2293 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2294 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2295 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2296 + default_lna_gain);
2297 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2298 +
2299 + return 0;
2300 +}
2301 +
2302 +static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2303 +{
2304 + u32 reg;
2305 + u16 value;
2306 + u16 eeprom;
2307 +
2308 + /*
2309 + * Read EEPROM word for configuration.
2310 + */
2311 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2312 +
2313 + /*
2314 + * Identify RF chipset.
2315 + */
2316 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2317 + rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
2318 + rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2319 +
2320 + /*
2321 + * The check for rt2860 is not a typo, some rt2870 hardware
2322 + * identifies itself as rt2860 in the CSR register.
2323 + */
2324 + if ((rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2860) &&
2325 + (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2870)) {
2326 + ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2327 + return -ENODEV;
2328 + }
2329 +
2330 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2331 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2332 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2333 + !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2334 + !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2335 + !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2336 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2337 + return -ENODEV;
2338 + }
2339 +
2340 + /*
2341 + * Read frequency offset and RF programming sequence.
2342 + */
2343 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2344 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2345 +
2346 + /*
2347 + * Read external LNA informations.
2348 + */
2349 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2350 +
2351 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2352 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2353 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2354 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2355 +
2356 + /*
2357 + * Detect if this device has an hardware controlled radio.
2358 + */
2359 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2360 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2361 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2362 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2363 +
2364 + /*
2365 + * Store led settings, for correct led behaviour.
2366 + */
2367 +#ifdef CONFIG_RT2X00_LIB_LEDS
2368 + rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2369 + rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2370 + rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2371 +
2372 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2373 + &rt2x00dev->led_mcu_reg);
2374 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2375 +
2376 + return 0;
2377 +}
2378 +
2379 +/*
2380 + * RF value list for rt2870
2381 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2382 + */
2383 +static const struct rf_channel rf_vals[] = {
2384 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2385 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2386 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2387 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2388 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2389 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2390 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2391 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2392 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2393 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2394 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2395 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2396 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2397 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2398 +
2399 + /* 802.11 UNI / HyperLan 2 */
2400 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2401 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2402 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2403 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2404 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2405 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2406 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2407 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2408 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2409 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2410 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2411 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2412 +
2413 + /* 802.11 HyperLan 2 */
2414 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2415 + { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2416 + { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
2417 + { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
2418 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2419 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2420 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2421 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2422 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2423 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2424 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2425 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2426 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2427 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2428 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2429 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2430 +
2431 + /* 802.11 UNII */
2432 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2433 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2434 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2435 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2436 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2437 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2438 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2439 +
2440 + /* 802.11 Japan */
2441 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2442 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2443 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2444 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2445 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2446 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2447 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2448 +};
2449 +
2450 +/*
2451 + * RF value list for rt3070
2452 + * Supports: 2.4 GHz
2453 + */
2454 +static const struct rf_channel rf_vals_3070[] = {
2455 + {1, 241, 2, 2 },
2456 + {2, 241, 2, 7 },
2457 + {3, 242, 2, 2 },
2458 + {4, 242, 2, 7 },
2459 + {5, 243, 2, 2 },
2460 + {6, 243, 2, 7 },
2461 + {7, 244, 2, 2 },
2462 + {8, 244, 2, 7 },
2463 + {9, 245, 2, 2 },
2464 + {10, 245, 2, 7 },
2465 + {11, 246, 2, 2 },
2466 + {12, 246, 2, 7 },
2467 + {13, 247, 2, 2 },
2468 + {14, 248, 2, 4 },
2469 +};
2470 +
2471 +static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2472 +{
2473 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2474 + struct channel_info *info;
2475 + char *tx_power1;
2476 + char *tx_power2;
2477 + unsigned int i;
2478 +
2479 + /*
2480 + * Initialize all hw fields.
2481 + */
2482 + rt2x00dev->hw->flags =
2483 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2484 + IEEE80211_HW_SIGNAL_DBM |
2485 + IEEE80211_HW_SUPPORTS_PS |
2486 + IEEE80211_HW_PS_NULLFUNC_STACK;
2487 + rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2488 +
2489 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2490 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2491 + rt2x00_eeprom_addr(rt2x00dev,
2492 + EEPROM_MAC_ADDR_0));
2493 +
2494 + /*
2495 + * Initialize HT information.
2496 + */
2497 + spec->ht.ht_supported = true;
2498 + spec->ht.cap =
2499 + IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2500 + IEEE80211_HT_CAP_GRN_FLD |
2501 + IEEE80211_HT_CAP_SGI_20 |
2502 + IEEE80211_HT_CAP_SGI_40 |
2503 + IEEE80211_HT_CAP_TX_STBC |
2504 + IEEE80211_HT_CAP_RX_STBC |
2505 + IEEE80211_HT_CAP_PSMP_SUPPORT;
2506 + spec->ht.ampdu_factor = 3;
2507 + spec->ht.ampdu_density = 4;
2508 + spec->ht.mcs.rx_mask[0] = 0xff;
2509 + spec->ht.mcs.rx_mask[1] = 0xff;
2510 + spec->ht.mcs.tx_params =
2511 + IEEE80211_HT_MCS_TX_DEFINED;
2512 +
2513 + /*
2514 + * Initialize hw_mode information.
2515 + */
2516 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2517 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2518 +
2519 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2520 + rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2521 + spec->num_channels = 14;
2522 + spec->channels = rf_vals;
2523 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2524 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2525 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2526 + spec->num_channels = ARRAY_SIZE(rf_vals);
2527 + spec->channels = rf_vals;
2528 + } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2529 + rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2530 + spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2531 + spec->channels = rf_vals_3070;
2532 + }
2533 +
2534 + /*
2535 + * Create channel information array
2536 + */
2537 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2538 + if (!info)
2539 + return -ENOMEM;
2540 +
2541 + spec->channels_info = info;
2542 +
2543 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2544 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2545 +
2546 + for (i = 0; i < 14; i++) {
2547 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2548 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2549 + }
2550 +
2551 + if (spec->num_channels > 14) {
2552 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2553 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2554 +
2555 + for (i = 14; i < spec->num_channels; i++) {
2556 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2557 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2558 + }
2559 + }
2560 +
2561 + return 0;
2562 +}
2563 +
2564 +static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2565 +{
2566 + int retval;
2567 +
2568 + /*
2569 + * Allocate eeprom data.
2570 + */
2571 + retval = rt2800usb_validate_eeprom(rt2x00dev);
2572 + if (retval)
2573 + return retval;
2574 +
2575 + retval = rt2800usb_init_eeprom(rt2x00dev);
2576 + if (retval)
2577 + return retval;
2578 +
2579 + /*
2580 + * Initialize hw specifications.
2581 + */
2582 + retval = rt2800usb_probe_hw_mode(rt2x00dev);
2583 + if (retval)
2584 + return retval;
2585 +
2586 + /*
2587 + * This device requires firmware.
2588 + */
2589 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2590 + __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2591 + if (!modparam_nohwcrypt)
2592 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2593 +
2594 + /*
2595 + * Set the rssi offset.
2596 + */
2597 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2598 +
2599 + return 0;
2600 +}
2601 +
2602 +/*
2603 + * IEEE80211 stack callback functions.
2604 + */
2605 +static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2606 +{
2607 + struct rt2x00_dev *rt2x00dev = hw->priv;
2608 + u32 reg;
2609 + bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2610 +
2611 + rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2612 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2613 + rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2614 +
2615 + rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2616 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2617 + rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2618 +
2619 + rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2620 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2621 + rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2622 +
2623 + rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2624 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2625 + rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2626 +
2627 + rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2628 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2629 + rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2630 +
2631 + rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2632 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2633 + rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2634 +
2635 + rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2636 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2637 + rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2638 +
2639 + return 0;
2640 +}
2641 +
2642 +static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2643 + const struct ieee80211_tx_queue_params *params)
2644 +{
2645 + struct rt2x00_dev *rt2x00dev = hw->priv;
2646 + struct data_queue *queue;
2647 + struct rt2x00_field32 field;
2648 + int retval;
2649 + u32 reg;
2650 + u32 offset;
2651 +
2652 + /*
2653 + * First pass the configuration through rt2x00lib, that will
2654 + * update the queue settings and validate the input. After that
2655 + * we are free to update the registers based on the value
2656 + * in the queue parameter.
2657 + */
2658 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2659 + if (retval)
2660 + return retval;
2661 +
2662 + /*
2663 + * We only need to perform additional register initialization
2664 + * for WMM queues/
2665 + */
2666 + if (queue_idx >= 4)
2667 + return 0;
2668 +
2669 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2670 +
2671 + /* Update WMM TXOP register */
2672 + offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2673 + field.bit_offset = (queue_idx & 1) * 16;
2674 + field.bit_mask = 0xffff << field.bit_offset;
2675 +
2676 + rt2x00usb_register_read(rt2x00dev, offset, &reg);
2677 + rt2x00_set_field32(&reg, field, queue->txop);
2678 + rt2x00usb_register_write(rt2x00dev, offset, reg);
2679 +
2680 + /* Update WMM registers */
2681 + field.bit_offset = queue_idx * 4;
2682 + field.bit_mask = 0xf << field.bit_offset;
2683 +
2684 + rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2685 + rt2x00_set_field32(&reg, field, queue->aifs);
2686 + rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2687 +
2688 + rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2689 + rt2x00_set_field32(&reg, field, queue->cw_min);
2690 + rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2691 +
2692 + rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2693 + rt2x00_set_field32(&reg, field, queue->cw_max);
2694 + rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2695 +
2696 + /* Update EDCA registers */
2697 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2698 +
2699 + rt2x00usb_register_read(rt2x00dev, offset, &reg);
2700 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2701 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2702 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2703 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2704 + rt2x00usb_register_write(rt2x00dev, offset, reg);
2705 +
2706 + return 0;
2707 +}
2708 +
2709 +#if 0
2710 +/*
2711 + * Mac80211 demands get_tsf must be atomic.
2712 + * This is not possible for rt2800usb since all register access
2713 + * functions require sleeping. Untill mac80211 no longer needs
2714 + * get_tsf to be atomic, this function should be disabled.
2715 + */
2716 +static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2717 +{
2718 + struct rt2x00_dev *rt2x00dev = hw->priv;
2719 + u64 tsf;
2720 + u32 reg;
2721 +
2722 + rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2723 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2724 + rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2725 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2726 +
2727 + return tsf;
2728 +}
2729 +#else
2730 +#define rt2800usb_get_tsf NULL
2731 +#endif
2732 +
2733 +static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2734 + .tx = rt2x00mac_tx,
2735 + .start = rt2x00mac_start,
2736 + .stop = rt2x00mac_stop,
2737 + .add_interface = rt2x00mac_add_interface,
2738 + .remove_interface = rt2x00mac_remove_interface,
2739 + .config = rt2x00mac_config,
2740 + .config_interface = rt2x00mac_config_interface,
2741 + .configure_filter = rt2x00mac_configure_filter,
2742 + .set_key = rt2x00mac_set_key,
2743 + .get_stats = rt2x00mac_get_stats,
2744 + .set_rts_threshold = rt2800usb_set_rts_threshold,
2745 + .bss_info_changed = rt2x00mac_bss_info_changed,
2746 + .conf_tx = rt2800usb_conf_tx,
2747 + .get_tx_stats = rt2x00mac_get_tx_stats,
2748 + .get_tsf = rt2800usb_get_tsf,
2749 +};
2750 +
2751 +static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2752 + .probe_hw = rt2800usb_probe_hw,
2753 + .get_firmware_name = rt2800usb_get_firmware_name,
2754 + .get_firmware_crc = rt2800usb_get_firmware_crc,
2755 + .load_firmware = rt2800usb_load_firmware,
2756 + .initialize = rt2x00usb_initialize,
2757 + .uninitialize = rt2x00usb_uninitialize,
2758 + .clear_entry = rt2x00usb_clear_entry,
2759 + .set_device_state = rt2800usb_set_device_state,
2760 + .rfkill_poll = rt2800usb_rfkill_poll,
2761 + .link_stats = rt2800usb_link_stats,
2762 + .reset_tuner = rt2800usb_reset_tuner,
2763 + .link_tuner = rt2800usb_link_tuner,
2764 + .write_tx_desc = rt2800usb_write_tx_desc,
2765 + .write_tx_data = rt2x00usb_write_tx_data,
2766 + .write_beacon = rt2800usb_write_beacon,
2767 + .get_tx_data_len = rt2800usb_get_tx_data_len,
2768 + .kick_tx_queue = rt2800usb_kick_tx_queue,
2769 + .fill_rxdone = rt2800usb_fill_rxdone,
2770 + .config_shared_key = rt2800usb_config_shared_key,
2771 + .config_pairwise_key = rt2800usb_config_pairwise_key,
2772 + .config_filter = rt2800usb_config_filter,
2773 + .config_intf = rt2800usb_config_intf,
2774 + .config_erp = rt2800usb_config_erp,
2775 + .config_ant = rt2800usb_config_ant,
2776 + .config = rt2800usb_config,
2777 +};
2778 +
2779 +static const struct data_queue_desc rt2800usb_queue_rx = {
2780 + .entry_num = RX_ENTRIES,
2781 + .data_size = DATA_FRAME_SIZE,
2782 + .desc_size = RXD_DESC_SIZE,
2783 + .priv_size = sizeof(struct queue_entry_priv_usb),
2784 +};
2785 +
2786 +static const struct data_queue_desc rt2800usb_queue_tx = {
2787 + .entry_num = TX_ENTRIES,
2788 + .data_size = DATA_FRAME_SIZE,
2789 + .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2790 + .priv_size = sizeof(struct queue_entry_priv_usb),
2791 +};
2792 +
2793 +static const struct data_queue_desc rt2800usb_queue_bcn = {
2794 + .entry_num = 8 * BEACON_ENTRIES,
2795 + .data_size = MGMT_FRAME_SIZE,
2796 + .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2797 + .priv_size = sizeof(struct queue_entry_priv_usb),
2798 +};
2799 +
2800 +static const struct rt2x00_ops rt2800usb_ops = {
2801 + .name = KBUILD_MODNAME,
2802 + .max_sta_intf = 1,
2803 + .max_ap_intf = 8,
2804 + .eeprom_size = EEPROM_SIZE,
2805 + .rf_size = RF_SIZE,
2806 + .tx_queues = NUM_TX_QUEUES,
2807 + .rx = &rt2800usb_queue_rx,
2808 + .tx = &rt2800usb_queue_tx,
2809 + .bcn = &rt2800usb_queue_bcn,
2810 + .lib = &rt2800usb_rt2x00_ops,
2811 + .hw = &rt2800usb_mac80211_ops,
2812 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2813 + .debugfs = &rt2800usb_rt2x00debug,
2814 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2815 +};
2816 +
2817 +/*
2818 + * rt2800usb module information.
2819 + */
2820 +static struct usb_device_id rt2800usb_device_table[] = {
2821 + /* Abocom */
2822 + { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2823 + { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2824 + { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2825 + { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2826 + { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2827 + /* Amit */
2828 + { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2829 + /* ASUS */
2830 + { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2831 + { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2832 + { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2833 + /* AzureWave */
2834 + { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2835 + /* Belkin */
2836 + { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2837 + { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2838 + /* Conceptronic */
2839 + { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2840 + { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2841 + { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2842 + { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2843 + { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2844 + { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2845 + { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2846 + { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2847 + /* Corega */
2848 + { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2849 + { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2850 + { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2851 + { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2852 + /* D-Link */
2853 + { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2854 + { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2855 + /* Edimax */
2856 + { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2857 + /* EnGenius */
2858 + { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2859 + { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2860 + /* Gigabyte */
2861 + { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2862 + /* Hawking */
2863 + { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2864 + { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2865 + /* Linksys */
2866 + { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2867 + /* Logitec */
2868 + { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2869 + { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2870 + { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2871 + /* Philips */
2872 + { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2873 + /* Planex */
2874 + { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2875 + { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
2876 + /* Ralink */
2877 + { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2878 + { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2879 + { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2880 + /* Samsung */
2881 + { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
2882 + /* Siemens */
2883 + { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
2884 + /* Sitecom */
2885 + { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
2886 + { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
2887 + { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
2888 + { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
2889 + /* SMC */
2890 + { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
2891 + { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
2892 + { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
2893 + { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
2894 + /* Sparklan */
2895 + { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
2896 + /* U-Media*/
2897 + { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
2898 + /* ZCOM */
2899 + { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
2900 + { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
2901 + /* Zinwell */
2902 + { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
2903 + { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
2904 + /* Zyxel */
2905 + { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
2906 + { 0, }
2907 +};
2908 +
2909 +MODULE_AUTHOR(DRV_PROJECT);
2910 +MODULE_VERSION(DRV_VERSION);
2911 +MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
2912 +MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
2913 +MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
2914 +MODULE_FIRMWARE(FIRMWARE_RT2870);
2915 +MODULE_LICENSE("GPL");
2916 +
2917 +static struct usb_driver rt2800usb_driver = {
2918 + .name = KBUILD_MODNAME,
2919 + .id_table = rt2800usb_device_table,
2920 + .probe = rt2x00usb_probe,
2921 + .disconnect = rt2x00usb_disconnect,
2922 + .suspend = rt2x00usb_suspend,
2923 + .resume = rt2x00usb_resume,
2924 +};
2925 +
2926 +static int __init rt2800usb_init(void)
2927 +{
2928 + return usb_register(&rt2800usb_driver);
2929 +}
2930 +
2931 +static void __exit rt2800usb_exit(void)
2932 +{
2933 + usb_deregister(&rt2800usb_driver);
2934 +}
2935 +
2936 +module_init(rt2800usb_init);
2937 +module_exit(rt2800usb_exit);
2938 --- /dev/null
2939 +++ b/drivers/net/wireless/rt2x00/rt2800usb.h
2940 @@ -0,0 +1,1944 @@
2941 +/*
2942 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
2943 + <http://rt2x00.serialmonkey.com>
2944 +
2945 + This program is free software; you can redistribute it and/or modify
2946 + it under the terms of the GNU General Public License as published by
2947 + the Free Software Foundation; either version 2 of the License, or
2948 + (at your option) any later version.
2949 +
2950 + This program is distributed in the hope that it will be useful,
2951 + but WITHOUT ANY WARRANTY; without even the implied warranty of
2952 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2953 + GNU General Public License for more details.
2954 +
2955 + You should have received a copy of the GNU General Public License
2956 + along with this program; if not, write to the
2957 + Free Software Foundation, Inc.,
2958 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2959 + */
2960 +
2961 +/*
2962 + Module: rt2800usb
2963 + Abstract: Data structures and registers for the rt2800usb module.
2964 + Supported chipsets: RT2800U.
2965 + */
2966 +
2967 +#ifndef RT2800USB_H
2968 +#define RT2800USB_H
2969 +
2970 +/*
2971 + * RF chip defines.
2972 + *
2973 + * RF2820 2.4G 2T3R
2974 + * RF2850 2.4G/5G 2T3R
2975 + * RF2720 2.4G 1T2R
2976 + * RF2750 2.4G/5G 1T2R
2977 + * RF3020 2.4G 1T1R
2978 + * RF2020 2.4G B/G
2979 + */
2980 +#define RF2820 0x0001
2981 +#define RF2850 0x0002
2982 +#define RF2720 0x0003
2983 +#define RF2750 0x0004
2984 +#define RF3020 0x0005
2985 +#define RF2020 0x0006
2986 +
2987 +/*
2988 + * RT2870 version
2989 + */
2990 +#define RT2860C_VERSION 0x28600100
2991 +#define RT2860D_VERSION 0x28600101
2992 +#define RT2880E_VERSION 0x28720200
2993 +#define RT2883_VERSION 0x28830300
2994 +#define RT3070_VERSION 0x30700200
2995 +
2996 +/*
2997 + * Signal information.
2998 + * Defaul offset is required for RSSI <-> dBm conversion.
2999 + */
3000 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
3001 +
3002 +/*
3003 + * Register layout information.
3004 + */
3005 +#define CSR_REG_BASE 0x1000
3006 +#define CSR_REG_SIZE 0x0800
3007 +#define EEPROM_BASE 0x0000
3008 +#define EEPROM_SIZE 0x0110
3009 +#define BBP_BASE 0x0000
3010 +#define BBP_SIZE 0x0080
3011 +#define RF_BASE 0x0000
3012 +#define RF_SIZE 0x0014
3013 +
3014 +/*
3015 + * Number of TX queues.
3016 + */
3017 +#define NUM_TX_QUEUES 4
3018 +
3019 +/*
3020 + * USB registers.
3021 + */
3022 +
3023 +/*
3024 + * HOST-MCU shared memory
3025 + */
3026 +#define HOST_CMD_CSR 0x0404
3027 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
3028 +
3029 +/*
3030 + * INT_SOURCE_CSR: Interrupt source register.
3031 + * Write one to clear corresponding bit.
3032 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
3033 + */
3034 +#define INT_SOURCE_CSR 0x0200
3035 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
3036 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
3037 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
3038 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
3039 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
3040 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
3041 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
3042 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
3043 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
3044 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
3045 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
3046 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
3047 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
3048 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
3049 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
3050 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
3051 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
3052 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
3053 +
3054 +/*
3055 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
3056 + */
3057 +#define INT_MASK_CSR 0x0204
3058 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
3059 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
3060 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
3061 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
3062 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
3063 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
3064 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
3065 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
3066 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
3067 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
3068 +#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
3069 +#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
3070 +#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
3071 +#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
3072 +#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
3073 +#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
3074 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
3075 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
3076 +
3077 +/*
3078 + * WPDMA_GLO_CFG
3079 + */
3080 +#define WPDMA_GLO_CFG 0x0208
3081 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
3082 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
3083 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
3084 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
3085 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
3086 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
3087 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
3088 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
3089 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
3090 +
3091 +/*
3092 + * WPDMA_RST_IDX
3093 + */
3094 +#define WPDMA_RST_IDX 0x020c
3095 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
3096 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
3097 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
3098 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
3099 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
3100 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
3101 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
3102 +
3103 +/*
3104 + * DELAY_INT_CFG
3105 + */
3106 +#define DELAY_INT_CFG 0x0210
3107 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
3108 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
3109 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
3110 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
3111 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
3112 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
3113 +
3114 +/*
3115 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
3116 + * AIFSN0: AC_BE
3117 + * AIFSN1: AC_BK
3118 + * AIFSN1: AC_VI
3119 + * AIFSN1: AC_VO
3120 + */
3121 +#define WMM_AIFSN_CFG 0x0214
3122 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
3123 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
3124 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
3125 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
3126 +
3127 +/*
3128 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3129 + * CWMIN0: AC_BE
3130 + * CWMIN1: AC_BK
3131 + * CWMIN1: AC_VI
3132 + * CWMIN1: AC_VO
3133 + */
3134 +#define WMM_CWMIN_CFG 0x0218
3135 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
3136 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
3137 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
3138 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
3139 +
3140 +/*
3141 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3142 + * CWMAX0: AC_BE
3143 + * CWMAX1: AC_BK
3144 + * CWMAX1: AC_VI
3145 + * CWMAX1: AC_VO
3146 + */
3147 +#define WMM_CWMAX_CFG 0x021c
3148 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
3149 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
3150 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
3151 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
3152 +
3153 +/*
3154 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3155 + * AC0TXOP: AC_BK in unit of 32us
3156 + * AC1TXOP: AC_BE in unit of 32us
3157 + */
3158 +#define WMM_TXOP0_CFG 0x0220
3159 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
3160 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
3161 +
3162 +/*
3163 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3164 + * AC2TXOP: AC_VI in unit of 32us
3165 + * AC3TXOP: AC_VO in unit of 32us
3166 + */
3167 +#define WMM_TXOP1_CFG 0x0224
3168 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
3169 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
3170 +
3171 +/*
3172 + * RINGREG_DIFF
3173 + */
3174 +#define RINGREG_DIFF 0x0010
3175 +
3176 +/*
3177 + * GPIO_CTRL_CFG:
3178 + */
3179 +#define GPIO_CTRL_CFG 0x0228
3180 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
3181 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
3182 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
3183 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
3184 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
3185 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
3186 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
3187 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
3188 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
3189 +
3190 +/*
3191 + * MCU_CMD_CFG
3192 + */
3193 +#define MCU_CMD_CFG 0x022c
3194 +
3195 +/*
3196 + * AC_BK register offsets
3197 + */
3198 +#define TX_BASE_PTR0 0x0230
3199 +#define TX_MAX_CNT0 0x0234
3200 +#define TX_CTX_IDX0 0x0238
3201 +#define TX_DTX_IDX0 0x023c
3202 +
3203 +/*
3204 + * AC_BE register offsets
3205 + */
3206 +#define TX_BASE_PTR1 0x0240
3207 +#define TX_MAX_CNT1 0x0244
3208 +#define TX_CTX_IDX1 0x0248
3209 +#define TX_DTX_IDX1 0x024c
3210 +
3211 +/*
3212 + * AC_VI register offsets
3213 + */
3214 +#define TX_BASE_PTR2 0x0250
3215 +#define TX_MAX_CNT2 0x0254
3216 +#define TX_CTX_IDX2 0x0258
3217 +#define TX_DTX_IDX2 0x025c
3218 +
3219 +/*
3220 + * AC_VO register offsets
3221 + */
3222 +#define TX_BASE_PTR3 0x0260
3223 +#define TX_MAX_CNT3 0x0264
3224 +#define TX_CTX_IDX3 0x0268
3225 +#define TX_DTX_IDX3 0x026c
3226 +
3227 +/*
3228 + * HCCA register offsets
3229 + */
3230 +#define TX_BASE_PTR4 0x0270
3231 +#define TX_MAX_CNT4 0x0274
3232 +#define TX_CTX_IDX4 0x0278
3233 +#define TX_DTX_IDX4 0x027c
3234 +
3235 +/*
3236 + * MGMT register offsets
3237 + */
3238 +#define TX_BASE_PTR5 0x0280
3239 +#define TX_MAX_CNT5 0x0284
3240 +#define TX_CTX_IDX5 0x0288
3241 +#define TX_DTX_IDX5 0x028c
3242 +
3243 +/*
3244 + * RX register offsets
3245 + */
3246 +#define RX_BASE_PTR 0x0290
3247 +#define RX_MAX_CNT 0x0294
3248 +#define RX_CRX_IDX 0x0298
3249 +#define RX_DRX_IDX 0x029c
3250 +
3251 +/*
3252 + * USB_DMA_CFG
3253 + * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
3254 + * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
3255 + * PHY_CLEAR: phy watch dog enable.
3256 + * TX_CLEAR: Clear USB DMA TX path.
3257 + * TXOP_HALT: Halt TXOP count down when TX buffer is full.
3258 + * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
3259 + * RX_BULK_EN: Enable USB DMA Rx.
3260 + * TX_BULK_EN: Enable USB DMA Tx.
3261 + * EP_OUT_VALID: OUT endpoint data valid.
3262 + * RX_BUSY: USB DMA RX FSM busy.
3263 + * TX_BUSY: USB DMA TX FSM busy.
3264 + */
3265 +#define USB_DMA_CFG 0x02a0
3266 +#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
3267 +#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
3268 +#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
3269 +#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
3270 +#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
3271 +#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
3272 +#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
3273 +#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
3274 +#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
3275 +#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
3276 +#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
3277 +
3278 +/*
3279 + * USB_CYC_CFG
3280 + */
3281 +#define USB_CYC_CFG 0x02a4
3282 +#define USB_CYC_CFG_CLOCK_CYCLE FIELD32(0x000000ff)
3283 +
3284 +/*
3285 + * PBF_SYS_CTRL
3286 + * HOST_RAM_WRITE: enable Host program ram write selection
3287 + */
3288 +#define PBF_SYS_CTRL 0x0400
3289 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
3290 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
3291 +
3292 +/*
3293 + * PBF registers
3294 + * Most are for debug. Driver doesn't touch PBF register.
3295 + */
3296 +#define PBF_CFG 0x0408
3297 +#define PBF_MAX_PCNT 0x040c
3298 +#define PBF_CTRL 0x0410
3299 +#define PBF_INT_STA 0x0414
3300 +#define PBF_INT_ENA 0x0418
3301 +
3302 +/*
3303 + * BCN_OFFSET0:
3304 + */
3305 +#define BCN_OFFSET0 0x042c
3306 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
3307 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
3308 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
3309 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
3310 +
3311 +/*
3312 + * BCN_OFFSET1:
3313 + */
3314 +#define BCN_OFFSET1 0x0430
3315 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
3316 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
3317 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
3318 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
3319 +
3320 +/*
3321 + * PBF registers
3322 + * Most are for debug. Driver doesn't touch PBF register.
3323 + */
3324 +#define TXRXQ_PCNT 0x0438
3325 +#define PBF_DBG 0x043c
3326 +
3327 +/*
3328 + * RF registers
3329 + */
3330 +#define RF_CSR_CFG 0x0500
3331 +#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
3332 +#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
3333 +#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
3334 +#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
3335 +
3336 +/*
3337 + * MAC Control/Status Registers(CSR).
3338 + * Some values are set in TU, whereas 1 TU == 1024 us.
3339 + */
3340 +
3341 +/*
3342 + * MAC_CSR0: ASIC revision number.
3343 + * ASIC_REV: 0
3344 + * ASIC_VER: 2870
3345 + */
3346 +#define MAC_CSR0 0x1000
3347 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
3348 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
3349 +
3350 +/*
3351 + * MAC_SYS_CTRL:
3352 + */
3353 +#define MAC_SYS_CTRL 0x1004
3354 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
3355 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
3356 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
3357 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
3358 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
3359 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
3360 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
3361 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
3362 +
3363 +/*
3364 + * MAC_ADDR_DW0: STA MAC register 0
3365 + */
3366 +#define MAC_ADDR_DW0 0x1008
3367 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
3368 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
3369 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
3370 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
3371 +
3372 +/*
3373 + * MAC_ADDR_DW1: STA MAC register 1
3374 + * UNICAST_TO_ME_MASK:
3375 + * Used to mask off bits from byte 5 of the MAC address
3376 + * to determine the UNICAST_TO_ME bit for RX frames.
3377 + * The full mask is complemented by BSS_ID_MASK:
3378 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3379 + */
3380 +#define MAC_ADDR_DW1 0x100c
3381 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3382 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3383 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3384 +
3385 +/*
3386 + * MAC_BSSID_DW0: BSSID register 0
3387 + */
3388 +#define MAC_BSSID_DW0 0x1010
3389 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3390 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3391 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3392 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3393 +
3394 +/*
3395 + * MAC_BSSID_DW1: BSSID register 1
3396 + * BSS_ID_MASK:
3397 + * 0: 1-BSSID mode (BSS index = 0)
3398 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3399 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3400 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3401 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3402 + * BSSID. This will make sure that those bits will be ignored
3403 + * when determining the MY_BSS of RX frames.
3404 + */
3405 +#define MAC_BSSID_DW1 0x1014
3406 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3407 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3408 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3409 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3410 +
3411 +/*
3412 + * MAX_LEN_CFG: Maximum frame length register.
3413 + * MAX_MPDU: rt2860b max 16k bytes
3414 + * MAX_PSDU: Maximum PSDU length
3415 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3416 + */
3417 +#define MAX_LEN_CFG 0x1018
3418 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3419 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3420 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3421 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3422 +
3423 +/*
3424 + * BBP_CSR_CFG: BBP serial control register
3425 + * VALUE: Register value to program into BBP
3426 + * REG_NUM: Selected BBP register
3427 + * READ_CONTROL: 0 write BBP, 1 read BBP
3428 + * BUSY: ASIC is busy executing BBP commands
3429 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3430 + * BBP_RW_MODE: 0 serial, 1 paralell
3431 + */
3432 +#define BBP_CSR_CFG 0x101c
3433 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3434 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3435 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3436 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3437 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3438 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3439 +
3440 +/*
3441 + * RF_CSR_CFG0: RF control register
3442 + * REGID_AND_VALUE: Register value to program into RF
3443 + * BITWIDTH: Selected RF register
3444 + * STANDBYMODE: 0 high when standby, 1 low when standby
3445 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3446 + * BUSY: ASIC is busy executing RF commands
3447 + */
3448 +#define RF_CSR_CFG0 0x1020
3449 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3450 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3451 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3452 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3453 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3454 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3455 +
3456 +/*
3457 + * RF_CSR_CFG1: RF control register
3458 + * REGID_AND_VALUE: Register value to program into RF
3459 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3460 + * 0: 3 system clock cycle (37.5usec)
3461 + * 1: 5 system clock cycle (62.5usec)
3462 + */
3463 +#define RF_CSR_CFG1 0x1024
3464 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3465 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3466 +
3467 +/*
3468 + * RF_CSR_CFG2: RF control register
3469 + * VALUE: Register value to program into RF
3470 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3471 + * 0: 3 system clock cycle (37.5usec)
3472 + * 1: 5 system clock cycle (62.5usec)
3473 + */
3474 +#define RF_CSR_CFG2 0x1028
3475 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3476 +
3477 +/*
3478 + * LED_CFG: LED control
3479 + * color LED's:
3480 + * 0: off
3481 + * 1: blinking upon TX2
3482 + * 2: periodic slow blinking
3483 + * 3: always on
3484 + * LED polarity:
3485 + * 0: active low
3486 + * 1: active high
3487 + */
3488 +#define LED_CFG 0x102c
3489 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3490 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3491 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3492 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3493 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3494 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3495 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3496 +
3497 +/*
3498 + * XIFS_TIME_CFG: MAC timing
3499 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3500 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3501 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3502 + * when MAC doesn't reference BBP signal BBRXEND
3503 + * EIFS: unit 1us
3504 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3505 + *
3506 + */
3507 +#define XIFS_TIME_CFG 0x1100
3508 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3509 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3510 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3511 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3512 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3513 +
3514 +/*
3515 + * BKOFF_SLOT_CFG:
3516 + */
3517 +#define BKOFF_SLOT_CFG 0x1104
3518 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3519 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3520 +
3521 +/*
3522 + * NAV_TIME_CFG:
3523 + */
3524 +#define NAV_TIME_CFG 0x1108
3525 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3526 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3527 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3528 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3529 +
3530 +/*
3531 + * CH_TIME_CFG: count as channel busy
3532 + */
3533 +#define CH_TIME_CFG 0x110c
3534 +
3535 +/*
3536 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3537 + */
3538 +#define PBF_LIFE_TIMER 0x1110
3539 +
3540 +/*
3541 + * BCN_TIME_CFG:
3542 + * BEACON_INTERVAL: in unit of 1/16 TU
3543 + * TSF_TICKING: Enable TSF auto counting
3544 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3545 + * BEACON_GEN: Enable beacon generator
3546 + */
3547 +#define BCN_TIME_CFG 0x1114
3548 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3549 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3550 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3551 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3552 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3553 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3554 +
3555 +/*
3556 + * TBTT_SYNC_CFG:
3557 + */
3558 +#define TBTT_SYNC_CFG 0x1118
3559 +
3560 +/*
3561 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3562 + */
3563 +#define TSF_TIMER_DW0 0x111c
3564 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3565 +
3566 +/*
3567 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3568 + */
3569 +#define TSF_TIMER_DW1 0x1120
3570 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3571 +
3572 +/*
3573 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3574 + */
3575 +#define TBTT_TIMER 0x1124
3576 +
3577 +/*
3578 + * INT_TIMER_CFG:
3579 + */
3580 +#define INT_TIMER_CFG 0x1128
3581 +
3582 +/*
3583 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3584 + */
3585 +#define INT_TIMER_EN 0x112c
3586 +
3587 +/*
3588 + * CH_IDLE_STA: channel idle time
3589 + */
3590 +#define CH_IDLE_STA 0x1130
3591 +
3592 +/*
3593 + * CH_BUSY_STA: channel busy time
3594 + */
3595 +#define CH_BUSY_STA 0x1134
3596 +
3597 +/*
3598 + * MAC_STATUS_CFG:
3599 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3600 + * if 1 or higher one of the 2 registers is busy.
3601 + */
3602 +#define MAC_STATUS_CFG 0x1200
3603 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3604 +
3605 +/*
3606 + * PWR_PIN_CFG:
3607 + */
3608 +#define PWR_PIN_CFG 0x1204
3609 +
3610 +/*
3611 + * AUTOWAKEUP_CFG: Manual power control / status register
3612 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3613 + * AUTOWAKE: 0:sleep, 1:awake
3614 + */
3615 +#define AUTOWAKEUP_CFG 0x1208
3616 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3617 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3618 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3619 +
3620 +/*
3621 + * EDCA_AC0_CFG:
3622 + */
3623 +#define EDCA_AC0_CFG 0x1300
3624 +#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
3625 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3626 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3627 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3628 +
3629 +/*
3630 + * EDCA_AC1_CFG:
3631 + */
3632 +#define EDCA_AC1_CFG 0x1304
3633 +#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
3634 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3635 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3636 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3637 +
3638 +/*
3639 + * EDCA_AC2_CFG:
3640 + */
3641 +#define EDCA_AC2_CFG 0x1308
3642 +#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
3643 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3644 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3645 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3646 +
3647 +/*
3648 + * EDCA_AC3_CFG:
3649 + */
3650 +#define EDCA_AC3_CFG 0x130c
3651 +#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
3652 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3653 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3654 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3655 +
3656 +/*
3657 + * EDCA_TID_AC_MAP:
3658 + */
3659 +#define EDCA_TID_AC_MAP 0x1310
3660 +
3661 +/*
3662 + * TX_PWR_CFG_0:
3663 + */
3664 +#define TX_PWR_CFG_0 0x1314
3665 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3666 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
3667 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
3668 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
3669 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
3670 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
3671 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
3672 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
3673 +
3674 +/*
3675 + * TX_PWR_CFG_1:
3676 + */
3677 +#define TX_PWR_CFG_1 0x1318
3678 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
3679 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
3680 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
3681 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
3682 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
3683 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
3684 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
3685 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
3686 +
3687 +/*
3688 + * TX_PWR_CFG_2:
3689 + */
3690 +#define TX_PWR_CFG_2 0x131c
3691 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
3692 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
3693 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
3694 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
3695 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
3696 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
3697 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
3698 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
3699 +
3700 +/*
3701 + * TX_PWR_CFG_3:
3702 + */
3703 +#define TX_PWR_CFG_3 0x1320
3704 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
3705 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
3706 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
3707 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
3708 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
3709 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
3710 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
3711 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
3712 +
3713 +/*
3714 + * TX_PWR_CFG_4:
3715 + */
3716 +#define TX_PWR_CFG_4 0x1324
3717 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
3718 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
3719 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
3720 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
3721 +
3722 +/*
3723 + * TX_PIN_CFG:
3724 + */
3725 +#define TX_PIN_CFG 0x1328
3726 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
3727 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
3728 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
3729 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
3730 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
3731 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
3732 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
3733 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
3734 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
3735 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
3736 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
3737 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
3738 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
3739 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
3740 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
3741 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
3742 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
3743 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
3744 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
3745 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
3746 +
3747 +/*
3748 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3749 + */
3750 +#define TX_BAND_CFG 0x132c
3751 +#define TX_BAND_CFG_A FIELD32(0x00000002)
3752 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
3753 +
3754 +/*
3755 + * TX_SW_CFG0:
3756 + */
3757 +#define TX_SW_CFG0 0x1330
3758 +
3759 +/*
3760 + * TX_SW_CFG1:
3761 + */
3762 +#define TX_SW_CFG1 0x1334
3763 +
3764 +/*
3765 + * TX_SW_CFG2:
3766 + */
3767 +#define TX_SW_CFG2 0x1338
3768 +
3769 +/*
3770 + * TXOP_THRES_CFG:
3771 + */
3772 +#define TXOP_THRES_CFG 0x133c
3773 +
3774 +/*
3775 + * TXOP_CTRL_CFG:
3776 + */
3777 +#define TXOP_CTRL_CFG 0x1340
3778 +
3779 +/*
3780 + * TX_RTS_CFG:
3781 + * RTS_THRES: unit:byte
3782 + * RTS_FBK_EN: enable rts rate fallback
3783 + */
3784 +#define TX_RTS_CFG 0x1344
3785 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
3786 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
3787 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
3788 +
3789 +/*
3790 + * TX_TIMEOUT_CFG:
3791 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3792 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3793 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3794 + * it is recommended that:
3795 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3796 + */
3797 +#define TX_TIMEOUT_CFG 0x1348
3798 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
3799 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
3800 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
3801 +
3802 +/*
3803 + * TX_RTY_CFG:
3804 + * SHORT_RTY_LIMIT: short retry limit
3805 + * LONG_RTY_LIMIT: long retry limit
3806 + * LONG_RTY_THRE: Long retry threshoold
3807 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3808 + * 0:expired by retry limit, 1: expired by mpdu life timer
3809 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3810 + * 0:expired by retry limit, 1: expired by mpdu life timer
3811 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3812 + */
3813 +#define TX_RTY_CFG 0x134c
3814 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
3815 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
3816 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
3817 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
3818 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
3819 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
3820 +
3821 +/*
3822 + * TX_LINK_CFG:
3823 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3824 + * MFB_ENABLE: TX apply remote MFB 1:enable
3825 + * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
3826 + * 0: not apply remote remote unsolicit (MFS=7)
3827 + * TX_MRQ_EN: MCS request TX enable
3828 + * TX_RDG_EN: RDG TX enable
3829 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3830 + * REMOTE_MFB: remote MCS feedback
3831 + * REMOTE_MFS: remote MCS feedback sequence number
3832 + */
3833 +#define TX_LINK_CFG 0x1350
3834 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
3835 +#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
3836 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3837 +#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
3838 +#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
3839 +#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
3840 +#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
3841 +#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
3842 +
3843 +/*
3844 + * HT_FBK_CFG0:
3845 + */
3846 +#define HT_FBK_CFG0 0x1354
3847 +#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
3848 +#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
3849 +#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
3850 +#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
3851 +#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
3852 +#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
3853 +#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
3854 +#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
3855 +
3856 +/*
3857 + * HT_FBK_CFG1:
3858 + */
3859 +#define HT_FBK_CFG1 0x1358
3860 +#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
3861 +#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
3862 +#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
3863 +#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
3864 +#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
3865 +#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
3866 +#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
3867 +#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
3868 +
3869 +/*
3870 + * LG_FBK_CFG0:
3871 + */
3872 +#define LG_FBK_CFG0 0x135c
3873 +#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
3874 +#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
3875 +#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
3876 +#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
3877 +#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
3878 +#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
3879 +#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
3880 +#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
3881 +
3882 +/*
3883 + * LG_FBK_CFG1:
3884 + */
3885 +#define LG_FBK_CFG1 0x1360
3886 +#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
3887 +#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
3888 +#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
3889 +#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
3890 +
3891 +/*
3892 + * CCK_PROT_CFG: CCK Protection
3893 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
3894 + * PROTECT_CTRL: Protection control frame type for CCK TX
3895 + * 0:none, 1:RTS/CTS, 2:CTS-to-self
3896 + * PROTECT_NAV: TXOP protection type for CCK TX
3897 + * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
3898 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
3899 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
3900 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
3901 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
3902 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
3903 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
3904 + * RTS_TH_EN: RTS threshold enable on CCK TX
3905 + */
3906 +#define CCK_PROT_CFG 0x1364
3907 +#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3908 +#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3909 +#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3910 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3911 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3912 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3913 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3914 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3915 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3916 +#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3917 +
3918 +/*
3919 + * OFDM_PROT_CFG: OFDM Protection
3920 + */
3921 +#define OFDM_PROT_CFG 0x1368
3922 +#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3923 +#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3924 +#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3925 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3926 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3927 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3928 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3929 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3930 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3931 +#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3932 +
3933 +/*
3934 + * MM20_PROT_CFG: MM20 Protection
3935 + */
3936 +#define MM20_PROT_CFG 0x136c
3937 +#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3938 +#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3939 +#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3940 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3941 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3942 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3943 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3944 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3945 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3946 +#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3947 +
3948 +/*
3949 + * MM40_PROT_CFG: MM40 Protection
3950 + */
3951 +#define MM40_PROT_CFG 0x1370
3952 +#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3953 +#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3954 +#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3955 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3956 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3957 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3958 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3959 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3960 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3961 +#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3962 +
3963 +/*
3964 + * GF20_PROT_CFG: GF20 Protection
3965 + */
3966 +#define GF20_PROT_CFG 0x1374
3967 +#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3968 +#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3969 +#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3970 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3971 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3972 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3973 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3974 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3975 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3976 +#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3977 +
3978 +/*
3979 + * GF40_PROT_CFG: GF40 Protection
3980 + */
3981 +#define GF40_PROT_CFG 0x1378
3982 +#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3983 +#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3984 +#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3985 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3986 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3987 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3988 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3989 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3990 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3991 +#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3992 +
3993 +/*
3994 + * EXP_CTS_TIME:
3995 + */
3996 +#define EXP_CTS_TIME 0x137c
3997 +
3998 +/*
3999 + * EXP_ACK_TIME:
4000 + */
4001 +#define EXP_ACK_TIME 0x1380
4002 +
4003 +/*
4004 + * RX_FILTER_CFG: RX configuration register.
4005 + */
4006 +#define RX_FILTER_CFG 0x1400
4007 +#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
4008 +#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
4009 +#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
4010 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
4011 +#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
4012 +#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
4013 +#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
4014 +#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
4015 +#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
4016 +#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
4017 +#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
4018 +#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
4019 +#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
4020 +#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
4021 +#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
4022 +#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
4023 +#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
4024 +
4025 +/*
4026 + * AUTO_RSP_CFG:
4027 + * AUTORESPONDER: 0: disable, 1: enable
4028 + * BAC_ACK_POLICY: 0:long, 1:short preamble
4029 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
4030 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
4031 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
4032 + * DUAL_CTS_EN: Power bit value in control frame
4033 + * ACK_CTS_PSM_BIT:Power bit value in control frame
4034 + */
4035 +#define AUTO_RSP_CFG 0x1404
4036 +#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
4037 +#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
4038 +#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
4039 +#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
4040 +#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
4041 +#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
4042 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
4043 +
4044 +/*
4045 + * LEGACY_BASIC_RATE:
4046 + */
4047 +#define LEGACY_BASIC_RATE 0x1408
4048 +
4049 +/*
4050 + * HT_BASIC_RATE:
4051 + */
4052 +#define HT_BASIC_RATE 0x140c
4053 +
4054 +/*
4055 + * HT_CTRL_CFG:
4056 + */
4057 +#define HT_CTRL_CFG 0x1410
4058 +
4059 +/*
4060 + * SIFS_COST_CFG:
4061 + */
4062 +#define SIFS_COST_CFG 0x1414
4063 +
4064 +/*
4065 + * RX_PARSER_CFG:
4066 + * Set NAV for all received frames
4067 + */
4068 +#define RX_PARSER_CFG 0x1418
4069 +
4070 +/*
4071 + * TX_SEC_CNT0:
4072 + */
4073 +#define TX_SEC_CNT0 0x1500
4074 +
4075 +/*
4076 + * RX_SEC_CNT0:
4077 + */
4078 +#define RX_SEC_CNT0 0x1504
4079 +
4080 +/*
4081 + * CCMP_FC_MUTE:
4082 + */
4083 +#define CCMP_FC_MUTE 0x1508
4084 +
4085 +/*
4086 + * TXOP_HLDR_ADDR0:
4087 + */
4088 +#define TXOP_HLDR_ADDR0 0x1600
4089 +
4090 +/*
4091 + * TXOP_HLDR_ADDR1:
4092 + */
4093 +#define TXOP_HLDR_ADDR1 0x1604
4094 +
4095 +/*
4096 + * TXOP_HLDR_ET:
4097 + */
4098 +#define TXOP_HLDR_ET 0x1608
4099 +
4100 +/*
4101 + * QOS_CFPOLL_RA_DW0:
4102 + */
4103 +#define QOS_CFPOLL_RA_DW0 0x160c
4104 +
4105 +/*
4106 + * QOS_CFPOLL_RA_DW1:
4107 + */
4108 +#define QOS_CFPOLL_RA_DW1 0x1610
4109 +
4110 +/*
4111 + * QOS_CFPOLL_QC:
4112 + */
4113 +#define QOS_CFPOLL_QC 0x1614
4114 +
4115 +/*
4116 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
4117 + */
4118 +#define RX_STA_CNT0 0x1700
4119 +#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
4120 +#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
4121 +
4122 +/*
4123 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
4124 + */
4125 +#define RX_STA_CNT1 0x1704
4126 +#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
4127 +#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
4128 +
4129 +/*
4130 + * RX_STA_CNT2:
4131 + */
4132 +#define RX_STA_CNT2 0x1708
4133 +#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
4134 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
4135 +
4136 +/*
4137 + * TX_STA_CNT0: TX Beacon count
4138 + */
4139 +#define TX_STA_CNT0 0x170c
4140 +#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
4141 +#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
4142 +
4143 +/*
4144 + * TX_STA_CNT1: TX tx count
4145 + */
4146 +#define TX_STA_CNT1 0x1710
4147 +#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
4148 +#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
4149 +
4150 +/*
4151 + * TX_STA_CNT2: TX tx count
4152 + */
4153 +#define TX_STA_CNT2 0x1714
4154 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
4155 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
4156 +
4157 +/*
4158 + * TX_STA_FIFO: TX Result for specific PID status fifo register
4159 + */
4160 +#define TX_STA_FIFO 0x1718
4161 +#define TX_STA_FIFO_B_VALID FIELD32(0x00000001)
4162 +#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
4163 +#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
4164 +#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
4165 +#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
4166 +#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
4167 +#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
4168 +
4169 +/*
4170 + * TX_AGG_CNT: Debug counter
4171 + */
4172 +#define TX_AGG_CNT 0x171c
4173 +#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
4174 +#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
4175 +
4176 +/*
4177 + * TX_AGG_CNT0:
4178 + */
4179 +#define TX_AGG_CNT0 0x1720
4180 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
4181 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
4182 +
4183 +/*
4184 + * TX_AGG_CNT1:
4185 + */
4186 +#define TX_AGG_CNT1 0x1724
4187 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
4188 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
4189 +
4190 +/*
4191 + * TX_AGG_CNT2:
4192 + */
4193 +#define TX_AGG_CNT2 0x1728
4194 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
4195 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
4196 +
4197 +/*
4198 + * TX_AGG_CNT3:
4199 + */
4200 +#define TX_AGG_CNT3 0x172c
4201 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
4202 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
4203 +
4204 +/*
4205 + * TX_AGG_CNT4:
4206 + */
4207 +#define TX_AGG_CNT4 0x1730
4208 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
4209 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
4210 +
4211 +/*
4212 + * TX_AGG_CNT5:
4213 + */
4214 +#define TX_AGG_CNT5 0x1734
4215 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
4216 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
4217 +
4218 +/*
4219 + * TX_AGG_CNT6:
4220 + */
4221 +#define TX_AGG_CNT6 0x1738
4222 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
4223 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
4224 +
4225 +/*
4226 + * TX_AGG_CNT7:
4227 + */
4228 +#define TX_AGG_CNT7 0x173c
4229 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
4230 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
4231 +
4232 +/*
4233 + * MPDU_DENSITY_CNT:
4234 + * TX_ZERO_DEL: TX zero length delimiter count
4235 + * RX_ZERO_DEL: RX zero length delimiter count
4236 + */
4237 +#define MPDU_DENSITY_CNT 0x1740
4238 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
4239 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
4240 +
4241 +/*
4242 + * Security key table memory, base address = 0x1800
4243 + */
4244 +struct hw_pairwise_ta_entry {
4245 + u8 address[6];
4246 + u8 reserved[2];
4247 +} __attribute__ ((packed));
4248 +
4249 +struct wcid_entry {
4250 + u8 rx_ba_bitmat7;
4251 + u8 rx_ba_bitmat0;
4252 + u8 mac[6];
4253 +} __attribute__ ((packed));
4254 +
4255 +struct hw_key_entry {
4256 + u8 key[16];
4257 + u8 tx_mic[8];
4258 + u8 rx_mic[8];
4259 +} __attribute__ ((packed));
4260 +
4261 +/*
4262 + * Security key table memory.
4263 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4264 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4265 + * PAIRWISE_IVEIV_TABLE_BASE: 8-byte * 256-entry
4266 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4267 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4268 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4269 + * SHARED_KEY_MODE_BASE: 32-byte * 16-entry
4270 + */
4271 +#define MAC_WCID_BASE 0x1800
4272 +#define PAIRWISE_KEY_TABLE_BASE 0x4000
4273 +#define PAIRWISE_IVEIV_TABLE_BASE 0x6000
4274 +#define MAC_IVEIV_TABLE_BASE 0x6000
4275 +#define MAC_WCID_ATTRIBUTE_BASE 0x6800
4276 +#define SHARED_KEY_TABLE_BASE 0x6c00
4277 +#define SHARED_KEY_MODE_BASE 0x7000
4278 +
4279 +#define SHARED_KEY_ENTRY(__idx) \
4280 + ( SHARED_KEY_TABLE_BASE + \
4281 + ((__idx) * sizeof(struct hw_key_entry)) )
4282 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4283 + ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4284 +#define PAIRWISE_KEY_ENTRY(__idx) \
4285 + ( PAIRWISE_KEY_TABLE_BASE + \
4286 + ((__idx) * sizeof(struct hw_key_entry)) )
4287 +
4288 +#define MAC_WCID_ENTRY(__idx) \
4289 + ( MAC_WCID_BASE + (2 * sizeof(u32) * (__idx)) )
4290 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4291 + ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4292 +
4293 +/*
4294 + * MAC_WCID_ATTRIBUTE:
4295 + * KEYTAB: 0: shared key table, 1: pairwise key table
4296 + * BSS_IDX: multipleBSS index for the WCID
4297 + */
4298 +#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
4299 +#define MAC_WCID_ATTRIBUTE_PAIRKEY_MODE FIELD32(0x0000000e)
4300 +#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
4301 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
4302 +
4303 +/*
4304 + * SHARED_KEY_MODE:
4305 + */
4306 +#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
4307 +#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
4308 +#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
4309 +#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
4310 +#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
4311 +#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
4312 +#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
4313 +#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
4314 +
4315 +/*
4316 + * HOST-MCU communication
4317 + */
4318 +
4319 +/*
4320 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4321 + */
4322 +#define H2M_MAILBOX_CSR 0x7010
4323 +#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
4324 +#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
4325 +#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
4326 +#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
4327 +
4328 +/*
4329 + * H2M_MAILBOX_CID:
4330 + */
4331 +#define H2M_MAILBOX_CID 0x7014
4332 +
4333 +/*
4334 + * H2M_MAILBOX_STATUS:
4335 + */
4336 +#define H2M_MAILBOX_STATUS 0x701c
4337 +
4338 +/*
4339 + * H2M_INT_SRC:
4340 + */
4341 +#define H2M_INT_SRC 0x7024
4342 +
4343 +/*
4344 + * H2M_BBP_AGENT:
4345 + */
4346 +#define H2M_BBP_AGENT 0x7028
4347 +
4348 +/*
4349 + * MCU_LEDCS: LED control for MCU Mailbox.
4350 + */
4351 +#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
4352 +#define MCU_LEDCS_POLARITY FIELD8(0x01)
4353 +
4354 +/*
4355 + * HW_CS_CTS_BASE:
4356 + * Carrier-sense CTS frame base address.
4357 + * It's where mac stores carrier-sense frame for carrier-sense function.
4358 + */
4359 +#define HW_CS_CTS_BASE 0x7700
4360 +
4361 +/*
4362 + * HW_DFS_CTS_BASE:
4363 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4364 + */
4365 +#define HW_DFS_CTS_BASE 0x7780
4366 +
4367 +/*
4368 + * TXRX control registers - base address 0x3000
4369 + */
4370 +
4371 +/*
4372 + * TXRX_CSR1:
4373 + * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4374 + */
4375 +#define TXRX_CSR1 0x77d0
4376 +
4377 +/*
4378 + * HW_DEBUG_SETTING_BASE:
4379 + * since NULL frame won't be that long (256 byte)
4380 + * We steal 16 tail bytes to save debugging settings
4381 + */
4382 +#define HW_DEBUG_SETTING_BASE 0x77f0
4383 +#define HW_DEBUG_SETTING_BASE2 0x7770
4384 +
4385 +/*
4386 + * HW_BEACON_BASE
4387 + * In order to support maximum 8 MBSS and its maximum length
4388 + * is 512 bytes for each beacon
4389 + * Three section discontinue memory segments will be used.
4390 + * 1. The original region for BCN 0~3
4391 + * 2. Extract memory from FCE table for BCN 4~5
4392 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4393 + * It occupied those memory of wcid 238~253 for BCN 6
4394 + * and wcid 222~237 for BCN 7
4395 + *
4396 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4397 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4398 + */
4399 +#define HW_BEACON_BASE0 0x7800
4400 +#define HW_BEACON_BASE1 0x7a00
4401 +#define HW_BEACON_BASE2 0x7c00
4402 +#define HW_BEACON_BASE3 0x7e00
4403 +#define HW_BEACON_BASE4 0x7200
4404 +#define HW_BEACON_BASE5 0x7400
4405 +#define HW_BEACON_BASE6 0x5dc0
4406 +#define HW_BEACON_BASE7 0x5bc0
4407 +
4408 +#define HW_BEACON_OFFSET(__index) \
4409 + ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4410 + (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4411 + (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4412 +
4413 +/*
4414 + * 8051 firmware image.
4415 + */
4416 +#define FIRMWARE_RT2870 "rt2870.bin"
4417 +#define FIRMWARE_IMAGE_BASE 0x3000
4418 +
4419 +/*
4420 + * BBP registers.
4421 + * The wordsize of the BBP is 8 bits.
4422 + */
4423 +
4424 +/*
4425 + * BBP 1: TX Antenna
4426 + */
4427 +#define BBP1_TX_POWER FIELD8(0x07)
4428 +#define BBP1_TX_ANTENNA FIELD8(0x18)
4429 +
4430 +/*
4431 + * BBP 3: RX Antenna
4432 + */
4433 +#define BBP3_RX_ANTENNA FIELD8(0x18)
4434 +
4435 +/*
4436 + * BBP 4: Bandwidth
4437 + */
4438 +#define BBP4_BANDWIDTH FIELD8(0x18)
4439 +
4440 +/*
4441 + * RFCSR registers
4442 + * The wordsize of the RFCSR is 8 bits.
4443 + */
4444 +
4445 +/*
4446 + * RFCSR 6:
4447 + */
4448 +#define RFCSR6_R FIELD8(0x03)
4449 +
4450 +/*
4451 + * RFCSR 7:
4452 + */
4453 +#define RFCSR7_RF_TUNING FIELD8(0x01)
4454 +
4455 +/*
4456 + * RFCSR 12:
4457 + */
4458 +#define RFCSR12_TX_POWER FIELD8(0x1f)
4459 +
4460 +/*
4461 + * RFCSR 22:
4462 + */
4463 +#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
4464 +
4465 +/*
4466 + * RFCSR 23:
4467 + */
4468 +#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
4469 +
4470 +/*
4471 + * RFCSR 30:
4472 + */
4473 +#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
4474 +
4475 +/*
4476 + * RF registers
4477 + */
4478 +
4479 +/*
4480 + * RF 2
4481 + */
4482 +#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
4483 +#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
4484 +#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
4485 +
4486 +/*
4487 + * RF 3
4488 + */
4489 +#define RF3_TXPOWER_G FIELD32(0x00003e00)
4490 +#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
4491 +#define RF3_TXPOWER_A FIELD32(0x00003c00)
4492 +
4493 +/*
4494 + * RF 4
4495 + */
4496 +#define RF4_TXPOWER_G FIELD32(0x000007c0)
4497 +#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
4498 +#define RF4_TXPOWER_A FIELD32(0x00000780)
4499 +#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
4500 +#define RF4_BW40 FIELD32(0x00200000)
4501 +
4502 +/*
4503 + * EEPROM content.
4504 + * The wordsize of the EEPROM is 16 bits.
4505 + */
4506 +
4507 +/*
4508 + * EEPROM Version
4509 + */
4510 +#define EEPROM_VERSION 0x0001
4511 +#define EEPROM_VERSION_FAE FIELD16(0x00ff)
4512 +#define EEPROM_VERSION_VERSION FIELD16(0xff00)
4513 +
4514 +/*
4515 + * HW MAC address.
4516 + */
4517 +#define EEPROM_MAC_ADDR_0 0x0002
4518 +#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
4519 +#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
4520 +#define EEPROM_MAC_ADDR_1 0x0003
4521 +#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
4522 +#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
4523 +#define EEPROM_MAC_ADDR_2 0x0004
4524 +#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
4525 +#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
4526 +
4527 +/*
4528 + * EEPROM ANTENNA config
4529 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4530 + * TXPATH: 1: 1T, 2: 2T
4531 + */
4532 +#define EEPROM_ANTENNA 0x001a
4533 +#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
4534 +#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
4535 +#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
4536 +
4537 +/*
4538 + * EEPROM NIC config
4539 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4540 + */
4541 +#define EEPROM_NIC 0x001b
4542 +#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
4543 +#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
4544 +#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
4545 +#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
4546 +#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
4547 +#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
4548 +#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
4549 +#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
4550 +#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
4551 +#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
4552 +
4553 +/*
4554 + * EEPROM frequency
4555 + */
4556 +#define EEPROM_FREQ 0x001d
4557 +#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
4558 +#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
4559 +#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
4560 +
4561 +/*
4562 + * EEPROM LED
4563 + * POLARITY_RDY_G: Polarity RDY_G setting.
4564 + * POLARITY_RDY_A: Polarity RDY_A setting.
4565 + * POLARITY_ACT: Polarity ACT setting.
4566 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4567 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4568 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4569 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4570 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4571 + * LED_MODE: Led mode.
4572 + */
4573 +#define EEPROM_LED1 0x001e
4574 +#define EEPROM_LED2 0x001f
4575 +#define EEPROM_LED3 0x0020
4576 +#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
4577 +#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
4578 +#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
4579 +#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
4580 +#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
4581 +#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
4582 +#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
4583 +#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
4584 +#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
4585 +
4586 +/*
4587 + * EEPROM LNA
4588 + */
4589 +#define EEPROM_LNA 0x0022
4590 +#define EEPROM_LNA_BG FIELD16(0x00ff)
4591 +#define EEPROM_LNA_A0 FIELD16(0xff00)
4592 +
4593 +/*
4594 + * EEPROM RSSI BG offset
4595 + */
4596 +#define EEPROM_RSSI_BG 0x0023
4597 +#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
4598 +#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
4599 +
4600 +/*
4601 + * EEPROM RSSI BG2 offset
4602 + */
4603 +#define EEPROM_RSSI_BG2 0x0024
4604 +#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
4605 +#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
4606 +
4607 +/*
4608 + * EEPROM RSSI A offset
4609 + */
4610 +#define EEPROM_RSSI_A 0x0025
4611 +#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
4612 +#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
4613 +
4614 +/*
4615 + * EEPROM RSSI A2 offset
4616 + */
4617 +#define EEPROM_RSSI_A2 0x0026
4618 +#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
4619 +#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
4620 +
4621 +/*
4622 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4623 + * This is delta in 40MHZ.
4624 + * VALUE: Tx Power dalta value (MAX=4)
4625 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4626 + * TXPOWER: Enable:
4627 + */
4628 +#define EEPROM_TXPOWER_DELTA 0x0028
4629 +#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
4630 +#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
4631 +#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
4632 +
4633 +/*
4634 + * EEPROM TXPOWER 802.11BG
4635 + */
4636 +#define EEPROM_TXPOWER_BG1 0x0029
4637 +#define EEPROM_TXPOWER_BG2 0x0030
4638 +#define EEPROM_TXPOWER_BG_SIZE 7
4639 +#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
4640 +#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
4641 +
4642 +/*
4643 + * EEPROM TXPOWER 802.11A
4644 + */
4645 +#define EEPROM_TXPOWER_A1 0x003c
4646 +#define EEPROM_TXPOWER_A2 0x0053
4647 +#define EEPROM_TXPOWER_A_SIZE 6
4648 +#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
4649 +#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
4650 +
4651 +/*
4652 + * EEPROM TXpower byrate: 20MHZ power
4653 + */
4654 +#define EEPROM_TXPOWER_BYRATE 0x006f
4655 +
4656 +/*
4657 + * EEPROM BBP.
4658 + */
4659 +#define EEPROM_BBP_START 0x0078
4660 +#define EEPROM_BBP_SIZE 16
4661 +#define EEPROM_BBP_VALUE FIELD16(0x00ff)
4662 +#define EEPROM_BBP_REG_ID FIELD16(0xff00)
4663 +
4664 +/*
4665 + * MCU mailbox commands.
4666 + */
4667 +#define MCU_SLEEP 0x30
4668 +#define MCU_WAKEUP 0x31
4669 +#define MCU_LED 0x50
4670 +#define MCU_LED_STRENGTH 0x51
4671 +#define MCU_LED_1 0x52
4672 +#define MCU_LED_2 0x53
4673 +#define MCU_LED_3 0x54
4674 +#define MCU_RADAR 0x60
4675 +#define MCU_BOOT_SIGNAL 0x72
4676 +
4677 +/*
4678 + * DMA descriptor defines.
4679 + */
4680 +#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
4681 +#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
4682 +#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4683 +#define RXD_DESC_SIZE ( 1 * sizeof(__le32) )
4684 +#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4685 +
4686 +/*
4687 + * TX descriptor format for TX, PRIO and Beacon Ring.
4688 + */
4689 +
4690 +/*
4691 + * Word0
4692 + */
4693 +#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
4694 +
4695 +/*
4696 + * Word1
4697 + */
4698 +#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
4699 +#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
4700 +#define TXD_W1_BURST FIELD32(0x00008000)
4701 +#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
4702 +#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
4703 +#define TXD_W1_DMA_DONE FIELD32(0x80000000)
4704 +
4705 +/*
4706 + * Word2
4707 + */
4708 +#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
4709 +
4710 +/*
4711 + * Word3
4712 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
4713 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4714 + * 0:MGMT, 1:HCCA 2:EDCA
4715 + */
4716 +#define TXD_W3_WIV FIELD32(0x01000000)
4717 +#define TXD_W3_QSEL FIELD32(0x06000000)
4718 +#define TXD_W3_TCO FIELD32(0x20000000)
4719 +#define TXD_W3_UCO FIELD32(0x40000000)
4720 +#define TXD_W3_ICO FIELD32(0x80000000)
4721 +
4722 +/*
4723 + * TX Info structure
4724 + */
4725 +
4726 +/*
4727 + * Word0
4728 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
4729 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4730 + * 0:MGMT, 1:HCCA 2:EDCA
4731 + * USB_DMA_NEXT_VALID: Used ONLY in USB bulk Aggregation, NextValid
4732 + * DMA_TX_BURST: used ONLY in USB bulk Aggregation.
4733 + * Force USB DMA transmit frame from current selected endpoint
4734 + */
4735 +#define TXINFO_W0_USB_DMA_TX_PKT_LEN FIELD32(0x0000ffff)
4736 +#define TXINFO_W0_WIV FIELD32(0x01000000)
4737 +#define TXINFO_W0_QSEL FIELD32(0x06000000)
4738 +#define TXINFO_W0_SW_USE_LAST_ROUND FIELD32(0x08000000)
4739 +#define TXINFO_W0_USB_DMA_NEXT_VALID FIELD32(0x40000000)
4740 +#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000)
4741 +
4742 +/*
4743 + * TX WI structure
4744 + */
4745 +
4746 +/*
4747 + * Word0
4748 + * FRAG: 1 To inform TKIP engine this is a fragment.
4749 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4750 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4751 + * BW: Channel bandwidth 20MHz or 40 MHz
4752 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4753 + */
4754 +#define TXWI_W0_FRAG FIELD32(0x00000001)
4755 +#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
4756 +#define TXWI_W0_CF_ACK FIELD32(0x00000004)
4757 +#define TXWI_W0_TS FIELD32(0x00000008)
4758 +#define TXWI_W0_AMPDU FIELD32(0x00000010)
4759 +#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
4760 +#define TXWI_W0_TX_OP FIELD32(0x00000300)
4761 +#define TXWI_W0_MCS FIELD32(0x007f0000)
4762 +#define TXWI_W0_BW FIELD32(0x00800000)
4763 +#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
4764 +#define TXWI_W0_STBC FIELD32(0x06000000)
4765 +#define TXWI_W0_IFS FIELD32(0x08000000)
4766 +#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
4767 +
4768 +/*
4769 + * Word1
4770 + */
4771 +#define TXWI_W1_ACK FIELD32(0x00000001)
4772 +#define TXWI_W1_NSEQ FIELD32(0x00000002)
4773 +#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
4774 +#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
4775 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4776 +#define TXWI_W1_PACKETID FIELD32(0xf0000000)
4777 +
4778 +/*
4779 + * Word2
4780 + */
4781 +#define TXWI_W2_IV FIELD32(0xffffffff)
4782 +
4783 +/*
4784 + * Word3
4785 + */
4786 +#define TXWI_W3_EIV FIELD32(0xffffffff)
4787 +
4788 +/*
4789 + * RX descriptor format for RX Ring.
4790 + */
4791 +
4792 +/*
4793 + * Word0
4794 + * UNICAST_TO_ME: This RX frame is unicast to me.
4795 + * MULTICAST: This is a multicast frame.
4796 + * BROADCAST: This is a broadcast frame.
4797 + * MY_BSS: this frame belongs to the same BSSID.
4798 + * CRC_ERROR: CRC error.
4799 + * CIPHER_ERROR: 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid.
4800 + * AMSDU: rx with 802.3 header, not 802.11 header.
4801 + */
4802 +
4803 +#define RXD_W0_BA FIELD32(0x00000001)
4804 +#define RXD_W0_DATA FIELD32(0x00000002)
4805 +#define RXD_W0_NULLDATA FIELD32(0x00000004)
4806 +#define RXD_W0_FRAG FIELD32(0x00000008)
4807 +#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000010)
4808 +#define RXD_W0_MULTICAST FIELD32(0x00000020)
4809 +#define RXD_W0_BROADCAST FIELD32(0x00000040)
4810 +#define RXD_W0_MY_BSS FIELD32(0x00000080)
4811 +#define RXD_W0_CRC_ERROR FIELD32(0x00000100)
4812 +#define RXD_W0_CIPHER_ERROR FIELD32(0x00000600)
4813 +#define RXD_W0_AMSDU FIELD32(0x00000800)
4814 +#define RXD_W0_HTC FIELD32(0x00001000)
4815 +#define RXD_W0_RSSI FIELD32(0x00002000)
4816 +#define RXD_W0_L2PAD FIELD32(0x00004000)
4817 +#define RXD_W0_AMPDU FIELD32(0x00008000)
4818 +#define RXD_W0_DECRYPTED FIELD32(0x00010000)
4819 +#define RXD_W0_PLCP_RSSI FIELD32(0x00020000)
4820 +#define RXD_W0_CIPHER_ALG FIELD32(0x00040000)
4821 +#define RXD_W0_LAST_AMSDU FIELD32(0x00080000)
4822 +#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000)
4823 +
4824 +/*
4825 + * RX WI structure
4826 + */
4827 +
4828 +/*
4829 + * Word0
4830 + */
4831 +#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
4832 +#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
4833 +#define RXWI_W0_BSSID FIELD32(0x00001c00)
4834 +#define RXWI_W0_UDF FIELD32(0x0000e000)
4835 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4836 +#define RXWI_W0_TID FIELD32(0xf0000000)
4837 +
4838 +/*
4839 + * Word1
4840 + */
4841 +#define RXWI_W1_FRAG FIELD32(0x0000000f)
4842 +#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
4843 +#define RXWI_W1_MCS FIELD32(0x007f0000)
4844 +#define RXWI_W1_BW FIELD32(0x00800000)
4845 +#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
4846 +#define RXWI_W1_STBC FIELD32(0x06000000)
4847 +#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
4848 +
4849 +/*
4850 + * Word2
4851 + */
4852 +#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
4853 +#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
4854 +#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
4855 +
4856 +/*
4857 + * Word3
4858 + */
4859 +#define RXWI_W3_SNR0 FIELD32(0x000000ff)
4860 +#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
4861 +
4862 +/*
4863 + * Macro's for converting txpower from EEPROM to mac80211 value
4864 + * and from mac80211 value to register value.
4865 + */
4866 +#define MIN_G_TXPOWER 0
4867 +#define MIN_A_TXPOWER -7
4868 +#define MAX_G_TXPOWER 31
4869 +#define MAX_A_TXPOWER 15
4870 +#define DEFAULT_TXPOWER 5
4871 +
4872 +#define TXPOWER_G_FROM_DEV(__txpower) \
4873 + ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4874 +
4875 +#define TXPOWER_G_TO_DEV(__txpower) \
4876 + clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4877 +
4878 +#define TXPOWER_A_FROM_DEV(__txpower) \
4879 + ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4880 +
4881 +#define TXPOWER_A_TO_DEV(__txpower) \
4882 + clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
4883 +
4884 +#endif /* RT2800USB_H */
4885 --- a/drivers/net/wireless/rt2x00/rt2x00.h
4886 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
4887 @@ -143,6 +143,7 @@ struct rt2x00_chip {
4888 #define RT2860D 0x0681 /* 2.4GHz, 5GHz PCI/CB */
4889 #define RT2890 0x0701 /* 2.4GHz PCIe */
4890 #define RT2890D 0x0781 /* 2.4GHz, 5GHz PCIe */
4891 +#define RT2870 0x1600
4892
4893 u16 rf;
4894 u32 rev;
4895 @@ -778,6 +779,12 @@ struct rt2x00_dev {
4896 u8 freq_offset;
4897
4898 /*
4899 + * Calibration information (for rt2800usb).
4900 + */
4901 + u8 calibration_bw20;
4902 + u8 calibration_bw40;
4903 +
4904 + /*
4905 * Low level statistics which will have
4906 * to be kept up to date while device is running.
4907 */
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