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[package] mac80211: cleanup patches
[openwrt/svn-archive/archive.git] / package / mac80211 / patches / 307-rt2x00-Implement-support-for-rt2800pci.patch
1 From b7dcb460c4c441ce52b3c5ce30d65e1ecfbb30ad Mon Sep 17 00:00:00 2001
2 From: Ivo van Doorn <IvDoorn@gmail.com>
3 Date: Sat, 28 Mar 2009 20:46:46 +0100
4 Subject: [PATCH 8/9] rt2x00: Implement support for rt2800pci
5
6 Add support for the rt2800pci chipset.
7
8 Includes various patches from Mattias, Mark, Felix and Xose.
9
10 Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
11 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
12 Signed-off-by: Mark Asselstine <asselsm@gmail.com>
13 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
14 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
15 ---
16 drivers/net/wireless/rt2x00/Kconfig | 26 +
17 drivers/net/wireless/rt2x00/Makefile | 1 +
18 drivers/net/wireless/rt2x00/rt2800pci.c | 3244 +++++++++++++++++++++++++++++++
19 drivers/net/wireless/rt2x00/rt2800pci.h | 1927 ++++++++++++++++++
20 drivers/net/wireless/rt2x00/rt2x00.h | 6 +
21 5 files changed, 5204 insertions(+), 0 deletions(-)
22 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
23 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
24
25 --- a/drivers/net/wireless/rt2x00/Makefile
26 +++ b/drivers/net/wireless/rt2x00/Makefile
27 @@ -17,5 +17,6 @@ obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00u
28 obj-$(CONFIG_RT2400PCI) += rt2400pci.o
29 obj-$(CONFIG_RT2500PCI) += rt2500pci.o
30 obj-$(CONFIG_RT61PCI) += rt61pci.o
31 +obj-$(CONFIG_RT2800PCI) += rt2800pci.o
32 obj-$(CONFIG_RT2500USB) += rt2500usb.o
33 obj-$(CONFIG_RT73USB) += rt73usb.o
34 --- /dev/null
35 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
36 @@ -0,0 +1,3244 @@
37 +/*
38 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
39 + <http://rt2x00.serialmonkey.com>
40 +
41 + This program is free software; you can redistribute it and/or modify
42 + it under the terms of the GNU General Public License as published by
43 + the Free Software Foundation; either version 2 of the License, or
44 + (at your option) any later version.
45 +
46 + This program is distributed in the hope that it will be useful,
47 + but WITHOUT ANY WARRANTY; without even the implied warranty of
48 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
49 + GNU General Public License for more details.
50 +
51 + You should have received a copy of the GNU General Public License
52 + along with this program; if not, write to the
53 + Free Software Foundation, Inc.,
54 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
55 + */
56 +
57 +/*
58 + Module: rt2800pci
59 + Abstract: rt2800pci device specific routines.
60 + Supported chipsets: RT2800E & RT2800ED.
61 + */
62 +
63 +#include <linux/crc-ccitt.h>
64 +#include <linux/delay.h>
65 +#include <linux/etherdevice.h>
66 +#include <linux/init.h>
67 +#include <linux/kernel.h>
68 +#include <linux/module.h>
69 +#include <linux/pci.h>
70 +#include <linux/platform_device.h>
71 +#include <linux/eeprom_93cx6.h>
72 +
73 +#include "rt2x00.h"
74 +#include "rt2x00pci.h"
75 +#include "rt2x00soc.h"
76 +#include "rt2800pci.h"
77 +
78 +#ifdef CONFIG_RT2800PCI_PCI_MODULE
79 +#define CONFIG_RT2800PCI_PCI
80 +#endif
81 +
82 +#ifdef CONFIG_RT2800PCI_WISOC_MODULE
83 +#define CONFIG_RT2800PCI_WISOC
84 +#endif
85 +
86 +/*
87 + * Allow hardware encryption to be disabled.
88 + */
89 +static int modparam_nohwcrypt = 0;
90 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
91 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
92 +
93 +/*
94 + * Register access.
95 + * BBP and RF register require indirect register access,
96 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
97 + * These indirect registers work with busy bits,
98 + * and we will try maximal REGISTER_BUSY_COUNT times to access
99 + * the register while taking a REGISTER_BUSY_DELAY us delay
100 + * between each attampt. When the busy bit is still set at that time,
101 + * the access attempt is considered to have failed,
102 + * and we will print an error.
103 + */
104 +#define WAIT_FOR_BBP(__dev, __reg) \
105 + rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
106 +#define WAIT_FOR_RFCSR(__dev, __reg) \
107 + rt2x00pci_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
108 +#define WAIT_FOR_RF(__dev, __reg) \
109 + rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
110 +#define WAIT_FOR_MCU(__dev, __reg) \
111 + rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
112 + H2M_MAILBOX_CSR_OWNER, (__reg))
113 +
114 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
115 + const unsigned int word, const u8 value)
116 +{
117 + u32 reg;
118 +
119 + mutex_lock(&rt2x00dev->csr_mutex);
120 +
121 + /*
122 + * Wait until the BBP becomes available, afterwards we
123 + * can safely write the new data into the register.
124 + */
125 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
126 + reg = 0;
127 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
128 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
129 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
130 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
131 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
132 +
133 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
134 + }
135 +
136 + mutex_unlock(&rt2x00dev->csr_mutex);
137 +}
138 +
139 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
140 + const unsigned int word, u8 *value)
141 +{
142 + u32 reg;
143 +
144 + mutex_lock(&rt2x00dev->csr_mutex);
145 +
146 + /*
147 + * Wait until the BBP becomes available, afterwards we
148 + * can safely write the read request into the register.
149 + * After the data has been written, we wait until hardware
150 + * returns the correct value, if at any time the register
151 + * doesn't become available in time, reg will be 0xffffffff
152 + * which means we return 0xff to the caller.
153 + */
154 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
155 + reg = 0;
156 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
157 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
158 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
159 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
160 +
161 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
162 +
163 + WAIT_FOR_BBP(rt2x00dev, &reg);
164 + }
165 +
166 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
167 +
168 + mutex_unlock(&rt2x00dev->csr_mutex);
169 +}
170 +
171 +static void rt2800pci_rfcsr_write(struct rt2x00_dev *rt2x00dev,
172 + const unsigned int word, const u8 value)
173 +{
174 + u32 reg;
175 +
176 + mutex_lock(&rt2x00dev->csr_mutex);
177 +
178 + /*
179 + * Wait until the RFCSR becomes available, afterwards we
180 + * can safely write the new data into the register.
181 + */
182 + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
183 + reg = 0;
184 + rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
185 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
187 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188 +
189 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
190 + }
191 +
192 + mutex_unlock(&rt2x00dev->csr_mutex);
193 +}
194 +
195 +static void rt2800pci_rfcsr_read(struct rt2x00_dev *rt2x00dev,
196 + const unsigned int word, u8 *value)
197 +{
198 + u32 reg;
199 +
200 + mutex_lock(&rt2x00dev->csr_mutex);
201 +
202 + /*
203 + * Wait until the RFCSR becomes available, afterwards we
204 + * can safely write the read request into the register.
205 + * After the data has been written, we wait until hardware
206 + * returns the correct value, if at any time the register
207 + * doesn't become available in time, reg will be 0xffffffff
208 + * which means we return 0xff to the caller.
209 + */
210 + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
211 + reg = 0;
212 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
213 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
214 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
215 +
216 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
217 +
218 + WAIT_FOR_RFCSR(rt2x00dev, &reg);
219 + }
220 +
221 + *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
222 +
223 + mutex_unlock(&rt2x00dev->csr_mutex);
224 +}
225 +
226 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
227 + const unsigned int word, const u32 value)
228 +{
229 + u32 reg;
230 +
231 + mutex_lock(&rt2x00dev->csr_mutex);
232 +
233 + /*
234 + * Wait until the RF becomes available, afterwards we
235 + * can safely write the new data into the register.
236 + */
237 + if (WAIT_FOR_RF(rt2x00dev, &reg)) {
238 + reg = 0;
239 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
240 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
241 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
242 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
243 +
244 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
245 + rt2x00_rf_write(rt2x00dev, word, value);
246 + }
247 +
248 + mutex_unlock(&rt2x00dev->csr_mutex);
249 +}
250 +
251 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
252 + const u8 command, const u8 token,
253 + const u8 arg0, const u8 arg1)
254 +{
255 + u32 reg;
256 +
257 + /*
258 + * RT2880 and RT3052 don't support MCU requests.
259 + */
260 + if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
261 + rt2x00_rt(&rt2x00dev->chip, RT3052))
262 + return;
263 +
264 + mutex_lock(&rt2x00dev->csr_mutex);
265 +
266 + /*
267 + * Wait until the MCU becomes available, afterwards we
268 + * can safely write the new data into the register.
269 + */
270 + if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
271 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
272 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
273 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
274 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
275 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
276 +
277 + reg = 0;
278 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
279 + rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
280 + }
281 +
282 + mutex_unlock(&rt2x00dev->csr_mutex);
283 +}
284 +
285 +static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
286 +{
287 + unsigned int i;
288 + u32 reg;
289 +
290 + for (i = 0; i < 200; i++) {
291 + rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
292 +
293 + if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
294 + (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
295 + (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
296 + (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
297 + break;
298 +
299 + udelay(REGISTER_BUSY_DELAY);
300 + }
301 +
302 + if (i == 200)
303 + ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
304 +
305 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
306 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
307 +}
308 +
309 +#ifdef CONFIG_RT2800PCI_WISOC
310 +static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
311 +{
312 + u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
313 +
314 + memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
315 +}
316 +#else
317 +static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
318 +{
319 +}
320 +#endif /* CONFIG_RT2800PCI_WISOC */
321 +
322 +#ifdef CONFIG_RT2800PCI_PCI
323 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
324 +{
325 + struct rt2x00_dev *rt2x00dev = eeprom->data;
326 + u32 reg;
327 +
328 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
329 +
330 + eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
331 + eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
332 + eeprom->reg_data_clock =
333 + !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
334 + eeprom->reg_chip_select =
335 + !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
336 +}
337 +
338 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
339 +{
340 + struct rt2x00_dev *rt2x00dev = eeprom->data;
341 + u32 reg = 0;
342 +
343 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
344 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
345 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
346 + !!eeprom->reg_data_clock);
347 + rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
348 + !!eeprom->reg_chip_select);
349 +
350 + rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
351 +}
352 +
353 +static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
354 +{
355 + struct eeprom_93cx6 eeprom;
356 + u32 reg;
357 +
358 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
359 +
360 + eeprom.data = rt2x00dev;
361 + eeprom.register_read = rt2800pci_eepromregister_read;
362 + eeprom.register_write = rt2800pci_eepromregister_write;
363 + eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
364 + PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
365 + eeprom.reg_data_in = 0;
366 + eeprom.reg_data_out = 0;
367 + eeprom.reg_data_clock = 0;
368 + eeprom.reg_chip_select = 0;
369 +
370 + eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
371 + EEPROM_SIZE / sizeof(u16));
372 +}
373 +#else
374 +static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
375 +{
376 +}
377 +#endif /* CONFIG_RT2800PCI_PCI */
378 +
379 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
380 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
381 + .owner = THIS_MODULE,
382 + .csr = {
383 + .read = rt2x00pci_register_read,
384 + .write = rt2x00pci_register_write,
385 + .flags = RT2X00DEBUGFS_OFFSET,
386 + .word_base = CSR_REG_BASE,
387 + .word_size = sizeof(u32),
388 + .word_count = CSR_REG_SIZE / sizeof(u32),
389 + },
390 + .eeprom = {
391 + .read = rt2x00_eeprom_read,
392 + .write = rt2x00_eeprom_write,
393 + .word_base = EEPROM_BASE,
394 + .word_size = sizeof(u16),
395 + .word_count = EEPROM_SIZE / sizeof(u16),
396 + },
397 + .bbp = {
398 + .read = rt2800pci_bbp_read,
399 + .write = rt2800pci_bbp_write,
400 + .word_base = BBP_BASE,
401 + .word_size = sizeof(u8),
402 + .word_count = BBP_SIZE / sizeof(u8),
403 + },
404 + .rf = {
405 + .read = rt2x00_rf_read,
406 + .write = rt2800pci_rf_write,
407 + .word_base = RF_BASE,
408 + .word_size = sizeof(u32),
409 + .word_count = RF_SIZE / sizeof(u32),
410 + },
411 +};
412 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
413 +
414 +#ifdef CONFIG_RT2X00_LIB_RFKILL
415 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
416 +{
417 + u32 reg;
418 +
419 + rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
420 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
421 +}
422 +#else
423 +#define rt2800pci_rfkill_poll NULL
424 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
425 +
426 +#ifdef CONFIG_RT2X00_LIB_LEDS
427 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
428 + enum led_brightness brightness)
429 +{
430 + struct rt2x00_led *led =
431 + container_of(led_cdev, struct rt2x00_led, led_dev);
432 + unsigned int enabled = brightness != LED_OFF;
433 + unsigned int bg_mode =
434 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
435 + unsigned int polarity =
436 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
437 + EEPROM_FREQ_LED_POLARITY);
438 + unsigned int ledmode =
439 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
440 + EEPROM_FREQ_LED_MODE);
441 +
442 + if (led->type == LED_TYPE_RADIO) {
443 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
444 + enabled ? 0x20 : 0);
445 + } else if (led->type == LED_TYPE_ASSOC) {
446 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
447 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
448 + } else if (led->type == LED_TYPE_QUALITY) {
449 + /*
450 + * The brightness is divided into 6 levels (0 - 5),
451 + * The specs tell us the following levels:
452 + * 0, 1 ,3, 7, 15, 31
453 + * to determine the level in a simple way we can simply
454 + * work with bitshifting:
455 + * (1 << level) - 1
456 + */
457 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
458 + (1 << brightness / (LED_FULL / 6)) - 1,
459 + polarity);
460 + }
461 +}
462 +
463 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
464 + unsigned long *delay_on,
465 + unsigned long *delay_off)
466 +{
467 + struct rt2x00_led *led =
468 + container_of(led_cdev, struct rt2x00_led, led_dev);
469 + u32 reg;
470 +
471 + rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
472 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
473 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
474 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
475 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
476 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
477 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
478 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
479 + rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
480 +
481 + return 0;
482 +}
483 +
484 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
485 + struct rt2x00_led *led,
486 + enum led_type type)
487 +{
488 + led->rt2x00dev = rt2x00dev;
489 + led->type = type;
490 + led->led_dev.brightness_set = rt2800pci_brightness_set;
491 + led->led_dev.blink_set = rt2800pci_blink_set;
492 + led->flags = LED_INITIALIZED;
493 +}
494 +#endif /* CONFIG_RT2X00_LIB_LEDS */
495 +
496 +/*
497 + * Configuration handlers.
498 + */
499 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
500 + struct rt2x00lib_crypto *crypto,
501 + struct ieee80211_key_conf *key)
502 +{
503 + struct mac_wcid_entry wcid_entry;
504 + struct mac_iveiv_entry iveiv_entry;
505 + u32 offset;
506 + u32 reg;
507 +
508 + offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
509 +
510 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
511 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
512 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
513 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
514 + (crypto->cmd == SET_KEY) * crypto->cipher);
515 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
516 + (crypto->cmd == SET_KEY) * crypto->bssidx);
517 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
518 + rt2x00pci_register_write(rt2x00dev, offset, reg);
519 +
520 + offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
521 +
522 + memset(&iveiv_entry, 0, sizeof(iveiv_entry));
523 + if ((crypto->cipher == CIPHER_TKIP) ||
524 + (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
525 + (crypto->cipher == CIPHER_AES))
526 + iveiv_entry.iv[3] |= 0x20;
527 + iveiv_entry.iv[3] |= key->keyidx << 6;
528 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
529 + &iveiv_entry, sizeof(iveiv_entry));
530 +
531 + offset = MAC_WCID_ENTRY(key->hw_key_idx);
532 +
533 + memset(&wcid_entry, 0, sizeof(wcid_entry));
534 + if (crypto->cmd == SET_KEY)
535 + memcpy(&wcid_entry, crypto->address, ETH_ALEN);
536 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
537 + &wcid_entry, sizeof(wcid_entry));
538 +}
539 +
540 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
541 + struct rt2x00lib_crypto *crypto,
542 + struct ieee80211_key_conf *key)
543 +{
544 + struct hw_key_entry key_entry;
545 + struct rt2x00_field32 field;
546 + u32 offset;
547 + u32 reg;
548 +
549 + if (crypto->cmd == SET_KEY) {
550 + key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
551 +
552 + memcpy(key_entry.key, crypto->key,
553 + sizeof(key_entry.key));
554 + memcpy(key_entry.tx_mic, crypto->tx_mic,
555 + sizeof(key_entry.tx_mic));
556 + memcpy(key_entry.rx_mic, crypto->rx_mic,
557 + sizeof(key_entry.rx_mic));
558 +
559 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
560 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
561 + &key_entry, sizeof(key_entry));
562 + }
563 +
564 + /*
565 + * The cipher types are stored over multiple registers
566 + * starting with SHARED_KEY_MODE_BASE each word will have
567 + * 32 bits and contains the cipher types for 2 bssidx each.
568 + * Using the correct defines correctly will cause overhead,
569 + * so just calculate the correct offset.
570 + */
571 + field.bit_offset = 4 * (key->hw_key_idx % 8);
572 + field.bit_mask = 0x7 << field.bit_offset;
573 +
574 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
575 +
576 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
577 + rt2x00_set_field32(&reg, field,
578 + (crypto->cmd == SET_KEY) * crypto->cipher);
579 + rt2x00pci_register_write(rt2x00dev, offset, reg);
580 +
581 + /*
582 + * Update WCID information
583 + */
584 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
585 +
586 + return 0;
587 +}
588 +
589 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
590 + struct rt2x00lib_crypto *crypto,
591 + struct ieee80211_key_conf *key)
592 +{
593 + struct hw_key_entry key_entry;
594 + u32 offset;
595 +
596 + if (crypto->cmd == SET_KEY) {
597 + /*
598 + * 1 pairwise key is possible per AID, this means that the AID
599 + * equals our hw_key_idx. Make sure the WCID starts _after_ the
600 + * last possible shared key entry.
601 + */
602 + if (crypto->aid > (256 - 32))
603 + return -ENOSPC;
604 +
605 + key->hw_key_idx = 32 + crypto->aid;
606 +
607 +
608 + memcpy(key_entry.key, crypto->key,
609 + sizeof(key_entry.key));
610 + memcpy(key_entry.tx_mic, crypto->tx_mic,
611 + sizeof(key_entry.tx_mic));
612 + memcpy(key_entry.rx_mic, crypto->rx_mic,
613 + sizeof(key_entry.rx_mic));
614 +
615 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
616 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
617 + &key_entry, sizeof(key_entry));
618 + }
619 +
620 + /*
621 + * Update WCID information
622 + */
623 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
624 +
625 + return 0;
626 +}
627 +
628 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
629 + const unsigned int filter_flags)
630 +{
631 + u32 reg;
632 +
633 + /*
634 + * Start configuration steps.
635 + * Note that the version error will always be dropped
636 + * and broadcast frames will always be accepted since
637 + * there is no filter for it at this time.
638 + */
639 + rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
640 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
641 + !(filter_flags & FIF_FCSFAIL));
642 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
643 + !(filter_flags & FIF_PLCPFAIL));
644 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
645 + !(filter_flags & FIF_PROMISC_IN_BSS));
646 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
647 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
648 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
649 + !(filter_flags & FIF_ALLMULTI));
650 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
651 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
652 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
653 + !(filter_flags & FIF_CONTROL));
654 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
655 + !(filter_flags & FIF_CONTROL));
656 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
657 + !(filter_flags & FIF_CONTROL));
658 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
659 + !(filter_flags & FIF_CONTROL));
660 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
661 + !(filter_flags & FIF_CONTROL));
662 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
663 + !(filter_flags & FIF_CONTROL));
664 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
665 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
666 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
667 + !(filter_flags & FIF_CONTROL));
668 + rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
669 +}
670 +
671 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
672 + struct rt2x00_intf *intf,
673 + struct rt2x00intf_conf *conf,
674 + const unsigned int flags)
675 +{
676 + unsigned int beacon_base;
677 + u32 reg;
678 +
679 + if (flags & CONFIG_UPDATE_TYPE) {
680 + /*
681 + * Clear current synchronisation setup.
682 + * For the Beacon base registers we only need to clear
683 + * the first byte since that byte contains the VALID and OWNER
684 + * bits which (when set to 0) will invalidate the entire beacon.
685 + */
686 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
687 + rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
688 +
689 + /*
690 + * Enable synchronisation.
691 + */
692 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
693 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
694 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
695 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
696 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
697 + }
698 +
699 + if (flags & CONFIG_UPDATE_MAC) {
700 + reg = le32_to_cpu(conf->mac[1]);
701 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
702 + conf->mac[1] = cpu_to_le32(reg);
703 +
704 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
705 + conf->mac, sizeof(conf->mac));
706 + }
707 +
708 + if (flags & CONFIG_UPDATE_BSSID) {
709 + reg = le32_to_cpu(conf->bssid[1]);
710 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
711 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
712 + conf->bssid[1] = cpu_to_le32(reg);
713 +
714 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
715 + conf->bssid, sizeof(conf->bssid));
716 + }
717 +}
718 +
719 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
720 + struct rt2x00lib_erp *erp)
721 +{
722 + u32 reg;
723 +
724 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
725 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
726 + DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
727 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
728 +
729 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
730 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
731 + !!erp->short_preamble);
732 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
733 + !!erp->short_preamble);
734 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
735 +
736 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
737 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
738 + erp->cts_protection ? 2 : 0);
739 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
740 +
741 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
742 + erp->basic_rates);
743 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
744 +
745 + rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
746 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
747 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
748 + rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
749 +
750 + rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
751 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
752 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
753 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
754 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
755 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
756 + rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
757 +}
758 +
759 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
760 + struct antenna_setup *ant)
761 +{
762 + u16 eeprom;
763 + u8 r1;
764 + u8 r3;
765 +
766 + /*
767 + * FIXME: Use requested antenna configuration.
768 + */
769 +
770 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
771 +
772 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
773 + rt2800pci_bbp_read(rt2x00dev, 3, &r3);
774 +
775 + /*
776 + * Configure the TX antenna.
777 + */
778 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
779 + case 1:
780 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
781 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
782 + break;
783 + case 2:
784 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
785 + break;
786 + case 3:
787 + /* Do nothing */
788 + break;
789 + }
790 +
791 + /*
792 + * Configure the RX antenna.
793 + */
794 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
795 + case 1:
796 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
797 + break;
798 + case 2:
799 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
800 + break;
801 + case 3:
802 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
803 + break;
804 + }
805 +
806 + rt2800pci_bbp_write(rt2x00dev, 3, r3);
807 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
808 +}
809 +
810 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
811 + struct rt2x00lib_conf *libconf)
812 +{
813 + u16 eeprom;
814 + short lna_gain;
815 +
816 + if (libconf->rf.channel <= 14) {
817 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
818 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
819 + } else if (libconf->rf.channel <= 64) {
820 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
821 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
822 + } else if (libconf->rf.channel <= 128) {
823 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
824 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
825 + } else {
826 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
827 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
828 + }
829 +
830 + rt2x00dev->lna_gain = lna_gain;
831 +}
832 +
833 +static void rt2800pci_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
834 + struct ieee80211_conf *conf,
835 + struct rf_channel *rf,
836 + struct channel_info *info)
837 +{
838 + u16 eeprom;
839 +
840 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
841 +
842 + /*
843 + * Determine antenna settings from EEPROM
844 + */
845 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
846 +
847 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
848 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
849 +
850 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
851 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
852 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
853 + } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
854 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
855 +
856 + if (rf->channel > 14) {
857 + /*
858 + * When TX power is below 0, we should increase it by 7 to
859 + * make it a positive value (Minumum value is -7).
860 + * However this means that values between 0 and 7 have
861 + * double meaning, and we should set a 7DBm boost flag.
862 + */
863 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
864 + (info->tx_power1 >= 0));
865 +
866 + if (info->tx_power1 < 0)
867 + info->tx_power1 += 7;
868 +
869 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
870 + TXPOWER_A_TO_DEV(info->tx_power1));
871 +
872 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
873 + (info->tx_power2 >= 0));
874 +
875 + if (info->tx_power2 < 0)
876 + info->tx_power2 += 7;
877 +
878 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
879 + TXPOWER_A_TO_DEV(info->tx_power2));
880 + } else {
881 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
882 + TXPOWER_G_TO_DEV(info->tx_power1));
883 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
884 + TXPOWER_G_TO_DEV(info->tx_power2));
885 + }
886 +
887 + rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
888 +
889 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
890 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
891 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
892 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
893 +
894 + udelay(200);
895 +
896 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
897 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
898 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
899 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
900 +
901 + udelay(200);
902 +
903 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
904 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
905 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
906 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
907 +}
908 +
909 +static void rt2800pci_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
910 + struct ieee80211_conf *conf,
911 + struct rf_channel *rf,
912 + struct channel_info *info)
913 +{
914 + u8 rfcsr;
915 +
916 + rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf1);
917 + rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf3);
918 +
919 + rt2800pci_rfcsr_read(rt2x00dev, 6, &rfcsr);
920 + rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
921 + rt2800pci_rfcsr_write(rt2x00dev, 6, rfcsr);
922 +
923 + rt2800pci_rfcsr_read(rt2x00dev, 12, &rfcsr);
924 + rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
925 + TXPOWER_G_TO_DEV(info->tx_power1));
926 + rt2800pci_rfcsr_write(rt2x00dev, 12, rfcsr);
927 +
928 + rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
929 + rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
930 + rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
931 +
932 + if (conf_is_ht40(conf))
933 + rt2800pci_rfcsr_write(rt2x00dev, 24,
934 + rt2x00dev->calibration_bw40);
935 + else
936 + rt2800pci_rfcsr_write(rt2x00dev, 24,
937 + rt2x00dev->calibration_bw20);
938 +
939 + rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
940 + rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
941 + rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
942 +}
943 +
944 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
945 + struct ieee80211_conf *conf,
946 + struct rf_channel *rf,
947 + struct channel_info *info)
948 +{
949 + u32 reg;
950 + unsigned int tx_pin;
951 + u16 eeprom;
952 + u8 bbp;
953 +
954 + /*
955 + * Determine antenna settings from EEPROM
956 + */
957 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
958 +
959 + if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
960 + rt2800pci_config_channel_rt2x(rt2x00dev, conf, rf, info);
961 + else
962 + rt2800pci_config_channel_rt3x(rt2x00dev, conf, rf, info);
963 +
964 + /*
965 + * Change BBP settings
966 + */
967 + rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
968 + rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
969 + rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
970 + rt2800pci_bbp_write(rt2x00dev, 86, 0);
971 +
972 + if (rf->channel <= 14) {
973 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
974 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
975 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
976 + } else {
977 + rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
978 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
979 + }
980 + } else {
981 + rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
982 +
983 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
984 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
985 + else
986 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
987 + }
988 +
989 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
990 + rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
991 + rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
992 + rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
993 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
994 +
995 + tx_pin = 0;
996 +
997 + /* Turn on unused PA or LNA when not using 1T or 1R */
998 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) != 1) {
999 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1000 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1001 + }
1002 +
1003 + /* Turn on unused PA or LNA when not using 1T or 1R */
1004 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) != 1) {
1005 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1006 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1007 + }
1008 +
1009 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1010 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1011 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1012 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1013 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1014 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1015 +
1016 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1017 +
1018 + rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1019 + rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1020 + rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1021 +
1022 + rt2800pci_bbp_read(rt2x00dev, 3, &bbp);
1023 + rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
1024 + rt2800pci_bbp_write(rt2x00dev, 3, bbp);
1025 +
1026 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1027 + if (conf_is_ht40(conf)) {
1028 + rt2800pci_bbp_write(rt2x00dev, 69, 0x1a);
1029 + rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1030 + rt2800pci_bbp_write(rt2x00dev, 73, 0x16);
1031 + } else {
1032 + rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1033 + rt2800pci_bbp_write(rt2x00dev, 70, 0x08);
1034 + rt2800pci_bbp_write(rt2x00dev, 73, 0x11);
1035 + }
1036 + }
1037 +
1038 + msleep(1);
1039 +}
1040 +
1041 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1042 + const int txpower)
1043 +{
1044 + u32 reg;
1045 + u32 value = TXPOWER_G_TO_DEV(txpower);
1046 + u8 r1;
1047 +
1048 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
1049 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
1050 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
1051 +
1052 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1053 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1054 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1055 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1056 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1057 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1058 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1059 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1060 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1061 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1062 +
1063 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1064 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1065 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1066 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1067 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1068 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1069 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1070 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1071 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1072 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1073 +
1074 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1075 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1076 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1077 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1078 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1079 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1080 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1081 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1082 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1083 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1084 +
1085 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1086 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1087 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1088 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1089 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1090 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1091 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1092 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1093 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1094 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1095 +
1096 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1097 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1098 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1099 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1100 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1101 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1102 +}
1103 +
1104 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1105 + struct rt2x00lib_conf *libconf)
1106 +{
1107 + u32 reg;
1108 +
1109 + rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1110 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1111 + libconf->conf->short_frame_max_tx_count);
1112 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1113 + libconf->conf->long_frame_max_tx_count);
1114 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1115 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1116 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1117 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1118 + rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
1119 +}
1120 +
1121 +static void rt2800pci_config_duration(struct rt2x00_dev *rt2x00dev,
1122 + struct rt2x00lib_conf *libconf)
1123 +{
1124 + u32 reg;
1125 +
1126 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1127 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1128 + libconf->conf->beacon_int * 16);
1129 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1130 +}
1131 +
1132 +static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
1133 + struct rt2x00lib_conf *libconf)
1134 +{
1135 + enum dev_state state =
1136 + (libconf->conf->flags & IEEE80211_CONF_PS) ?
1137 + STATE_SLEEP : STATE_AWAKE;
1138 + u32 reg;
1139 +
1140 + if (state == STATE_SLEEP) {
1141 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1142 +
1143 + rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1144 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1145 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1146 + libconf->conf->listen_interval - 1);
1147 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1148 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1149 +
1150 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1151 + } else {
1152 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1153 +
1154 + rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1155 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1156 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1157 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1158 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1159 + }
1160 +}
1161 +
1162 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
1163 + struct rt2x00lib_conf *libconf,
1164 + const unsigned int flags)
1165 +{
1166 + /* Always recalculate LNA gain before changing configuration */
1167 + rt2800pci_config_lna_gain(rt2x00dev, libconf);
1168 +
1169 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1170 + rt2800pci_config_channel(rt2x00dev, libconf->conf,
1171 + &libconf->rf, &libconf->channel);
1172 + if (flags & IEEE80211_CONF_CHANGE_POWER)
1173 + rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1174 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1175 + rt2800pci_config_retry_limit(rt2x00dev, libconf);
1176 + if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1177 + rt2800pci_config_duration(rt2x00dev, libconf);
1178 + if (flags & IEEE80211_CONF_CHANGE_PS)
1179 + rt2800pci_config_ps(rt2x00dev, libconf);
1180 +}
1181 +
1182 +/*
1183 + * Link tuning
1184 + */
1185 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
1186 + struct link_qual *qual)
1187 +{
1188 + u32 reg;
1189 +
1190 + /*
1191 + * Update FCS error count from register.
1192 + */
1193 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1194 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1195 +}
1196 +
1197 +static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1198 +{
1199 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
1200 + return 0x2e + rt2x00dev->lna_gain;
1201 +
1202 + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1203 + return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1204 + else
1205 + return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1206 +}
1207 +
1208 +static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1209 + struct link_qual *qual, u8 vgc_level)
1210 +{
1211 + if (qual->vgc_level != vgc_level) {
1212 + rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
1213 + qual->vgc_level = vgc_level;
1214 + qual->vgc_level_reg = vgc_level;
1215 + }
1216 +}
1217 +
1218 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1219 + struct link_qual *qual)
1220 +{
1221 + rt2800pci_set_vgc(rt2x00dev, qual,
1222 + rt2800pci_get_default_vgc(rt2x00dev));
1223 +}
1224 +
1225 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1226 + struct link_qual *qual, const u32 count)
1227 +{
1228 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1229 + return;
1230 +
1231 + /*
1232 + * When RSSI is better then -80 increase VGC level with 0x10
1233 + */
1234 + rt2800pci_set_vgc(rt2x00dev, qual,
1235 + rt2800pci_get_default_vgc(rt2x00dev) +
1236 + ((qual->rssi > -80) * 0x10));
1237 +}
1238 +
1239 +/*
1240 + * Firmware functions
1241 + */
1242 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1243 +{
1244 + return FIRMWARE_RT2860;
1245 +}
1246 +
1247 +static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1248 + const u8 *data, const size_t len)
1249 +{
1250 + u16 fw_crc;
1251 + u16 crc;
1252 +
1253 + /*
1254 + * Only support 8kb firmware files.
1255 + */
1256 + if (len != 8192)
1257 + return FW_BAD_LENGTH;
1258 +
1259 + /*
1260 + * The last 2 bytes in the firmware array are the crc checksum itself,
1261 + * this means that we should never pass those 2 bytes to the crc
1262 + * algorithm.
1263 + */
1264 + fw_crc = (data[len - 2] << 8 | data[len - 1]);
1265 +
1266 + /*
1267 + * Use the crc ccitt algorithm.
1268 + * This will return the same value as the legacy driver which
1269 + * used bit ordering reversion on the both the firmware bytes
1270 + * before input input as well as on the final output.
1271 + * Obviously using crc ccitt directly is much more efficient.
1272 + */
1273 + crc = crc_ccitt(~0, data, len - 2);
1274 +
1275 + /*
1276 + * There is a small difference between the crc-itu-t + bitrev and
1277 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
1278 + * will be swapped, use swab16 to convert the crc to the correct
1279 + * value.
1280 + */
1281 + crc = swab16(crc);
1282 +
1283 + return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1284 +}
1285 +
1286 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1287 + const u8 *data, const size_t len)
1288 +{
1289 + unsigned int i;
1290 + u32 reg;
1291 +
1292 + /*
1293 + * Wait for stable hardware.
1294 + */
1295 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1296 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1297 + if (reg && reg != ~0)
1298 + break;
1299 + msleep(1);
1300 + }
1301 +
1302 + if (i == REGISTER_BUSY_COUNT) {
1303 + ERROR(rt2x00dev, "Unstable hardware.\n");
1304 + return -EBUSY;
1305 + }
1306 +
1307 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1308 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1309 +
1310 + /*
1311 + * Disable DMA, will be reenabled later when enabling
1312 + * the radio.
1313 + */
1314 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1315 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1316 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1317 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1318 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1319 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1320 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1321 +
1322 + /*
1323 + * enable Host program ram write selection
1324 + */
1325 + reg = 0;
1326 + rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1327 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1328 +
1329 + /*
1330 + * Write firmware to device.
1331 + */
1332 + rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1333 + data, len);
1334 +
1335 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1336 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1337 +
1338 + /*
1339 + * Wait for device to stabilize.
1340 + */
1341 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1342 + rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1343 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1344 + break;
1345 + msleep(1);
1346 + }
1347 +
1348 + if (i == REGISTER_BUSY_COUNT) {
1349 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1350 + return -EBUSY;
1351 + }
1352 +
1353 + /*
1354 + * Disable interrupts
1355 + */
1356 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
1357 +
1358 + /*
1359 + * Initialize BBP R/W access agent
1360 + */
1361 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1362 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1363 +
1364 + return 0;
1365 +}
1366 +
1367 +/*
1368 + * Initialization functions.
1369 + */
1370 +static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1371 +{
1372 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1373 + u32 word;
1374 +
1375 + if (entry->queue->qid == QID_RX) {
1376 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1377 +
1378 + return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1379 + } else {
1380 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1381 +
1382 + return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1383 + }
1384 +}
1385 +
1386 +static void rt2800pci_clear_entry(struct queue_entry *entry)
1387 +{
1388 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1389 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1390 + u32 word;
1391 +
1392 + if (entry->queue->qid == QID_RX) {
1393 + rt2x00_desc_read(entry_priv->desc, 0, &word);
1394 + rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1395 + rt2x00_desc_write(entry_priv->desc, 0, word);
1396 +
1397 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1398 + rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1399 + rt2x00_desc_write(entry_priv->desc, 1, word);
1400 + } else {
1401 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1402 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1403 + rt2x00_desc_write(entry_priv->desc, 1, word);
1404 + }
1405 +}
1406 +
1407 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1408 +{
1409 + struct queue_entry_priv_pci *entry_priv;
1410 + u32 reg;
1411 +
1412 + /*
1413 + * Initialize registers.
1414 + */
1415 + entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1416 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1417 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1418 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1419 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
1420 +
1421 + entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1422 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1423 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1424 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1425 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
1426 +
1427 + entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1428 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1429 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1430 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1431 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
1432 +
1433 + entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1434 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1435 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1436 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1437 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
1438 +
1439 + entry_priv = rt2x00dev->rx->entries[0].priv_data;
1440 + rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1441 + rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1442 + rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
1443 + rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
1444 +
1445 + /*
1446 + * Enable global DMA configuration
1447 + */
1448 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1449 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1450 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1451 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1452 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1453 +
1454 + rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1455 +
1456 + return 0;
1457 +}
1458 +
1459 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1460 +{
1461 + u32 reg;
1462 + unsigned int i;
1463 +
1464 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1465 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1466 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1467 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1468 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1469 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1470 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1471 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1472 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1473 +
1474 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1475 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1476 +
1477 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1478 +
1479 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1480 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1481 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1482 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1483 +
1484 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1485 +
1486 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1487 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1488 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1489 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1490 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1491 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1492 +
1493 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1494 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1495 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1496 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1497 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1498 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1499 +
1500 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1501 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1502 +
1503 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1504 +
1505 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1506 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1507 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1508 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1509 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1510 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1511 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1512 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1513 +
1514 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1515 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1516 +
1517 + rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1518 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1519 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1520 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1521 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1522 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1523 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1524 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1525 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1526 + rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1527 +
1528 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1529 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1530 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1531 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1532 +
1533 + rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1534 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1535 + if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1536 + rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1537 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1538 + else
1539 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1540 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1541 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1542 + rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1543 +
1544 + rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1545 +
1546 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1547 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1548 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1549 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1550 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1551 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1552 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1553 +
1554 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1555 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1556 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1557 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1558 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1559 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1560 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1561 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1562 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1563 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1564 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1565 +
1566 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1567 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1568 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1569 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1570 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1571 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1572 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1573 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1574 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1575 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1576 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1577 +
1578 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1579 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1580 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1581 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1582 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1583 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1584 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1585 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1586 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1587 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1588 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1589 +
1590 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1591 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1592 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1593 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1594 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1595 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1596 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1597 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1598 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1599 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1600 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1601 +
1602 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1603 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1604 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1605 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1606 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1607 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1608 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1609 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1610 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1611 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1612 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1613 +
1614 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1615 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1616 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1617 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1618 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1619 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1620 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1621 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1622 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1623 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1624 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1625 +
1626 + rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1627 + rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1628 +
1629 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1630 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1631 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1632 + IEEE80211_MAX_RTS_THRESHOLD);
1633 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1634 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1635 +
1636 + rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1637 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1638 +
1639 + /*
1640 + * ASIC will keep garbage value after boot, clear encryption keys.
1641 + */
1642 + for (i = 0; i < 256; i++) {
1643 + u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1644 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1645 + wcid, sizeof(wcid));
1646 +
1647 + rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1648 + rt2x00pci_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1649 + }
1650 +
1651 + for (i = 0; i < 16; i++)
1652 + rt2x00pci_register_write(rt2x00dev,
1653 + SHARED_KEY_MODE_ENTRY(i), 0);
1654 +
1655 + /*
1656 + * Clear all beacons
1657 + * For the Beacon base registers we only need to clear
1658 + * the first byte since that byte contains the VALID and OWNER
1659 + * bits which (when set to 0) will invalidate the entire beacon.
1660 + */
1661 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1662 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1663 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1664 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1665 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1666 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1667 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1668 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1669 +
1670 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1671 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1672 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1673 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1674 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1675 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1676 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1677 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1678 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1679 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1680 +
1681 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1682 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1683 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1684 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1685 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1686 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1687 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1688 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1689 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1690 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1691 +
1692 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1693 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1694 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1695 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1696 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1697 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1698 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1699 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1700 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1701 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1702 +
1703 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1704 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1705 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1706 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1707 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1708 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1709 +
1710 + /*
1711 + * We must clear the error counters.
1712 + * These registers are cleared on read,
1713 + * so we may pass a useless variable to store the value.
1714 + */
1715 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1716 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1717 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1718 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1719 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1720 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1721 +
1722 + return 0;
1723 +}
1724 +
1725 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1726 +{
1727 + unsigned int i;
1728 + u32 reg;
1729 +
1730 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1731 + rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1732 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1733 + return 0;
1734 +
1735 + udelay(REGISTER_BUSY_DELAY);
1736 + }
1737 +
1738 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1739 + return -EACCES;
1740 +}
1741 +
1742 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1743 +{
1744 + unsigned int i;
1745 + u8 value;
1746 +
1747 + /*
1748 + * BBP was enabled after firmware was loaded,
1749 + * but we need to reactivate it now.
1750 + */
1751 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1752 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1753 + msleep(1);
1754 +
1755 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1756 + rt2800pci_bbp_read(rt2x00dev, 0, &value);
1757 + if ((value != 0xff) && (value != 0x00))
1758 + return 0;
1759 + udelay(REGISTER_BUSY_DELAY);
1760 + }
1761 +
1762 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1763 + return -EACCES;
1764 +}
1765 +
1766 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1767 +{
1768 + unsigned int i;
1769 + u16 eeprom;
1770 + u8 reg_id;
1771 + u8 value;
1772 +
1773 + if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1774 + rt2800pci_wait_bbp_ready(rt2x00dev)))
1775 + return -EACCES;
1776 +
1777 + rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1778 + rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1779 + rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1780 + rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1781 + rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1782 + rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1783 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1784 + rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1785 + rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1786 + rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1787 + rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1788 + rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1789 + rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1790 + rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1791 +
1792 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1793 + rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1794 + rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1795 + }
1796 +
1797 + if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1798 + rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1799 +
1800 + if (rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1801 + rt2800pci_bbp_write(rt2x00dev, 31, 0x08);
1802 + rt2800pci_bbp_write(rt2x00dev, 78, 0x0e);
1803 + rt2800pci_bbp_write(rt2x00dev, 80, 0x08);
1804 + }
1805 +
1806 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1807 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1808 +
1809 + if (eeprom != 0xffff && eeprom != 0x0000) {
1810 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1811 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1812 + rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1813 + }
1814 + }
1815 +
1816 + return 0;
1817 +}
1818 +
1819 +static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1820 + bool bw40, u8 rfcsr24, u8 filter_target)
1821 +{
1822 + unsigned int i;
1823 + u8 bbp;
1824 + u8 rfcsr;
1825 + u8 passband;
1826 + u8 stopband;
1827 + u8 overtuned = 0;
1828 +
1829 + rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1830 +
1831 + rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1832 + rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1833 + rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1834 +
1835 + rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1836 + rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1837 + rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1838 +
1839 + /*
1840 + * Set power & frequency of passband test tone
1841 + */
1842 + rt2800pci_bbp_write(rt2x00dev, 24, 0);
1843 +
1844 + for (i = 0; i < 100; i++) {
1845 + rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1846 + msleep(1);
1847 +
1848 + rt2800pci_bbp_read(rt2x00dev, 55, &passband);
1849 + if (passband)
1850 + break;
1851 + }
1852 +
1853 + /*
1854 + * Set power & frequency of stopband test tone
1855 + */
1856 + rt2800pci_bbp_write(rt2x00dev, 24, 0x06);
1857 +
1858 + for (i = 0; i < 100; i++) {
1859 + rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1860 + msleep(1);
1861 +
1862 + rt2800pci_bbp_read(rt2x00dev, 55, &stopband);
1863 +
1864 + if ((passband - stopband) <= filter_target) {
1865 + rfcsr24++;
1866 + overtuned += ((passband - stopband) == filter_target);
1867 + } else
1868 + break;
1869 +
1870 + rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1871 + }
1872 +
1873 + rfcsr24 -= !!overtuned;
1874 +
1875 + rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1876 + return rfcsr24;
1877 +}
1878 +
1879 +static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1880 +{
1881 + u8 rfcsr;
1882 + u8 bbp;
1883 +
1884 + if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1885 + !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1886 + !rt2x00_rf(&rt2x00dev->chip, RF3022))
1887 + return 0;
1888 +
1889 + /*
1890 + * Init RF calibration.
1891 + */
1892 + rt2800pci_rfcsr_read(rt2x00dev, 30, &rfcsr);
1893 + rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1894 + rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1895 + msleep(1);
1896 + rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1897 + rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1898 +
1899 + rt2800pci_rfcsr_write(rt2x00dev, 0, 0x50);
1900 + rt2800pci_rfcsr_write(rt2x00dev, 1, 0x01);
1901 + rt2800pci_rfcsr_write(rt2x00dev, 2, 0xf7);
1902 + rt2800pci_rfcsr_write(rt2x00dev, 3, 0x75);
1903 + rt2800pci_rfcsr_write(rt2x00dev, 4, 0x40);
1904 + rt2800pci_rfcsr_write(rt2x00dev, 5, 0x03);
1905 + rt2800pci_rfcsr_write(rt2x00dev, 6, 0x02);
1906 + rt2800pci_rfcsr_write(rt2x00dev, 7, 0x50);
1907 + rt2800pci_rfcsr_write(rt2x00dev, 8, 0x39);
1908 + rt2800pci_rfcsr_write(rt2x00dev, 9, 0x0f);
1909 + rt2800pci_rfcsr_write(rt2x00dev, 10, 0x60);
1910 + rt2800pci_rfcsr_write(rt2x00dev, 11, 0x21);
1911 + rt2800pci_rfcsr_write(rt2x00dev, 12, 0x75);
1912 + rt2800pci_rfcsr_write(rt2x00dev, 13, 0x75);
1913 + rt2800pci_rfcsr_write(rt2x00dev, 14, 0x90);
1914 + rt2800pci_rfcsr_write(rt2x00dev, 15, 0x58);
1915 + rt2800pci_rfcsr_write(rt2x00dev, 16, 0xb3);
1916 + rt2800pci_rfcsr_write(rt2x00dev, 17, 0x92);
1917 + rt2800pci_rfcsr_write(rt2x00dev, 18, 0x2c);
1918 + rt2800pci_rfcsr_write(rt2x00dev, 19, 0x02);
1919 + rt2800pci_rfcsr_write(rt2x00dev, 20, 0xba);
1920 + rt2800pci_rfcsr_write(rt2x00dev, 21, 0xdb);
1921 + rt2800pci_rfcsr_write(rt2x00dev, 22, 0x00);
1922 + rt2800pci_rfcsr_write(rt2x00dev, 23, 0x31);
1923 + rt2800pci_rfcsr_write(rt2x00dev, 24, 0x08);
1924 + rt2800pci_rfcsr_write(rt2x00dev, 25, 0x01);
1925 + rt2800pci_rfcsr_write(rt2x00dev, 26, 0x25);
1926 + rt2800pci_rfcsr_write(rt2x00dev, 27, 0x23);
1927 + rt2800pci_rfcsr_write(rt2x00dev, 28, 0x13);
1928 + rt2800pci_rfcsr_write(rt2x00dev, 29, 0x83);
1929 +
1930 + /*
1931 + * Set RX Filter calibration for 20MHz and 40MHz
1932 + */
1933 + rt2x00dev->calibration_bw20 =
1934 + rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1935 + rt2x00dev->calibration_bw40 =
1936 + rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1937 +
1938 + /*
1939 + * Set back to initial state
1940 + */
1941 + rt2800pci_bbp_write(rt2x00dev, 24, 0);
1942 +
1943 + rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1944 + rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1945 + rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1946 +
1947 + /*
1948 + * set BBP back to BW20
1949 + */
1950 + rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1951 + rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1952 + rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1953 +
1954 + return 0;
1955 +}
1956 +
1957 +/*
1958 + * Device state switch handlers.
1959 + */
1960 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1961 + enum dev_state state)
1962 +{
1963 + u32 reg;
1964 +
1965 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1966 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1967 + (state == STATE_RADIO_RX_ON) ||
1968 + (state == STATE_RADIO_RX_ON_LINK));
1969 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1970 +}
1971 +
1972 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1973 + enum dev_state state)
1974 +{
1975 + int mask = (state == STATE_RADIO_IRQ_ON);
1976 + u32 reg;
1977 +
1978 + /*
1979 + * When interrupts are being enabled, the interrupt registers
1980 + * should clear the register to assure a clean state.
1981 + */
1982 + if (state == STATE_RADIO_IRQ_ON) {
1983 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1984 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1985 + }
1986 +
1987 + rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1988 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1989 + rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1990 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1991 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1992 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1993 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1994 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1995 + rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1996 + rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1997 + rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1998 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
1999 + rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
2000 + rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
2001 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
2002 + rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
2003 + rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
2004 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
2005 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
2006 + rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
2007 +}
2008 +
2009 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
2010 +{
2011 + unsigned int i;
2012 + u32 reg;
2013 +
2014 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2015 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2016 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
2017 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
2018 + return 0;
2019 +
2020 + msleep(1);
2021 + }
2022 +
2023 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
2024 + return -EACCES;
2025 +}
2026 +
2027 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
2028 +{
2029 + u32 reg;
2030 + u16 word;
2031 +
2032 + /*
2033 + * Initialize all registers.
2034 + */
2035 + if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2036 + rt2800pci_init_queues(rt2x00dev) ||
2037 + rt2800pci_init_registers(rt2x00dev) ||
2038 + rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2039 + rt2800pci_init_bbp(rt2x00dev) ||
2040 + rt2800pci_init_rfcsr(rt2x00dev)))
2041 + return -EIO;
2042 +
2043 + /*
2044 + * Send signal to firmware during boot time.
2045 + */
2046 + rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
2047 +
2048 + /*
2049 + * Enable RX.
2050 + */
2051 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2052 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2053 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2054 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2055 +
2056 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2057 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2058 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2059 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2060 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2061 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2062 +
2063 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2064 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2065 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2066 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2067 +
2068 + /*
2069 + * Initialize LED control
2070 + */
2071 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2072 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2073 + word & 0xff, (word >> 8) & 0xff);
2074 +
2075 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2076 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2077 + word & 0xff, (word >> 8) & 0xff);
2078 +
2079 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2080 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2081 + word & 0xff, (word >> 8) & 0xff);
2082 +
2083 + return 0;
2084 +}
2085 +
2086 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2087 +{
2088 + u32 reg;
2089 +
2090 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2091 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2092 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2093 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2094 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2095 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2096 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2097 +
2098 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
2099 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2100 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
2101 +
2102 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
2103 +
2104 + /* Wait for DMA, ignore error */
2105 + rt2800pci_wait_wpdma_ready(rt2x00dev);
2106 +}
2107 +
2108 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
2109 + enum dev_state state)
2110 +{
2111 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2112 +
2113 + if (state == STATE_AWAKE) {
2114 + rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
2115 + rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
2116 + } else
2117 + rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
2118 +
2119 + return 0;
2120 +}
2121 +
2122 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
2123 + enum dev_state state)
2124 +{
2125 + int retval = 0;
2126 +
2127 + switch (state) {
2128 + case STATE_RADIO_ON:
2129 + /*
2130 + * Before the radio can be enabled, the device first has
2131 + * to be woken up. After that it needs a bit of time
2132 + * to be fully awake and the radio can be enabled.
2133 + */
2134 + rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
2135 + msleep(1);
2136 + retval = rt2800pci_enable_radio(rt2x00dev);
2137 + break;
2138 + case STATE_RADIO_OFF:
2139 + /*
2140 + * After the radio has been disablee, the device should
2141 + * be put to sleep for powersaving.
2142 + */
2143 + rt2800pci_disable_radio(rt2x00dev);
2144 + rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
2145 + break;
2146 + case STATE_RADIO_RX_ON:
2147 + case STATE_RADIO_RX_ON_LINK:
2148 + case STATE_RADIO_RX_OFF:
2149 + case STATE_RADIO_RX_OFF_LINK:
2150 + rt2800pci_toggle_rx(rt2x00dev, state);
2151 + break;
2152 + case STATE_RADIO_IRQ_ON:
2153 + case STATE_RADIO_IRQ_OFF:
2154 + rt2800pci_toggle_irq(rt2x00dev, state);
2155 + break;
2156 + case STATE_DEEP_SLEEP:
2157 + case STATE_SLEEP:
2158 + case STATE_STANDBY:
2159 + case STATE_AWAKE:
2160 + retval = rt2800pci_set_state(rt2x00dev, state);
2161 + break;
2162 + default:
2163 + retval = -ENOTSUPP;
2164 + break;
2165 + }
2166 +
2167 + if (unlikely(retval))
2168 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
2169 + state, retval);
2170 +
2171 + return retval;
2172 +}
2173 +
2174 +/*
2175 + * TX descriptor initialization
2176 + */
2177 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2178 + struct sk_buff *skb,
2179 + struct txentry_desc *txdesc)
2180 +{
2181 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
2182 + __le32 *txd = skbdesc->desc;
2183 + __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
2184 + u32 word;
2185 +
2186 + /*
2187 + * Initialize TX Info descriptor
2188 + */
2189 + rt2x00_desc_read(txwi, 0, &word);
2190 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
2191 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2192 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
2193 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
2194 + rt2x00_set_field32(&word, TXWI_W0_TS,
2195 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
2196 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
2197 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
2198 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
2199 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
2200 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
2201 + rt2x00_set_field32(&word, TXWI_W0_BW,
2202 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
2203 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
2204 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
2205 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
2206 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2207 + rt2x00_desc_write(txwi, 0, word);
2208 +
2209 + rt2x00_desc_read(txwi, 1, &word);
2210 + rt2x00_set_field32(&word, TXWI_W1_ACK,
2211 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2212 + rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2213 + test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2214 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2215 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2216 + test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2217 + txdesc->key_idx : 0xff);
2218 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
2219 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2220 + skbdesc->entry->queue->qid);
2221 + rt2x00_desc_write(txwi, 1, word);
2222 +
2223 + /*
2224 + * Always write 0 to IV/EIV fields, hardware will insert the IV
2225 + * from the IVEIV register when ENTRY_TXD_ENCRYPT_IV is set to 0.
2226 + * When ENTRY_TXD_ENCRYPT_IV is set to 1 it will use the IV data
2227 + * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2228 + * crypto entry in the registers should be used to encrypt the frame.
2229 + */
2230 + _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2231 + _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2232 +
2233 + /*
2234 + * Initialize TX descriptor
2235 + */
2236 + rt2x00_desc_read(txd, 0, &word);
2237 + rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
2238 + rt2x00_desc_write(txd, 0, word);
2239 +
2240 + rt2x00_desc_read(txd, 1, &word);
2241 + rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
2242 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
2243 + rt2x00_set_field32(&word, TXD_W1_BURST,
2244 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2245 + rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
2246 + rt2x00dev->hw->extra_tx_headroom);
2247 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
2248 + !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2249 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
2250 + rt2x00_desc_write(txd, 1, word);
2251 +
2252 + rt2x00_desc_read(txd, 2, &word);
2253 + rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
2254 + skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
2255 + rt2x00_desc_write(txd, 2, word);
2256 +
2257 + rt2x00_desc_read(txd, 3, &word);
2258 + rt2x00_set_field32(&word, TXD_W3_WIV,
2259 + !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2260 + rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
2261 + rt2x00_desc_write(txd, 3, word);
2262 +}
2263 +
2264 +/*
2265 + * TX data initialization
2266 + */
2267 +static void rt2800pci_write_beacon(struct queue_entry *entry)
2268 +{
2269 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2270 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2271 + unsigned int beacon_base;
2272 + u32 reg;
2273 +
2274 + /*
2275 + * Disable beaconing while we are reloading the beacon data,
2276 + * otherwise we might be sending out invalid data.
2277 + */
2278 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2279 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2280 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2281 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2282 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2283 +
2284 + /*
2285 + * Write entire beacon with descriptor to register.
2286 + */
2287 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2288 + rt2x00pci_register_multiwrite(rt2x00dev,
2289 + beacon_base,
2290 + skbdesc->desc, skbdesc->desc_len);
2291 + rt2x00pci_register_multiwrite(rt2x00dev,
2292 + beacon_base + skbdesc->desc_len,
2293 + entry->skb->data, entry->skb->len);
2294 +
2295 + /*
2296 + * Clean up beacon skb.
2297 + */
2298 + dev_kfree_skb_any(entry->skb);
2299 + entry->skb = NULL;
2300 +}
2301 +
2302 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2303 + const enum data_queue_qid queue_idx)
2304 +{
2305 + struct data_queue *queue;
2306 + unsigned int idx, qidx = 0;
2307 + u32 reg;
2308 +
2309 + if (queue_idx == QID_BEACON) {
2310 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2311 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2312 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2313 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2314 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2315 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2316 + }
2317 + return;
2318 + }
2319 +
2320 + if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
2321 + return;
2322 +
2323 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2324 + idx = queue->index[Q_INDEX];
2325 +
2326 + if (queue_idx == QID_MGMT)
2327 + qidx = 5;
2328 + else
2329 + qidx = queue_idx;
2330 +
2331 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
2332 +}
2333 +
2334 +static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
2335 + const enum data_queue_qid qid)
2336 +{
2337 + u32 reg;
2338 +
2339 + if (qid == QID_BEACON) {
2340 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, 0);
2341 + return;
2342 + }
2343 +
2344 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2345 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
2346 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
2347 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
2348 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
2349 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2350 +}
2351 +
2352 +/*
2353 + * RX control handlers
2354 + */
2355 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
2356 + struct rxdone_entry_desc *rxdesc)
2357 +{
2358 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2359 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
2360 + __le32 *rxd = entry_priv->desc;
2361 + __le32 *rxwi = (__le32 *)entry->skb->data;
2362 + u32 rxd3;
2363 + u32 rxwi0;
2364 + u32 rxwi1;
2365 + u32 rxwi2;
2366 + u32 rxwi3;
2367 +
2368 + rt2x00_desc_read(rxd, 3, &rxd3);
2369 + rt2x00_desc_read(rxwi, 0, &rxwi0);
2370 + rt2x00_desc_read(rxwi, 1, &rxwi1);
2371 + rt2x00_desc_read(rxwi, 2, &rxwi2);
2372 + rt2x00_desc_read(rxwi, 3, &rxwi3);
2373 +
2374 + if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
2375 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2376 +
2377 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2378 + /*
2379 + * Unfortunately we don't know the cipher type used during
2380 + * decryption. This prevents us from correct providing
2381 + * correct statistics through debugfs.
2382 + */
2383 + rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2384 + rxdesc->cipher_status =
2385 + rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
2386 + }
2387 +
2388 + if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
2389 + /*
2390 + * Hardware has stripped IV/EIV data from 802.11 frame during
2391 + * decryption. Unfortunately the descriptor doesn't contain
2392 + * any fields with the EIV/IV data either, so they can't
2393 + * be restored by rt2x00lib.
2394 + */
2395 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2396 +
2397 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2398 + rxdesc->flags |= RX_FLAG_DECRYPTED;
2399 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2400 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2401 + }
2402 +
2403 + if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
2404 + rxdesc->dev_flags |= RXDONE_MY_BSS;
2405 +
2406 + if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2407 + rxdesc->flags |= RX_FLAG_SHORT_GI;
2408 +
2409 + if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2410 + rxdesc->flags |= RX_FLAG_40MHZ;
2411 +
2412 + /*
2413 + * Detect RX rate, always use MCS as signal type.
2414 + */
2415 + rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2416 + rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2417 + rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2418 +
2419 + /*
2420 + * Mask of 0x8 bit to remove the short preamble flag.
2421 + */
2422 + if (rxdesc->rate_mode == RATE_MODE_CCK)
2423 + rxdesc->signal &= ~0x8;
2424 +
2425 + rxdesc->rssi =
2426 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2427 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2428 +
2429 + rxdesc->noise =
2430 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2431 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2432 +
2433 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2434 +
2435 + /*
2436 + * Set RX IDX in register to inform hardware that we have handled
2437 + * this entry and it is available for reuse again.
2438 + */
2439 + rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
2440 +
2441 + /*
2442 + * Remove TXWI descriptor from start of buffer.
2443 + */
2444 + skb_pull(entry->skb, RXWI_DESC_SIZE);
2445 + skb_trim(entry->skb, rxdesc->size);
2446 +}
2447 +
2448 +/*
2449 + * Interrupt functions.
2450 + */
2451 +static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2452 +{
2453 + struct data_queue *queue;
2454 + struct queue_entry *entry;
2455 + struct queue_entry *entry_done;
2456 + struct queue_entry_priv_pci *entry_priv;
2457 + struct txdone_entry_desc txdesc;
2458 + u32 word;
2459 + u32 reg;
2460 + u32 old_reg;
2461 + int type;
2462 + int index;
2463 +
2464 + /*
2465 + * During each loop we will compare the freshly read
2466 + * TX_STA_FIFO register value with the value read from
2467 + * the previous loop. If the 2 values are equal then
2468 + * we should stop processing because the chance it
2469 + * quite big that the device has been unplugged and
2470 + * we risk going into an endless loop.
2471 + */
2472 + old_reg = 0;
2473 +
2474 + while (1) {
2475 + rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2476 + if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2477 + break;
2478 +
2479 + if (old_reg == reg)
2480 + break;
2481 + old_reg = reg;
2482 +
2483 + /*
2484 + * Skip this entry when it contains an invalid
2485 + * queue identication number.
2486 + */
2487 + type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
2488 + queue = rt2x00queue_get_queue(rt2x00dev, type);
2489 + if (unlikely(!queue))
2490 + continue;
2491 +
2492 + /*
2493 + * Skip this entry when it contains an invalid
2494 + * index number.
2495 + */
2496 + index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
2497 + if (unlikely(index >= queue->limit))
2498 + continue;
2499 +
2500 + entry = &queue->entries[index];
2501 + entry_priv = entry->priv_data;
2502 + rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
2503 +
2504 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2505 + while (entry != entry_done) {
2506 + /*
2507 + * Catch up.
2508 + * Just report any entries we missed as failed.
2509 + */
2510 + WARNING(rt2x00dev,
2511 + "TX status report missed for entry %d\n",
2512 + entry_done->entry_idx);
2513 +
2514 + txdesc.flags = 0;
2515 + __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2516 + txdesc.retry = 0;
2517 +
2518 + rt2x00lib_txdone(entry_done, &txdesc);
2519 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2520 + }
2521 +
2522 + /*
2523 + * Obtain the status about this packet.
2524 + */
2525 + txdesc.flags = 0;
2526 + if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
2527 + __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2528 + else
2529 + __set_bit(TXDONE_FAILURE, &txdesc.flags);
2530 + txdesc.retry = rt2x00_get_field32(word, TXWI_W0_MCS);
2531 +
2532 + rt2x00lib_txdone(entry, &txdesc);
2533 + }
2534 +}
2535 +
2536 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2537 +{
2538 + struct rt2x00_dev *rt2x00dev = dev_instance;
2539 + u32 reg;
2540 +
2541 + /* Read status and ACK all interrupts */
2542 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2543 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2544 +
2545 + if (!reg)
2546 + return IRQ_NONE;
2547 +
2548 + if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2549 + return IRQ_HANDLED;
2550 +
2551 + /*
2552 + * 1 - Rx ring done interrupt.
2553 + */
2554 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
2555 + rt2x00pci_rxdone(rt2x00dev);
2556 +
2557 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
2558 + rt2800pci_txdone(rt2x00dev);
2559 +
2560 + return IRQ_HANDLED;
2561 +}
2562 +
2563 +/*
2564 + * Device probe functions.
2565 + */
2566 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2567 +{
2568 + u16 word;
2569 + u8 *mac;
2570 + u8 default_lna_gain;
2571 +
2572 + /*
2573 + * Read EEPROM into buffer
2574 + */
2575 + switch(rt2x00dev->chip.rt) {
2576 + case RT2880:
2577 + case RT3052:
2578 + rt2800pci_read_eeprom_soc(rt2x00dev);
2579 + break;
2580 + default:
2581 + rt2800pci_read_eeprom_pci(rt2x00dev);
2582 + break;
2583 + }
2584 +
2585 + /*
2586 + * Start validation of the data that has been read.
2587 + */
2588 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2589 + if (!is_valid_ether_addr(mac)) {
2590 + DECLARE_MAC_BUF(macbuf);
2591 +
2592 + random_ether_addr(mac);
2593 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2594 + }
2595 +
2596 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2597 + if (word == 0xffff) {
2598 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2599 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2600 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2601 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2602 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2603 + } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2604 + /*
2605 + * There is a max of 2 RX streams for RT2860 series
2606 + */
2607 + if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2608 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2609 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2610 + }
2611 +
2612 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2613 + if (word == 0xffff) {
2614 + rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2615 + rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2616 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2617 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2618 + rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2619 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2620 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2621 + rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2622 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2623 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2624 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2625 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2626 + }
2627 +
2628 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2629 + if ((word & 0x00ff) == 0x00ff) {
2630 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2631 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2632 + LED_MODE_TXRX_ACTIVITY);
2633 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2634 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2635 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2636 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2637 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2638 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2639 + }
2640 +
2641 + /*
2642 + * During the LNA validation we are going to use
2643 + * lna0 as correct value. Note that EEPROM_LNA
2644 + * is never validated.
2645 + */
2646 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2647 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2648 +
2649 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2650 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2651 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2652 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2653 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2654 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2655 +
2656 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2657 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2658 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2659 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2660 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2661 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2662 + default_lna_gain);
2663 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2664 +
2665 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2666 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2667 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2668 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2669 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2670 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2671 +
2672 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2673 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2674 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2675 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2676 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2677 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2678 + default_lna_gain);
2679 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2680 +
2681 + return 0;
2682 +}
2683 +
2684 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2685 +{
2686 + u32 reg;
2687 + u16 value;
2688 + u16 eeprom;
2689 +
2690 + /*
2691 + * Read EEPROM word for configuration.
2692 + */
2693 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2694 +
2695 + /*
2696 + * Identify RF chipset.
2697 + */
2698 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2699 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2700 + rt2x00_set_chip_rf(rt2x00dev, value, reg);
2701 +
2702 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2703 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2704 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2705 + !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2706 + !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2707 + !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
2708 + !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
2709 + !rt2x00_rf(&rt2x00dev->chip, RF3022)) {
2710 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2711 + return -ENODEV;
2712 + }
2713 +
2714 + /*
2715 + * Read frequency offset and RF programming sequence.
2716 + */
2717 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2718 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2719 +
2720 + /*
2721 + * Read external LNA informations.
2722 + */
2723 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2724 +
2725 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2726 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2727 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2728 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2729 +
2730 + /*
2731 + * Detect if this device has an hardware controlled radio.
2732 + */
2733 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2734 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2735 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2736 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2737 +
2738 + /*
2739 + * Store led settings, for correct led behaviour.
2740 + */
2741 +#ifdef CONFIG_RT2X00_LIB_LEDS
2742 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2743 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2744 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2745 +
2746 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2747 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2748 +
2749 + return 0;
2750 +}
2751 +
2752 +/*
2753 + * RF value list for rt2860
2754 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2755 + */
2756 +static const struct rf_channel rf_vals[] = {
2757 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2758 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2759 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2760 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2761 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2762 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2763 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2764 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2765 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2766 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2767 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2768 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2769 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2770 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2771 +
2772 + /* 802.11 UNI / HyperLan 2 */
2773 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2774 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2775 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2776 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2777 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2778 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2779 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2780 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2781 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2782 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2783 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2784 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2785 +
2786 + /* 802.11 HyperLan 2 */
2787 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2788 + { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2789 + { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2790 + { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2791 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2792 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2793 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2794 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2795 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2796 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2797 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2798 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2799 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2800 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2801 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2802 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2803 +
2804 + /* 802.11 UNII */
2805 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2806 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2807 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2808 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2809 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2810 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2811 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2812 +
2813 + /* 802.11 Japan */
2814 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2815 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2816 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2817 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2818 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2819 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2820 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2821 +};
2822 +
2823 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2824 +{
2825 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2826 + struct channel_info *info;
2827 + char *tx_power1;
2828 + char *tx_power2;
2829 + unsigned int i;
2830 + u16 eeprom;
2831 +
2832 + /*
2833 + * Initialize all hw fields.
2834 + */
2835 + rt2x00dev->hw->flags =
2836 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2837 + IEEE80211_HW_SIGNAL_DBM |
2838 + IEEE80211_HW_SUPPORTS_PS |
2839 + IEEE80211_HW_PS_NULLFUNC_STACK;
2840 + rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2841 +
2842 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2843 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2844 + rt2x00_eeprom_addr(rt2x00dev,
2845 + EEPROM_MAC_ADDR_0));
2846 +
2847 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2848 +
2849 + /*
2850 + * Initialize hw_mode information.
2851 + */
2852 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2853 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2854 +
2855 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2856 + rt2x00_rf(&rt2x00dev->chip, RF2720) ||
2857 + rt2x00_rf(&rt2x00dev->chip, RF3021) ||
2858 + rt2x00_rf(&rt2x00dev->chip, RF3022)) {
2859 + spec->num_channels = 14;
2860 + spec->channels = rf_vals;
2861 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2862 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2863 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2864 + spec->num_channels = ARRAY_SIZE(rf_vals);
2865 + spec->channels = rf_vals;
2866 + }
2867 +
2868 + /*
2869 + * Initialize HT information.
2870 + */
2871 + spec->ht.ht_supported = true;
2872 + spec->ht.cap =
2873 + IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2874 + IEEE80211_HT_CAP_GRN_FLD |
2875 + IEEE80211_HT_CAP_SGI_20 |
2876 + IEEE80211_HT_CAP_SGI_40 |
2877 + IEEE80211_HT_CAP_TX_STBC |
2878 + IEEE80211_HT_CAP_RX_STBC |
2879 + IEEE80211_HT_CAP_PSMP_SUPPORT;
2880 + spec->ht.ampdu_factor = 3;
2881 + spec->ht.ampdu_density = 4;
2882 + spec->ht.mcs.tx_params =
2883 + IEEE80211_HT_MCS_TX_DEFINED |
2884 + IEEE80211_HT_MCS_TX_RX_DIFF |
2885 + ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2886 + IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2887 +
2888 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2889 + case 3:
2890 + spec->ht.mcs.rx_mask[2] = 0xff;
2891 + case 2:
2892 + spec->ht.mcs.rx_mask[1] = 0xff;
2893 + case 1:
2894 + spec->ht.mcs.rx_mask[0] = 0xff;
2895 + spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2896 + break;
2897 + }
2898 +
2899 + /*
2900 + * Create channel information array
2901 + */
2902 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2903 + if (!info)
2904 + return -ENOMEM;
2905 +
2906 + spec->channels_info = info;
2907 +
2908 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2909 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2910 +
2911 + for (i = 0; i < 14; i++) {
2912 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2913 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2914 + }
2915 +
2916 + if (spec->num_channels > 14) {
2917 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2918 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2919 +
2920 + for (i = 14; i < spec->num_channels; i++) {
2921 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2922 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2923 + }
2924 + }
2925 +
2926 + return 0;
2927 +}
2928 +
2929 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2930 +{
2931 + int retval;
2932 +
2933 + /*
2934 + * Allocate eeprom data.
2935 + */
2936 + retval = rt2800pci_validate_eeprom(rt2x00dev);
2937 + if (retval)
2938 + return retval;
2939 +
2940 + retval = rt2800pci_init_eeprom(rt2x00dev);
2941 + if (retval)
2942 + return retval;
2943 +
2944 + /*
2945 + * Initialize hw specifications.
2946 + */
2947 + retval = rt2800pci_probe_hw_mode(rt2x00dev);
2948 + if (retval)
2949 + return retval;
2950 +
2951 + /*
2952 + * This device requires firmware.
2953 + */
2954 + if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
2955 + !rt2x00_rt(&rt2x00dev->chip, RT3052))
2956 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2957 + if (!modparam_nohwcrypt)
2958 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2959 +
2960 + /*
2961 + * Set the rssi offset.
2962 + */
2963 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2964 +
2965 + return 0;
2966 +}
2967 +
2968 +/*
2969 + * IEEE80211 stack callback functions.
2970 + */
2971 +static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2972 + u32 *iv32, u16 *iv16)
2973 +{
2974 + struct rt2x00_dev *rt2x00dev = hw->priv;
2975 + struct mac_iveiv_entry iveiv_entry;
2976 + u32 offset;
2977 +
2978 + offset = MAC_IVEIV_ENTRY(hw_key_idx);
2979 + rt2x00pci_register_multiread(rt2x00dev, offset,
2980 + &iveiv_entry, sizeof(iveiv_entry));
2981 +
2982 + memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2983 + memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2984 +}
2985 +
2986 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2987 +{
2988 + struct rt2x00_dev *rt2x00dev = hw->priv;
2989 + u32 reg;
2990 + bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2991 +
2992 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2993 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2994 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2995 +
2996 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2997 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2998 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2999 +
3000 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3001 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3002 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3003 +
3004 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3005 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3006 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3007 +
3008 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3009 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3010 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3011 +
3012 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3013 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3014 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3015 +
3016 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3017 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3018 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3019 +
3020 + return 0;
3021 +}
3022 +
3023 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3024 + const struct ieee80211_tx_queue_params *params)
3025 +{
3026 + struct rt2x00_dev *rt2x00dev = hw->priv;
3027 + struct data_queue *queue;
3028 + struct rt2x00_field32 field;
3029 + int retval;
3030 + u32 reg;
3031 + u32 offset;
3032 +
3033 + /*
3034 + * First pass the configuration through rt2x00lib, that will
3035 + * update the queue settings and validate the input. After that
3036 + * we are free to update the registers based on the value
3037 + * in the queue parameter.
3038 + */
3039 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3040 + if (retval)
3041 + return retval;
3042 +
3043 + /*
3044 + * We only need to perform additional register initialization
3045 + * for WMM queues/
3046 + */
3047 + if (queue_idx >= 4)
3048 + return 0;
3049 +
3050 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3051 +
3052 + /* Update WMM TXOP register */
3053 + offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3054 + field.bit_offset = (queue_idx & 1) * 16;
3055 + field.bit_mask = 0xffff << field.bit_offset;
3056 +
3057 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
3058 + rt2x00_set_field32(&reg, field, queue->txop);
3059 + rt2x00pci_register_write(rt2x00dev, offset, reg);
3060 +
3061 + /* Update WMM registers */
3062 + field.bit_offset = queue_idx * 4;
3063 + field.bit_mask = 0xf << field.bit_offset;
3064 +
3065 + rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3066 + rt2x00_set_field32(&reg, field, queue->aifs);
3067 + rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3068 +
3069 + rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3070 + rt2x00_set_field32(&reg, field, queue->cw_min);
3071 + rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3072 +
3073 + rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3074 + rt2x00_set_field32(&reg, field, queue->cw_max);
3075 + rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3076 +
3077 + /* Update EDCA registers */
3078 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3079 +
3080 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
3081 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3082 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3083 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3084 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3085 + rt2x00pci_register_write(rt2x00dev, offset, reg);
3086 +
3087 + return 0;
3088 +}
3089 +
3090 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
3091 +{
3092 + struct rt2x00_dev *rt2x00dev = hw->priv;
3093 + u64 tsf;
3094 + u32 reg;
3095 +
3096 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3097 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3098 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3099 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3100 +
3101 + return tsf;
3102 +}
3103 +
3104 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
3105 + .tx = rt2x00mac_tx,
3106 + .start = rt2x00mac_start,
3107 + .stop = rt2x00mac_stop,
3108 + .add_interface = rt2x00mac_add_interface,
3109 + .remove_interface = rt2x00mac_remove_interface,
3110 + .config = rt2x00mac_config,
3111 + .config_interface = rt2x00mac_config_interface,
3112 + .configure_filter = rt2x00mac_configure_filter,
3113 + .set_key = rt2x00mac_set_key,
3114 + .get_stats = rt2x00mac_get_stats,
3115 + .get_tkip_seq = rt2800pci_get_tkip_seq,
3116 + .set_rts_threshold = rt2800pci_set_rts_threshold,
3117 + .bss_info_changed = rt2x00mac_bss_info_changed,
3118 + .conf_tx = rt2800pci_conf_tx,
3119 + .get_tx_stats = rt2x00mac_get_tx_stats,
3120 + .get_tsf = rt2800pci_get_tsf,
3121 +};
3122 +
3123 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
3124 + .irq_handler = rt2800pci_interrupt,
3125 + .probe_hw = rt2800pci_probe_hw,
3126 + .get_firmware_name = rt2800pci_get_firmware_name,
3127 + .check_firmware = rt2800pci_check_firmware,
3128 + .load_firmware = rt2800pci_load_firmware,
3129 + .initialize = rt2x00pci_initialize,
3130 + .uninitialize = rt2x00pci_uninitialize,
3131 + .get_entry_state = rt2800pci_get_entry_state,
3132 + .clear_entry = rt2800pci_clear_entry,
3133 + .set_device_state = rt2800pci_set_device_state,
3134 + .rfkill_poll = rt2800pci_rfkill_poll,
3135 + .link_stats = rt2800pci_link_stats,
3136 + .reset_tuner = rt2800pci_reset_tuner,
3137 + .link_tuner = rt2800pci_link_tuner,
3138 + .write_tx_desc = rt2800pci_write_tx_desc,
3139 + .write_tx_data = rt2x00pci_write_tx_data,
3140 + .write_beacon = rt2800pci_write_beacon,
3141 + .kick_tx_queue = rt2800pci_kick_tx_queue,
3142 + .kill_tx_queue = rt2800pci_kill_tx_queue,
3143 + .fill_rxdone = rt2800pci_fill_rxdone,
3144 + .config_shared_key = rt2800pci_config_shared_key,
3145 + .config_pairwise_key = rt2800pci_config_pairwise_key,
3146 + .config_filter = rt2800pci_config_filter,
3147 + .config_intf = rt2800pci_config_intf,
3148 + .config_erp = rt2800pci_config_erp,
3149 + .config_ant = rt2800pci_config_ant,
3150 + .config = rt2800pci_config,
3151 +};
3152 +
3153 +static const struct data_queue_desc rt2800pci_queue_rx = {
3154 + .entry_num = RX_ENTRIES,
3155 + .data_size = AGGREGATION_SIZE,
3156 + .desc_size = RXD_DESC_SIZE,
3157 + .priv_size = sizeof(struct queue_entry_priv_pci),
3158 +};
3159 +
3160 +static const struct data_queue_desc rt2800pci_queue_tx = {
3161 + .entry_num = TX_ENTRIES,
3162 + .data_size = AGGREGATION_SIZE,
3163 + .desc_size = TXD_DESC_SIZE,
3164 + .priv_size = sizeof(struct queue_entry_priv_pci),
3165 +};
3166 +
3167 +static const struct data_queue_desc rt2800pci_queue_bcn = {
3168 + .entry_num = 8 * BEACON_ENTRIES,
3169 + .data_size = 0, /* No DMA required for beacons */
3170 + .desc_size = TXWI_DESC_SIZE,
3171 + .priv_size = sizeof(struct queue_entry_priv_pci),
3172 +};
3173 +
3174 +static const struct rt2x00_ops rt2800pci_ops = {
3175 + .name = KBUILD_MODNAME,
3176 + .max_sta_intf = 1,
3177 + .max_ap_intf = 8,
3178 + .eeprom_size = EEPROM_SIZE,
3179 + .rf_size = RF_SIZE,
3180 + .tx_queues = NUM_TX_QUEUES,
3181 + .rx = &rt2800pci_queue_rx,
3182 + .tx = &rt2800pci_queue_tx,
3183 + .bcn = &rt2800pci_queue_bcn,
3184 + .lib = &rt2800pci_rt2x00_ops,
3185 + .hw = &rt2800pci_mac80211_ops,
3186 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
3187 + .debugfs = &rt2800pci_rt2x00debug,
3188 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3189 +};
3190 +
3191 +/*
3192 + * RT2800pci module information.
3193 + */
3194 +static struct pci_device_id rt2800pci_device_table[] = {
3195 + { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
3196 + { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
3197 + { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
3198 + { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
3199 + { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
3200 + { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
3201 + { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
3202 + { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
3203 + { 0, }
3204 +};
3205 +
3206 +MODULE_AUTHOR(DRV_PROJECT);
3207 +MODULE_VERSION(DRV_VERSION);
3208 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
3209 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
3210 +#ifdef CONFIG_RT2800PCI_PCI
3211 +MODULE_FIRMWARE(FIRMWARE_RT2860);
3212 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
3213 +#endif /* CONFIG_RT2800PCI_PCI */
3214 +MODULE_LICENSE("GPL");
3215 +
3216 +#ifdef CONFIG_RT2800PCI_WISOC
3217 +#if defined(CONFIG_RALINK_RT288X)
3218 +__rt2x00soc_probe(RT2880, &rt2800pci_ops);
3219 +#elif defined(CONFIG_RALINK_RT305X)
3220 +__rt2x00soc_probe(RT3052, &rt2800pci_ops);
3221 +#endif
3222 +
3223 +static struct platform_driver rt2800soc_driver = {
3224 + .driver = {
3225 + .name = "rt2800_wmac",
3226 + .owner = THIS_MODULE,
3227 + .mod_name = KBUILD_MODNAME,
3228 + },
3229 + .probe = __rt2x00soc_probe,
3230 + .remove = __devexit_p(rt2x00soc_remove),
3231 + .suspend = rt2x00soc_suspend,
3232 + .resume = rt2x00soc_resume,
3233 +};
3234 +#endif /* CONFIG_RT2800PCI_WISOC */
3235 +
3236 +#ifdef CONFIG_RT2800PCI_PCI
3237 +static struct pci_driver rt2800pci_driver = {
3238 + .name = KBUILD_MODNAME,
3239 + .id_table = rt2800pci_device_table,
3240 + .probe = rt2x00pci_probe,
3241 + .remove = __devexit_p(rt2x00pci_remove),
3242 + .suspend = rt2x00pci_suspend,
3243 + .resume = rt2x00pci_resume,
3244 +};
3245 +#endif /* CONFIG_RT2800PCI_PCI */
3246 +
3247 +static int __init rt2800pci_init(void)
3248 +{
3249 + int ret = 0;
3250 +
3251 +#ifdef CONFIG_RT2800PCI_WISOC
3252 + ret = platform_driver_register(&rt2800soc_driver);
3253 + if (ret)
3254 + return ret;
3255 +#endif
3256 +#ifdef CONFIG_RT2800PCI_PCI
3257 + ret = pci_register_driver(&rt2800pci_driver);
3258 + if (ret) {
3259 +#ifdef CONFIG_RT2800PCI_WISOC
3260 + platform_driver_unregister(&rt2800soc_driver);
3261 +#endif
3262 + return ret;
3263 + }
3264 +#endif
3265 +
3266 + return ret;
3267 +}
3268 +
3269 +static void __exit rt2800pci_exit(void)
3270 +{
3271 +#ifdef CONFIG_RT2800PCI_PCI
3272 + pci_unregister_driver(&rt2800pci_driver);
3273 +#endif
3274 +#ifdef CONFIG_RT2800PCI_WISOC
3275 + platform_driver_unregister(&rt2800soc_driver);
3276 +#endif
3277 +}
3278 +
3279 +module_init(rt2800pci_init);
3280 +module_exit(rt2800pci_exit);
3281 --- /dev/null
3282 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
3283 @@ -0,0 +1,1927 @@
3284 +/*
3285 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3286 + <http://rt2x00.serialmonkey.com>
3287 +
3288 + This program is free software; you can redistribute it and/or modify
3289 + it under the terms of the GNU General Public License as published by
3290 + the Free Software Foundation; either version 2 of the License, or
3291 + (at your option) any later version.
3292 +
3293 + This program is distributed in the hope that it will be useful,
3294 + but WITHOUT ANY WARRANTY; without even the implied warranty of
3295 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3296 + GNU General Public License for more details.
3297 +
3298 + You should have received a copy of the GNU General Public License
3299 + along with this program; if not, write to the
3300 + Free Software Foundation, Inc.,
3301 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
3302 + */
3303 +
3304 +/*
3305 + Module: rt2800pci
3306 + Abstract: Data structures and registers for the rt2800pci module.
3307 + Supported chipsets: RT2800E & RT2800ED.
3308 + */
3309 +
3310 +#ifndef RT2800PCI_H
3311 +#define RT2800PCI_H
3312 +
3313 +/*
3314 + * RF chip defines.
3315 + *
3316 + * RF2820 2.4G 2T3R
3317 + * RF2850 2.4G/5G 2T3R
3318 + * RF2720 2.4G 1T2R
3319 + * RF2750 2.4G/5G 1T2R
3320 + * RF3020 2.4G 1T1R
3321 + * RF2020 2.4G B/G
3322 + * RF3021 2.4G 1T2R
3323 + * RF3022 2.4G 2T2R
3324 + */
3325 +#define RF2820 0x0001
3326 +#define RF2850 0x0002
3327 +#define RF2720 0x0003
3328 +#define RF2750 0x0004
3329 +#define RF3020 0x0005
3330 +#define RF2020 0x0006
3331 +#define RF3021 0x0007
3332 +#define RF3022 0x0008
3333 +
3334 +/*
3335 + * RT2860 version
3336 + */
3337 +#define RT2860C_VERSION 0x28600100
3338 +#define RT2860D_VERSION 0x28600101
3339 +#define RT2880E_VERSION 0x28720200
3340 +#define RT2883_VERSION 0x28830300
3341 +#define RT3070_VERSION 0x30700200
3342 +
3343 +/*
3344 + * Signal information.
3345 + * Defaul offset is required for RSSI <-> dBm conversion.
3346 + */
3347 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
3348 +
3349 +/*
3350 + * Register layout information.
3351 + */
3352 +#define CSR_REG_BASE 0x1000
3353 +#define CSR_REG_SIZE 0x0800
3354 +#define EEPROM_BASE 0x0000
3355 +#define EEPROM_SIZE 0x0110
3356 +#define BBP_BASE 0x0000
3357 +#define BBP_SIZE 0x0080
3358 +#define RF_BASE 0x0004
3359 +#define RF_SIZE 0x0010
3360 +
3361 +/*
3362 + * Number of TX queues.
3363 + */
3364 +#define NUM_TX_QUEUES 4
3365 +
3366 +/*
3367 + * PCI registers.
3368 + */
3369 +
3370 +/*
3371 + * E2PROM_CSR: EEPROM control register.
3372 + * RELOAD: Write 1 to reload eeprom content.
3373 + * TYPE: 0: 93c46, 1:93c66.
3374 + * LOAD_STATUS: 1:loading, 0:done.
3375 + */
3376 +#define E2PROM_CSR 0x0004
3377 +#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
3378 +#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
3379 +#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
3380 +#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
3381 +#define E2PROM_CSR_TYPE FIELD32(0x00000030)
3382 +#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
3383 +#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
3384 +
3385 +/*
3386 + * HOST-MCU shared memory
3387 + */
3388 +#define HOST_CMD_CSR 0x0404
3389 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
3390 +
3391 +/*
3392 + * INT_SOURCE_CSR: Interrupt source register.
3393 + * Write one to clear corresponding bit.
3394 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
3395 + */
3396 +#define INT_SOURCE_CSR 0x0200
3397 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
3398 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
3399 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
3400 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
3401 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
3402 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
3403 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
3404 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
3405 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
3406 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
3407 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
3408 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
3409 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
3410 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
3411 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
3412 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
3413 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
3414 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
3415 +
3416 +/*
3417 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
3418 + */
3419 +#define INT_MASK_CSR 0x0204
3420 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
3421 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
3422 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
3423 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
3424 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
3425 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
3426 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
3427 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
3428 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
3429 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
3430 +#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
3431 +#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
3432 +#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
3433 +#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
3434 +#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
3435 +#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
3436 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
3437 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
3438 +
3439 +/*
3440 + * WPDMA_GLO_CFG
3441 + */
3442 +#define WPDMA_GLO_CFG 0x0208
3443 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
3444 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
3445 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
3446 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
3447 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
3448 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
3449 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
3450 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
3451 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
3452 +
3453 +/*
3454 + * WPDMA_RST_IDX
3455 + */
3456 +#define WPDMA_RST_IDX 0x020c
3457 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
3458 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
3459 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
3460 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
3461 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
3462 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
3463 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
3464 +
3465 +/*
3466 + * DELAY_INT_CFG
3467 + */
3468 +#define DELAY_INT_CFG 0x0210
3469 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
3470 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
3471 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
3472 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
3473 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
3474 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
3475 +
3476 +/*
3477 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
3478 + * AIFSN0: AC_BE
3479 + * AIFSN1: AC_BK
3480 + * AIFSN1: AC_VI
3481 + * AIFSN1: AC_VO
3482 + */
3483 +#define WMM_AIFSN_CFG 0x0214
3484 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
3485 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
3486 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
3487 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
3488 +
3489 +/*
3490 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3491 + * CWMIN0: AC_BE
3492 + * CWMIN1: AC_BK
3493 + * CWMIN1: AC_VI
3494 + * CWMIN1: AC_VO
3495 + */
3496 +#define WMM_CWMIN_CFG 0x0218
3497 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
3498 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
3499 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
3500 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
3501 +
3502 +/*
3503 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3504 + * CWMAX0: AC_BE
3505 + * CWMAX1: AC_BK
3506 + * CWMAX1: AC_VI
3507 + * CWMAX1: AC_VO
3508 + */
3509 +#define WMM_CWMAX_CFG 0x021c
3510 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
3511 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
3512 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
3513 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
3514 +
3515 +/*
3516 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3517 + * AC0TXOP: AC_BK in unit of 32us
3518 + * AC1TXOP: AC_BE in unit of 32us
3519 + */
3520 +#define WMM_TXOP0_CFG 0x0220
3521 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
3522 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
3523 +
3524 +/*
3525 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3526 + * AC2TXOP: AC_VI in unit of 32us
3527 + * AC3TXOP: AC_VO in unit of 32us
3528 + */
3529 +#define WMM_TXOP1_CFG 0x0224
3530 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
3531 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
3532 +
3533 +/*
3534 + * GPIO_CTRL_CFG:
3535 + */
3536 +#define GPIO_CTRL_CFG 0x0228
3537 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
3538 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
3539 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
3540 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
3541 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
3542 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
3543 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
3544 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
3545 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
3546 +
3547 +/*
3548 + * MCU_CMD_CFG
3549 + */
3550 +#define MCU_CMD_CFG 0x022c
3551 +
3552 +/*
3553 + * AC_BK register offsets
3554 + */
3555 +#define TX_BASE_PTR0 0x0230
3556 +#define TX_MAX_CNT0 0x0234
3557 +#define TX_CTX_IDX0 0x0238
3558 +#define TX_DTX_IDX0 0x023c
3559 +
3560 +/*
3561 + * AC_BE register offsets
3562 + */
3563 +#define TX_BASE_PTR1 0x0240
3564 +#define TX_MAX_CNT1 0x0244
3565 +#define TX_CTX_IDX1 0x0248
3566 +#define TX_DTX_IDX1 0x024c
3567 +
3568 +/*
3569 + * AC_VI register offsets
3570 + */
3571 +#define TX_BASE_PTR2 0x0250
3572 +#define TX_MAX_CNT2 0x0254
3573 +#define TX_CTX_IDX2 0x0258
3574 +#define TX_DTX_IDX2 0x025c
3575 +
3576 +/*
3577 + * AC_VO register offsets
3578 + */
3579 +#define TX_BASE_PTR3 0x0260
3580 +#define TX_MAX_CNT3 0x0264
3581 +#define TX_CTX_IDX3 0x0268
3582 +#define TX_DTX_IDX3 0x026c
3583 +
3584 +/*
3585 + * HCCA register offsets
3586 + */
3587 +#define TX_BASE_PTR4 0x0270
3588 +#define TX_MAX_CNT4 0x0274
3589 +#define TX_CTX_IDX4 0x0278
3590 +#define TX_DTX_IDX4 0x027c
3591 +
3592 +/*
3593 + * MGMT register offsets
3594 + */
3595 +#define TX_BASE_PTR5 0x0280
3596 +#define TX_MAX_CNT5 0x0284
3597 +#define TX_CTX_IDX5 0x0288
3598 +#define TX_DTX_IDX5 0x028c
3599 +
3600 +/*
3601 + * Queue register offset macros
3602 + */
3603 +#define TX_QUEUE_REG_OFFSET 0x10
3604 +#define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
3605 +#define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
3606 +#define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3607 +#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3608 +
3609 +/*
3610 + * RX register offsets
3611 + */
3612 +#define RX_BASE_PTR 0x0290
3613 +#define RX_MAX_CNT 0x0294
3614 +#define RX_CRX_IDX 0x0298
3615 +#define RX_DRX_IDX 0x029c
3616 +
3617 +/*
3618 + * PBF_SYS_CTRL
3619 + * HOST_RAM_WRITE: enable Host program ram write selection
3620 + */
3621 +#define PBF_SYS_CTRL 0x0400
3622 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
3623 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
3624 +
3625 +/*
3626 + * PBF registers
3627 + * Most are for debug. Driver doesn't touch PBF register.
3628 + */
3629 +#define PBF_CFG 0x0408
3630 +#define PBF_MAX_PCNT 0x040c
3631 +#define PBF_CTRL 0x0410
3632 +#define PBF_INT_STA 0x0414
3633 +#define PBF_INT_ENA 0x0418
3634 +
3635 +/*
3636 + * BCN_OFFSET0:
3637 + */
3638 +#define BCN_OFFSET0 0x042c
3639 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
3640 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
3641 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
3642 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
3643 +
3644 +/*
3645 + * BCN_OFFSET1:
3646 + */
3647 +#define BCN_OFFSET1 0x0430
3648 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
3649 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
3650 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
3651 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
3652 +
3653 +/*
3654 + * PBF registers
3655 + * Most are for debug. Driver doesn't touch PBF register.
3656 + */
3657 +#define TXRXQ_PCNT 0x0438
3658 +#define PBF_DBG 0x043c
3659 +
3660 +/*
3661 + * RF registers
3662 + */
3663 +#define RF_CSR_CFG 0x0500
3664 +#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
3665 +#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
3666 +#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
3667 +#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
3668 +
3669 +/*
3670 + * MAC Control/Status Registers(CSR).
3671 + * Some values are set in TU, whereas 1 TU == 1024 us.
3672 + */
3673 +
3674 +/*
3675 + * MAC_CSR0: ASIC revision number.
3676 + * ASIC_REV: 0
3677 + * ASIC_VER: 2860
3678 + */
3679 +#define MAC_CSR0 0x1000
3680 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
3681 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
3682 +
3683 +/*
3684 + * MAC_SYS_CTRL:
3685 + */
3686 +#define MAC_SYS_CTRL 0x1004
3687 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
3688 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
3689 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
3690 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
3691 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
3692 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
3693 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
3694 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
3695 +
3696 +/*
3697 + * MAC_ADDR_DW0: STA MAC register 0
3698 + */
3699 +#define MAC_ADDR_DW0 0x1008
3700 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
3701 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
3702 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
3703 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
3704 +
3705 +/*
3706 + * MAC_ADDR_DW1: STA MAC register 1
3707 + * UNICAST_TO_ME_MASK:
3708 + * Used to mask off bits from byte 5 of the MAC address
3709 + * to determine the UNICAST_TO_ME bit for RX frames.
3710 + * The full mask is complemented by BSS_ID_MASK:
3711 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3712 + */
3713 +#define MAC_ADDR_DW1 0x100c
3714 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3715 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3716 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3717 +
3718 +/*
3719 + * MAC_BSSID_DW0: BSSID register 0
3720 + */
3721 +#define MAC_BSSID_DW0 0x1010
3722 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3723 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3724 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3725 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3726 +
3727 +/*
3728 + * MAC_BSSID_DW1: BSSID register 1
3729 + * BSS_ID_MASK:
3730 + * 0: 1-BSSID mode (BSS index = 0)
3731 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3732 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3733 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3734 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3735 + * BSSID. This will make sure that those bits will be ignored
3736 + * when determining the MY_BSS of RX frames.
3737 + */
3738 +#define MAC_BSSID_DW1 0x1014
3739 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3740 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3741 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3742 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3743 +
3744 +/*
3745 + * MAX_LEN_CFG: Maximum frame length register.
3746 + * MAX_MPDU: rt2860b max 16k bytes
3747 + * MAX_PSDU: Maximum PSDU length
3748 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3749 + */
3750 +#define MAX_LEN_CFG 0x1018
3751 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3752 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3753 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3754 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3755 +
3756 +/*
3757 + * BBP_CSR_CFG: BBP serial control register
3758 + * VALUE: Register value to program into BBP
3759 + * REG_NUM: Selected BBP register
3760 + * READ_CONTROL: 0 write BBP, 1 read BBP
3761 + * BUSY: ASIC is busy executing BBP commands
3762 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3763 + * BBP_RW_MODE: 0 serial, 1 paralell
3764 + */
3765 +#define BBP_CSR_CFG 0x101c
3766 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3767 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3768 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3769 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3770 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3771 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3772 +
3773 +/*
3774 + * RF_CSR_CFG0: RF control register
3775 + * REGID_AND_VALUE: Register value to program into RF
3776 + * BITWIDTH: Selected RF register
3777 + * STANDBYMODE: 0 high when standby, 1 low when standby
3778 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3779 + * BUSY: ASIC is busy executing RF commands
3780 + */
3781 +#define RF_CSR_CFG0 0x1020
3782 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3783 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3784 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3785 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3786 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3787 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3788 +
3789 +/*
3790 + * RF_CSR_CFG1: RF control register
3791 + * REGID_AND_VALUE: Register value to program into RF
3792 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3793 + * 0: 3 system clock cycle (37.5usec)
3794 + * 1: 5 system clock cycle (62.5usec)
3795 + */
3796 +#define RF_CSR_CFG1 0x1024
3797 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3798 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3799 +
3800 +/*
3801 + * RF_CSR_CFG2: RF control register
3802 + * VALUE: Register value to program into RF
3803 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3804 + * 0: 3 system clock cycle (37.5usec)
3805 + * 1: 5 system clock cycle (62.5usec)
3806 + */
3807 +#define RF_CSR_CFG2 0x1028
3808 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3809 +
3810 +/*
3811 + * LED_CFG: LED control
3812 + * color LED's:
3813 + * 0: off
3814 + * 1: blinking upon TX2
3815 + * 2: periodic slow blinking
3816 + * 3: always on
3817 + * LED polarity:
3818 + * 0: active low
3819 + * 1: active high
3820 + */
3821 +#define LED_CFG 0x102c
3822 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3823 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3824 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3825 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3826 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3827 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3828 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3829 +
3830 +/*
3831 + * XIFS_TIME_CFG: MAC timing
3832 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3833 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3834 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3835 + * when MAC doesn't reference BBP signal BBRXEND
3836 + * EIFS: unit 1us
3837 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3838 + *
3839 + */
3840 +#define XIFS_TIME_CFG 0x1100
3841 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3842 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3843 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3844 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3845 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3846 +
3847 +/*
3848 + * BKOFF_SLOT_CFG:
3849 + */
3850 +#define BKOFF_SLOT_CFG 0x1104
3851 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3852 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3853 +
3854 +/*
3855 + * NAV_TIME_CFG:
3856 + */
3857 +#define NAV_TIME_CFG 0x1108
3858 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3859 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3860 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3861 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3862 +
3863 +/*
3864 + * CH_TIME_CFG: count as channel busy
3865 + */
3866 +#define CH_TIME_CFG 0x110c
3867 +
3868 +/*
3869 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3870 + */
3871 +#define PBF_LIFE_TIMER 0x1110
3872 +
3873 +/*
3874 + * BCN_TIME_CFG:
3875 + * BEACON_INTERVAL: in unit of 1/16 TU
3876 + * TSF_TICKING: Enable TSF auto counting
3877 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3878 + * BEACON_GEN: Enable beacon generator
3879 + */
3880 +#define BCN_TIME_CFG 0x1114
3881 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3882 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3883 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3884 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3885 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3886 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3887 +
3888 +/*
3889 + * TBTT_SYNC_CFG:
3890 + */
3891 +#define TBTT_SYNC_CFG 0x1118
3892 +
3893 +/*
3894 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3895 + */
3896 +#define TSF_TIMER_DW0 0x111c
3897 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3898 +
3899 +/*
3900 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3901 + */
3902 +#define TSF_TIMER_DW1 0x1120
3903 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3904 +
3905 +/*
3906 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3907 + */
3908 +#define TBTT_TIMER 0x1124
3909 +
3910 +/*
3911 + * INT_TIMER_CFG:
3912 + */
3913 +#define INT_TIMER_CFG 0x1128
3914 +
3915 +/*
3916 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3917 + */
3918 +#define INT_TIMER_EN 0x112c
3919 +
3920 +/*
3921 + * CH_IDLE_STA: channel idle time
3922 + */
3923 +#define CH_IDLE_STA 0x1130
3924 +
3925 +/*
3926 + * CH_BUSY_STA: channel busy time
3927 + */
3928 +#define CH_BUSY_STA 0x1134
3929 +
3930 +/*
3931 + * MAC_STATUS_CFG:
3932 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3933 + * if 1 or higher one of the 2 registers is busy.
3934 + */
3935 +#define MAC_STATUS_CFG 0x1200
3936 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3937 +
3938 +/*
3939 + * PWR_PIN_CFG:
3940 + */
3941 +#define PWR_PIN_CFG 0x1204
3942 +
3943 +/*
3944 + * AUTOWAKEUP_CFG: Manual power control / status register
3945 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3946 + * AUTOWAKE: 0:sleep, 1:awake
3947 + */
3948 +#define AUTOWAKEUP_CFG 0x1208
3949 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3950 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3951 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3952 +
3953 +/*
3954 + * EDCA_AC0_CFG:
3955 + */
3956 +#define EDCA_AC0_CFG 0x1300
3957 +#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
3958 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3959 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3960 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3961 +
3962 +/*
3963 + * EDCA_AC1_CFG:
3964 + */
3965 +#define EDCA_AC1_CFG 0x1304
3966 +#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
3967 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3968 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3969 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3970 +
3971 +/*
3972 + * EDCA_AC2_CFG:
3973 + */
3974 +#define EDCA_AC2_CFG 0x1308
3975 +#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
3976 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3977 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3978 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3979 +
3980 +/*
3981 + * EDCA_AC3_CFG:
3982 + */
3983 +#define EDCA_AC3_CFG 0x130c
3984 +#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
3985 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3986 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3987 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3988 +
3989 +/*
3990 + * EDCA_TID_AC_MAP:
3991 + */
3992 +#define EDCA_TID_AC_MAP 0x1310
3993 +
3994 +/*
3995 + * TX_PWR_CFG_0:
3996 + */
3997 +#define TX_PWR_CFG_0 0x1314
3998 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3999 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
4000 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
4001 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
4002 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
4003 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
4004 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
4005 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
4006 +
4007 +/*
4008 + * TX_PWR_CFG_1:
4009 + */
4010 +#define TX_PWR_CFG_1 0x1318
4011 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
4012 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
4013 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
4014 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
4015 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
4016 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
4017 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
4018 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
4019 +
4020 +/*
4021 + * TX_PWR_CFG_2:
4022 + */
4023 +#define TX_PWR_CFG_2 0x131c
4024 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
4025 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
4026 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
4027 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
4028 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
4029 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
4030 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
4031 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
4032 +
4033 +/*
4034 + * TX_PWR_CFG_3:
4035 + */
4036 +#define TX_PWR_CFG_3 0x1320
4037 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
4038 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
4039 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
4040 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
4041 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
4042 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
4043 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
4044 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
4045 +
4046 +/*
4047 + * TX_PWR_CFG_4:
4048 + */
4049 +#define TX_PWR_CFG_4 0x1324
4050 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
4051 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
4052 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
4053 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
4054 +
4055 +/*
4056 + * TX_PIN_CFG:
4057 + */
4058 +#define TX_PIN_CFG 0x1328
4059 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
4060 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
4061 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
4062 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
4063 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
4064 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
4065 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
4066 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
4067 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
4068 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
4069 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
4070 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
4071 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
4072 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
4073 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
4074 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
4075 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
4076 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
4077 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
4078 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
4079 +
4080 +/*
4081 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
4082 + */
4083 +#define TX_BAND_CFG 0x132c
4084 +#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
4085 +#define TX_BAND_CFG_A FIELD32(0x00000002)
4086 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
4087 +
4088 +/*
4089 + * TX_SW_CFG0:
4090 + */
4091 +#define TX_SW_CFG0 0x1330
4092 +
4093 +/*
4094 + * TX_SW_CFG1:
4095 + */
4096 +#define TX_SW_CFG1 0x1334
4097 +
4098 +/*
4099 + * TX_SW_CFG2:
4100 + */
4101 +#define TX_SW_CFG2 0x1338
4102 +
4103 +/*
4104 + * TXOP_THRES_CFG:
4105 + */
4106 +#define TXOP_THRES_CFG 0x133c
4107 +
4108 +/*
4109 + * TXOP_CTRL_CFG:
4110 + */
4111 +#define TXOP_CTRL_CFG 0x1340
4112 +
4113 +/*
4114 + * TX_RTS_CFG:
4115 + * RTS_THRES: unit:byte
4116 + * RTS_FBK_EN: enable rts rate fallback
4117 + */
4118 +#define TX_RTS_CFG 0x1344
4119 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
4120 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
4121 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
4122 +
4123 +/*
4124 + * TX_TIMEOUT_CFG:
4125 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
4126 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
4127 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
4128 + * it is recommended that:
4129 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
4130 + */
4131 +#define TX_TIMEOUT_CFG 0x1348
4132 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
4133 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
4134 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
4135 +
4136 +/*
4137 + * TX_RTY_CFG:
4138 + * SHORT_RTY_LIMIT: short retry limit
4139 + * LONG_RTY_LIMIT: long retry limit
4140 + * LONG_RTY_THRE: Long retry threshoold
4141 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
4142 + * 0:expired by retry limit, 1: expired by mpdu life timer
4143 + * AGG_RTY_MODE: Aggregate MPDU retry mode
4144 + * 0:expired by retry limit, 1: expired by mpdu life timer
4145 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
4146 + */
4147 +#define TX_RTY_CFG 0x134c
4148 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
4149 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
4150 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
4151 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
4152 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
4153 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
4154 +
4155 +/*
4156 + * TX_LINK_CFG:
4157 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
4158 + * MFB_ENABLE: TX apply remote MFB 1:enable
4159 + * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
4160 + * 0: not apply remote remote unsolicit (MFS=7)
4161 + * TX_MRQ_EN: MCS request TX enable
4162 + * TX_RDG_EN: RDG TX enable
4163 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
4164 + * REMOTE_MFB: remote MCS feedback
4165 + * REMOTE_MFS: remote MCS feedback sequence number
4166 + */
4167 +#define TX_LINK_CFG 0x1350
4168 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
4169 +#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
4170 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
4171 +#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
4172 +#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
4173 +#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
4174 +#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
4175 +#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
4176 +
4177 +/*
4178 + * HT_FBK_CFG0:
4179 + */
4180 +#define HT_FBK_CFG0 0x1354
4181 +#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
4182 +#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
4183 +#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
4184 +#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
4185 +#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
4186 +#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
4187 +#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
4188 +#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
4189 +
4190 +/*
4191 + * HT_FBK_CFG1:
4192 + */
4193 +#define HT_FBK_CFG1 0x1358
4194 +#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
4195 +#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
4196 +#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
4197 +#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
4198 +#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
4199 +#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
4200 +#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
4201 +#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
4202 +
4203 +/*
4204 + * LG_FBK_CFG0:
4205 + */
4206 +#define LG_FBK_CFG0 0x135c
4207 +#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
4208 +#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
4209 +#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
4210 +#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
4211 +#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
4212 +#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
4213 +#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
4214 +#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
4215 +
4216 +/*
4217 + * LG_FBK_CFG1:
4218 + */
4219 +#define LG_FBK_CFG1 0x1360
4220 +#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
4221 +#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
4222 +#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
4223 +#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
4224 +
4225 +/*
4226 + * CCK_PROT_CFG: CCK Protection
4227 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
4228 + * PROTECT_CTRL: Protection control frame type for CCK TX
4229 + * 0:none, 1:RTS/CTS, 2:CTS-to-self
4230 + * PROTECT_NAV: TXOP protection type for CCK TX
4231 + * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
4232 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
4233 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
4234 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
4235 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
4236 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
4237 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
4238 + * RTS_TH_EN: RTS threshold enable on CCK TX
4239 + */
4240 +#define CCK_PROT_CFG 0x1364
4241 +#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4242 +#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4243 +#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4244 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4245 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4246 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4247 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4248 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4249 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4250 +#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4251 +
4252 +/*
4253 + * OFDM_PROT_CFG: OFDM Protection
4254 + */
4255 +#define OFDM_PROT_CFG 0x1368
4256 +#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4257 +#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4258 +#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4259 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4260 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4261 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4262 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4263 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4264 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4265 +#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4266 +
4267 +/*
4268 + * MM20_PROT_CFG: MM20 Protection
4269 + */
4270 +#define MM20_PROT_CFG 0x136c
4271 +#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4272 +#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4273 +#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4274 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4275 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4276 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4277 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4278 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4279 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4280 +#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4281 +
4282 +/*
4283 + * MM40_PROT_CFG: MM40 Protection
4284 + */
4285 +#define MM40_PROT_CFG 0x1370
4286 +#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4287 +#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4288 +#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4289 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4290 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4291 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4292 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4293 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4294 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4295 +#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4296 +
4297 +/*
4298 + * GF20_PROT_CFG: GF20 Protection
4299 + */
4300 +#define GF20_PROT_CFG 0x1374
4301 +#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4302 +#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4303 +#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4304 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4305 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4306 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4307 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4308 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4309 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4310 +#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4311 +
4312 +/*
4313 + * GF40_PROT_CFG: GF40 Protection
4314 + */
4315 +#define GF40_PROT_CFG 0x1378
4316 +#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4317 +#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4318 +#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4319 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4320 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4321 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4322 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4323 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4324 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4325 +#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4326 +
4327 +/*
4328 + * EXP_CTS_TIME:
4329 + */
4330 +#define EXP_CTS_TIME 0x137c
4331 +
4332 +/*
4333 + * EXP_ACK_TIME:
4334 + */
4335 +#define EXP_ACK_TIME 0x1380
4336 +
4337 +/*
4338 + * RX_FILTER_CFG: RX configuration register.
4339 + */
4340 +#define RX_FILTER_CFG 0x1400
4341 +#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
4342 +#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
4343 +#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
4344 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
4345 +#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
4346 +#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
4347 +#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
4348 +#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
4349 +#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
4350 +#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
4351 +#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
4352 +#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
4353 +#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
4354 +#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
4355 +#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
4356 +#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
4357 +#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
4358 +
4359 +/*
4360 + * AUTO_RSP_CFG:
4361 + * AUTORESPONDER: 0: disable, 1: enable
4362 + * BAC_ACK_POLICY: 0:long, 1:short preamble
4363 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
4364 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
4365 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
4366 + * DUAL_CTS_EN: Power bit value in control frame
4367 + * ACK_CTS_PSM_BIT:Power bit value in control frame
4368 + */
4369 +#define AUTO_RSP_CFG 0x1404
4370 +#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
4371 +#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
4372 +#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
4373 +#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
4374 +#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
4375 +#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
4376 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
4377 +
4378 +/*
4379 + * LEGACY_BASIC_RATE:
4380 + */
4381 +#define LEGACY_BASIC_RATE 0x1408
4382 +
4383 +/*
4384 + * HT_BASIC_RATE:
4385 + */
4386 +#define HT_BASIC_RATE 0x140c
4387 +
4388 +/*
4389 + * HT_CTRL_CFG:
4390 + */
4391 +#define HT_CTRL_CFG 0x1410
4392 +
4393 +/*
4394 + * SIFS_COST_CFG:
4395 + */
4396 +#define SIFS_COST_CFG 0x1414
4397 +
4398 +/*
4399 + * RX_PARSER_CFG:
4400 + * Set NAV for all received frames
4401 + */
4402 +#define RX_PARSER_CFG 0x1418
4403 +
4404 +/*
4405 + * TX_SEC_CNT0:
4406 + */
4407 +#define TX_SEC_CNT0 0x1500
4408 +
4409 +/*
4410 + * RX_SEC_CNT0:
4411 + */
4412 +#define RX_SEC_CNT0 0x1504
4413 +
4414 +/*
4415 + * CCMP_FC_MUTE:
4416 + */
4417 +#define CCMP_FC_MUTE 0x1508
4418 +
4419 +/*
4420 + * TXOP_HLDR_ADDR0:
4421 + */
4422 +#define TXOP_HLDR_ADDR0 0x1600
4423 +
4424 +/*
4425 + * TXOP_HLDR_ADDR1:
4426 + */
4427 +#define TXOP_HLDR_ADDR1 0x1604
4428 +
4429 +/*
4430 + * TXOP_HLDR_ET:
4431 + */
4432 +#define TXOP_HLDR_ET 0x1608
4433 +
4434 +/*
4435 + * QOS_CFPOLL_RA_DW0:
4436 + */
4437 +#define QOS_CFPOLL_RA_DW0 0x160c
4438 +
4439 +/*
4440 + * QOS_CFPOLL_RA_DW1:
4441 + */
4442 +#define QOS_CFPOLL_RA_DW1 0x1610
4443 +
4444 +/*
4445 + * QOS_CFPOLL_QC:
4446 + */
4447 +#define QOS_CFPOLL_QC 0x1614
4448 +
4449 +/*
4450 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
4451 + */
4452 +#define RX_STA_CNT0 0x1700
4453 +#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
4454 +#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
4455 +
4456 +/*
4457 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
4458 + */
4459 +#define RX_STA_CNT1 0x1704
4460 +#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
4461 +#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
4462 +
4463 +/*
4464 + * RX_STA_CNT2:
4465 + */
4466 +#define RX_STA_CNT2 0x1708
4467 +#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
4468 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
4469 +
4470 +/*
4471 + * TX_STA_CNT0: TX Beacon count
4472 + */
4473 +#define TX_STA_CNT0 0x170c
4474 +#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
4475 +#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
4476 +
4477 +/*
4478 + * TX_STA_CNT1: TX tx count
4479 + */
4480 +#define TX_STA_CNT1 0x1710
4481 +#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
4482 +#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
4483 +
4484 +/*
4485 + * TX_STA_CNT2: TX tx count
4486 + */
4487 +#define TX_STA_CNT2 0x1714
4488 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
4489 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
4490 +
4491 +/*
4492 + * TX_STA_FIFO: TX Result for specific PID status fifo register
4493 + */
4494 +#define TX_STA_FIFO 0x1718
4495 +#define TX_STA_FIFO_VALID FIELD32(0x00000001)
4496 +#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
4497 +#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
4498 +#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
4499 +#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
4500 +#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
4501 +#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
4502 +
4503 +/*
4504 + * TX_AGG_CNT: Debug counter
4505 + */
4506 +#define TX_AGG_CNT 0x171c
4507 +#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
4508 +#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
4509 +
4510 +/*
4511 + * TX_AGG_CNT0:
4512 + */
4513 +#define TX_AGG_CNT0 0x1720
4514 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
4515 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
4516 +
4517 +/*
4518 + * TX_AGG_CNT1:
4519 + */
4520 +#define TX_AGG_CNT1 0x1724
4521 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
4522 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
4523 +
4524 +/*
4525 + * TX_AGG_CNT2:
4526 + */
4527 +#define TX_AGG_CNT2 0x1728
4528 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
4529 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
4530 +
4531 +/*
4532 + * TX_AGG_CNT3:
4533 + */
4534 +#define TX_AGG_CNT3 0x172c
4535 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
4536 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
4537 +
4538 +/*
4539 + * TX_AGG_CNT4:
4540 + */
4541 +#define TX_AGG_CNT4 0x1730
4542 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
4543 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
4544 +
4545 +/*
4546 + * TX_AGG_CNT5:
4547 + */
4548 +#define TX_AGG_CNT5 0x1734
4549 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
4550 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
4551 +
4552 +/*
4553 + * TX_AGG_CNT6:
4554 + */
4555 +#define TX_AGG_CNT6 0x1738
4556 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
4557 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
4558 +
4559 +/*
4560 + * TX_AGG_CNT7:
4561 + */
4562 +#define TX_AGG_CNT7 0x173c
4563 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
4564 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
4565 +
4566 +/*
4567 + * MPDU_DENSITY_CNT:
4568 + * TX_ZERO_DEL: TX zero length delimiter count
4569 + * RX_ZERO_DEL: RX zero length delimiter count
4570 + */
4571 +#define MPDU_DENSITY_CNT 0x1740
4572 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
4573 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
4574 +
4575 +/*
4576 + * Security key table memory.
4577 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4578 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4579 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4580 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4581 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4582 + * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
4583 + */
4584 +#define MAC_WCID_BASE 0x1800
4585 +#define PAIRWISE_KEY_TABLE_BASE 0x4000
4586 +#define MAC_IVEIV_TABLE_BASE 0x6000
4587 +#define MAC_WCID_ATTRIBUTE_BASE 0x6800
4588 +#define SHARED_KEY_TABLE_BASE 0x6c00
4589 +#define SHARED_KEY_MODE_BASE 0x7000
4590 +
4591 +#define MAC_WCID_ENTRY(__idx) \
4592 + ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
4593 +#define PAIRWISE_KEY_ENTRY(__idx) \
4594 + ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4595 +#define MAC_IVEIV_ENTRY(__idx) \
4596 + ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
4597 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4598 + ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4599 +#define SHARED_KEY_ENTRY(__idx) \
4600 + ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4601 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4602 + ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4603 +
4604 +struct mac_wcid_entry {
4605 + u8 mac[6];
4606 + u8 reserved[2];
4607 +} __attribute__ ((packed));
4608 +
4609 +struct hw_key_entry {
4610 + u8 key[16];
4611 + u8 tx_mic[8];
4612 + u8 rx_mic[8];
4613 +} __attribute__ ((packed));
4614 +
4615 +struct mac_iveiv_entry {
4616 + u8 iv[8];
4617 +} __attribute__ ((packed));
4618 +
4619 +/*
4620 + * MAC_WCID_ATTRIBUTE:
4621 + */
4622 +#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
4623 +#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
4624 +#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
4625 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
4626 +
4627 +/*
4628 + * SHARED_KEY_MODE:
4629 + */
4630 +#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
4631 +#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
4632 +#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
4633 +#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
4634 +#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
4635 +#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
4636 +#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
4637 +#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
4638 +
4639 +/*
4640 + * HOST-MCU communication
4641 + */
4642 +
4643 +/*
4644 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4645 + */
4646 +#define H2M_MAILBOX_CSR 0x7010
4647 +#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
4648 +#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
4649 +#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
4650 +#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
4651 +
4652 +/*
4653 + * H2M_MAILBOX_CID:
4654 + */
4655 +#define H2M_MAILBOX_CID 0x7014
4656 +#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
4657 +#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
4658 +#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
4659 +#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
4660 +
4661 +/*
4662 + * H2M_MAILBOX_STATUS:
4663 + */
4664 +#define H2M_MAILBOX_STATUS 0x701c
4665 +
4666 +/*
4667 + * H2M_INT_SRC:
4668 + */
4669 +#define H2M_INT_SRC 0x7024
4670 +
4671 +/*
4672 + * H2M_BBP_AGENT:
4673 + */
4674 +#define H2M_BBP_AGENT 0x7028
4675 +
4676 +/*
4677 + * MCU_LEDCS: LED control for MCU Mailbox.
4678 + */
4679 +#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
4680 +#define MCU_LEDCS_POLARITY FIELD8(0x01)
4681 +
4682 +/*
4683 + * HW_CS_CTS_BASE:
4684 + * Carrier-sense CTS frame base address.
4685 + * It's where mac stores carrier-sense frame for carrier-sense function.
4686 + */
4687 +#define HW_CS_CTS_BASE 0x7700
4688 +
4689 +/*
4690 + * HW_DFS_CTS_BASE:
4691 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4692 + */
4693 +#define HW_DFS_CTS_BASE 0x7780
4694 +
4695 +/*
4696 + * TXRX control registers - base address 0x3000
4697 + */
4698 +
4699 +/*
4700 + * TXRX_CSR1:
4701 + * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4702 + */
4703 +#define TXRX_CSR1 0x77d0
4704 +
4705 +/*
4706 + * HW_DEBUG_SETTING_BASE:
4707 + * since NULL frame won't be that long (256 byte)
4708 + * We steal 16 tail bytes to save debugging settings
4709 + */
4710 +#define HW_DEBUG_SETTING_BASE 0x77f0
4711 +#define HW_DEBUG_SETTING_BASE2 0x7770
4712 +
4713 +/*
4714 + * HW_BEACON_BASE
4715 + * In order to support maximum 8 MBSS and its maximum length
4716 + * is 512 bytes for each beacon
4717 + * Three section discontinue memory segments will be used.
4718 + * 1. The original region for BCN 0~3
4719 + * 2. Extract memory from FCE table for BCN 4~5
4720 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4721 + * It occupied those memory of wcid 238~253 for BCN 6
4722 + * and wcid 222~237 for BCN 7
4723 + *
4724 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4725 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4726 + */
4727 +#define HW_BEACON_BASE0 0x7800
4728 +#define HW_BEACON_BASE1 0x7a00
4729 +#define HW_BEACON_BASE2 0x7c00
4730 +#define HW_BEACON_BASE3 0x7e00
4731 +#define HW_BEACON_BASE4 0x7200
4732 +#define HW_BEACON_BASE5 0x7400
4733 +#define HW_BEACON_BASE6 0x5dc0
4734 +#define HW_BEACON_BASE7 0x5bc0
4735 +
4736 +#define HW_BEACON_OFFSET(__index) \
4737 + ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4738 + (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4739 + (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4740 +
4741 +/*
4742 + * 8051 firmware image.
4743 + */
4744 +#define FIRMWARE_RT2860 "rt2860.bin"
4745 +#define FIRMWARE_IMAGE_BASE 0x2000
4746 +
4747 +/*
4748 + * BBP registers.
4749 + * The wordsize of the BBP is 8 bits.
4750 + */
4751 +
4752 +/*
4753 + * BBP 1: TX Antenna
4754 + */
4755 +#define BBP1_TX_POWER FIELD8(0x07)
4756 +#define BBP1_TX_ANTENNA FIELD8(0x18)
4757 +
4758 +/*
4759 + * BBP 3: RX Antenna
4760 + */
4761 +#define BBP3_RX_ANTENNA FIELD8(0x18)
4762 +#define BBP3_HT40_PLUS FIELD8(0x20)
4763 +
4764 +/*
4765 + * BBP 4: Bandwidth
4766 + */
4767 +#define BBP4_TX_BF FIELD8(0x01)
4768 +#define BBP4_BANDWIDTH FIELD8(0x18)
4769 +
4770 +/*
4771 + * RFCSR registers
4772 + * The wordsize of the RFCSR is 8 bits.
4773 + */
4774 +
4775 +/*
4776 + * RFCSR 6:
4777 + */
4778 +#define RFCSR6_R FIELD8(0x03)
4779 +
4780 +/*
4781 + * RFCSR 7:
4782 + */
4783 +#define RFCSR7_RF_TUNING FIELD8(0x01)
4784 +
4785 +/*
4786 + * RFCSR 12:
4787 + */
4788 +#define RFCSR12_TX_POWER FIELD8(0x1f)
4789 +
4790 +/*
4791 + * RFCSR 22:
4792 + */
4793 +#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
4794 +
4795 +/*
4796 + * RFCSR 23:
4797 + */
4798 +#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
4799 +
4800 +/*
4801 + * RFCSR 30:
4802 + */
4803 +#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
4804 +
4805 +/*
4806 + * RF registers
4807 + */
4808 +
4809 +/*
4810 + * RF 2
4811 + */
4812 +#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
4813 +#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
4814 +#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
4815 +
4816 +/*
4817 + * RF 3
4818 + */
4819 +#define RF3_TXPOWER_G FIELD32(0x00003e00)
4820 +#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
4821 +#define RF3_TXPOWER_A FIELD32(0x00003c00)
4822 +
4823 +/*
4824 + * RF 4
4825 + */
4826 +#define RF4_TXPOWER_G FIELD32(0x000007c0)
4827 +#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
4828 +#define RF4_TXPOWER_A FIELD32(0x00000780)
4829 +#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
4830 +#define RF4_HT40 FIELD32(0x00200000)
4831 +
4832 +/*
4833 + * EEPROM content.
4834 + * The wordsize of the EEPROM is 16 bits.
4835 + */
4836 +
4837 +/*
4838 + * EEPROM Version
4839 + */
4840 +#define EEPROM_VERSION 0x0001
4841 +#define EEPROM_VERSION_FAE FIELD16(0x00ff)
4842 +#define EEPROM_VERSION_VERSION FIELD16(0xff00)
4843 +
4844 +/*
4845 + * HW MAC address.
4846 + */
4847 +#define EEPROM_MAC_ADDR_0 0x0002
4848 +#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
4849 +#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
4850 +#define EEPROM_MAC_ADDR_1 0x0003
4851 +#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
4852 +#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
4853 +#define EEPROM_MAC_ADDR_2 0x0004
4854 +#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
4855 +#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
4856 +
4857 +/*
4858 + * EEPROM ANTENNA config
4859 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4860 + * TXPATH: 1: 1T, 2: 2T
4861 + */
4862 +#define EEPROM_ANTENNA 0x001a
4863 +#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
4864 +#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
4865 +#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
4866 +
4867 +/*
4868 + * EEPROM NIC config
4869 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4870 + */
4871 +#define EEPROM_NIC 0x001b
4872 +#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
4873 +#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
4874 +#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
4875 +#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
4876 +#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
4877 +#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
4878 +#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
4879 +#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
4880 +#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
4881 +#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
4882 +
4883 +/*
4884 + * EEPROM frequency
4885 + */
4886 +#define EEPROM_FREQ 0x001d
4887 +#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
4888 +#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
4889 +#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
4890 +
4891 +/*
4892 + * EEPROM LED
4893 + * POLARITY_RDY_G: Polarity RDY_G setting.
4894 + * POLARITY_RDY_A: Polarity RDY_A setting.
4895 + * POLARITY_ACT: Polarity ACT setting.
4896 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4897 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4898 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4899 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4900 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4901 + * LED_MODE: Led mode.
4902 + */
4903 +#define EEPROM_LED1 0x001e
4904 +#define EEPROM_LED2 0x001f
4905 +#define EEPROM_LED3 0x0020
4906 +#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
4907 +#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
4908 +#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
4909 +#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
4910 +#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
4911 +#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
4912 +#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
4913 +#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
4914 +#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
4915 +
4916 +/*
4917 + * EEPROM LNA
4918 + */
4919 +#define EEPROM_LNA 0x0022
4920 +#define EEPROM_LNA_BG FIELD16(0x00ff)
4921 +#define EEPROM_LNA_A0 FIELD16(0xff00)
4922 +
4923 +/*
4924 + * EEPROM RSSI BG offset
4925 + */
4926 +#define EEPROM_RSSI_BG 0x0023
4927 +#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
4928 +#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
4929 +
4930 +/*
4931 + * EEPROM RSSI BG2 offset
4932 + */
4933 +#define EEPROM_RSSI_BG2 0x0024
4934 +#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
4935 +#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
4936 +
4937 +/*
4938 + * EEPROM RSSI A offset
4939 + */
4940 +#define EEPROM_RSSI_A 0x0025
4941 +#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
4942 +#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
4943 +
4944 +/*
4945 + * EEPROM RSSI A2 offset
4946 + */
4947 +#define EEPROM_RSSI_A2 0x0026
4948 +#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
4949 +#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
4950 +
4951 +/*
4952 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4953 + * This is delta in 40MHZ.
4954 + * VALUE: Tx Power dalta value (MAX=4)
4955 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4956 + * TXPOWER: Enable:
4957 + */
4958 +#define EEPROM_TXPOWER_DELTA 0x0028
4959 +#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
4960 +#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
4961 +#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
4962 +
4963 +/*
4964 + * EEPROM TXPOWER 802.11BG
4965 + */
4966 +#define EEPROM_TXPOWER_BG1 0x0029
4967 +#define EEPROM_TXPOWER_BG2 0x0030
4968 +#define EEPROM_TXPOWER_BG_SIZE 7
4969 +#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
4970 +#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
4971 +
4972 +/*
4973 + * EEPROM TXPOWER 802.11A
4974 + */
4975 +#define EEPROM_TXPOWER_A1 0x003c
4976 +#define EEPROM_TXPOWER_A2 0x0053
4977 +#define EEPROM_TXPOWER_A_SIZE 6
4978 +#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
4979 +#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
4980 +
4981 +/*
4982 + * EEPROM TXpower byrate: 20MHZ power
4983 + */
4984 +#define EEPROM_TXPOWER_BYRATE 0x006f
4985 +
4986 +/*
4987 + * EEPROM BBP.
4988 + */
4989 +#define EEPROM_BBP_START 0x0078
4990 +#define EEPROM_BBP_SIZE 16
4991 +#define EEPROM_BBP_VALUE FIELD16(0x00ff)
4992 +#define EEPROM_BBP_REG_ID FIELD16(0xff00)
4993 +
4994 +/*
4995 + * MCU mailbox commands.
4996 + */
4997 +#define MCU_SLEEP 0x30
4998 +#define MCU_WAKEUP 0x31
4999 +#define MCU_RADIO_OFF 0x35
5000 +#define MCU_LED 0x50
5001 +#define MCU_LED_STRENGTH 0x51
5002 +#define MCU_LED_1 0x52
5003 +#define MCU_LED_2 0x53
5004 +#define MCU_LED_3 0x54
5005 +#define MCU_RADAR 0x60
5006 +#define MCU_BOOT_SIGNAL 0x72
5007 +#define MCU_BBP_SIGNAL 0x80
5008 +
5009 +/*
5010 + * MCU mailbox tokens
5011 + */
5012 +#define TOKEN_WAKUP 3
5013 +
5014 +/*
5015 + * DMA descriptor defines.
5016 + */
5017 +#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
5018 +#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
5019 +#define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
5020 +#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
5021 +
5022 +/*
5023 + * TX descriptor format for TX, PRIO and Beacon Ring.
5024 + */
5025 +
5026 +/*
5027 + * Word0
5028 + */
5029 +#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
5030 +
5031 +/*
5032 + * Word1
5033 + */
5034 +#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
5035 +#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
5036 +#define TXD_W1_BURST FIELD32(0x00008000)
5037 +#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
5038 +#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
5039 +#define TXD_W1_DMA_DONE FIELD32(0x80000000)
5040 +
5041 +/*
5042 + * Word2
5043 + */
5044 +#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
5045 +
5046 +/*
5047 + * Word3
5048 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
5049 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
5050 + * 0:MGMT, 1:HCCA 2:EDCA
5051 + */
5052 +#define TXD_W3_WIV FIELD32(0x01000000)
5053 +#define TXD_W3_QSEL FIELD32(0x06000000)
5054 +#define TXD_W3_TCO FIELD32(0x20000000)
5055 +#define TXD_W3_UCO FIELD32(0x40000000)
5056 +#define TXD_W3_ICO FIELD32(0x80000000)
5057 +
5058 +/*
5059 + * TX WI structure
5060 + */
5061 +
5062 +/*
5063 + * Word0
5064 + * FRAG: 1 To inform TKIP engine this is a fragment.
5065 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
5066 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
5067 + * BW: Channel bandwidth 20MHz or 40 MHz
5068 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
5069 + */
5070 +#define TXWI_W0_FRAG FIELD32(0x00000001)
5071 +#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
5072 +#define TXWI_W0_CF_ACK FIELD32(0x00000004)
5073 +#define TXWI_W0_TS FIELD32(0x00000008)
5074 +#define TXWI_W0_AMPDU FIELD32(0x00000010)
5075 +#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
5076 +#define TXWI_W0_TX_OP FIELD32(0x00000300)
5077 +#define TXWI_W0_MCS FIELD32(0x007f0000)
5078 +#define TXWI_W0_BW FIELD32(0x00800000)
5079 +#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
5080 +#define TXWI_W0_STBC FIELD32(0x06000000)
5081 +#define TXWI_W0_IFS FIELD32(0x08000000)
5082 +#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
5083 +
5084 +/*
5085 + * Word1
5086 + */
5087 +#define TXWI_W1_ACK FIELD32(0x00000001)
5088 +#define TXWI_W1_NSEQ FIELD32(0x00000002)
5089 +#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
5090 +#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
5091 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
5092 +#define TXWI_W1_PACKETID FIELD32(0xf0000000)
5093 +
5094 +/*
5095 + * Word2
5096 + */
5097 +#define TXWI_W2_IV FIELD32(0xffffffff)
5098 +
5099 +/*
5100 + * Word3
5101 + */
5102 +#define TXWI_W3_EIV FIELD32(0xffffffff)
5103 +
5104 +/*
5105 + * RX descriptor format for RX Ring.
5106 + */
5107 +
5108 +/*
5109 + * Word0
5110 + */
5111 +#define RXD_W0_SDP0 FIELD32(0xffffffff)
5112 +
5113 +/*
5114 + * Word1
5115 + */
5116 +#define RXD_W1_SDL1 FIELD32(0x00003fff)
5117 +#define RXD_W1_SDL0 FIELD32(0x3fff0000)
5118 +#define RXD_W1_LS0 FIELD32(0x40000000)
5119 +#define RXD_W1_DMA_DONE FIELD32(0x80000000)
5120 +
5121 +/*
5122 + * Word2
5123 + */
5124 +#define RXD_W2_SDP1 FIELD32(0xffffffff)
5125 +
5126 +/*
5127 + * Word3
5128 + * AMSDU: RX with 802.3 header, not 802.11 header.
5129 + * DECRYPTED: This frame is being decrypted.
5130 + */
5131 +#define RXD_W3_BA FIELD32(0x00000001)
5132 +#define RXD_W3_DATA FIELD32(0x00000002)
5133 +#define RXD_W3_NULLDATA FIELD32(0x00000004)
5134 +#define RXD_W3_FRAG FIELD32(0x00000008)
5135 +#define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
5136 +#define RXD_W3_MULTICAST FIELD32(0x00000020)
5137 +#define RXD_W3_BROADCAST FIELD32(0x00000040)
5138 +#define RXD_W3_MY_BSS FIELD32(0x00000080)
5139 +#define RXD_W3_CRC_ERROR FIELD32(0x00000100)
5140 +#define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
5141 +#define RXD_W3_AMSDU FIELD32(0x00000800)
5142 +#define RXD_W3_HTC FIELD32(0x00001000)
5143 +#define RXD_W3_RSSI FIELD32(0x00002000)
5144 +#define RXD_W3_L2PAD FIELD32(0x00004000)
5145 +#define RXD_W3_AMPDU FIELD32(0x00008000)
5146 +#define RXD_W3_DECRYPTED FIELD32(0x00010000)
5147 +#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
5148 +#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
5149 +
5150 +/*
5151 + * RX WI structure
5152 + */
5153 +
5154 +/*
5155 + * Word0
5156 + */
5157 +#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
5158 +#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
5159 +#define RXWI_W0_BSSID FIELD32(0x00001c00)
5160 +#define RXWI_W0_UDF FIELD32(0x0000e000)
5161 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
5162 +#define RXWI_W0_TID FIELD32(0xf0000000)
5163 +
5164 +/*
5165 + * Word1
5166 + */
5167 +#define RXWI_W1_FRAG FIELD32(0x0000000f)
5168 +#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
5169 +#define RXWI_W1_MCS FIELD32(0x007f0000)
5170 +#define RXWI_W1_BW FIELD32(0x00800000)
5171 +#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
5172 +#define RXWI_W1_STBC FIELD32(0x06000000)
5173 +#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
5174 +
5175 +/*
5176 + * Word2
5177 + */
5178 +#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
5179 +#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
5180 +#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
5181 +
5182 +/*
5183 + * Word3
5184 + */
5185 +#define RXWI_W3_SNR0 FIELD32(0x000000ff)
5186 +#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
5187 +
5188 +/*
5189 + * Macro's for converting txpower from EEPROM to mac80211 value
5190 + * and from mac80211 value to register value.
5191 + */
5192 +#define MIN_G_TXPOWER 0
5193 +#define MIN_A_TXPOWER -7
5194 +#define MAX_G_TXPOWER 31
5195 +#define MAX_A_TXPOWER 15
5196 +#define DEFAULT_TXPOWER 5
5197 +
5198 +#define TXPOWER_G_FROM_DEV(__txpower) \
5199 + ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
5200 +
5201 +#define TXPOWER_G_TO_DEV(__txpower) \
5202 + clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
5203 +
5204 +#define TXPOWER_A_FROM_DEV(__txpower) \
5205 + ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
5206 +
5207 +#define TXPOWER_A_TO_DEV(__txpower) \
5208 + clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
5209 +
5210 +#endif /* RT2800PCI_H */
5211 --- a/drivers/net/wireless/rt2x00/rt2x00.h
5212 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
5213 @@ -138,6 +138,12 @@ struct rt2x00_chip {
5214 #define RT2561 0x0302
5215 #define RT2661 0x0401
5216 #define RT2571 0x1300
5217 +#define RT2860 0x0601 /* 2.4GHz PCI/CB */
5218 +#define RT2860D 0x0681 /* 2.4GHz, 5GHz PCI/CB */
5219 +#define RT2890 0x0701 /* 2.4GHz PCIe */
5220 +#define RT2890D 0x0781 /* 2.4GHz, 5GHz PCIe */
5221 +#define RT2880 0x2880 /* WSOC */
5222 +#define RT3052 0x3052 /* WSOC */
5223
5224 u16 rf;
5225 u32 rev;
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