package/mac80211/patches/616-rt2x00-support-rt5350.patch

   1 Index: compat-wireless-2013-02-22/drivers/net/wireless/rt2x00/rt2800.h
   2 ===================================================================
   3 --- compat-wireless-2013-02-22.orig/drivers/net/wireless/rt2x00/rt2800.h        2013-04-01 18:42:38.843812191 +0200
   4 +++ compat-wireless-2013-02-22/drivers/net/wireless/rt2x00/rt2800.h     2013-04-01 18:42:44.483812325 +0200
   5 @@ -69,6 +69,7 @@
   6  #define RF3322                         0x000c
   7  #define RF3053                         0x000d
   8  #define RF3290                         0x3290
   9 +#define RF5350                         0x5350
  10  #define RF5360                         0x5360
  11  #define RF5370                         0x5370
  12  #define RF5372                         0x5372
  13 Index: compat-wireless-2013-02-22/drivers/net/wireless/rt2x00/rt2800lib.c
  14 ===================================================================
  15 --- compat-wireless-2013-02-22.orig/drivers/net/wireless/rt2x00/rt2800lib.c     2013-04-01 18:42:38.843812191 +0200
  16 +++ compat-wireless-2013-02-22/drivers/net/wireless/rt2x00/rt2800lib.c  2013-04-01 18:43:27.907813351 +0200
  17 @@ -2137,6 +2137,15 @@
  18         if (rf->channel <= 14) {
  19                 int idx = rf->channel-1;
  20
  21 +               if (rt2x00_rt(rt2x00dev, RT5350)) {
  22 +                       static const char r59_non_bt[] = {0x0b, 0x0b,
  23 +                               0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
  24 +                               0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
  25 +
  26 +                       rt2800_rfcsr_write(rt2x00dev, 59,
  27 +                                          r59_non_bt[idx]);
  28 +               }
  29 +
  30                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
  31                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
  32                                 /* r55/r59 value array of channel 1~14 */
  33 @@ -2218,6 +2227,7 @@
  34         case RF3322:
  35                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
  36                 break;
  37 +       case RF5350:
  38         case RF5360:
  39         case RF5370:
  40         case RF5372:
  41 @@ -2231,6 +2241,7 @@
  42
  43         if (rt2x00_rf(rt2x00dev, RF3290) ||
  44             rt2x00_rf(rt2x00dev, RF3322) ||
  45 +           rt2x00_rf(rt2x00dev, RF5350) ||
  46             rt2x00_rf(rt2x00dev, RF5360) ||
  47             rt2x00_rf(rt2x00dev, RF5370) ||
  48             rt2x00_rf(rt2x00dev, RF5372) ||
  49 @@ -2361,7 +2372,8 @@
  50         /*
  51          * Clear update flag
  52          */
  53 -       if (rt2x00_rt(rt2x00dev, RT3352)) {
  54 +       if (rt2x00_rt(rt2x00dev, RT3352) ||
  55 +           rt2x00_rt(rt2x00dev, RT5350)) {
  56                 rt2800_bbp_read(rt2x00dev, 49, &bbp);
  57                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
  58                 rt2800_bbp_write(rt2x00dev, 49, bbp);
  59 @@ -2800,6 +2812,7 @@
  60                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
  61                 break;
  62         case RF3290:
  63 +       case RF5350:
  64         case RF5360:
  65         case RF5370:
  66         case RF5372:
  67 @@ -3124,7 +3137,8 @@
  68         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
  69                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
  70                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  71 -       } else if (rt2x00_rt(rt2x00dev, RT5390) ||
  72 +       } else if (rt2x00_rt(rt2x00dev, RT5350) ||
  73 +                  rt2x00_rt(rt2x00dev, RT5390) ||
  74                    rt2x00_rt(rt2x00dev, RT5392)) {
  75                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
  76                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  77 @@ -3506,6 +3520,10 @@
  78                 rt2800_bbp_write(rt2x00dev, 4, 0x50);
  79         }
  80
  81 +       if (rt2x00_rt(rt2x00dev, RT5350)) {
  82 +               rt2800_bbp_write(rt2x00dev, 4, 0x50);
  83 +       }
  84 +
  85         if (rt2x00_rt(rt2x00dev, RT3290) ||
  86             rt2x00_rt(rt2x00dev, RT5390) ||
  87             rt2x00_rt(rt2x00dev, RT5392)) {
  88 @@ -3518,11 +3536,13 @@
  89             rt2x00_rt(rt2x00dev, RT3290) ||
  90             rt2x00_rt(rt2x00dev, RT3352) ||
  91             rt2x00_rt(rt2x00dev, RT3572) ||
  92 +           rt2x00_rt(rt2x00dev, RT5350) ||
  93             rt2x00_rt(rt2x00dev, RT5390) ||
  94             rt2x00_rt(rt2x00dev, RT5392))
  95                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
  96
  97 -       if (rt2x00_rt(rt2x00dev, RT3352))
  98 +       if (rt2x00_rt(rt2x00dev, RT3352) ||
  99 +           rt2x00_rt(rt2x00dev, RT5350))
 100                 rt2800_bbp_write(rt2x00dev, 47, 0x48);
 101
 102         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
 103 @@ -3530,6 +3550,7 @@
 104
 105         if (rt2x00_rt(rt2x00dev, RT3290) ||
 106             rt2x00_rt(rt2x00dev, RT3352) ||
 107 +           rt2x00_rt(rt2x00dev, RT5350) ||
 108             rt2x00_rt(rt2x00dev, RT5390) ||
 109             rt2x00_rt(rt2x00dev, RT5392))
 110                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
 111 @@ -3539,6 +3560,7 @@
 112                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
 113         } else if (rt2x00_rt(rt2x00dev, RT3290) ||
 114                    rt2x00_rt(rt2x00dev, RT3352) ||
 115 +                  rt2x00_rt(rt2x00dev, RT5350) ||
 116                    rt2x00_rt(rt2x00dev, RT5390) ||
 117                    rt2x00_rt(rt2x00dev, RT5392)) {
 118                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
 119 @@ -3575,7 +3597,8 @@
 120                 rt2800_bbp_write(rt2x00dev, 79, 0x18);
 121                 rt2800_bbp_write(rt2x00dev, 80, 0x09);
 122                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
 123 -       } else if (rt2x00_rt(rt2x00dev, RT3352)) {
 124 +       } else if (rt2x00_rt(rt2x00dev, RT3352) ||
 125 +               rt2x00_rt(rt2x00dev, RT5350)) {
 126                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
 127                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
 128                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
 129 @@ -3585,6 +3608,7 @@
 130
 131         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 132         if (rt2x00_rt(rt2x00dev, RT3290) ||
 133 +           rt2x00_rt(rt2x00dev, RT5350) ||
 134             rt2x00_rt(rt2x00dev, RT5390) ||
 135             rt2x00_rt(rt2x00dev, RT5392))
 136                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
 137 @@ -3594,6 +3618,7 @@
 138         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
 139                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
 140         else if (rt2x00_rt(rt2x00dev, RT3290) ||
 141 +                rt2x00_rt(rt2x00dev, RT5350) ||
 142                  rt2x00_rt(rt2x00dev, RT5390) ||
 143                  rt2x00_rt(rt2x00dev, RT5392))
 144                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
 145 @@ -3602,6 +3627,7 @@
 146
 147         if (rt2x00_rt(rt2x00dev, RT3290) ||
 148             rt2x00_rt(rt2x00dev, RT3352) ||
 149 +           rt2x00_rt(rt2x00dev, RT5350) ||
 150             rt2x00_rt(rt2x00dev, RT5390) ||
 151             rt2x00_rt(rt2x00dev, RT5392))
 152                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
 153 @@ -3616,6 +3642,7 @@
 154
 155         if (rt2x00_rt(rt2x00dev, RT3290) ||
 156             rt2x00_rt(rt2x00dev, RT3352) ||
 157 +           rt2x00_rt(rt2x00dev, RT5350) ||
 158             rt2x00_rt(rt2x00dev, RT5390) ||
 159             rt2x00_rt(rt2x00dev, RT5392))
 160                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
 161 @@ -3634,6 +3661,7 @@
 162             rt2x00_rt(rt2x00dev, RT3290) ||
 163             rt2x00_rt(rt2x00dev, RT3352) ||
 164             rt2x00_rt(rt2x00dev, RT3572) ||
 165 +           rt2x00_rt(rt2x00dev, RT5350) ||
 166             rt2x00_rt(rt2x00dev, RT5390) ||
 167             rt2x00_rt(rt2x00dev, RT5392) ||
 168             rt2800_is_305x_soc(rt2x00dev))
 169 @@ -3643,6 +3671,7 @@
 170
 171         if (rt2x00_rt(rt2x00dev, RT3290) ||
 172             rt2x00_rt(rt2x00dev, RT3352) ||
 173 +           rt2x00_rt(rt2x00dev, RT5350) ||
 174             rt2x00_rt(rt2x00dev, RT5390) ||
 175             rt2x00_rt(rt2x00dev, RT5392))
 176                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
 177 @@ -3653,13 +3682,15 @@
 178                 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
 179         else if (rt2x00_rt(rt2x00dev, RT3352))
 180                 rt2800_bbp_write(rt2x00dev, 105, 0x34);
 181 -       else if (rt2x00_rt(rt2x00dev, RT5390) ||
 182 +       else if (rt2x00_rt(rt2x00dev, RT5350) ||
 183 +                rt2x00_rt(rt2x00dev, RT5390) ||
 184                  rt2x00_rt(rt2x00dev, RT5392))
 185                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
 186         else
 187                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
 188
 189         if (rt2x00_rt(rt2x00dev, RT3290) ||
 190 +               rt2x00_rt(rt2x00dev, RT5350) ||
 191             rt2x00_rt(rt2x00dev, RT5390))
 192                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
 193         else if (rt2x00_rt(rt2x00dev, RT3352))
 194 @@ -3669,11 +3700,13 @@
 195         else
 196                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
 197
 198 -       if (rt2x00_rt(rt2x00dev, RT3352))
 199 +       if (rt2x00_rt(rt2x00dev, RT3352) ||
 200 +           rt2x00_rt(rt2x00dev, RT5350))
 201                 rt2800_bbp_write(rt2x00dev, 120, 0x50);
 202
 203         if (rt2x00_rt(rt2x00dev, RT3290) ||
 204             rt2x00_rt(rt2x00dev, RT3352) ||
 205 +           rt2x00_rt(rt2x00dev, RT5350) ||
 206             rt2x00_rt(rt2x00dev, RT5390) ||
 207             rt2x00_rt(rt2x00dev, RT5392))
 208                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
 209 @@ -3683,13 +3716,15 @@
 210                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
 211         }
 212
 213 -       if (rt2x00_rt(rt2x00dev, RT3352))
 214 +       if (rt2x00_rt(rt2x00dev, RT3352) ||
 215 +           rt2x00_rt(rt2x00dev, RT5350))
 216                 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
 217
 218         if (rt2x00_rt(rt2x00dev, RT3071) ||
 219             rt2x00_rt(rt2x00dev, RT3090) ||
 220             rt2x00_rt(rt2x00dev, RT3390) ||
 221             rt2x00_rt(rt2x00dev, RT3572) ||
 222 +           rt2x00_rt(rt2x00dev, RT5350) ||
 223             rt2x00_rt(rt2x00dev, RT5390) ||
 224             rt2x00_rt(rt2x00dev, RT5392)) {
 225                 rt2800_bbp_read(rt2x00dev, 138, &value);
 226 @@ -3726,7 +3761,8 @@
 227                 rt2800_bbp_write(rt2x00dev, 3, value);
 228         }
 229
 230 -       if (rt2x00_rt(rt2x00dev, RT3352)) {
 231 +       if (rt2x00_rt(rt2x00dev, RT3352) ||
 232 +           rt2x00_rt(rt2x00dev, RT5350)) {
 233                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
 234                 /* Set ITxBF timeout to 0x9c40=1000msec */
 235                 rt2800_bbp_write(rt2x00dev, 179, 0x02);
 236 @@ -3748,6 +3784,14 @@
 237                 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
 238         }
 239
 240 +       if (rt2x00_rt(rt2x00dev, RT5350)) {
 241 +               rt2800_bbp_write(rt2x00dev, 150, 0x40); /* Antenna Software OFDM */
 242 +               rt2800_bbp_write(rt2x00dev, 151, 0x30); /* Antenna Software CCK */
 243 +               rt2800_bbp_write(rt2x00dev, 152, 0xa3);
 244 +               rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
 245 +       }
 246 +
 247 +
 248         if (rt2x00_rt(rt2x00dev, RT5390) ||
 249             rt2x00_rt(rt2x00dev, RT5392)) {
 250                 int ant, div_mode;
 251 @@ -4142,6 +4186,76 @@
 252         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
 253  }
 254
 255 +static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
 256 +{
 257 +       rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
 258 +       rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
 259 +       rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
 260 +       rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
 261 +       rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
 262 +       rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
 263 +       rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
 264 +       rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
 265 +       rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
 266 +       rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
 267 +       rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
 268 +       rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
 269 +       rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
 270 +       if(rt2x00dev->spec.clk_is_20mhz)
 271 +               rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
 272 +       else
 273 +               rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
 274 +       rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
 275 +       rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
 276 +       rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
 277 +       rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
 278 +       rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
 279 +       rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
 280 +       rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
 281 +       rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
 282 +       rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
 283 +       rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
 284 +       rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
 285 +       rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
 286 +       rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
 287 +       rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
 288 +       rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
 289 +       rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
 290 +       rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
 291 +       rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
 292 +       rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
 293 +       rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
 294 +       rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
 295 +       rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
 296 +       rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
 297 +       rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
 298 +       rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
 299 +       rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
 300 +       rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
 301 +       rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
 302 +       rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
 303 +       rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
 304 +       rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
 305 +       rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
 306 +       rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
 307 +       rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
 308 +       rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
 309 +       rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
 310 +       rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
 311 +       rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
 312 +       rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
 313 +       rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
 314 +       rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
 315 +       rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
 316 +       rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
 317 +       rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
 318 +       rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
 319 +       rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
 320 +       rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
 321 +       rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
 322 +       rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
 323 +}
 324 +
 325  static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
 326  {
 327         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
 328 @@ -4304,6 +4418,7 @@
 329             !rt2x00_rt(rt2x00dev, RT3352) &&
 330             !rt2x00_rt(rt2x00dev, RT3390) &&
 331             !rt2x00_rt(rt2x00dev, RT3572) &&
 332 +           !rt2x00_rt(rt2x00dev, RT5350) &&
 333             !rt2x00_rt(rt2x00dev, RT5390) &&
 334             !rt2x00_rt(rt2x00dev, RT5392) &&
 335             !rt2800_is_305x_soc(rt2x00dev))
 336 @@ -4354,6 +4469,9 @@
 337         case RT3572:
 338                 rt2800_init_rfcsr_3572(rt2x00dev);
 339                 break;
 340 +       case RT5350:
 341 +               rt2800_init_rfcsr_5350(rt2x00dev);
 342 +               break;
 343         case RT5390:
 344                 rt2800_init_rfcsr_5390(rt2x00dev);
 345                 break;
 346 @@ -4750,6 +4868,12 @@
 347                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
 348                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
 349                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
 350 +       } else if(rt2x00_rt(rt2x00dev, RT5350)) {
 351 +               rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 1);
 352 +               rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
 353 +               rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF3320);
 354 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
 355 +               EEPROM(rt2x00dev, "rt5350: Ant: 0x%04x\n", word);
 356         }
 357
 358         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
 359 @@ -4874,6 +4998,8 @@
 360             rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
 361             rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
 362                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
 363 +       else if(rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5350)
 364 +               value = RF5350;
 365         else
 366                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
 367
 368 @@ -4891,6 +5017,7 @@
 369         case RT3352:
 370         case RT3390:
 371         case RT3572:
 372 +       case RT5350:
 373         case RT5390:
 374         case RT5392:
 375                 break;
 376 @@ -4912,6 +5039,7 @@
 377         case RF3290:
 378         case RF3320:
 379         case RF3322:
 380 +       case RF5350:
 381         case RF5360:
 382         case RF5370:
 383         case RF5372:
 384 @@ -5274,7 +5402,8 @@
 385                    rt2x00_rf(rt2x00dev, RF5392)) {
 386                 spec->num_channels = 14;
 387                 spec->channels = rf_vals_3x;
 388 -       } else if (rt2x00_rf(rt2x00dev, RF3322)) {
 389 +       } else if (rt2x00_rf(rt2x00dev, RF3322) ||
 390 +                  rt2x00_rf(rt2x00dev, RF5350)) {
 391                 spec->num_channels = 14;
 392                 if (spec->clk_is_20mhz)
 393                         spec->channels = rf_vals_xtal20mhz_3x;
 394 @@ -5363,6 +5492,7 @@
 395         case RF3290:
 396         case RF5360:
 397         case RF5370:
 398 +       case RF5350:
 399         case RF5372:
 400         case RF5390:
 401         case RF5392:
 402 Index: compat-wireless-2013-02-22/drivers/net/wireless/rt2x00/rt2x00.h
 403 ===================================================================
 404 --- compat-wireless-2013-02-22.orig/drivers/net/wireless/rt2x00/rt2x00.h        2013-04-01 18:42:38.843812191 +0200
 405 +++ compat-wireless-2013-02-22/drivers/net/wireless/rt2x00/rt2x00.h     2013-04-01 18:42:44.487812326 +0200
 406 @@ -192,6 +192,7 @@
 407  #define RT3572         0x3572
 408  #define RT3593         0x3593
 409  #define RT3883         0x3883  /* WSOC */
 410 +#define RT5350         0x5350  /* WSOC 2.4GHz */
 411  #define RT5390         0x5390  /* 2.4GHz */
 412  #define RT5392         0x5392  /* 2.4GHz */
 413