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ar7: remove unneeded packed and array initialization
[openwrt/svn-archive/archive.git] / package / rt2x00 / src / rt61pci.c
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
27 /*
28 * Set enviroment defines for rt2x00.h
29 */
30 #define DRV_NAME "rt61pci"
31
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/init.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/eeprom_93cx6.h>
39
40 #include "rt2x00.h"
41 #include "rt2x00pci.h"
42 #include "rt61pci.h"
43
44 /*
45 * Register access.
46 * BBP and RF register require indirect register access,
47 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
48 * These indirect registers work with busy bits,
49 * and we will try maximal REGISTER_BUSY_COUNT times to access
50 * the register while taking a REGISTER_BUSY_DELAY us delay
51 * between each attampt. When the busy bit is still set at that time,
52 * the access attempt is considered to have failed,
53 * and we will print an error.
54 */
55 static u32 rt61pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
56 {
57 u32 reg;
58 unsigned int i;
59
60 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
61 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
62 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
63 break;
64 udelay(REGISTER_BUSY_DELAY);
65 }
66
67 return reg;
68 }
69
70 static void rt61pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
71 const unsigned int word, const u8 value)
72 {
73 u32 reg;
74
75 /*
76 * Wait until the BBP becomes ready.
77 */
78 reg = rt61pci_bbp_check(rt2x00dev);
79 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
80 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
81 return;
82 }
83
84 /*
85 * Write the data into the BBP.
86 */
87 reg = 0;
88 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
89 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
90 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
91 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
92
93 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
94 }
95
96 static void rt61pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
97 const unsigned int word, u8 *value)
98 {
99 u32 reg;
100
101 /*
102 * Wait until the BBP becomes ready.
103 */
104 reg = rt61pci_bbp_check(rt2x00dev);
105 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
106 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
107 return;
108 }
109
110 /*
111 * Write the request into the BBP.
112 */
113 reg = 0;
114 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
115 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
116 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
117
118 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
119
120 /*
121 * Wait until the BBP becomes ready.
122 */
123 reg = rt61pci_bbp_check(rt2x00dev);
124 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
125 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
126 *value = 0xff;
127 return;
128 }
129
130 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
131 }
132
133 static void rt61pci_rf_write(const struct rt2x00_dev *rt2x00dev,
134 const unsigned int word, const u32 value)
135 {
136 u32 reg;
137 unsigned int i;
138
139 if (!word)
140 return;
141
142 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
143 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
144 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
145 goto rf_write;
146 udelay(REGISTER_BUSY_DELAY);
147 }
148
149 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
150 return;
151
152 rf_write:
153 reg = 0;
154 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
155 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
156 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
157 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
158
159 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
160 rt2x00_rf_write(rt2x00dev, word, value);
161 }
162
163 static void rt61pci_mcu_request(const struct rt2x00_dev *rt2x00dev,
164 const u8 command, const u8 token,
165 const u8 arg0, const u8 arg1)
166 {
167 u32 reg;
168
169 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
170
171 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
172 ERROR(rt2x00dev, "mcu request error. "
173 "Request 0x%02x failed for token 0x%02x.\n",
174 command, token);
175 return;
176 }
177
178 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
179 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
180 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
181 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
182 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
183
184 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
185 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
186 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
187 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
188 }
189
190 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
191 {
192 struct rt2x00_dev *rt2x00dev = eeprom->data;
193 u32 reg;
194
195 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
196
197 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
198 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
199 eeprom->reg_data_clock =
200 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
201 eeprom->reg_chip_select =
202 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
203 }
204
205 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
206 {
207 struct rt2x00_dev *rt2x00dev = eeprom->data;
208 u32 reg = 0;
209
210 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
211 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
212 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
213 !!eeprom->reg_data_clock);
214 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
215 !!eeprom->reg_chip_select);
216
217 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
218 }
219
220 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
221 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
222
223 static void rt61pci_read_csr(const struct rt2x00_dev *rt2x00dev,
224 const unsigned int word, u32 *data)
225 {
226 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
227 }
228
229 static void rt61pci_write_csr(const struct rt2x00_dev *rt2x00dev,
230 const unsigned int word, u32 data)
231 {
232 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
233 }
234
235 static const struct rt2x00debug rt61pci_rt2x00debug = {
236 .owner = THIS_MODULE,
237 .csr = {
238 .read = rt61pci_read_csr,
239 .write = rt61pci_write_csr,
240 .word_size = sizeof(u32),
241 .word_count = CSR_REG_SIZE / sizeof(u32),
242 },
243 .eeprom = {
244 .read = rt2x00_eeprom_read,
245 .write = rt2x00_eeprom_write,
246 .word_size = sizeof(u16),
247 .word_count = EEPROM_SIZE / sizeof(u16),
248 },
249 .bbp = {
250 .read = rt61pci_bbp_read,
251 .write = rt61pci_bbp_write,
252 .word_size = sizeof(u8),
253 .word_count = BBP_SIZE / sizeof(u8),
254 },
255 .rf = {
256 .read = rt2x00_rf_read,
257 .write = rt61pci_rf_write,
258 .word_size = sizeof(u32),
259 .word_count = RF_SIZE / sizeof(u32),
260 },
261 };
262 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
263
264 #ifdef CONFIG_RT61PCI_RFKILL
265 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
266 {
267 u32 reg;
268
269 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
270 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
271 }
272 #else
273 #define rt61pci_rfkill_poll NULL
274 #endif /* CONFIG_RT61PCI_RFKILL */
275
276 /*
277 * Configuration handlers.
278 */
279 static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
280 {
281 u32 tmp;
282
283 tmp = le32_to_cpu(mac[1]);
284 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
285 mac[1] = cpu_to_le32(tmp);
286
287 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
288 (2 * sizeof(__le32)));
289 }
290
291 static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
292 {
293 u32 tmp;
294
295 tmp = le32_to_cpu(bssid[1]);
296 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
297 bssid[1] = cpu_to_le32(tmp);
298
299 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
300 (2 * sizeof(__le32)));
301 }
302
303 static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
304 const int tsf_sync)
305 {
306 u32 reg;
307
308 /*
309 * Clear current synchronisation setup.
310 * For the Beacon base registers we only need to clear
311 * the first byte since that byte contains the VALID and OWNER
312 * bits which (when set to 0) will invalidate the entire beacon.
313 */
314 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
315 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
316 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
317 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
318 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
319
320 /*
321 * Enable synchronisation.
322 */
323 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
324 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
325 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
326 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
327 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync);
328 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
329 }
330
331 static void rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
332 const int short_preamble,
333 const int ack_timeout,
334 const int ack_consume_time)
335 {
336 u32 reg;
337
338 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
339 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
340 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
341
342 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
343 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
344 !!short_preamble);
345 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
346 }
347
348 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
349 const int basic_rate_mask)
350 {
351 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
352 }
353
354 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
355 struct rf_channel *rf, const int txpower)
356 {
357 u8 r3;
358 u8 r94;
359 u8 smart;
360
361 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
362 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
363
364 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
365 rt2x00_rf(&rt2x00dev->chip, RF2527));
366
367 rt61pci_bbp_read(rt2x00dev, 3, &r3);
368 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
369 rt61pci_bbp_write(rt2x00dev, 3, r3);
370
371 r94 = 6;
372 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
373 r94 += txpower - MAX_TXPOWER;
374 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
375 r94 += txpower;
376 rt61pci_bbp_write(rt2x00dev, 94, r94);
377
378 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
379 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
380 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
381 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
382
383 udelay(200);
384
385 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
386 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
387 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
388 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
389
390 udelay(200);
391
392 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
393 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
394 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
395 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
396
397 msleep(1);
398 }
399
400 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
401 const int txpower)
402 {
403 struct rf_channel rf;
404
405 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
406 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
407 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
408 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
409
410 rt61pci_config_channel(rt2x00dev, &rf, txpower);
411 }
412
413 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
414 const int antenna_tx,
415 const int antenna_rx)
416 {
417 u8 r3;
418 u8 r4;
419 u8 r77;
420
421 rt61pci_bbp_read(rt2x00dev, 3, &r3);
422 rt61pci_bbp_read(rt2x00dev, 4, &r4);
423 rt61pci_bbp_read(rt2x00dev, 77, &r77);
424
425 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
426 !rt2x00_rf(&rt2x00dev->chip, RF5225));
427
428 switch (antenna_rx) {
429 case ANTENNA_SW_DIVERSITY:
430 case ANTENNA_HW_DIVERSITY:
431 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
432 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
433 !!(rt2x00dev->curr_hwmode != HWMODE_A));
434 break;
435 case ANTENNA_A:
436 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
437 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
438
439 if (rt2x00dev->curr_hwmode == HWMODE_A)
440 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
441 else
442 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
443 break;
444 case ANTENNA_B:
445 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
446 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
447
448 if (rt2x00dev->curr_hwmode == HWMODE_A)
449 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
450 else
451 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
452 break;
453 }
454
455 rt61pci_bbp_write(rt2x00dev, 77, r77);
456 rt61pci_bbp_write(rt2x00dev, 3, r3);
457 rt61pci_bbp_write(rt2x00dev, 4, r4);
458 }
459
460 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
461 const int antenna_tx,
462 const int antenna_rx)
463 {
464 u8 r3;
465 u8 r4;
466 u8 r77;
467
468 rt61pci_bbp_read(rt2x00dev, 3, &r3);
469 rt61pci_bbp_read(rt2x00dev, 4, &r4);
470 rt61pci_bbp_read(rt2x00dev, 77, &r77);
471
472 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
473 !rt2x00_rf(&rt2x00dev->chip, RF2527));
474 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
475 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
476
477 switch (antenna_rx) {
478 case ANTENNA_SW_DIVERSITY:
479 case ANTENNA_HW_DIVERSITY:
480 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
481 break;
482 case ANTENNA_A:
483 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
484 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
485 break;
486 case ANTENNA_B:
487 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
488 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
489 break;
490 }
491
492 rt61pci_bbp_write(rt2x00dev, 77, r77);
493 rt61pci_bbp_write(rt2x00dev, 3, r3);
494 rt61pci_bbp_write(rt2x00dev, 4, r4);
495 }
496
497 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
498 const int p1, const int p2)
499 {
500 u32 reg;
501
502 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
503
504 if (p1 != 0xff) {
505 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, !!p1);
506 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
507 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
508 }
509 if (p2 != 0xff) {
510 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
511 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
512 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
513 }
514 }
515
516 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
517 const int antenna_tx,
518 const int antenna_rx)
519 {
520 u16 eeprom;
521 u8 r3;
522 u8 r4;
523 u8 r77;
524
525 rt61pci_bbp_read(rt2x00dev, 3, &r3);
526 rt61pci_bbp_read(rt2x00dev, 4, &r4);
527 rt61pci_bbp_read(rt2x00dev, 77, &r77);
528 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
529
530 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
531
532 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
533 rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
534 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
535 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 1);
536 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
537 } else if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) {
538 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED) >= 2) {
539 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
540 rt61pci_bbp_write(rt2x00dev, 77, r77);
541 }
542 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
543 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
544 } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
545 rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
546 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
547 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
548
549 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
550 case 0:
551 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
552 break;
553 case 1:
554 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
555 break;
556 case 2:
557 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
558 break;
559 case 3:
560 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
561 break;
562 }
563 } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
564 !rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
565 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
566 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
567
568 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
569 case 0:
570 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
571 rt61pci_bbp_write(rt2x00dev, 77, r77);
572 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
573 break;
574 case 1:
575 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
576 rt61pci_bbp_write(rt2x00dev, 77, r77);
577 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
578 break;
579 case 2:
580 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
581 rt61pci_bbp_write(rt2x00dev, 77, r77);
582 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
583 break;
584 case 3:
585 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
586 rt61pci_bbp_write(rt2x00dev, 77, r77);
587 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
588 break;
589 }
590 }
591
592 rt61pci_bbp_write(rt2x00dev, 3, r3);
593 rt61pci_bbp_write(rt2x00dev, 4, r4);
594 }
595
596 struct antenna_sel {
597 u8 word;
598 /*
599 * value[0] -> non-LNA
600 * value[1] -> LNA
601 */
602 u8 value[2];
603 };
604
605 static const struct antenna_sel antenna_sel_a[] = {
606 { 96, { 0x58, 0x78 } },
607 { 104, { 0x38, 0x48 } },
608 { 75, { 0xfe, 0x80 } },
609 { 86, { 0xfe, 0x80 } },
610 { 88, { 0xfe, 0x80 } },
611 { 35, { 0x60, 0x60 } },
612 { 97, { 0x58, 0x58 } },
613 { 98, { 0x58, 0x58 } },
614 };
615
616 static const struct antenna_sel antenna_sel_bg[] = {
617 { 96, { 0x48, 0x68 } },
618 { 104, { 0x2c, 0x3c } },
619 { 75, { 0xfe, 0x80 } },
620 { 86, { 0xfe, 0x80 } },
621 { 88, { 0xfe, 0x80 } },
622 { 35, { 0x50, 0x50 } },
623 { 97, { 0x48, 0x48 } },
624 { 98, { 0x48, 0x48 } },
625 };
626
627 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
628 const int antenna_tx, const int antenna_rx)
629 {
630 const struct antenna_sel *sel;
631 unsigned int lna;
632 unsigned int i;
633 u32 reg;
634
635 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
636
637 if (rt2x00dev->curr_hwmode == HWMODE_A) {
638 sel = antenna_sel_a;
639 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
640
641 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 0);
642 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 1);
643 } else {
644 sel = antenna_sel_bg;
645 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
646
647 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 1);
648 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 0);
649 }
650
651 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
652 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
653
654 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
655
656 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
657 rt2x00_rf(&rt2x00dev->chip, RF5325))
658 rt61pci_config_antenna_5x(rt2x00dev, antenna_tx, antenna_rx);
659 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
660 rt61pci_config_antenna_2x(rt2x00dev, antenna_tx, antenna_rx);
661 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
662 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
663 rt61pci_config_antenna_2x(rt2x00dev, antenna_tx,
664 antenna_rx);
665 else
666 rt61pci_config_antenna_2529(rt2x00dev, antenna_tx,
667 antenna_rx);
668 }
669 }
670
671 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
672 struct rt2x00lib_conf *libconf)
673 {
674 u32 reg;
675
676 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
677 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
678 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
679
680 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
681 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
682 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
683 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
684 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
685
686 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
687 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
688 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
689
690 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
691 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
692 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
693
694 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
695 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
696 libconf->conf->beacon_int * 16);
697 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
698 }
699
700 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
701 const unsigned int flags,
702 struct rt2x00lib_conf *libconf)
703 {
704 if (flags & CONFIG_UPDATE_PHYMODE)
705 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
706 if (flags & CONFIG_UPDATE_CHANNEL)
707 rt61pci_config_channel(rt2x00dev, &libconf->rf,
708 libconf->conf->power_level);
709 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
710 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
711 if (flags & CONFIG_UPDATE_ANTENNA)
712 rt61pci_config_antenna(rt2x00dev, libconf->conf->antenna_sel_tx,
713 libconf->conf->antenna_sel_rx);
714 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
715 rt61pci_config_duration(rt2x00dev, libconf);
716 }
717
718 /*
719 * LED functions.
720 */
721 static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
722 {
723 u32 reg;
724 u16 led_reg;
725 u8 arg0;
726 u8 arg1;
727
728 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
729 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
730 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
731 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
732
733 led_reg = rt2x00dev->led_reg;
734 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 1);
735 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
736 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 1);
737 else
738 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 1);
739
740 arg0 = led_reg & 0xff;
741 arg1 = (led_reg >> 8) & 0xff;
742
743 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
744 }
745
746 static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
747 {
748 u16 led_reg;
749 u8 arg0;
750 u8 arg1;
751
752 led_reg = rt2x00dev->led_reg;
753 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
754 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
755 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
756
757 arg0 = led_reg & 0xff;
758 arg1 = (led_reg >> 8) & 0xff;
759
760 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
761 }
762
763 static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
764 {
765 u8 led;
766
767 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
768 return;
769
770 /*
771 * Led handling requires a positive value for the rssi,
772 * to do that correctly we need to add the correction.
773 */
774 rssi += rt2x00dev->rssi_offset;
775
776 if (rssi <= 30)
777 led = 0;
778 else if (rssi <= 39)
779 led = 1;
780 else if (rssi <= 49)
781 led = 2;
782 else if (rssi <= 53)
783 led = 3;
784 else if (rssi <= 63)
785 led = 4;
786 else
787 led = 5;
788
789 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
790 }
791
792 /*
793 * Link tuning
794 */
795 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev)
796 {
797 u32 reg;
798
799 /*
800 * Update FCS error count from register.
801 */
802 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
803 rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
804
805 /*
806 * Update False CCA count from register.
807 */
808 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
809 rt2x00dev->link.false_cca =
810 rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
811 }
812
813 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
814 {
815 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
816 rt2x00dev->link.vgc_level = 0x20;
817 }
818
819 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
820 {
821 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
822 u8 r17;
823 u8 up_bound;
824 u8 low_bound;
825
826 /*
827 * Update Led strength
828 */
829 rt61pci_activity_led(rt2x00dev, rssi);
830
831 rt61pci_bbp_read(rt2x00dev, 17, &r17);
832
833 /*
834 * Determine r17 bounds.
835 */
836 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
837 low_bound = 0x28;
838 up_bound = 0x48;
839 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
840 low_bound += 0x10;
841 up_bound += 0x10;
842 }
843 } else {
844 low_bound = 0x20;
845 up_bound = 0x40;
846 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
847 low_bound += 0x10;
848 up_bound += 0x10;
849 }
850 }
851
852 /*
853 * Special big-R17 for very short distance
854 */
855 if (rssi >= -35) {
856 if (r17 != 0x60)
857 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
858 return;
859 }
860
861 /*
862 * Special big-R17 for short distance
863 */
864 if (rssi >= -58) {
865 if (r17 != up_bound)
866 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
867 return;
868 }
869
870 /*
871 * Special big-R17 for middle-short distance
872 */
873 if (rssi >= -66) {
874 low_bound += 0x10;
875 if (r17 != low_bound)
876 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
877 return;
878 }
879
880 /*
881 * Special mid-R17 for middle distance
882 */
883 if (rssi >= -74) {
884 low_bound += 0x08;
885 if (r17 != low_bound)
886 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
887 return;
888 }
889
890 /*
891 * Special case: Change up_bound based on the rssi.
892 * Lower up_bound when rssi is weaker then -74 dBm.
893 */
894 up_bound -= 2 * (-74 - rssi);
895 if (low_bound > up_bound)
896 up_bound = low_bound;
897
898 if (r17 > up_bound) {
899 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
900 return;
901 }
902
903 /*
904 * r17 does not yet exceed upper limit, continue and base
905 * the r17 tuning on the false CCA count.
906 */
907 if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) {
908 if (++r17 > up_bound)
909 r17 = up_bound;
910 rt61pci_bbp_write(rt2x00dev, 17, r17);
911 } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) {
912 if (--r17 < low_bound)
913 r17 = low_bound;
914 rt61pci_bbp_write(rt2x00dev, 17, r17);
915 }
916 }
917
918 /*
919 * Firmware name function.
920 */
921 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
922 {
923 char *fw_name;
924
925 switch (rt2x00dev->chip.rt) {
926 case RT2561:
927 fw_name = FIRMWARE_RT2561;
928 break;
929 case RT2561s:
930 fw_name = FIRMWARE_RT2561s;
931 break;
932 case RT2661:
933 fw_name = FIRMWARE_RT2661;
934 break;
935 default:
936 fw_name = NULL;
937 break;
938 }
939
940 return fw_name;
941 }
942
943 /*
944 * Initialization functions.
945 */
946 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
947 const size_t len)
948 {
949 int i;
950 u32 reg;
951
952 /*
953 * Wait for stable hardware.
954 */
955 for (i = 0; i < 100; i++) {
956 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
957 if (reg)
958 break;
959 msleep(1);
960 }
961
962 if (!reg) {
963 ERROR(rt2x00dev, "Unstable hardware.\n");
964 return -EBUSY;
965 }
966
967 /*
968 * Prepare MCU and mailbox for firmware loading.
969 */
970 reg = 0;
971 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
972 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
973 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
974 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
975 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
976
977 /*
978 * Write firmware to device.
979 */
980 reg = 0;
981 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
982 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
983 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
984
985 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
986 data, len);
987
988 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
989 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
990
991 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
992 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
993
994 for (i = 0; i < 100; i++) {
995 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
996 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
997 break;
998 msleep(1);
999 }
1000
1001 if (i == 100) {
1002 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1003 return -EBUSY;
1004 }
1005
1006 /*
1007 * Reset MAC and BBP registers.
1008 */
1009 reg = 0;
1010 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1011 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1012 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1013
1014 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1015 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1016 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1017 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1018
1019 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1020 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1021 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1022
1023 return 0;
1024 }
1025
1026 static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
1027 {
1028 struct data_ring *ring = rt2x00dev->rx;
1029 struct data_desc *rxd;
1030 unsigned int i;
1031 u32 word;
1032
1033 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1034
1035 for (i = 0; i < ring->stats.limit; i++) {
1036 rxd = ring->entry[i].priv;
1037
1038 rt2x00_desc_read(rxd, 5, &word);
1039 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1040 ring->entry[i].data_dma);
1041 rt2x00_desc_write(rxd, 5, word);
1042
1043 rt2x00_desc_read(rxd, 0, &word);
1044 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1045 rt2x00_desc_write(rxd, 0, word);
1046 }
1047
1048 rt2x00_ring_index_clear(rt2x00dev->rx);
1049 }
1050
1051 static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
1052 {
1053 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1054 struct data_desc *txd;
1055 unsigned int i;
1056 u32 word;
1057
1058 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1059
1060 for (i = 0; i < ring->stats.limit; i++) {
1061 txd = ring->entry[i].priv;
1062
1063 rt2x00_desc_read(txd, 1, &word);
1064 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1065 rt2x00_desc_write(txd, 1, word);
1066
1067 rt2x00_desc_read(txd, 5, &word);
1068 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, queue);
1069 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, i);
1070 rt2x00_desc_write(txd, 5, word);
1071
1072 rt2x00_desc_read(txd, 6, &word);
1073 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1074 ring->entry[i].data_dma);
1075 rt2x00_desc_write(txd, 6, word);
1076
1077 rt2x00_desc_read(txd, 0, &word);
1078 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1079 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1080 rt2x00_desc_write(txd, 0, word);
1081 }
1082
1083 rt2x00_ring_index_clear(ring);
1084 }
1085
1086 static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1087 {
1088 u32 reg;
1089
1090 /*
1091 * Initialize rings.
1092 */
1093 rt61pci_init_rxring(rt2x00dev);
1094 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1095 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1096 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
1097 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
1098 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
1099
1100 /*
1101 * Initialize registers.
1102 */
1103 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1104 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1105 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
1106 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1107 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
1108 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1109 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
1110 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1111 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
1112 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1113
1114 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1115 rt2x00_set_field32(&reg, TX_RING_CSR1_MGMT_RING_SIZE,
1116 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1117 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1118 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
1119 4);
1120 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1121
1122 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1123 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1124 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
1125 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1126
1127 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1128 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1129 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
1130 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1131
1132 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1133 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1134 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
1135 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1136
1137 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1138 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1139 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
1140 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1141
1142 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, &reg);
1143 rt2x00_set_field32(&reg, MGMT_BASE_CSR_RING_REGISTER,
1144 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1145 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1146
1147 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1148 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE,
1149 rt2x00dev->rx->stats.limit);
1150 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1151 rt2x00dev->rx->desc_size / 4);
1152 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1153 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1154
1155 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1156 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1157 rt2x00dev->rx->data_dma);
1158 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1159
1160 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1161 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1162 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1163 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1164 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1165 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_MGMT, 0);
1166 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1167
1168 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1169 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1170 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1171 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1172 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1173 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
1174 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1175
1176 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1177 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1178 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1179
1180 return 0;
1181 }
1182
1183 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1184 {
1185 u32 reg;
1186
1187 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1188 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1189 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1190 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1191 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1192
1193 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1194 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1195 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1196 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1197 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1198 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1199 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1200 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1201 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1202 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1203
1204 /*
1205 * CCK TXD BBP registers
1206 */
1207 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1208 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1209 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1210 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1211 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1212 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1213 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1214 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1215 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1216 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1217
1218 /*
1219 * OFDM TXD BBP registers
1220 */
1221 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1222 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1223 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1224 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1225 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1226 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1227 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1228 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1229
1230 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1231 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1232 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1233 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1234 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1235 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1236
1237 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1238 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1239 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1240 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1241 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1242 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1243
1244 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1245
1246 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1247
1248 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1249 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1250 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1251
1252 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1253
1254 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1255 return -EBUSY;
1256
1257 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1258
1259 /*
1260 * Invalidate all Shared Keys (SEC_CSR0),
1261 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1262 */
1263 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1264 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1265 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1266
1267 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1268 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1269 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1270 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1271
1272 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1273
1274 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1275
1276 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1277
1278 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1279 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1280 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1281 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1282
1283 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1284 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1285 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1286 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1287
1288 /*
1289 * We must clear the error counters.
1290 * These registers are cleared on read,
1291 * so we may pass a useless variable to store the value.
1292 */
1293 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1294 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1295 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1296
1297 /*
1298 * Reset MAC and BBP registers.
1299 */
1300 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1301 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1302 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1303 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1304
1305 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1306 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1307 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1308 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1309
1310 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1311 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1312 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1313
1314 return 0;
1315 }
1316
1317 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1318 {
1319 unsigned int i;
1320 u16 eeprom;
1321 u8 reg_id;
1322 u8 value;
1323
1324 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1325 rt61pci_bbp_read(rt2x00dev, 0, &value);
1326 if ((value != 0xff) && (value != 0x00))
1327 goto continue_csr_init;
1328 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1329 udelay(REGISTER_BUSY_DELAY);
1330 }
1331
1332 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1333 return -EACCES;
1334
1335 continue_csr_init:
1336 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1337 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1338 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1339 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1340 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1341 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1342 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1343 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1344 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1345 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1346 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1347 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1348 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1349 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1350 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1351 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1352 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1353 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1354 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1355 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1356 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1357 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1358 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1359 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1360
1361 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1362 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1363 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1364
1365 if (eeprom != 0xffff && eeprom != 0x0000) {
1366 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1367 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1368 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1369 reg_id, value);
1370 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1371 }
1372 }
1373 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1374
1375 return 0;
1376 }
1377
1378 /*
1379 * Device state switch handlers.
1380 */
1381 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1382 enum dev_state state)
1383 {
1384 u32 reg;
1385
1386 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1387 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1388 state == STATE_RADIO_RX_OFF);
1389 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1390 }
1391
1392 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1393 enum dev_state state)
1394 {
1395 int mask = (state == STATE_RADIO_IRQ_OFF);
1396 u32 reg;
1397
1398 /*
1399 * When interrupts are being enabled, the interrupt registers
1400 * should clear the register to assure a clean state.
1401 */
1402 if (state == STATE_RADIO_IRQ_ON) {
1403 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1404 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1405
1406 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1407 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1408 }
1409
1410 /*
1411 * Only toggle the interrupts bits we are going to use.
1412 * Non-checked interrupt bits are disabled by default.
1413 */
1414 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1415 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1416 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1417 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1418 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1419 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1420
1421 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1422 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1423 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1424 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1425 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1426 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1427 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1428 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1429 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1430 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1431 }
1432
1433 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1434 {
1435 u32 reg;
1436
1437 /*
1438 * Initialize all registers.
1439 */
1440 if (rt61pci_init_rings(rt2x00dev) ||
1441 rt61pci_init_registers(rt2x00dev) ||
1442 rt61pci_init_bbp(rt2x00dev)) {
1443 ERROR(rt2x00dev, "Register initialization failed.\n");
1444 return -EIO;
1445 }
1446
1447 /*
1448 * Enable interrupts.
1449 */
1450 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1451
1452 /*
1453 * Enable RX.
1454 */
1455 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1456 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1457 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1458
1459 /*
1460 * Enable LED
1461 */
1462 rt61pci_enable_led(rt2x00dev);
1463
1464 return 0;
1465 }
1466
1467 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1468 {
1469 u32 reg;
1470
1471 /*
1472 * Disable LED
1473 */
1474 rt61pci_disable_led(rt2x00dev);
1475
1476 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1477
1478 /*
1479 * Disable synchronisation.
1480 */
1481 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1482
1483 /*
1484 * Cancel RX and TX.
1485 */
1486 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1487 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1488 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1489 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1490 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1491 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1492 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1493
1494 /*
1495 * Disable interrupts.
1496 */
1497 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1498 }
1499
1500 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1501 {
1502 u32 reg;
1503 unsigned int i;
1504 char put_to_sleep;
1505 char current_state;
1506
1507 put_to_sleep = (state != STATE_AWAKE);
1508
1509 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1510 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1511 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1512 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1513
1514 /*
1515 * Device is not guaranteed to be in the requested state yet.
1516 * We must wait until the register indicates that the
1517 * device has entered the correct state.
1518 */
1519 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1520 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1521 current_state =
1522 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1523 if (current_state == !put_to_sleep)
1524 return 0;
1525 msleep(10);
1526 }
1527
1528 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1529 "current device state %d.\n", !put_to_sleep, current_state);
1530
1531 return -EBUSY;
1532 }
1533
1534 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1535 enum dev_state state)
1536 {
1537 int retval = 0;
1538
1539 switch (state) {
1540 case STATE_RADIO_ON:
1541 retval = rt61pci_enable_radio(rt2x00dev);
1542 break;
1543 case STATE_RADIO_OFF:
1544 rt61pci_disable_radio(rt2x00dev);
1545 break;
1546 case STATE_RADIO_RX_ON:
1547 case STATE_RADIO_RX_OFF:
1548 rt61pci_toggle_rx(rt2x00dev, state);
1549 break;
1550 case STATE_DEEP_SLEEP:
1551 case STATE_SLEEP:
1552 case STATE_STANDBY:
1553 case STATE_AWAKE:
1554 retval = rt61pci_set_state(rt2x00dev, state);
1555 break;
1556 default:
1557 retval = -ENOTSUPP;
1558 break;
1559 }
1560
1561 return retval;
1562 }
1563
1564 /*
1565 * TX descriptor initialization
1566 */
1567 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1568 struct data_desc *txd,
1569 struct txdata_entry_desc *desc,
1570 struct ieee80211_hdr *ieee80211hdr,
1571 unsigned int length,
1572 struct ieee80211_tx_control *control)
1573 {
1574 u32 word;
1575
1576 /*
1577 * Start writing the descriptor words.
1578 */
1579 rt2x00_desc_read(txd, 1, &word);
1580 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1581 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1582 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1583 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1584 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1585 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1586 rt2x00_desc_write(txd, 1, word);
1587
1588 rt2x00_desc_read(txd, 2, &word);
1589 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1590 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1591 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1592 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1593 rt2x00_desc_write(txd, 2, word);
1594
1595 rt2x00_desc_read(txd, 5, &word);
1596 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1597 TXPOWER_TO_DEV(control->power_level));
1598 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1599 rt2x00_desc_write(txd, 5, word);
1600
1601 rt2x00_desc_read(txd, 11, &word);
1602 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, length);
1603 rt2x00_desc_write(txd, 11, word);
1604
1605 rt2x00_desc_read(txd, 0, &word);
1606 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1607 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1608 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1609 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1610 rt2x00_set_field32(&word, TXD_W0_ACK,
1611 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1612 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1613 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1614 rt2x00_set_field32(&word, TXD_W0_OFDM,
1615 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1616 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1617 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1618 !!(control->flags &
1619 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1620 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1621 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1622 rt2x00_set_field32(&word, TXD_W0_BURST,
1623 test_bit(ENTRY_TXD_BURST, &desc->flags));
1624 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1625 rt2x00_desc_write(txd, 0, word);
1626 }
1627
1628 /*
1629 * TX data initialization
1630 */
1631 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1632 unsigned int queue)
1633 {
1634 u32 reg;
1635
1636 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1637 /*
1638 * For Wi-Fi faily generated beacons between participating
1639 * stations. Set TBTT phase adaptive adjustment step to 8us.
1640 */
1641 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1642
1643 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1644 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1645 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1646 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1647 }
1648 return;
1649 }
1650
1651 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1652 if (queue == IEEE80211_TX_QUEUE_DATA0)
1653 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1654 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1655 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1656 else if (queue == IEEE80211_TX_QUEUE_DATA2)
1657 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1658 else if (queue == IEEE80211_TX_QUEUE_DATA3)
1659 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1660 else if (queue == IEEE80211_TX_QUEUE_DATA4)
1661 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_MGMT, 1);
1662 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1663 }
1664
1665 /*
1666 * RX control handlers
1667 */
1668 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1669 {
1670 u16 eeprom;
1671 u8 offset;
1672 u8 lna;
1673
1674 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1675 switch (lna) {
1676 case 3:
1677 offset = 90;
1678 break;
1679 case 2:
1680 offset = 74;
1681 break;
1682 case 1:
1683 offset = 64;
1684 break;
1685 default:
1686 return 0;
1687 }
1688
1689 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1690 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1691 offset += 14;
1692
1693 if (lna == 3 || lna == 2)
1694 offset += 10;
1695
1696 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1697 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1698 } else {
1699 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1700 offset += 14;
1701
1702 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1703 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1704 }
1705
1706 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1707 }
1708
1709 static void rt61pci_fill_rxdone(struct data_entry *entry,
1710 struct rxdata_entry_desc *desc)
1711 {
1712 struct data_desc *rxd = entry->priv;
1713 u32 word0;
1714 u32 word1;
1715
1716 rt2x00_desc_read(rxd, 0, &word0);
1717 rt2x00_desc_read(rxd, 1, &word1);
1718
1719 desc->flags = 0;
1720 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1721 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1722
1723 /*
1724 * Obtain the status about this packet.
1725 */
1726 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1727 desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
1728 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1729 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1730
1731 return;
1732 }
1733
1734 /*
1735 * Interrupt functions.
1736 */
1737 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1738 {
1739 struct data_ring *ring;
1740 struct data_entry *entry;
1741 struct data_entry *entry_done;
1742 struct data_desc *txd;
1743 u32 word;
1744 u32 reg;
1745 u32 old_reg;
1746 int type;
1747 int index;
1748 int tx_status;
1749 int retry;
1750
1751 /*
1752 * During each loop we will compare the freshly read
1753 * STA_CSR4 register value with the value read from
1754 * the previous loop. If the 2 values are equal then
1755 * we should stop processing because the chance it
1756 * quite big that the device has been unplugged and
1757 * we risk going into an endless loop.
1758 */
1759 old_reg = 0;
1760
1761 while (1) {
1762 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1763 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1764 break;
1765
1766 if (old_reg == reg)
1767 break;
1768 old_reg = reg;
1769
1770 /*
1771 * Skip this entry when it contains an invalid
1772 * ring identication number.
1773 */
1774 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1775 ring = rt2x00lib_get_ring(rt2x00dev, type);
1776 if (unlikely(!ring))
1777 continue;
1778
1779 /*
1780 * Skip this entry when it contains an invalid
1781 * index number.
1782 */
1783 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1784 if (unlikely(index >= ring->stats.limit))
1785 continue;
1786
1787 entry = &ring->entry[index];
1788 txd = entry->priv;
1789 rt2x00_desc_read(txd, 0, &word);
1790
1791 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1792 !rt2x00_get_field32(word, TXD_W0_VALID))
1793 return;
1794
1795 entry_done = rt2x00_get_data_entry_done(ring);
1796 while (entry != entry_done) {
1797 /* Catch up. Just report any entries we missed as
1798 * failed. */
1799 WARNING(rt2x00dev,
1800 "TX status report missed for entry %p\n",
1801 entry_done);
1802 rt2x00lib_txdone(entry_done, TX_FAIL_OTHER, 0);
1803 entry_done = rt2x00_get_data_entry_done(ring);
1804 }
1805
1806 /*
1807 * Obtain the status about this packet.
1808 */
1809 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1810 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1811
1812 rt2x00lib_txdone(entry, tx_status, retry);
1813
1814 /*
1815 * Make this entry available for reuse.
1816 */
1817 entry->flags = 0;
1818 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1819 rt2x00_desc_write(txd, 0, word);
1820 rt2x00_ring_index_done_inc(entry->ring);
1821
1822 /*
1823 * If the data ring was full before the txdone handler
1824 * we must make sure the packet queue in the mac80211 stack
1825 * is reenabled when the txdone handler has finished.
1826 */
1827 if (!rt2x00_ring_full(ring))
1828 ieee80211_wake_queue(rt2x00dev->hw,
1829 entry->tx_status.control.queue);
1830 }
1831 }
1832
1833 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1834 {
1835 struct rt2x00_dev *rt2x00dev = dev_instance;
1836 u32 reg_mcu;
1837 u32 reg;
1838
1839 /*
1840 * Get the interrupt sources & saved to local variable.
1841 * Write register value back to clear pending interrupts.
1842 */
1843 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1844 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1845
1846 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1847 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1848
1849 if (!reg && !reg_mcu)
1850 return IRQ_NONE;
1851
1852 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1853 return IRQ_HANDLED;
1854
1855 /*
1856 * Handle interrupts, walk through all bits
1857 * and run the tasks, the bits are checked in order of
1858 * priority.
1859 */
1860
1861 /*
1862 * 1 - Rx ring done interrupt.
1863 */
1864 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1865 rt2x00pci_rxdone(rt2x00dev);
1866
1867 /*
1868 * 2 - Tx ring done interrupt.
1869 */
1870 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1871 rt61pci_txdone(rt2x00dev);
1872
1873 /*
1874 * 3 - Handle MCU command done.
1875 */
1876 if (reg_mcu)
1877 rt2x00pci_register_write(rt2x00dev,
1878 M2H_CMD_DONE_CSR, 0xffffffff);
1879
1880 return IRQ_HANDLED;
1881 }
1882
1883 /*
1884 * Device probe functions.
1885 */
1886 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1887 {
1888 struct eeprom_93cx6 eeprom;
1889 u32 reg;
1890 u16 word;
1891 u8 *mac;
1892 s8 value;
1893
1894 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1895
1896 eeprom.data = rt2x00dev;
1897 eeprom.register_read = rt61pci_eepromregister_read;
1898 eeprom.register_write = rt61pci_eepromregister_write;
1899 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1900 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1901 eeprom.reg_data_in = 0;
1902 eeprom.reg_data_out = 0;
1903 eeprom.reg_data_clock = 0;
1904 eeprom.reg_chip_select = 0;
1905
1906 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1907 EEPROM_SIZE / sizeof(u16));
1908
1909 /*
1910 * Start validation of the data that has been read.
1911 */
1912 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1913 if (!is_valid_ether_addr(mac)) {
1914 DECLARE_MAC_BUF(macbuf);
1915
1916 random_ether_addr(mac);
1917 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1918 }
1919
1920 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1921 if (word == 0xffff) {
1922 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1923 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2);
1924 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2);
1925 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1926 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1927 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1928 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1929 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1930 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1931 }
1932
1933 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1934 if (word == 0xffff) {
1935 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1936 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1937 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1938 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1939 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1940 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1941 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1942 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1943 }
1944
1945 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1946 if (word == 0xffff) {
1947 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1948 LED_MODE_DEFAULT);
1949 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1950 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1951 }
1952
1953 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1954 if (word == 0xffff) {
1955 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1956 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1957 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1958 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1959 }
1960
1961 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1962 if (word == 0xffff) {
1963 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1964 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1965 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1966 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1967 } else {
1968 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1969 if (value < -10 || value > 10)
1970 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1971 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1972 if (value < -10 || value > 10)
1973 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1974 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1975 }
1976
1977 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1978 if (word == 0xffff) {
1979 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1980 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1981 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1982 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1983 } else {
1984 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1985 if (value < -10 || value > 10)
1986 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1987 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1988 if (value < -10 || value > 10)
1989 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1990 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1991 }
1992
1993 return 0;
1994 }
1995
1996 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1997 {
1998 u32 reg;
1999 u16 value;
2000 u16 eeprom;
2001 u16 device;
2002
2003 /*
2004 * Read EEPROM word for configuration.
2005 */
2006 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2007
2008 /*
2009 * Identify RF chipset.
2010 * To determine the RT chip we have to read the
2011 * PCI header of the device.
2012 */
2013 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
2014 PCI_CONFIG_HEADER_DEVICE, &device);
2015 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2016 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2017 rt2x00_set_chip(rt2x00dev, device, value, reg);
2018
2019 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2020 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2021 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2022 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2023 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2024 return -ENODEV;
2025 }
2026
2027 /*
2028 * Identify default antenna configuration.
2029 */
2030 rt2x00dev->hw->conf.antenna_sel_tx =
2031 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2032 rt2x00dev->hw->conf.antenna_sel_rx =
2033 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2034
2035 /*
2036 * Read the Frame type.
2037 */
2038 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2039 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2040
2041 /*
2042 * Determine number of antenna's.
2043 */
2044 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2045 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2046
2047 /*
2048 * Detect if this device has an hardware controlled radio.
2049 */
2050 #ifdef CONFIG_RT61PCI_RFKILL
2051 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2052 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2053 #endif /* CONFIG_RT61PCI_RFKILL */
2054
2055 /*
2056 * Read frequency offset and RF programming sequence.
2057 */
2058 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2059 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2060 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2061
2062 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2063
2064 /*
2065 * Read external LNA informations.
2066 */
2067 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2068
2069 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2070 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2071 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2072 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2073
2074 /*
2075 * Store led settings, for correct led behaviour.
2076 * If the eeprom value is invalid,
2077 * switch to default led mode.
2078 */
2079 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2080
2081 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2082
2083 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2084 rt2x00dev->led_mode);
2085 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2086 rt2x00_get_field16(eeprom,
2087 EEPROM_LED_POLARITY_GPIO_0));
2088 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2089 rt2x00_get_field16(eeprom,
2090 EEPROM_LED_POLARITY_GPIO_1));
2091 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2092 rt2x00_get_field16(eeprom,
2093 EEPROM_LED_POLARITY_GPIO_2));
2094 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2095 rt2x00_get_field16(eeprom,
2096 EEPROM_LED_POLARITY_GPIO_3));
2097 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2098 rt2x00_get_field16(eeprom,
2099 EEPROM_LED_POLARITY_GPIO_4));
2100 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2101 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2102 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2103 rt2x00_get_field16(eeprom,
2104 EEPROM_LED_POLARITY_RDY_G));
2105 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2106 rt2x00_get_field16(eeprom,
2107 EEPROM_LED_POLARITY_RDY_A));
2108
2109 return 0;
2110 }
2111
2112 /*
2113 * RF value list for RF5225 & RF5325
2114 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2115 */
2116 static const struct rf_channel rf_vals_noseq[] = {
2117 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2118 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2119 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2120 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2121 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2122 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2123 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2124 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2125 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2126 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2127 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2128 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2129 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2130 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2131
2132 /* 802.11 UNI / HyperLan 2 */
2133 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2134 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2135 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2136 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2137 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2138 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2139 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2140 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2141
2142 /* 802.11 HyperLan 2 */
2143 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2144 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2145 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2146 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2147 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2148 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2149 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2150 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2151 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2152 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2153
2154 /* 802.11 UNII */
2155 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2156 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2157 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2158 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2159 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2160 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2161
2162 /* MMAC(Japan)J52 ch 34,38,42,46 */
2163 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2164 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2165 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2166 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2167 };
2168
2169 /*
2170 * RF value list for RF5225 & RF5325
2171 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2172 */
2173 static const struct rf_channel rf_vals_seq[] = {
2174 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2175 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2176 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2177 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2178 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2179 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2180 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2181 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2182 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2183 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2184 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2185 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2186 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2187 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2188
2189 /* 802.11 UNI / HyperLan 2 */
2190 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2191 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2192 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2193 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2194 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2195 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2196 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2197 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2198
2199 /* 802.11 HyperLan 2 */
2200 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2201 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2202 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2203 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2204 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2205 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2206 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2207 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2208 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2209 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2210
2211 /* 802.11 UNII */
2212 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2213 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2214 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2215 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2216 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2217 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2218
2219 /* MMAC(Japan)J52 ch 34,38,42,46 */
2220 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2221 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2222 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2223 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2224 };
2225
2226 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2227 {
2228 struct hw_mode_spec *spec = &rt2x00dev->spec;
2229 u8 *txpower;
2230 unsigned int i;
2231
2232 /*
2233 * Initialize all hw fields.
2234 */
2235 rt2x00dev->hw->flags =
2236 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2237 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2238 rt2x00dev->hw->extra_tx_headroom = 0;
2239 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2240 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2241 rt2x00dev->hw->queues = 5;
2242
2243 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2244 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2245 rt2x00_eeprom_addr(rt2x00dev,
2246 EEPROM_MAC_ADDR_0));
2247
2248 /*
2249 * Convert tx_power array in eeprom.
2250 */
2251 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2252 for (i = 0; i < 14; i++)
2253 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2254
2255 /*
2256 * Initialize hw_mode information.
2257 */
2258 spec->num_modes = 2;
2259 spec->num_rates = 12;
2260 spec->tx_power_a = NULL;
2261 spec->tx_power_bg = txpower;
2262 spec->tx_power_default = DEFAULT_TXPOWER;
2263
2264 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2265 spec->num_channels = 14;
2266 spec->channels = rf_vals_noseq;
2267 } else {
2268 spec->num_channels = 14;
2269 spec->channels = rf_vals_seq;
2270 }
2271
2272 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2273 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2274 spec->num_modes = 3;
2275 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2276
2277 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2278 for (i = 0; i < 14; i++)
2279 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2280
2281 spec->tx_power_a = txpower;
2282 }
2283 }
2284
2285 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2286 {
2287 int retval;
2288
2289 /*
2290 * Allocate eeprom data.
2291 */
2292 retval = rt61pci_validate_eeprom(rt2x00dev);
2293 if (retval)
2294 return retval;
2295
2296 retval = rt61pci_init_eeprom(rt2x00dev);
2297 if (retval)
2298 return retval;
2299
2300 /*
2301 * Initialize hw specifications.
2302 */
2303 rt61pci_probe_hw_mode(rt2x00dev);
2304
2305 /*
2306 * This device requires firmware
2307 */
2308 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2309
2310 /*
2311 * Set the rssi offset.
2312 */
2313 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2314
2315 return 0;
2316 }
2317
2318 /*
2319 * IEEE80211 stack callback functions.
2320 */
2321 static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2322 unsigned int changed_flags,
2323 unsigned int *total_flags,
2324 int mc_count,
2325 struct dev_addr_list *mc_list)
2326 {
2327 struct rt2x00_dev *rt2x00dev = hw->priv;
2328 struct interface *intf = &rt2x00dev->interface;
2329 u32 reg;
2330
2331 /*
2332 * Mask off any flags we are going to ignore from
2333 * the total_flags field.
2334 */
2335 *total_flags &=
2336 FIF_ALLMULTI |
2337 FIF_FCSFAIL |
2338 FIF_PLCPFAIL |
2339 FIF_CONTROL |
2340 FIF_OTHER_BSS |
2341 FIF_PROMISC_IN_BSS;
2342
2343 /*
2344 * Apply some rules to the filters:
2345 * - Some filters imply different filters to be set.
2346 * - Some things we can't filter out at all.
2347 * - Some filters are set based on interface type.
2348 */
2349 if (mc_count)
2350 *total_flags |= FIF_ALLMULTI;
2351 if (*total_flags & FIF_OTHER_BSS ||
2352 *total_flags & FIF_PROMISC_IN_BSS)
2353 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2354 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
2355 *total_flags |= FIF_PROMISC_IN_BSS;
2356
2357 /*
2358 * Check if there is any work left for us.
2359 */
2360 if (intf->filter == *total_flags)
2361 return;
2362 intf->filter = *total_flags;
2363
2364 /*
2365 * Start configuration steps.
2366 * Note that the version error will always be dropped
2367 * and broadcast frames will always be accepted since
2368 * there is no filter for it at this time.
2369 */
2370 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2371 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2372 !(*total_flags & FIF_FCSFAIL));
2373 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2374 !(*total_flags & FIF_PLCPFAIL));
2375 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2376 !(*total_flags & FIF_CONTROL));
2377 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2378 !(*total_flags & FIF_PROMISC_IN_BSS));
2379 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2380 !(*total_flags & FIF_PROMISC_IN_BSS));
2381 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2382 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2383 !(*total_flags & FIF_ALLMULTI));
2384 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0);
2385 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
2386 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2387 }
2388
2389 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2390 u32 short_retry, u32 long_retry)
2391 {
2392 struct rt2x00_dev *rt2x00dev = hw->priv;
2393 u32 reg;
2394
2395 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2396 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2397 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2398 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2399
2400 return 0;
2401 }
2402
2403 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2404 {
2405 struct rt2x00_dev *rt2x00dev = hw->priv;
2406 u64 tsf;
2407 u32 reg;
2408
2409 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2410 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2411 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2412 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2413
2414 return tsf;
2415 }
2416
2417 static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2418 {
2419 struct rt2x00_dev *rt2x00dev = hw->priv;
2420
2421 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2422 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2423 }
2424
2425 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2426 struct ieee80211_tx_control *control)
2427 {
2428 struct rt2x00_dev *rt2x00dev = hw->priv;
2429
2430 /*
2431 * Just in case the ieee80211 doesn't set this,
2432 * but we need this queue set for the descriptor
2433 * initialization.
2434 */
2435 control->queue = IEEE80211_TX_QUEUE_BEACON;
2436
2437 /*
2438 * We need to append the descriptor in front of the
2439 * beacon frame.
2440 */
2441 if (skb_headroom(skb) < TXD_DESC_SIZE) {
2442 if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
2443 dev_kfree_skb(skb);
2444 return -ENOMEM;
2445 }
2446 }
2447
2448 /*
2449 * First we create the beacon.
2450 */
2451 skb_push(skb, TXD_DESC_SIZE);
2452 memset(skb->data, 0, TXD_DESC_SIZE);
2453
2454 rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
2455 (struct ieee80211_hdr *)(skb->data +
2456 TXD_DESC_SIZE),
2457 skb->len - TXD_DESC_SIZE, control);
2458
2459 /*
2460 * Write entire beacon with descriptor to register,
2461 * and kick the beacon generator.
2462 */
2463 rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0,
2464 skb->data, skb->len);
2465 rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
2466
2467 return 0;
2468 }
2469
2470 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2471 .tx = rt2x00mac_tx,
2472 .start = rt2x00mac_start,
2473 .stop = rt2x00mac_stop,
2474 .add_interface = rt2x00mac_add_interface,
2475 .remove_interface = rt2x00mac_remove_interface,
2476 .config = rt2x00mac_config,
2477 .config_interface = rt2x00mac_config_interface,
2478 .configure_filter = rt61pci_configure_filter,
2479 .get_stats = rt2x00mac_get_stats,
2480 .set_retry_limit = rt61pci_set_retry_limit,
2481 .erp_ie_changed = rt2x00mac_erp_ie_changed,
2482 .conf_tx = rt2x00mac_conf_tx,
2483 .get_tx_stats = rt2x00mac_get_tx_stats,
2484 .get_tsf = rt61pci_get_tsf,
2485 .reset_tsf = rt61pci_reset_tsf,
2486 .beacon_update = rt61pci_beacon_update,
2487 };
2488
2489 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2490 .irq_handler = rt61pci_interrupt,
2491 .probe_hw = rt61pci_probe_hw,
2492 .get_firmware_name = rt61pci_get_firmware_name,
2493 .load_firmware = rt61pci_load_firmware,
2494 .initialize = rt2x00pci_initialize,
2495 .uninitialize = rt2x00pci_uninitialize,
2496 .set_device_state = rt61pci_set_device_state,
2497 .rfkill_poll = rt61pci_rfkill_poll,
2498 .link_stats = rt61pci_link_stats,
2499 .reset_tuner = rt61pci_reset_tuner,
2500 .link_tuner = rt61pci_link_tuner,
2501 .write_tx_desc = rt61pci_write_tx_desc,
2502 .write_tx_data = rt2x00pci_write_tx_data,
2503 .kick_tx_queue = rt61pci_kick_tx_queue,
2504 .fill_rxdone = rt61pci_fill_rxdone,
2505 .config_mac_addr = rt61pci_config_mac_addr,
2506 .config_bssid = rt61pci_config_bssid,
2507 .config_type = rt61pci_config_type,
2508 .config_preamble = rt61pci_config_preamble,
2509 .config = rt61pci_config,
2510 };
2511
2512 static const struct rt2x00_ops rt61pci_ops = {
2513 .name = DRV_NAME,
2514 .rxd_size = RXD_DESC_SIZE,
2515 .txd_size = TXD_DESC_SIZE,
2516 .eeprom_size = EEPROM_SIZE,
2517 .rf_size = RF_SIZE,
2518 .lib = &rt61pci_rt2x00_ops,
2519 .hw = &rt61pci_mac80211_ops,
2520 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2521 .debugfs = &rt61pci_rt2x00debug,
2522 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2523 };
2524
2525 /*
2526 * RT61pci module information.
2527 */
2528 static struct pci_device_id rt61pci_device_table[] = {
2529 /* RT2561s */
2530 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2531 /* RT2561 v2 */
2532 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2533 /* RT2661 */
2534 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2535 { 0, }
2536 };
2537
2538 MODULE_AUTHOR(DRV_PROJECT);
2539 MODULE_VERSION(DRV_VERSION);
2540 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2541 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2542 "PCI & PCMCIA chipset based cards");
2543 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2544 MODULE_FIRMWARE(FIRMWARE_RT2561);
2545 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2546 MODULE_FIRMWARE(FIRMWARE_RT2661);
2547 MODULE_LICENSE("GPL");
2548
2549 static struct pci_driver rt61pci_driver = {
2550 .name = DRV_NAME,
2551 .id_table = rt61pci_device_table,
2552 .probe = rt2x00pci_probe,
2553 .remove = __devexit_p(rt2x00pci_remove),
2554 .suspend = rt2x00pci_suspend,
2555 .resume = rt2x00pci_resume,
2556 };
2557
2558 static int __init rt61pci_init(void)
2559 {
2560 return pci_register_driver(&rt61pci_driver);
2561 }
2562
2563 static void __exit rt61pci_exit(void)
2564 {
2565 pci_unregister_driver(&rt61pci_driver);
2566 }
2567
2568 module_init(rt61pci_init);
2569 module_exit(rt61pci_exit);
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