3 /******************************************************************************
4 Copyright (c) 2002, Infineon Technologies. All rights reserved.
7 Because the program is licensed free of charge, there is no warranty for
8 the program, to the extent permitted by applicable law. Except when
9 otherwise stated in writing the copyright holders and/or other parties
10 provide the program "as is" without warranty of any kind, either
11 expressed or implied, including, but not limited to, the implied
12 warranties of merchantability and fitness for a particular purpose. The
13 entire risk as to the quality and performance of the program is with
14 you. should the program prove defective, you assume the cost of all
15 necessary servicing, repair or correction.
17 In no event unless required by applicable law or agreed to in writing
18 will any copyright holder, or any other party who may modify and/or
19 redistribute the program as permitted above, be liable to you for
20 damages, including any general, special, incidental or consequential
21 damages arising out of the use or inability to use the program
22 (including but not limited to loss of data or data being rendered
23 inaccurate or losses sustained by you or third parties or a failure of
24 the program to operate with any other programs), even if such holder or
25 other party has been advised of the possibility of such damages.
26 ******************************************************************************/
28 /***********************************************************************/
29 /* Module : MEI register address and bits */
30 /***********************************************************************/
31 #define MEI_SPACE_ACCESS 0xB0100C00
32 #define MEI_DATA_XFR (0x0000 + MEI_SPACE_ACCESS)
33 #define MEI_VERSION (0x0200 + MEI_SPACE_ACCESS)
34 #define ARC_GP_STAT (0x0204 + MEI_SPACE_ACCESS)
35 #define MEI_XFR_ADDR (0x020C + MEI_SPACE_ACCESS)
36 #define MEI_TO_ARC_INT (0x021C + MEI_SPACE_ACCESS)
37 #define ARC_TO_MEI_INT (0x0220 + MEI_SPACE_ACCESS)
38 #define ARC_TO_MEI_INT_MASK (0x0224 + MEI_SPACE_ACCESS)
39 #define MEI_DEBUG_WAD (0x0228 + MEI_SPACE_ACCESS)
40 #define MEI_DEBUG_RAD (0x022C + MEI_SPACE_ACCESS)
41 #define MEI_DEBUG_DATA (0x0230 + MEI_SPACE_ACCESS)
42 #define MEI_DEBUG_DEC (0x0234 + MEI_SPACE_ACCESS)
43 #define MEI_CONTROL (0x0238 + MEI_SPACE_ACCESS)
44 #define AT_CELLRDY_BC0 (0x023C + MEI_SPACE_ACCESS)
45 #define AT_CELLRDY_BC1 (0x0240 + MEI_SPACE_ACCESS)
46 #define AR_CELLRDY_BC0 (0x0244 + MEI_SPACE_ACCESS)
47 #define AR_CELLRDY_BC1 (0x0248 + MEI_SPACE_ACCESS)
48 #define AAI_ACCESS (0x024C + MEI_SPACE_ACCESS)
49 #define AAITXCB0 (0x0300 + MEI_SPACE_ACCESS)
50 #define AAITXCB1 (0x0304 + MEI_SPACE_ACCESS)
51 #define AAIRXCB0 (0x0308 + MEI_SPACE_ACCESS)
52 #define AAIRXCB1 (0x030C + MEI_SPACE_ACCESS)
55 /***********************************************************************/
56 /* Module : WDT register address and bits */
57 /***********************************************************************/
58 #define DANUBE_BIU_WDT_BASE (0xBf8803F0)
59 #define DANUBE_BIU_WDT_CR (0x0000 + DANUBE_BIU_WDT_BASE)
60 #define DANUBE_BIU_WDT_SR (0x0008 + DANUBE_BIU_WDT_BASE)
63 /***********************************************************************/
64 /* Module : PMU register address and bits */
65 /***********************************************************************/
66 #define DANUBE_PMU_BASE_ADDR (KSEG1+0x1F102000)
68 /***PM Control Register***/
69 #define DANUBE_PMU_CR ((volatile u32*)(0x001C + DANUBE_PMU_BASE_ADDR))
70 #define DANUBE_PMU_PWDCR DANUBE_PMU_CR
71 #define DANUBE_PMU_SR ((volatile u32*)(0x0020 + DANUBE_PMU_BASE_ADDR))
73 #define DANUBE_PMU_DMA_SHIFT 5
74 #define DANUBE_PMU_PPE_SHIFT 13
75 #define DANUBE_PMU_ETOP_SHIFT 22
76 #define DANUBE_PMU_ENET0_SHIFT 24
77 #define DANUBE_PMU_ENET1_SHIFT 25
80 #define DANUBE_PMU DANUBE_PMU_BASE_ADDR
81 /***PM Global Enable Register***/
82 #define DANUBE_PMU_PM_GEN ((volatile u32*)(DANUBE_PMU+ 0x0000))
83 #define DANUBE_PMU_PM_GEN_EN16 (1 << 16)
84 #define DANUBE_PMU_PM_GEN_EN15 (1 << 15)
85 #define DANUBE_PMU_PM_GEN_EN14 (1 << 14)
86 #define DANUBE_PMU_PM_GEN_EN13 (1 << 13)
87 #define DANUBE_PMU_PM_GEN_EN12 (1 << 12)
88 #define DANUBE_PMU_PM_GEN_EN11 (1 << 11)
89 #define DANUBE_PMU_PM_GEN_EN10 (1 << 10)
90 #define DANUBE_PMU_PM_GEN_EN9 (1 << 9)
91 #define DANUBE_PMU_PM_GEN_EN8 (1 << 8)
92 #define DANUBE_PMU_PM_GEN_EN7 (1 << 7)
93 #define DANUBE_PMU_PM_GEN_EN6 (1 << 6)
94 #define DANUBE_PMU_PM_GEN_EN5 (1 << 5)
95 #define DANUBE_PMU_PM_GEN_EN4 (1 << 4)
96 #define DANUBE_PMU_PM_GEN_EN3 (1 << 3)
97 #define DANUBE_PMU_PM_GEN_EN2 (1 << 2)
98 #define DANUBE_PMU_PM_GEN_EN0 (1 << 0)
100 /***PM Power Down Enable Register***/
101 #define DANUBE_PMU_PM_PDEN ((volatile u32*)(DANUBE_PMU+ 0x0008))
102 #define DANUBE_PMU_PM_PDEN_EN16 (1 << 16)
103 #define DANUBE_PMU_PM_PDEN_EN15 (1 << 15)
104 #define DANUBE_PMU_PM_PDEN_EN14 (1 << 14)
105 #define DANUBE_PMU_PM_PDEN_EN13 (1 << 13)
106 #define DANUBE_PMU_PM_PDEN_EN12 (1 << 12)
107 #define DANUBE_PMU_PM_PDEN_EN11 (1 << 11)
108 #define DANUBE_PMU_PM_PDEN_EN10 (1 << 10)
109 #define DANUBE_PMU_PM_PDEN_EN9 (1 << 9)
110 #define DANUBE_PMU_PM_PDEN_EN8 (1 << 8)
111 #define DANUBE_PMU_PM_PDEN_EN7 (1 << 7)
112 #define DANUBE_PMU_PM_PDEN_EN5 (1 << 5)
113 #define DANUBE_PMU_PM_PDEN_EN4 (1 << 4)
114 #define DANUBE_PMU_PM_PDEN_EN3 (1 << 3)
115 #define DANUBE_PMU_PM_PDEN_EN2 (1 << 2)
116 #define DANUBE_PMU_PM_PDEN_EN0 (1 << 0)
118 /***PM Wake-Up from Power Down Register***/
119 #define DANUBE_PMU_PM_WUP ((volatile u32*)(DANUBE_PMU+ 0x0010))
120 #define DANUBE_PMU_PM_WUP_WUP16 (1 << 16)
121 #define DANUBE_PMU_PM_WUP_WUP15 (1 << 15)
122 #define DANUBE_PMU_PM_WUP_WUP14 (1 << 14)
123 #define DANUBE_PMU_PM_WUP_WUP13 (1 << 13)
124 #define DANUBE_PMU_PM_WUP_WUP12 (1 << 12)
125 #define DANUBE_PMU_PM_WUP_WUP11 (1 << 11)
126 #define DANUBE_PMU_PM_WUP_WUP10 (1 << 10)
127 #define DANUBE_PMU_PM_WUP_WUP9 (1 << 9)
128 #define DANUBE_PMU_PM_WUP_WUP8 (1 << 8)
129 #define DANUBE_PMU_PM_PDEN_EN7 (1 << 7)
130 #define DANUBE_PMU_PM_PDEN_EN5 (1 << 5)
131 #define DANUBE_PMU_PM_PDEN_EN4 (1 << 4)
132 #define DANUBE_PMU_PM_PDEN_EN3 (1 << 3)
133 #define DANUBE_PMU_PM_PDEN_EN2 (1 << 2)
134 #define DANUBE_PMU_PM_PDEN_EN0 (1 << 0)
136 /***PM Wake-Up from Power Down Register***/
137 #define DANUBE_PMU_PM_WUP ((volatile u32*)(DANUBE_PMU+ 0x0010))
138 #define DANUBE_PMU_PM_WUP_WUP16 (1 << 16)
139 #define DANUBE_PMU_PM_WUP_WUP15 (1 << 15)
140 #define DANUBE_PMU_PM_WUP_WUP14 (1 << 14)
141 #define DANUBE_PMU_PM_WUP_WUP13 (1 << 13)
142 #define DANUBE_PMU_PM_WUP_WUP12 (1 << 12)
143 #define DANUBE_PMU_PM_WUP_WUP11 (1 << 11)
144 #define DANUBE_PMU_PM_WUP_WUP10 (1 << 10)
145 #define DANUBE_PMU_PM_WUP_WUP9 (1 << 9)
146 #define DANUBE_PMU_PM_WUP_WUP8 (1 << 8)
147 #define DANUBE_PMU_PM_WUP_WUP7 (1 << 7)
148 #define DANUBE_PMU_PM_WUP_WUP5 (1 << 5)
149 #define DANUBE_PMU_PM_WUP_WUP4 (1 << 4)
150 #define DANUBE_PMU_PM_WUP_WUP3 (1 << 3)
151 #define DANUBE_PMU_PM_WUP_WUP2 (1 << 2)
152 #define DANUBE_PMU_PM_WUP_WUP0 (1 << 0)
154 /***PM Control Register***/
155 #define DANUBE_PMU_PM_CR ((volatile u32*)(DANUBE_PMU+ 0x0014))
156 #define DANUBE_PMU_PM_CR_AWEN (1 << 31)
157 #define DANUBE_PMU_PM_CR_SWRST (1 << 30)
158 #define DANUBE_PMU_PM_CR_SWCR (1 << 2)
159 #define DANUBE_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0)
161 /***********************************************************************/
162 /* Module : RCU register address and bits */
163 /***********************************************************************/
164 #define DANUBE_RCU_BASE_ADDR (0xBF203000)
166 #define DANUBE_RCU_REQ (0x0010 + DANUBE_RCU_BASE_ADDR)
167 #define DANUBE_RCU_RST_REQ ((volatile u32*)(DANUBE_RCU_REQ))
168 #define DANUBE_RCU_STAT (0x0014 + DANUBE_RCU_BASE_ADDR)
169 #define DANUBE_RCU_RST_SR ( (volatile u32 *)(DANUBE_RCU_STAT))
170 #define DANUBE_RCU_PCI_RDY ( (volatile u32 *)(DANUBE_RCU_BASE_ADDR+0x28))
171 #define DANUBE_RCU_MON (0x0030 + DANUBE_RCU_BASE_ADDR)
174 /***********************************************************************/
175 /* Module : BCU register address and bits */
176 /***********************************************************************/
177 #define DANUBE_BCU_BASE_ADDR (0xB0100000)
178 /***BCU Control Register (0010H)***/
179 #define DANUBE_BCU_CON (0x0010 + DANUBE_BCU_BASE_ADDR)
180 #define DANUBE_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24)
181 #define DANUBE_BCU_BCU_CON_SPE (1 << 19)
182 #define DANUBE_BCU_BCU_CON_PSE (1 << 18)
183 #define DANUBE_BCU_BCU_CON_DBG (1 << 16)
184 #define DANUBE_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0)
187 /***BCU Error Control Capture Register (0020H)***/
188 #define DANUBE_BCU_ECON (0x0020 + DANUBE_BCU_BASE_ADDR)
189 #define DANUBE_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24)
190 #define DANUBE_BCU_BCU_ECON_RDN (1 << 23)
191 #define DANUBE_BCU_BCU_ECON_WRN (1 << 22)
192 #define DANUBE_BCU_BCU_ECON_SVM (1 << 21)
193 #define DANUBE_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19)
194 #define DANUBE_BCU_BCU_ECON_ABT (1 << 18)
195 #define DANUBE_BCU_BCU_ECON_RDY (1 << 17)
196 #define DANUBE_BCU_BCU_ECON_TOUT (1 << 16)
197 #define DANUBE_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0)
198 #define DANUBE_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28)
200 /***BCU Error Address Capture Register (0024 H)***/
201 #define DANUBE_BCU_EADD (0x0024 + DANUBE_BCU_BASE_ADDR)
203 /***BCU Error Data Capture Register (0028H)***/
204 #define DANUBE_BCU_EDAT (0x0028 + DANUBE_BCU_BASE_ADDR)
206 #define DANUBE_BCU_IRNEN (0x00F4 + DANUBE_BCU_BASE_ADDR)
207 #define DANUBE_BCU_IRNICR (0x00F8 + DANUBE_BCU_BASE_ADDR)
208 #define DANUBE_BCU_IRNCR (0x00FC + DANUBE_BCU_BASE_ADDR)
211 /***********************************************************************/
212 /* Module : MBC register address and bits */
213 /***********************************************************************/
215 #define DANUBE_MBC (0xBF103000)
216 /***********************************************************************/
219 /***Mailbox CPU Configuration Register***/
220 #define DANUBE_MBC_MBC_CFG ((volatile u32*)(DANUBE_MBC+ 0x0080))
221 #define DANUBE_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6)
222 #define DANUBE_MBC_MBC_CFG_RES (1 << 5)
223 #define DANUBE_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1)
224 #define DANUBE_MBC_MBC_CFG_SIZE (1 << 0)
226 /***Mailbox CPU Interrupt Status Register***/
227 #define DANUBE_MBC_MBC_ISR ((volatile u32*)(DANUBE_MBC+ 0x0084))
228 #define DANUBE_MBC_MBC_ISR_B3DA (1 << 31)
229 #define DANUBE_MBC_MBC_ISR_B2DA (1 << 30)
230 #define DANUBE_MBC_MBC_ISR_B1E (1 << 29)
231 #define DANUBE_MBC_MBC_ISR_B0E (1 << 28)
232 #define DANUBE_MBC_MBC_ISR_WDT (1 << 27)
233 #define DANUBE_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
235 /***Mailbox CPU Mask Register***/
236 #define DANUBE_MBC_MBC_MSK ((volatile u32*)(DANUBE_MBC+ 0x0088))
237 #define DANUBE_MBC_MBC_MSK_B3DA (1 << 31)
238 #define DANUBE_MBC_MBC_MSK_B2DA (1 << 30)
239 #define DANUBE_MBC_MBC_MSK_B1E (1 << 29)
240 #define DANUBE_MBC_MBC_MSK_B0E (1 << 28)
241 #define DANUBE_MBC_MBC_MSK_WDT (1 << 27)
242 #define DANUBE_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
244 /***Mailbox CPU Mask 01 Register***/
245 #define DANUBE_MBC_MBC_MSK01 ((volatile u32*)(DANUBE_MBC+ 0x008C))
246 #define DANUBE_MBC_MBC_MSK01_B3DA (1 << 31)
247 #define DANUBE_MBC_MBC_MSK01_B2DA (1 << 30)
248 #define DANUBE_MBC_MBC_MSK01_B1E (1 << 29)
249 #define DANUBE_MBC_MBC_MSK01_B0E (1 << 28)
250 #define DANUBE_MBC_MBC_MSK01_WDT (1 << 27)
251 #define DANUBE_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
253 /***Mailbox CPU Mask 10 Register***/
254 #define DANUBE_MBC_MBC_MSK10 ((volatile u32*)(DANUBE_MBC+ 0x0090))
255 #define DANUBE_MBC_MBC_MSK10_B3DA (1 << 31)
256 #define DANUBE_MBC_MBC_MSK10_B2DA (1 << 30)
257 #define DANUBE_MBC_MBC_MSK10_B1E (1 << 29)
258 #define DANUBE_MBC_MBC_MSK10_B0E (1 << 28)
259 #define DANUBE_MBC_MBC_MSK10_WDT (1 << 27)
260 #define DANUBE_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
262 /***Mailbox CPU Short Command Register***/
263 #define DANUBE_MBC_MBC_CMD ((volatile u32*)(DANUBE_MBC+ 0x0094))
264 #define DANUBE_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0)
266 /***Mailbox CPU Input Data of Buffer 0***/
267 #define DANUBE_MBC_MBC_ID0 ((volatile u32*)(DANUBE_MBC+ 0x0000))
268 #define DANUBE_MBC_MBC_ID0_INDATA
270 /***Mailbox CPU Input Data of Buffer 1***/
271 #define DANUBE_MBC_MBC_ID1 ((volatile u32*)(DANUBE_MBC+ 0x0020))
272 #define DANUBE_MBC_MBC_ID1_INDATA
274 /***Mailbox CPU Output Data of Buffer 2***/
275 #define DANUBE_MBC_MBC_OD2 ((volatile u32*)(DANUBE_MBC+ 0x0040))
276 #define DANUBE_MBC_MBC_OD2_OUTDATA
278 /***Mailbox CPU Output Data of Buffer 3***/
279 #define DANUBE_MBC_MBC_OD3 ((volatile u32*)(DANUBE_MBC+ 0x0060))
280 #define DANUBE_MBC_MBC_OD3_OUTDATA
282 /***Mailbox CPU Control Register of Buffer 0***/
283 #define DANUBE_MBC_MBC_CR0 ((volatile u32*)(DANUBE_MBC+ 0x0004))
284 #define DANUBE_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
286 /***Mailbox CPU Control Register of Buffer 1***/
287 #define DANUBE_MBC_MBC_CR1 ((volatile u32*)(DANUBE_MBC+ 0x0024))
288 #define DANUBE_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
290 /***Mailbox CPU Control Register of Buffer 2***/
291 #define DANUBE_MBC_MBC_CR2 ((volatile u32*)(DANUBE_MBC+ 0x0044))
292 #define DANUBE_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
294 /***Mailbox CPU Control Register of Buffer 3***/
295 #define DANUBE_MBC_MBC_CR3 ((volatile u32*)(DANUBE_MBC+ 0x0064))
296 #define DANUBE_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
298 /***Mailbox CPU Free Space of Buffer 0***/
299 #define DANUBE_MBC_MBC_FS0 ((volatile u32*)(DANUBE_MBC+ 0x0008))
300 #define DANUBE_MBC_MBC_FS0_FS
302 /***Mailbox CPU Free Space of Buffer 1***/
303 #define DANUBE_MBC_MBC_FS1 ((volatile u32*)(DANUBE_MBC+ 0x0028))
304 #define DANUBE_MBC_MBC_FS1_FS
306 /***Mailbox CPU Free Space of Buffer 2***/
307 #define DANUBE_MBC_MBC_FS2 ((volatile u32*)(DANUBE_MBC+ 0x0048))
308 #define DANUBE_MBC_MBC_FS2_FS
310 /***Mailbox CPU Free Space of Buffer 3***/
311 #define DANUBE_MBC_MBC_FS3 ((volatile u32*)(DANUBE_MBC+ 0x0068))
312 #define DANUBE_MBC_MBC_FS3_FS
314 /***Mailbox CPU Data Available in Buffer 0***/
315 #define DANUBE_MBC_MBC_DA0 ((volatile u32*)(DANUBE_MBC+ 0x000C))
316 #define DANUBE_MBC_MBC_DA0_DA
318 /***Mailbox CPU Data Available in Buffer 1***/
319 #define DANUBE_MBC_MBC_DA1 ((volatile u32*)(DANUBE_MBC+ 0x002C))
320 #define DANUBE_MBC_MBC_DA1_DA
322 /***Mailbox CPU Data Available in Buffer 2***/
323 #define DANUBE_MBC_MBC_DA2 ((volatile u32*)(DANUBE_MBC+ 0x004C))
324 #define DANUBE_MBC_MBC_DA2_DA
326 /***Mailbox CPU Data Available in Buffer 3***/
327 #define DANUBE_MBC_MBC_DA3 ((volatile u32*)(DANUBE_MBC+ 0x006C))
328 #define DANUBE_MBC_MBC_DA3_DA
330 /***Mailbox CPU Input Absolute Pointer of Buffer 0***/
331 #define DANUBE_MBC_MBC_IABS0 ((volatile u32*)(DANUBE_MBC+ 0x0010))
332 #define DANUBE_MBC_MBC_IABS0_IABS
334 /***Mailbox CPU Input Absolute Pointer of Buffer 1***/
335 #define DANUBE_MBC_MBC_IABS1 ((volatile u32*)(DANUBE_MBC+ 0x0030))
336 #define DANUBE_MBC_MBC_IABS1_IABS
338 /***Mailbox CPU Input Absolute Pointer of Buffer 2***/
339 #define DANUBE_MBC_MBC_IABS2 ((volatile u32*)(DANUBE_MBC+ 0x0050))
340 #define DANUBE_MBC_MBC_IABS2_IABS
342 /***Mailbox CPU Input Absolute Pointer of Buffer 3***/
343 #define DANUBE_MBC_MBC_IABS3 ((volatile u32*)(DANUBE_MBC+ 0x0070))
344 #define DANUBE_MBC_MBC_IABS3_IABS
346 /***Mailbox CPU Input Temporary Pointer of Buffer 0***/
347 #define DANUBE_MBC_MBC_ITMP0 ((volatile u32*)(DANUBE_MBC+ 0x0014))
348 #define DANUBE_MBC_MBC_ITMP0_ITMP
350 /***Mailbox CPU Input Temporary Pointer of Buffer 1***/
351 #define DANUBE_MBC_MBC_ITMP1 ((volatile u32*)(DANUBE_MBC+ 0x0034))
352 #define DANUBE_MBC_MBC_ITMP1_ITMP
354 /***Mailbox CPU Input Temporary Pointer of Buffer 2***/
355 #define DANUBE_MBC_MBC_ITMP2 ((volatile u32*)(DANUBE_MBC+ 0x0054))
356 #define DANUBE_MBC_MBC_ITMP2_ITMP
358 /***Mailbox CPU Input Temporary Pointer of Buffer 3***/
359 #define DANUBE_MBC_MBC_ITMP3 ((volatile u32*)(DANUBE_MBC+ 0x0074))
360 #define DANUBE_MBC_MBC_ITMP3_ITMP
362 /***Mailbox CPU Output Absolute Pointer of Buffer 0***/
363 #define DANUBE_MBC_MBC_OABS0 ((volatile u32*)(DANUBE_MBC+ 0x0018))
364 #define DANUBE_MBC_MBC_OABS0_OABS
366 /***Mailbox CPU Output Absolute Pointer of Buffer 1***/
367 #define DANUBE_MBC_MBC_OABS1 ((volatile u32*)(DANUBE_MBC+ 0x0038))
368 #define DANUBE_MBC_MBC_OABS1_OABS
370 /***Mailbox CPU Output Absolute Pointer of Buffer 2***/
371 #define DANUBE_MBC_MBC_OABS2 ((volatile u32*)(DANUBE_MBC+ 0x0058))
372 #define DANUBE_MBC_MBC_OABS2_OABS
374 /***Mailbox CPU Output Absolute Pointer of Buffer 3***/
375 #define DANUBE_MBC_MBC_OABS3 ((volatile u32*)(DANUBE_MBC+ 0x0078))
376 #define DANUBE_MBC_MBC_OABS3_OABS
378 /***Mailbox CPU Output Temporary Pointer of Buffer 0***/
379 #define DANUBE_MBC_MBC_OTMP0 ((volatile u32*)(DANUBE_MBC+ 0x001C))
380 #define DANUBE_MBC_MBC_OTMP0_OTMP
382 /***Mailbox CPU Output Temporary Pointer of Buffer 1***/
383 #define DANUBE_MBC_MBC_OTMP1 ((volatile u32*)(DANUBE_MBC+ 0x003C))
384 #define DANUBE_MBC_MBC_OTMP1_OTMP
386 /***Mailbox CPU Output Temporary Pointer of Buffer 2***/
387 #define DANUBE_MBC_MBC_OTMP2 ((volatile u32*)(DANUBE_MBC+ 0x005C))
388 #define DANUBE_MBC_MBC_OTMP2_OTMP
390 /***Mailbox CPU Output Temporary Pointer of Buffer 3***/
391 #define DANUBE_MBC_MBC_OTMP3 ((volatile u32*)(DANUBE_MBC+ 0x007C))
392 #define DANUBE_MBC_MBC_OTMP3_OTMP
394 /***DSP Control Register***/
395 #define DANUBE_MBC_DCTRL ((volatile u32*)(DANUBE_MBC+ 0x00A0))
396 #define DANUBE_MBC_DCTRL_BA (1 << 0)
397 #define DANUBE_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1)
398 #define DANUBE_MBC_DCTRL_IDL (1 << 4)
399 #define DANUBE_MBC_DCTRL_RES (1 << 15)
401 /***DSP Status Register***/
402 #define DANUBE_MBC_DSTA ((volatile u32*)(DANUBE_MBC+ 0x00A4))
403 #define DANUBE_MBC_DSTA_IDLE (1 << 0)
404 #define DANUBE_MBC_DSTA_PD (1 << 1)
406 /***DSP Test 1 Register***/
407 #define DANUBE_MBC_DTST1 ((volatile u32*)(DANUBE_MBC+ 0x00A8))
408 #define DANUBE_MBC_DTST1_ABORT (1 << 0)
409 #define DANUBE_MBC_DTST1_HWF32 (1 << 1)
410 #define DANUBE_MBC_DTST1_HWF4M (1 << 2)
411 #define DANUBE_MBC_DTST1_HWFOP (1 << 3)
414 /***********************************************************************/
415 /* Module : SSC1 register address and bits */
416 /***********************************************************************/
417 #define DANUBE_SSC1 (KSEG1+0x1e100800)
418 /***********************************************************************/
419 /***SSC Clock Control Register***/
420 #define DANUBE_SSC_CLC (0x0000)
421 #define DANUBE_SSC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8)
422 #define DANUBE_SSC_CLC_DISS (1 << 1)
423 #define DANUBE_SSC_CLC_DISR (1 << 0)
424 /***SSC Port Input Selection Register***/
425 #define DANUBE_SSC_PISEL (0x0004)
426 /***SSC Identification Register***/
427 #define DANUBE_SSC_ID (0x0008)
428 /***Control Register (Programming Mode)***/
429 #define DANUBE_SSC_CON (0x0010)
430 #define DANUBE_SSC_CON_RUEN (1 << 12)
431 #define DANUBE_SSC_CON_TUEN (1 << 11)
432 #define DANUBE_SSC_CON_AEN (1 << 10)
433 #define DANUBE_SSC_CON_REN (1 << 9)
434 #define DANUBE_SSC_CON_TEN (1 << 8)
435 #define DANUBE_SSC_CON_LB (1 << 7)
436 #define DANUBE_SSC_CON_PO (1 << 6)
437 #define DANUBE_SSC_CON_PH (1 << 5)
438 #define DANUBE_SSC_CON_HB (1 << 4)
439 #define DANUBE_SSC_CON_BM(value) (((( 1 << 5) - 1) & (value)) << 16)
440 #define DANUBE_SSC_CON_RX_OFF (1 << 1)
441 #define DANUBE_SSC_CON_TX_OFF (1 << 0)
442 /***SCC Status Register***/
443 #define DANUBE_SSC_STATE (0x0014)
444 #define DANUBE_SSC_STATE_EN (1 << 0)
445 #define DANUBE_SSC_STATE_MS (1 << 1)
446 #define DANUBE_SSC_STATE_BSY (1 << 13)
447 #define DANUBE_SSC_STATE_RUE (1 << 12)
448 #define DANUBE_SSC_STATE_TUE (1 << 11)
449 #define DANUBE_SSC_STATE_AE (1 << 10)
450 #define DANUBE_SSC_STATE_RE (1 << 9)
451 #define DANUBE_SSC_STATE_TE (1 << 8)
452 #define DANUBE_SSC_STATE_BC(value) (((( 1 << 5) - 1) & (value)) << 16)
453 /***SSC Write Hardware Modified Control Register***/
454 #define DANUBE_SSC_WHBSTATE ( 0x0018)
455 #define DANUBE_SSC_WHBSTATE_SETBE (1 << 15)
456 #define DANUBE_SSC_WHBSTATE_SETPE (1 << 14)
457 #define DANUBE_SSC_WHBSTATE_SETRE (1 << 13)
458 #define DANUBE_SSC_WHBSTATE_SETTE (1 << 12)
459 #define DANUBE_SSC_WHBSTATE_CLRBE (1 << 11)
460 #define DANUBE_SSC_WHBSTATE_CLRPE (1 << 10)
461 #define DANUBE_SSC_WHBSTATE_CLRRE (1 << 9)
462 #define DANUBE_SSC_WHBSTATE_CLRTE (1 << 8)
463 /***SSC Transmitter Buffer Register***/
464 #define DANUBE_SSC_TB (0x0020)
465 #define DANUBE_SSC_TB_TB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
466 /***SSC Receiver Buffer Register***/
467 #define DANUBE_SSC_RB (0x0024)
468 #define DANUBE_SSC_RB_RB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
469 /***SSC Receive FIFO Control Register***/
470 #define DANUBE_SSC_RXFCON (0x0030)
471 #define DANUBE_SSC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
472 #define DANUBE_SSC_RXFCON_RXTMEN (1 << 2)
473 #define DANUBE_SSC_RXFCON_RXFLU (1 << 1)
474 #define DANUBE_SSC_RXFCON_RXFEN (1 << 0)
475 /***SSC Transmit FIFO Control Register***/
476 #define DANUBE_SSC_TXFCON ( 0x0034)
477 #define DANUBE_SSC_TXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
478 #define DANUBE_SSC_TXFCON_TXTMEN (1 << 2)
479 #define DANUBE_SSC_TXFCON_TXFLU (1 << 1)
480 #define DANUBE_SSC_TXFCON_TXFEN (1 << 0)
481 /***SSC FIFO Status Register***/
482 #define DANUBE_SSC_FSTAT (0x0038)
483 #define DANUBE_SSC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8)
484 #define DANUBE_SSC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0)
485 /***SSC Baudrate Timer Reload Register***/
486 #define DANUBE_SSC_BR (0x0040)
487 #define DANUBE_SSC_BR_BR_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
488 #define DANUBE_SSC_BRSTAT (0x0044)
489 #define DANUBE_SSC_SFCON (0x0060)
490 #define DANUBE_SSC_SFSTAT (0x0064)
491 #define DANUBE_SSC_GPOCON (0x0070)
492 #define DANUBE_SSC_GPOSTAT (0x0074)
493 #define DANUBE_SSC_WHBGPOSTAT (0x0078)
494 #define DANUBE_SSC_RXREQ (0x0080)
495 #define DANUBE_SSC_RXCNT (0x0084)
496 /*DMA Registers in Bus Clock Domain*/
497 #define DANUBE_SSC_DMA_CON (0x00EC)
498 /*interrupt Node Registers in Bus Clock Domain*/
499 #define DANUBE_SSC_IRNEN (0x00F4)
500 #define DANUBE_SSC_IRNCR (0x00F8)
501 #define DANUBE_SSC_IRNICR (0x00FC)
502 #define DANUBE_SSC_IRN_FIR 0x8
503 #define DANUBE_SSC_IRN_EIR 0x4
504 #define DANUBE_SSC_IRN_RIR 0x2
505 #define DANUBE_SSC_IRN_TIR 0x1
508 #define DANUBE_SSC1_CLC ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CLC))
509 #define DANUBE_SSC1_ID ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_ID))
510 #define DANUBE_SSC1_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CON))
511 #define DANUBE_SSC1_STATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_STATE))
512 #define DANUBE_SSC1_WHBSTATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBSTATE))
513 #define DANUBE_SSC1_TB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TB))
514 #define DANUBE_SSC1_RB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RB))
515 #define DANUBE_SSC1_FSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_FSTAT))
516 #define DANUBE_SSC1_PISEL ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_PISEL))
517 #define DANUBE_SSC1_RXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXFCON))
518 #define DANUBE_SSC1_TXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TXFCON))
519 #define DANUBE_SSC1_BR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BR))
520 #define DANUBE_SSC1_BRSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BRSTAT))
521 #define DANUBE_SSC1_SFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFCON))
522 #define DANUBE_SSC1_SFSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFSTAT))
523 #define DANUBE_SSC1_GPOCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOCON))
524 #define DANUBE_SSC1_GPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOSTAT))
525 #define DANUBE_SSC1_WHBGPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBGPOSTAT))
526 #define DANUBE_SSC1_RXREQ ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXREQ))
527 #define DANUBE_SSC1_RXCNT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXCNT))
528 #define DANUBE_SSC1_DMA_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_DMA_CON))
529 #define DANUBE_SSC1_IRNEN ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNEN))
530 #define DANUBE_SSC1_IRNICR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNICR))
531 #define DANUBE_SSC1_IRNCR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNCR))
533 /***********************************************************************/
534 /* Module : GPIO register address and bits */
535 /***********************************************************************/
536 #define DANUBE_GPIO (0xBE100B00)
537 /***Port 0 Data Output Register (0010H)***/
538 #define DANUBE_GPIO_P0_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0010))
539 /***Port 1 Data Output Register (0040H)***/
540 #define DANUBE_GPIO_P1_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0040))
541 /***Port 0 Data Input Register (0014H)***/
542 #define DANUBE_GPIO_P0_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0014))
543 /***Port 1 Data Input Register (0044H)***/
544 #define DANUBE_GPIO_P1_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0044))
545 /***Port 0 Direction Register (0018H)***/
546 #define DANUBE_GPIO_P0_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0018))
547 /***Port 1 Direction Register (0048H)***/
548 #define DANUBE_GPIO_P1_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0048))
549 /***Port 0 Alternate Function Select Register 0 (001C H) ***/
550 #define DANUBE_GPIO_P0_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x001C))
551 /***Port 1 Alternate Function Select Register 0 (004C H) ***/
552 #define DANUBE_GPIO_P1_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x004C))
553 /***Port 0 Alternate Function Select Register 1 (0020 H) ***/
554 #define DANUBE_GPIO_P0_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0020))
555 /***Port 1 Alternate Function Select Register 0 (0050 H) ***/
556 #define DANUBE_GPIO_P1_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0050))
557 /***Port 0 Open Drain Control Register (0024H)***/
558 #define DANUBE_GPIO_P0_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0024))
559 /***Port 1 Open Drain Control Register (0054H)***/
560 #define DANUBE_GPIO_P1_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0054))
561 /***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/
562 #define DANUBE_GPIO_P0_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0028))
563 /***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/
564 #define DANUBE_GPIO_P1_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0058))
565 /***Port 0 Pull Up/Pull Down Select Register (002C H)***/
566 #define DANUBE_GPIO_P0_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x002C))
567 /***Port 1 Pull Up/Pull Down Select Register (005C H)***/
568 #define DANUBE_GPIO_P1_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x005C))
569 /***Port 0 Pull Up Device Enable Register (0030 H)***/
570 #define DANUBE_GPIO_P0_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0030))
571 /***Port 1 Pull Up Device Enable Register (0060 H)***/
572 #define DANUBE_GPIO_P1_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0060))
573 /***********************************************************************/
574 /* Module : CGU register address and bits */
575 /***********************************************************************/
577 #define DANUBE_CGU (0xBF103000)
578 /***********************************************************************/
580 /***CGU Clock PLL0 ***/
581 #define DANUBE_CGU_PLL0_CFG ((volatile u32*)(DANUBE_CGU+ 0x0004))
582 /***CGU Clock PLL1 ***/
583 #define DANUBE_CGU_PLL1_CFG ((volatile u32*)(DANUBE_CGU+ 0x0008))
584 /***CGU Clock SYS Mux Register***/
585 #define DANUBE_CGU_SYS ((volatile u32*)(DANUBE_CGU+ 0x0010))
586 /***CGU Interface Clock Control Register***/
587 #define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018))
588 /***CGU PCI Clock Control Register**/
589 #define DANUBE_CGU_PCICR ((volatile u32*)(DANUBE_CGU+ 0x0034))
592 /***********************************************************************/
593 /* Module : PCI register address and bits */
594 /***********************************************************************/
595 #define PCI_CR_PR_OFFSET 0xBE105400
596 #define PCI_CR_CLK_CTRL_REG (PCI_CR_PR_OFFSET + 0x0000)
598 #define PCI_CR_PCI_ID_REG (PCI_CR_PR_OFFSET + 0x0004)
599 #define PCI_CR_SFT_RST_REG (PCI_CR_PR_OFFSET + 0x0010)
600 #define PCI_CR_PCI_FPI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0014)
601 #define PCI_CR_FCI_PCI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0018)
602 #define PCI_CR_FPI_ERR_TAG_REG (PCI_CR_PR_OFFSET + 0x001C)
603 #define PCI_CR_PCI_IRR_REG (PCI_CR_PR_OFFSET + 0x0020)
604 #define PCI_CR_PCI_IRA_REG (PCI_CR_PR_OFFSET + 0x0024)
605 #define PCI_CR_PCI_IRM_REG (PCI_CR_PR_OFFSET + 0x0028)
606 #define PCI_CR_PCI_EOI_REG (PCI_CR_PR_OFFSET + 0x002C)
607 #define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
608 #define PCI_CR_DV_ID_REG (PCI_CR_PR_OFFSET + 0x0034)
609 #define PCI_CR_SUBSYS_ID_REG (PCI_CR_PR_OFFSET + 0x0038)
610 #define PCI_CR_PCI_PM_REG (PCI_CR_PR_OFFSET + 0x003C)
611 #define PCI_CR_CLASS_CODE1_REG (PCI_CR_PR_OFFSET + 0x0040)
612 #define PCI_CR_BAR11MASK_REG (PCI_CR_PR_OFFSET + 0x0044)
613 #define PCI_CR_BAR12MASK_REG (PCI_CR_PR_OFFSET + 0x0048)
614 #define PCI_CR_BAR13MASK_REG (PCI_CR_PR_OFFSET + 0x004C)
615 #define PCI_CR_BAR14MASK_REG (PCI_CR_PR_OFFSET + 0x0050)
616 #define PCI_CR_BAR15MASK_REG (PCI_CR_PR_OFFSET + 0x0054)
617 #define PCI_CR_BAR16MASK_REG (PCI_CR_PR_OFFSET + 0x0058)
618 #define PCI_CR_CIS_PT1_REG (PCI_CR_PR_OFFSET + 0x005C)
619 #define PCI_CR_SUBSYS_ID1_REG (PCI_CR_PR_OFFSET + 0x0060)
620 #define PCI_CR_PCI_ADDR_MAP11_REG (PCI_CR_PR_OFFSET + 0x0064)
621 #define PCI_CR_PCI_ADDR_MAP12_REG (PCI_CR_PR_OFFSET + 0x0068)
622 #define PCI_CR_PCI_ADDR_MAP13_REG (PCI_CR_PR_OFFSET + 0x006C)
623 #define PCI_CR_PCI_ADDR_MAP14_REG (PCI_CR_PR_OFFSET + 0x0070)
624 #define PCI_CR_PCI_ADDR_MAP15_REG (PCI_CR_PR_OFFSET + 0x0074)
625 #define PCI_CR_PCI_ADDR_MAP16_REG (PCI_CR_PR_OFFSET + 0x0078)
626 #define PCI_CR_FPI_SEG_EN_REG (PCI_CR_PR_OFFSET + 0x007C)
627 #define PCI_CR_PC_ARB_REG (PCI_CR_PR_OFFSET + 0x0080)
628 #define PCI_CR_BAR21MASK_REG (PCI_CR_PR_OFFSET + 0x0084)
629 #define PCI_CR_BAR22MASK_REG (PCI_CR_PR_OFFSET + 0x0088)
630 #define PCI_CR_BAR23MASK_REG (PCI_CR_PR_OFFSET + 0x008C)
631 #define PCI_CR_BAR24MASK_REG (PCI_CR_PR_OFFSET + 0x0090)
632 #define PCI_CR_BAR25MASK_REG (PCI_CR_PR_OFFSET + 0x0094)
633 #define PCI_CR_BAR26MASK_REG (PCI_CR_PR_OFFSET + 0x0098)
634 #define PCI_CR_CIS_PT2_REG (PCI_CR_PR_OFFSET + 0x009C)
635 #define PCI_CR_SUBSYS_ID2_REG (PCI_CR_PR_OFFSET + 0x00A0)
636 #define PCI_CR_PCI_ADDR_MAP21_REG (PCI_CR_PR_OFFSET + 0x00A4)
637 #define PCI_CR_PCI_ADDR_MAP22_REG (PCI_CR_PR_OFFSET + 0x00A8)
638 #define PCI_CR_PCI_ADDR_MAP23_REG (PCI_CR_PR_OFFSET + 0x00AC)
641 /***********************************************************************/
642 /* Module : MCD register address and bits */
643 /***********************************************************************/
644 #define DANUBE_MCD (KSEG1+0x1F106000)
646 /***Manufacturer Identification Register***/
647 #define DANUBE_MCD_MANID ((volatile u32*)(DANUBE_MCD+ 0x0024))
648 #define DANUBE_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5)
650 /***Chip Identification Register***/
651 #define DANUBE_MCD_CHIPID ((volatile u32*)(DANUBE_MCD+ 0x0028))
652 #define DANUBE_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
653 #define DANUBE_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
654 #define DANUBE_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1))
655 #define DANUBE_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
656 #define DANUBE_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1))
657 #define DANUBE_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1)
659 #define DANUBE_CHIPID_STANDARD 0x00EB
660 #define DANUBE_CHIPID_YANGTSE 0x00ED
662 /***Redesign Tracing Identification Register***/
663 #define DANUBE_MCD_RTID ((volatile u32*)(DANUBE_MCD+ 0x002C))
664 #define DANUBE_MCD_RTID_LC (1 << 15)
665 #define DANUBE_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0)
668 /***********************************************************************/
669 /* Module : EBU register address and bits */
670 /***********************************************************************/
672 #define DANUBE_EBU (0xBE105300)
673 #define EBU_ADDR_SEL_0 (volatile u32*)(DANUBE_EBU + 0x20)
674 #define EBU_ADDR_SEL_1 (volatile u32*)(DANUBE_EBU + 0x24)
675 #define EBU_CON_0 (volatile u32*)(DANUBE_EBU + 0x60)
676 #define EBU_CON_1 (volatile u32*)(DANUBE_EBU + 0x64)
677 #define EBU_NAND_CON (volatile u32*)(DANUBE_EBU + 0xB0)
678 #define EBU_NAND_WAIT (volatile u32*)(DANUBE_EBU + 0xB4)
679 #define EBU_NAND_ECC0 (volatile u32*)(DANUBE_EBU + 0xB8)
680 #define EBU_NAND_ECC_AC (volatile u32*)(DANUBE_EBU + 0xBC)
682 /***********************************************************************/
685 /***EBU Clock Control Register***/
686 #define DANUBE_EBU_CLC ((volatile u32*)(DANUBE_EBU+ 0x0000))
687 #define DANUBE_EBU_CLC_DISS (1 << 1)
688 #define DANUBE_EBU_CLC_DISR (1 << 0)
690 /***EBU Global Control Register***/
691 #define DANUBE_EBU_CON ((volatile u32*)(DANUBE_EBU+ 0x0010))
692 #define DANUBE_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20)
693 #define DANUBE_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16)
694 #define DANUBE_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8)
695 #define DANUBE_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6)
696 #define DANUBE_EBU_CON_ARBSYNC (1 << 5)
697 #define DANUBE_EBU_CON_1 (1 << 3)
699 /***EBU Address Select Register 0***/
700 #define DANUBE_EBU_ADDSEL0 ((volatile u32*)(DANUBE_EBU+ 0x0020))
701 #define DANUBE_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
702 #define DANUBE_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
703 #define DANUBE_EBU_ADDSEL0_MIRRORE (1 << 1)
704 #define DANUBE_EBU_ADDSEL0_REGEN (1 << 0)
706 /***EBU Address Select Register 1***/
707 #define DANUBE_EBU_ADDSEL1 ((volatile u32*)(DANUBE_EBU+ 0x0024))
708 #define DANUBE_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
709 #define DANUBE_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
710 #define DANUBE_EBU_ADDSEL1_MIRRORE (1 << 1)
711 #define DANUBE_EBU_ADDSEL1_REGEN (1 << 0)
713 /***EBU Address Select Register 2***/
714 #define DANUBE_EBU_ADDSEL2 ((volatile u32*)(DANUBE_EBU+ 0x0028))
715 #define DANUBE_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
716 #define DANUBE_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
717 #define DANUBE_EBU_ADDSEL2_MIRRORE (1 << 1)
718 #define DANUBE_EBU_ADDSEL2_REGEN (1 << 0)
720 /***EBU Address Select Register 3***/
721 #define DANUBE_EBU_ADDSEL3 ((volatile u32*)(DANUBE_EBU+ 0x0028))
722 #define DANUBE_EBU_ADDSEL3_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
723 #define DANUBE_EBU_ADDSEL3_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
724 #define DANUBE_EBU_ADDSEL3_MIRRORE (1 << 1)
725 #define DANUBE_EBU_ADDSEL3_REGEN (1 << 0)
727 /***EBU Bus Configuration Register 0***/
728 #define DANUBE_EBU_BUSCON0 ((volatile u32*)(DANUBE_EBU+ 0x0060))
729 #define DANUBE_EBU_BUSCON0_WRDIS (1 << 31)
730 #define DANUBE_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
731 #define DANUBE_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
732 #define DANUBE_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
733 #define DANUBE_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
734 #define DANUBE_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
735 #define DANUBE_EBU_BUSCON0_WAITINV (1 << 19)
736 #define DANUBE_EBU_BUSCON0_SETUP (1 << 18)
737 #define DANUBE_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
738 #define DANUBE_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
739 #define DANUBE_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
740 #define DANUBE_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
741 #define DANUBE_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
742 #define DANUBE_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
744 /***EBU Bus Configuration Register 1***/
745 #define DANUBE_EBU_BUSCON1 ((volatile u32*)(DANUBE_EBU+ 0x0064))
746 #define DANUBE_EBU_BUSCON1_WRDIS (1 << 31)
747 #define DANUBE_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
748 #define DANUBE_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
749 #define DANUBE_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
750 #define DANUBE_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
751 #define DANUBE_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
752 #define DANUBE_EBU_BUSCON1_WAITINV (1 << 19)
753 #define DANUBE_EBU_BUSCON1_SETUP (1 << 18)
754 #define DANUBE_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
755 #define DANUBE_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
756 #define DANUBE_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
757 #define DANUBE_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
758 #define DANUBE_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
759 #define DANUBE_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
761 /***EBU Bus Configuration Register 2***/
762 #define DANUBE_EBU_BUSCON2 ((volatile u32*)(DANUBE_EBU+ 0x0068))
763 #define DANUBE_EBU_BUSCON2_WRDIS (1 << 31)
764 #define DANUBE_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
765 #define DANUBE_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
766 #define DANUBE_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
767 #define DANUBE_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
768 #define DANUBE_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
769 #define DANUBE_EBU_BUSCON2_WAITINV (1 << 19)
770 #define DANUBE_EBU_BUSCON2_SETUP (1 << 18)
771 #define DANUBE_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
772 #define DANUBE_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
773 #define DANUBE_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
774 #define DANUBE_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
775 #define DANUBE_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
776 #define DANUBE_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
778 /***********************************************************************/
779 /* Module : SDRAM register address and bits */
780 /***********************************************************************/
782 #define DANUBE_SDRAM (0xBF800000)
783 /***********************************************************************/
786 /***MC Access Error Cause Register***/
787 #define DANUBE_SDRAM_MC_ERRCAUSE ((volatile u32*)(DANUBE_SDRAM+ 0x0100))
788 #define DANUBE_SDRAM_MC_ERRCAUSE_ERR (1 << 31)
789 #define DANUBE_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
790 #define DANUBE_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
791 #define DANUBE_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN)
793 /***MC Access Error Address Register***/
794 #define DANUBE_SDRAM_MC_ERRADDR ((volatile u32*)(DANUBE_SDRAM+ 0x0108))
795 #define DANUBE_SDRAM_MC_ERRADDR_ADDR
797 /***MC I/O General Purpose Register***/
798 #define DANUBE_SDRAM_MC_IOGP ((volatile u32*)(DANUBE_SDRAM+ 0x0800))
799 #define DANUBE_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28)
800 #define DANUBE_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24)
801 #define DANUBE_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20)
802 #define DANUBE_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16)
803 #define DANUBE_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12)
804 #define DANUBE_SDRAM_MC_IOGP_CPS (1 << 11)
805 #define DANUBE_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8)
806 #define DANUBE_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4)
807 #define DANUBE_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0)
809 /***MC Self Refresh Register***/
810 #define DANUBE_SDRAM_MC_SELFRFSH ((volatile u32*)(DANUBE_SDRAM+ 0x0A00))
811 #define DANUBE_SDRAM_MC_SELFRFSH_PWDS (1 << 1)
812 #define DANUBE_SDRAM_MC_SELFRFSH_PWD (1 << 0)
813 #define DANUBE_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2)
815 /***MC Enable Register***/
816 #define DANUBE_SDRAM_MC_CTRLENA ((volatile u32*)(DANUBE_SDRAM+ 0x1000))
817 #define DANUBE_SDRAM_MC_CTRLENA_ENA (1 << 0)
818 #define DANUBE_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1)
820 /***MC Mode Register Setup Code***/
821 #define DANUBE_SDRAM_MC_MRSCODE ((volatile u32*)(DANUBE_SDRAM+ 0x1008))
822 #define DANUBE_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7)
823 #define DANUBE_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4)
824 #define DANUBE_SDRAM_MC_MRSCODE_WT (1 << 3)
825 #define DANUBE_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0)
827 /***MC Configuration Data-word Width Register***/
828 #define DANUBE_SDRAM_MC_CFGDW ((volatile u32*)(DANUBE_SDRAM+ 0x1010))
829 #define DANUBE_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0)
830 #define DANUBE_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4)
832 /***MC Configuration Physical Bank 0 Register***/
833 #define DANUBE_SDRAM_MC_CFGPB0 ((volatile u32*)(DANUBE_SDRAM+ 0x1018))
834 #define DANUBE_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12)
835 #define DANUBE_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8)
836 #define DANUBE_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4)
837 #define DANUBE_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0)
838 #define DANUBE_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16)
840 /***MC Latency Register***/
841 #define DANUBE_SDRAM_MC_LATENCY ((volatile u32*)(DANUBE_SDRAM+ 0x1038))
842 #define DANUBE_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16)
843 #define DANUBE_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12)
844 #define DANUBE_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8)
845 #define DANUBE_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4)
846 #define DANUBE_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0)
847 #define DANUBE_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20)
849 /***MC Refresh Cycle Time Register***/
850 #define DANUBE_SDRAM_MC_TREFRESH ((volatile u32*)(DANUBE_SDRAM+ 0x1040))
851 #define DANUBE_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0)
852 #define DANUBE_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13)
855 /***********************************************************************/
856 /* Module : GPTU register address and bits */
857 /***********************************************************************/
859 #define DANUBE_GPTU (0xB8000300)
860 /***********************************************************************/
863 /***GPT Clock Control Register***/
864 #define DANUBE_GPTU_GPT_CLC ((volatile u32*)(DANUBE_GPTU+ 0x0000))
865 #define DANUBE_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
866 #define DANUBE_GPTU_GPT_CLC_DISS (1 << 1)
867 #define DANUBE_GPTU_GPT_CLC_DISR (1 << 0)
869 /***GPT Timer 3 Control Register***/
870 #define DANUBE_GPTU_GPT_T3CON ((volatile u32*)(DANUBE_GPTU+ 0x0014))
871 #define DANUBE_GPTU_GPT_T3CON_T3RDIR (1 << 15)
872 #define DANUBE_GPTU_GPT_T3CON_T3CHDIR (1 << 14)
873 #define DANUBE_GPTU_GPT_T3CON_T3EDGE (1 << 13)
874 #define DANUBE_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11)
875 #define DANUBE_GPTU_GPT_T3CON_T3OTL (1 << 10)
876 #define DANUBE_GPTU_GPT_T3CON_T3UD (1 << 7)
877 #define DANUBE_GPTU_GPT_T3CON_T3R (1 << 6)
878 #define DANUBE_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3)
879 #define DANUBE_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0)
881 /***GPT Write Hardware Modified Timer 3 Control Register
882 If set and clear bit are written concurrently with 1, the associated bit is not changed.***/
883 #define DANUBE_GPTU_GPT_WHBT3CON ((volatile u32*)(DANUBE_GPTU+ 0x004C))
884 #define DANUBE_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15)
885 #define DANUBE_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14)
886 #define DANUBE_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13)
887 #define DANUBE_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12)
888 #define DANUBE_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11)
889 #define DANUBE_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10)
891 /***GPT Timer 2 Control Register***/
892 #define DANUBE_GPTU_GPT_T2CON ((volatile u32*)(DANUBE_GPTU+ 0x0010))
893 #define DANUBE_GPTU_GPT_T2CON_TxRDIR (1 << 15)
894 #define DANUBE_GPTU_GPT_T2CON_TxCHDIR (1 << 14)
895 #define DANUBE_GPTU_GPT_T2CON_TxEDGE (1 << 13)
896 #define DANUBE_GPTU_GPT_T2CON_TxIRDIS (1 << 12)
897 #define DANUBE_GPTU_GPT_T2CON_TxRC (1 << 9)
898 #define DANUBE_GPTU_GPT_T2CON_TxUD (1 << 7)
899 #define DANUBE_GPTU_GPT_T2CON_TxR (1 << 6)
900 #define DANUBE_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3)
901 #define DANUBE_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0)
903 /***GPT Timer 4 Control Register***/
904 #define DANUBE_GPTU_GPT_T4CON ((volatile u32*)(DANUBE_GPTU+ 0x0018))
905 #define DANUBE_GPTU_GPT_T4CON_TxRDIR (1 << 15)
906 #define DANUBE_GPTU_GPT_T4CON_TxCHDIR (1 << 14)
907 #define DANUBE_GPTU_GPT_T4CON_TxEDGE (1 << 13)
908 #define DANUBE_GPTU_GPT_T4CON_TxIRDIS (1 << 12)
909 #define DANUBE_GPTU_GPT_T4CON_TxRC (1 << 9)
910 #define DANUBE_GPTU_GPT_T4CON_TxUD (1 << 7)
911 #define DANUBE_GPTU_GPT_T4CON_TxR (1 << 6)
912 #define DANUBE_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3)
913 #define DANUBE_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0)
915 /***GPT Write HW Modified Timer 2 Control Register If set
916 and clear bit are written concurrently with 1, the associated bit is not changed.***/
917 #define DANUBE_GPTU_GPT_WHBT2CON ((volatile u32*)(DANUBE_GPTU+ 0x0048))
918 #define DANUBE_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15)
919 #define DANUBE_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14)
920 #define DANUBE_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13)
921 #define DANUBE_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12)
923 /***GPT Write HW Modified Timer 4 Control Register If set
924 and clear bit are written concurrently with 1, the associated bit is not changed.***/
925 #define DANUBE_GPTU_GPT_WHBT4CON ((volatile u32*)(DANUBE_GPTU+ 0x0050))
926 #define DANUBE_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15)
927 #define DANUBE_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14)
928 #define DANUBE_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13)
929 #define DANUBE_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12)
931 /***GPT Capture Reload Register***/
932 #define DANUBE_GPTU_GPT_CAPREL ((volatile u32*)(DANUBE_GPTU+ 0x0030))
933 #define DANUBE_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0)
935 /***GPT Timer 2 Register***/
936 #define DANUBE_GPTU_GPT_T2 ((volatile u32*)(DANUBE_GPTU+ 0x0034))
937 #define DANUBE_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
939 /***GPT Timer 3 Register***/
940 #define DANUBE_GPTU_GPT_T3 ((volatile u32*)(DANUBE_GPTU+ 0x0038))
941 #define DANUBE_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
943 /***GPT Timer 4 Register***/
944 #define DANUBE_GPTU_GPT_T4 ((volatile u32*)(DANUBE_GPTU+ 0x003C))
945 #define DANUBE_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
947 /***GPT Timer 5 Register***/
948 #define DANUBE_GPTU_GPT_T5 ((volatile u32*)(DANUBE_GPTU+ 0x0040))
949 #define DANUBE_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
951 /***GPT Timer 6 Register***/
952 #define DANUBE_GPTU_GPT_T6 ((volatile u32*)(DANUBE_GPTU+ 0x0044))
953 #define DANUBE_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
955 /***GPT Timer 6 Control Register***/
956 #define DANUBE_GPTU_GPT_T6CON ((volatile u32*)(DANUBE_GPTU+ 0x0020))
957 #define DANUBE_GPTU_GPT_T6CON_T6SR (1 << 15)
958 #define DANUBE_GPTU_GPT_T6CON_T6CLR (1 << 14)
959 #define DANUBE_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11)
960 #define DANUBE_GPTU_GPT_T6CON_T6OTL (1 << 10)
961 #define DANUBE_GPTU_GPT_T6CON_T6UD (1 << 7)
962 #define DANUBE_GPTU_GPT_T6CON_T6R (1 << 6)
963 #define DANUBE_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3)
964 #define DANUBE_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0)
966 /***GPT Write HW Modified Timer 6 Control Register If set
967 and clear bit are written concurrently with 1, the associated bit is not changed.***/
968 #define DANUBE_GPTU_GPT_WHBT6CON ((volatile u32*)(DANUBE_GPTU+ 0x0054))
969 #define DANUBE_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11)
970 #define DANUBE_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10)
972 /***GPT Timer 5 Control Register***/
973 #define DANUBE_GPTU_GPT_T5CON ((volatile u32*)(DANUBE_GPTU+ 0x001C))
974 #define DANUBE_GPTU_GPT_T5CON_T5SC (1 << 15)
975 #define DANUBE_GPTU_GPT_T5CON_T5CLR (1 << 14)
976 #define DANUBE_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12)
977 #define DANUBE_GPTU_GPT_T5CON_T5CC (1 << 11)
978 #define DANUBE_GPTU_GPT_T5CON_CT3 (1 << 10)
979 #define DANUBE_GPTU_GPT_T5CON_T5RC (1 << 9)
980 #define DANUBE_GPTU_GPT_T5CON_T5UDE (1 << 8)
981 #define DANUBE_GPTU_GPT_T5CON_T5UD (1 << 7)
982 #define DANUBE_GPTU_GPT_T5CON_T5R (1 << 6)
983 #define DANUBE_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3)
984 #define DANUBE_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0)
987 /***********************************************************************/
988 /* Module : IOM register address and bits */
989 /***********************************************************************/
991 #define DANUBE_IOM (0xBF105000)
992 /***********************************************************************/
996 #define DANUBE_IOM_RFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000))
997 #define DANUBE_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0)
999 /***Transmit FIFO***/
1000 #define DANUBE_IOM_XFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000))
1001 #define DANUBE_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0)
1003 /***Interrupt Status Register HDLC***/
1004 #define DANUBE_IOM_ISTAH ((volatile u32*)(DANUBE_IOM+ 0x0080))
1005 #define DANUBE_IOM_ISTAH_RME (1 << 7)
1006 #define DANUBE_IOM_ISTAH_RPF (1 << 6)
1007 #define DANUBE_IOM_ISTAH_RFO (1 << 5)
1008 #define DANUBE_IOM_ISTAH_XPR (1 << 4)
1009 #define DANUBE_IOM_ISTAH_XMR (1 << 3)
1010 #define DANUBE_IOM_ISTAH_XDU (1 << 2)
1012 /***Interrupt Mask Register HDLC***/
1013 #define DANUBE_IOM_MASKH ((volatile u32*)(DANUBE_IOM+ 0x0080))
1014 #define DANUBE_IOM_MASKH_RME (1 << 7)
1015 #define DANUBE_IOM_MASKH_RPF (1 << 6)
1016 #define DANUBE_IOM_MASKH_RFO (1 << 5)
1017 #define DANUBE_IOM_MASKH_XPR (1 << 4)
1018 #define DANUBE_IOM_MASKH_XMR (1 << 3)
1019 #define DANUBE_IOM_MASKH_XDU (1 << 2)
1021 /***Status Register***/
1022 #define DANUBE_IOM_STAR ((volatile u32*)(DANUBE_IOM+ 0x0084))
1023 #define DANUBE_IOM_STAR_XDOV (1 << 7)
1024 #define DANUBE_IOM_STAR_XFW (1 << 6)
1025 #define DANUBE_IOM_STAR_RACI (1 << 3)
1026 #define DANUBE_IOM_STAR_XACI (1 << 1)
1028 /***Command Register***/
1029 #define DANUBE_IOM_CMDR ((volatile u32*)(DANUBE_IOM+ 0x0084))
1030 #define DANUBE_IOM_CMDR_RMC (1 << 7)
1031 #define DANUBE_IOM_CMDR_RRES (1 << 6)
1032 #define DANUBE_IOM_CMDR_XTF (1 << 3)
1033 #define DANUBE_IOM_CMDR_XME (1 << 1)
1034 #define DANUBE_IOM_CMDR_XRES (1 << 0)
1036 /***Mode Register***/
1037 #define DANUBE_IOM_MODEH ((volatile u32*)(DANUBE_IOM+ 0x0088))
1038 #define DANUBE_IOM_MODEH_MDS2 (1 << 7)
1039 #define DANUBE_IOM_MODEH_MDS1 (1 << 6)
1040 #define DANUBE_IOM_MODEH_MDS0 (1 << 5)
1041 #define DANUBE_IOM_MODEH_RAC (1 << 3)
1042 #define DANUBE_IOM_MODEH_DIM2 (1 << 2)
1043 #define DANUBE_IOM_MODEH_DIM1 (1 << 1)
1044 #define DANUBE_IOM_MODEH_DIM0 (1 << 0)
1046 /***Extended Mode Register***/
1047 #define DANUBE_IOM_EXMR ((volatile u32*)(DANUBE_IOM+ 0x008C))
1048 #define DANUBE_IOM_EXMR_XFBS (1 << 7)
1049 #define DANUBE_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5)
1050 #define DANUBE_IOM_EXMR_SRA (1 << 4)
1051 #define DANUBE_IOM_EXMR_XCRC (1 << 3)
1052 #define DANUBE_IOM_EXMR_RCRC (1 << 2)
1053 #define DANUBE_IOM_EXMR_ITF (1 << 0)
1055 /***SAPI1 Register***/
1056 #define DANUBE_IOM_SAP1 ((volatile u32*)(DANUBE_IOM+ 0x0094))
1057 #define DANUBE_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2)
1058 #define DANUBE_IOM_SAP1_MHA (1 << 0)
1060 /***Receive Frame Byte Count Low***/
1061 #define DANUBE_IOM_RBCL ((volatile u32*)(DANUBE_IOM+ 0x0098))
1062 #define DANUBE_IOM_RBCL_RBC(value) (1 << value)
1065 /***SAPI2 Register***/
1066 #define DANUBE_IOM_SAP2 ((volatile u32*)(DANUBE_IOM+ 0x0098))
1067 #define DANUBE_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2)
1068 #define DANUBE_IOM_SAP2_MLA (1 << 0)
1070 /***Receive Frame Byte Count High***/
1071 #define DANUBE_IOM_RBCH ((volatile u32*)(DANUBE_IOM+ 0x009C))
1072 #define DANUBE_IOM_RBCH_OV (1 << 4)
1073 #define DANUBE_IOM_RBCH_RBC11 (1 << 3)
1074 #define DANUBE_IOM_RBCH_RBC10 (1 << 2)
1075 #define DANUBE_IOM_RBCH_RBC9 (1 << 1)
1076 #define DANUBE_IOM_RBCH_RBC8 (1 << 0)
1078 /***TEI1 Register 1***/
1079 #define DANUBE_IOM_TEI1 ((volatile u32*)(DANUBE_IOM+ 0x009C))
1080 #define DANUBE_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1)
1081 #define DANUBE_IOM_TEI1_EA (1 << 0)
1083 /***Receive Status Register***/
1084 #define DANUBE_IOM_RSTA ((volatile u32*)(DANUBE_IOM+ 0x00A0))
1085 #define DANUBE_IOM_RSTA_VFR (1 << 7)
1086 #define DANUBE_IOM_RSTA_RDO (1 << 6)
1087 #define DANUBE_IOM_RSTA_CRC (1 << 5)
1088 #define DANUBE_IOM_RSTA_RAB (1 << 4)
1089 #define DANUBE_IOM_RSTA_SA1 (1 << 3)
1090 #define DANUBE_IOM_RSTA_SA0 (1 << 2)
1091 #define DANUBE_IOM_RSTA_TA (1 << 0)
1092 #define DANUBE_IOM_RSTA_CR (1 << 1)
1094 /***TEI2 Register***/
1095 #define DANUBE_IOM_TEI2 ((volatile u32*)(DANUBE_IOM+ 0x00A0))
1096 #define DANUBE_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1)
1097 #define DANUBE_IOM_TEI2_EA (1 << 0)
1099 /***Test Mode Register HDLC***/
1100 #define DANUBE_IOM_TMH ((volatile u32*)(DANUBE_IOM+ 0x00A4))
1101 #define DANUBE_IOM_TMH_TLP (1 << 0)
1103 /***Command/Indication Receive 0***/
1104 #define DANUBE_IOM_CIR0 ((volatile u32*)(DANUBE_IOM+ 0x00B8))
1105 #define DANUBE_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4)
1106 #define DANUBE_IOM_CIR0_CIC0 (1 << 3)
1107 #define DANUBE_IOM_CIR0_CIC1 (1 << 2)
1108 #define DANUBE_IOM_CIR0_SG (1 << 1)
1109 #define DANUBE_IOM_CIR0_BAS (1 << 0)
1111 /***Command/Indication Transmit 0***/
1112 #define DANUBE_IOM_CIX0 ((volatile u32*)(DANUBE_IOM+ 0x00B8))
1113 #define DANUBE_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4)
1114 #define DANUBE_IOM_CIX0_TBA2 (1 << 3)
1115 #define DANUBE_IOM_CIX0_TBA1 (1 << 2)
1116 #define DANUBE_IOM_CIX0_TBA0 (1 << 1)
1117 #define DANUBE_IOM_CIX0_BAC (1 << 0)
1119 /***Command/Indication Receive 1***/
1120 #define DANUBE_IOM_CIR1 ((volatile u32*)(DANUBE_IOM+ 0x00BC))
1121 #define DANUBE_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2)
1123 /***Command/Indication Transmit 1***/
1124 #define DANUBE_IOM_CIX1 ((volatile u32*)(DANUBE_IOM+ 0x00BC))
1125 #define DANUBE_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2)
1126 #define DANUBE_IOM_CIX1_CICW (1 << 1)
1127 #define DANUBE_IOM_CIX1_CI1E (1 << 0)
1129 /***Controller Data Access Reg. (CH10)***/
1130 #define DANUBE_IOM_CDA10 ((volatile u32*)(DANUBE_IOM+ 0x0100))
1131 #define DANUBE_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
1133 /***Controller Data Access Reg. (CH11)***/
1134 #define DANUBE_IOM_CDA11 ((volatile u32*)(DANUBE_IOM+ 0x0104))
1135 #define DANUBE_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
1137 /***Controller Data Access Reg. (CH20)***/
1138 #define DANUBE_IOM_CDA20 ((volatile u32*)(DANUBE_IOM+ 0x0108))
1139 #define DANUBE_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
1141 /***Controller Data Access Reg. (CH21)***/
1142 #define DANUBE_IOM_CDA21 ((volatile u32*)(DANUBE_IOM+ 0x010C))
1143 #define DANUBE_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
1145 /***Time Slot and Data Port Sel. (CH10)***/
1146 #define DANUBE_IOM_CDA_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0110))
1147 #define DANUBE_IOM_CDA_TSDP10_DPS (1 << 7)
1148 #define DANUBE_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1150 /***Time Slot and Data Port Sel. (CH11)***/
1151 #define DANUBE_IOM_CDA_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0114))
1152 #define DANUBE_IOM_CDA_TSDP11_DPS (1 << 7)
1153 #define DANUBE_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1155 /***Time Slot and Data Port Sel. (CH20)***/
1156 #define DANUBE_IOM_CDA_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0118))
1157 #define DANUBE_IOM_CDA_TSDP20_DPS (1 << 7)
1158 #define DANUBE_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1160 /***Time Slot and Data Port Sel. (CH21)***/
1161 #define DANUBE_IOM_CDA_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x011C))
1162 #define DANUBE_IOM_CDA_TSDP21_DPS (1 << 7)
1163 #define DANUBE_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1165 /***Time Slot and Data Port Sel. (CH10)***/
1166 #define DANUBE_IOM_CO_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0120))
1167 #define DANUBE_IOM_CO_TSDP10_DPS (1 << 7)
1168 #define DANUBE_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1170 /***Time Slot and Data Port Sel. (CH11)***/
1171 #define DANUBE_IOM_CO_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0124))
1172 #define DANUBE_IOM_CO_TSDP11_DPS (1 << 7)
1173 #define DANUBE_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1175 /***Time Slot and Data Port Sel. (CH20)***/
1176 #define DANUBE_IOM_CO_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0128))
1177 #define DANUBE_IOM_CO_TSDP20_DPS (1 << 7)
1178 #define DANUBE_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1180 /***Time Slot and Data Port Sel. (CH21)***/
1181 #define DANUBE_IOM_CO_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x012C))
1182 #define DANUBE_IOM_CO_TSDP21_DPS (1 << 7)
1183 #define DANUBE_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1185 /***Ctrl. Reg. Contr. Data Access CH1x***/
1186 #define DANUBE_IOM_CDA1_CR ((volatile u32*)(DANUBE_IOM+ 0x0138))
1187 #define DANUBE_IOM_CDA1_CR_EN_TBM (1 << 5)
1188 #define DANUBE_IOM_CDA1_CR_EN_I1 (1 << 4)
1189 #define DANUBE_IOM_CDA1_CR_EN_I0 (1 << 3)
1190 #define DANUBE_IOM_CDA1_CR_EN_O1 (1 << 2)
1191 #define DANUBE_IOM_CDA1_CR_EN_O0 (1 << 1)
1192 #define DANUBE_IOM_CDA1_CR_SWAP (1 << 0)
1194 /***Ctrl. Reg. Contr. Data Access CH1x***/
1195 #define DANUBE_IOM_CDA2_CR ((volatile u32*)(DANUBE_IOM+ 0x013C))
1196 #define DANUBE_IOM_CDA2_CR_EN_TBM (1 << 5)
1197 #define DANUBE_IOM_CDA2_CR_EN_I1 (1 << 4)
1198 #define DANUBE_IOM_CDA2_CR_EN_I0 (1 << 3)
1199 #define DANUBE_IOM_CDA2_CR_EN_O1 (1 << 2)
1200 #define DANUBE_IOM_CDA2_CR_EN_O0 (1 << 1)
1201 #define DANUBE_IOM_CDA2_CR_SWAP (1 << 0)
1203 /***Control Register B-Channel Data***/
1204 #define DANUBE_IOM_BCHA_CR ((volatile u32*)(DANUBE_IOM+ 0x0144))
1205 #define DANUBE_IOM_BCHA_CR_EN_BC2 (1 << 4)
1206 #define DANUBE_IOM_BCHA_CR_EN_BC1 (1 << 3)
1208 /***Control Register B-Channel Data***/
1209 #define DANUBE_IOM_BCHB_CR ((volatile u32*)(DANUBE_IOM+ 0x0148))
1210 #define DANUBE_IOM_BCHB_CR_EN_BC2 (1 << 4)
1211 #define DANUBE_IOM_BCHB_CR_EN_BC1 (1 << 3)
1213 /***Control Reg. for HDLC and CI1 Data***/
1214 #define DANUBE_IOM_DCI_CR ((volatile u32*)(DANUBE_IOM+ 0x014C))
1215 #define DANUBE_IOM_DCI_CR_DPS_CI1 (1 << 7)
1216 #define DANUBE_IOM_DCI_CR_EN_CI1 (1 << 6)
1217 #define DANUBE_IOM_DCI_CR_EN_D (1 << 5)
1219 /***Control Reg. for HDLC and CI1 Data***/
1220 #define DANUBE_IOM_DCIC_CR ((volatile u32*)(DANUBE_IOM+ 0x014C))
1221 #define DANUBE_IOM_DCIC_CR_DPS_CI0 (1 << 7)
1222 #define DANUBE_IOM_DCIC_CR_EN_CI0 (1 << 6)
1223 #define DANUBE_IOM_DCIC_CR_DPS_D (1 << 5)
1225 /***Control Reg. Serial Data Strobe x***/
1226 #define DANUBE_IOM_SDS_CR ((volatile u32*)(DANUBE_IOM+ 0x0154))
1227 #define DANUBE_IOM_SDS_CR_ENS_TSS (1 << 7)
1228 #define DANUBE_IOM_SDS_CR_ENS_TSS_1 (1 << 6)
1229 #define DANUBE_IOM_SDS_CR_ENS_TSS_3 (1 << 5)
1230 #define DANUBE_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1232 /***Control Register IOM Data***/
1233 #define DANUBE_IOM_IOM_CR ((volatile u32*)(DANUBE_IOM+ 0x015C))
1234 #define DANUBE_IOM_IOM_CR_SPU (1 << 7)
1235 #define DANUBE_IOM_IOM_CR_CI_CS (1 << 5)
1236 #define DANUBE_IOM_IOM_CR_TIC_DIS (1 << 4)
1237 #define DANUBE_IOM_IOM_CR_EN_BCL (1 << 3)
1238 #define DANUBE_IOM_IOM_CR_CLKM (1 << 2)
1239 #define DANUBE_IOM_IOM_CR_Res (1 << 1)
1240 #define DANUBE_IOM_IOM_CR_DIS_IOM (1 << 0)
1242 /***Synchronous Transfer Interrupt***/
1243 #define DANUBE_IOM_STI ((volatile u32*)(DANUBE_IOM+ 0x0160))
1244 #define DANUBE_IOM_STI_STOV21 (1 << 7)
1245 #define DANUBE_IOM_STI_STOV20 (1 << 6)
1246 #define DANUBE_IOM_STI_STOV11 (1 << 5)
1247 #define DANUBE_IOM_STI_STOV10 (1 << 4)
1248 #define DANUBE_IOM_STI_STI21 (1 << 3)
1249 #define DANUBE_IOM_STI_STI20 (1 << 2)
1250 #define DANUBE_IOM_STI_STI11 (1 << 1)
1251 #define DANUBE_IOM_STI_STI10 (1 << 0)
1253 /***Acknowledge Synchronous Transfer Interrupt***/
1254 #define DANUBE_IOM_ASTI ((volatile u32*)(DANUBE_IOM+ 0x0160))
1255 #define DANUBE_IOM_ASTI_ACK21 (1 << 3)
1256 #define DANUBE_IOM_ASTI_ACK20 (1 << 2)
1257 #define DANUBE_IOM_ASTI_ACK11 (1 << 1)
1258 #define DANUBE_IOM_ASTI_ACK10 (1 << 0)
1260 /***Mask Synchronous Transfer Interrupt***/
1261 #define DANUBE_IOM_MSTI ((volatile u32*)(DANUBE_IOM+ 0x0164))
1262 #define DANUBE_IOM_MSTI_STOV21 (1 << 7)
1263 #define DANUBE_IOM_MSTI_STOV20 (1 << 6)
1264 #define DANUBE_IOM_MSTI_STOV11 (1 << 5)
1265 #define DANUBE_IOM_MSTI_STOV10 (1 << 4)
1266 #define DANUBE_IOM_MSTI_STI21 (1 << 3)
1267 #define DANUBE_IOM_MSTI_STI20 (1 << 2)
1268 #define DANUBE_IOM_MSTI_STI11 (1 << 1)
1269 #define DANUBE_IOM_MSTI_STI10 (1 << 0)
1271 /***Configuration Register for Serial Data Strobes***/
1272 #define DANUBE_IOM_SDS_CONF ((volatile u32*)(DANUBE_IOM+ 0x0168))
1273 #define DANUBE_IOM_SDS_CONF_SDS_BCL (1 << 0)
1275 /***Monitoring CDA Bits***/
1276 #define DANUBE_IOM_MCDA ((volatile u32*)(DANUBE_IOM+ 0x016C))
1277 #define DANUBE_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6)
1278 #define DANUBE_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4)
1279 #define DANUBE_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2)
1280 #define DANUBE_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0)
1282 /***********************************************************************/
1283 /* Module : ASC0 register address and bits */
1284 /***********************************************************************/
1285 #define DANUBE_ASC0 (KSEG1+0x1E100400)
1286 /***********************************************************************/
1287 #define DANUBE_ASC0_TBUF ((volatile u32*)(DANUBE_ASC0 + 0x0020))
1288 #define DANUBE_ASC0_RBUF ((volatile u32*)(DANUBE_ASC0 + 0x0024))
1289 #define DANUBE_ASC0_FSTAT ((volatile u32*)(DANUBE_ASC0 + 0x0048))
1290 #define DANUBE_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1))
1291 #define DANUBE_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24)
1292 #define DANUBE_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1))
1293 #define DANUBE_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16)
1294 #define DANUBE_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1))
1295 #define DANUBE_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8)
1296 #define DANUBE_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1))
1297 #define DANUBE_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0)
1300 /***********************************************************************/
1301 /* Module : ASC1 register address and bits */
1302 /***********************************************************************/
1304 #define DANUBE_ASC1 (KSEG1+0x1E100C00)
1305 /***********************************************************************/
1307 #define DANUBE_ASC1_TBUF ((volatile u32*)(DANUBE_ASC1 + 0x0020))
1308 #define DANUBE_ASC1_RBUF ((volatile u32*)(DANUBE_ASC1 + 0x0024))
1309 #define DANUBE_ASC1_FSTAT ((volatile u32*)(DANUBE_ASC1 + 0x0048))
1310 #define DANUBE_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1))
1311 #define DANUBE_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24)
1312 #define DANUBE_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1))
1313 #define DANUBE_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16)
1314 #define DANUBE_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1))
1315 #define DANUBE_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8)
1316 #define DANUBE_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1))
1317 #define DANUBE_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0)
1319 /***********************************************************************/
1320 /* Module : DMA register address and bits */
1321 /***********************************************************************/
1322 /***********************************************************************/
1323 /* Module : DMA register address and bits */
1324 /***********************************************************************/
1326 #define DANUBE_DMA (0xBE104100)
1327 /***********************************************************************/
1329 #define DANUBE_DMA_BASE DANUBE_DMA
1330 #define DANUBE_DMA_CLC (volatile u32*)DANUBE_DMA_BASE
1331 #define DANUBE_DMA_ID (volatile u32*)(DANUBE_DMA_BASE+0x08)
1332 #define DANUBE_DMA_CTRL (volatile u32*)(DANUBE_DMA_BASE+0x10)
1333 #define DANUBE_DMA_CPOLL (volatile u32*)(DANUBE_DMA_BASE+0x14)
1334 #define DANUBE_DMA_CS (volatile u32*)(DANUBE_DMA_BASE+0x18)
1335 #define DANUBE_DMA_CCTRL (volatile u32*)(DANUBE_DMA_BASE+0x1C)
1336 #define DANUBE_DMA_CDBA (volatile u32*)(DANUBE_DMA_BASE+0x20)
1337 #define DANUBE_DMA_CDLEN (volatile u32*)(DANUBE_DMA_BASE+0x24)
1338 #define DANUBE_DMA_CIS (volatile u32*)(DANUBE_DMA_BASE+0x28)
1339 #define DANUBE_DMA_CIE (volatile u32*)(DANUBE_DMA_BASE+0x2C)
1341 #define DANUBE_DMA_PS (volatile u32*)(DANUBE_DMA_BASE+0x40)
1342 #define DANUBE_DMA_PCTRL (volatile u32*)(DANUBE_DMA_BASE+0x44)
1344 #define DANUBE_DMA_IRNEN (volatile u32*)(DANUBE_DMA_BASE+0xf4)
1345 #define DANUBE_DMA_IRNCR (volatile u32*)(DANUBE_DMA_BASE+0xf8)
1346 #define DANUBE_DMA_IRNICR (volatile u32*)(DANUBE_DMA_BASE+0xfc)
1347 /***********************************************************************/
1348 /* Module : Debug register address and bits */
1349 /***********************************************************************/
1351 #define DANUBE_Debug (0xBF106000)
1352 /***********************************************************************/
1355 /***MCD Break Bus Switch Register***/
1356 #define DANUBE_Debug_MCD_BBS ((volatile u32*)(DANUBE_Debug+ 0x0000))
1357 #define DANUBE_Debug_MCD_BBS_BTP1 (1 << 19)
1358 #define DANUBE_Debug_MCD_BBS_BTP0 (1 << 18)
1359 #define DANUBE_Debug_MCD_BBS_BSP1 (1 << 17)
1360 #define DANUBE_Debug_MCD_BBS_BSP0 (1 << 16)
1361 #define DANUBE_Debug_MCD_BBS_BT5EN (1 << 15)
1362 #define DANUBE_Debug_MCD_BBS_BT4EN (1 << 14)
1363 #define DANUBE_Debug_MCD_BBS_BT5 (1 << 13)
1364 #define DANUBE_Debug_MCD_BBS_BT4 (1 << 12)
1365 #define DANUBE_Debug_MCD_BBS_BS5EN (1 << 7)
1366 #define DANUBE_Debug_MCD_BBS_BS4EN (1 << 6)
1367 #define DANUBE_Debug_MCD_BBS_BS5 (1 << 5)
1368 #define DANUBE_Debug_MCD_BBS_BS4 (1 << 4)
1370 /***MCD Multiplexer Control Register***/
1371 #define DANUBE_Debug_MCD_MCR ((volatile u32*)(DANUBE_Debug+ 0x0008))
1372 #define DANUBE_Debug_MCD_MCR_MUX5 (1 << 4)
1373 #define DANUBE_Debug_MCD_MCR_MUX4 (1 << 3)
1374 #define DANUBE_Debug_MCD_MCR_MUX1 (1 << 0)
1377 /***********************************************************************/
1378 /* Module : SRAM register address and bits */
1379 /***********************************************************************/
1381 #define DANUBE_SRAM (0xBF980000)
1382 /***********************************************************************/
1385 /***SRAM Size Register***/
1386 #define DANUBE_SRAM_SRAM_SIZE ((volatile u32*)(DANUBE_SRAM+ 0x0800))
1387 #define DANUBE_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0)
1389 /***********************************************************************/
1390 /* Module : BIU register address and bits */
1391 /***********************************************************************/
1393 #define DANUBE_BIU (0xBFA80000)
1394 /***********************************************************************/
1397 /***BIU Identification Register***/
1398 #define DANUBE_BIU_BIU_ID ((volatile u32*)(DANUBE_BIU+ 0x0000))
1399 #define DANUBE_BIU_BIU_ID_ARCH (1 << 16)
1400 #define DANUBE_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8)
1401 #define DANUBE_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0)
1403 /***BIU Access Error Cause Register***/
1404 #define DANUBE_BIU_BIU_ERRCAUSE ((volatile u32*)(DANUBE_BIU+ 0x0100))
1405 #define DANUBE_BIU_BIU_ERRCAUSE_ERR (1 << 31)
1406 #define DANUBE_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
1407 #define DANUBE_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
1409 /***BIU Access Error Address Register***/
1410 #define DANUBE_BIU_BIU_ERRADDR ((volatile u32*)(DANUBE_BIU+ 0x0108))
1411 #define DANUBE_BIU_BIU_ERRADDR_ADDR
1414 /***********************************************************************/
1415 /* Module : ICU register address and bits */
1416 /***********************************************************************/
1418 #define DANUBE_ICU (0xBF880200)
1419 #define DANUBE_ICU (0xBF880200)
1420 #define DANUBE_ICU_EXI (0xBF101000)
1421 /***********************************************************************/
1424 /***IM0 Interrupt Status Register***/
1425 #define DANUBE_ICU_IM0_ISR ((volatile u32*)(DANUBE_ICU+ 0x0000))
1426 #define DANUBE_ICU_IM0_ISR_IR(value) (1 << (value))
1429 /***IM1 Interrupt Status Register***/
1430 #define DANUBE_ICU_IM1_ISR ((volatile u32*)(DANUBE_ICU+ 0x0020))
1431 #define DANUBE_ICU_IM1_ISR_IR(value) (1 << (value))
1434 /***IM2 Interrupt Status Register***/
1435 #define DANUBE_ICU_IM2_ISR ((volatile u32*)(DANUBE_ICU+ 0x0040))
1436 #define DANUBE_ICU_IM2_ISR_IR(value) (1 << (value))
1438 /***IM3 Interrupt Status Register***/
1439 #define DANUBE_ICU_IM3_ISR ((volatile u32*)(DANUBE_ICU+ 0x0060))
1440 #define DANUBE_ICU_IM3_ISR_IR(value) (1 << (value))
1442 /***IM4 Interrupt Status Register***/
1443 #define DANUBE_ICU_IM4_ISR ((volatile u32*)(DANUBE_ICU+ 0x0080))
1444 #define DANUBE_ICU_IM4_ISR_IR(value) (1 << (value))
1447 /***IM0 Interrupt Enable Register***/
1448 #define DANUBE_ICU_IM0_IER ((volatile u32*)(DANUBE_ICU+ 0x0008))
1449 #define DANUBE_ICU_IM0_IER_IR(value) (1 << (value))
1452 /***IM1 Interrupt Enable Register***/
1453 #define DANUBE_ICU_IM1_IER ((volatile u32*)(DANUBE_ICU+ 0x0028))
1454 #define DANUBE_ICU_IM1_IER_IR(value) (1 << (value))
1457 /***IM2 Interrupt Enable Register***/
1458 #define DANUBE_ICU_IM2_IER ((volatile u32*)(DANUBE_ICU+ 0x0048))
1459 #define DANUBE_ICU_IM2_IER_IR(value) (1 << (value)8
1461 /***IM3 Interrupt Enable Register***/
1462 #define DANUBE_ICU_IM3_IER ((volatile u32*)(DANUBE_ICU+ 0x0068))
1463 #define DANUBE_ICU_IM3_IER_IR(value) (1 << (value))
1465 /***IM4 Interrupt Enable Register***/
1466 #define DANUBE_ICU_IM4_IER ((volatile u32*)(DANUBE_ICU+ 0x0088))
1467 #define DANUBE_ICU_IM4_IER_IR(value) (1 << (value))
1470 /***IM0 Interrupt Output Status Register***/
1471 #define DANUBE_ICU_IM0_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0010))
1472 #define DANUBE_ICU_IM0_IOSR_IR(value) (1 << (value))
1475 /***IM1 Interrupt Output Status Register***/
1476 #define DANUBE_ICU_IM1_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0030))
1477 #define DANUBE_ICU_IM1_IOSR_IR(value) (1 << (value))
1480 /***IM2 Interrupt Output Status Register***/
1481 #define DANUBE_ICU_IM2_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0050))
1482 #define DANUBE_ICU_IM2_IOSR_IR(value) (1 << (value))
1484 /***IM3 Interrupt Output Status Register***/
1485 #define DANUBE_ICU_IM3_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0070))
1486 #define DANUBE_ICU_IM3_IOSR_IR(value) (1 << (value))
1488 /***IM4 Interrupt Output Status Register***/
1489 #define DANUBE_ICU_IM4_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0090))
1490 #define DANUBE_ICU_IM4_IOSR_IR(value) (1 << (value))
1493 /***IM0 Interrupt Request Set Register***/
1494 #define DANUBE_ICU_IM0_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0018))
1495 #define DANUBE_ICU_IM0_IRSR_IR(value) (1 << (value))
1498 /***IM1 Interrupt Request Set Register***/
1499 #define DANUBE_ICU_IM1_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0038))
1500 #define DANUBE_ICU_IM1_IRSR_IR(value) (1 << (value))
1503 /***IM2 Interrupt Request Set Register***/
1504 #define DANUBE_ICU_IM2_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0058))
1505 #define DANUBE_ICU_IM2_IRSR_IR(value) (1 << (value))
1507 /***IM3 Interrupt Request Set Register***/
1508 #define DANUBE_ICU_IM3_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0078))
1509 #define DANUBE_ICU_IM3_IRSR_IR(value) (1 << (value))
1511 /***IM4 Interrupt Request Set Register***/
1512 #define DANUBE_ICU_IM4_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0098))
1513 #define DANUBE_ICU_IM4_IRSR_IR(value) (1 << (value))
1515 /***Interrupt Vector Value Register***/
1516 #define DANUBE_ICU_IM_VEC ((volatile u32*)(DANUBE_ICU+ 0x0060))
1518 /***Interrupt Vector Value Mask***/
1519 #define DANUBE_ICU_IM0_VEC_MASK 0x0000001f
1520 #define DANUBE_ICU_IM1_VEC_MASK 0x000003e0
1521 #define DANUBE_ICU_IM2_VEC_MASK 0x00007c00
1522 #define DANUBE_ICU_IM3_VEC_MASK 0x000f8000
1523 #define DANUBE_ICU_IM4_VEC_MASK 0x01f00000
1525 /***DMA Interrupt Mask Value***/
1526 #define DANUBE_DMA_H_MASK 0x00000fff
1528 /***External Interrupt Control Register***/
1529 #define DANUBE_ICU_EXTINTCR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0000))
1530 #define DANUBE_ICU_IRNICR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0004))
1531 #define DANUBE_ICU_IRNCR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0008))
1532 #define DANUBE_ICU_IRNEN ((volatile u32*)(DANUBE_ICU_EXI+ 0x000c))
1533 #define DANUBE_ICU_NMI_CR ((volatile u32*)(DANUBE_ICU_EXI+ 0x00f0))
1534 #define DANUBE_ICU_NMI_SR ((volatile u32*)(DANUBE_ICU_EXI+ 0x00f4))
1536 /***********************************************************************/
1537 /* Module : MPS register address and bits */
1538 /***********************************************************************/
1540 #define DANUBE_MPS (KSEG1+0x1F107000)
1541 /***********************************************************************/
1543 #define DANUBE_MPS_CHIPID ((volatile u32*)(DANUBE_MPS + 0x0344))
1544 #define DANUBE_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
1545 #define DANUBE_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
1546 #define DANUBE_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
1547 #define DANUBE_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
1548 #define DANUBE_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
1549 #define DANUBE_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1)
1552 /* voice channel 0 ... 3 interrupt enable register */
1553 #define DANUBE_MPS_VC0ENR ((volatile u32*)(DANUBE_MPS + 0x0000))
1554 #define DANUBE_MPS_VC1ENR ((volatile u32*)(DANUBE_MPS + 0x0004))
1555 #define DANUBE_MPS_VC2ENR ((volatile u32*)(DANUBE_MPS + 0x0008))
1556 #define DANUBE_MPS_VC3ENR ((volatile u32*)(DANUBE_MPS + 0x000C))
1557 /* voice channel 0 ... 3 interrupt status read register */
1558 #define DANUBE_MPS_RVC0SR ((volatile u32*)(DANUBE_MPS + 0x0010))
1559 #define DANUBE_MPS_RVC1SR ((volatile u32*)(DANUBE_MPS + 0x0014))
1560 #define DANUBE_MPS_RVC2SR ((volatile u32*)(DANUBE_MPS + 0x0018))
1561 #define DANUBE_MPS_RVC3SR ((volatile u32*)(DANUBE_MPS + 0x001C))
1562 /* voice channel 0 ... 3 interrupt status set register */
1563 #define DANUBE_MPS_SVC0SR ((volatile u32*)(DANUBE_MPS + 0x0020))
1564 #define DANUBE_MPS_SVC1SR ((volatile u32*)(DANUBE_MPS + 0x0024))
1565 #define DANUBE_MPS_SVC2SR ((volatile u32*)(DANUBE_MPS + 0x0028))
1566 #define DANUBE_MPS_SVC3SR ((volatile u32*)(DANUBE_MPS + 0x002C))
1567 /* voice channel 0 ... 3 interrupt status clear register */
1568 #define DANUBE_MPS_CVC0SR ((volatile u32*)(DANUBE_MPS + 0x0030))
1569 #define DANUBE_MPS_CVC1SR ((volatile u32*)(DANUBE_MPS + 0x0034))
1570 #define DANUBE_MPS_CVC2SR ((volatile u32*)(DANUBE_MPS + 0x0038))
1571 #define DANUBE_MPS_CVC3SR ((volatile u32*)(DANUBE_MPS + 0x003C))
1572 /* common status 0 and 1 read register */
1573 #define DANUBE_MPS_RAD0SR ((volatile u32*)(DANUBE_MPS + 0x0040))
1574 #define DANUBE_MPS_RAD1SR ((volatile u32*)(DANUBE_MPS + 0x0044))
1575 /* common status 0 and 1 set register */
1576 #define DANUBE_MPS_SAD0SR ((volatile u32*)(DANUBE_MPS + 0x0048))
1577 #define DANUBE_MPS_SAD1SR ((volatile u32*)(DANUBE_MPS + 0x004C))
1578 /* common status 0 and 1 clear register */
1579 #define DANUBE_MPS_CAD0SR ((volatile u32*)(DANUBE_MPS + 0x0050))
1580 #define DANUBE_MPS_CAD1SR ((volatile u32*)(DANUBE_MPS + 0x0054))
1581 /* common status 0 and 1 enable register */
1582 #define DANUBE_MPS_AD0ENR ((volatile u32*)(DANUBE_MPS + 0x0058))
1583 #define DANUBE_MPS_AD1ENR ((volatile u32*)(DANUBE_MPS + 0x005C))
1584 /* notification enable register */
1585 #define DANUBE_MPS_CPU0_NFER ((volatile u32*)(DANUBE_MPS + 0x0060))
1586 #define DANUBE_MPS_CPU1_NFER ((volatile u32*)(DANUBE_MPS + 0x0064))
1587 /* CPU to CPU interrup request register */
1588 #define DANUBE_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(DANUBE_MPS + 0x0070))
1589 #define DANUBE_MPS_CPU0_2_CPU1_IER ((volatile u32*)(DANUBE_MPS + 0x0074))
1590 /* Global interrupt request and request enable register */
1591 #define DANUBE_MPS_GIRR ((volatile u32*)(DANUBE_MPS + 0x0078))
1592 #define DANUBE_MPS_GIER ((volatile u32*)(DANUBE_MPS + 0x007C))
1595 #define DANUBE_MPS_CPU0_SMP0 ((volatile u32*)(DANUBE_MPS + 0x00100))
1597 #define DANUBE_MPS_CPU1_SMP0 ((volatile u32*)(DANUBE_MPS + 0x00200))
1599 /************************************************************************/
1600 /* Module : DEU register address and bits */
1601 /************************************************************************/
1602 #define DANUBE_DEU_BASE_ADDR (0xBE102000)
1603 /* DEU Control Register */
1604 #define DANUBE_DEU_CLK ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0000))
1605 #define DANUBE_DEU_ID ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0008))
1607 /* DEU control register */
1608 #define DANUBE_DEU_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0010))
1609 #define DANUBE_DEU_IHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0014))
1610 #define DANUBE_DEU_ILR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0018))
1611 #define DANUBE_DEU_K1HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x001C))
1612 #define DANUBE_DEU_K1LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0020))
1613 #define DANUBE_DEU_K3HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0024))
1614 #define DANUBE_DEU_K3LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0028))
1615 #define DANUBE_DEU_IVHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x002C))
1616 #define DANUBE_DEU_IVLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0030))
1617 #define DANUBE_DEU_OHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0040))
1618 #define DANUBE_DEU_OLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050))
1620 /* AES DEU register */
1621 #define DANUBE_AES_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050))
1622 #define DANUBE_AES_ID3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0054))
1623 #define DANUBE_AES_ID2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0058))
1624 #define DANUBE_AES_ID1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x005C))
1625 #define DANUBE_AES_ID0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0060))
1627 /* AES Key register */
1628 #define DANUBE_AES_K7R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0064))
1629 #define DANUBE_AES_K6R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0068))
1630 #define DANUBE_AES_K5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x006C))
1631 #define DANUBE_AES_K4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0070))
1632 #define DANUBE_AES_K3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0074))
1633 #define DANUBE_AES_K2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0078))
1634 #define DANUBE_AES_K1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x007C))
1635 #define DANUBE_AES_K0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0080))
1637 /* AES vector register */
1638 #define DANUBE_AES_IV3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0084))
1639 #define DANUBE_AES_IV2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0088))
1640 #define DANUBE_AES_IV1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x008C))
1641 #define DANUBE_AES_IV0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0090))
1642 #define DANUBE_AES_0D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0094))
1643 #define DANUBE_AES_0D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0098))
1644 #define DANUBE_AES_OD1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x009C))
1645 #define DANUBE_AES_OD0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00A0))
1647 /* hash control registe */
1648 #define DANUBE_HASH_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B0))
1649 #define DANUBE_HASH_MR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B4))
1650 #define DANUBE_HASH_D1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B8 ))
1651 #define DANUBE_HASH_D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00BC ))
1652 #define DANUBE_HASH_D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C0 ))
1653 #define DANUBE_HASH_D4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C4))
1654 #define DANUBE_HASH_D5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C8))
1656 #define DANUBE_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00EC))
1661 /************************************************************************/
1662 /* Module : PPE register address and bits */
1663 /************************************************************************/
1664 #define DANUBE_PPE_BASE_ADDR (KSEG1 + 0x1E180000)
1665 #define DANUBE_PPE_PP32_DEBUG_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0000) << 2)))
1666 #define DANUBE_PPE_PPM_INT_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0030) << 2)))
1667 #define DANUBE_PPE_PP32_INTERNAL_RES_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0040) << 2)))
1668 #define DANUBE_PPE_PPE_CLOCK_CONTROL_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0100) << 2)))
1669 #define DANUBE_PPE_CDM_CODE_MEMORY_RAM0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x1000) << 2)))
1670 #define DANUBE_PPE_CDM_CODE_MEMORY_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x2000) << 2)))
1671 #define DANUBE_PPE_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x4000) << 2)))
1672 #define DANUBE_PPE_PP32_DATA_MEMORY_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x5000) << 2)))
1673 #define DANUBE_PPE_PPM_INT_UNIT_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6000) << 2)))
1674 #define DANUBE_PPE_PPM_TIMER0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6100) << 2)))
1675 #define DANUBE_PPE_PPM_TASK_IND_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6200) << 2)))
1676 #define DANUBE_PPE_PPS_BRK_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6300) << 2)))
1677 #define DANUBE_PPE_PPM_TIMER1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6400) << 2)))
1678 #define DANUBE_PPE_SB_RAM0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8000) << 2)))
1679 #define DANUBE_PPE_SB_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8400) << 2)))
1680 #define DANUBE_PPE_SB_RAM2_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8C00) << 2)))
1681 #define DANUBE_PPE_SB_RAM3_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x9600) << 2)))
1683 #define DANUBE_PPE_PP32_SLEEP DANUBE_PPE_REG_ADDR(0x0010) /* PP32 Power Saving Register */
1684 #define DANUBE_PPE_CDM_CFG DANUBE_PPE_REG_ADDR(0x0100) /* Code/Data Memory (CDM) Register */
1686 /* Mailbox Registers */
1687 #define DANUBE_PPE_MBOX_IGU0_ISRS DANUBE_PPE_REG_ADDR(0x0200)
1688 #define DANUBE_PPE_MBOX_IGU0_ISRC DANUBE_PPE_REG_ADDR(0x0201)
1689 #define DANUBE_PPE_MBOX_IGU0_ISR DANUBE_PPE_REG_ADDR(0x0202)
1690 #define DANUBE_PPE_MBOX_IGU0_IER DANUBE_PPE_REG_ADDR(0x0203)
1691 #define DANUBE_PPE_MBOX_IGU1_ISRS0 DANUBE_PPE_REG_ADDR(0x0204)
1692 #define DANUBE_PPE_MBOX_IGU1_ISRC0 DANUBE_PPE_REG_ADDR(0x0205)
1693 #define DANUBE_PPE_MBOX_IGU1_ISR0 DANUBE_PPE_REG_ADDR(0x0206)
1694 #define DANUBE_PPE_MBOX_IGU1_IER0 DANUBE_PPE_REG_ADDR(0x0207)
1695 #define DANUBE_PPE_MBOX_IGU1_ISRS1 DANUBE_PPE_REG_ADDR(0x0208)
1696 #define DANUBE_PPE_MBOX_IGU1_ISRC1 DANUBE_PPE_REG_ADDR(0x0209)
1697 #define DANUBE_PPE_MBOX_IGU1_ISR1 DANUBE_PPE_REG_ADDR(0x020A)
1698 #define DANUBE_PPE_MBOX_IGU1_IER1 DANUBE_PPE_REG_ADDR(0x020B)
1699 #define DANUBE_PPE_MBOX_IGU1_ISRS2 DANUBE_PPE_REG_ADDR(0x020C)
1700 #define DANUBE_PPE_MBOX_IGU1_ISRC2 DANUBE_PPE_REG_ADDR(0x020D)
1701 #define DANUBE_PPE_MBOX_IGU1_ISR2 DANUBE_PPE_REG_ADDR(0x020E)
1702 #define DANUBE_PPE_MBOX_IGU1_IER2 DANUBE_PPE_REG_ADDR(0x020F)
1703 #define DANUBE_PPE_MBOX_IGU2_ISRS DANUBE_PPE_REG_ADDR(0x0210)
1704 #define DANUBE_PPE_MBOX_IGU2_ISRC DANUBE_PPE_REG_ADDR(0x0211)
1705 #define DANUBE_PPE_MBOX_IGU2_ISR DANUBE_PPE_REG_ADDR(0x0212)
1706 #define DANUBE_PPE_MBOX_IGU2_IER DANUBE_PPE_REG_ADDR(0x0213)
1707 #define DANUBE_PPE_MBOX_IGU3_ISRS DANUBE_PPE_REG_ADDR(0x0214)
1708 #define DANUBE_PPE_MBOX_IGU3_ISRC DANUBE_PPE_REG_ADDR(0x0215)
1709 #define DANUBE_PPE_MBOX_IGU3_ISR DANUBE_PPE_REG_ADDR(0x0216)
1710 #define DANUBE_PPE_MBOX_IGU3_IER DANUBE_PPE_REG_ADDR(0x0217)
1711 #define DANUBE_PPE_MBOX_IGU4_ISRS DANUBE_PPE_REG_ADDR(0x0218)
1712 #define DANUBE_PPE_MBOX_IGU4_ISRC DANUBE_PPE_REG_ADDR(0x0219)
1713 #define DANUBE_PPE_MBOX_IGU4_ISR DANUBE_PPE_REG_ADDR(0x021A)
1714 #define DANUBE_PPE_MBOX_IGU4_IER DANUBE_PPE_REG_ADDR(0x021B)
1716 * Shared Buffer (SB) Registers
1718 #define DANUBE_PPE_SB_MST_PRI0 DANUBE_PPE_REG_ADDR(0x0300)
1719 #define DANUBE_PPE_SB_MST_PRI1 DANUBE_PPE_REG_ADDR(0x0301)
1720 #define DANUBE_PPE_SB_MST_PRI2 DANUBE_PPE_REG_ADDR(0x0302)
1721 #define DANUBE_PPE_SB_MST_PRI3 DANUBE_PPE_REG_ADDR(0x0303)
1722 #define DANUBE_PPE_SB_MST_PRI4 DANUBE_PPE_REG_ADDR(0x0304)
1723 #define DANUBE_PPE_SB_MST_SEL DANUBE_PPE_REG_ADDR(0x0305)
1727 #define DANUBE_PPE_RFBI_CFG DANUBE_PPE_REG_ADDR(0x0400)
1728 #define DANUBE_PPE_RBA_CFG0 DANUBE_PPE_REG_ADDR(0x0404)
1729 #define DANUBE_PPE_RBA_CFG1 DANUBE_PPE_REG_ADDR(0x0405)
1730 #define DANUBE_PPE_RCA_CFG0 DANUBE_PPE_REG_ADDR(0x0408)
1731 #define DANUBE_PPE_RCA_CFG1 DANUBE_PPE_REG_ADDR(0x0409)
1732 #define DANUBE_PPE_RDES_CFG0 DANUBE_PPE_REG_ADDR(0x040C)
1733 #define DANUBE_PPE_RDES_CFG1 DANUBE_PPE_REG_ADDR(0x040D)
1734 #define DANUBE_PPE_SFSM_STATE0 DANUBE_PPE_REG_ADDR(0x0410)
1735 #define DANUBE_PPE_SFSM_STATE1 DANUBE_PPE_REG_ADDR(0x0411)
1736 #define DANUBE_PPE_SFSM_DBA0 DANUBE_PPE_REG_ADDR(0x0412)
1737 #define DANUBE_PPE_SFSM_DBA1 DANUBE_PPE_REG_ADDR(0x0413)
1738 #define DANUBE_PPE_SFSM_CBA0 DANUBE_PPE_REG_ADDR(0x0414)
1739 #define DANUBE_PPE_SFSM_CBA1 DANUBE_PPE_REG_ADDR(0x0415)
1740 #define DANUBE_PPE_SFSM_CFG0 DANUBE_PPE_REG_ADDR(0x0416)
1741 #define DANUBE_PPE_SFSM_CFG1 DANUBE_PPE_REG_ADDR(0x0417)
1742 #define DANUBE_PPE_SFSM_PGCNT0 DANUBE_PPE_REG_ADDR(0x041C)
1743 #define DANUBE_PPE_SFSM_PGCNT1 DANUBE_PPE_REG_ADDR(0x041D)
1747 #define DANUBE_PPE_FFSM_DBA0 DANUBE_PPE_REG_ADDR(0x0508)
1748 #define DANUBE_PPE_FFSM_DBA1 DANUBE_PPE_REG_ADDR(0x0509)
1749 #define DANUBE_PPE_FFSM_CFG0 DANUBE_PPE_REG_ADDR(0x050A)
1750 #define DANUBE_PPE_FFSM_CFG1 DANUBE_PPE_REG_ADDR(0x050B)
1751 #define DANUBE_PPE_FFSM_IDLE_HEAD_BC0 DANUBE_PPE_REG_ADDR(0x050E)
1752 #define DANUBE_PPE_FFSM_IDLE_HEAD_BC1 DANUBE_PPE_REG_ADDR(0x050F)
1753 #define DANUBE_PPE_FFSM_PGCNT0 DANUBE_PPE_REG_ADDR(0x0514)
1754 #define DANUBE_PPE_FFSM_PGCNT1 DANUBE_PPE_REG_ADDR(0x0515)
1756 * ETOP MDIO Registers
1758 #define DANUBE_PPE_ETOP_MDIO_CFG DANUBE_PPE_REG_ADDR(0x0600)
1759 #define DANUBE_PPE_ETOP_MDIO_ACC DANUBE_PPE_REG_ADDR(0x0601)
1760 #define DANUBE_PPE_ETOP_CFG DANUBE_PPE_REG_ADDR(0x0602)
1761 #define DANUBE_PPE_ETOP_IG_VLAN_COS DANUBE_PPE_REG_ADDR(0x0603)
1762 #define DANUBE_PPE_ETOP_IG_DSCP_COS3 DANUBE_PPE_REG_ADDR(0x0604)
1763 #define DANUBE_PPE_ETOP_IG_DSCP_COS2 DANUBE_PPE_REG_ADDR(0x0605)
1764 #define DANUBE_PPE_ETOP_IG_DSCP_COS1 DANUBE_PPE_REG_ADDR(0x0606)
1765 #define DANUBE_PPE_ETOP_IG_DSCP_COS0 DANUBE_PPE_REG_ADDR(0x0607)
1766 #define DANUBE_PPE_ETOP_IG_PLEN_CTRL0 DANUBE_PPE_REG_ADDR(0x0608)
1767 #define DANUBE_PPE_ETOP_IG_PLEN_CTRL1 DANUBE_PPE_REG_ADDR(0x0609)
1768 #define DANUBE_PPE_ETOP_ISR DANUBE_PPE_REG_ADDR(0x060A)
1769 #define DANUBE_PPE_ETOP_IER DANUBE_PPE_REG_ADDR(0x060B)
1770 #define DANUBE_PPE_ETOP_VPID DANUBE_PPE_REG_ADDR(0x060C)
1771 #define DANUBE_PPE_ENET_MAC_CFG DANUBE_PPE_REG_ADDR(0x0610)
1772 #define DANUBE_PPE_ENETS_DBA DANUBE_PPE_REG_ADDR(0x0612)
1773 #define DANUBE_PPE_ENETS_CBA DANUBE_PPE_REG_ADDR(0x0613)
1774 #define DANUBE_PPE_ENETS_CFG DANUBE_PPE_REG_ADDR(0x0614)
1775 #define DANUBE_PPE_ENETS_PGCNT DANUBE_PPE_REG_ADDR(0x0615)
1776 #define DANUBE_PPE_ENETS_PGCNT_DSRC_PP32 (0x00020000)
1777 #define DANUBE_PPE_ENETS_PGCNT_DVAL_SHIFT (9)
1778 #define DANUBE_PPE_ENETS_PGCNT_DCMD (0x00000100)
1779 #define DANUBE_PPE_ENETS_PKTCNT DANUBE_PPE_REG_ADDR(0x0616)
1780 #define DANUBE_PPE_ENETS_PKTCNT_DSRC_PP32 (0x00000200)
1781 #define DANUBE_PPE_ENETS_PKTCNT_DCMD (0x00000100)
1782 #define DANUBE_PPE_ENETS_PKTCNT_UPKT (0x000000FF)
1783 #define DANUBE_PPE_ENETS_BUF_CTRL DANUBE_PPE_REG_ADDR(0x0617)
1784 #define DANUBE_PPE_ENETS_COS_CFG DANUBE_PPE_REG_ADDR(0x0618)
1785 #define DANUBE_PPE_ENETS_IGDROP DANUBE_PPE_REG_ADDR(0x0619)
1786 #define DANUBE_PPE_ENETF_DBA DANUBE_PPE_REG_ADDR(0x0630)
1787 #define DANUBE_PPE_ENETF_CBA DANUBE_PPE_REG_ADDR(0x0631)
1788 #define DANUBE_PPE_ENETF_CFG DANUBE_PPE_REG_ADDR(0x0632)
1789 #define DANUBE_PPE_ENETF_PGCNT DANUBE_PPE_REG_ADDR(0x0633)
1790 #define DANUBE_PPE_ENETF_PGCNT_ISRC_PP32 (0x00020000)
1791 #define DANUBE_PPE_ENETF_PGCNT_IVAL_SHIFT (9)
1792 #define DANUBE_PPE_ENETF_PGCNT_ICMD (0x00000100)
1793 #define DANUBE_PPE_ENETF_PKTCNT DANUBE_PPE_REG_ADDR(0x0634)
1794 #define DANUBE_PPE_ENETF_PKTCNT_ISRC_PP32 (0x00000200)
1795 #define DANUBE_PPE_ENETF_PKTCNT_ICMD (0x00000100)
1796 #define DANUBE_PPE_ENETF_PKTCNT_VPKT (0x000000FF)
1797 #define DANUBE_PPE_ENETF_HFCTRL DANUBE_PPE_REG_ADDR(0x0635)
1798 #define DANUBE_PPE_ENETF_TXCTRL DANUBE_PPE_REG_ADDR(0x0636)
1799 #define DANUBE_PPE_ENETF_VLCOS0 DANUBE_PPE_REG_ADDR(0x0638)
1800 #define DANUBE_PPE_ENETF_VLCOS1 DANUBE_PPE_REG_ADDR(0x0639)
1801 #define DANUBE_PPE_ENETF_VLCOS2 DANUBE_PPE_REG_ADDR(0x063A)
1802 #define DANUBE_PPE_ENETF_VLCOS3 DANUBE_PPE_REG_ADDR(0x063B)
1803 #define DANUBE_PPE_ENETF_EGERR DANUBE_PPE_REG_ADDR(0x063C)
1804 #define DANUBE_PPE_ENETF_EGDROP DANUBE_PPE_REG_ADDR(0x063D)
1808 #define DANUBE_PPE_DPLUS_TXDB DANUBE_PPE_REG_ADDR(0x0700)
1809 #define DANUBE_PPE_DPLUS_TXCB DANUBE_PPE_REG_ADDR(0x0701)
1810 #define DANUBE_PPE_DPLUS_TXCFG DANUBE_PPE_REG_ADDR(0x0702)
1811 #define DANUBE_PPE_DPLUS_TXPGCNT DANUBE_PPE_REG_ADDR(0x0703)
1812 #define DANUBE_PPE_DPLUS_RXDB DANUBE_PPE_REG_ADDR(0x0710)
1813 #define DANUBE_PPE_DPLUS_RXCB DANUBE_PPE_REG_ADDR(0x0711)
1814 #define DANUBE_PPE_DPLUS_RXCFG DANUBE_PPE_REG_ADDR(0x0712)
1815 #define DANUBE_PPE_DPLUS_RXPGCNT DANUBE_PPE_REG_ADDR(0x0713)
1819 #define DANUBE_PPE_BMC_CMD3 DANUBE_PPE_REG_ADDR(0x0800)
1820 #define DANUBE_PPE_BMC_CMD2 DANUBE_PPE_REG_ADDR(0x0801)
1821 #define DANUBE_PPE_BMC_CMD1 DANUBE_PPE_REG_ADDR(0x0802)
1822 #define DANUBE_PPE_BMC_CMD0 DANUBE_PPE_REG_ADDR(0x0803)
1823 #define DANUBE_PPE_BMC_CFG0 DANUBE_PPE_REG_ADDR(0x0804)
1824 #define DANUBE_PPE_BMC_CFG1 DANUBE_PPE_REG_ADDR(0x0805)
1825 #define DANUBE_PPE_BMC_POLY0 DANUBE_PPE_REG_ADDR(0x0806)
1826 #define DANUBE_PPE_BMC_POLY1 DANUBE_PPE_REG_ADDR(0x0807)
1827 #define DANUBE_PPE_BMC_CRC0 DANUBE_PPE_REG_ADDR(0x0808)
1828 #define DANUBE_PPE_BMC_CRC1 DANUBE_PPE_REG_ADDR(0x0809)
1832 #define DANUBE_PPE_SLL_CMD1 DANUBE_PPE_REG_ADDR(0x0900)
1833 #define DANUBE_PPE_SLL_CMD0 DANUBE_PPE_REG_ADDR(0x0901)
1834 #define DANUBE_PPE_SLL_KEY0 DANUBE_PPE_REG_ADDR(0x0910)
1835 #define DANUBE_PPE_SLL_KEY1 DANUBE_PPE_REG_ADDR(0x0911)
1836 #define DANUBE_PPE_SLL_KEY2 DANUBE_PPE_REG_ADDR(0x0912)
1837 #define DANUBE_PPE_SLL_KEY3 DANUBE_PPE_REG_ADDR(0x0913)
1838 #define DANUBE_PPE_SLL_KEY4 DANUBE_PPE_REG_ADDR(0x0914)
1839 #define DANUBE_PPE_SLL_KEY5 DANUBE_PPE_REG_ADDR(0x0915)
1840 #define DANUBE_PPE_SLL_RESULT DANUBE_PPE_REG_ADDR(0x0920)
1844 #define DANUBE_PPE_EMA_CMD2 DANUBE_PPE_REG_ADDR(0x0A00)
1845 #define DANUBE_PPE_EMA_CMD1 DANUBE_PPE_REG_ADDR(0x0A01)
1846 #define DANUBE_PPE_EMA_CMD0 DANUBE_PPE_REG_ADDR(0x0A02)
1847 #define DANUBE_PPE_EMA_ISR DANUBE_PPE_REG_ADDR(0x0A04)
1848 #define DANUBE_PPE_EMA_IER DANUBE_PPE_REG_ADDR(0x0A05)
1849 #define DANUBE_PPE_EMA_CFG DANUBE_PPE_REG_ADDR(0x0A06)
1853 #define DANUBE_PPE_UTP_TXCA0 DANUBE_PPE_REG_ADDR(0x0B00)
1854 #define DANUBE_PPE_UTP_TXNA0 DANUBE_PPE_REG_ADDR(0x0B01)
1855 #define DANUBE_PPE_UTP_TXCA1 DANUBE_PPE_REG_ADDR(0x0B02)
1856 #define DANUBE_PPE_UTP_TXNA1 DANUBE_PPE_REG_ADDR(0x0B03)
1857 #define DANUBE_PPE_UTP_RXCA0 DANUBE_PPE_REG_ADDR(0x0B10)
1858 #define DANUBE_PPE_UTP_RXNA0 DANUBE_PPE_REG_ADDR(0x0B11)
1859 #define DANUBE_PPE_UTP_RXCA1 DANUBE_PPE_REG_ADDR(0x0B12)
1860 #define DANUBE_PPE_UTP_RXNA1 DANUBE_PPE_REG_ADDR(0x0B13)
1861 #define DANUBE_PPE_UTP_CFG DANUBE_PPE_REG_ADDR(0x0B20)
1862 #define DANUBE_PPE_UTP_ISR DANUBE_PPE_REG_ADDR(0x0B30)
1863 #define DANUBE_PPE_UTP_IER DANUBE_PPE_REG_ADDR(0x0B31)
1867 #define DANUBE_PPE_QSB_RELOG DANUBE_PPE_REG_ADDR(0x0C00)
1868 #define DANUBE_PPE_QSB_EMIT0 DANUBE_PPE_REG_ADDR(0x0C01)
1869 #define DANUBE_PPE_QSB_EMIT1 DANUBE_PPE_REG_ADDR(0x0C02)
1870 #define DANUBE_PPE_QSB_ICDV DANUBE_PPE_REG_ADDR(0x0C07)
1871 #define DANUBE_PPE_QSB_SBL DANUBE_PPE_REG_ADDR(0x0C09)
1872 #define DANUBE_PPE_QSB_CFG DANUBE_PPE_REG_ADDR(0x0C0A)
1873 #define DANUBE_PPE_QSB_RTM DANUBE_PPE_REG_ADDR(0x0C0B)
1874 #define DANUBE_PPE_QSB_RTD DANUBE_PPE_REG_ADDR(0x0C0C)
1875 #define DANUBE_PPE_QSB_RAMAC DANUBE_PPE_REG_ADDR(0x0C0D)
1876 #define DANUBE_PPE_QSB_ISTAT DANUBE_PPE_REG_ADDR(0x0C0E)
1877 #define DANUBE_PPE_QSB_IMR DANUBE_PPE_REG_ADDR(0x0C0F)
1878 #define DANUBE_PPE_QSB_SRC DANUBE_PPE_REG_ADDR(0x0C10)
1880 * DSP User Registers
1882 #define DANUBE_PPE_DREG_A_VERSION DANUBE_PPE_REG_ADDR(0x0D00)
1883 #define DANUBE_PPE_DREG_A_CFG DANUBE_PPE_REG_ADDR(0x0D01)
1884 #define DANUBE_PPE_DREG_AT_CTRL DANUBE_PPE_REG_ADDR(0x0D02)
1885 #define DANUBE_PPE_DREG_AR_CTRL DANUBE_PPE_REG_ADDR(0x0D08)
1886 #define DANUBE_PPE_DREG_A_UTPCFG DANUBE_PPE_REG_ADDR(0x0D0E)
1887 #define DANUBE_PPE_DREG_A_STATUS DANUBE_PPE_REG_ADDR(0x0D0F)
1888 #define DANUBE_PPE_DREG_AT_CFG0 DANUBE_PPE_REG_ADDR(0x0D20)
1889 #define DANUBE_PPE_DREG_AT_CFG1 DANUBE_PPE_REG_ADDR(0x0D21)
1890 #define DANUBE_PPE_DREG_FB_SIZE0 DANUBE_PPE_REG_ADDR(0x0D22)
1891 #define DANUBE_PPE_DREG_FB_SIZE1 DANUBE_PPE_REG_ADDR(0x0D23)
1892 #define DANUBE_PPE_DREG_AT_CELL0 DANUBE_PPE_REG_ADDR(0x0D24)
1893 #define DANUBE_PPE_DREG_AT_CELL1 DANUBE_PPE_REG_ADDR(0x0D25)
1894 #define DANUBE_PPE_DREG_AT_IDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D26)
1895 #define DANUBE_PPE_DREG_AT_IDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D27)
1896 #define DANUBE_PPE_DREG_AT_IDLE0 DANUBE_PPE_REG_ADDR(0x0D28)
1897 #define DANUBE_PPE_DREG_AT_IDLE1 DANUBE_PPE_REG_ADDR(0x0D29)
1898 #define DANUBE_PPE_DREG_AR_CFG0 DANUBE_PPE_REG_ADDR(0x0D60)
1899 #define DANUBE_PPE_DREG_AR_CFG1 DANUBE_PPE_REG_ADDR(0x0D61)
1900 #define DANUBE_PPE_DREG_AR_FB_START0 DANUBE_PPE_REG_ADDR(0x0D62)
1901 #define DANUBE_PPE_DREG_AR_FB_START1 DANUBE_PPE_REG_ADDR(0x0D63)
1902 #define DANUBE_PPE_DREG_AR_FB_END0 DANUBE_PPE_REG_ADDR(0x0D64)
1903 #define DANUBE_PPE_DREG_AR_FB_END1 DANUBE_PPE_REG_ADDR(0x0D65)
1904 #define DANUBE_PPE_DREG_AR_ATM_STAT0 DANUBE_PPE_REG_ADDR(0x0D66)
1905 #define DANUBE_PPE_DREG_AR_ATM_STAT1 DANUBE_PPE_REG_ADDR(0x0D67)
1906 #define DANUBE_PPE_DREG_AR_CELL0 DANUBE_PPE_REG_ADDR(0x0D68)
1907 #define DANUBE_PPE_DREG_AR_CELL1 DANUBE_PPE_REG_ADDR(0x0D69)
1908 #define DANUBE_PPE_DREG_AR_IDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6A)
1909 #define DANUBE_PPE_DREG_AR_IDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6B)
1910 #define DANUBE_PPE_DREG_AR_AIIDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6C)
1911 #define DANUBE_PPE_DREG_AR_AIIDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6D)
1912 #define DANUBE_PPE_DREG_AR_BE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6E)
1913 #define DANUBE_PPE_DREG_AR_BE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6F)
1914 #define DANUBE_PPE_DREG_AR_HEC_CNT0 DANUBE_PPE_REG_ADDR(0x0D70)
1915 #define DANUBE_PPE_DREG_AR_HEC_CNT1 DANUBE_PPE_REG_ADDR(0x0D71)
1916 #define DANUBE_PPE_DREG_AR_CD_CNT0 DANUBE_PPE_REG_ADDR(0x0D72)
1917 #define DANUBE_PPE_DREG_AR_CD_CNT1 DANUBE_PPE_REG_ADDR(0x0D73)
1918 #define DANUBE_PPE_DREG_AR_IDLE0 DANUBE_PPE_REG_ADDR(0x0D74)
1919 #define DANUBE_PPE_DREG_AR_IDLE1 DANUBE_PPE_REG_ADDR(0x0D75)
1920 #define DANUBE_PPE_DREG_AR_DELIN0 DANUBE_PPE_REG_ADDR(0x0D76)
1921 #define DANUBE_PPE_DREG_AR_DELIN1 DANUBE_PPE_REG_ADDR(0x0D77)
1922 #define DANUBE_PPE_DREG_RESV0 DANUBE_PPE_REG_ADDR(0x0D78)
1923 #define DANUBE_PPE_DREG_RESV1 DANUBE_PPE_REG_ADDR(0x0D79)
1924 #define DANUBE_PPE_DREG_RX_MIB_CMD0 DANUBE_PPE_REG_ADDR(0x0D80)
1925 #define DANUBE_PPE_DREG_RX_MIB_CMD1 DANUBE_PPE_REG_ADDR(0x0D81)
1926 #define DANUBE_PPE_DREG_AR_OVDROP_CNT0 DANUBE_PPE_REG_ADDR(0x0D98)
1927 #define DANUBE_PPE_DREG_AR_OVDROP_CNT1 DANUBE_PPE_REG_ADDR(0x0D99)
1930 /************************************************************************/
1931 /* Module : PPE register address and bits */
1932 /************************************************************************/
1933 #define DANUBE_PPE32_BASE 0xBE180000
1934 #define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4))
1935 #define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4))
1936 #define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4))
1937 #define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4))
1938 #define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4))
1939 #define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4))
1941 /************************************************************************/
1942 /* Module : PPE register address and bits */
1943 /************************************************************************/
1944 #define DANUBE_PPE32_BASE 0xBE180000
1945 #define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4))
1946 #define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4))
1947 #define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4))
1948 #define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4))
1949 #define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4))
1950 #define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4))
1953 * ETOP MDIO Registers
1955 #define ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
1956 #define ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
1957 #define ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
1958 #define ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
1959 #define ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
1960 #define ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
1961 #define ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
1962 #define ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
1963 #define ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
1964 #define ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
1965 #define ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
1966 #define ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
1967 #define ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
1968 #define ENETS_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4)))
1969 #define ENETS_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4)))
1970 #define ENETS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4)))
1971 #define ENETS_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4)))
1972 #define ENETS_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4)))
1973 #define ENETS_BUF_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4)))
1974 #define ENETS_COS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
1975 #define ENETS_IGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
1976 #define ENETS_IGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4)))
1977 #define ENET_MAC_DA0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4)))
1978 #define ENET_MAC_DA1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4)))
1980 #define ENETF_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4)))
1981 #define ENETF_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4)))
1982 #define ENETF_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4)))
1983 #define ENETF_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4)))
1984 #define ENETF_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4)))
1985 #define ENETF_HFCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4)))
1986 #define ENETF_TXCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4)))
1988 #define ENETF_VLCOS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4)))
1989 #define ENETF_VLCOS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4)))
1990 #define ENETF_VLCOS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4)))
1991 #define ENETF_VLCOS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4)))
1992 #define ENETF_EGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4)))
1993 #define ENETF_EGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4)))
1997 * ETOP MDIO Registers
1999 #define DANUBE_PPE32_ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
2000 #define DANUBE_PPE32_ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
2001 #define DANUBE_PPE32_ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
2002 #define DANUBE_PPE32_ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
2003 #define DANUBE_PPE32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
2004 #define DANUBE_PPE32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
2005 #define DANUBE_PPE32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
2006 #define DANUBE_PPE32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
2007 #define DANUBE_PPE32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
2008 #define DANUBE_PPE32_ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
2009 #define DANUBE_PPE32_ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
2010 #define DANUBE_PPE32_ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
2014 #define DANUBE_PPE32_ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
2015 #define DANUBE_PPE32_ENET_IG_PKTDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
2016 #define DANUBE_PPE32_ENET_CoS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
2018 /*********LED register definition****************/
2020 #define DANUBE_LED 0xBE100BB0
2021 #define DANUBE_LED_CON0 ((volatile u32*)(DANUBE_LED + 0x0000))
2022 #define DANUBE_LED_CON1 ((volatile u32*)(DANUBE_LED + 0x0004))
2023 #define DANUBE_LED_CPU0 ((volatile u32*)(DANUBE_LED + 0x0008))
2024 #define DANUBE_LED_CPU1 ((volatile u32*)(DANUBE_LED + 0x000C))
2025 #define DANUBE_LED_AR ((volatile u32*)(DANUBE_LED + 0x0010))
2030 /***********************************************************************/
2031 #define DANUBE_REG32(addr) *((volatile u32 *)(addr))
2032 /***********************************************************************/
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