package/uboot-ifxmips/files/include/configs/danube.h

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * This file contains the configuration parameters for the danube board.
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #include <configs/ifx_cfg.h>
  32
  33 #define  USE_REFERENCE_BOARD
  34 //#define   USE_EVALUATION_BOARD
  35
  36 #define   DANUBE_BOOT_FROM_EBU
  37 #define   DANUBE_USE_DDR_RAM
  38
  39 #ifdef DANUBE_USE_DDR_RAM
  40 //#define  DANUBE_DDR_RAM_111M
  41 #define DANUBE_DDR_RAM_166M
  42 //#define PROMOSDDR400
  43 //#define DDR_SAMSUNG_166M
  44 //#define DDR_PSC_166M
  45 //#define DANUBE_DDR_RAM_133M
  46 #define DANUBE_DDR_RAM_SIZE     32      /* 32M DDR-DRAM for reference board */
  47 #endif
  48 #define CLK_OUT2_25MHZ
  49 #define CONFIG_MIPS32           1       /* MIPS 4Kc CPU core    */
  50 #define CONFIG_DANUBE           1       /* on a danube Board    */
  51 #define RAM_SIZE                0x2000000 /*32M ram*/
  52
  53 #define CPU_CLOCK_RATE          235000000   /* 235 MHz clock for the MIPS core */
  54
  55 #define INFINEON_EBU_BOOTCFG    0x688C688C      /* CMULT = 8 for 150 MHz */
  56
  57 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  58
  59 #define CONFIG_BAUDRATE         115200
  60
  61 #define DEBUG_PARSER            2
  62
  63 /* valid baudrates */
  64 #define CFG_BAUDRATE_TABLE      { 300, 9600, 19200, 38400, 57600, 115200 }
  65
  66 #ifndef CFG_HEAD_CODE
  67 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  68 #endif
  69
  70 #define CONFIG_PREBOOT  "echo;" \
  71         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  72         "echo"
  73
  74 #undef  CONFIG_BOOTARGS
  75 /* by MarsLin 2005/05/10, to support different hardware configuations */
  76 //#define CONFIG_EXTRA_ENV_SETTINGS     <configs/ifx_extra_env.h>
  77 #define CONFIG_EXTRA_ENV_SETTINGS \
  78         "ethaddr=11:22:33:44:55:66\0" \
  79         "serverip=192.168.45.100\0" \
  80         "ipaddr=192.168.45.108\0"  \
  81         "update_uboot=tftp 0x80500000 u-boot.ifx;era 1:0-10; cp.b 0x80500000 0xb0000000 0x10000\0" \
  82         "update_openwrt=tftp 0x80500000 openwrt-ifxmips-squashfs.image; era 1:10-120; cp.b 0x80500000 0xb0030000 0x300000\0" \
  83         "bootargs=console=ttyS1,115200 rootfstype=squashfs,jffs2 init=/etc/preinit\0"
  84
  85 #define CONFIG_BOOTCOMMAND      "bootm 0xb0030000"
  86
  87 #define CONFIG_COMMANDS_YES     (CONFIG_CMD_DFL | \
  88                                  CFG_CMD_ASKENV         | \
  89                                  CFG_CMD_DHRYSTONE      | \
  90                                  CFG_CMD_NET    )
  91
  92 #define CONFIG_COMMANDS_NO      (CFG_CMD_NFS            | \
  93                                  CFG_CMD_FPGA           | \
  94                                  CFG_CMD_IMLS           | \
  95                                  CFG_CMD_ITEST          | \
  96                                  CFG_CMD_XING           | \
  97                                  CFG_CMD_IMI            | \
  98                                  CFG_CMD_BMP            | \
  99                                  CFG_CMD_BOOTD          | \
 100                                  CFG_CMD_CONSOLE        | \
 101                                  CFG_CMD_LOADS          | \
 102                                  CFG_CMD_LOADB          )
 103
 104 #define CONFIG_COMMANDS         (CONFIG_COMMANDS_YES & ~CONFIG_COMMANDS_NO)
 105
 106 #if 0
 107                                  CFG_CMD_DHCP
 108                                  CFG_CMD_ELF
 109                                  CFG_CMD_NAND
 110 #endif
 111
 112 #include <cmd_confdefs.h>
 113
 114 /*
 115  * Miscellaneous configurable options
 116  */
 117 #define CFG_LONGHELP                            /* undef to save memory      */
 118 #define CFG_PROMPT              "DANUBE # "     /* Monitor Command Prompt    */
 119 #define CFG_CBSIZE              256             /* Console I/O Buffer Size   */
 120 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
 121 #define CFG_MAXARGS             16              /* max number of command args*/
 122
 123 #define CFG_MALLOC_LEN          128*1024
 124
 125 #define CFG_BOOTPARAMS_LEN      128*1024
 126
 127 #define CFG_HZ       (CPU_CLOCK_RATE / 2)
 128
 129 #define CFG_LOAD_ADDR           0x80100000      /* default load address */
 130
 131 #define CFG_MEMTEST_START       0x80100000
 132 #define CFG_MEMTEST_END         0x80400000
 133
 134 /*-----------------------------------------------------------------------
 135  * FLASH and environment organization
 136  */
 137 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks */
 138 #define CFG_MAX_FLASH_SECT      (135)   /* max number of sectors on one chip */
 139
 140 #define PHYS_FLASH_1            0xB0000000 /* Flash Bank #1 */
 141 #define PHYS_FLASH_2            0xB4000000 /* Flash Bank #2 */
 142
 143 #define BOOTSTRAP_TEXT_BASE 0xb0000000
 144
 145 /* The following #defines are needed to get flash environment right */
 146 #define CFG_MONITOR_BASE        UBOOT_RAM_TEXT_BASE     /* board/danube/config.mk. = 0xA0800000 */
 147 #define BOOTSTRAP_CFG_MONITOR_BASE      BOOTSTRAP_TEXT_BASE     /* board/danube/config.mk. = 0xA0800000 */
 148 #define CFG_MONITOR_LEN         (256 << 10)
 149
 150 #define CFG_INIT_SP_OFFSET      0x400000
 151
 152 #define CFG_FLASH_BASE          PHYS_FLASH_1
 153
 154 /* timeout values are in ticks */
 155 #define CFG_FLASH_ERASE_TOUT    (20 * CFG_HZ) /* Timeout for Flash Erase */
 156 #define CFG_FLASH_WRITE_TOUT    (20 * CFG_HZ) /* Timeout for Flash Write */
 157
 158 #define CFG_ENV_IS_IN_FLASH     1
 159 //#define CFG_ENV_IS_NOWHERE    1
 160 //#define CFG_ENV_IS_IN_NVRAM   1
 161 /* Address and size of Primary Environment Sector       */
 162 #define CFG_ENV_ADDR            IFX_CFG_FLASH_UBOOT_CFG_START_ADDR
 163 #define CFG_ENV_SIZE            IFX_CFG_FLASH_UBOOT_CFG_SIZE
 164
 165 #define CONFIG_FLASH_16BIT
 166
 167 #define CONFIG_NR_DRAM_BANKS    1
 168
 169 #define CONFIG_DANUBE_SWITCH
 170 #define CONFIG_NET_MULTI
 171 #define CONFIG_ENV_OVERWRITE
 172
 173 #define EXCEPTION_BASE  0x200
 174
 175 /**
 176  *\brief definition for nand
 177  *
 178  */
 179 #define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
 180 #define NAND_ChipID_UNKNOWN     0x00
 181 #define SECTORSIZE 512
 182 #define NAND_MAX_FLOORS 1
 183 #define NAND_MAX_CHIPS 1
 184
 185
 186 #define ADDR_COLUMN 1
 187 #define ADDR_PAGE 2
 188 #define ADDR_COLUMN_PAGE 3
 189
 190
 191 #define AT91_SMART_MEDIA_ALE (1 << 22)  /* our ALE is AD22 */
 192 #define AT91_SMART_MEDIA_CLE (1 << 21)  /* our CLE is AD21 */
 193
 194 #define NAND_DISABLE_CE(nand)
 195 #define NAND_ENABLE_CE(nand)
 196 #define NAND_WAIT_READY(nand)
 197 #define WRITE_NAND_COMMAND(d, adr)
 198 #define WRITE_NAND_ADDRESS(d, adr)
 199 #define WRITE_NAND(d, adr)
 200 #define READ_NAND(adr)
 201 /* the following are NOP's in our implementation */
 202 #define NAND_CTL_CLRALE(nandptr)
 203 #define NAND_CTL_SETALE(nandptr)
 204 #define NAND_CTL_CLRCLE(nandptr)
 205 #define NAND_CTL_SETCLE(nandptr)
 206
 207
 208
 209 #define NAND_BASE_ADDRESS  0xB4000000
 210
 211 #define NAND_WRITE(addr, val)     *((u8*)(NAND_BASE_ADDRESS | (addr))) = val;while((*EBU_NAND_WAIT & 0x08) == 0);
 212 #define NAND_READ(addr, val)      val = *((u8*)(NAND_BASE_ADDRESS | (addr)))
 213 #define NAND_CE_SET
 214 #define NAND_CE_CLEAR
 215 #define NAND_READY       ( ((*EBU_NAND_WAIT)&0x07) == 7)
 216 #define NAND_READY_CLEAR  *EBU_NAND_WAIT = 0;
 217 #define WRITE_CMD    0x18
 218 #define WRITE_ADDR   0x14
 219 #define WRITE_LADDR  0x10
 220 #define WRITE_DATA  0x10
 221 #define READ_DATA    0x10
 222 #define READ_LDATA   0x00
 223 #define ACCESS_WAIT
 224 #define IFX_ATC_NAND 0xc176
 225 #define IFX_BTC_NAND 0xc166
 226 #define ST_512WB2_NAND 0x2076
 227
 228 #define NAND_OK              0x00000000    /* Bootstrap succesful, start address in BOOT_RVEC */
 229 #define NAND_ERR             0x80000000
 230 #define NAND_ACC_TIMEOUT     (NAND_ERR | 0x00000001)
 231 #define NAND_ACC_ERR         (NAND_ERR | 0x00000002)
 232
 233
 234 /*****************************************************************************
 235  * DANUBE
 236  *****************************************************************************/
 237 /* lock cache for C program stack */
 238 /* points to ROM */
 239 /* stack size is 16K */
 240 #define LOCK_DCACHE_ADDR        0x9FC00000
 241 #define LOCK_DCACHE_SIZE        0x1000
 242
 243 /*
 244  * Memory layout
 245  */
 246 #define CFG_SDRAM_BASE          0x80000000
 247 #define CFG_SDRAM_BASE_UNCACHE  0xA0000000
 248 #define CFG_CACHE_LOCK_SIZE  LOCK_DCACHE_SIZE
 249
 250 /*
 251  * Cache settings
 252  */
 253 #define CFG_CACHE_SIZE   16384
 254 #define CFG_CACHE_LINES  32
 255 #define CFG_CACHE_WAYS   4
 256 #define CFG_CACHE_SETS   128
 257
 258 #define CFG_ICACHE_SIZE   CFG_CACHE_SIZE
 259 #define CFG_DCACHE_SIZE   CFG_CACHE_SIZE
 260 #define CFG_CACHELINE_SIZE  CFG_CACHE_LINES
 261
 262 #endif  /* __CONFIG_H */