target/linux/adm8668/files/arch/mips/adm8668/net.h

   1 /*
   2  * originally drivers/net/tulip/tulip.h
   3  *   Copyright 2000,2001  The Linux Kernel Team
   4  *   Written/copyright 1994-2001 by Donald Becker.
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #ifndef __NET_TULIP_H__
  12 #define __NET_TULIP_H__
  13
  14 #include <linux/module.h>
  15 #include <linux/slab.h>
  16 #include <linux/init.h>
  17 #include <linux/mii.h>
  18 #include <linux/crc32.h>
  19 #include <linux/kernel.h>
  20 #include <linux/types.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/timer.h>
  25 #include <linux/delay.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/platform_device.h>
  28 #include <asm/unaligned.h>
  29 #include <asm/uaccess.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32
  33 /* undefine, or define to various debugging levels (>4 == obscene levels) */
  34 #define TULIP_DEBUG 1
  35 #define VALID_INTR      0x0001a451
  36 #define ADM8668_WAN_IRQ         8
  37 #define ADM8668_LAN_IRQ         7
  38 #define ADM8668_WAN_MACADDR     0xb00205ac
  39 #define ADM8668_LAN_MACADDR     0xb0020404
  40
  41 /* Offsets to the Command and Status Registers, "CSRs".  All accesses
  42    must be longword instructions and quadword aligned. */
  43 enum tulip_offsets {
  44         CSR0 = 0,
  45         CSR1 = 0x08,
  46         CSR2 = 0x10,
  47         CSR3 = 0x18,
  48         CSR4 = 0x20,
  49         CSR5 = 0x28,
  50         CSR6 = 0x30,
  51         CSR7 = 0x38,
  52         CSR8 = 0x40,
  53         CSR9 = 0x48,
  54         CSR10 = 0x50,
  55         CSR11 = 0x58,
  56         CSR12 = 0x60,
  57         CSR13 = 0x68,
  58         CSR14 = 0x70,
  59         CSR15 = 0x78,
  60         CSR18 = 0x88,
  61         CSR19 = 0x8c,
  62         CSR20 = 0x90,
  63         CSR27 = 0xAC,
  64         CSR28 = 0xB0,
  65 };
  66
  67 #define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
  68
  69 /* The bits in the CSR5 status registers, mostly interrupt sources. */
  70 enum status_bits {
  71         TimerInt = 0x800,
  72         SystemError = 0x2000,
  73         TPLnkFail = 0x1000,
  74         TPLnkPass = 0x10,
  75         NormalIntr = 0x10000,
  76         AbnormalIntr = 0x8000,
  77         RxJabber = 0x200,
  78         RxDied = 0x100,
  79         RxNoBuf = 0x80,
  80         RxIntr = 0x40,
  81         TxFIFOUnderflow = 0x20,
  82         RxErrIntr = 0x10,
  83         TxJabber = 0x08,
  84         TxNoBuf = 0x04,
  85         TxDied = 0x02,
  86         TxIntr = 0x01,
  87 };
  88
  89 /* bit mask for CSR5 TX/RX process state */
  90 #define CSR5_TS 0x00700000
  91 #define CSR5_RS 0x000e0000
  92
  93 enum tulip_mode_bits {
  94         TxThreshold             = (1 << 22),
  95         FullDuplex              = (1 << 9),
  96         TxOn                    = 0x2000,
  97         AcceptBroadcast         = 0x0100,
  98         AcceptAllMulticast      = 0x0080,
  99         AcceptAllPhys           = 0x0040,
 100         AcceptRunt              = 0x0008,
 101         RxOn                    = 0x0002,
 102         RxTx                    = (TxOn | RxOn),
 103 };
 104
 105 /* The Tulip Rx and Tx buffer descriptors. */
 106 struct tulip_rx_desc {
 107         __le32 status;
 108         __le32 length;
 109         __le32 buffer1;
 110         __le32 buffer2;
 111 };
 112
 113 struct tulip_tx_desc {
 114         __le32 status;
 115         __le32 length;
 116         __le32 buffer1;
 117         __le32 buffer2;         /* We use only buffer 1.  */
 118 };
 119
 120 enum desc_status_bits {
 121         DescOwned    = 0x80000000,
 122         DescWholePkt = 0x60000000,
 123         DescEndPkt   = 0x40000000,
 124         DescStartPkt = 0x20000000,
 125         DescEndRing  = 0x02000000,
 126         DescUseLink  = 0x01000000,
 127
 128         /*
 129          * Error summary flag is logical or of 'CRC Error', 'Collision Seen',
 130          * 'Frame Too Long', 'Runt' and 'Descriptor Error' flags generated
 131          * within tulip chip.
 132          */
 133         RxDescErrorSummary = 0x8000,
 134         RxDescCRCError = 0x0002,
 135         RxDescCollisionSeen = 0x0040,
 136
 137         /*
 138          * 'Frame Too Long' flag is set if packet length including CRC exceeds
 139          * 1518.  However, a full sized VLAN tagged frame is 1522 bytes
 140          * including CRC.
 141          *
 142          * The tulip chip does not block oversized frames, and if this flag is
 143          * set on a receive descriptor it does not indicate the frame has been
 144          * truncated.  The receive descriptor also includes the actual length.
 145          * Therefore we can safety ignore this flag and check the length
 146          * ourselves.
 147          */
 148         RxDescFrameTooLong = 0x0080,
 149         RxDescRunt = 0x0800,
 150         RxDescDescErr = 0x4000,
 151         RxWholePkt   = 0x00000300,
 152         /*
 153          * Top three bits of 14 bit frame length (status bits 27-29) should
 154          * never be set as that would make frame over 2047 bytes. The Receive
 155          * Watchdog flag (bit 4) may indicate the length is over 2048 and the
 156          * length field is invalid.
 157          */
 158         RxLengthOver2047 = 0x38000010
 159 };
 160
 161 /* Keep the ring sizes a power of two for efficiency.
 162    Making the Tx ring too large decreases the effectiveness of channel
 163    bonding and packet priority.
 164    There are no ill effects from too-large receive rings. */
 165
 166 #define TX_RING_SIZE    32
 167 #define RX_RING_SIZE    128
 168
 169 /* The receiver on the DC21143 rev 65 can fail to close the last
 170  * receive descriptor in certain circumstances (see errata) when
 171  * using MWI. This can only occur if the receive buffer ends on
 172  * a cache line boundary, so the "+ 4" below ensures it doesn't.
 173  */
 174 #define PKT_BUF_SZ      (1536 + 4)      /* Size of each temporary Rx buffer. */
 175
 176 /* Ring-wrap flag in length field, use for last ring entry.
 177         0x01000000 means chain on buffer2 address,
 178         0x02000000 means use the ring start address in CSR2/3.
 179    Note: Some work-alike chips do not function correctly in chained mode.
 180    The ASIX chip works only in chained mode.
 181    Thus we indicates ring mode, but always write the 'next' field for
 182    chained mode as well.
 183 */
 184 #define DESC_RING_WRAP 0x02000000
 185
 186 struct ring_info {
 187         struct sk_buff  *skb;
 188         dma_addr_t      mapping;
 189 };
 190
 191 struct tulip_private {
 192         struct tulip_rx_desc *rx_ring;
 193         struct tulip_tx_desc *tx_ring;
 194         dma_addr_t rx_ring_dma;
 195         dma_addr_t tx_ring_dma;
 196         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 197         struct ring_info tx_buffers[TX_RING_SIZE];
 198         /* The addresses of receive-in-place skbuffs. */
 199         struct ring_info rx_buffers[RX_RING_SIZE];
 200         struct napi_struct napi;
 201         struct net_device_stats stats;
 202         struct timer_list oom_timer;    /* Out of memory timer. */
 203         u32 mc_filter[2];
 204         spinlock_t lock;
 205         unsigned int cur_rx, cur_tx;    /* The next free ring entry */
 206         unsigned int dirty_rx, dirty_tx;        /* The ring entries to be free()ed. */
 207         unsigned int csr0;      /* CSR0 setting. */
 208         unsigned int csr6;      /* Current CSR6 control settings. */
 209         void (*link_change) (struct net_device * dev, int csr5);
 210         struct platform_device *pdev;
 211         unsigned long nir;
 212         void __iomem *base_addr;
 213         int pad0;               /* Used for 8-byte alignment */
 214         struct net_device *dev;
 215 };
 216
 217
 218 /* interrupt.c */
 219 irqreturn_t tulip_interrupt(int irq, void *dev_instance);
 220 int tulip_refill_rx(struct net_device *dev);
 221 int tulip_poll(struct napi_struct *napi, int budget);
 222
 223 /* tulip_core.c */
 224 extern int tulip_debug;
 225 void oom_timer(unsigned long data);
 226
 227 static inline void tulip_start_rxtx(struct tulip_private *tp)
 228 {
 229         void __iomem *ioaddr = tp->base_addr;
 230         iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
 231         barrier();
 232         (void) ioread32(ioaddr + CSR6); /* mmio sync */
 233 }
 234
 235 static inline void tulip_stop_rxtx(struct tulip_private *tp)
 236 {
 237         void __iomem *ioaddr = tp->base_addr;
 238         u32 csr6 = ioread32(ioaddr + CSR6);
 239
 240         if (csr6 & RxTx) {
 241                 unsigned i=1300/10;
 242                 iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
 243                 barrier();
 244                 /* wait until in-flight frame completes.
 245                  * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
 246                  * Typically expect this loop to end in < 50 us on 100BT.
 247                  */
 248                 while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
 249                         udelay(10);
 250
 251                 if (!i)
 252                         printk(KERN_DEBUG "fixme: tulip_stop_rxtx() failed"
 253                                         " (CSR5 0x%x CSR6 0x%x)\n",
 254                                         ioread32(ioaddr + CSR5),
 255                                         ioread32(ioaddr + CSR6));
 256         }
 257 }
 258
 259 static inline void tulip_restart_rxtx(struct tulip_private *tp)
 260 {
 261         tulip_stop_rxtx(tp);
 262         udelay(5);
 263         tulip_start_rxtx(tp);
 264 }
 265
 266 static inline void tulip_tx_timeout_complete(struct tulip_private *tp, void __iomem *ioaddr)
 267 {
 268         /* Stop and restart the chip's Tx processes. */
 269         tulip_restart_rxtx(tp);
 270         /* Trigger an immediate transmit demand. */
 271         iowrite32(0, ioaddr + CSR1);
 272
 273         tp->stats.tx_errors++;
 274 }
 275
 276 #endif /* __NET_TULIP_H__ */