f3ebdbfbdfe087757bacbd04916233167b777aa0
[openwrt/svn-archive/archive.git] / target / linux / amazon / files / arch / mips / amazon / setup.c
1 /*
2 * Copyright (C) 2004 Peng Liu <peng.liu@infineon.com>
3 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
4 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
19 *
20 */
21
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/module.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27
28 #include <asm/reboot.h>
29 #include <asm/system.h>
30 #include <asm/time.h>
31 #include <asm/cpu.h>
32 #include <asm/bootinfo.h>
33 #include <asm/irq.h>
34 #include <asm/mipsregs.h>
35 #include <asm/amazon/amazon.h>
36 #include <asm/amazon/irq.h>
37 #include <asm/amazon/model.h>
38
39 static unsigned int r4k_offset;
40 static unsigned int r4k_cur;
41
42 /* required in arch/mips/kernel/kspd.c */
43 unsigned long cpu_khz;
44
45 static void amazon_reboot_setup(void);
46
47 /* the CPU clock rate - lifted from u-boot */
48 unsigned int amazon_get_cpu_hz(void)
49 {
50 /*-----------------------------------*/
51 /**CGU CPU Clock Reduction Register***/
52 /*-----------------------------------*/
53 switch(amazon_readl(AMAZON_CGU_CPUCRD) & 0x3){
54 case 0:
55 /*divider ration 1/1, 235 MHz clock */
56 return 235000000;
57 case 1:
58 /*divider ration 2/3, 235 MHz clock, clock not accurate, here */
59 return 150000000;
60 case 2:
61 /*divider ration 1/2, 235 MHz clock */
62 return 117500000;
63 default:
64 /*divider ration 1/4, 235 MHz clock */
65 return 58750000;
66 }
67 }
68
69 /* the FPI clock rate - lifted from u-boot */
70 unsigned int amazon_get_fpi_hz(void)
71 {
72 unsigned int clkCPU;
73 clkCPU = amazon_get_cpu_hz();
74
75 /*-------------------------------------*/
76 /***CGU Clock Divider Select Register***/
77 /*-------------------------------------*/
78 switch (amazon_readl(AMAZON_CGU_DIV) & 0x3)
79 {
80 case 1:
81 return clkCPU >> 1;
82 case 2:
83 return clkCPU >> 2;
84 default:
85 return clkCPU;
86 /* '11' is reserved */
87 }
88 }
89
90 /* this doesn't really belong here, but it's a convenient location */
91 unsigned int amazon_get_cpu_ver(void)
92 {
93 static unsigned int cpu_ver = 0;
94 if (cpu_ver == 0)
95 cpu_ver = amazon_readl(AMAZON_MCD_CHIPID) & 0xFFFFF000;
96 return cpu_ver;
97 }
98
99 static inline u32 amazon_get_counter_resolution(void)
100 {
101 u32 res;
102 __asm__ __volatile__(
103 ".set push\n"
104 ".set mips32r2\n"
105 ".set noreorder\n"
106 "rdhwr %0, $3\n"
107 "ehb\n"
108 ".set pop\n"
109 : "=&r" (res)
110 : /* no input */
111 : "memory");
112 instruction_hazard();
113 return res;
114 }
115
116 void __init plat_time_init(void)
117 {
118 mips_hpt_frequency = amazon_get_cpu_hz() / amazon_get_counter_resolution();
119 r4k_offset = mips_hpt_frequency / HZ;
120 printk("mips_hpt_frequency:%d\n", mips_hpt_frequency);
121 printk("r4k_offset: %08x(%d)\n", r4k_offset, r4k_offset);
122
123 r4k_cur = (read_c0_count() + r4k_offset);
124 write_c0_compare(r4k_cur);
125
126 /* enable the timer in the PMU */
127 amazon_writel(amazon_readl(AMAZON_PMU_PWDCR)| AMAZON_PMU_PWDCR_GPT|AMAZON_PMU_PWDCR_FPI, AMAZON_PMU_PWDCR);
128
129 /* setup the GPTU for timer tick f_fpi == f_gptu*/
130 amazon_writel(0x0100, AMAZON_GPTU_CLC);
131 amazon_writel(0xffff, AMAZON_GPTU_CAPREL);
132 amazon_writel(0x80C0, AMAZON_GPTU_T6CON);
133 }
134
135 void __init plat_mem_setup(void)
136 {
137 u32 chipid = 0;
138 u32 part_no = 0;
139
140 chipid = amazon_readl(AMAZON_MCD_CHIPID);
141 part_no = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid);
142
143 if(part_no == AMAZON_CHIPID_YANGTSE){
144 printk("Yangtse Version\n");
145 } else if (part_no == AMAZON_CHIPID_STANDARD) {
146 printk(SYSTEM_MODEL_NAME "\n");
147 } else {
148 printk("unknown version %8x\n",part_no);
149 }
150
151 amazon_reboot_setup();
152
153 //stop reset TPE and DFE
154 amazon_writel(0, AMAZON_RST_REQ);
155 //clock
156 amazon_writel(0x3fff, AMAZON_PMU_PWDCR);
157 //reenable trace capability
158 part_no = readl(AMAZON_BCU_ECON);
159
160 ioport_resource.start = IOPORT_RESOURCE_START;
161 ioport_resource.end = IOPORT_RESOURCE_END;
162 iomem_resource.start = IOMEM_RESOURCE_START;
163 iomem_resource.end = IOMEM_RESOURCE_END;
164 }
165
166 static void amazon_machine_restart(char *command)
167 {
168 local_irq_disable();
169 amazon_writel(AMAZON_RST_ALL, AMAZON_RST_REQ);
170 for (;;) ;
171 }
172
173 static void amazon_machine_halt(void)
174 {
175 printk(KERN_NOTICE "System halted.\n");
176 local_irq_disable();
177 for (;;) ;
178 }
179
180 static void amazon_machine_power_off(void)
181 {
182 printk(KERN_NOTICE "Please turn off the power now.\n");
183 local_irq_disable();
184 for (;;) ;
185 }
186
187 static void amazon_reboot_setup(void)
188 {
189 _machine_restart = amazon_machine_restart;
190 _machine_halt = amazon_machine_halt;
191 pm_power_off = amazon_machine_power_off;
192 }