target/linux/ar7/files/arch/mips/ar7/vlynq-pci.c

   1 /*
   2  * $Id$
   3  *
   4  * Copyright (C) 2006, 2007 OpenWrt.org
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/pci.h>
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <linux/irq.h>
  26 #include <asm/ar7/vlynq.h>
  27
  28 #define VLYNQ_PCI_SLOTS 2
  29
  30 struct vlynq_reg_config {
  31         u32 offset;
  32         u32 value;
  33 };
  34
  35 struct vlynq_pci_config {
  36         u32 chip_id;
  37         char name[32];
  38         struct vlynq_mapping rx_mapping[4];
  39         int irq;
  40         int irq_type;
  41         u32 chip;
  42         u32 class;
  43         int num_regs;
  44         struct vlynq_reg_config regs[10];
  45 };
  46
  47 struct vlynq_pci_private {
  48         u32 latency;
  49         u32 cache_line;
  50         u32 command;
  51         u32 sz_mask;
  52         struct vlynq_pci_config *config;
  53 };
  54
  55 static struct vlynq_pci_config known_devices[] = {
  56         {
  57                 .chip_id = 0x00000009, .name = "TI TNETW1130",
  58                 .rx_mapping = {
  59                         { .size = 0x22000, .offset = 0xf0000000 },
  60                         { .size = 0x40000, .offset = 0xc0000000 },
  61                         { .size = 0x0, .offset = 0x0 },
  62                         { .size = 0x0, .offset = 0x0 },
  63                 },
  64                 .irq = 0, .chip = 0x9066104c,
  65                 .irq_type = IRQ_TYPE_EDGE_RISING,
  66                 .class = PCI_CLASS_NETWORK_OTHER,
  67                 .num_regs = 5,
  68                 .regs = {
  69                         {
  70                                 .offset = 0x790,
  71                                 .value = (0xd0000000 - PHYS_OFFSET)
  72                         },
  73                         {
  74                                 .offset = 0x794,
  75                                 .value = (0xd0000000 - PHYS_OFFSET)
  76                         },
  77                         { .offset = 0x740, .value = 0 },
  78                         { .offset = 0x744, .value = 0x00010000 },
  79                         { .offset = 0x764, .value = 0x00010000 },
  80                 },
  81         },
  82         {
  83                 .chip_id = 0x00000029, .name = "TI TNETW1350",
  84                 .rx_mapping = {
  85                         { .size = 0x100000, .offset = 0x00300000 },
  86                         { .size = 0x80000, .offset = 0x00000000 },
  87                         { .size = 0x0, .offset = 0x0 },
  88                         { .size = 0x0, .offset = 0x0 },
  89                 },
  90                 .irq = 0, .chip = 0x9066104c,
  91                 .irq_type = IRQ_TYPE_EDGE_RISING,
  92                 .class = PCI_CLASS_NETWORK_OTHER,
  93                 .num_regs = 5,
  94                 .regs = {
  95                         {
  96                                 .offset = 0x790,
  97                                 .value = (0x60000000 - PHYS_OFFSET)
  98                         },
  99                         {
 100                                 .offset = 0x794,
 101                                 .value = (0x60000000 - PHYS_OFFSET)
 102                         },
 103                         { .offset = 0x740, .value = 0 },
 104                         { .offset = 0x744, .value = 0x00010000 },
 105                         { .offset = 0x764, .value = 0x00010000 },
 106                 },
 107         },
 108 };
 109
 110 static struct vlynq_device *slots[VLYNQ_PCI_SLOTS] = { NULL, };
 111
 112 static struct resource vlynq_io_resource = {
 113         .start  = 0x00000000,
 114         .end    = 0x00000000,
 115         .name   = "pci IO space",
 116         .flags  = IORESOURCE_IO
 117 };
 118
 119 static struct resource vlynq_mem_resource = {
 120         .start  = 0x00000000,
 121         .end    = 0x00000000,
 122         .name   = "pci memory space",
 123         .flags  = IORESOURCE_MEM
 124 };
 125
 126 static inline u32 vlynq_get_mapped(struct vlynq_device *dev, int res)
 127 {
 128         int i;
 129         struct vlynq_pci_private *priv = dev->priv;
 130         u32 ret = dev->mem_start;
 131         if (!priv->config->rx_mapping[res].size) return 0;
 132         for (i = 0; i < res; i++)
 133                 ret += priv->config->rx_mapping[i].size;
 134
 135         return ret;
 136 }
 137
 138 static inline u32 vlynq_read(u32 val, int size) {
 139         switch (size) {
 140         case 1:
 141                 return *(u8 *)&val;
 142         case 2:
 143                 return *(u16 *)&val;
 144         }
 145         return val;
 146 }
 147
 148 static int vlynq_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
 149 {
 150         struct vlynq_device *dev;
 151         struct vlynq_pci_private *priv;
 152         int resno, slot = PCI_SLOT(devfn);
 153
 154         if ((size == 2) && (where & 1))
 155                 return PCIBIOS_BAD_REGISTER_NUMBER;
 156         else if ((size == 4) && (where & 3))
 157                 return PCIBIOS_BAD_REGISTER_NUMBER;
 158
 159         if (slot >= VLYNQ_PCI_SLOTS)
 160                 return PCIBIOS_DEVICE_NOT_FOUND;
 161
 162         dev = slots[slot];
 163
 164         if (!dev || (PCI_FUNC(devfn) > 0))
 165                 return PCIBIOS_DEVICE_NOT_FOUND;
 166
 167         priv = dev->priv;
 168
 169         switch (where) {
 170         case PCI_VENDOR_ID:
 171                 *val = vlynq_read(priv->config->chip, size);
 172                 break;
 173         case PCI_DEVICE_ID:
 174                 *val = priv->config->chip & 0xffff;
 175         case PCI_COMMAND:
 176                 *val = priv->command;
 177         case PCI_STATUS:
 178 /*              *val = PCI_STATUS_CAP_LIST;*/
 179                 *val = 0;
 180                 break;
 181         case PCI_CLASS_REVISION:
 182                 *val = priv->config->class;
 183                 break;
 184         case PCI_LATENCY_TIMER:
 185                 *val = priv->latency;
 186                 break;
 187         case PCI_HEADER_TYPE:
 188                 *val = PCI_HEADER_TYPE_NORMAL;
 189                 break;
 190         case PCI_CACHE_LINE_SIZE:
 191                 *val = priv->cache_line;
 192                 break;
 193         case PCI_BASE_ADDRESS_0:
 194         case PCI_BASE_ADDRESS_1:
 195         case PCI_BASE_ADDRESS_2:
 196         case PCI_BASE_ADDRESS_3:
 197                 resno = (where - PCI_BASE_ADDRESS_0) >> 2;
 198                 if (priv->sz_mask & (1 << resno)) {
 199                         priv->sz_mask &= ~(1 << resno);
 200                         *val = priv->config->rx_mapping[resno].size;
 201                 } else {
 202                         *val = vlynq_get_mapped(dev, resno);
 203                 }
 204                 break;
 205         case PCI_BASE_ADDRESS_4:
 206         case PCI_BASE_ADDRESS_5:
 207         case PCI_SUBSYSTEM_VENDOR_ID:
 208         case PCI_SUBSYSTEM_ID:
 209         case PCI_ROM_ADDRESS:
 210         case PCI_INTERRUPT_LINE:
 211         case PCI_CARDBUS_CIS:
 212         case PCI_CAPABILITY_LIST:
 213                 *val = 0;
 214                 break;
 215         case PCI_INTERRUPT_PIN:
 216                 *val = 1;
 217                 break;
 218         default:
 219                 printk("%s: Read of unknown register 0x%x (size %d)\n",
 220                        dev->dev.bus_id, where, size);
 221                 return PCIBIOS_BAD_REGISTER_NUMBER;
 222         }
 223         return PCIBIOS_SUCCESSFUL;
 224 }
 225
 226 static int vlynq_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 227 {
 228         struct vlynq_device *dev;
 229         struct vlynq_pci_private *priv;
 230         int resno, slot = PCI_SLOT(devfn);
 231
 232         if ((size == 2) && (where & 1))
 233                 return PCIBIOS_BAD_REGISTER_NUMBER;
 234         else if ((size == 4) && (where & 3))
 235                 return PCIBIOS_BAD_REGISTER_NUMBER;
 236
 237         if (slot >= VLYNQ_PCI_SLOTS)
 238                 return PCIBIOS_DEVICE_NOT_FOUND;
 239
 240         dev = slots[slot];
 241
 242         if (!dev || (PCI_FUNC(devfn) > 0))
 243                 return PCIBIOS_DEVICE_NOT_FOUND;
 244
 245         priv = dev->priv;
 246
 247         switch (where) {
 248         case PCI_VENDOR_ID:
 249         case PCI_DEVICE_ID:
 250         case PCI_STATUS:
 251         case PCI_CLASS_REVISION:
 252         case PCI_HEADER_TYPE:
 253         case PCI_CACHE_LINE_SIZE:
 254         case PCI_SUBSYSTEM_VENDOR_ID:
 255         case PCI_SUBSYSTEM_ID:
 256         case PCI_INTERRUPT_LINE:
 257         case PCI_INTERRUPT_PIN:
 258         case PCI_CARDBUS_CIS:
 259         case PCI_CAPABILITY_LIST:
 260                 return PCIBIOS_FUNC_NOT_SUPPORTED;
 261         case PCI_COMMAND:
 262                 priv->command = val;
 263         case PCI_LATENCY_TIMER:
 264                 priv->latency = val;
 265                 break;
 266         case PCI_BASE_ADDRESS_0:
 267         case PCI_BASE_ADDRESS_1:
 268         case PCI_BASE_ADDRESS_2:
 269         case PCI_BASE_ADDRESS_3:
 270                 if (val == 0xffffffff) {
 271                         resno = (where - PCI_BASE_ADDRESS_0) >> 2;
 272                         priv->sz_mask |= (1 << resno);
 273                         break;
 274                 }
 275         case PCI_BASE_ADDRESS_4:
 276         case PCI_BASE_ADDRESS_5:
 277         case PCI_ROM_ADDRESS:
 278                 break;
 279         default:
 280                 printk("%s: Write to unknown register 0x%x (size %d) value=0x%x\n",
 281                        dev->dev.bus_id, where, size, val);
 282                 return PCIBIOS_BAD_REGISTER_NUMBER;
 283         }
 284         return PCIBIOS_SUCCESSFUL;
 285 }
 286
 287 static struct pci_ops vlynq_pci_ops = {
 288         vlynq_config_read,
 289         vlynq_config_write
 290 };
 291
 292 static struct pci_controller vlynq_controller = {
 293         .pci_ops        = &vlynq_pci_ops,
 294         .io_resource    = &vlynq_io_resource,
 295         .mem_resource   = &vlynq_mem_resource,
 296 };
 297
 298 static int vlynq_pci_probe(struct vlynq_device *dev)
 299 {
 300         int result, i;
 301         u32 chip_id, addr;
 302         struct vlynq_pci_private *priv;
 303         struct vlynq_mapping mapping[4] = { { 0, }, };
 304         struct vlynq_pci_config *config = NULL;
 305
 306         result = vlynq_set_local_irq(dev, 31);
 307         if (result)
 308                 return result;
 309
 310         result = vlynq_set_remote_irq(dev, 30);
 311         if (result)
 312                 return result;
 313
 314         result = vlynq_device_enable(dev);
 315         if (result)
 316                 return result;
 317
 318         chip_id = vlynq_remote_id(dev);
 319         for (i = 0; i < ARRAY_SIZE(known_devices); i++)
 320                 if (chip_id == known_devices[i].chip_id)
 321                         config = &known_devices[i];
 322
 323         if (!config) {
 324                 printk("vlynq-pci: skipping unknown device "
 325                        "%04x:%04x at %s\n", chip_id >> 16,
 326                        chip_id & 0xffff, dev->dev.bus_id);
 327                 result = -ENODEV;
 328                 goto fail;
 329         }
 330
 331         printk("vlynq-pci: attaching device %s at %s\n",
 332                config->name, dev->dev.bus_id);
 333
 334         priv = kmalloc(sizeof(struct vlynq_pci_private), GFP_KERNEL);
 335         if (!priv) {
 336                 printk(KERN_ERR "%s: failed to allocate private data\n",
 337                        dev->dev.bus_id);
 338                 result = -ENOMEM;
 339                 goto fail;
 340         }
 341
 342         memset(priv, 0, sizeof(struct vlynq_pci_private));
 343         priv->latency = 64;
 344         priv->cache_line = 32;
 345         priv->config = config;
 346
 347         mapping[0].offset = ARCH_PFN_OFFSET << PAGE_SHIFT;
 348         mapping[0].size = 0x02000000;
 349         vlynq_set_local_mapping(dev, dev->mem_start, mapping);
 350         vlynq_set_remote_mapping(dev, 0, config->rx_mapping);
 351
 352         set_irq_type(vlynq_virq_to_irq(dev, config->irq), config->irq_type);
 353
 354         addr = (u32)ioremap_nocache(dev->mem_start, 0x10000);
 355         if (!addr) {
 356                 printk(KERN_ERR "%s: failed to remap io memory\n",
 357                        dev->dev.bus_id);
 358                 result = -ENXIO;
 359                 goto fail;
 360         }
 361
 362         for (i = 0; i < config->num_regs; i++)
 363                 iowrite32(config->regs[i].value,
 364                           (u32 *)(addr + config->regs[i].offset));
 365
 366         dev->priv = priv;
 367         for (i = 0; i < VLYNQ_PCI_SLOTS; i++) {
 368                 if (!slots[i]) {
 369                         slots[i] = dev;
 370                         break;
 371                 }
 372         }
 373
 374         return 0;
 375
 376 fail:
 377         vlynq_device_disable(dev);
 378
 379         return result;
 380 }
 381
 382 static int vlynq_pci_remove(struct vlynq_device *dev)
 383 {
 384         int i;
 385         struct vlynq_pci_private *priv = dev->priv;
 386
 387         for (i = 0; i < VLYNQ_PCI_SLOTS; i++)
 388                 if (slots[i] == dev)
 389                         slots[i] = NULL;
 390
 391         vlynq_device_disable(dev);
 392         kfree(priv);
 393
 394         return 0;
 395 }
 396
 397 static struct vlynq_driver vlynq_pci = {
 398         .name = "PCI over VLYNQ emulation",
 399         .probe = vlynq_pci_probe,
 400         .remove = vlynq_pci_remove,
 401 };
 402
 403 int vlynq_pci_init(void)
 404 {
 405         int res;
 406         res = vlynq_register_driver(&vlynq_pci);
 407         if (res)
 408                 return res;
 409
 410         register_pci_controller(&vlynq_controller);
 411
 412         return 0;
 413 }
 414
 415 int pcibios_map_irq(struct pci_dev *pdev, u8 slot, u8 pin)
 416 {
 417         struct vlynq_device *dev;
 418         struct vlynq_pci_private *priv;
 419
 420         dev = slots[slot];
 421
 422         if (!dev)
 423                 return 0;
 424
 425         priv = dev->priv;
 426
 427         return vlynq_virq_to_irq(dev, priv->config->irq);
 428 }
 429
 430 /* Do platform specific device initialization at pci_enable_device() time */
 431 int pcibios_plat_dev_init(struct pci_dev *dev)
 432 {
 433         return 0;
 434 }