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ar71xx: set MII interface speed from the set_speed callbacks
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ar71xx / devices.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22
23 #include <asm/mach-ar71xx/ar71xx.h>
24 #include <asm/mach-ar71xx/ar933x_uart_platform.h>
25
26 #include "devices.h"
27
28 unsigned char ar71xx_mac_base[ETH_ALEN] __initdata;
29
30 static struct resource ar71xx_uart_resources[] = {
31 {
32 .start = AR71XX_UART_BASE,
33 .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
34 .flags = IORESOURCE_MEM,
35 },
36 };
37
38 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
39 static struct plat_serial8250_port ar71xx_uart_data[] = {
40 {
41 .mapbase = AR71XX_UART_BASE,
42 .irq = AR71XX_MISC_IRQ_UART,
43 .flags = AR71XX_UART_FLAGS,
44 .iotype = UPIO_MEM32,
45 .regshift = 2,
46 }, {
47 /* terminating entry */
48 }
49 };
50
51 static struct platform_device ar71xx_uart_device = {
52 .name = "serial8250",
53 .id = PLAT8250_DEV_PLATFORM,
54 .resource = ar71xx_uart_resources,
55 .num_resources = ARRAY_SIZE(ar71xx_uart_resources),
56 .dev = {
57 .platform_data = ar71xx_uart_data
58 },
59 };
60
61 static struct resource ar933x_uart_resources[] = {
62 {
63 .start = AR933X_UART_BASE,
64 .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
65 .flags = IORESOURCE_MEM,
66 },
67 {
68 .start = AR71XX_MISC_IRQ_UART,
69 .end = AR71XX_MISC_IRQ_UART,
70 .flags = IORESOURCE_IRQ,
71 },
72 };
73
74 static struct ar933x_uart_platform_data ar933x_uart_data;
75 static struct platform_device ar933x_uart_device = {
76 .name = "ar933x-uart",
77 .id = -1,
78 .resource = ar933x_uart_resources,
79 .num_resources = ARRAY_SIZE(ar933x_uart_resources),
80 .dev = {
81 .platform_data = &ar933x_uart_data,
82 },
83 };
84
85 void __init ar71xx_add_device_uart(void)
86 {
87 struct platform_device *pdev;
88
89 switch (ar71xx_soc) {
90 case AR71XX_SOC_AR7130:
91 case AR71XX_SOC_AR7141:
92 case AR71XX_SOC_AR7161:
93 case AR71XX_SOC_AR7240:
94 case AR71XX_SOC_AR7241:
95 case AR71XX_SOC_AR7242:
96 case AR71XX_SOC_AR9130:
97 case AR71XX_SOC_AR9132:
98 pdev = &ar71xx_uart_device;
99 ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
100 break;
101
102 case AR71XX_SOC_AR9330:
103 case AR71XX_SOC_AR9331:
104 pdev = &ar933x_uart_device;
105 ar933x_uart_data.uartclk = ar71xx_ref_freq;
106 break;
107
108 case AR71XX_SOC_AR9341:
109 case AR71XX_SOC_AR9342:
110 case AR71XX_SOC_AR9344:
111 pdev = &ar71xx_uart_device;
112 ar71xx_uart_data[0].uartclk = ar71xx_ref_freq;
113 break;
114
115 default:
116 BUG();
117 }
118
119 platform_device_register(pdev);
120 }
121
122 static struct resource ar71xx_mdio0_resources[] = {
123 {
124 .name = "mdio_base",
125 .flags = IORESOURCE_MEM,
126 .start = AR71XX_GE0_BASE,
127 .end = AR71XX_GE0_BASE + 0x200 - 1,
128 }
129 };
130
131 static struct ag71xx_mdio_platform_data ar71xx_mdio0_data;
132
133 struct platform_device ar71xx_mdio0_device = {
134 .name = "ag71xx-mdio",
135 .id = 0,
136 .resource = ar71xx_mdio0_resources,
137 .num_resources = ARRAY_SIZE(ar71xx_mdio0_resources),
138 .dev = {
139 .platform_data = &ar71xx_mdio0_data,
140 },
141 };
142
143 static struct resource ar71xx_mdio1_resources[] = {
144 {
145 .name = "mdio_base",
146 .flags = IORESOURCE_MEM,
147 .start = AR71XX_GE1_BASE,
148 .end = AR71XX_GE1_BASE + 0x200 - 1,
149 }
150 };
151
152 static struct ag71xx_mdio_platform_data ar71xx_mdio1_data;
153
154 struct platform_device ar71xx_mdio1_device = {
155 .name = "ag71xx-mdio",
156 .id = 1,
157 .resource = ar71xx_mdio1_resources,
158 .num_resources = ARRAY_SIZE(ar71xx_mdio1_resources),
159 .dev = {
160 .platform_data = &ar71xx_mdio1_data,
161 },
162 };
163
164 static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
165 {
166 void __iomem *base;
167 u32 t;
168
169 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
170
171 t = __raw_readl(base + cfg_reg);
172 t &= ~(3 << shift);
173 t |= (2 << shift);
174 __raw_writel(t, base + cfg_reg);
175 udelay(100);
176
177 __raw_writel(pll_val, base + pll_reg);
178
179 t |= (3 << shift);
180 __raw_writel(t, base + cfg_reg);
181 udelay(100);
182
183 t &= ~(3 << shift);
184 __raw_writel(t, base + cfg_reg);
185 udelay(100);
186
187 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
188 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
189
190 iounmap(base);
191 }
192
193 static void __init ar71xx_mii_ctrl_set_if(unsigned int reg,
194 unsigned int mii_if)
195 {
196 void __iomem *base;
197 u32 t;
198
199 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
200
201 t = __raw_readl(base + reg);
202 t &= ~(MII_CTRL_IF_MASK);
203 t |= (mii_if & MII_CTRL_IF_MASK);
204 __raw_writel(t, base + reg);
205
206 iounmap(base);
207 }
208
209 static void ar71xx_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
210 {
211 void __iomem *base;
212 unsigned int mii_speed;
213 u32 t;
214
215 switch (speed) {
216 case SPEED_10:
217 mii_speed = MII_CTRL_SPEED_10;
218 break;
219 case SPEED_100:
220 mii_speed = MII_CTRL_SPEED_100;
221 break;
222 case SPEED_1000:
223 mii_speed = MII_CTRL_SPEED_1000;
224 break;
225 default:
226 BUG();
227 }
228
229 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
230
231 t = __raw_readl(base + reg);
232 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
233 t |= mii_speed << MII_CTRL_SPEED_SHIFT;
234 __raw_writel(t, base + reg);
235
236 iounmap(base);
237 }
238
239 void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
240 {
241 struct platform_device *mdio_dev;
242 struct ag71xx_mdio_platform_data *mdio_data;
243 unsigned int max_id;
244
245 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
246 ar71xx_soc == AR71XX_SOC_AR9342 ||
247 ar71xx_soc == AR71XX_SOC_AR9344)
248 max_id = 1;
249 else
250 max_id = 0;
251
252 if (id > max_id) {
253 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
254 return;
255 }
256
257 switch (ar71xx_soc) {
258 case AR71XX_SOC_AR7241:
259 case AR71XX_SOC_AR9330:
260 case AR71XX_SOC_AR9331:
261 mdio_dev = &ar71xx_mdio1_device;
262 mdio_data = &ar71xx_mdio1_data;
263 break;
264
265 case AR71XX_SOC_AR9341:
266 case AR71XX_SOC_AR9342:
267 case AR71XX_SOC_AR9344:
268 if (id == 0) {
269 mdio_dev = &ar71xx_mdio0_device;
270 mdio_data = &ar71xx_mdio0_data;
271 } else {
272 mdio_dev = &ar71xx_mdio1_device;
273 mdio_data = &ar71xx_mdio1_data;
274 }
275 break;
276
277 case AR71XX_SOC_AR7242:
278 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
279 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
280 AR71XX_ETH0_PLL_SHIFT);
281 /* fall through */
282 default:
283 mdio_dev = &ar71xx_mdio0_device;
284 mdio_data = &ar71xx_mdio0_data;
285 break;
286 }
287
288 mdio_data->phy_mask = phy_mask;
289
290 switch (ar71xx_soc) {
291 case AR71XX_SOC_AR7240:
292 case AR71XX_SOC_AR7241:
293 case AR71XX_SOC_AR9330:
294 case AR71XX_SOC_AR9331:
295 mdio_data->is_ar7240 = 1;
296 break;
297
298 case AR71XX_SOC_AR9341:
299 case AR71XX_SOC_AR9342:
300 case AR71XX_SOC_AR9344:
301 if (id == 1)
302 mdio_data->is_ar7240 = 1;
303 break;
304
305 default:
306 break;
307 }
308
309 platform_device_register(mdio_dev);
310 }
311
312 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
313 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
314
315 static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
316 {
317 struct ar71xx_eth_pll_data *pll_data;
318 u32 pll_val;
319
320 switch (mac) {
321 case 0:
322 pll_data = &ar71xx_eth0_pll_data;
323 break;
324 case 1:
325 pll_data = &ar71xx_eth1_pll_data;
326 break;
327 default:
328 BUG();
329 }
330
331 switch (speed) {
332 case SPEED_10:
333 pll_val = pll_data->pll_10;
334 break;
335 case SPEED_100:
336 pll_val = pll_data->pll_100;
337 break;
338 case SPEED_1000:
339 pll_val = pll_data->pll_1000;
340 break;
341 default:
342 BUG();
343 }
344
345 return pll_val;
346 }
347
348 static void ar71xx_set_speed_ge0(int speed)
349 {
350 u32 val = ar71xx_get_eth_pll(0, speed);
351
352 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
353 val, AR71XX_ETH0_PLL_SHIFT);
354 ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
355 }
356
357 static void ar71xx_set_speed_ge1(int speed)
358 {
359 u32 val = ar71xx_get_eth_pll(1, speed);
360
361 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
362 val, AR71XX_ETH1_PLL_SHIFT);
363 ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
364 }
365
366 static void ar724x_set_speed_ge0(int speed)
367 {
368 /* TODO */
369 }
370
371 static void ar724x_set_speed_ge1(int speed)
372 {
373 /* TODO */
374 }
375
376 static void ar7242_set_speed_ge0(int speed)
377 {
378 u32 val = ar71xx_get_eth_pll(0, speed);
379 void __iomem *base;
380
381 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
382 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
383 iounmap(base);
384 }
385
386 static void ar91xx_set_speed_ge0(int speed)
387 {
388 u32 val = ar71xx_get_eth_pll(0, speed);
389
390 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
391 val, AR91XX_ETH0_PLL_SHIFT);
392 ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
393 }
394
395 static void ar91xx_set_speed_ge1(int speed)
396 {
397 u32 val = ar71xx_get_eth_pll(1, speed);
398
399 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
400 val, AR91XX_ETH1_PLL_SHIFT);
401 ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
402 }
403
404 static void ar933x_set_speed_ge0(int speed)
405 {
406 /* TODO */
407 }
408
409 static void ar933x_set_speed_ge1(int speed)
410 {
411 /* TODO */
412 }
413
414 static void ar934x_set_speed_ge0(int speed)
415 {
416 /* TODO */
417 }
418
419 static void ar934x_set_speed_ge1(int speed)
420 {
421 /* TODO */
422 }
423
424 static void ar71xx_ddr_flush_ge0(void)
425 {
426 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
427 }
428
429 static void ar71xx_ddr_flush_ge1(void)
430 {
431 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
432 }
433
434 static void ar724x_ddr_flush_ge0(void)
435 {
436 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
437 }
438
439 static void ar724x_ddr_flush_ge1(void)
440 {
441 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
442 }
443
444 static void ar91xx_ddr_flush_ge0(void)
445 {
446 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
447 }
448
449 static void ar91xx_ddr_flush_ge1(void)
450 {
451 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
452 }
453
454 static void ar933x_ddr_flush_ge0(void)
455 {
456 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
457 }
458
459 static void ar933x_ddr_flush_ge1(void)
460 {
461 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
462 }
463
464 static void ar934x_ddr_flush_ge0(void)
465 {
466 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
467 }
468
469 static void ar934x_ddr_flush_ge1(void)
470 {
471 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
472 }
473
474 static struct resource ar71xx_eth0_resources[] = {
475 {
476 .name = "mac_base",
477 .flags = IORESOURCE_MEM,
478 .start = AR71XX_GE0_BASE,
479 .end = AR71XX_GE0_BASE + 0x200 - 1,
480 }, {
481 .name = "mii_ctrl",
482 .flags = IORESOURCE_MEM,
483 .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL,
484 .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3,
485 }, {
486 .name = "mac_irq",
487 .flags = IORESOURCE_IRQ,
488 .start = AR71XX_CPU_IRQ_GE0,
489 .end = AR71XX_CPU_IRQ_GE0,
490 },
491 };
492
493 struct ag71xx_platform_data ar71xx_eth0_data = {
494 .reset_bit = RESET_MODULE_GE0_MAC,
495 };
496
497 struct platform_device ar71xx_eth0_device = {
498 .name = "ag71xx",
499 .id = 0,
500 .resource = ar71xx_eth0_resources,
501 .num_resources = ARRAY_SIZE(ar71xx_eth0_resources),
502 .dev = {
503 .platform_data = &ar71xx_eth0_data,
504 },
505 };
506
507 static struct resource ar71xx_eth1_resources[] = {
508 {
509 .name = "mac_base",
510 .flags = IORESOURCE_MEM,
511 .start = AR71XX_GE1_BASE,
512 .end = AR71XX_GE1_BASE + 0x200 - 1,
513 }, {
514 .name = "mii_ctrl",
515 .flags = IORESOURCE_MEM,
516 .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL,
517 .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3,
518 }, {
519 .name = "mac_irq",
520 .flags = IORESOURCE_IRQ,
521 .start = AR71XX_CPU_IRQ_GE1,
522 .end = AR71XX_CPU_IRQ_GE1,
523 },
524 };
525
526 struct ag71xx_platform_data ar71xx_eth1_data = {
527 .reset_bit = RESET_MODULE_GE1_MAC,
528 };
529
530 struct platform_device ar71xx_eth1_device = {
531 .name = "ag71xx",
532 .id = 1,
533 .resource = ar71xx_eth1_resources,
534 .num_resources = ARRAY_SIZE(ar71xx_eth1_resources),
535 .dev = {
536 .platform_data = &ar71xx_eth1_data,
537 },
538 };
539
540 #define AR71XX_PLL_VAL_1000 0x00110000
541 #define AR71XX_PLL_VAL_100 0x00001099
542 #define AR71XX_PLL_VAL_10 0x00991099
543
544 #define AR724X_PLL_VAL_1000 0x00110000
545 #define AR724X_PLL_VAL_100 0x00001099
546 #define AR724X_PLL_VAL_10 0x00991099
547
548 #define AR7242_PLL_VAL_1000 0x16000000
549 #define AR7242_PLL_VAL_100 0x00000101
550 #define AR7242_PLL_VAL_10 0x00001616
551
552 #define AR91XX_PLL_VAL_1000 0x1a000000
553 #define AR91XX_PLL_VAL_100 0x13000a44
554 #define AR91XX_PLL_VAL_10 0x00441099
555
556 #define AR933X_PLL_VAL_1000 0x00110000
557 #define AR933X_PLL_VAL_100 0x00001099
558 #define AR933X_PLL_VAL_10 0x00991099
559
560 #define AR934X_PLL_VAL_1000 0x00110000
561 #define AR934X_PLL_VAL_100 0x00001099
562 #define AR934X_PLL_VAL_10 0x00991099
563
564 static void __init ar71xx_init_eth_pll_data(unsigned int id)
565 {
566 struct ar71xx_eth_pll_data *pll_data;
567 u32 pll_10, pll_100, pll_1000;
568
569 switch (id) {
570 case 0:
571 pll_data = &ar71xx_eth0_pll_data;
572 break;
573 case 1:
574 pll_data = &ar71xx_eth1_pll_data;
575 break;
576 default:
577 BUG();
578 }
579
580 switch (ar71xx_soc) {
581 case AR71XX_SOC_AR7130:
582 case AR71XX_SOC_AR7141:
583 case AR71XX_SOC_AR7161:
584 pll_10 = AR71XX_PLL_VAL_10;
585 pll_100 = AR71XX_PLL_VAL_100;
586 pll_1000 = AR71XX_PLL_VAL_1000;
587 break;
588
589 case AR71XX_SOC_AR7240:
590 case AR71XX_SOC_AR7241:
591 pll_10 = AR724X_PLL_VAL_10;
592 pll_100 = AR724X_PLL_VAL_100;
593 pll_1000 = AR724X_PLL_VAL_1000;
594 break;
595
596 case AR71XX_SOC_AR7242:
597 pll_10 = AR7242_PLL_VAL_10;
598 pll_100 = AR7242_PLL_VAL_100;
599 pll_1000 = AR7242_PLL_VAL_1000;
600 break;
601
602 case AR71XX_SOC_AR9130:
603 case AR71XX_SOC_AR9132:
604 pll_10 = AR91XX_PLL_VAL_10;
605 pll_100 = AR91XX_PLL_VAL_100;
606 pll_1000 = AR91XX_PLL_VAL_1000;
607 break;
608
609 case AR71XX_SOC_AR9330:
610 case AR71XX_SOC_AR9331:
611 pll_10 = AR933X_PLL_VAL_10;
612 pll_100 = AR933X_PLL_VAL_100;
613 pll_1000 = AR933X_PLL_VAL_1000;
614 break;
615
616 case AR71XX_SOC_AR9341:
617 case AR71XX_SOC_AR9342:
618 case AR71XX_SOC_AR9344:
619 pll_10 = AR934X_PLL_VAL_10;
620 pll_100 = AR934X_PLL_VAL_100;
621 pll_1000 = AR934X_PLL_VAL_1000;
622 break;
623
624 default:
625 BUG();
626 }
627
628 if (!pll_data->pll_10)
629 pll_data->pll_10 = pll_10;
630
631 if (!pll_data->pll_100)
632 pll_data->pll_100 = pll_100;
633
634 if (!pll_data->pll_1000)
635 pll_data->pll_1000 = pll_1000;
636 }
637
638 static int __init ar71xx_setup_phy_if_mode(unsigned int id,
639 struct ag71xx_platform_data *pdata)
640 {
641 unsigned int mii_if;
642
643 switch (id) {
644 case 0:
645 switch (ar71xx_soc) {
646 case AR71XX_SOC_AR7130:
647 case AR71XX_SOC_AR7141:
648 case AR71XX_SOC_AR7161:
649 case AR71XX_SOC_AR9130:
650 case AR71XX_SOC_AR9132:
651 switch (pdata->phy_if_mode) {
652 case PHY_INTERFACE_MODE_MII:
653 mii_if = MII0_CTRL_IF_MII;
654 break;
655 case PHY_INTERFACE_MODE_GMII:
656 mii_if = MII0_CTRL_IF_GMII;
657 break;
658 case PHY_INTERFACE_MODE_RGMII:
659 mii_if = MII0_CTRL_IF_RGMII;
660 break;
661 case PHY_INTERFACE_MODE_RMII:
662 mii_if = MII0_CTRL_IF_RMII;
663 break;
664 default:
665 return -EINVAL;
666 }
667 ar71xx_mii_ctrl_set_if(MII_REG_MII0_CTRL, mii_if);
668 break;
669
670 case AR71XX_SOC_AR7240:
671 case AR71XX_SOC_AR7241:
672 case AR71XX_SOC_AR9330:
673 case AR71XX_SOC_AR9331:
674 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
675 break;
676
677 case AR71XX_SOC_AR7242:
678 /* FIXME */
679
680 case AR71XX_SOC_AR9341:
681 case AR71XX_SOC_AR9342:
682 case AR71XX_SOC_AR9344:
683 switch (pdata->phy_if_mode) {
684 case PHY_INTERFACE_MODE_MII:
685 case PHY_INTERFACE_MODE_GMII:
686 case PHY_INTERFACE_MODE_RGMII:
687 case PHY_INTERFACE_MODE_RMII:
688 break;
689 default:
690 return -EINVAL;
691 }
692 break;
693
694 default:
695 BUG();
696 }
697 break;
698 case 1:
699 switch (ar71xx_soc) {
700 case AR71XX_SOC_AR7130:
701 case AR71XX_SOC_AR7141:
702 case AR71XX_SOC_AR7161:
703 case AR71XX_SOC_AR9130:
704 case AR71XX_SOC_AR9132:
705 switch (pdata->phy_if_mode) {
706 case PHY_INTERFACE_MODE_RMII:
707 mii_if = MII1_CTRL_IF_RMII;
708 break;
709 case PHY_INTERFACE_MODE_RGMII:
710 mii_if = MII1_CTRL_IF_RGMII;
711 break;
712 default:
713 return -EINVAL;
714 }
715 ar71xx_mii_ctrl_set_if(MII_REG_MII1_CTRL, mii_if);
716 break;
717
718 case AR71XX_SOC_AR7240:
719 case AR71XX_SOC_AR7241:
720 case AR71XX_SOC_AR9330:
721 case AR71XX_SOC_AR9331:
722 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
723 break;
724
725 case AR71XX_SOC_AR7242:
726 /* FIXME */
727
728 case AR71XX_SOC_AR9341:
729 case AR71XX_SOC_AR9342:
730 case AR71XX_SOC_AR9344:
731 switch (pdata->phy_if_mode) {
732 case PHY_INTERFACE_MODE_MII:
733 case PHY_INTERFACE_MODE_GMII:
734 break;
735 default:
736 return -EINVAL;
737 }
738 break;
739
740 default:
741 BUG();
742 }
743 break;
744 }
745
746 return 0;
747 }
748
749 static int ar71xx_eth_instance __initdata;
750 void __init ar71xx_add_device_eth(unsigned int id)
751 {
752 struct platform_device *pdev;
753 struct ag71xx_platform_data *pdata;
754 int err;
755
756 if (id > 1) {
757 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
758 return;
759 }
760
761 ar71xx_init_eth_pll_data(id);
762
763 if (id == 0)
764 pdev = &ar71xx_eth0_device;
765 else
766 pdev = &ar71xx_eth1_device;
767
768 pdata = pdev->dev.platform_data;
769
770 err = ar71xx_setup_phy_if_mode(id, pdata);
771 if (err) {
772 printk(KERN_ERR
773 "ar71xx: invalid PHY interface mode for GE%u\n", id);
774 return;
775 }
776
777 switch (ar71xx_soc) {
778 case AR71XX_SOC_AR7130:
779 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
780 : ar71xx_ddr_flush_ge0;
781 pdata->set_speed = id ? ar71xx_set_speed_ge1
782 : ar71xx_set_speed_ge0;
783 break;
784
785 case AR71XX_SOC_AR7141:
786 case AR71XX_SOC_AR7161:
787 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
788 : ar71xx_ddr_flush_ge0;
789 pdata->set_speed = id ? ar71xx_set_speed_ge1
790 : ar71xx_set_speed_ge0;
791 pdata->has_gbit = 1;
792 break;
793
794 case AR71XX_SOC_AR7242:
795 ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO |
796 RESET_MODULE_GE0_PHY;
797 ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO |
798 RESET_MODULE_GE1_PHY;
799 pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
800 : ar724x_ddr_flush_ge0;
801 pdata->set_speed = id ? ar724x_set_speed_ge1
802 : ar7242_set_speed_ge0;
803 pdata->has_gbit = 1;
804 pdata->is_ar724x = 1;
805
806 if (!pdata->fifo_cfg1)
807 pdata->fifo_cfg1 = 0x0010ffff;
808 if (!pdata->fifo_cfg2)
809 pdata->fifo_cfg2 = 0x015500aa;
810 if (!pdata->fifo_cfg3)
811 pdata->fifo_cfg3 = 0x01f00140;
812 break;
813
814 case AR71XX_SOC_AR7241:
815 ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
816 ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
817 /* fall through */
818 case AR71XX_SOC_AR7240:
819 ar71xx_eth0_data.reset_bit |= RESET_MODULE_GE0_PHY;
820 ar71xx_eth1_data.reset_bit |= RESET_MODULE_GE1_PHY;
821 pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
822 : ar724x_ddr_flush_ge0;
823 pdata->set_speed = id ? ar724x_set_speed_ge1
824 : ar724x_set_speed_ge0;
825 pdata->is_ar724x = 1;
826 if (ar71xx_soc == AR71XX_SOC_AR7240)
827 pdata->is_ar7240 = 1;
828
829 if (!pdata->fifo_cfg1)
830 pdata->fifo_cfg1 = 0x0010ffff;
831 if (!pdata->fifo_cfg2)
832 pdata->fifo_cfg2 = 0x015500aa;
833 if (!pdata->fifo_cfg3)
834 pdata->fifo_cfg3 = 0x01f00140;
835 break;
836
837 case AR71XX_SOC_AR9130:
838 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
839 : ar91xx_ddr_flush_ge0;
840 pdata->set_speed = id ? ar91xx_set_speed_ge1
841 : ar91xx_set_speed_ge0;
842 pdata->is_ar91xx = 1;
843 break;
844
845 case AR71XX_SOC_AR9132:
846 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
847 : ar91xx_ddr_flush_ge0;
848 pdata->set_speed = id ? ar91xx_set_speed_ge1
849 : ar91xx_set_speed_ge0;
850 pdata->is_ar91xx = 1;
851 pdata->has_gbit = 1;
852 break;
853
854 case AR71XX_SOC_AR9330:
855 case AR71XX_SOC_AR9331:
856 ar71xx_eth0_data.reset_bit = AR933X_RESET_GE0_MAC |
857 AR933X_RESET_GE0_MDIO;
858 ar71xx_eth1_data.reset_bit = AR933X_RESET_GE1_MAC |
859 AR933X_RESET_GE1_MDIO;
860 pdata->ddr_flush = id ? ar933x_ddr_flush_ge1
861 : ar933x_ddr_flush_ge0;
862 pdata->set_speed = id ? ar933x_set_speed_ge1
863 : ar933x_set_speed_ge0;
864 pdata->has_gbit = 1;
865 pdata->is_ar724x = 1;
866
867 if (!pdata->fifo_cfg1)
868 pdata->fifo_cfg1 = 0x0010ffff;
869 if (!pdata->fifo_cfg2)
870 pdata->fifo_cfg2 = 0x015500aa;
871 if (!pdata->fifo_cfg3)
872 pdata->fifo_cfg3 = 0x01f00140;
873 break;
874
875 case AR71XX_SOC_AR9341:
876 case AR71XX_SOC_AR9342:
877 case AR71XX_SOC_AR9344:
878 ar71xx_eth0_data.reset_bit = AR934X_RESET_GE0_MAC |
879 AR934X_RESET_GE0_MDIO;
880 ar71xx_eth1_data.reset_bit = AR934X_RESET_GE1_MAC |
881 AR934X_RESET_GE1_MDIO;
882 pdata->ddr_flush = id ? ar934x_ddr_flush_ge1
883 : ar934x_ddr_flush_ge0;
884 pdata->set_speed = id ? ar934x_set_speed_ge1
885 : ar934x_set_speed_ge0;
886 pdata->has_gbit = 1;
887 pdata->is_ar724x = 1;
888
889 if (!pdata->fifo_cfg1)
890 pdata->fifo_cfg1 = 0x0010ffff;
891 if (!pdata->fifo_cfg2)
892 pdata->fifo_cfg2 = 0x015500aa;
893 if (!pdata->fifo_cfg3)
894 pdata->fifo_cfg3 = 0x01f00140;
895 break;
896
897 default:
898 BUG();
899 }
900
901 switch (pdata->phy_if_mode) {
902 case PHY_INTERFACE_MODE_GMII:
903 case PHY_INTERFACE_MODE_RGMII:
904 if (!pdata->has_gbit) {
905 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
906 id);
907 return;
908 }
909 /* fallthrough */
910 default:
911 break;
912 }
913
914 if (!is_valid_ether_addr(pdata->mac_addr)) {
915 random_ether_addr(pdata->mac_addr);
916 printk(KERN_DEBUG
917 "ar71xx: using random MAC address for eth%d\n",
918 ar71xx_eth_instance);
919 }
920
921 if (pdata->mii_bus_dev == NULL) {
922 switch (ar71xx_soc) {
923 case AR71XX_SOC_AR9341:
924 case AR71XX_SOC_AR9342:
925 case AR71XX_SOC_AR9344:
926 if (id == 0)
927 pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
928 else
929 pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
930 break;
931
932 case AR71XX_SOC_AR7241:
933 case AR71XX_SOC_AR9330:
934 case AR71XX_SOC_AR9331:
935 pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
936 break;
937
938 default:
939 pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
940 break;
941 }
942 }
943
944 /* Reset the device */
945 ar71xx_device_stop(pdata->reset_bit);
946 mdelay(100);
947
948 ar71xx_device_start(pdata->reset_bit);
949 mdelay(100);
950
951 platform_device_register(pdev);
952 ar71xx_eth_instance++;
953 }
954
955 static struct resource ar71xx_spi_resources[] = {
956 [0] = {
957 .start = AR71XX_SPI_BASE,
958 .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
959 .flags = IORESOURCE_MEM,
960 },
961 };
962
963 static struct platform_device ar71xx_spi_device = {
964 .name = "ar71xx-spi",
965 .id = -1,
966 .resource = ar71xx_spi_resources,
967 .num_resources = ARRAY_SIZE(ar71xx_spi_resources),
968 };
969
970 void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
971 struct spi_board_info const *info,
972 unsigned n)
973 {
974 spi_register_board_info(info, n);
975 ar71xx_spi_device.dev.platform_data = pdata;
976 platform_device_register(&ar71xx_spi_device);
977 }
978
979 void __init ar71xx_add_device_wdt(void)
980 {
981 platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
982 }
983
984 void __init ar71xx_set_mac_base(unsigned char *mac)
985 {
986 memcpy(ar71xx_mac_base, mac, ETH_ALEN);
987 }
988
989 void __init ar71xx_parse_mac_addr(char *mac_str)
990 {
991 u8 tmp[ETH_ALEN];
992 int t;
993
994 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
995 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
996
997 if (t != ETH_ALEN)
998 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
999 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1000
1001 if (t == ETH_ALEN)
1002 ar71xx_set_mac_base(tmp);
1003 else
1004 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
1005 "\"%s\"\n", mac_str);
1006 }
1007
1008 static int __init ar71xx_ethaddr_setup(char *str)
1009 {
1010 ar71xx_parse_mac_addr(str);
1011 return 1;
1012 }
1013 __setup("ethaddr=", ar71xx_ethaddr_setup);
1014
1015 static int __init ar71xx_kmac_setup(char *str)
1016 {
1017 ar71xx_parse_mac_addr(str);
1018 return 1;
1019 }
1020 __setup("kmac=", ar71xx_kmac_setup);
1021
1022 void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src,
1023 unsigned offset)
1024 {
1025 u32 t;
1026
1027 if (!is_valid_ether_addr(src)) {
1028 memset(dst, '\0', ETH_ALEN);
1029 return;
1030 }
1031
1032 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1033 t += offset;
1034
1035 dst[0] = src[0];
1036 dst[1] = src[1];
1037 dst[2] = src[2];
1038 dst[3] = (t >> 16) & 0xff;
1039 dst[4] = (t >> 8) & 0xff;
1040 dst[5] = t & 0xff;
1041 }
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