target/linux/ar71xx/files/arch/mips/ar71xx/irq.c

   1 /*
   2  *  Atheros AR71xx SoC specific interrupt handling
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros 2.6.15 BSP
   9  *  Parts of this file are based on Atheros 2.6.31 BSP
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License version 2 as published
  13  *  by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20
  21 #include <asm/irq_cpu.h>
  22 #include <asm/mipsregs.h>
  23
  24 #include <asm/mach-ar71xx/ar71xx.h>
  25
  26 static void ar71xx_gpio_irq_dispatch(void)
  27 {
  28         void __iomem *base = ar71xx_gpio_base;
  29         u32 pending;
  30
  31         pending = __raw_readl(base + GPIO_REG_INT_PENDING) &
  32                   __raw_readl(base + GPIO_REG_INT_ENABLE);
  33
  34         if (pending)
  35                 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
  36         else
  37                 spurious_interrupt();
  38 }
  39
  40 static void ar71xx_gpio_irq_unmask(unsigned int irq)
  41 {
  42         void __iomem *base = ar71xx_gpio_base;
  43         u32 t;
  44
  45         irq -= AR71XX_GPIO_IRQ_BASE;
  46
  47         t = __raw_readl(base + GPIO_REG_INT_ENABLE);
  48         __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE);
  49
  50         /* flush write */
  51         (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
  52 }
  53
  54 static void ar71xx_gpio_irq_mask(unsigned int irq)
  55 {
  56         void __iomem *base = ar71xx_gpio_base;
  57         u32 t;
  58
  59         irq -= AR71XX_GPIO_IRQ_BASE;
  60
  61         t = __raw_readl(base + GPIO_REG_INT_ENABLE);
  62         __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE);
  63
  64         /* flush write */
  65         (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
  66 }
  67
  68 #if 0
  69 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
  70 {
  71         /* TODO: implement */
  72         return 0;
  73 }
  74 #else
  75 #define ar71xx_gpio_irq_set_type        NULL
  76 #endif
  77
  78 static struct irq_chip ar71xx_gpio_irq_chip = {
  79         .name           = "AR71XX GPIO",
  80         .unmask         = ar71xx_gpio_irq_unmask,
  81         .mask           = ar71xx_gpio_irq_mask,
  82         .mask_ack       = ar71xx_gpio_irq_mask,
  83         .set_type       = ar71xx_gpio_irq_set_type,
  84 };
  85
  86 static struct irqaction ar71xx_gpio_irqaction = {
  87         .handler        = no_action,
  88         .name           = "cascade [AR71XX GPIO]",
  89 };
  90
  91 #define GPIO_INT_ALL    0xffff
  92
  93 static void __init ar71xx_gpio_irq_init(void)
  94 {
  95         void __iomem *base = ar71xx_gpio_base;
  96         int i;
  97
  98         __raw_writel(0, base + GPIO_REG_INT_ENABLE);
  99         __raw_writel(0, base + GPIO_REG_INT_PENDING);
 100
 101         /* setup type of all GPIO interrupts to level sensitive */
 102         __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE);
 103
 104         /* setup polarity of all GPIO interrupts to active high */
 105         __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY);
 106
 107         for (i = AR71XX_GPIO_IRQ_BASE;
 108              i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++)
 109                 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
 110                                          handle_level_irq);
 111
 112         setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
 113 }
 114
 115 static void ar71xx_misc_irq_dispatch(void)
 116 {
 117         u32 pending;
 118
 119         pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
 120             & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 121
 122         if (pending & MISC_INT_UART)
 123                 do_IRQ(AR71XX_MISC_IRQ_UART);
 124
 125         else if (pending & MISC_INT_DMA)
 126                 do_IRQ(AR71XX_MISC_IRQ_DMA);
 127
 128         else if (pending & MISC_INT_PERFC)
 129                 do_IRQ(AR71XX_MISC_IRQ_PERFC);
 130
 131         else if (pending & MISC_INT_TIMER)
 132                 do_IRQ(AR71XX_MISC_IRQ_TIMER);
 133
 134         else if (pending & MISC_INT_OHCI)
 135                 do_IRQ(AR71XX_MISC_IRQ_OHCI);
 136
 137         else if (pending & MISC_INT_ERROR)
 138                 do_IRQ(AR71XX_MISC_IRQ_ERROR);
 139
 140         else if (pending & MISC_INT_GPIO)
 141                 ar71xx_gpio_irq_dispatch();
 142
 143         else if (pending & MISC_INT_WDOG)
 144                 do_IRQ(AR71XX_MISC_IRQ_WDOG);
 145
 146         else if (pending & MISC_INT_TIMER2)
 147                 do_IRQ(AR71XX_MISC_IRQ_TIMER2);
 148
 149         else if (pending & MISC_INT_TIMER3)
 150                 do_IRQ(AR71XX_MISC_IRQ_TIMER3);
 151
 152         else if (pending & MISC_INT_TIMER4)
 153                 do_IRQ(AR71XX_MISC_IRQ_TIMER4);
 154
 155         else if (pending & MISC_INT_DDR_PERF)
 156                 do_IRQ(AR71XX_MISC_IRQ_DDR_PERF);
 157
 158         else if (pending & MISC_INT_ENET_LINK)
 159                 do_IRQ(AR71XX_MISC_IRQ_ENET_LINK);
 160
 161         else
 162                 spurious_interrupt();
 163 }
 164
 165 static void ar71xx_misc_irq_unmask(unsigned int irq)
 166 {
 167         void __iomem *base = ar71xx_reset_base;
 168         u32 t;
 169
 170         irq -= AR71XX_MISC_IRQ_BASE;
 171
 172         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 173         __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 174
 175         /* flush write */
 176         (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 177 }
 178
 179 static void ar71xx_misc_irq_mask(unsigned int irq)
 180 {
 181         void __iomem *base = ar71xx_reset_base;
 182         u32 t;
 183
 184         irq -= AR71XX_MISC_IRQ_BASE;
 185
 186         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 187         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 188
 189         /* flush write */
 190         (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 191 }
 192
 193 static void ar724x_misc_irq_ack(unsigned int irq)
 194 {
 195         void __iomem *base = ar71xx_reset_base;
 196         u32 t;
 197
 198         irq -= AR71XX_MISC_IRQ_BASE;
 199
 200         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
 201         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
 202
 203         /* flush write */
 204         (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
 205 }
 206
 207 static struct irq_chip ar71xx_misc_irq_chip = {
 208         .name           = "AR71XX MISC",
 209         .unmask         = ar71xx_misc_irq_unmask,
 210         .mask           = ar71xx_misc_irq_mask,
 211 };
 212
 213 static struct irqaction ar71xx_misc_irqaction = {
 214         .handler        = no_action,
 215         .name           = "cascade [AR71XX MISC]",
 216 };
 217
 218 static void __init ar71xx_misc_irq_init(void)
 219 {
 220         void __iomem *base = ar71xx_reset_base;
 221         int i;
 222
 223         __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 224         __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
 225
 226         switch (ar71xx_soc) {
 227         case AR71XX_SOC_AR7240:
 228         case AR71XX_SOC_AR7241:
 229         case AR71XX_SOC_AR7242:
 230         case AR71XX_SOC_AR9330:
 231         case AR71XX_SOC_AR9331:
 232         case AR71XX_SOC_AR9341:
 233         case AR71XX_SOC_AR9342:
 234         case AR71XX_SOC_AR9344:
 235                 ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
 236                 break;
 237         default:
 238                 ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
 239                 break;
 240         }
 241
 242         for (i = AR71XX_MISC_IRQ_BASE;
 243              i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++)
 244                 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
 245                                          handle_level_irq);
 246
 247         setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
 248 }
 249
 250 /*
 251  * The IP2 line is tied to a PCI/WMAC device. Drivers for these
 252  * devices typically allocate coherent DMA memory for the descriptor
 253  * ring, however the DMA controller may still have some unsynchronized
 254  * data in the FIFO.
 255  * Issue a flush in the handlers to ensure that the driver sees
 256  * the update.
 257  */
 258 static void ar71xx_ip2_handler(void)
 259 {
 260         ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_PCI);
 261         do_IRQ(AR71XX_CPU_IRQ_IP2);
 262 }
 263
 264 static void ar724x_ip2_handler(void)
 265 {
 266         ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE);
 267         do_IRQ(AR71XX_CPU_IRQ_IP2);
 268 }
 269
 270 static void ar913x_ip2_handler(void)
 271 {
 272         ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
 273         do_IRQ(AR71XX_CPU_IRQ_IP2);
 274 }
 275
 276 static void ar933x_ip2_handler(void)
 277 {
 278         ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
 279         do_IRQ(AR71XX_CPU_IRQ_IP2);
 280 }
 281
 282 static void ar934x_ip2_handler(void)
 283 {
 284         ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_PCIE);
 285         do_IRQ(AR71XX_CPU_IRQ_IP2);
 286 }
 287
 288 static void (*ip2_handler)(void);
 289
 290 asmlinkage void plat_irq_dispatch(void)
 291 {
 292         unsigned long pending;
 293
 294         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 295
 296         if (pending & STATUSF_IP7)
 297                 do_IRQ(AR71XX_CPU_IRQ_TIMER);
 298
 299         else if (pending & STATUSF_IP2)
 300                 ip2_handler();
 301
 302         else if (pending & STATUSF_IP4)
 303                 do_IRQ(AR71XX_CPU_IRQ_GE0);
 304
 305         else if (pending & STATUSF_IP5)
 306                 do_IRQ(AR71XX_CPU_IRQ_GE1);
 307
 308         else if (pending & STATUSF_IP3)
 309                 do_IRQ(AR71XX_CPU_IRQ_USB);
 310
 311         else if (pending & STATUSF_IP6)
 312                 ar71xx_misc_irq_dispatch();
 313
 314         spurious_interrupt();
 315 }
 316
 317 void __init arch_init_irq(void)
 318 {
 319         switch (ar71xx_soc) {
 320         case AR71XX_SOC_AR7130:
 321         case AR71XX_SOC_AR7141:
 322         case AR71XX_SOC_AR7161:
 323                 ip2_handler = ar71xx_ip2_handler;
 324                 break;
 325
 326         case AR71XX_SOC_AR7240:
 327         case AR71XX_SOC_AR7241:
 328         case AR71XX_SOC_AR7242:
 329                 ip2_handler = ar724x_ip2_handler;
 330                 break;
 331
 332         case AR71XX_SOC_AR9130:
 333         case AR71XX_SOC_AR9132:
 334                 ip2_handler = ar913x_ip2_handler;
 335                 break;
 336
 337         case AR71XX_SOC_AR9330:
 338         case AR71XX_SOC_AR9331:
 339                 ip2_handler = ar933x_ip2_handler;
 340                 break;
 341
 342         case AR71XX_SOC_AR9341:
 343         case AR71XX_SOC_AR9342:
 344         case AR71XX_SOC_AR9344:
 345                 ip2_handler = ar934x_ip2_handler;
 346                 break;
 347
 348         default:
 349                 BUG();
 350         }
 351
 352         mips_cpu_irq_init();
 353
 354         ar71xx_misc_irq_init();
 355
 356         cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
 357
 358         ar71xx_gpio_irq_init();
 359 }