target/linux/ar71xx/files/arch/mips/ar71xx/mach-dir825b1.c

   1 /*
   2  *  D-Link DIR-825 rev. B1 board support
   3  *
   4  *  Copyright (C) 2009 Lukas Kuna, Evkanet, s.r.o.
   5  *
   6  *  based on mach-wndr3700.c
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/mtd/mtd.h>
  15 #include <linux/mtd/partitions.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/spi/flash.h>
  18 #include <linux/input.h>
  19
  20 #include <asm/mips_machine.h>
  21 #include <asm/mach-ar71xx/ar71xx.h>
  22 #include <asm/mach-ar71xx/pci.h>
  23
  24 #include <linux/pci.h>
  25 #include <linux/ath9k_platform.h>
  26 #include <linux/delay.h>
  27
  28 #include "devices.h"
  29
  30
  31 #define DIR825B1_GPIO_LED_BLUE_USB              0
  32 #define DIR825B1_GPIO_LED_ORANGE_POWER          1
  33 #define DIR825B1_GPIO_LED_BLUE_POWER            2
  34 #define DIR825B1_GPIO_LED_BLUE_POWERSAVE        4
  35 #define DIR825B1_GPIO_LED_ORANGE_PLANET         6
  36 #define DIR825B1_GPIO_LED_BLUE_PLANET           11
  37
  38 #define DIR825B1_GPIO_BTN_RESET                 3
  39 #define DIR825B1_GPIO_BTN_POWERSAVE             8
  40
  41 #define DIR825B1_BUTTONS_POLL_INTERVAL          20
  42
  43
  44 #define DIR825B1_CAL_LOCATION_0                 0xbf661000
  45 #define DIR825B1_CAL_LOCATION_1                 0xbf665000
  46
  47 #define DIR825B1_MAC_LOCATION_0                 0x2ffa81b8
  48 #define DIR825B1_MAC_LOCATION_1                 0x2ffa8370
  49
  50
  51 static struct ath9k_platform_data dir825b1_wmac0_data;
  52 static struct ath9k_platform_data dir825b1_wmac1_data;
  53 static char dir825b1_wmac0_mac[6];
  54 static char dir825b1_wmac1_mac[6];
  55
  56
  57 #ifdef CONFIG_MTD_PARTITIONS
  58 static struct mtd_partition dir825b1_partitions[] = {
  59         {
  60                 .name           = "uboot",
  61                 .offset         = 0,
  62                 .size           = 0x040000,
  63                 .mask_flags     = MTD_WRITEABLE,
  64         } , {
  65                 .name           = "config",
  66                 .offset         = 0x040000,
  67                 .size           = 0x010000,
  68                 .mask_flags     = MTD_WRITEABLE,
  69         } , {
  70                 .name           = "firmware",
  71                 .offset         = 0x050000,
  72                 .size           = 0x610000,
  73         } , {
  74                 .name           = "caldata",
  75                 .offset         = 0x660000,
  76                 .size           = 0x010000,
  77                 .mask_flags     = MTD_WRITEABLE,
  78         }
  79 };
  80 #endif /* CONFIG_MTD_PARTITIONS */
  81
  82
  83 static struct flash_platform_data dir825b1_flash_data = {
  84 #ifdef CONFIG_MTD_PARTITIONS
  85         .parts          = dir825b1_partitions,
  86         .nr_parts       = ARRAY_SIZE(dir825b1_partitions),
  87 #endif
  88 };
  89
  90
  91 static struct spi_board_info dir825b1_spi_info[] = {
  92         {
  93                 .bus_num        = 0,
  94                 .chip_select    = 0,
  95                 .max_speed_hz   = 25000000,
  96                 .modalias       = "m25p80",
  97                 .platform_data  = &dir825b1_flash_data,
  98         }
  99 };
 100
 101
 102 static struct gpio_led dir825b1_leds_gpio[] __initdata = {
 103         {
 104                 .name           = "dir825b1:blue:usb",
 105                 .gpio           = DIR825B1_GPIO_LED_BLUE_USB,
 106                 .active_low     = 1,
 107         }, {
 108                 .name           = "dir825b1:orange:power",
 109                 .gpio           = DIR825B1_GPIO_LED_ORANGE_POWER,
 110                 .active_low     = 1,
 111         }, {
 112                 .name           = "dir825b1:blue:power",
 113                 .gpio           = DIR825B1_GPIO_LED_BLUE_POWER,
 114                 .active_low     = 1,
 115         }, {
 116                 .name           = "dir825b1:blue:powersave",
 117                 .gpio           = DIR825B1_GPIO_LED_BLUE_POWERSAVE,
 118                 .active_low     = 1,
 119         }, {
 120                 .name           = "dir825b1:orange:planet",
 121                 .gpio           = DIR825B1_GPIO_LED_ORANGE_PLANET,
 122                 .active_low     = 1,
 123         }, {
 124                 .name           = "dir825b1:blue:planet",
 125                 .gpio           = DIR825B1_GPIO_LED_BLUE_PLANET,
 126                 .active_low     = 1,
 127         }
 128 };
 129
 130
 131 static struct gpio_button dir825b1_gpio_buttons[] __initdata = {
 132         {
 133                 .desc           = "reset",
 134                 .type           = EV_KEY,
 135                 .code           = BTN_0,
 136                 .threshold      = 5,
 137                 .gpio           = DIR825B1_GPIO_BTN_RESET,
 138                 .active_low     = 1,
 139         } , {
 140                 .desc           = "powersave",
 141                 .type           = EV_KEY,
 142                 .code           = BTN_1,
 143                 .threshold      = 5,
 144                 .gpio           = DIR825B1_GPIO_BTN_POWERSAVE,
 145                 .active_low     = 1,
 146         }
 147 };
 148
 149
 150 #ifdef CONFIG_PCI
 151 static struct ar71xx_pci_irq dir825b1_pci_irqs[] __initdata = {
 152         {
 153                 .slot   = 0,
 154                 .pin    = 1,
 155                 .irq    = AR71XX_PCI_IRQ_DEV0,
 156         }, {
 157                 .slot   = 1,
 158                 .pin    = 1,
 159                 .irq    = AR71XX_PCI_IRQ_DEV1,
 160         }
 161 };
 162
 163
 164 static int dir825b1_pci_plat_dev_init(struct pci_dev *dev)
 165 {
 166         switch(PCI_SLOT(dev->devfn))
 167         {
 168                 case 17:
 169                         dev->dev.platform_data = &dir825b1_wmac0_data;
 170                         break;
 171
 172                 case 18:
 173                         dev->dev.platform_data = &dir825b1_wmac1_data;
 174                         break;
 175         }
 176
 177         return(0);
 178 }
 179
 180
 181 static void dir825b1_pci_fixup(struct pci_dev *dev)
 182 {
 183         void __iomem *mem;
 184         u16 *cal_data;
 185         u16 cmd;
 186         u32 bar0;
 187         u32 val;
 188
 189         if (ar71xx_mach != AR71XX_MACH_DIR825B1) return;
 190
 191         dir825b1_pci_plat_dev_init(dev);
 192         cal_data = dev->dev.platform_data;
 193
 194         if (*cal_data != 0xa55a)
 195         {
 196                 printk(KERN_ERR "PCI: no calibration data found for %s\n",
 197                        pci_name(dev));
 198                 return;
 199         }
 200
 201         mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000);
 202         if (!mem)
 203         {
 204                 printk(KERN_ERR "PCI: ioremap error for device %s\n",
 205                        pci_name(dev));
 206                 return;
 207         }
 208
 209         printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev));
 210
 211         pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
 212
 213         /* Setup the PCI device to allow access to the internal registers */
 214         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, AR71XX_PCI_MEM_BASE);
 215         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 216         cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 217         pci_write_config_word(dev, PCI_COMMAND, cmd);
 218
 219         /* set pointer to first reg address */
 220         cal_data += 3;
 221         while (*cal_data != 0xffff)
 222         {
 223                 u32 reg;
 224                 reg = *cal_data++;
 225                 val = *cal_data++;
 226                 val |= (*cal_data++) << 16;
 227
 228                 __raw_writel(val, mem + reg);
 229                 udelay(100);
 230         }
 231
 232         pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
 233         dev->vendor = val & 0xffff;
 234         dev->device = (val >> 16) & 0xffff;
 235
 236         pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
 237         dev->revision = val & 0xff;
 238         dev->class = val >> 8; /* upper 3 bytes */
 239
 240         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 241         cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 242         pci_write_config_word(dev, PCI_COMMAND, cmd);
 243
 244         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
 245
 246         iounmap(mem);
 247 }
 248 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID,
 249                         dir825b1_pci_fixup);
 250
 251
 252 static void __init dir825b1_pci_init(void)
 253 {
 254         memcpy(dir825b1_wmac0_data.eeprom_data,
 255                (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0),
 256                sizeof(dir825b1_wmac0_data.eeprom_data));
 257
 258         memcpy(dir825b1_wmac1_data.eeprom_data,
 259                (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1),
 260                sizeof(dir825b1_wmac1_data.eeprom_data));
 261
 262         memcpy(dir825b1_wmac0_mac, (u8 *)KSEG1ADDR(DIR825B1_MAC_LOCATION_0), 6);
 263         dir825b1_wmac0_data.macaddr = dir825b1_wmac0_mac;
 264         memcpy(dir825b1_wmac1_mac, (u8 *)KSEG1ADDR(DIR825B1_MAC_LOCATION_1), 6);
 265         dir825b1_wmac1_data.macaddr = dir825b1_wmac1_mac;
 266
 267         ar71xx_pci_plat_dev_init = dir825b1_pci_plat_dev_init;
 268         ar71xx_pci_init(ARRAY_SIZE(dir825b1_pci_irqs), dir825b1_pci_irqs);
 269 }
 270 #else
 271 static void __init dir825b1_pci_init(void) { }
 272 #endif /* CONFIG_PCI */
 273
 274
 275 static void __init dir825b1_setup(void)
 276 {
 277         u8 mac[6], i;
 278
 279         memcpy(mac, (u8*)KSEG1ADDR(DIR825B1_MAC_LOCATION_1), 6);
 280         for(i = 5; i >= 3; i--)
 281                 if(++mac[i] != 0x00) break;
 282
 283         ar71xx_set_mac_base(mac);
 284
 285         ar71xx_add_device_mdio(0x0);
 286
 287         ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 288         ar71xx_eth0_data.phy_mask = 0x1E;
 289         ar71xx_eth0_data.speed = SPEED_1000;
 290         ar71xx_eth0_data.duplex = DUPLEX_FULL;
 291         ar71xx_eth0_pll_data.pll_1000 = 0x11110000;
 292
 293         ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 294         ar71xx_eth1_data.phy_mask = 0xC0;
 295         ar71xx_eth1_data.speed = SPEED_1000;
 296         ar71xx_eth1_data.duplex = DUPLEX_FULL;
 297         ar71xx_eth1_pll_data.pll_1000 = 0x11110000;
 298
 299         ar71xx_add_device_eth(0);
 300         ar71xx_add_device_eth(1);
 301
 302         ar71xx_add_device_spi(NULL, dir825b1_spi_info,
 303                               ARRAY_SIZE(dir825b1_spi_info));
 304
 305         ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio),
 306                                         dir825b1_leds_gpio);
 307
 308         ar71xx_add_device_gpio_buttons(-1, DIR825B1_BUTTONS_POLL_INTERVAL,
 309                                         ARRAY_SIZE(dir825b1_gpio_buttons),
 310                                         dir825b1_gpio_buttons);
 311
 312         ar71xx_add_device_usb();
 313
 314         dir825b1_pci_init();
 315 }
 316
 317 MIPS_MACHINE(AR71XX_MACH_DIR825B1, "D-Link DIR825B1", dir825b1_setup);