target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c

   1 /*
   2  *  Atheros PB42 board support
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/bitops.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/spi/spi.h>
  16 #include <linux/spi/flash.h>
  17
  18 #include <asm/mips_machine.h>
  19 #include <asm/mach-ar71xx/ar71xx.h>
  20 #include <asm/mach-ar71xx/pci.h>
  21
  22 #include "devices.h"
  23
  24 static struct spi_board_info pb42_spi_info[] = {
  25         {
  26                 .bus_num        = 0,
  27                 .chip_select    = 0,
  28                 .max_speed_hz   = 25000000,
  29                 .modalias       = "m25p80",
  30         }
  31 };
  32
  33 static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = {
  34         {
  35                 .slot   = 0,
  36                 .pin    = 1,
  37                 .irq    = AR71XX_PCI_IRQ_DEV0,
  38         }, {
  39                 .slot   = 1,
  40                 .pin    = 1,
  41                 .irq    = AR71XX_PCI_IRQ_DEV1,
  42         }, {
  43                 .slot   = 2,
  44                 .pin    = 1,
  45                 .irq    = AR71XX_PCI_IRQ_DEV2,
  46         }
  47 };
  48
  49 #define PB42_WAN_PHYMASK        BIT(20)
  50 #define PB42_LAN_PHYMASK        (BIT(16) | BIT(17) | BIT(18) | BIT(19))
  51 #define PB42_MDIO_PHYMASK       (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK)
  52
  53 static void __init pb42_init(void)
  54 {
  55         ar71xx_add_device_spi(NULL, pb42_spi_info,
  56                                 ARRAY_SIZE(pb42_spi_info));
  57
  58         ar71xx_add_device_mdio(~PB42_MDIO_PHYMASK);
  59
  60         ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  61         ar71xx_eth0_data.phy_mask = PB42_WAN_PHYMASK;
  62
  63         ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  64         ar71xx_eth1_data.phy_mask = PB42_LAN_PHYMASK;
  65         ar71xx_eth1_data.speed = SPEED_100;
  66         ar71xx_eth1_data.duplex = DUPLEX_FULL;
  67
  68         ar71xx_add_device_eth(0);
  69         ar71xx_add_device_eth(1);
  70
  71         ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs);
  72 }
  73
  74 MIPS_MACHINE(AR71XX_MACH_PB42, "Atheros PB42", pb42_init);