target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c

   1 /*
   2  *  Atheros PB42 board support
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/bitops.h>
  14 #include <linux/platform_device.h>
  15
  16 #include <asm/mips_machine.h>
  17 #include <asm/mach-ar71xx/ar71xx.h>
  18
  19 #include "devices.h"
  20 #include "dev-m25p80.h"
  21 #include "dev-gpio-buttons.h"
  22 #include "dev-pb42-pci.h"
  23
  24 #define PB42_BUTTONS_POLL_INTERVAL      20
  25
  26 #define PB42_GPIO_BTN_SW4       8
  27 #define PB42_GPIO_BTN_SW5       3
  28
  29 static struct gpio_button pb42_gpio_buttons[] __initdata = {
  30         {
  31                 .desc           = "sw4",
  32                 .type           = EV_KEY,
  33                 .code           = BTN_0,
  34                 .threshold      = 5,
  35                 .gpio           = PB42_GPIO_BTN_SW4,
  36                 .active_low     = 1,
  37         } , {
  38                 .desc           = "sw5",
  39                 .type           = EV_KEY,
  40                 .code           = BTN_1,
  41                 .threshold      = 5,
  42                 .gpio           = PB42_GPIO_BTN_SW5,
  43                 .active_low     = 1,
  44         }
  45 };
  46
  47 #define PB42_WAN_PHYMASK        BIT(20)
  48 #define PB42_LAN_PHYMASK        (BIT(16) | BIT(17) | BIT(18) | BIT(19))
  49 #define PB42_MDIO_PHYMASK       (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK)
  50
  51 static void __init pb42_init(void)
  52 {
  53         ar71xx_add_device_m25p80(NULL);
  54
  55         ar71xx_add_device_mdio(~PB42_MDIO_PHYMASK);
  56
  57         ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  58         ar71xx_eth0_data.phy_mask = PB42_WAN_PHYMASK;
  59
  60         ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  61         ar71xx_eth1_data.phy_mask = PB42_LAN_PHYMASK;
  62         ar71xx_eth1_data.speed = SPEED_100;
  63         ar71xx_eth1_data.duplex = DUPLEX_FULL;
  64
  65         ar71xx_add_device_eth(0);
  66         ar71xx_add_device_eth(1);
  67
  68         ar71xx_add_device_gpio_buttons(-1, PB42_BUTTONS_POLL_INTERVAL,
  69                                        ARRAY_SIZE(pb42_gpio_buttons),
  70                                        pb42_gpio_buttons);
  71
  72         pb42_pci_init();
  73 }
  74
  75 MIPS_MACHINE(AR71XX_MACH_PB42, "Atheros PB42", pb42_init);