target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/serial_8250.h>
  17 #include <linux/bootmem.h>
  18
  19 #include <asm/bootinfo.h>
  20 #include <asm/time.h>           /* for mips_hpt_frequency */
  21 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  22 #include <asm/mips_machine.h>
  23
  24 #include <asm/mach-ar71xx/ar71xx.h>
  25 #include <asm/mach-ar71xx/pci.h>
  26
  27 #include "machtype.h"
  28 #include "devices.h"
  29
  30 #define AR71XX_SYS_TYPE_LEN     64
  31 #define AR71XX_BASE_FREQ        40000000
  32 #define AR91XX_BASE_FREQ        5000000
  33 #define AR724X_BASE_FREQ        5000000
  34
  35 u32 ar71xx_cpu_freq;
  36 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  37
  38 u32 ar71xx_ahb_freq;
  39 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  40
  41 u32 ar71xx_ddr_freq;
  42 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  43
  44 enum ar71xx_soc_type ar71xx_soc;
  45 EXPORT_SYMBOL_GPL(ar71xx_soc);
  46
  47 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  48
  49 static void ar71xx_restart(char *command)
  50 {
  51         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  52         for (;;)
  53                 if (cpu_wait)
  54                         cpu_wait();
  55 }
  56
  57 static void ar71xx_halt(void)
  58 {
  59         while (1)
  60                 cpu_wait();
  61 }
  62
  63 static void __init ar71xx_detect_mem_size(void)
  64 {
  65         unsigned long size;
  66
  67         for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
  68              size <<= 1 ) {
  69                 if (!memcmp(ar71xx_detect_mem_size,
  70                             ar71xx_detect_mem_size + size, 1024))
  71                         break;
  72         }
  73
  74         add_memory_region(0, size, BOOT_MEM_RAM);
  75 }
  76
  77 static void __init ar71xx_detect_sys_type(void)
  78 {
  79         char *chip = "????";
  80         u32 id;
  81         u32 major;
  82         u32 minor;
  83         u32 rev = 0;
  84
  85         id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
  86         major = id & REV_ID_MAJOR_MASK;
  87
  88         switch (major) {
  89         case REV_ID_MAJOR_AR71XX:
  90                 minor = id & AR71XX_REV_ID_MINOR_MASK;
  91                 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
  92                 rev &= AR71XX_REV_ID_REVISION_MASK;
  93                 switch (minor) {
  94                 case AR71XX_REV_ID_MINOR_AR7130:
  95                         ar71xx_soc = AR71XX_SOC_AR7130;
  96                         chip = "7130";
  97                         break;
  98
  99                 case AR71XX_REV_ID_MINOR_AR7141:
 100                         ar71xx_soc = AR71XX_SOC_AR7141;
 101                         chip = "7141";
 102                         break;
 103
 104                 case AR71XX_REV_ID_MINOR_AR7161:
 105                         ar71xx_soc = AR71XX_SOC_AR7161;
 106                         chip = "7161";
 107                         break;
 108                 }
 109                 break;
 110
 111         case REV_ID_MAJOR_AR724X:
 112                 ar71xx_soc = AR71XX_SOC_AR7240;
 113                 chip = "7240";
 114                 rev = (id & AR724X_REV_ID_REVISION_MASK);
 115                 break;
 116
 117         case REV_ID_MAJOR_AR913X:
 118                 minor = id & AR91XX_REV_ID_MINOR_MASK;
 119                 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
 120                 rev &= AR91XX_REV_ID_REVISION_MASK;
 121                 switch (minor) {
 122                 case AR91XX_REV_ID_MINOR_AR9130:
 123                         ar71xx_soc = AR71XX_SOC_AR9130;
 124                         chip = "9130";
 125                         break;
 126
 127                 case AR91XX_REV_ID_MINOR_AR9132:
 128                         ar71xx_soc = AR71XX_SOC_AR9132;
 129                         chip = "9132";
 130                         break;
 131                 }
 132                 break;
 133
 134         default:
 135                 panic("ar71xx: unknown chip id:0x%08x\n", id);
 136         }
 137
 138         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
 139 }
 140
 141 static void __init ar91xx_detect_sys_frequency(void)
 142 {
 143         u32 pll;
 144         u32 freq;
 145         u32 div;
 146
 147         pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 148
 149         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 150         freq = div * AR91XX_BASE_FREQ;
 151
 152         ar71xx_cpu_freq = freq;
 153
 154         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 155         ar71xx_ddr_freq = freq / div;
 156
 157         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 158         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 159 }
 160
 161 static void __init ar71xx_detect_sys_frequency(void)
 162 {
 163         u32 pll;
 164         u32 freq;
 165         u32 div;
 166
 167         pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 168
 169         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 170         freq = div * AR71XX_BASE_FREQ;
 171
 172         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 173         ar71xx_cpu_freq = freq / div;
 174
 175         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 176         ar71xx_ddr_freq = freq / div;
 177
 178         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 179         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 180 }
 181
 182 static void __init ar724x_detect_sys_frequency(void)
 183 {
 184         u32 pll;
 185         u32 freq;
 186         u32 div;
 187
 188         pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
 189
 190         div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
 191         freq = div * AR724X_BASE_FREQ;
 192
 193         div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
 194         freq *= div;
 195
 196         ar71xx_cpu_freq = freq;
 197
 198         div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
 199         ar71xx_ddr_freq = freq / div;
 200
 201         div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
 202         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 203 }
 204
 205 static void __init detect_sys_frequency(void)
 206 {
 207         switch (ar71xx_soc) {
 208         case AR71XX_SOC_AR7130:
 209         case AR71XX_SOC_AR7141:
 210         case AR71XX_SOC_AR7161:
 211                 ar71xx_detect_sys_frequency();
 212                 break;
 213
 214         case AR71XX_SOC_AR7240:
 215                 ar724x_detect_sys_frequency();
 216                 break;
 217
 218         case AR71XX_SOC_AR9130:
 219         case AR71XX_SOC_AR9132:
 220                 ar91xx_detect_sys_frequency();
 221                 break;
 222
 223         default:
 224                 BUG();
 225         }
 226 }
 227
 228 const char *get_system_type(void)
 229 {
 230         return ar71xx_sys_type;
 231 }
 232
 233 unsigned int __cpuinit get_c0_compare_irq(void)
 234 {
 235         return CP0_LEGACY_COMPARE_IRQ;
 236 }
 237
 238 void __init plat_mem_setup(void)
 239 {
 240         set_io_port_base(KSEG1);
 241
 242         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 243                                                 AR71XX_DDR_CTRL_SIZE);
 244
 245         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 246                                                 AR71XX_PLL_SIZE);
 247
 248         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 249                                                 AR71XX_RESET_SIZE);
 250
 251         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 252
 253         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 254                                                 AR71XX_USB_CTRL_SIZE);
 255
 256         ar71xx_detect_mem_size();
 257         ar71xx_detect_sys_type();
 258         detect_sys_frequency();
 259
 260         printk(KERN_INFO
 261                 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
 262                 ar71xx_sys_type,
 263                 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
 264                 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
 265                 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
 266
 267         _machine_restart = ar71xx_restart;
 268         _machine_halt = ar71xx_halt;
 269         pm_power_off = ar71xx_halt;
 270 }
 271
 272 void __init plat_time_init(void)
 273 {
 274         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 275 }
 276
 277 __setup("board=", mips_machtype_setup);
 278
 279 static int __init ar71xx_machine_setup(void)
 280 {
 281         ar71xx_gpio_init();
 282
 283         ar71xx_add_device_uart();
 284         ar71xx_add_device_wdt();
 285
 286         mips_machine_setup();
 287         return 0;
 288 }
 289
 290 arch_initcall(ar71xx_machine_setup);