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[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/phy.h>
29 #include <linux/skbuff.h>
30 #include <linux/dma-mapping.h>
31
32 #include <linux/bitops.h>
33
34 #include <asm/mach-ar71xx/ar71xx.h>
35 #include <asm/mach-ar71xx/platform.h>
36
37 #define ETH_FCS_LEN 4
38
39 #define AG71XX_DRV_NAME "ag71xx"
40 #define AG71XX_DRV_VERSION "0.4.2"
41
42 #define AG71XX_NAPI_TX 1
43
44 #define AG71XX_NAPI_WEIGHT 64
45
46 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
47 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
48 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
49
50 #ifdef AG71XX_NAPI_TX
51 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
52 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
53 #else
54 #define AG71XX_INT_POLL (AG71XX_INT_RX)
55 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL | AG71XX_INT_TX)
56 #endif
57
58 #define AG71XX_TX_FIFO_LEN 2048
59 #define AG71XX_TX_MTU_LEN 1536
60 #define AG71XX_RX_PKT_RESERVE 64
61 #define AG71XX_RX_PKT_SIZE \
62 (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
63
64 #define AG71XX_TX_RING_SIZE 64
65 #define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
66 #define AG71XX_TX_THRES_WAKEUP \
67 (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
68
69 #define AG71XX_RX_RING_SIZE 128
70
71 #undef AG71XX_DEBUG
72 #ifdef AG71XX_DEBUG
73 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
74 #else
75 #define DBG(fmt, args...) do {} while (0)
76 #endif
77
78 #define ag71xx_assert(_cond) \
79 do { \
80 if (_cond) \
81 break; \
82 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
83 BUG(); \
84 } while (0)
85
86 struct ag71xx_desc {
87 u32 data;
88 u32 ctrl;
89 #define DESC_EMPTY BIT(31)
90 #define DESC_MORE BIT(24)
91 #define DESC_PKTLEN_M 0x1fff
92 u32 next;
93 };
94
95 struct ag71xx_buf {
96 struct sk_buff *skb;
97 };
98
99 struct ag71xx_ring {
100 struct ag71xx_buf *buf;
101 struct ag71xx_desc *descs;
102 dma_addr_t descs_dma;
103 unsigned int curr;
104 unsigned int dirty;
105 unsigned int size;
106 };
107
108 struct ag71xx_mdio {
109 struct mii_bus mii_bus;
110 int mii_irq[PHY_MAX_ADDR];
111 void __iomem *mdio_base;
112 };
113
114 struct ag71xx {
115 void __iomem *mac_base;
116 void __iomem *mac_base2;
117 void __iomem *mii_ctrl;
118
119 spinlock_t lock;
120 struct platform_device *pdev;
121 struct net_device *dev;
122 struct napi_struct napi;
123 u32 msg_enable;
124
125 struct ag71xx_ring rx_ring;
126 struct ag71xx_ring tx_ring;
127
128 struct mii_bus *mii_bus;
129 struct phy_device *phy_dev;
130
131 unsigned int link;
132 unsigned int speed;
133 int duplex;
134 };
135
136 extern struct ethtool_ops ag71xx_ethtool_ops;
137
138 extern struct ag71xx_mdio *ag71xx_mdio_bus;
139 extern int ag71xx_mdio_driver_init(void) __init;
140 extern void ag71xx_mdio_driver_exit(void);
141
142 extern int ag71xx_phy_connect(struct ag71xx *ag);
143 extern void ag71xx_phy_disconnect(struct ag71xx *ag);
144 extern void ag71xx_phy_start(struct ag71xx *ag);
145 extern void ag71xx_phy_stop(struct ag71xx *ag);
146
147 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
148 {
149 return ag->pdev->dev.platform_data;
150 }
151
152 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
153 {
154 return ((desc->ctrl & DESC_EMPTY) != 0);
155 }
156
157 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
158 {
159 return (desc->ctrl & DESC_PKTLEN_M);
160 }
161
162 /* Register offsets */
163 #define AG71XX_REG_MAC_CFG1 0x0000
164 #define AG71XX_REG_MAC_CFG2 0x0004
165 #define AG71XX_REG_MAC_IPG 0x0008
166 #define AG71XX_REG_MAC_HDX 0x000c
167 #define AG71XX_REG_MAC_MFL 0x0010
168 #define AG71XX_REG_MII_CFG 0x0020
169 #define AG71XX_REG_MII_CMD 0x0024
170 #define AG71XX_REG_MII_ADDR 0x0028
171 #define AG71XX_REG_MII_CTRL 0x002c
172 #define AG71XX_REG_MII_STATUS 0x0030
173 #define AG71XX_REG_MII_IND 0x0034
174 #define AG71XX_REG_MAC_IFCTL 0x0038
175 #define AG71XX_REG_MAC_ADDR1 0x0040
176 #define AG71XX_REG_MAC_ADDR2 0x0044
177 #define AG71XX_REG_FIFO_CFG0 0x0048
178 #define AG71XX_REG_FIFO_CFG1 0x004c
179 #define AG71XX_REG_FIFO_CFG2 0x0050
180 #define AG71XX_REG_FIFO_CFG3 0x0054
181 #define AG71XX_REG_FIFO_CFG4 0x0058
182 #define AG71XX_REG_FIFO_CFG5 0x005c
183 #define AG71XX_REG_FIFO_RAM0 0x0060
184 #define AG71XX_REG_FIFO_RAM1 0x0064
185 #define AG71XX_REG_FIFO_RAM2 0x0068
186 #define AG71XX_REG_FIFO_RAM3 0x006c
187 #define AG71XX_REG_FIFO_RAM4 0x0070
188 #define AG71XX_REG_FIFO_RAM5 0x0074
189 #define AG71XX_REG_FIFO_RAM6 0x0078
190 #define AG71XX_REG_FIFO_RAM7 0x007c
191
192 #define AG71XX_REG_TX_CTRL 0x0180
193 #define AG71XX_REG_TX_DESC 0x0184
194 #define AG71XX_REG_TX_STATUS 0x0188
195 #define AG71XX_REG_RX_CTRL 0x018c
196 #define AG71XX_REG_RX_DESC 0x0190
197 #define AG71XX_REG_RX_STATUS 0x0194
198 #define AG71XX_REG_INT_ENABLE 0x0198
199 #define AG71XX_REG_INT_STATUS 0x019c
200
201 #define MAC_CFG1_TXE BIT(0)
202 #define MAC_CFG1_STX BIT(1)
203 #define MAC_CFG1_RXE BIT(2)
204 #define MAC_CFG1_SRX BIT(3)
205 #define MAC_CFG1_LB BIT(8)
206 #define MAC_CFG1_SR BIT(31)
207
208 #define MAC_CFG2_FDX BIT(0)
209 #define MAC_CFG2_CRC_EN BIT(1)
210 #define MAC_CFG2_PAD_CRC_EN BIT(2)
211 #define MAC_CFG2_LEN_CHECK BIT(4)
212 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
213 #define MAC_CFG2_IF_1000 BIT(9)
214 #define MAC_CFG2_IF_10_100 BIT(8)
215
216 #define AG71XX_INT_TX_PS BIT(0)
217 #define AG71XX_INT_TX_UR BIT(1)
218 #define AG71XX_INT_TX_BE BIT(3)
219 #define AG71XX_INT_RX_PR BIT(4)
220 #define AG71XX_INT_RX_OF BIT(6)
221 #define AG71XX_INT_RX_BE BIT(7)
222
223 #define MAC_IFCTL_SPEED BIT(16)
224
225 #define MII_CFG_CLK_DIV_4 0
226 #define MII_CFG_CLK_DIV_6 2
227 #define MII_CFG_CLK_DIV_8 3
228 #define MII_CFG_CLK_DIV_10 4
229 #define MII_CFG_CLK_DIV_14 5
230 #define MII_CFG_CLK_DIV_20 6
231 #define MII_CFG_CLK_DIV_28 7
232 #define MII_CFG_RESET BIT(31)
233
234 #define MII_CMD_WRITE 0x0
235 #define MII_CMD_READ 0x1
236 #define MII_ADDR_S 8
237 #define MII_IND_BUSY BIT(0)
238 #define MII_IND_INVALID BIT(2)
239
240 #define TX_CTRL_TXE BIT(0)
241
242 #define TX_STATUS_PS BIT(0)
243 #define TX_STATUS_UR BIT(1)
244 #define TX_STATUS_BE BIT(3)
245
246 #define RX_CTRL_RXE BIT(0)
247
248 #define RX_STATUS_PR BIT(0)
249 #define RX_STATUS_OF BIT(1)
250 #define RX_STATUS_BE BIT(3)
251
252 #define FIFO_CFG5_BYTE_PER_CLK BIT(19)
253
254 #define MII_CTRL_IF_MASK 3
255 #define MII_CTRL_SPEED_SHIFT 4
256 #define MII_CTRL_SPEED_MASK 3
257 #define MII_CTRL_SPEED_10 0
258 #define MII_CTRL_SPEED_100 1
259 #define MII_CTRL_SPEED_1000 2
260
261 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
262 {
263 switch (reg) {
264 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
265 __raw_writel(value, ag->mac_base + reg);
266 break;
267 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
268 reg -= AG71XX_REG_MAC_IFCTL;
269 __raw_writel(value, ag->mac_base2 + reg);
270 break;
271 default:
272 BUG();
273 }
274 }
275
276 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
277 {
278 u32 ret;
279
280 switch (reg) {
281 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
282 ret = __raw_readl(ag->mac_base + reg);
283 break;
284 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
285 reg -= AG71XX_REG_MAC_IFCTL;
286 ret = __raw_readl(ag->mac_base2 + reg);
287 break;
288 }
289
290 return ret;
291 }
292
293 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
294 {
295 void __iomem *r;
296
297 switch (reg) {
298 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
299 r = ag->mac_base + reg;
300 __raw_writel(__raw_readl(r) | mask, r);
301 break;
302 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
303 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
304 __raw_writel(__raw_readl(r) | mask, r);
305 break;
306 default:
307 BUG();
308 }
309 }
310
311 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
312 {
313 void __iomem *r;
314
315 switch (reg) {
316 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
317 r = ag->mac_base + reg;
318 __raw_writel(__raw_readl(r) & ~mask, r);
319 break;
320 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
321 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
322 __raw_writel(__raw_readl(r) & ~mask, r);
323 break;
324 default:
325 BUG();
326 }
327 }
328
329 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
330 {
331 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
332 }
333
334 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
335 {
336 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
337 }
338
339 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
340 {
341 __raw_writel(value, ag->mii_ctrl);
342 }
343
344 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
345 {
346 return __raw_readl(ag->mii_ctrl);
347 }
348
349 static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
350 unsigned int mii_if)
351 {
352 u32 t;
353
354 t = ag71xx_mii_ctrl_rr(ag);
355 t &= ~(MII_CTRL_IF_MASK);
356 t |= (mii_if & MII_CTRL_IF_MASK);
357 ag71xx_mii_ctrl_wr(ag, t);
358 }
359
360 static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
361 unsigned int speed)
362 {
363 u32 t;
364
365 t = ag71xx_mii_ctrl_rr(ag);
366 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
367 t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
368 ag71xx_mii_ctrl_wr(ag, t);
369 }
370
371 #endif /* _AG71XX_H */
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