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ar71xx: ag71xx: setup switch interface mode on AR934X
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
31
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
34
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
37
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
40
41 #define AR7240_REG_VTU 0x0040
42 #define AR7240_VTU_OP BITM(3)
43 #define AR7240_VTU_OP_NOOP 0x0
44 #define AR7240_VTU_OP_FLUSH 0x1
45 #define AR7240_VTU_OP_LOAD 0x2
46 #define AR7240_VTU_OP_PURGE 0x3
47 #define AR7240_VTU_OP_REMOVE_PORT 0x4
48 #define AR7240_VTU_ACTIVE BIT(3)
49 #define AR7240_VTU_FULL BIT(4)
50 #define AR7240_VTU_PORT BITS(8, 4)
51 #define AR7240_VTU_PORT_S 8
52 #define AR7240_VTU_VID BITS(16, 12)
53 #define AR7240_VTU_VID_S 16
54 #define AR7240_VTU_PRIO BITS(28, 3)
55 #define AR7240_VTU_PRIO_S 28
56 #define AR7240_VTU_PRIO_EN BIT(31)
57
58 #define AR7240_REG_VTU_DATA 0x0044
59 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
60 #define AR7240_VTUDATA_VALID BIT(11)
61
62 #define AR7240_REG_ATU 0x50
63 #define AR7240_ATU_FLUSH_ALL 0x1
64
65 #define AR7240_REG_AT_CTRL 0x5c
66 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
67 #define AR7240_AT_CTRL_AGE_EN BIT(17)
68 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
69 #define AR7240_AT_CTRL_ARP_EN BIT(20)
70
71 #define AR7240_REG_TAG_PRIORITY 0x70
72
73 #define AR7240_REG_SERVICE_TAG 0x74
74 #define AR7240_SERVICE_TAG_M BITM(16)
75
76 #define AR7240_REG_CPU_PORT 0x78
77 #define AR7240_MIRROR_PORT_S 4
78 #define AR7240_CPU_PORT_EN BIT(8)
79
80 #define AR7240_REG_MIB_FUNCTION0 0x80
81 #define AR7240_MIB_TIMER_M BITM(16)
82 #define AR7240_MIB_AT_HALF_EN BIT(16)
83 #define AR7240_MIB_BUSY BIT(17)
84 #define AR7240_MIB_FUNC_S 24
85 #define AR7240_MIB_FUNC_NO_OP 0x0
86 #define AR7240_MIB_FUNC_FLUSH 0x1
87 #define AR7240_MIB_FUNC_CAPTURE 0x3
88
89 #define AR7240_REG_MDIO_CTRL 0x98
90 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
91 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
92 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
93 #define AR7240_MDIO_CTRL_CMD_WRITE 0
94 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
95 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
96 #define AR7240_MDIO_CTRL_BUSY BIT(31)
97
98 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
99
100 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
101 #define AR7240_PORT_STATUS_SPEED_S 0
102 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
103 #define AR7240_PORT_STATUS_SPEED_10 0
104 #define AR7240_PORT_STATUS_SPEED_100 1
105 #define AR7240_PORT_STATUS_SPEED_1000 2
106 #define AR7240_PORT_STATUS_TXMAC BIT(2)
107 #define AR7240_PORT_STATUS_RXMAC BIT(3)
108 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
109 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
110 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
111 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
112 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
113 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
114
115 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
116 #define AR7240_PORT_CTRL_STATE_M BITM(3)
117 #define AR7240_PORT_CTRL_STATE_DISABLED 0
118 #define AR7240_PORT_CTRL_STATE_BLOCK 1
119 #define AR7240_PORT_CTRL_STATE_LISTEN 2
120 #define AR7240_PORT_CTRL_STATE_LEARN 3
121 #define AR7240_PORT_CTRL_STATE_FORWARD 4
122 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
123 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
124 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
125 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
126 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
127 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
128 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
129 #define AR7240_PORT_CTRL_HEADER BIT(11)
130 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
131 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
132 #define AR7240_PORT_CTRL_LEARN BIT(14)
133 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
134 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
135 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
136
137 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
138
139 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
140 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
141 #define AR7240_PORT_VLAN_MODE_S 30
142 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
143 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
144 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
145 #define AR7240_PORT_VLAN_MODE_SECURE 3
146
147
148 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
149
150 #define AR7240_STATS_RXBROAD 0x00
151 #define AR7240_STATS_RXPAUSE 0x04
152 #define AR7240_STATS_RXMULTI 0x08
153 #define AR7240_STATS_RXFCSERR 0x0c
154 #define AR7240_STATS_RXALIGNERR 0x10
155 #define AR7240_STATS_RXRUNT 0x14
156 #define AR7240_STATS_RXFRAGMENT 0x18
157 #define AR7240_STATS_RX64BYTE 0x1c
158 #define AR7240_STATS_RX128BYTE 0x20
159 #define AR7240_STATS_RX256BYTE 0x24
160 #define AR7240_STATS_RX512BYTE 0x28
161 #define AR7240_STATS_RX1024BYTE 0x2c
162 #define AR7240_STATS_RX1518BYTE 0x30
163 #define AR7240_STATS_RXMAXBYTE 0x34
164 #define AR7240_STATS_RXTOOLONG 0x38
165 #define AR7240_STATS_RXGOODBYTE 0x3c
166 #define AR7240_STATS_RXBADBYTE 0x44
167 #define AR7240_STATS_RXOVERFLOW 0x4c
168 #define AR7240_STATS_FILTERED 0x50
169 #define AR7240_STATS_TXBROAD 0x54
170 #define AR7240_STATS_TXPAUSE 0x58
171 #define AR7240_STATS_TXMULTI 0x5c
172 #define AR7240_STATS_TXUNDERRUN 0x60
173 #define AR7240_STATS_TX64BYTE 0x64
174 #define AR7240_STATS_TX128BYTE 0x68
175 #define AR7240_STATS_TX256BYTE 0x6c
176 #define AR7240_STATS_TX512BYTE 0x70
177 #define AR7240_STATS_TX1024BYTE 0x74
178 #define AR7240_STATS_TX1518BYTE 0x78
179 #define AR7240_STATS_TXMAXBYTE 0x7c
180 #define AR7240_STATS_TXOVERSIZE 0x80
181 #define AR7240_STATS_TXBYTE 0x84
182 #define AR7240_STATS_TXCOLLISION 0x8c
183 #define AR7240_STATS_TXABORTCOL 0x90
184 #define AR7240_STATS_TXMULTICOL 0x94
185 #define AR7240_STATS_TXSINGLECOL 0x98
186 #define AR7240_STATS_TXEXCDEFER 0x9c
187 #define AR7240_STATS_TXDEFER 0xa0
188 #define AR7240_STATS_TXLATECOL 0xa4
189
190 #define AR7240_PORT_CPU 0
191 #define AR7240_NUM_PORTS 6
192 #define AR7240_NUM_PHYS 5
193
194 #define AR7240_PHY_ID1 0x004d
195 #define AR7240_PHY_ID2 0xd041
196
197 #define AR934X_PHY_ID1 0x004d
198 #define AR934X_PHY_ID2 0xd042
199
200 #define AR7240_MAX_VLANS 16
201
202 #define AR934X_REG_OPER_MODE0 0x04
203 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
204 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
205
206 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
207
208 struct ar7240sw {
209 struct mii_bus *mii_bus;
210 struct ag71xx_switch_platform_data *swdata;
211 struct switch_dev swdev;
212 int num_ports;
213 u8 ver;
214 bool vlan;
215 u16 vlan_id[AR7240_MAX_VLANS];
216 u8 vlan_table[AR7240_MAX_VLANS];
217 u8 vlan_tagged;
218 u16 pvid[AR7240_NUM_PORTS];
219 char buf[80];
220 };
221
222 struct ar7240sw_hw_stat {
223 char string[ETH_GSTRING_LEN];
224 int sizeof_stat;
225 int reg;
226 };
227
228 static DEFINE_MUTEX(reg_mutex);
229
230 static inline int sw_is_ar7240(struct ar7240sw *as)
231 {
232 return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
233 }
234
235 static inline int sw_is_ar934x(struct ar7240sw *as)
236 {
237 return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
238 }
239
240 static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
241 {
242 return BIT(port);
243 }
244
245 static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
246 {
247 return BIT(as->swdev.ports) - 1;
248 }
249
250 static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
251 {
252 return ar7240sw_port_mask_all(as) & ~BIT(port);
253 }
254
255 static inline u16 mk_phy_addr(u32 reg)
256 {
257 return 0x17 & ((reg >> 4) | 0x10);
258 }
259
260 static inline u16 mk_phy_reg(u32 reg)
261 {
262 return (reg << 1) & 0x1e;
263 }
264
265 static inline u16 mk_high_addr(u32 reg)
266 {
267 return (reg >> 7) & 0x1ff;
268 }
269
270 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
271 {
272 unsigned long flags;
273 u16 phy_addr;
274 u16 phy_reg;
275 u32 hi, lo;
276
277 reg = (reg & 0xfffffffc) >> 2;
278 phy_addr = mk_phy_addr(reg);
279 phy_reg = mk_phy_reg(reg);
280
281 local_irq_save(flags);
282 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
283 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
284 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
285 local_irq_restore(flags);
286
287 return (hi << 16) | lo;
288 }
289
290 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
291 {
292 unsigned long flags;
293 u16 phy_addr;
294 u16 phy_reg;
295
296 reg = (reg & 0xfffffffc) >> 2;
297 phy_addr = mk_phy_addr(reg);
298 phy_reg = mk_phy_reg(reg);
299
300 local_irq_save(flags);
301 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
302 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
303 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
304 local_irq_restore(flags);
305 }
306
307 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
308 {
309 u32 ret;
310
311 mutex_lock(&reg_mutex);
312 ret = __ar7240sw_reg_read(mii, reg_addr);
313 mutex_unlock(&reg_mutex);
314
315 return ret;
316 }
317
318 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
319 {
320 mutex_lock(&reg_mutex);
321 __ar7240sw_reg_write(mii, reg_addr, reg_val);
322 mutex_unlock(&reg_mutex);
323 }
324
325 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
326 {
327 u32 t;
328
329 mutex_lock(&reg_mutex);
330 t = __ar7240sw_reg_read(mii, reg);
331 t &= ~mask;
332 t |= val;
333 __ar7240sw_reg_write(mii, reg, t);
334 mutex_unlock(&reg_mutex);
335
336 return t;
337 }
338
339 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
340 {
341 u32 t;
342
343 mutex_lock(&reg_mutex);
344 t = __ar7240sw_reg_read(mii, reg);
345 t |= val;
346 __ar7240sw_reg_write(mii, reg, t);
347 mutex_unlock(&reg_mutex);
348 }
349
350 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
351 unsigned timeout)
352 {
353 int i;
354
355 for (i = 0; i < timeout; i++) {
356 u32 t;
357
358 t = __ar7240sw_reg_read(mii, reg);
359 if ((t & mask) == val)
360 return 0;
361
362 msleep(1);
363 }
364
365 return -ETIMEDOUT;
366 }
367
368 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
369 unsigned timeout)
370 {
371 int ret;
372
373 mutex_lock(&reg_mutex);
374 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
375 mutex_unlock(&reg_mutex);
376 return ret;
377 }
378
379 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
380 unsigned reg_addr)
381 {
382 u32 t, val = 0xffff;
383 int err;
384
385 if (phy_addr >= AR7240_NUM_PHYS)
386 return 0xffff;
387
388 mutex_lock(&reg_mutex);
389 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
390 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
391 AR7240_MDIO_CTRL_MASTER_EN |
392 AR7240_MDIO_CTRL_BUSY |
393 AR7240_MDIO_CTRL_CMD_READ;
394
395 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
396 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
397 AR7240_MDIO_CTRL_BUSY, 0, 5);
398 if (!err)
399 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
400 mutex_unlock(&reg_mutex);
401
402 return val & AR7240_MDIO_CTRL_DATA_M;
403 }
404
405 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
406 unsigned reg_addr, u16 reg_val)
407 {
408 u32 t;
409 int ret;
410
411 if (phy_addr >= AR7240_NUM_PHYS)
412 return -EINVAL;
413
414 mutex_lock(&reg_mutex);
415 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
416 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
417 AR7240_MDIO_CTRL_MASTER_EN |
418 AR7240_MDIO_CTRL_BUSY |
419 AR7240_MDIO_CTRL_CMD_WRITE |
420 reg_val;
421
422 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
423 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
424 AR7240_MDIO_CTRL_BUSY, 0, 5);
425 mutex_unlock(&reg_mutex);
426
427 return ret;
428 }
429
430 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
431 {
432 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
433 AR7240_PORT_CTRL_STATE_DISABLED);
434 }
435
436 static void ar7240sw_setup(struct ar7240sw *as)
437 {
438 struct mii_bus *mii = as->mii_bus;
439
440 /* Enable CPU port, and disable mirror port */
441 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
442 AR7240_CPU_PORT_EN |
443 (15 << AR7240_MIRROR_PORT_S));
444
445 /* Setup TAG priority mapping */
446 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
447
448 /* Enable ARP frame acknowledge, aging, MAC replacing */
449 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
450 0x2b /* 5 min age time */ |
451 AR7240_AT_CTRL_AGE_EN |
452 AR7240_AT_CTRL_ARP_EN |
453 AR7240_AT_CTRL_LEARN_CHANGE);
454
455 /* Enable Broadcast frames transmitted to the CPU */
456 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
457 AR7240_FLOOD_MASK_BROAD_TO_CPU);
458
459 /* setup MTU */
460 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
461 1536);
462
463 /* setup Service TAG */
464 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
465 }
466
467 static int ar7240sw_reset(struct ar7240sw *as)
468 {
469 struct mii_bus *mii = as->mii_bus;
470 int ret;
471 int i;
472
473 /* Set all ports to disabled state. */
474 for (i = 0; i < AR7240_NUM_PORTS; i++)
475 ar7240sw_disable_port(as, i);
476
477 /* Wait for transmit queues to drain. */
478 msleep(2);
479
480 /* Reset the switch. */
481 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
482 AR7240_MASK_CTRL_SOFT_RESET);
483
484 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
485 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
486
487 ar7240sw_setup(as);
488 return ret;
489 }
490
491 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
492 {
493 struct mii_bus *mii = as->mii_bus;
494 u32 ctrl;
495 u32 vlan;
496
497 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
498 AR7240_PORT_CTRL_SINGLE_VLAN;
499
500 if (port == AR7240_PORT_CPU) {
501 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
502 AR7240_PORT_STATUS_SPEED_1000 |
503 AR7240_PORT_STATUS_TXFLOW |
504 AR7240_PORT_STATUS_RXFLOW |
505 AR7240_PORT_STATUS_TXMAC |
506 AR7240_PORT_STATUS_RXMAC |
507 AR7240_PORT_STATUS_DUPLEX);
508 } else {
509 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
510 AR7240_PORT_STATUS_LINK_AUTO);
511 }
512
513 /* Set the default VID for this port */
514 if (as->vlan) {
515 vlan = as->vlan_id[as->pvid[port]];
516 vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
517 AR7240_PORT_VLAN_MODE_S;
518 } else {
519 vlan = port;
520 vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
521 AR7240_PORT_VLAN_MODE_S;
522 }
523
524 if (as->vlan && (as->vlan_tagged & BIT(port))) {
525 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
526 AR7240_PORT_CTRL_VLAN_MODE_S;
527 } else {
528 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
529 AR7240_PORT_CTRL_VLAN_MODE_S;
530 }
531
532 if (!portmask) {
533 if (port == AR7240_PORT_CPU)
534 portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
535 else
536 portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
537 }
538
539 /* allow the port to talk to all other ports, but exclude its
540 * own ID to prevent frames from being reflected back to the
541 * port that they came from */
542 portmask &= ar7240sw_port_mask_but(as, port);
543
544 /* set default VID and and destination ports for this VLAN */
545 vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
546
547 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
548 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
549 }
550
551 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
552 {
553 struct mii_bus *mii = as->mii_bus;
554 u32 t;
555
556 t = (addr[4] << 8) | addr[5];
557 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
558
559 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
560 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
561
562 return 0;
563 }
564
565 static int
566 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
567 struct switch_val *val)
568 {
569 struct ar7240sw *as = sw_to_ar7240(dev);
570 as->vlan_id[val->port_vlan] = val->value.i;
571 return 0;
572 }
573
574 static int
575 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
576 struct switch_val *val)
577 {
578 struct ar7240sw *as = sw_to_ar7240(dev);
579 val->value.i = as->vlan_id[val->port_vlan];
580 return 0;
581 }
582
583 static int
584 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
585 {
586 struct ar7240sw *as = sw_to_ar7240(dev);
587
588 /* make sure no invalid PVIDs get set */
589
590 if (vlan >= dev->vlans)
591 return -EINVAL;
592
593 as->pvid[port] = vlan;
594 return 0;
595 }
596
597 static int
598 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
599 {
600 struct ar7240sw *as = sw_to_ar7240(dev);
601 *vlan = as->pvid[port];
602 return 0;
603 }
604
605 static int
606 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
607 {
608 struct ar7240sw *as = sw_to_ar7240(dev);
609 u8 ports = as->vlan_table[val->port_vlan];
610 int i;
611
612 val->len = 0;
613 for (i = 0; i < as->swdev.ports; i++) {
614 struct switch_port *p;
615
616 if (!(ports & (1 << i)))
617 continue;
618
619 p = &val->value.ports[val->len++];
620 p->id = i;
621 if (as->vlan_tagged & (1 << i))
622 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
623 else
624 p->flags = 0;
625 }
626 return 0;
627 }
628
629 static int
630 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
631 {
632 struct ar7240sw *as = sw_to_ar7240(dev);
633 u8 *vt = &as->vlan_table[val->port_vlan];
634 int i, j;
635
636 *vt = 0;
637 for (i = 0; i < val->len; i++) {
638 struct switch_port *p = &val->value.ports[i];
639
640 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
641 as->vlan_tagged |= (1 << p->id);
642 else {
643 as->vlan_tagged &= ~(1 << p->id);
644 as->pvid[p->id] = val->port_vlan;
645
646 /* make sure that an untagged port does not
647 * appear in other vlans */
648 for (j = 0; j < AR7240_MAX_VLANS; j++) {
649 if (j == val->port_vlan)
650 continue;
651 as->vlan_table[j] &= ~(1 << p->id);
652 }
653 }
654
655 *vt |= 1 << p->id;
656 }
657 return 0;
658 }
659
660 static int
661 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
662 struct switch_val *val)
663 {
664 struct ar7240sw *as = sw_to_ar7240(dev);
665 as->vlan = !!val->value.i;
666 return 0;
667 }
668
669 static int
670 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
671 struct switch_val *val)
672 {
673 struct ar7240sw *as = sw_to_ar7240(dev);
674 val->value.i = as->vlan;
675 return 0;
676 }
677
678 static const char *
679 ar7240_speed_str(u32 status)
680 {
681 u32 speed;
682
683 speed = (status >> AR7240_PORT_STATUS_SPEED_S) &
684 AR7240_PORT_STATUS_SPEED_M;
685 switch (speed) {
686 case AR7240_PORT_STATUS_SPEED_10:
687 return "10baseT";
688 case AR7240_PORT_STATUS_SPEED_100:
689 return "100baseT";
690 case AR7240_PORT_STATUS_SPEED_1000:
691 return "1000baseT";
692 }
693
694 return "unknown";
695 }
696
697 static int
698 ar7240_port_get_link(struct switch_dev *dev, const struct switch_attr *attr,
699 struct switch_val *val)
700 {
701 struct ar7240sw *as = sw_to_ar7240(dev);
702 struct mii_bus *mii = as->mii_bus;
703 u32 len;
704 u32 status;
705 int port;
706
707 port = val->port_vlan;
708
709 memset(as->buf, '\0', sizeof(as->buf));
710 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
711
712 if (status & AR7240_PORT_STATUS_LINK_UP) {
713 len = snprintf(as->buf, sizeof(as->buf),
714 "port:%d link:up speed:%s %s-duplex %s%s%s",
715 port,
716 ar7240_speed_str(status),
717 (status & AR7240_PORT_STATUS_DUPLEX) ?
718 "full" : "half",
719 (status & AR7240_PORT_STATUS_TXFLOW) ?
720 "txflow ": "",
721 (status & AR7240_PORT_STATUS_RXFLOW) ?
722 "rxflow " : "",
723 (status & AR7240_PORT_STATUS_LINK_AUTO) ?
724 "auto ": "");
725 } else {
726 len = snprintf(as->buf, sizeof(as->buf),
727 "port:%d link:down", port);
728 }
729
730 val->value.s = as->buf;
731 val->len = len;
732
733 return 0;
734 }
735
736 static void
737 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
738 {
739 struct mii_bus *mii = as->mii_bus;
740
741 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
742 return;
743
744 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
745 val &= AR7240_VTUDATA_MEMBER;
746 val |= AR7240_VTUDATA_VALID;
747 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
748 }
749 op |= AR7240_VTU_ACTIVE;
750 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
751 }
752
753 static int
754 ar7240_hw_apply(struct switch_dev *dev)
755 {
756 struct ar7240sw *as = sw_to_ar7240(dev);
757 u8 portmask[AR7240_NUM_PORTS];
758 int i, j;
759
760 /* flush all vlan translation unit entries */
761 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
762
763 memset(portmask, 0, sizeof(portmask));
764 if (as->vlan) {
765 /* calculate the port destination masks and load vlans
766 * into the vlan translation unit */
767 for (j = 0; j < AR7240_MAX_VLANS; j++) {
768 u8 vp = as->vlan_table[j];
769
770 if (!vp)
771 continue;
772
773 for (i = 0; i < as->swdev.ports; i++) {
774 u8 mask = (1 << i);
775 if (vp & mask)
776 portmask[i] |= vp & ~mask;
777 }
778
779 ar7240_vtu_op(as,
780 AR7240_VTU_OP_LOAD |
781 (as->vlan_id[j] << AR7240_VTU_VID_S),
782 as->vlan_table[j]);
783 }
784 } else {
785 /* vlan disabled:
786 * isolate all ports, but connect them to the cpu port */
787 for (i = 0; i < as->swdev.ports; i++) {
788 if (i == AR7240_PORT_CPU)
789 continue;
790
791 portmask[i] = 1 << AR7240_PORT_CPU;
792 portmask[AR7240_PORT_CPU] |= (1 << i);
793 }
794 }
795
796 /* update the port destination mask registers and tag settings */
797 for (i = 0; i < as->swdev.ports; i++)
798 ar7240sw_setup_port(as, i, portmask[i]);
799
800 return 0;
801 }
802
803 static int
804 ar7240_reset_switch(struct switch_dev *dev)
805 {
806 struct ar7240sw *as = sw_to_ar7240(dev);
807 ar7240sw_reset(as);
808 return 0;
809 }
810
811 static struct switch_attr ar7240_globals[] = {
812 {
813 .type = SWITCH_TYPE_INT,
814 .name = "enable_vlan",
815 .description = "Enable VLAN mode",
816 .set = ar7240_set_vlan,
817 .get = ar7240_get_vlan,
818 .max = 1
819 },
820 };
821
822 static struct switch_attr ar7240_port[] = {
823 {
824 .type = SWITCH_TYPE_STRING,
825 .name = "link",
826 .description = "Get port link information",
827 .max = 1,
828 .set = NULL,
829 .get = ar7240_port_get_link,
830 },
831 };
832
833 static struct switch_attr ar7240_vlan[] = {
834 {
835 .type = SWITCH_TYPE_INT,
836 .name = "vid",
837 .description = "VLAN ID",
838 .set = ar7240_set_vid,
839 .get = ar7240_get_vid,
840 .max = 4094,
841 },
842 };
843
844 static const struct switch_dev_ops ar7240_ops = {
845 .attr_global = {
846 .attr = ar7240_globals,
847 .n_attr = ARRAY_SIZE(ar7240_globals),
848 },
849 .attr_port = {
850 .attr = ar7240_port,
851 .n_attr = ARRAY_SIZE(ar7240_port),
852 },
853 .attr_vlan = {
854 .attr = ar7240_vlan,
855 .n_attr = ARRAY_SIZE(ar7240_vlan),
856 },
857 .get_port_pvid = ar7240_get_pvid,
858 .set_port_pvid = ar7240_set_pvid,
859 .get_vlan_ports = ar7240_get_ports,
860 .set_vlan_ports = ar7240_set_ports,
861 .apply_config = ar7240_hw_apply,
862 .reset_switch = ar7240_reset_switch,
863 };
864
865 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
866 {
867 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
868 struct mii_bus *mii = ag->mii_bus;
869 struct ar7240sw *as;
870 struct switch_dev *swdev;
871 u32 ctrl;
872 u16 phy_id1;
873 u16 phy_id2;
874 int i;
875
876 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
877 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
878 if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
879 (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
880 pr_err("%s: unknown phy id '%04x:%04x'\n",
881 ag->dev->name, phy_id1, phy_id2);
882 return NULL;
883 }
884
885 as = kzalloc(sizeof(*as), GFP_KERNEL);
886 if (!as)
887 return NULL;
888
889 as->mii_bus = mii;
890 as->swdata = pdata->switch_data;
891
892 swdev = &as->swdev;
893
894 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
895 as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
896 AR7240_MASK_CTRL_VERSION_M;
897
898 if (sw_is_ar7240(as)) {
899 swdev->name = "AR7240/AR9330 built-in switch";
900 } else if (sw_is_ar934x(as)) {
901 struct ag71xx_platform_data *pdata;
902
903 swdev->name = "AR934X built-in switch";
904
905 pdata = ag71xx_get_pdata(ag);
906 if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
907 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
908 AR934X_OPER_MODE0_MAC_GMII_EN);
909 } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
910 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
911 AR934X_OPER_MODE0_PHY_MII_EN);
912 } else {
913 pr_err("%s: invalid PHY interface mode\n",
914 ag->dev->name);
915 goto err_free;
916 }
917 } else {
918 pr_err("%s: unsupported chip, ctrl=%08x\n",
919 ag->dev->name, ctrl);
920 goto err_free;
921 }
922
923 swdev->ports = AR7240_NUM_PORTS - 1;
924 swdev->cpu_port = AR7240_PORT_CPU;
925 swdev->vlans = AR7240_MAX_VLANS;
926 swdev->ops = &ar7240_ops;
927
928 if (register_switch(&as->swdev, ag->dev) < 0)
929 goto err_free;
930
931 pr_info("%s: Found an %s\n", ag->dev->name, swdev->name);
932
933 /* initialize defaults */
934 for (i = 0; i < AR7240_MAX_VLANS; i++)
935 as->vlan_id[i] = i;
936
937 as->vlan_table[0] = ar7240sw_port_mask_all(as);
938
939 return as;
940
941 err_free:
942 kfree(as);
943 return NULL;
944 }
945
946 static void link_function(struct work_struct *work) {
947 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
948 unsigned long flags;
949 int i;
950 int status = 0;
951
952 for (i = 0; i < 4; i++) {
953 int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
954 if(link & BMSR_LSTATUS) {
955 status = 1;
956 break;
957 }
958 }
959
960 spin_lock_irqsave(&ag->lock, flags);
961 if(status != ag->link) {
962 ag->link = status;
963 ag71xx_link_adjust(ag);
964 }
965 spin_unlock_irqrestore(&ag->lock, flags);
966
967 schedule_delayed_work(&ag->link_work, HZ / 2);
968 }
969
970 void ag71xx_ar7240_start(struct ag71xx *ag)
971 {
972 struct ar7240sw *as = ag->phy_priv;
973
974 ar7240sw_reset(as);
975
976 ag->speed = SPEED_1000;
977 ag->duplex = 1;
978
979 ar7240_set_addr(as, ag->dev->dev_addr);
980 ar7240_hw_apply(&as->swdev);
981
982 schedule_delayed_work(&ag->link_work, HZ / 10);
983 }
984
985 void ag71xx_ar7240_stop(struct ag71xx *ag)
986 {
987 cancel_delayed_work_sync(&ag->link_work);
988 }
989
990 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
991 {
992 struct ar7240sw *as;
993
994 as = ar7240_probe(ag);
995 if (!as)
996 return -ENODEV;
997
998 ag->phy_priv = as;
999 ar7240sw_reset(as);
1000
1001 INIT_DELAYED_WORK(&ag->link_work, link_function);
1002
1003 return 0;
1004 }
1005
1006 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
1007 {
1008 struct ar7240sw *as = ag->phy_priv;
1009
1010 if (!as)
1011 return;
1012
1013 unregister_switch(&as->swdev);
1014 kfree(as);
1015 ag->phy_priv = NULL;
1016 }
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