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[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 ( NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR )
25
26 static int ag71xx_debug = -1;
27
28 module_param(ag71xx_debug, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_regs(struct ag71xx *ag)
32 {
33 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
36 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
37 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
38 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
39 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
40 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
41 ag->dev->name,
42 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
43 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
44 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
45 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
46 ag->dev->name,
47 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
48 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
49 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
50 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
51 ag->dev->name,
52 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
53 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
54 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
55 }
56
57 static void ag71xx_ring_free(struct ag71xx_ring *ring)
58 {
59 kfree(ring->buf);
60
61 if (ring->descs)
62 dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
63 ring->descs, ring->descs_dma);
64 }
65
66 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
67 {
68 int err;
69
70 ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
71 &ring->descs_dma,
72 GFP_ATOMIC);
73 if (!ring->descs) {
74 err = -ENOMEM;
75 goto err;
76 }
77
78 ring->size = size;
79
80 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
81 if (!ring->buf) {
82 err = -ENOMEM;
83 goto err;
84 }
85
86 return 0;
87
88 err:
89 return err;
90 }
91
92 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
93 {
94 struct ag71xx_ring *ring = &ag->tx_ring;
95 struct net_device *dev = ag->dev;
96
97 while (ring->curr != ring->dirty) {
98 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
99
100 if (!ag71xx_desc_empty(&ring->descs[i])) {
101 ring->descs[i].ctrl = 0;
102 dev->stats.tx_errors++;
103 }
104
105 if (ring->buf[i].skb)
106 dev_kfree_skb_any(ring->buf[i].skb);
107
108 ring->buf[i].skb = NULL;
109
110 ring->dirty++;
111 }
112
113 /* flush descriptors */
114 wmb();
115
116 }
117
118 static void ag71xx_ring_tx_init(struct ag71xx *ag)
119 {
120 struct ag71xx_ring *ring = &ag->tx_ring;
121 int i;
122
123 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
124 ring->descs[i].next = (u32) (ring->descs_dma +
125 sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
126
127 ring->descs[i].ctrl = DESC_EMPTY;
128 ring->buf[i].skb = NULL;
129 }
130
131 /* flush descriptors */
132 wmb();
133
134 ring->curr = 0;
135 ring->dirty = 0;
136 }
137
138 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
139 {
140 struct ag71xx_ring *ring = &ag->rx_ring;
141 int i;
142
143 if (!ring->buf)
144 return;
145
146 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
147 if (ring->buf[i].skb)
148 kfree_skb(ring->buf[i].skb);
149
150 }
151
152 static int ag71xx_ring_rx_init(struct ag71xx *ag)
153 {
154 struct ag71xx_ring *ring = &ag->rx_ring;
155 unsigned int i;
156 int ret;
157
158 ret = 0;
159 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
160 ring->descs[i].next = (u32) (ring->descs_dma +
161 sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
162
163 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
164 struct sk_buff *skb;
165
166 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
167 if (!skb) {
168 ret = -ENOMEM;
169 break;
170 }
171
172 skb->dev = ag->dev;
173 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
174
175 ring->buf[i].skb = skb;
176 ring->descs[i].data = virt_to_phys(skb->data);
177 ring->descs[i].ctrl = DESC_EMPTY;
178 }
179
180 /* flush descriptors */
181 wmb();
182
183 ring->curr = 0;
184 ring->dirty = 0;
185
186 return ret;
187 }
188
189 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
190 {
191 struct ag71xx_ring *ring = &ag->rx_ring;
192 unsigned int count;
193
194 count = 0;
195 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
196 unsigned int i;
197
198 i = ring->dirty % AG71XX_RX_RING_SIZE;
199
200 if (ring->buf[i].skb == NULL) {
201 struct sk_buff *skb;
202
203 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
204 if (skb == NULL) {
205 printk(KERN_ERR "%s: no memory for skb\n",
206 ag->dev->name);
207 break;
208 }
209
210 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
211 skb->dev = ag->dev;
212 ring->buf[i].skb = skb;
213 ring->descs[i].data = virt_to_phys(skb->data);
214 }
215
216 ring->descs[i].ctrl = DESC_EMPTY;
217 count++;
218 }
219
220 /* flush descriptors */
221 wmb();
222
223 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
224
225 return count;
226 }
227
228 static int ag71xx_rings_init(struct ag71xx *ag)
229 {
230 int ret;
231
232 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
233 if (ret)
234 return ret;
235
236 ag71xx_ring_tx_init(ag);
237
238 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
239 if (ret)
240 return ret;
241
242 ret = ag71xx_ring_rx_init(ag);
243 return ret;
244 }
245
246 static void ag71xx_rings_cleanup(struct ag71xx *ag)
247 {
248 ag71xx_ring_rx_clean(ag);
249 ag71xx_ring_free(&ag->rx_ring);
250
251 ag71xx_ring_tx_clean(ag);
252 ag71xx_ring_free(&ag->tx_ring);
253 }
254
255 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
256 {
257 u32 t;
258
259 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
260 | (((u32) mac[2]) << 8) | ((u32) mac[2]);
261
262 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
263
264 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
265 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
266 }
267
268 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | MAC_CFG1_SRX \
269 | MAC_CFG1_STX)
270
271 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
272
273 static void ag71xx_hw_init(struct ag71xx *ag)
274 {
275 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
276
277 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
278 udelay(20);
279
280 ar71xx_device_stop(pdata->reset_bit);
281 mdelay(100);
282 ar71xx_device_start(pdata->reset_bit);
283 mdelay(100);
284
285 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
286
287 /* TODO: set max packet size */
288
289 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
290 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
291
292 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
293
294 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
295
296 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
297 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
298 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
299 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, 0x0007ffef);
300 }
301
302 static void ag71xx_hw_start(struct ag71xx *ag)
303 {
304 /* start RX engine */
305 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
306
307 /* enable interrupts */
308 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
309 }
310
311 static void ag71xx_hw_stop(struct ag71xx *ag)
312 {
313 /* stop RX and TX */
314 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
315 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
316
317 /* disable all interrupts */
318 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
319 }
320
321 static int ag71xx_open(struct net_device *dev)
322 {
323 struct ag71xx *ag = netdev_priv(dev);
324 int ret;
325
326 ret = ag71xx_rings_init(ag);
327 if (ret)
328 goto err;
329
330 napi_enable(&ag->napi);
331
332 netif_carrier_off(dev);
333 ag71xx_phy_start(ag);
334
335 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
336 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
337
338 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
339
340 ag71xx_hw_start(ag);
341
342 netif_start_queue(dev);
343
344 return 0;
345
346 err:
347 ag71xx_rings_cleanup(ag);
348 return ret;
349 }
350
351 static int ag71xx_stop(struct net_device *dev)
352 {
353 struct ag71xx *ag = netdev_priv(dev);
354 unsigned long flags;
355
356 spin_lock_irqsave(&ag->lock, flags);
357
358 netif_stop_queue(dev);
359
360 ag71xx_hw_stop(ag);
361
362 netif_carrier_off(dev);
363 ag71xx_phy_stop(ag);
364
365 napi_disable(&ag->napi);
366
367 spin_unlock_irqrestore(&ag->lock, flags);
368
369 ag71xx_rings_cleanup(ag);
370
371 return 0;
372 }
373
374 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
375 {
376 struct ag71xx *ag = netdev_priv(dev);
377 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
378 struct ag71xx_ring *ring = &ag->tx_ring;
379 struct ag71xx_desc *desc;
380 unsigned long flags;
381 int i;
382
383 i = ring->curr % AG71XX_TX_RING_SIZE;
384 desc = &ring->descs[i];
385
386 spin_lock_irqsave(&ag->lock, flags);
387 pdata->ddr_flush();
388 spin_unlock_irqrestore(&ag->lock, flags);
389
390 if (!ag71xx_desc_empty(desc))
391 goto err_drop;
392
393 if (skb->len <= 0) {
394 DBG("%s: packet len is too small\n", ag->dev->name);
395 goto err_drop;
396 }
397
398 dma_cache_wback_inv((unsigned long)skb->data, skb->len);
399
400 ring->buf[i].skb = skb;
401
402 /* setup descriptor fields */
403 desc->data = virt_to_phys(skb->data);
404 desc->ctrl = (skb->len & DESC_PKTLEN_M);
405
406 /* flush descriptor */
407 wmb();
408
409 ring->curr++;
410 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
411 DBG("%s: tx queue full\n", ag->dev->name);
412 netif_stop_queue(dev);
413 }
414
415 DBG("%s: packet injected into TX queue\n", ag->dev->name);
416
417 /* enable TX engine */
418 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
419
420 dev->trans_start = jiffies;
421
422 return 0;
423
424 err_drop:
425 dev->stats.tx_dropped++;
426
427 dev_kfree_skb(skb);
428 return 0;
429 }
430
431 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
432 {
433 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
434 struct ag71xx *ag = netdev_priv(dev);
435 int ret;
436
437 switch (cmd) {
438 case SIOCETHTOOL:
439 if (ag->phy_dev == NULL)
440 break;
441
442 spin_lock_irq(&ag->lock);
443 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
444 spin_unlock_irq(&ag->lock);
445 return ret;
446
447 case SIOCSIFHWADDR:
448 if (copy_from_user
449 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
450 return -EFAULT;
451 return 0;
452
453 case SIOCGIFHWADDR:
454 if (copy_to_user
455 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
456 return -EFAULT;
457 return 0;
458
459 case SIOCGMIIPHY:
460 case SIOCGMIIREG:
461 case SIOCSMIIREG:
462 if (ag->phy_dev == NULL)
463 break;
464
465 return phy_mii_ioctl(ag->phy_dev, data, cmd);
466
467 default:
468 break;
469 }
470
471 return -EOPNOTSUPP;
472 }
473
474 static void ag71xx_tx_packets(struct ag71xx *ag)
475 {
476 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
477 struct ag71xx_ring *ring = &ag->tx_ring;
478 unsigned int sent;
479
480 DBG("%s: processing TX ring\n", ag->dev->name);
481
482 #ifdef AG71XX_NAPI_TX
483 pdata->ddr_flush();
484 #endif
485
486 sent = 0;
487 while (ring->dirty != ring->curr) {
488 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
489 struct ag71xx_desc *desc = &ring->descs[i];
490 struct sk_buff *skb = ring->buf[i].skb;
491
492 if (!ag71xx_desc_empty(desc))
493 break;
494
495 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
496
497 ag->dev->stats.tx_bytes += skb->len;
498 ag->dev->stats.tx_packets++;
499
500 dev_kfree_skb_any(skb);
501 ring->buf[i].skb = NULL;
502
503 ring->dirty++;
504 sent++;
505 }
506
507 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
508
509 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
510 netif_wake_queue(ag->dev);
511
512 }
513
514 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
515 {
516 struct net_device *dev = ag->dev;
517 struct ag71xx_ring *ring = &ag->rx_ring;
518 #ifndef AG71XX_NAPI_TX
519 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
520 unsigned long flags;
521 #endif
522 int done = 0;
523
524 #ifndef AG71XX_NAPI_TX
525 spin_lock_irqsave(&ag->lock, flags);
526 pdata->ddr_flush();
527 spin_unlock_irqrestore(&ag->lock, flags);
528 #endif
529
530 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
531 dev->name, limit, ring->curr, ring->dirty);
532
533 while (done < limit) {
534 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
535 struct ag71xx_desc *desc = &ring->descs[i];
536 struct sk_buff *skb;
537 int pktlen;
538
539 if (ag71xx_desc_empty(desc))
540 break;
541
542 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
543 ag71xx_assert(0);
544 break;
545 }
546
547 skb = ring->buf[i].skb;
548 pktlen = ag71xx_desc_pktlen(desc);
549 pktlen -= ETH_FCS_LEN;
550
551 /* TODO: move it into the refill function */
552 dma_cache_wback_inv((unsigned long)skb->data, pktlen);
553 skb_put(skb, pktlen);
554
555 skb->dev = dev;
556 skb->protocol = eth_type_trans(skb, dev);
557 skb->ip_summed = CHECKSUM_UNNECESSARY;
558
559 netif_receive_skb(skb);
560
561 dev->last_rx = jiffies;
562 dev->stats.rx_packets++;
563 dev->stats.rx_bytes += pktlen;
564
565 ring->buf[i].skb = NULL;
566 done++;
567
568 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
569
570 ring->curr++;
571 if ((ring->curr - ring->dirty) > (AG71XX_RX_RING_SIZE / 4))
572 ag71xx_ring_rx_refill(ag);
573 }
574
575 ag71xx_ring_rx_refill(ag);
576
577 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
578 dev->name, ring->curr, ring->dirty, done);
579
580 return done;
581 }
582
583 static int ag71xx_poll(struct napi_struct *napi, int limit)
584 {
585 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
586 #ifdef AG71XX_NAPI_TX
587 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
588 #endif
589 struct net_device *dev = ag->dev;
590 unsigned long flags;
591 u32 status;
592 int done;
593
594 #ifdef AG71XX_NAPI_TX
595 pdata->ddr_flush();
596 ag71xx_tx_packets(ag);
597 #endif
598
599 DBG("%s: processing RX ring\n", dev->name);
600 done = ag71xx_rx_packets(ag, limit);
601
602 /* TODO: add OOM handler */
603
604 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
605 status &= AG71XX_INT_POLL;
606
607 if ((done < limit) && (!status)) {
608 DBG("%s: disable polling mode, done=%d, status=%x\n",
609 dev->name, done, status);
610
611 netif_rx_complete(dev, napi);
612
613 /* enable interrupts */
614 spin_lock_irqsave(&ag->lock, flags);
615 ag71xx_int_enable(ag, AG71XX_INT_POLL);
616 spin_unlock_irqrestore(&ag->lock, flags);
617 return 0;
618 }
619
620 if (status & AG71XX_INT_RX_OF) {
621 if (netif_msg_rx_err(ag))
622 printk(KERN_ALERT "%s: rx owerflow, restarting dma\n",
623 dev->name);
624
625 /* ack interrupt */
626 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
627 /* restart RX */
628 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
629 }
630
631 DBG("%s: stay in polling mode, done=%d, status=%x\n",
632 dev->name, done, status);
633 return 1;
634 }
635
636 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
637 {
638 struct net_device *dev = dev_id;
639 struct ag71xx *ag = netdev_priv(dev);
640 u32 status;
641
642 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
643 status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE);
644
645 if (unlikely(!status))
646 return IRQ_NONE;
647
648 if (unlikely(status & AG71XX_INT_ERR)) {
649 if (status & AG71XX_INT_TX_BE) {
650 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
651 dev_err(&dev->dev, "TX BUS error\n");
652 }
653 if (status & AG71XX_INT_RX_BE) {
654 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
655 dev_err(&dev->dev, "RX BUS error\n");
656 }
657 }
658
659 #if 0
660 if (unlikely(status & AG71XX_INT_TX_UR)) {
661 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_UR);
662 DBG("%s: TX underrun\n", dev->name);
663 }
664 #endif
665
666 #ifndef AG71XX_NAPI_TX
667 if (likely(status & AG71XX_INT_TX_PS))
668 ag71xx_tx_packets(ag);
669 #endif
670
671 if (likely(status & AG71XX_INT_POLL)) {
672 ag71xx_int_disable(ag, AG71XX_INT_POLL);
673 DBG("%s: enable polling mode\n", dev->name);
674 netif_rx_schedule(dev, &ag->napi);
675 }
676
677 return IRQ_HANDLED;
678 }
679
680 static void ag71xx_set_multicast_list(struct net_device *dev)
681 {
682 /* TODO */
683 }
684
685 static int __init ag71xx_probe(struct platform_device *pdev)
686 {
687 struct net_device *dev;
688 struct resource *res;
689 struct ag71xx *ag;
690 struct ag71xx_platform_data *pdata;
691 int err;
692
693 pdata = pdev->dev.platform_data;
694 if (!pdata) {
695 dev_err(&pdev->dev, "no platform data specified\n");
696 err = -ENXIO;
697 goto err_out;
698 }
699
700 dev = alloc_etherdev(sizeof(*ag));
701 if (!dev) {
702 dev_err(&pdev->dev, "alloc_etherdev failed\n");
703 err = -ENOMEM;
704 goto err_out;
705 }
706
707 SET_NETDEV_DEV(dev, &pdev->dev);
708
709 ag = netdev_priv(dev);
710 ag->pdev = pdev;
711 ag->dev = dev;
712 ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
713 ag->msg_enable = netif_msg_init(ag71xx_debug,
714 AG71XX_DEFAULT_MSG_ENABLE);
715 spin_lock_init(&ag->lock);
716
717 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
718 if (!res) {
719 dev_err(&pdev->dev, "no mac_base resource found\n");
720 err = -ENXIO;
721 goto err_out;
722 }
723
724 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
725 if (!ag->mac_base) {
726 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
727 err = -ENOMEM;
728 goto err_free_dev;
729 }
730
731 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
732 if (!res) {
733 dev_err(&pdev->dev, "no mac_base2 resource found\n");
734 err = -ENXIO;
735 goto err_unmap_base1;
736 }
737
738 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
739 if (!ag->mac_base) {
740 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
741 err = -ENOMEM;
742 goto err_unmap_base1;
743 }
744
745 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
746 if (!res) {
747 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
748 err = -ENXIO;
749 goto err_unmap_base2;
750 }
751
752 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
753 if (!ag->mii_ctrl) {
754 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
755 err = -ENOMEM;
756 goto err_unmap_base2;
757 }
758
759 dev->irq = platform_get_irq(pdev, 0);
760 err = request_irq(dev->irq, ag71xx_interrupt,
761 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
762 dev->name, dev);
763 if (err) {
764 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
765 goto err_unmap_mii_ctrl;
766 }
767
768 dev->base_addr = (unsigned long)ag->mac_base;
769 dev->open = ag71xx_open;
770 dev->stop = ag71xx_stop;
771 dev->hard_start_xmit = ag71xx_hard_start_xmit;
772 dev->set_multicast_list = ag71xx_set_multicast_list;
773 dev->do_ioctl = ag71xx_do_ioctl;
774 dev->ethtool_ops = &ag71xx_ethtool_ops;
775
776 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
777
778 if (is_valid_ether_addr(pdata->mac_addr))
779 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
780 else {
781 dev->dev_addr[0] = 0xde;
782 dev->dev_addr[1] = 0xad;
783 get_random_bytes(&dev->dev_addr[2], 3);
784 dev->dev_addr[5] = pdev->id & 0xff;
785 }
786
787 err = register_netdev(dev);
788 if (err) {
789 dev_err(&pdev->dev, "unable to register net device\n");
790 goto err_free_irq;
791 }
792
793 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
794 dev->name, dev->base_addr, dev->irq);
795
796 ag71xx_dump_regs(ag);
797
798 ag71xx_hw_init(ag);
799
800 ag71xx_dump_regs(ag);
801
802 /* Reset the mdio bus explicitly */
803 if (ag->mii_bus) {
804 mutex_lock(&ag->mii_bus->mdio_lock);
805 ag->mii_bus->reset(ag->mii_bus);
806 mutex_unlock(&ag->mii_bus->mdio_lock);
807 }
808
809 err = ag71xx_phy_connect(ag);
810 if (err)
811 goto err_unregister_netdev;
812
813 platform_set_drvdata(pdev, dev);
814
815 return 0;
816
817 err_unregister_netdev:
818 unregister_netdev(dev);
819 err_free_irq:
820 free_irq(dev->irq, dev);
821 err_unmap_mii_ctrl:
822 iounmap(ag->mii_ctrl);
823 err_unmap_base2:
824 iounmap(ag->mac_base2);
825 err_unmap_base1:
826 iounmap(ag->mac_base);
827 err_free_dev:
828 kfree(dev);
829 err_out:
830 platform_set_drvdata(pdev, NULL);
831 return err;
832 }
833
834 static int __exit ag71xx_remove(struct platform_device *pdev)
835 {
836 struct net_device *dev = platform_get_drvdata(pdev);
837
838 if (dev) {
839 struct ag71xx *ag = netdev_priv(dev);
840
841 ag71xx_phy_disconnect(ag);
842 unregister_netdev(dev);
843 free_irq(dev->irq, dev);
844 iounmap(ag->mii_ctrl);
845 iounmap(ag->mac_base2);
846 iounmap(ag->mac_base);
847 kfree(dev);
848 platform_set_drvdata(pdev, NULL);
849 }
850
851 return 0;
852 }
853
854 static struct platform_driver ag71xx_driver = {
855 .probe = ag71xx_probe,
856 .remove = __exit_p(ag71xx_remove),
857 .driver = {
858 .name = AG71XX_DRV_NAME,
859 }
860 };
861
862 static int __init ag71xx_module_init(void)
863 {
864 int ret;
865
866 ret = ag71xx_mdio_driver_init();
867 if (ret)
868 goto err_out;
869
870 ret = platform_driver_register(&ag71xx_driver);
871 if (ret)
872 goto err_mdio_exit;
873
874 return 0;
875
876 err_mdio_exit:
877 ag71xx_mdio_driver_exit();
878 err_out:
879 return ret;
880 }
881
882 static void __exit ag71xx_module_exit(void)
883 {
884 platform_driver_unregister(&ag71xx_driver);
885 ag71xx_mdio_driver_exit();
886 }
887
888 module_init(ag71xx_module_init);
889 module_exit(ag71xx_module_exit);
890
891 MODULE_VERSION(AG71XX_DRV_VERSION);
892 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
893 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
894 MODULE_LICENSE("GPL v2");
895 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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