target/linux/ar71xx/patches-3.3/123-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch

   1 From 77bb01d1919bcb6787d5cde9056936420288ab34 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Wed, 14 Mar 2012 10:45:23 +0100
   4 Subject: [PATCH 28/47] MIPS: ath79: add GPIO support code for AR934X
   5
   6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   7 Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
   8 Cc: linux-mips@linux-mips.org
   9 Cc: mcgrof@infradead.org
  10 Patchwork: https://patchwork.linux-mips.org/patch/3508/
  11 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  12 ---
  13  arch/mips/ath79/gpio.c                         |   47 +++++++++++++++++++++++-
  14  arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    1 +
  15  2 files changed, 47 insertions(+), 1 deletions(-)
  16
  17 --- a/arch/mips/ath79/gpio.c
  18 +++ b/arch/mips/ath79/gpio.c
  19 @@ -1,9 +1,12 @@
  20  /*
  21   *  Atheros AR71XX/AR724X/AR913X GPIO API support
  22   *
  23 - *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  24 + *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
  25 + *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  26   *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  27   *
  28 + *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
  29 + *
  30   *  This program is free software; you can redistribute it and/or modify it
  31   *  under the terms of the GNU General Public License version 2 as published
  32   *  by the Free Software Foundation.
  33 @@ -89,6 +92,42 @@ static int ath79_gpio_direction_output(s
  34         return 0;
  35  }
  36
  37 +static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  38 +{
  39 +       void __iomem *base = ath79_gpio_base;
  40 +       unsigned long flags;
  41 +
  42 +       spin_lock_irqsave(&ath79_gpio_lock, flags);
  43 +
  44 +       __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
  45 +                    base + AR71XX_GPIO_REG_OE);
  46 +
  47 +       spin_unlock_irqrestore(&ath79_gpio_lock, flags);
  48 +
  49 +       return 0;
  50 +}
  51 +
  52 +static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
  53 +                                       int value)
  54 +{
  55 +       void __iomem *base = ath79_gpio_base;
  56 +       unsigned long flags;
  57 +
  58 +       spin_lock_irqsave(&ath79_gpio_lock, flags);
  59 +
  60 +       if (value)
  61 +               __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
  62 +       else
  63 +               __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
  64 +
  65 +       __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
  66 +                    base + AR71XX_GPIO_REG_OE);
  67 +
  68 +       spin_unlock_irqrestore(&ath79_gpio_lock, flags);
  69 +
  70 +       return 0;
  71 +}
  72 +
  73  static struct gpio_chip ath79_gpio_chip = {
  74         .label                  = "ath79",
  75         .get                    = ath79_gpio_get_value,
  76 @@ -155,11 +194,17 @@ void __init ath79_gpio_init(void)
  77                 ath79_gpio_count = AR913X_GPIO_COUNT;
  78         else if (soc_is_ar933x())
  79                 ath79_gpio_count = AR933X_GPIO_COUNT;
  80 +       else if (soc_is_ar934x())
  81 +               ath79_gpio_count = AR934X_GPIO_COUNT;
  82         else
  83                 BUG();
  84
  85         ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
  86         ath79_gpio_chip.ngpio = ath79_gpio_count;
  87 +       if (soc_is_ar934x()) {
  88 +               ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
  89 +               ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
  90 +       }
  91
  92         err = gpiochip_add(&ath79_gpio_chip);
  93         if (err)
  94 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  95 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  96 @@ -367,5 +367,6 @@
  97  #define AR724X_GPIO_COUNT              18
  98  #define AR913X_GPIO_COUNT              22
  99  #define AR933X_GPIO_COUNT              30
 100 +#define AR934X_GPIO_COUNT              23
 101
 102  #endif /* __ASM_MACH_AR71XX_REGS_H */