target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch

   1 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   2 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   3 @@ -20,7 +20,13 @@
   4  #include <linux/io.h>
   5  #include <linux/bitops.h>
   6
   7 +#define AR71XX_PCI_MEM_BASE    0x10000000
   8 +#define AR71XX_PCI_MEM_SIZE    0x08000000
   9  #define AR71XX_APB_BASE                0x18000000
  10 +#define AR71XX_GE0_BASE                0x19000000
  11 +#define AR71XX_GE0_SIZE                0x10000
  12 +#define AR71XX_GE1_BASE                0x1a000000
  13 +#define AR71XX_GE1_SIZE                0x10000
  14  #define AR71XX_EHCI_BASE       0x1b000000
  15  #define AR71XX_EHCI_SIZE       0x1000
  16  #define AR71XX_OHCI_BASE       0x1c000000
  17 @@ -40,6 +46,8 @@
  18  #define AR71XX_PLL_SIZE                0x100
  19  #define AR71XX_RESET_BASE      (AR71XX_APB_BASE + 0x00060000)
  20  #define AR71XX_RESET_SIZE      0x100
  21 +#define AR71XX_MII_BASE                (AR71XX_APB_BASE + 0x00070000)
  22 +#define AR71XX_MII_SIZE                0x100
  23
  24  #define AR7240_USB_CTRL_BASE   (AR71XX_APB_BASE + 0x00030000)
  25  #define AR7240_USB_CTRL_SIZE   0x100
  26 @@ -56,11 +64,15 @@
  27
  28  #define AR933X_UART_BASE       (AR71XX_APB_BASE + 0x00020000)
  29  #define AR933X_UART_SIZE       0x14
  30 +#define AR933X_GMAC_BASE       (AR71XX_APB_BASE + 0x00070000)
  31 +#define AR933X_GMAC_SIZE       0x04
  32  #define AR933X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
  33  #define AR933X_WMAC_SIZE       0x20000
  34  #define AR933X_EHCI_BASE       0x1b000000
  35  #define AR933X_EHCI_SIZE       0x1000
  36
  37 +#define AR934X_GMAC_BASE       (AR71XX_APB_BASE + 0x00070000)
  38 +#define AR934X_GMAC_SIZE       0x14
  39  #define AR934X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
  40  #define AR934X_WMAC_SIZE       0x20000
  41  #define AR934X_EHCI_BASE       0x1b000000
  42 @@ -120,6 +132,9 @@
  43  #define AR71XX_AHB_DIV_SHIFT           20
  44  #define AR71XX_AHB_DIV_MASK            0x7
  45
  46 +#define AR71XX_ETH0_PLL_SHIFT          17
  47 +#define AR71XX_ETH1_PLL_SHIFT          19
  48 +
  49  #define AR724X_PLL_REG_CPU_CONFIG      0x00
  50  #define AR724X_PLL_REG_PCIE_CONFIG     0x18
  51
  52 @@ -132,6 +147,8 @@
  53  #define AR724X_DDR_DIV_SHIFT           22
  54  #define AR724X_DDR_DIV_MASK            0x3
  55
  56 +#define AR7242_PLL_REG_ETH0_INT_CLOCK  0x2c
  57 +
  58  #define AR913X_PLL_REG_CPU_CONFIG      0x00
  59  #define AR913X_PLL_REG_ETH_CONFIG      0x04
  60  #define AR913X_PLL_REG_ETH0_INT_CLOCK  0x14
  61 @@ -144,6 +161,9 @@
  62  #define AR913X_AHB_DIV_SHIFT           19
  63  #define AR913X_AHB_DIV_MASK            0x1
  64
  65 +#define AR913X_ETH0_PLL_SHIFT          20
  66 +#define AR913X_ETH1_PLL_SHIFT          22
  67 +
  68  #define AR933X_PLL_CPU_CONFIG_REG      0x00
  69  #define AR933X_PLL_CLOCK_CTRL_REG      0x08
  70
  71 @@ -165,6 +185,7 @@
  72  #define AR934X_PLL_CPU_CONFIG_REG              0x00
  73  #define AR934X_PLL_DDR_CONFIG_REG              0x04
  74  #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG                0x08
  75 +#define AR934X_PLL_ETH_XMII_CONTROL_REG                0x2c
  76
  77  #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT      0
  78  #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK       0x3f
  79 @@ -285,7 +306,11 @@
  80  #define AR913X_RESET_USB_HOST          BIT(5)
  81  #define AR913X_RESET_USB_PHY           BIT(4)
  82
  83 +#define AR933X_RESET_GE1_MDIO          BIT(23)
  84 +#define AR933X_RESET_GE0_MDIO          BIT(22)
  85 +#define AR933X_RESET_GE1_MAC           BIT(13)
  86  #define AR933X_RESET_WMAC              BIT(11)
  87 +#define AR933X_RESET_GE0_MAC           BIT(9)
  88  #define AR933X_RESET_USB_HOST          BIT(5)
  89  #define AR933X_RESET_USB_PHY           BIT(4)
  90  #define AR933X_RESET_USBSUS_OVERRIDE   BIT(3)
  91 @@ -323,6 +348,8 @@
  92  #define AR934X_RESET_MBOX              BIT(1)
  93  #define AR934X_RESET_I2S               BIT(0)
  94
  95 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN  BIT(18)
  96 +#define AR933X_BOOTSTRAP_EEPBUSY       BIT(4)
  97  #define AR933X_BOOTSTRAP_REF_CLK_40    BIT(0)
  98
  99  #define AR934X_BOOTSTRAP_SW_OPTION8    BIT(23)
 100 @@ -427,6 +454,14 @@
 101  #define AR71XX_GPIO_REG_INT_ENABLE     0x24
 102  #define AR71XX_GPIO_REG_FUNC           0x28
 103
 104 +#define AR934X_GPIO_REG_OUT_FUNC0      0x2c
 105 +#define AR934X_GPIO_REG_OUT_FUNC1      0x30
 106 +#define AR934X_GPIO_REG_OUT_FUNC2      0x34
 107 +#define AR934X_GPIO_REG_OUT_FUNC3      0x38
 108 +#define AR934X_GPIO_REG_OUT_FUNC4      0x3c
 109 +#define AR934X_GPIO_REG_OUT_FUNC5      0x40
 110 +#define AR934X_GPIO_REG_FUNC           0x6c
 111 +
 112  #define AR71XX_GPIO_COUNT              16
 113  #define AR7240_GPIO_COUNT              18
 114  #define AR7241_GPIO_COUNT              20
 115 @@ -434,4 +469,124 @@
 116  #define AR933X_GPIO_COUNT              30
 117  #define AR934X_GPIO_COUNT              23
 118
 119 +#define AR71XX_GPIO_FUNC_STEREO_EN             BIT(17)
 120 +#define AR71XX_GPIO_FUNC_SLIC_EN               BIT(16)
 121 +#define AR71XX_GPIO_FUNC_SPI_CS2_EN            BIT(13)
 122 +#define AR71XX_GPIO_FUNC_SPI_CS1_EN            BIT(12)
 123 +#define AR71XX_GPIO_FUNC_UART_EN               BIT(8)
 124 +#define AR71XX_GPIO_FUNC_USB_OC_EN             BIT(4)
 125 +#define AR71XX_GPIO_FUNC_USB_CLK_EN            BIT(0)
 126 +
 127 +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN                BIT(19)
 128 +#define AR724X_GPIO_FUNC_SPI_EN                        BIT(18)
 129 +#define AR724X_GPIO_FUNC_SPI_CS_EN2            BIT(14)
 130 +#define AR724X_GPIO_FUNC_SPI_CS_EN1            BIT(13)
 131 +#define AR724X_GPIO_FUNC_CLK_OBS5_EN           BIT(12)
 132 +#define AR724X_GPIO_FUNC_CLK_OBS4_EN           BIT(11)
 133 +#define AR724X_GPIO_FUNC_CLK_OBS3_EN           BIT(10)
 134 +#define AR724X_GPIO_FUNC_CLK_OBS2_EN           BIT(9)
 135 +#define AR724X_GPIO_FUNC_CLK_OBS1_EN           BIT(8)
 136 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN    BIT(7)
 137 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN    BIT(6)
 138 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN    BIT(5)
 139 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN    BIT(4)
 140 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN    BIT(3)
 141 +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN       BIT(2)
 142 +#define AR724X_GPIO_FUNC_UART_EN               BIT(1)
 143 +#define AR724X_GPIO_FUNC_JTAG_DISABLE          BIT(0)
 144 +
 145 +#define AR913X_GPIO_FUNC_WMAC_LED_EN           BIT(22)
 146 +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN                BIT(21)
 147 +#define AR913X_GPIO_FUNC_I2S_REFCLKEN          BIT(20)
 148 +#define AR913X_GPIO_FUNC_I2S_MCKEN             BIT(19)
 149 +#define AR913X_GPIO_FUNC_I2S1_EN               BIT(18)
 150 +#define AR913X_GPIO_FUNC_I2S0_EN               BIT(17)
 151 +#define AR913X_GPIO_FUNC_SLIC_EN               BIT(16)
 152 +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN                BIT(9)
 153 +#define AR913X_GPIO_FUNC_UART_EN               BIT(8)
 154 +#define AR913X_GPIO_FUNC_USB_CLK_EN            BIT(4)
 155 +
 156 +#define AR933X_GPIO_FUNC_SPDIF2TCK             BIT(31)
 157 +#define AR933X_GPIO_FUNC_SPDIF_EN              BIT(30)
 158 +#define AR933X_GPIO_FUNC_I2SO_22_18_EN         BIT(29)
 159 +#define AR933X_GPIO_FUNC_I2S_MCK_EN            BIT(27)
 160 +#define AR933X_GPIO_FUNC_I2SO_EN               BIT(26)
 161 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL   BIT(25)
 162 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL   BIT(24)
 163 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT    BIT(23)
 164 +#define AR933X_GPIO_FUNC_SPI_EN                        BIT(18)
 165 +#define AR933X_GPIO_FUNC_SPI_CS_EN2            BIT(14)
 166 +#define AR933X_GPIO_FUNC_SPI_CS_EN1            BIT(13)
 167 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN    BIT(7)
 168 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN    BIT(6)
 169 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN    BIT(5)
 170 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN    BIT(4)
 171 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN    BIT(3)
 172 +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN       BIT(2)
 173 +#define AR933X_GPIO_FUNC_UART_EN               BIT(1)
 174 +#define AR933X_GPIO_FUNC_JTAG_DISABLE          BIT(0)
 175 +
 176 +#define AR934X_GPIO_FUNC_DDR_DQOE_EN   BIT(17)
 177 +#define AR934X_GPIO_FUNC_SPI_CS_1_EN   BIT(14)
 178 +#define AR934X_GPIO_FUNC_SPI_CS_0_EN   BIT(13)
 179 +
 180 +#define AR934X_GPIO_OUT_GPIO           0x00
 181 +
 182 +/*
 183 + * MII_CTRL block
 184 + */
 185 +#define AR71XX_MII_REG_MII0_CTRL       0x00
 186 +#define AR71XX_MII_REG_MII1_CTRL       0x04
 187 +
 188 +#define AR71XX_MII_CTRL_IF_MASK                3
 189 +#define AR71XX_MII_CTRL_SPEED_SHIFT    4
 190 +#define AR71XX_MII_CTRL_SPEED_MASK     3
 191 +#define AR71XX_MII_CTRL_SPEED_10       0
 192 +#define AR71XX_MII_CTRL_SPEED_100      1
 193 +#define AR71XX_MII_CTRL_SPEED_1000     2
 194 +
 195 +#define AR71XX_MII0_CTRL_IF_GMII       0
 196 +#define AR71XX_MII0_CTRL_IF_MII                1
 197 +#define AR71XX_MII0_CTRL_IF_RGMII      2
 198 +#define AR71XX_MII0_CTRL_IF_RMII       3
 199 +
 200 +#define AR71XX_MII1_CTRL_IF_RGMII      0
 201 +#define AR71XX_MII1_CTRL_IF_RMII       1
 202 +
 203 +/*
 204 + * AR933X GMAC interface
 205 + */
 206 +#define AR933X_GMAC_REG_ETH_CFG                0x00
 207 +
 208 +#define AR933X_ETH_CFG_RGMII_GE0       BIT(0)
 209 +#define AR933X_ETH_CFG_MII_GE0         BIT(1)
 210 +#define AR933X_ETH_CFG_GMII_GE0                BIT(2)
 211 +#define AR933X_ETH_CFG_MII_GE0_MASTER  BIT(3)
 212 +#define AR933X_ETH_CFG_MII_GE0_SLAVE   BIT(4)
 213 +#define AR933X_ETH_CFG_MII_GE0_ERR_EN  BIT(5)
 214 +#define AR933X_ETH_CFG_SW_PHY_SWAP     BIT(7)
 215 +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP        BIT(8)
 216 +#define AR933X_ETH_CFG_RMII_GE0                BIT(9)
 217 +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
 218 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100        BIT(10)
 219 +
 220 +/*
 221 + * AR934X GMAC Interface
 222 + */
 223 +#define AR934X_GMAC_REG_ETH_CFG                0x00
 224 +
 225 +#define AR934X_ETH_CFG_RGMII_GMAC0     BIT(0)
 226 +#define AR934X_ETH_CFG_MII_GMAC0       BIT(1)
 227 +#define AR934X_ETH_CFG_GMII_GMAC0      BIT(2)
 228 +#define AR934X_ETH_CFG_MII_GMAC0_MASTER        BIT(3)
 229 +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
 230 +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN        BIT(5)
 231 +#define AR934X_ETH_CFG_SW_ONLY_MODE    BIT(6)
 232 +#define AR934X_ETH_CFG_SW_PHY_SWAP     BIT(7)
 233 +#define AR934X_ETH_CFG_SW_APB_ACCESS   BIT(9)
 234 +#define AR934X_ETH_CFG_RMII_GMAC0      BIT(10)
 235 +#define AR933X_ETH_CFG_MII_CNTL_SPEED  BIT(11)
 236 +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
 237 +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST        BIT(13)
 238 +
 239  #endif /* __ASM_MACH_AR71XX_REGS_H */