target/linux/ar71xx/patches-3.8/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch

   1 From 3c3c0eccf63b12fea98fd0eb65d0ccf69a7c5a57 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Sun, 24 Jun 2012 13:42:16 +0200
   4 Subject: [PATCH 17/34] MIPS: ath79: add SoC detection code for the QCA9558 SoC
   5
   6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   7 ---
   8  arch/mips/ath79/Kconfig                        |    4 ++++
   9  arch/mips/ath79/setup.c                        |   12 +++++++++++-
  10  arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 ++
  11  arch/mips/include/asm/mach-ath79/ath79.h       |   11 +++++++++++
  12  4 files changed, 28 insertions(+), 1 deletions(-)
  13
  14 --- a/arch/mips/ath79/Kconfig
  15 +++ b/arch/mips/ath79/Kconfig
  16 @@ -88,6 +88,10 @@ config SOC_AR934X
  17         select PCI_AR724X if PCI
  18         def_bool n
  19
  20 +config SOC_QCA955X
  21 +       select USB_ARCH_HAS_EHCI
  22 +       def_bool n
  23 +
  24  config PCI_AR724X
  25         def_bool n
  26
  27 --- a/arch/mips/ath79/setup.c
  28 +++ b/arch/mips/ath79/setup.c
  29 @@ -164,13 +164,23 @@ static void __init ath79_detect_sys_type
  30                 rev = id & AR934X_REV_ID_REVISION_MASK;
  31                 break;
  32
  33 +       case REV_ID_MAJOR_QCA9558:
  34 +               ath79_soc = ATH79_SOC_QCA9558;
  35 +               chip = "9558";
  36 +               rev = id & AR944X_REV_ID_REVISION_MASK;
  37 +               break;
  38 +
  39         default:
  40                 panic("ath79: unknown SoC, id:0x%08x", id);
  41         }
  42
  43         ath79_soc_rev = rev;
  44
  45 -       sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
  46 +       if (soc_is_qca955x())
  47 +               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
  48 +                       chip, rev);
  49 +       else
  50 +               sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
  51         pr_info("SoC: %s\n", ath79_sys_type);
  52  }
  53
  54 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  55 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  56 @@ -391,6 +391,8 @@
  57
  58  #define AR934X_REV_ID_REVISION_MASK     0xf
  59
  60 +#define AR944X_REV_ID_REVISION_MASK    0xf
  61 +
  62  /*
  63   * SPI block
  64   */
  65 --- a/arch/mips/include/asm/mach-ath79/ath79.h
  66 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
  67 @@ -32,6 +32,7 @@ enum ath79_soc_type {
  68         ATH79_SOC_AR9341,
  69         ATH79_SOC_AR9342,
  70         ATH79_SOC_AR9344,
  71 +       ATH79_SOC_QCA9558,
  72  };
  73
  74  extern enum ath79_soc_type ath79_soc;
  75 @@ -98,6 +99,16 @@ static inline int soc_is_ar934x(void)
  76         return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
  77  }
  78
  79 +static inline int soc_is_qca9558(void)
  80 +{
  81 +       return ath79_soc == ATH79_SOC_QCA9558;
  82 +}
  83 +
  84 +static inline int soc_is_qca955x(void)
  85 +{
  86 +       return soc_is_qca9558();
  87 +}
  88 +
  89  extern void __iomem *ath79_ddr_base;
  90  extern void __iomem *ath79_pll_base;
  91  extern void __iomem *ath79_reset_base;