ar71xx: refresh kernel config
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-4.1 / 736-MIPS-ath79-fix-chained-irq-disable.patch
1 --- a/arch/mips/ath79/irq.c
2 +++ b/arch/mips/ath79/irq.c
3 @@ -26,6 +26,8 @@
4
5 static void (*ath79_ip2_handler)(void);
6 static void (*ath79_ip3_handler)(void);
7 +static struct irq_chip ip2_chip;
8 +static struct irq_chip ip3_chip;
9
10 static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
11 {
12 @@ -149,8 +151,7 @@ static void ar934x_ip2_irq_init(void)
13
14 for (i = ATH79_IP2_IRQ_BASE;
15 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
16 - irq_set_chip_and_handler(i, &dummy_irq_chip,
17 - handle_level_irq);
18 + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
19
20 irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
21 }
22 @@ -182,7 +183,7 @@ static void qca953x_irq_init(void)
23
24 for (i = ATH79_IP2_IRQ_BASE;
25 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
26 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
27 + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
28
29 irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
30 }
31 @@ -256,15 +257,13 @@ static void qca955x_irq_init(void)
32
33 for (i = ATH79_IP2_IRQ_BASE;
34 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
35 - irq_set_chip_and_handler(i, &dummy_irq_chip,
36 - handle_level_irq);
37 + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
38
39 irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
40
41 for (i = ATH79_IP3_IRQ_BASE;
42 i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
43 - irq_set_chip_and_handler(i, &dummy_irq_chip,
44 - handle_level_irq);
45 + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
46
47 irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
48 }
49 @@ -345,13 +344,13 @@ static void qca956x_irq_init(void)
50
51 for (i = ATH79_IP2_IRQ_BASE;
52 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
53 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
54 + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
55
56 irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
57
58 for (i = ATH79_IP3_IRQ_BASE;
59 i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
60 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
61 + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
62
63 irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
64
65 @@ -466,8 +465,35 @@ static void qca953x_ip3_handler(void)
66 do_IRQ(ATH79_CPU_IRQ(3));
67 }
68
69 +static void ath79_ip2_disable(struct irq_data *data)
70 +{
71 + disable_irq(ATH79_CPU_IRQ(2));
72 +}
73 +
74 +static void ath79_ip2_enable(struct irq_data *data)
75 +{
76 + enable_irq(ATH79_CPU_IRQ(2));
77 +}
78 +
79 +static void ath79_ip3_disable(struct irq_data *data)
80 +{
81 + disable_irq(ATH79_CPU_IRQ(3));
82 +}
83 +
84 +static void ath79_ip3_enable(struct irq_data *data)
85 +{
86 + enable_irq(ATH79_CPU_IRQ(3));
87 +}
88 +
89 void __init arch_init_irq(void)
90 {
91 + ip2_chip = dummy_irq_chip;
92 + ip3_chip = dummy_irq_chip;
93 + ip2_chip.irq_disable = ath79_ip2_disable;
94 + ip2_chip.irq_enable = ath79_ip2_enable;
95 + ip3_chip.irq_disable = ath79_ip3_disable;
96 + ip3_chip.irq_enable = ath79_ip3_enable;
97 +
98 if (soc_is_ar71xx()) {
99 ath79_ip2_handler = ar71xx_ip2_handler;
100 ath79_ip3_handler = ar71xx_ip3_handler;