target/linux/at91-2.6/patches/000-at91patches.patch

   1 diff -urN -x CVS linux-2.6.19-final/arch/arm/Kconfig linux-2.6.19/arch/arm/Kconfig
   2 --- linux-2.6.19-final/arch/arm/Kconfig Mon Dec  4 16:39:27 2006
   3 +++ linux-2.6.19/arch/arm/Kconfig       Thu Nov 30 09:08:02 2006
   4 @@ -583,7 +591,7 @@
   5                    ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
   6                    ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
   7                    ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
   8 -                  ARCH_AT91RM9200 || MACH_TRIZEPS4
   9 +                  ARCH_AT91 || MACH_TRIZEPS4
  10         help
  11           If you say Y here, the LEDs on your machine will be used
  12           to provide useful information about your current system status.
  13 diff -urN -x CVS linux-2.6.19-final/arch/arm/configs/at91rm9200dk_defconfig linux-2.6.19/arch/arm/configs/at91rm9200dk_defconfig
  14 --- linux-2.6.19-final/arch/arm/configs/at91rm9200dk_defconfig  Mon Dec  4 16:39:28 2006
  15 +++ linux-2.6.19/arch/arm/configs/at91rm9200dk_defconfig        Mon Nov 20 10:46:02 2006
  16 @@ -357,9 +357,9 @@
  17  #
  18  # CONFIG_MTD_COMPLEX_MAPPINGS is not set
  19  CONFIG_MTD_PHYSMAP=y
  20 -CONFIG_MTD_PHYSMAP_START=0x10000000
  21 -CONFIG_MTD_PHYSMAP_LEN=0x200000
  22 -CONFIG_MTD_PHYSMAP_BANKWIDTH=2
  23 +CONFIG_MTD_PHYSMAP_START=0
  24 +CONFIG_MTD_PHYSMAP_LEN=0
  25 +CONFIG_MTD_PHYSMAP_BANKWIDTH=0
  26  # CONFIG_MTD_ARM_INTEGRATOR is not set
  27  # CONFIG_MTD_IMPA7 is not set
  28  # CONFIG_MTD_PLATRAM is not set
  29 @@ -585,7 +585,9 @@
  30  # CONFIG_USBPCWATCHDOG is not set
  31  # CONFIG_NVRAM is not set
  32  # CONFIG_RTC is not set
  33 -CONFIG_AT91_RTC=y
  34 +CONFIG_RTC_LIB=y
  35 +CONFIG_RTC_CLASS=y
  36 +CONFIG_RTC_DRV_AT91RM9200=y
  37  # CONFIG_DTLK is not set
  38  # CONFIG_R3964 is not set
  39
  40 diff -urN -x CVS linux-2.6.19-final/arch/arm/configs/at91rm9200ek_defconfig linux-2.6.19/arch/arm/configs/at91rm9200ek_defconfig
  41 --- linux-2.6.19-final/arch/arm/configs/at91rm9200ek_defconfig  Mon Dec  4 16:39:28 2006
  42 +++ linux-2.6.19/arch/arm/configs/at91rm9200ek_defconfig        Mon Nov 20 10:45:49 2006
  43 @@ -348,9 +348,9 @@
  44  #
  45  # CONFIG_MTD_COMPLEX_MAPPINGS is not set
  46  CONFIG_MTD_PHYSMAP=y
  47 -CONFIG_MTD_PHYSMAP_START=0x10000000
  48 -CONFIG_MTD_PHYSMAP_LEN=0x800000
  49 -CONFIG_MTD_PHYSMAP_BANKWIDTH=2
  50 +CONFIG_MTD_PHYSMAP_START=0
  51 +CONFIG_MTD_PHYSMAP_LEN=0
  52 +CONFIG_MTD_PHYSMAP_BANKWIDTH=0
  53  # CONFIG_MTD_ARM_INTEGRATOR is not set
  54  # CONFIG_MTD_IMPA7 is not set
  55  # CONFIG_MTD_PLATRAM is not set
  56 @@ -566,7 +566,9 @@
  57  # CONFIG_USBPCWATCHDOG is not set
  58  # CONFIG_NVRAM is not set
  59  # CONFIG_RTC is not set
  60 -CONFIG_AT91_RTC=y
  61 +CONFIG_RTC_LIB=y
  62 +CONFIG_RTC_CLASS=y
  63 +CONFIG_RTC_DRV_AT91RM9200=y
  64  # CONFIG_DTLK is not set
  65  # CONFIG_R3964 is not set
  66
  67 diff -urN -x CVS linux-2.6.19-final/arch/arm/configs/at91sam9260ek_defconfig linux-2.6.19/arch/arm/configs/at91sam9260ek_defconfig
  68 --- linux-2.6.19-final/arch/arm/configs/at91sam9260ek_defconfig Thu Jan  1 02:00:00 1970
  69 +++ linux-2.6.19/arch/arm/configs/at91sam9260ek_defconfig       Mon Nov 20 10:51:08 2006
  70 @@ -0,0 +1,950 @@
  71 +#
  72 +# Automatically generated make config: don't edit
  73 +# Linux kernel version: 2.6.19-rc6
  74 +# Fri Nov 17 18:42:21 2006
  75 +#
  76 +CONFIG_ARM=y
  77 +# CONFIG_GENERIC_TIME is not set
  78 +CONFIG_MMU=y
  79 +CONFIG_GENERIC_HARDIRQS=y
  80 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
  81 +CONFIG_HARDIRQS_SW_RESEND=y
  82 +CONFIG_GENERIC_IRQ_PROBE=y
  83 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
  84 +CONFIG_GENERIC_HWEIGHT=y
  85 +CONFIG_GENERIC_CALIBRATE_DELAY=y
  86 +CONFIG_VECTORS_BASE=0xffff0000
  87 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
  88 +
  89 +#
  90 +# Code maturity level options
  91 +#
  92 +CONFIG_EXPERIMENTAL=y
  93 +CONFIG_BROKEN_ON_SMP=y
  94 +CONFIG_INIT_ENV_ARG_LIMIT=32
  95 +
  96 +#
  97 +# General setup
  98 +#
  99 +CONFIG_LOCALVERSION=""
 100 +# CONFIG_LOCALVERSION_AUTO is not set
 101 +# CONFIG_SWAP is not set
 102 +CONFIG_SYSVIPC=y
 103 +# CONFIG_IPC_NS is not set
 104 +# CONFIG_POSIX_MQUEUE is not set
 105 +# CONFIG_BSD_PROCESS_ACCT is not set
 106 +# CONFIG_TASKSTATS is not set
 107 +# CONFIG_UTS_NS is not set
 108 +# CONFIG_AUDIT is not set
 109 +# CONFIG_IKCONFIG is not set
 110 +# CONFIG_RELAY is not set
 111 +CONFIG_INITRAMFS_SOURCE=""
 112 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 113 +CONFIG_SYSCTL=y
 114 +# CONFIG_EMBEDDED is not set
 115 +CONFIG_UID16=y
 116 +CONFIG_SYSCTL_SYSCALL=y
 117 +CONFIG_KALLSYMS=y
 118 +# CONFIG_KALLSYMS_ALL is not set
 119 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
 120 +CONFIG_HOTPLUG=y
 121 +CONFIG_PRINTK=y
 122 +CONFIG_BUG=y
 123 +CONFIG_ELF_CORE=y
 124 +CONFIG_BASE_FULL=y
 125 +CONFIG_FUTEX=y
 126 +CONFIG_EPOLL=y
 127 +CONFIG_SHMEM=y
 128 +CONFIG_SLAB=y
 129 +CONFIG_VM_EVENT_COUNTERS=y
 130 +CONFIG_RT_MUTEXES=y
 131 +# CONFIG_TINY_SHMEM is not set
 132 +CONFIG_BASE_SMALL=0
 133 +# CONFIG_SLOB is not set
 134 +
 135 +#
 136 +# Loadable module support
 137 +#
 138 +CONFIG_MODULES=y
 139 +CONFIG_MODULE_UNLOAD=y
 140 +# CONFIG_MODULE_FORCE_UNLOAD is not set
 141 +# CONFIG_MODVERSIONS is not set
 142 +# CONFIG_MODULE_SRCVERSION_ALL is not set
 143 +CONFIG_KMOD=y
 144 +
 145 +#
 146 +# Block layer
 147 +#
 148 +CONFIG_BLOCK=y
 149 +# CONFIG_BLK_DEV_IO_TRACE is not set
 150 +
 151 +#
 152 +# IO Schedulers
 153 +#
 154 +CONFIG_IOSCHED_NOOP=y
 155 +CONFIG_IOSCHED_AS=y
 156 +# CONFIG_IOSCHED_DEADLINE is not set
 157 +# CONFIG_IOSCHED_CFQ is not set
 158 +CONFIG_DEFAULT_AS=y
 159 +# CONFIG_DEFAULT_DEADLINE is not set
 160 +# CONFIG_DEFAULT_CFQ is not set
 161 +# CONFIG_DEFAULT_NOOP is not set
 162 +CONFIG_DEFAULT_IOSCHED="anticipatory"
 163 +
 164 +#
 165 +# System Type
 166 +#
 167 +# CONFIG_ARCH_AAEC2000 is not set
 168 +# CONFIG_ARCH_INTEGRATOR is not set
 169 +# CONFIG_ARCH_REALVIEW is not set
 170 +# CONFIG_ARCH_VERSATILE is not set
 171 +CONFIG_ARCH_AT91=y
 172 +# CONFIG_ARCH_CLPS7500 is not set
 173 +# CONFIG_ARCH_CLPS711X is not set
 174 +# CONFIG_ARCH_CO285 is not set
 175 +# CONFIG_ARCH_EBSA110 is not set
 176 +# CONFIG_ARCH_EP93XX is not set
 177 +# CONFIG_ARCH_FOOTBRIDGE is not set
 178 +# CONFIG_ARCH_NETX is not set
 179 +# CONFIG_ARCH_H720X is not set
 180 +# CONFIG_ARCH_IMX is not set
 181 +# CONFIG_ARCH_IOP32X is not set
 182 +# CONFIG_ARCH_IOP33X is not set
 183 +# CONFIG_ARCH_IXP4XX is not set
 184 +# CONFIG_ARCH_IXP2000 is not set
 185 +# CONFIG_ARCH_IXP23XX is not set
 186 +# CONFIG_ARCH_L7200 is not set
 187 +# CONFIG_ARCH_PNX4008 is not set
 188 +# CONFIG_ARCH_PXA is not set
 189 +# CONFIG_ARCH_RPC is not set
 190 +# CONFIG_ARCH_SA1100 is not set
 191 +# CONFIG_ARCH_S3C2410 is not set
 192 +# CONFIG_ARCH_SHARK is not set
 193 +# CONFIG_ARCH_LH7A40X is not set
 194 +# CONFIG_ARCH_OMAP is not set
 195 +
 196 +#
 197 +# Atmel AT91 System-on-Chip
 198 +#
 199 +# CONFIG_ARCH_AT91RM9200 is not set
 200 +CONFIG_ARCH_AT91SAM9260=y
 201 +# CONFIG_ARCH_AT91SAM9261 is not set
 202 +
 203 +#
 204 +# AT91SAM9260 Board Type
 205 +#
 206 +CONFIG_MACH_AT91SAM9260EK=y
 207 +
 208 +#
 209 +# AT91 Board Options
 210 +#
 211 +# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
 212 +
 213 +#
 214 +# AT91 Feature Selections
 215 +#
 216 +# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
 217 +
 218 +#
 219 +# Processor Type
 220 +#
 221 +CONFIG_CPU_32=y
 222 +CONFIG_CPU_ARM926T=y
 223 +CONFIG_CPU_32v5=y
 224 +CONFIG_CPU_ABRT_EV5TJ=y
 225 +CONFIG_CPU_CACHE_VIVT=y
 226 +CONFIG_CPU_COPY_V4WB=y
 227 +CONFIG_CPU_TLB_V4WBI=y
 228 +CONFIG_CPU_CP15=y
 229 +CONFIG_CPU_CP15_MMU=y
 230 +
 231 +#
 232 +# Processor Features
 233 +#
 234 +# CONFIG_ARM_THUMB is not set
 235 +# CONFIG_CPU_ICACHE_DISABLE is not set
 236 +# CONFIG_CPU_DCACHE_DISABLE is not set
 237 +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 238 +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
 239 +
 240 +#
 241 +# Bus support
 242 +#
 243 +
 244 +#
 245 +# PCCARD (PCMCIA/CardBus) support
 246 +#
 247 +# CONFIG_PCCARD is not set
 248 +
 249 +#
 250 +# Kernel Features
 251 +#
 252 +# CONFIG_PREEMPT is not set
 253 +# CONFIG_NO_IDLE_HZ is not set
 254 +CONFIG_HZ=100
 255 +# CONFIG_AEABI is not set
 256 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 257 +CONFIG_SELECT_MEMORY_MODEL=y
 258 +CONFIG_FLATMEM_MANUAL=y
 259 +# CONFIG_DISCONTIGMEM_MANUAL is not set
 260 +# CONFIG_SPARSEMEM_MANUAL is not set
 261 +CONFIG_FLATMEM=y
 262 +CONFIG_FLAT_NODE_MEM_MAP=y
 263 +# CONFIG_SPARSEMEM_STATIC is not set
 264 +CONFIG_SPLIT_PTLOCK_CPUS=4096
 265 +# CONFIG_RESOURCES_64BIT is not set
 266 +# CONFIG_LEDS is not set
 267 +CONFIG_ALIGNMENT_TRAP=y
 268 +
 269 +#
 270 +# Boot options
 271 +#
 272 +CONFIG_ZBOOT_ROM_TEXT=0x0
 273 +CONFIG_ZBOOT_ROM_BSS=0x0
 274 +CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
 275 +# CONFIG_XIP_KERNEL is not set
 276 +
 277 +#
 278 +# Floating point emulation
 279 +#
 280 +
 281 +#
 282 +# At least one emulation must be selected
 283 +#
 284 +CONFIG_FPE_NWFPE=y
 285 +# CONFIG_FPE_NWFPE_XP is not set
 286 +# CONFIG_FPE_FASTFPE is not set
 287 +# CONFIG_VFP is not set
 288 +
 289 +#
 290 +# Userspace binary formats
 291 +#
 292 +CONFIG_BINFMT_ELF=y
 293 +# CONFIG_BINFMT_AOUT is not set
 294 +# CONFIG_BINFMT_MISC is not set
 295 +# CONFIG_ARTHUR is not set
 296 +
 297 +#
 298 +# Power management options
 299 +#
 300 +# CONFIG_PM is not set
 301 +# CONFIG_APM is not set
 302 +
 303 +#
 304 +# Networking
 305 +#
 306 +CONFIG_NET=y
 307 +
 308 +#
 309 +# Networking options
 310 +#
 311 +# CONFIG_NETDEBUG is not set
 312 +CONFIG_PACKET=y
 313 +# CONFIG_PACKET_MMAP is not set
 314 +CONFIG_UNIX=y
 315 +CONFIG_XFRM=y
 316 +# CONFIG_XFRM_USER is not set
 317 +# CONFIG_XFRM_SUB_POLICY is not set
 318 +# CONFIG_NET_KEY is not set
 319 +CONFIG_INET=y
 320 +# CONFIG_IP_MULTICAST is not set
 321 +# CONFIG_IP_ADVANCED_ROUTER is not set
 322 +CONFIG_IP_FIB_HASH=y
 323 +CONFIG_IP_PNP=y
 324 +# CONFIG_IP_PNP_DHCP is not set
 325 +CONFIG_IP_PNP_BOOTP=y
 326 +# CONFIG_IP_PNP_RARP is not set
 327 +# CONFIG_NET_IPIP is not set
 328 +# CONFIG_NET_IPGRE is not set
 329 +# CONFIG_ARPD is not set
 330 +# CONFIG_SYN_COOKIES is not set
 331 +# CONFIG_INET_AH is not set
 332 +# CONFIG_INET_ESP is not set
 333 +# CONFIG_INET_IPCOMP is not set
 334 +# CONFIG_INET_XFRM_TUNNEL is not set
 335 +# CONFIG_INET_TUNNEL is not set
 336 +CONFIG_INET_XFRM_MODE_TRANSPORT=y
 337 +CONFIG_INET_XFRM_MODE_TUNNEL=y
 338 +CONFIG_INET_XFRM_MODE_BEET=y
 339 +CONFIG_INET_DIAG=y
 340 +CONFIG_INET_TCP_DIAG=y
 341 +# CONFIG_TCP_CONG_ADVANCED is not set
 342 +CONFIG_TCP_CONG_CUBIC=y
 343 +CONFIG_DEFAULT_TCP_CONG="cubic"
 344 +# CONFIG_IPV6 is not set
 345 +# CONFIG_INET6_XFRM_TUNNEL is not set
 346 +# CONFIG_INET6_TUNNEL is not set
 347 +# CONFIG_NETWORK_SECMARK is not set
 348 +# CONFIG_NETFILTER is not set
 349 +
 350 +#
 351 +# DCCP Configuration (EXPERIMENTAL)
 352 +#
 353 +# CONFIG_IP_DCCP is not set
 354 +
 355 +#
 356 +# SCTP Configuration (EXPERIMENTAL)
 357 +#
 358 +# CONFIG_IP_SCTP is not set
 359 +
 360 +#
 361 +# TIPC Configuration (EXPERIMENTAL)
 362 +#
 363 +# CONFIG_TIPC is not set
 364 +# CONFIG_ATM is not set
 365 +# CONFIG_BRIDGE is not set
 366 +# CONFIG_VLAN_8021Q is not set
 367 +# CONFIG_DECNET is not set
 368 +# CONFIG_LLC2 is not set
 369 +# CONFIG_IPX is not set
 370 +# CONFIG_ATALK is not set
 371 +# CONFIG_X25 is not set
 372 +# CONFIG_LAPB is not set
 373 +# CONFIG_ECONET is not set
 374 +# CONFIG_WAN_ROUTER is not set
 375 +
 376 +#
 377 +# QoS and/or fair queueing
 378 +#
 379 +# CONFIG_NET_SCHED is not set
 380 +
 381 +#
 382 +# Network testing
 383 +#
 384 +# CONFIG_NET_PKTGEN is not set
 385 +# CONFIG_HAMRADIO is not set
 386 +# CONFIG_IRDA is not set
 387 +# CONFIG_BT is not set
 388 +# CONFIG_IEEE80211 is not set
 389 +
 390 +#
 391 +# Device Drivers
 392 +#
 393 +
 394 +#
 395 +# Generic Driver Options
 396 +#
 397 +CONFIG_STANDALONE=y
 398 +CONFIG_PREVENT_FIRMWARE_BUILD=y
 399 +# CONFIG_FW_LOADER is not set
 400 +# CONFIG_DEBUG_DRIVER is not set
 401 +# CONFIG_SYS_HYPERVISOR is not set
 402 +
 403 +#
 404 +# Connector - unified userspace <-> kernelspace linker
 405 +#
 406 +# CONFIG_CONNECTOR is not set
 407 +
 408 +#
 409 +# Memory Technology Devices (MTD)
 410 +#
 411 +# CONFIG_MTD is not set
 412 +
 413 +#
 414 +# Parallel port support
 415 +#
 416 +# CONFIG_PARPORT is not set
 417 +
 418 +#
 419 +# Plug and Play support
 420 +#
 421 +
 422 +#
 423 +# Block devices
 424 +#
 425 +# CONFIG_BLK_DEV_COW_COMMON is not set
 426 +# CONFIG_BLK_DEV_LOOP is not set
 427 +# CONFIG_BLK_DEV_NBD is not set
 428 +# CONFIG_BLK_DEV_UB is not set
 429 +CONFIG_BLK_DEV_RAM=y
 430 +CONFIG_BLK_DEV_RAM_COUNT=16
 431 +CONFIG_BLK_DEV_RAM_SIZE=8192
 432 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 433 +CONFIG_BLK_DEV_INITRD=y
 434 +# CONFIG_CDROM_PKTCDVD is not set
 435 +# CONFIG_ATA_OVER_ETH is not set
 436 +
 437 +#
 438 +# SCSI device support
 439 +#
 440 +# CONFIG_RAID_ATTRS is not set
 441 +CONFIG_SCSI=y
 442 +# CONFIG_SCSI_NETLINK is not set
 443 +CONFIG_SCSI_PROC_FS=y
 444 +
 445 +#
 446 +# SCSI support type (disk, tape, CD-ROM)
 447 +#
 448 +CONFIG_BLK_DEV_SD=y
 449 +# CONFIG_CHR_DEV_ST is not set
 450 +# CONFIG_CHR_DEV_OSST is not set
 451 +# CONFIG_BLK_DEV_SR is not set
 452 +# CONFIG_CHR_DEV_SG is not set
 453 +# CONFIG_CHR_DEV_SCH is not set
 454 +
 455 +#
 456 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 457 +#
 458 +CONFIG_SCSI_MULTI_LUN=y
 459 +# CONFIG_SCSI_CONSTANTS is not set
 460 +# CONFIG_SCSI_LOGGING is not set
 461 +
 462 +#
 463 +# SCSI Transports
 464 +#
 465 +# CONFIG_SCSI_SPI_ATTRS is not set
 466 +# CONFIG_SCSI_FC_ATTRS is not set
 467 +# CONFIG_SCSI_ISCSI_ATTRS is not set
 468 +# CONFIG_SCSI_SAS_ATTRS is not set
 469 +# CONFIG_SCSI_SAS_LIBSAS is not set
 470 +
 471 +#
 472 +# SCSI low-level drivers
 473 +#
 474 +# CONFIG_ISCSI_TCP is not set
 475 +# CONFIG_SCSI_DEBUG is not set
 476 +
 477 +#
 478 +# Multi-device support (RAID and LVM)
 479 +#
 480 +# CONFIG_MD is not set
 481 +
 482 +#
 483 +# Fusion MPT device support
 484 +#
 485 +# CONFIG_FUSION is not set
 486 +
 487 +#
 488 +# IEEE 1394 (FireWire) support
 489 +#
 490 +
 491 +#
 492 +# I2O device support
 493 +#
 494 +
 495 +#
 496 +# Network device support
 497 +#
 498 +# CONFIG_NETDEVICES is not set
 499 +# CONFIG_NETPOLL is not set
 500 +# CONFIG_NET_POLL_CONTROLLER is not set
 501 +
 502 +#
 503 +# ISDN subsystem
 504 +#
 505 +# CONFIG_ISDN is not set
 506 +
 507 +#
 508 +# Input device support
 509 +#
 510 +CONFIG_INPUT=y
 511 +# CONFIG_INPUT_FF_MEMLESS is not set
 512 +
 513 +#
 514 +# Userland interfaces
 515 +#
 516 +CONFIG_INPUT_MOUSEDEV=y
 517 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 518 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 519 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 520 +# CONFIG_INPUT_JOYDEV is not set
 521 +# CONFIG_INPUT_TSDEV is not set
 522 +# CONFIG_INPUT_EVDEV is not set
 523 +# CONFIG_INPUT_EVBUG is not set
 524 +
 525 +#
 526 +# Input Device Drivers
 527 +#
 528 +# CONFIG_INPUT_KEYBOARD is not set
 529 +# CONFIG_INPUT_MOUSE is not set
 530 +# CONFIG_INPUT_JOYSTICK is not set
 531 +# CONFIG_INPUT_TOUCHSCREEN is not set
 532 +# CONFIG_INPUT_MISC is not set
 533 +
 534 +#
 535 +# Hardware I/O ports
 536 +#
 537 +# CONFIG_SERIO is not set
 538 +# CONFIG_GAMEPORT is not set
 539 +
 540 +#
 541 +# Character devices
 542 +#
 543 +CONFIG_VT=y
 544 +CONFIG_VT_CONSOLE=y
 545 +CONFIG_HW_CONSOLE=y
 546 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
 547 +# CONFIG_SERIAL_NONSTANDARD is not set
 548 +
 549 +#
 550 +# Serial drivers
 551 +#
 552 +# CONFIG_SERIAL_8250 is not set
 553 +
 554 +#
 555 +# Non-8250 serial port support
 556 +#
 557 +CONFIG_SERIAL_ATMEL=y
 558 +CONFIG_SERIAL_ATMEL_CONSOLE=y
 559 +# CONFIG_SERIAL_ATMEL_TTYAT is not set
 560 +CONFIG_SERIAL_CORE=y
 561 +CONFIG_SERIAL_CORE_CONSOLE=y
 562 +CONFIG_UNIX98_PTYS=y
 563 +CONFIG_LEGACY_PTYS=y
 564 +CONFIG_LEGACY_PTY_COUNT=256
 565 +
 566 +#
 567 +# IPMI
 568 +#
 569 +# CONFIG_IPMI_HANDLER is not set
 570 +
 571 +#
 572 +# Watchdog Cards
 573 +#
 574 +CONFIG_WATCHDOG=y
 575 +CONFIG_WATCHDOG_NOWAYOUT=y
 576 +
 577 +#
 578 +# Watchdog Device Drivers
 579 +#
 580 +# CONFIG_SOFT_WATCHDOG is not set
 581 +
 582 +#
 583 +# USB-based Watchdog Cards
 584 +#
 585 +# CONFIG_USBPCWATCHDOG is not set
 586 +CONFIG_HW_RANDOM=y
 587 +# CONFIG_NVRAM is not set
 588 +# CONFIG_DTLK is not set
 589 +# CONFIG_R3964 is not set
 590 +
 591 +#
 592 +# Ftape, the floppy tape device driver
 593 +#
 594 +# CONFIG_RAW_DRIVER is not set
 595 +
 596 +#
 597 +# TPM devices
 598 +#
 599 +# CONFIG_TCG_TPM is not set
 600 +
 601 +#
 602 +# I2C support
 603 +#
 604 +# CONFIG_I2C is not set
 605 +
 606 +#
 607 +# SPI support
 608 +#
 609 +# CONFIG_SPI is not set
 610 +# CONFIG_SPI_MASTER is not set
 611 +
 612 +#
 613 +# Dallas's 1-wire bus
 614 +#
 615 +# CONFIG_W1 is not set
 616 +
 617 +#
 618 +# Hardware Monitoring support
 619 +#
 620 +# CONFIG_HWMON is not set
 621 +# CONFIG_HWMON_VID is not set
 622 +
 623 +#
 624 +# Misc devices
 625 +#
 626 +# CONFIG_TIFM_CORE is not set
 627 +
 628 +#
 629 +# LED devices
 630 +#
 631 +# CONFIG_NEW_LEDS is not set
 632 +
 633 +#
 634 +# LED drivers
 635 +#
 636 +
 637 +#
 638 +# LED Triggers
 639 +#
 640 +
 641 +#
 642 +# Multimedia devices
 643 +#
 644 +# CONFIG_VIDEO_DEV is not set
 645 +
 646 +#
 647 +# Digital Video Broadcasting Devices
 648 +#
 649 +# CONFIG_DVB is not set
 650 +# CONFIG_USB_DABUSB is not set
 651 +
 652 +#
 653 +# Graphics support
 654 +#
 655 +# CONFIG_FIRMWARE_EDID is not set
 656 +# CONFIG_FB is not set
 657 +
 658 +#
 659 +# Console display driver support
 660 +#
 661 +# CONFIG_VGA_CONSOLE is not set
 662 +CONFIG_DUMMY_CONSOLE=y
 663 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 664 +
 665 +#
 666 +# Sound
 667 +#
 668 +# CONFIG_SOUND is not set
 669 +
 670 +#
 671 +# USB support
 672 +#
 673 +CONFIG_USB_ARCH_HAS_HCD=y
 674 +CONFIG_USB_ARCH_HAS_OHCI=y
 675 +# CONFIG_USB_ARCH_HAS_EHCI is not set
 676 +CONFIG_USB=y
 677 +# CONFIG_USB_DEBUG is not set
 678 +
 679 +#
 680 +# Miscellaneous USB options
 681 +#
 682 +CONFIG_USB_DEVICEFS=y
 683 +# CONFIG_USB_BANDWIDTH is not set
 684 +# CONFIG_USB_DYNAMIC_MINORS is not set
 685 +# CONFIG_USB_OTG is not set
 686 +
 687 +#
 688 +# USB Host Controller Drivers
 689 +#
 690 +# CONFIG_USB_ISP116X_HCD is not set
 691 +CONFIG_USB_OHCI_HCD=y
 692 +# CONFIG_USB_OHCI_BIG_ENDIAN is not set
 693 +CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 694 +# CONFIG_USB_SL811_HCD is not set
 695 +
 696 +#
 697 +# USB Device Class drivers
 698 +#
 699 +# CONFIG_USB_ACM is not set
 700 +# CONFIG_USB_PRINTER is not set
 701 +
 702 +#
 703 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 704 +#
 705 +
 706 +#
 707 +# may also be needed; see USB_STORAGE Help for more information
 708 +#
 709 +CONFIG_USB_STORAGE=y
 710 +CONFIG_USB_STORAGE_DEBUG=y
 711 +# CONFIG_USB_STORAGE_DATAFAB is not set
 712 +# CONFIG_USB_STORAGE_FREECOM is not set
 713 +# CONFIG_USB_STORAGE_DPCM is not set
 714 +# CONFIG_USB_STORAGE_USBAT is not set
 715 +# CONFIG_USB_STORAGE_SDDR09 is not set
 716 +# CONFIG_USB_STORAGE_SDDR55 is not set
 717 +# CONFIG_USB_STORAGE_JUMPSHOT is not set
 718 +# CONFIG_USB_STORAGE_ALAUDA is not set
 719 +# CONFIG_USB_STORAGE_KARMA is not set
 720 +# CONFIG_USB_LIBUSUAL is not set
 721 +
 722 +#
 723 +# USB Input Devices
 724 +#
 725 +# CONFIG_USB_HID is not set
 726 +
 727 +#
 728 +# USB HID Boot Protocol drivers
 729 +#
 730 +# CONFIG_USB_KBD is not set
 731 +# CONFIG_USB_MOUSE is not set
 732 +# CONFIG_USB_AIPTEK is not set
 733 +# CONFIG_USB_WACOM is not set
 734 +# CONFIG_USB_ACECAD is not set
 735 +# CONFIG_USB_KBTAB is not set
 736 +# CONFIG_USB_POWERMATE is not set
 737 +# CONFIG_USB_TOUCHSCREEN is not set
 738 +# CONFIG_USB_YEALINK is not set
 739 +# CONFIG_USB_XPAD is not set
 740 +# CONFIG_USB_ATI_REMOTE is not set
 741 +# CONFIG_USB_ATI_REMOTE2 is not set
 742 +# CONFIG_USB_KEYSPAN_REMOTE is not set
 743 +# CONFIG_USB_APPLETOUCH is not set
 744 +
 745 +#
 746 +# USB Imaging devices
 747 +#
 748 +# CONFIG_USB_MDC800 is not set
 749 +# CONFIG_USB_MICROTEK is not set
 750 +
 751 +#
 752 +# USB Network Adapters
 753 +#
 754 +# CONFIG_USB_CATC is not set
 755 +# CONFIG_USB_KAWETH is not set
 756 +# CONFIG_USB_PEGASUS is not set
 757 +# CONFIG_USB_RTL8150 is not set
 758 +# CONFIG_USB_USBNET_MII is not set
 759 +# CONFIG_USB_USBNET is not set
 760 +CONFIG_USB_MON=y
 761 +
 762 +#
 763 +# USB port drivers
 764 +#
 765 +
 766 +#
 767 +# USB Serial Converter support
 768 +#
 769 +# CONFIG_USB_SERIAL is not set
 770 +
 771 +#
 772 +# USB Miscellaneous drivers
 773 +#
 774 +# CONFIG_USB_EMI62 is not set
 775 +# CONFIG_USB_EMI26 is not set
 776 +# CONFIG_USB_ADUTUX is not set
 777 +# CONFIG_USB_AUERSWALD is not set
 778 +# CONFIG_USB_RIO500 is not set
 779 +# CONFIG_USB_LEGOTOWER is not set
 780 +# CONFIG_USB_LCD is not set
 781 +# CONFIG_USB_LED is not set
 782 +# CONFIG_USB_CYPRESS_CY7C63 is not set
 783 +# CONFIG_USB_CYTHERM is not set
 784 +# CONFIG_USB_PHIDGET is not set
 785 +# CONFIG_USB_IDMOUSE is not set
 786 +# CONFIG_USB_FTDI_ELAN is not set
 787 +# CONFIG_USB_APPLEDISPLAY is not set
 788 +# CONFIG_USB_LD is not set
 789 +# CONFIG_USB_TRANCEVIBRATOR is not set
 790 +# CONFIG_USB_TEST is not set
 791 +
 792 +#
 793 +# USB DSL modem support
 794 +#
 795 +
 796 +#
 797 +# USB Gadget Support
 798 +#
 799 +CONFIG_USB_GADGET=y
 800 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
 801 +CONFIG_USB_GADGET_SELECTED=y
 802 +# CONFIG_USB_GADGET_NET2280 is not set
 803 +# CONFIG_USB_GADGET_PXA2XX is not set
 804 +# CONFIG_USB_GADGET_GOKU is not set
 805 +# CONFIG_USB_GADGET_LH7A40X is not set
 806 +# CONFIG_USB_GADGET_OMAP is not set
 807 +CONFIG_USB_GADGET_AT91=y
 808 +CONFIG_USB_AT91=y
 809 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
 810 +# CONFIG_USB_GADGET_DUALSPEED is not set
 811 +CONFIG_USB_ZERO=m
 812 +# CONFIG_USB_ETH is not set
 813 +CONFIG_USB_GADGETFS=m
 814 +CONFIG_USB_FILE_STORAGE=m
 815 +# CONFIG_USB_FILE_STORAGE_TEST is not set
 816 +CONFIG_USB_G_SERIAL=m
 817 +# CONFIG_USB_MIDI_GADGET is not set
 818 +
 819 +#
 820 +# MMC/SD Card support
 821 +#
 822 +# CONFIG_MMC is not set
 823 +
 824 +#
 825 +# Real Time Clock
 826 +#
 827 +CONFIG_RTC_LIB=y
 828 +# CONFIG_RTC_CLASS is not set
 829 +
 830 +#
 831 +# File systems
 832 +#
 833 +CONFIG_EXT2_FS=y
 834 +# CONFIG_EXT2_FS_XATTR is not set
 835 +# CONFIG_EXT2_FS_XIP is not set
 836 +# CONFIG_EXT3_FS is not set
 837 +# CONFIG_EXT4DEV_FS is not set
 838 +# CONFIG_REISERFS_FS is not set
 839 +# CONFIG_JFS_FS is not set
 840 +# CONFIG_FS_POSIX_ACL is not set
 841 +# CONFIG_XFS_FS is not set
 842 +# CONFIG_GFS2_FS is not set
 843 +# CONFIG_OCFS2_FS is not set
 844 +# CONFIG_MINIX_FS is not set
 845 +# CONFIG_ROMFS_FS is not set
 846 +CONFIG_INOTIFY=y
 847 +CONFIG_INOTIFY_USER=y
 848 +# CONFIG_QUOTA is not set
 849 +CONFIG_DNOTIFY=y
 850 +# CONFIG_AUTOFS_FS is not set
 851 +# CONFIG_AUTOFS4_FS is not set
 852 +# CONFIG_FUSE_FS is not set
 853 +
 854 +#
 855 +# CD-ROM/DVD Filesystems
 856 +#
 857 +# CONFIG_ISO9660_FS is not set
 858 +# CONFIG_UDF_FS is not set
 859 +
 860 +#
 861 +# DOS/FAT/NT Filesystems
 862 +#
 863 +CONFIG_FAT_FS=y
 864 +# CONFIG_MSDOS_FS is not set
 865 +CONFIG_VFAT_FS=y
 866 +CONFIG_FAT_DEFAULT_CODEPAGE=437
 867 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 868 +# CONFIG_NTFS_FS is not set
 869 +
 870 +#
 871 +# Pseudo filesystems
 872 +#
 873 +CONFIG_PROC_FS=y
 874 +CONFIG_PROC_SYSCTL=y
 875 +CONFIG_SYSFS=y
 876 +CONFIG_TMPFS=y
 877 +# CONFIG_TMPFS_POSIX_ACL is not set
 878 +# CONFIG_HUGETLB_PAGE is not set
 879 +CONFIG_RAMFS=y
 880 +# CONFIG_CONFIGFS_FS is not set
 881 +
 882 +#
 883 +# Miscellaneous filesystems
 884 +#
 885 +# CONFIG_ADFS_FS is not set
 886 +# CONFIG_AFFS_FS is not set
 887 +# CONFIG_HFS_FS is not set
 888 +# CONFIG_HFSPLUS_FS is not set
 889 +# CONFIG_BEFS_FS is not set
 890 +# CONFIG_BFS_FS is not set
 891 +# CONFIG_EFS_FS is not set
 892 +CONFIG_CRAMFS=y
 893 +# CONFIG_VXFS_FS is not set
 894 +# CONFIG_HPFS_FS is not set
 895 +# CONFIG_QNX4FS_FS is not set
 896 +# CONFIG_SYSV_FS is not set
 897 +# CONFIG_UFS_FS is not set
 898 +
 899 +#
 900 +# Network File Systems
 901 +#
 902 +# CONFIG_NFS_FS is not set
 903 +# CONFIG_NFSD is not set
 904 +# CONFIG_SMB_FS is not set
 905 +# CONFIG_CIFS is not set
 906 +# CONFIG_NCP_FS is not set
 907 +# CONFIG_CODA_FS is not set
 908 +# CONFIG_AFS_FS is not set
 909 +# CONFIG_9P_FS is not set
 910 +
 911 +#
 912 +# Partition Types
 913 +#
 914 +# CONFIG_PARTITION_ADVANCED is not set
 915 +CONFIG_MSDOS_PARTITION=y
 916 +
 917 +#
 918 +# Native Language Support
 919 +#
 920 +CONFIG_NLS=y
 921 +CONFIG_NLS_DEFAULT="iso8859-1"
 922 +CONFIG_NLS_CODEPAGE_437=y
 923 +# CONFIG_NLS_CODEPAGE_737 is not set
 924 +# CONFIG_NLS_CODEPAGE_775 is not set
 925 +CONFIG_NLS_CODEPAGE_850=y
 926 +# CONFIG_NLS_CODEPAGE_852 is not set
 927 +# CONFIG_NLS_CODEPAGE_855 is not set
 928 +# CONFIG_NLS_CODEPAGE_857 is not set
 929 +# CONFIG_NLS_CODEPAGE_860 is not set
 930 +# CONFIG_NLS_CODEPAGE_861 is not set
 931 +# CONFIG_NLS_CODEPAGE_862 is not set
 932 +# CONFIG_NLS_CODEPAGE_863 is not set
 933 +# CONFIG_NLS_CODEPAGE_864 is not set
 934 +# CONFIG_NLS_CODEPAGE_865 is not set
 935 +# CONFIG_NLS_CODEPAGE_866 is not set
 936 +# CONFIG_NLS_CODEPAGE_869 is not set
 937 +# CONFIG_NLS_CODEPAGE_936 is not set
 938 +# CONFIG_NLS_CODEPAGE_950 is not set
 939 +# CONFIG_NLS_CODEPAGE_932 is not set
 940 +# CONFIG_NLS_CODEPAGE_949 is not set
 941 +# CONFIG_NLS_CODEPAGE_874 is not set
 942 +# CONFIG_NLS_ISO8859_8 is not set
 943 +# CONFIG_NLS_CODEPAGE_1250 is not set
 944 +# CONFIG_NLS_CODEPAGE_1251 is not set
 945 +# CONFIG_NLS_ASCII is not set
 946 +CONFIG_NLS_ISO8859_1=y
 947 +# CONFIG_NLS_ISO8859_2 is not set
 948 +# CONFIG_NLS_ISO8859_3 is not set
 949 +# CONFIG_NLS_ISO8859_4 is not set
 950 +# CONFIG_NLS_ISO8859_5 is not set
 951 +# CONFIG_NLS_ISO8859_6 is not set
 952 +# CONFIG_NLS_ISO8859_7 is not set
 953 +# CONFIG_NLS_ISO8859_9 is not set
 954 +# CONFIG_NLS_ISO8859_13 is not set
 955 +# CONFIG_NLS_ISO8859_14 is not set
 956 +# CONFIG_NLS_ISO8859_15 is not set
 957 +# CONFIG_NLS_KOI8_R is not set
 958 +# CONFIG_NLS_KOI8_U is not set
 959 +# CONFIG_NLS_UTF8 is not set
 960 +
 961 +#
 962 +# Profiling support
 963 +#
 964 +# CONFIG_PROFILING is not set
 965 +
 966 +#
 967 +# Kernel hacking
 968 +#
 969 +# CONFIG_PRINTK_TIME is not set
 970 +CONFIG_ENABLE_MUST_CHECK=y
 971 +# CONFIG_MAGIC_SYSRQ is not set
 972 +# CONFIG_UNUSED_SYMBOLS is not set
 973 +CONFIG_DEBUG_KERNEL=y
 974 +CONFIG_LOG_BUF_SHIFT=14
 975 +CONFIG_DETECT_SOFTLOCKUP=y
 976 +# CONFIG_SCHEDSTATS is not set
 977 +# CONFIG_DEBUG_SLAB is not set
 978 +# CONFIG_DEBUG_RT_MUTEXES is not set
 979 +# CONFIG_RT_MUTEX_TESTER is not set
 980 +# CONFIG_DEBUG_SPINLOCK is not set
 981 +# CONFIG_DEBUG_MUTEXES is not set
 982 +# CONFIG_DEBUG_RWSEMS is not set
 983 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 984 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 985 +# CONFIG_DEBUG_KOBJECT is not set
 986 +CONFIG_DEBUG_BUGVERBOSE=y
 987 +# CONFIG_DEBUG_INFO is not set
 988 +# CONFIG_DEBUG_FS is not set
 989 +# CONFIG_DEBUG_VM is not set
 990 +# CONFIG_DEBUG_LIST is not set
 991 +CONFIG_FRAME_POINTER=y
 992 +CONFIG_FORCED_INLINING=y
 993 +# CONFIG_HEADERS_CHECK is not set
 994 +# CONFIG_RCU_TORTURE_TEST is not set
 995 +CONFIG_DEBUG_USER=y
 996 +# CONFIG_DEBUG_WAITQ is not set
 997 +# CONFIG_DEBUG_ERRORS is not set
 998 +CONFIG_DEBUG_LL=y
 999 +# CONFIG_DEBUG_ICEDCC is not set
1000 +
1001 +#
1002 +# Security options
1003 +#
1004 +# CONFIG_KEYS is not set
1005 +# CONFIG_SECURITY is not set
1006 +
1007 +#
1008 +# Cryptographic options
1009 +#
1010 +# CONFIG_CRYPTO is not set
1011 +
1012 +#
1013 +# Library routines
1014 +#
1015 +# CONFIG_CRC_CCITT is not set
1016 +# CONFIG_CRC16 is not set
1017 +CONFIG_CRC32=y
1018 +# CONFIG_LIBCRC32C is not set
1019 +CONFIG_ZLIB_INFLATE=y
1020 +CONFIG_PLIST=y
1021 diff -urN -x CVS linux-2.6.19-final/arch/arm/configs/at91sam9261ek_defconfig linux-2.6.19/arch/arm/configs/at91sam9261ek_defconfig
1022 --- linux-2.6.19-final/arch/arm/configs/at91sam9261ek_defconfig Thu Jan  1 02:00:00 1970
1023 +++ linux-2.6.19/arch/arm/configs/at91sam9261ek_defconfig       Mon Nov 20 10:51:08 2006
1024 @@ -0,0 +1,1106 @@
1025 +#
1026 +# Automatically generated make config: don't edit
1027 +# Linux kernel version: 2.6.19-rc6
1028 +# Fri Nov 17 18:00:38 2006
1029 +#
1030 +CONFIG_ARM=y
1031 +# CONFIG_GENERIC_TIME is not set
1032 +CONFIG_MMU=y
1033 +CONFIG_GENERIC_HARDIRQS=y
1034 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1035 +CONFIG_HARDIRQS_SW_RESEND=y
1036 +CONFIG_GENERIC_IRQ_PROBE=y
1037 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
1038 +CONFIG_GENERIC_HWEIGHT=y
1039 +CONFIG_GENERIC_CALIBRATE_DELAY=y
1040 +CONFIG_VECTORS_BASE=0xffff0000
1041 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
1042 +
1043 +#
1044 +# Code maturity level options
1045 +#
1046 +CONFIG_EXPERIMENTAL=y
1047 +CONFIG_BROKEN_ON_SMP=y
1048 +CONFIG_INIT_ENV_ARG_LIMIT=32
1049 +
1050 +#
1051 +# General setup
1052 +#
1053 +CONFIG_LOCALVERSION=""
1054 +# CONFIG_LOCALVERSION_AUTO is not set
1055 +# CONFIG_SWAP is not set
1056 +CONFIG_SYSVIPC=y
1057 +# CONFIG_IPC_NS is not set
1058 +# CONFIG_POSIX_MQUEUE is not set
1059 +# CONFIG_BSD_PROCESS_ACCT is not set
1060 +# CONFIG_TASKSTATS is not set
1061 +# CONFIG_UTS_NS is not set
1062 +# CONFIG_AUDIT is not set
1063 +# CONFIG_IKCONFIG is not set
1064 +# CONFIG_RELAY is not set
1065 +CONFIG_INITRAMFS_SOURCE=""
1066 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
1067 +CONFIG_SYSCTL=y
1068 +# CONFIG_EMBEDDED is not set
1069 +CONFIG_UID16=y
1070 +CONFIG_SYSCTL_SYSCALL=y
1071 +CONFIG_KALLSYMS=y
1072 +# CONFIG_KALLSYMS_ALL is not set
1073 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
1074 +CONFIG_HOTPLUG=y
1075 +CONFIG_PRINTK=y
1076 +CONFIG_BUG=y
1077 +CONFIG_ELF_CORE=y
1078 +CONFIG_BASE_FULL=y
1079 +CONFIG_FUTEX=y
1080 +CONFIG_EPOLL=y
1081 +CONFIG_SHMEM=y
1082 +CONFIG_SLAB=y
1083 +CONFIG_VM_EVENT_COUNTERS=y
1084 +CONFIG_RT_MUTEXES=y
1085 +# CONFIG_TINY_SHMEM is not set
1086 +CONFIG_BASE_SMALL=0
1087 +# CONFIG_SLOB is not set
1088 +
1089 +#
1090 +# Loadable module support
1091 +#
1092 +CONFIG_MODULES=y
1093 +CONFIG_MODULE_UNLOAD=y
1094 +# CONFIG_MODULE_FORCE_UNLOAD is not set
1095 +# CONFIG_MODVERSIONS is not set
1096 +# CONFIG_MODULE_SRCVERSION_ALL is not set
1097 +CONFIG_KMOD=y
1098 +
1099 +#
1100 +# Block layer
1101 +#
1102 +CONFIG_BLOCK=y
1103 +# CONFIG_BLK_DEV_IO_TRACE is not set
1104 +
1105 +#
1106 +# IO Schedulers
1107 +#
1108 +CONFIG_IOSCHED_NOOP=y
1109 +CONFIG_IOSCHED_AS=y
1110 +# CONFIG_IOSCHED_DEADLINE is not set
1111 +# CONFIG_IOSCHED_CFQ is not set
1112 +CONFIG_DEFAULT_AS=y
1113 +# CONFIG_DEFAULT_DEADLINE is not set
1114 +# CONFIG_DEFAULT_CFQ is not set
1115 +# CONFIG_DEFAULT_NOOP is not set
1116 +CONFIG_DEFAULT_IOSCHED="anticipatory"
1117 +
1118 +#
1119 +# System Type
1120 +#
1121 +# CONFIG_ARCH_AAEC2000 is not set
1122 +# CONFIG_ARCH_INTEGRATOR is not set
1123 +# CONFIG_ARCH_REALVIEW is not set
1124 +# CONFIG_ARCH_VERSATILE is not set
1125 +CONFIG_ARCH_AT91=y
1126 +# CONFIG_ARCH_CLPS7500 is not set
1127 +# CONFIG_ARCH_CLPS711X is not set
1128 +# CONFIG_ARCH_CO285 is not set
1129 +# CONFIG_ARCH_EBSA110 is not set
1130 +# CONFIG_ARCH_EP93XX is not set
1131 +# CONFIG_ARCH_FOOTBRIDGE is not set
1132 +# CONFIG_ARCH_NETX is not set
1133 +# CONFIG_ARCH_H720X is not set
1134 +# CONFIG_ARCH_IMX is not set
1135 +# CONFIG_ARCH_IOP32X is not set
1136 +# CONFIG_ARCH_IOP33X is not set
1137 +# CONFIG_ARCH_IXP4XX is not set
1138 +# CONFIG_ARCH_IXP2000 is not set
1139 +# CONFIG_ARCH_IXP23XX is not set
1140 +# CONFIG_ARCH_L7200 is not set
1141 +# CONFIG_ARCH_PNX4008 is not set
1142 +# CONFIG_ARCH_PXA is not set
1143 +# CONFIG_ARCH_RPC is not set
1144 +# CONFIG_ARCH_SA1100 is not set
1145 +# CONFIG_ARCH_S3C2410 is not set
1146 +# CONFIG_ARCH_SHARK is not set
1147 +# CONFIG_ARCH_LH7A40X is not set
1148 +# CONFIG_ARCH_OMAP is not set
1149 +
1150 +#
1151 +# Atmel AT91 System-on-Chip
1152 +#
1153 +# CONFIG_ARCH_AT91RM9200 is not set
1154 +# CONFIG_ARCH_AT91SAM9260 is not set
1155 +CONFIG_ARCH_AT91SAM9261=y
1156 +
1157 +#
1158 +# AT91SAM9261 Board Type
1159 +#
1160 +CONFIG_MACH_AT91SAM9261EK=y
1161 +
1162 +#
1163 +# AT91 Board Options
1164 +#
1165 +# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
1166 +
1167 +#
1168 +# AT91 Feature Selections
1169 +#
1170 +# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
1171 +
1172 +#
1173 +# Processor Type
1174 +#
1175 +CONFIG_CPU_32=y
1176 +CONFIG_CPU_ARM926T=y
1177 +CONFIG_CPU_32v5=y
1178 +CONFIG_CPU_ABRT_EV5TJ=y
1179 +CONFIG_CPU_CACHE_VIVT=y
1180 +CONFIG_CPU_COPY_V4WB=y
1181 +CONFIG_CPU_TLB_V4WBI=y
1182 +CONFIG_CPU_CP15=y
1183 +CONFIG_CPU_CP15_MMU=y
1184 +
1185 +#
1186 +# Processor Features
1187 +#
1188 +# CONFIG_ARM_THUMB is not set
1189 +# CONFIG_CPU_ICACHE_DISABLE is not set
1190 +# CONFIG_CPU_DCACHE_DISABLE is not set
1191 +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
1192 +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
1193 +
1194 +#
1195 +# Bus support
1196 +#
1197 +
1198 +#
1199 +# PCCARD (PCMCIA/CardBus) support
1200 +#
1201 +# CONFIG_PCCARD is not set
1202 +
1203 +#
1204 +# Kernel Features
1205 +#
1206 +# CONFIG_PREEMPT is not set
1207 +# CONFIG_NO_IDLE_HZ is not set
1208 +CONFIG_HZ=100
1209 +# CONFIG_AEABI is not set
1210 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
1211 +CONFIG_SELECT_MEMORY_MODEL=y
1212 +CONFIG_FLATMEM_MANUAL=y
1213 +# CONFIG_DISCONTIGMEM_MANUAL is not set
1214 +# CONFIG_SPARSEMEM_MANUAL is not set
1215 +CONFIG_FLATMEM=y
1216 +CONFIG_FLAT_NODE_MEM_MAP=y
1217 +# CONFIG_SPARSEMEM_STATIC is not set
1218 +CONFIG_SPLIT_PTLOCK_CPUS=4096
1219 +# CONFIG_RESOURCES_64BIT is not set
1220 +# CONFIG_LEDS is not set
1221 +CONFIG_ALIGNMENT_TRAP=y
1222 +
1223 +#
1224 +# Boot options
1225 +#
1226 +CONFIG_ZBOOT_ROM_TEXT=0x0
1227 +CONFIG_ZBOOT_ROM_BSS=0x0
1228 +CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
1229 +# CONFIG_XIP_KERNEL is not set
1230 +
1231 +#
1232 +# Floating point emulation
1233 +#
1234 +
1235 +#
1236 +# At least one emulation must be selected
1237 +#
1238 +CONFIG_FPE_NWFPE=y
1239 +# CONFIG_FPE_NWFPE_XP is not set
1240 +# CONFIG_FPE_FASTFPE is not set
1241 +# CONFIG_VFP is not set
1242 +
1243 +#
1244 +# Userspace binary formats
1245 +#
1246 +CONFIG_BINFMT_ELF=y
1247 +# CONFIG_BINFMT_AOUT is not set
1248 +# CONFIG_BINFMT_MISC is not set
1249 +# CONFIG_ARTHUR is not set
1250 +
1251 +#
1252 +# Power management options
1253 +#
1254 +# CONFIG_PM is not set
1255 +# CONFIG_APM is not set
1256 +
1257 +#
1258 +# Networking
1259 +#
1260 +CONFIG_NET=y
1261 +
1262 +#
1263 +# Networking options
1264 +#
1265 +# CONFIG_NETDEBUG is not set
1266 +CONFIG_PACKET=y
1267 +# CONFIG_PACKET_MMAP is not set
1268 +CONFIG_UNIX=y
1269 +CONFIG_XFRM=y
1270 +# CONFIG_XFRM_USER is not set
1271 +# CONFIG_XFRM_SUB_POLICY is not set
1272 +# CONFIG_NET_KEY is not set
1273 +CONFIG_INET=y
1274 +# CONFIG_IP_MULTICAST is not set
1275 +# CONFIG_IP_ADVANCED_ROUTER is not set
1276 +CONFIG_IP_FIB_HASH=y
1277 +CONFIG_IP_PNP=y
1278 +# CONFIG_IP_PNP_DHCP is not set
1279 +CONFIG_IP_PNP_BOOTP=y
1280 +# CONFIG_IP_PNP_RARP is not set
1281 +# CONFIG_NET_IPIP is not set
1282 +# CONFIG_NET_IPGRE is not set
1283 +# CONFIG_ARPD is not set
1284 +# CONFIG_SYN_COOKIES is not set
1285 +# CONFIG_INET_AH is not set
1286 +# CONFIG_INET_ESP is not set
1287 +# CONFIG_INET_IPCOMP is not set
1288 +# CONFIG_INET_XFRM_TUNNEL is not set
1289 +# CONFIG_INET_TUNNEL is not set
1290 +CONFIG_INET_XFRM_MODE_TRANSPORT=y
1291 +CONFIG_INET_XFRM_MODE_TUNNEL=y
1292 +CONFIG_INET_XFRM_MODE_BEET=y
1293 +CONFIG_INET_DIAG=y
1294 +CONFIG_INET_TCP_DIAG=y
1295 +# CONFIG_TCP_CONG_ADVANCED is not set
1296 +CONFIG_TCP_CONG_CUBIC=y
1297 +CONFIG_DEFAULT_TCP_CONG="cubic"
1298 +# CONFIG_IPV6 is not set
1299 +# CONFIG_INET6_XFRM_TUNNEL is not set
1300 +# CONFIG_INET6_TUNNEL is not set
1301 +# CONFIG_NETWORK_SECMARK is not set
1302 +# CONFIG_NETFILTER is not set
1303 +
1304 +#
1305 +# DCCP Configuration (EXPERIMENTAL)
1306 +#
1307 +# CONFIG_IP_DCCP is not set
1308 +
1309 +#
1310 +# SCTP Configuration (EXPERIMENTAL)
1311 +#
1312 +# CONFIG_IP_SCTP is not set
1313 +
1314 +#
1315 +# TIPC Configuration (EXPERIMENTAL)
1316 +#
1317 +# CONFIG_TIPC is not set
1318 +# CONFIG_ATM is not set
1319 +# CONFIG_BRIDGE is not set
1320 +# CONFIG_VLAN_8021Q is not set
1321 +# CONFIG_DECNET is not set
1322 +# CONFIG_LLC2 is not set
1323 +# CONFIG_IPX is not set
1324 +# CONFIG_ATALK is not set
1325 +# CONFIG_X25 is not set
1326 +# CONFIG_LAPB is not set
1327 +# CONFIG_ECONET is not set
1328 +# CONFIG_WAN_ROUTER is not set
1329 +
1330 +#
1331 +# QoS and/or fair queueing
1332 +#
1333 +# CONFIG_NET_SCHED is not set
1334 +
1335 +#
1336 +# Network testing
1337 +#
1338 +# CONFIG_NET_PKTGEN is not set
1339 +# CONFIG_HAMRADIO is not set
1340 +# CONFIG_IRDA is not set
1341 +# CONFIG_BT is not set
1342 +# CONFIG_IEEE80211 is not set
1343 +
1344 +#
1345 +# Device Drivers
1346 +#
1347 +
1348 +#
1349 +# Generic Driver Options
1350 +#
1351 +CONFIG_STANDALONE=y
1352 +CONFIG_PREVENT_FIRMWARE_BUILD=y
1353 +# CONFIG_FW_LOADER is not set
1354 +# CONFIG_DEBUG_DRIVER is not set
1355 +# CONFIG_SYS_HYPERVISOR is not set
1356 +
1357 +#
1358 +# Connector - unified userspace <-> kernelspace linker
1359 +#
1360 +# CONFIG_CONNECTOR is not set
1361 +
1362 +#
1363 +# Memory Technology Devices (MTD)
1364 +#
1365 +CONFIG_MTD=y
1366 +# CONFIG_MTD_DEBUG is not set
1367 +# CONFIG_MTD_CONCAT is not set
1368 +CONFIG_MTD_PARTITIONS=y
1369 +# CONFIG_MTD_REDBOOT_PARTS is not set
1370 +CONFIG_MTD_CMDLINE_PARTS=y
1371 +# CONFIG_MTD_AFS_PARTS is not set
1372 +
1373 +#
1374 +# User Modules And Translation Layers
1375 +#
1376 +# CONFIG_MTD_CHAR is not set
1377 +CONFIG_MTD_BLOCK=y
1378 +# CONFIG_FTL is not set
1379 +# CONFIG_NFTL is not set
1380 +# CONFIG_INFTL is not set
1381 +# CONFIG_RFD_FTL is not set
1382 +# CONFIG_SSFDC is not set
1383 +
1384 +#
1385 +# RAM/ROM/Flash chip drivers
1386 +#
1387 +# CONFIG_MTD_CFI is not set
1388 +# CONFIG_MTD_JEDECPROBE is not set
1389 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
1390 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
1391 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
1392 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
1393 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
1394 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
1395 +CONFIG_MTD_CFI_I1=y
1396 +CONFIG_MTD_CFI_I2=y
1397 +# CONFIG_MTD_CFI_I4 is not set
1398 +# CONFIG_MTD_CFI_I8 is not set
1399 +# CONFIG_MTD_RAM is not set
1400 +# CONFIG_MTD_ROM is not set
1401 +# CONFIG_MTD_ABSENT is not set
1402 +# CONFIG_MTD_OBSOLETE_CHIPS is not set
1403 +
1404 +#
1405 +# Mapping drivers for chip access
1406 +#
1407 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
1408 +# CONFIG_MTD_PLATRAM is not set
1409 +
1410 +#
1411 +# Self-contained MTD device drivers
1412 +#
1413 +# CONFIG_MTD_SLRAM is not set
1414 +# CONFIG_MTD_PHRAM is not set
1415 +# CONFIG_MTD_MTDRAM is not set
1416 +# CONFIG_MTD_BLOCK2MTD is not set
1417 +
1418 +#
1419 +# Disk-On-Chip Device Drivers
1420 +#
1421 +# CONFIG_MTD_DOC2000 is not set
1422 +# CONFIG_MTD_DOC2001 is not set
1423 +# CONFIG_MTD_DOC2001PLUS is not set
1424 +
1425 +#
1426 +# NAND Flash Device Drivers
1427 +#
1428 +CONFIG_MTD_NAND=y
1429 +# CONFIG_MTD_NAND_VERIFY_WRITE is not set
1430 +# CONFIG_MTD_NAND_ECC_SMC is not set
1431 +CONFIG_MTD_NAND_IDS=y
1432 +# CONFIG_MTD_NAND_DISKONCHIP is not set
1433 +CONFIG_MTD_NAND_AT91=y
1434 +# CONFIG_MTD_NAND_NANDSIM is not set
1435 +
1436 +#
1437 +# OneNAND Flash Device Drivers
1438 +#
1439 +# CONFIG_MTD_ONENAND is not set
1440 +
1441 +#
1442 +# Parallel port support
1443 +#
1444 +# CONFIG_PARPORT is not set
1445 +
1446 +#
1447 +# Plug and Play support
1448 +#
1449 +
1450 +#
1451 +# Block devices
1452 +#
1453 +# CONFIG_BLK_DEV_COW_COMMON is not set
1454 +# CONFIG_BLK_DEV_LOOP is not set
1455 +# CONFIG_BLK_DEV_NBD is not set
1456 +# CONFIG_BLK_DEV_UB is not set
1457 +CONFIG_BLK_DEV_RAM=y
1458 +CONFIG_BLK_DEV_RAM_COUNT=16
1459 +CONFIG_BLK_DEV_RAM_SIZE=8192
1460 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
1461 +CONFIG_BLK_DEV_INITRD=y
1462 +# CONFIG_CDROM_PKTCDVD is not set
1463 +# CONFIG_ATA_OVER_ETH is not set
1464 +
1465 +#
1466 +# SCSI device support
1467 +#
1468 +# CONFIG_RAID_ATTRS is not set
1469 +CONFIG_SCSI=y
1470 +# CONFIG_SCSI_NETLINK is not set
1471 +CONFIG_SCSI_PROC_FS=y
1472 +
1473 +#
1474 +# SCSI support type (disk, tape, CD-ROM)
1475 +#
1476 +CONFIG_BLK_DEV_SD=y
1477 +# CONFIG_CHR_DEV_ST is not set
1478 +# CONFIG_CHR_DEV_OSST is not set
1479 +# CONFIG_BLK_DEV_SR is not set
1480 +# CONFIG_CHR_DEV_SG is not set
1481 +# CONFIG_CHR_DEV_SCH is not set
1482 +
1483 +#
1484 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
1485 +#
1486 +CONFIG_SCSI_MULTI_LUN=y
1487 +# CONFIG_SCSI_CONSTANTS is not set
1488 +# CONFIG_SCSI_LOGGING is not set
1489 +
1490 +#
1491 +# SCSI Transports
1492 +#
1493 +# CONFIG_SCSI_SPI_ATTRS is not set
1494 +# CONFIG_SCSI_FC_ATTRS is not set
1495 +# CONFIG_SCSI_ISCSI_ATTRS is not set
1496 +# CONFIG_SCSI_SAS_ATTRS is not set
1497 +# CONFIG_SCSI_SAS_LIBSAS is not set
1498 +
1499 +#
1500 +# SCSI low-level drivers
1501 +#
1502 +# CONFIG_ISCSI_TCP is not set
1503 +# CONFIG_SCSI_DEBUG is not set
1504 +
1505 +#
1506 +# Multi-device support (RAID and LVM)
1507 +#
1508 +# CONFIG_MD is not set
1509 +
1510 +#
1511 +# Fusion MPT device support
1512 +#
1513 +# CONFIG_FUSION is not set
1514 +
1515 +#
1516 +# IEEE 1394 (FireWire) support
1517 +#
1518 +
1519 +#
1520 +# I2O device support
1521 +#
1522 +
1523 +#
1524 +# Network device support
1525 +#
1526 +CONFIG_NETDEVICES=y
1527 +# CONFIG_DUMMY is not set
1528 +# CONFIG_BONDING is not set
1529 +# CONFIG_EQUALIZER is not set
1530 +# CONFIG_TUN is not set
1531 +
1532 +#
1533 +# PHY device support
1534 +#
1535 +# CONFIG_PHYLIB is not set
1536 +
1537 +#
1538 +# Ethernet (10 or 100Mbit)
1539 +#
1540 +CONFIG_NET_ETHERNET=y
1541 +CONFIG_MII=y
1542 +# CONFIG_SMC91X is not set
1543 +CONFIG_DM9000=y
1544 +
1545 +#
1546 +# Ethernet (1000 Mbit)
1547 +#
1548 +
1549 +#
1550 +# Ethernet (10000 Mbit)
1551 +#
1552 +
1553 +#
1554 +# Token Ring devices
1555 +#
1556 +
1557 +#
1558 +# Wireless LAN (non-hamradio)
1559 +#
1560 +# CONFIG_NET_RADIO is not set
1561 +
1562 +#
1563 +# Wan interfaces
1564 +#
1565 +# CONFIG_WAN is not set
1566 +# CONFIG_PPP is not set
1567 +# CONFIG_SLIP is not set
1568 +# CONFIG_SHAPER is not set
1569 +# CONFIG_NETCONSOLE is not set
1570 +# CONFIG_NETPOLL is not set
1571 +# CONFIG_NET_POLL_CONTROLLER is not set
1572 +
1573 +#
1574 +# ISDN subsystem
1575 +#
1576 +# CONFIG_ISDN is not set
1577 +
1578 +#
1579 +# Input device support
1580 +#
1581 +CONFIG_INPUT=y
1582 +# CONFIG_INPUT_FF_MEMLESS is not set
1583 +
1584 +#
1585 +# Userland interfaces
1586 +#
1587 +CONFIG_INPUT_MOUSEDEV=y
1588 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1589 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
1590 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
1591 +# CONFIG_INPUT_JOYDEV is not set
1592 +# CONFIG_INPUT_TSDEV is not set
1593 +# CONFIG_INPUT_EVDEV is not set
1594 +# CONFIG_INPUT_EVBUG is not set
1595 +
1596 +#
1597 +# Input Device Drivers
1598 +#
1599 +# CONFIG_INPUT_KEYBOARD is not set
1600 +# CONFIG_INPUT_MOUSE is not set
1601 +# CONFIG_INPUT_JOYSTICK is not set
1602 +# CONFIG_INPUT_TOUCHSCREEN is not set
1603 +# CONFIG_INPUT_MISC is not set
1604 +
1605 +#
1606 +# Hardware I/O ports
1607 +#
1608 +# CONFIG_SERIO is not set
1609 +# CONFIG_GAMEPORT is not set
1610 +
1611 +#
1612 +# Character devices
1613 +#
1614 +CONFIG_VT=y
1615 +CONFIG_VT_CONSOLE=y
1616 +CONFIG_HW_CONSOLE=y
1617 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
1618 +# CONFIG_SERIAL_NONSTANDARD is not set
1619 +
1620 +#
1621 +# Serial drivers
1622 +#
1623 +# CONFIG_SERIAL_8250 is not set
1624 +
1625 +#
1626 +# Non-8250 serial port support
1627 +#
1628 +CONFIG_SERIAL_ATMEL=y
1629 +CONFIG_SERIAL_ATMEL_CONSOLE=y
1630 +# CONFIG_SERIAL_ATMEL_TTYAT is not set
1631 +CONFIG_SERIAL_CORE=y
1632 +CONFIG_SERIAL_CORE_CONSOLE=y
1633 +CONFIG_UNIX98_PTYS=y
1634 +CONFIG_LEGACY_PTYS=y
1635 +CONFIG_LEGACY_PTY_COUNT=256
1636 +
1637 +#
1638 +# IPMI
1639 +#
1640 +# CONFIG_IPMI_HANDLER is not set
1641 +
1642 +#
1643 +# Watchdog Cards
1644 +#
1645 +CONFIG_WATCHDOG=y
1646 +CONFIG_WATCHDOG_NOWAYOUT=y
1647 +
1648 +#
1649 +# Watchdog Device Drivers
1650 +#
1651 +# CONFIG_SOFT_WATCHDOG is not set
1652 +
1653 +#
1654 +# USB-based Watchdog Cards
1655 +#
1656 +# CONFIG_USBPCWATCHDOG is not set
1657 +CONFIG_HW_RANDOM=y
1658 +# CONFIG_NVRAM is not set
1659 +# CONFIG_DTLK is not set
1660 +# CONFIG_R3964 is not set
1661 +
1662 +#
1663 +# Ftape, the floppy tape device driver
1664 +#
1665 +# CONFIG_RAW_DRIVER is not set
1666 +
1667 +#
1668 +# TPM devices
1669 +#
1670 +# CONFIG_TCG_TPM is not set
1671 +
1672 +#
1673 +# I2C support
1674 +#
1675 +CONFIG_I2C=y
1676 +CONFIG_I2C_CHARDEV=y
1677 +
1678 +#
1679 +# I2C Algorithms
1680 +#
1681 +# CONFIG_I2C_ALGOBIT is not set
1682 +# CONFIG_I2C_ALGOPCF is not set
1683 +# CONFIG_I2C_ALGOPCA is not set
1684 +
1685 +#
1686 +# I2C Hardware Bus support
1687 +#
1688 +CONFIG_I2C_AT91=y
1689 +# CONFIG_I2C_OCORES is not set
1690 +# CONFIG_I2C_PARPORT_LIGHT is not set
1691 +# CONFIG_I2C_STUB is not set
1692 +# CONFIG_I2C_PCA is not set
1693 +# CONFIG_I2C_PCA_ISA is not set
1694 +
1695 +#
1696 +# Miscellaneous I2C Chip support
1697 +#
1698 +# CONFIG_SENSORS_DS1337 is not set
1699 +# CONFIG_SENSORS_DS1374 is not set
1700 +# CONFIG_SENSORS_EEPROM is not set
1701 +# CONFIG_SENSORS_PCF8574 is not set
1702 +# CONFIG_SENSORS_PCA9539 is not set
1703 +# CONFIG_SENSORS_PCF8591 is not set
1704 +# CONFIG_SENSORS_MAX6875 is not set
1705 +# CONFIG_I2C_DEBUG_CORE is not set
1706 +# CONFIG_I2C_DEBUG_ALGO is not set
1707 +# CONFIG_I2C_DEBUG_BUS is not set
1708 +# CONFIG_I2C_DEBUG_CHIP is not set
1709 +
1710 +#
1711 +# SPI support
1712 +#
1713 +# CONFIG_SPI is not set
1714 +# CONFIG_SPI_MASTER is not set
1715 +
1716 +#
1717 +# Dallas's 1-wire bus
1718 +#
1719 +# CONFIG_W1 is not set
1720 +
1721 +#
1722 +# Hardware Monitoring support
1723 +#
1724 +# CONFIG_HWMON is not set
1725 +# CONFIG_HWMON_VID is not set
1726 +
1727 +#
1728 +# Misc devices
1729 +#
1730 +# CONFIG_TIFM_CORE is not set
1731 +
1732 +#
1733 +# LED devices
1734 +#
1735 +# CONFIG_NEW_LEDS is not set
1736 +
1737 +#
1738 +# LED drivers
1739 +#
1740 +
1741 +#
1742 +# LED Triggers
1743 +#
1744 +
1745 +#
1746 +# Multimedia devices
1747 +#
1748 +# CONFIG_VIDEO_DEV is not set
1749 +
1750 +#
1751 +# Digital Video Broadcasting Devices
1752 +#
1753 +# CONFIG_DVB is not set
1754 +# CONFIG_USB_DABUSB is not set
1755 +
1756 +#
1757 +# Graphics support
1758 +#
1759 +# CONFIG_FIRMWARE_EDID is not set
1760 +# CONFIG_FB is not set
1761 +
1762 +#
1763 +# Console display driver support
1764 +#
1765 +# CONFIG_VGA_CONSOLE is not set
1766 +CONFIG_DUMMY_CONSOLE=y
1767 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1768 +
1769 +#
1770 +# Sound
1771 +#
1772 +# CONFIG_SOUND is not set
1773 +
1774 +#
1775 +# USB support
1776 +#
1777 +CONFIG_USB_ARCH_HAS_HCD=y
1778 +CONFIG_USB_ARCH_HAS_OHCI=y
1779 +# CONFIG_USB_ARCH_HAS_EHCI is not set
1780 +CONFIG_USB=y
1781 +# CONFIG_USB_DEBUG is not set
1782 +
1783 +#
1784 +# Miscellaneous USB options
1785 +#
1786 +CONFIG_USB_DEVICEFS=y
1787 +# CONFIG_USB_BANDWIDTH is not set
1788 +# CONFIG_USB_DYNAMIC_MINORS is not set
1789 +# CONFIG_USB_OTG is not set
1790 +
1791 +#
1792 +# USB Host Controller Drivers
1793 +#
1794 +# CONFIG_USB_ISP116X_HCD is not set
1795 +CONFIG_USB_OHCI_HCD=y
1796 +# CONFIG_USB_OHCI_BIG_ENDIAN is not set
1797 +CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1798 +# CONFIG_USB_SL811_HCD is not set
1799 +
1800 +#
1801 +# USB Device Class drivers
1802 +#
1803 +# CONFIG_USB_ACM is not set
1804 +# CONFIG_USB_PRINTER is not set
1805 +
1806 +#
1807 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1808 +#
1809 +
1810 +#
1811 +# may also be needed; see USB_STORAGE Help for more information
1812 +#
1813 +CONFIG_USB_STORAGE=y
1814 +CONFIG_USB_STORAGE_DEBUG=y
1815 +# CONFIG_USB_STORAGE_DATAFAB is not set
1816 +# CONFIG_USB_STORAGE_FREECOM is not set
1817 +# CONFIG_USB_STORAGE_DPCM is not set
1818 +# CONFIG_USB_STORAGE_USBAT is not set
1819 +# CONFIG_USB_STORAGE_SDDR09 is not set
1820 +# CONFIG_USB_STORAGE_SDDR55 is not set
1821 +# CONFIG_USB_STORAGE_JUMPSHOT is not set
1822 +# CONFIG_USB_STORAGE_ALAUDA is not set
1823 +# CONFIG_USB_STORAGE_KARMA is not set
1824 +# CONFIG_USB_LIBUSUAL is not set
1825 +
1826 +#
1827 +# USB Input Devices
1828 +#
1829 +# CONFIG_USB_HID is not set
1830 +
1831 +#
1832 +# USB HID Boot Protocol drivers
1833 +#
1834 +# CONFIG_USB_KBD is not set
1835 +# CONFIG_USB_MOUSE is not set
1836 +# CONFIG_USB_AIPTEK is not set
1837 +# CONFIG_USB_WACOM is not set
1838 +# CONFIG_USB_ACECAD is not set
1839 +# CONFIG_USB_KBTAB is not set
1840 +# CONFIG_USB_POWERMATE is not set
1841 +# CONFIG_USB_TOUCHSCREEN is not set
1842 +# CONFIG_USB_YEALINK is not set
1843 +# CONFIG_USB_XPAD is not set
1844 +# CONFIG_USB_ATI_REMOTE is not set
1845 +# CONFIG_USB_ATI_REMOTE2 is not set
1846 +# CONFIG_USB_KEYSPAN_REMOTE is not set
1847 +# CONFIG_USB_APPLETOUCH is not set
1848 +
1849 +#
1850 +# USB Imaging devices
1851 +#
1852 +# CONFIG_USB_MDC800 is not set
1853 +# CONFIG_USB_MICROTEK is not set
1854 +
1855 +#
1856 +# USB Network Adapters
1857 +#
1858 +# CONFIG_USB_CATC is not set
1859 +# CONFIG_USB_KAWETH is not set
1860 +# CONFIG_USB_PEGASUS is not set
1861 +# CONFIG_USB_RTL8150 is not set
1862 +# CONFIG_USB_USBNET_MII is not set
1863 +# CONFIG_USB_USBNET is not set
1864 +CONFIG_USB_MON=y
1865 +
1866 +#
1867 +# USB port drivers
1868 +#
1869 +
1870 +#
1871 +# USB Serial Converter support
1872 +#
1873 +# CONFIG_USB_SERIAL is not set
1874 +
1875 +#
1876 +# USB Miscellaneous drivers
1877 +#
1878 +# CONFIG_USB_EMI62 is not set
1879 +# CONFIG_USB_EMI26 is not set
1880 +# CONFIG_USB_ADUTUX is not set
1881 +# CONFIG_USB_AUERSWALD is not set
1882 +# CONFIG_USB_RIO500 is not set
1883 +# CONFIG_USB_LEGOTOWER is not set
1884 +# CONFIG_USB_LCD is not set
1885 +# CONFIG_USB_LED is not set
1886 +# CONFIG_USB_CYPRESS_CY7C63 is not set
1887 +# CONFIG_USB_CYTHERM is not set
1888 +# CONFIG_USB_PHIDGET is not set
1889 +# CONFIG_USB_IDMOUSE is not set
1890 +# CONFIG_USB_FTDI_ELAN is not set
1891 +# CONFIG_USB_APPLEDISPLAY is not set
1892 +# CONFIG_USB_LD is not set
1893 +# CONFIG_USB_TRANCEVIBRATOR is not set
1894 +# CONFIG_USB_TEST is not set
1895 +
1896 +#
1897 +# USB DSL modem support
1898 +#
1899 +
1900 +#
1901 +# USB Gadget Support
1902 +#
1903 +CONFIG_USB_GADGET=y
1904 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
1905 +CONFIG_USB_GADGET_SELECTED=y
1906 +# CONFIG_USB_GADGET_NET2280 is not set
1907 +# CONFIG_USB_GADGET_PXA2XX is not set
1908 +# CONFIG_USB_GADGET_GOKU is not set
1909 +# CONFIG_USB_GADGET_LH7A40X is not set
1910 +# CONFIG_USB_GADGET_OMAP is not set
1911 +CONFIG_USB_GADGET_AT91=y
1912 +CONFIG_USB_AT91=y
1913 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
1914 +# CONFIG_USB_GADGET_DUALSPEED is not set
1915 +CONFIG_USB_ZERO=m
1916 +# CONFIG_USB_ETH is not set
1917 +CONFIG_USB_GADGETFS=m
1918 +CONFIG_USB_FILE_STORAGE=m
1919 +# CONFIG_USB_FILE_STORAGE_TEST is not set
1920 +CONFIG_USB_G_SERIAL=m
1921 +# CONFIG_USB_MIDI_GADGET is not set
1922 +
1923 +#
1924 +# MMC/SD Card support
1925 +#
1926 +CONFIG_MMC=y
1927 +# CONFIG_MMC_DEBUG is not set
1928 +CONFIG_MMC_BLOCK=y
1929 +CONFIG_MMC_AT91=m
1930 +# CONFIG_MMC_TIFM_SD is not set
1931 +
1932 +#
1933 +# Real Time Clock
1934 +#
1935 +CONFIG_RTC_LIB=y
1936 +# CONFIG_RTC_CLASS is not set
1937 +
1938 +#
1939 +# File systems
1940 +#
1941 +CONFIG_EXT2_FS=y
1942 +# CONFIG_EXT2_FS_XATTR is not set
1943 +# CONFIG_EXT2_FS_XIP is not set
1944 +# CONFIG_EXT3_FS is not set
1945 +# CONFIG_EXT4DEV_FS is not set
1946 +# CONFIG_REISERFS_FS is not set
1947 +# CONFIG_JFS_FS is not set
1948 +# CONFIG_FS_POSIX_ACL is not set
1949 +# CONFIG_XFS_FS is not set
1950 +# CONFIG_GFS2_FS is not set
1951 +# CONFIG_OCFS2_FS is not set
1952 +# CONFIG_MINIX_FS is not set
1953 +# CONFIG_ROMFS_FS is not set
1954 +CONFIG_INOTIFY=y
1955 +CONFIG_INOTIFY_USER=y
1956 +# CONFIG_QUOTA is not set
1957 +CONFIG_DNOTIFY=y
1958 +# CONFIG_AUTOFS_FS is not set
1959 +# CONFIG_AUTOFS4_FS is not set
1960 +# CONFIG_FUSE_FS is not set
1961 +
1962 +#
1963 +# CD-ROM/DVD Filesystems
1964 +#
1965 +# CONFIG_ISO9660_FS is not set
1966 +# CONFIG_UDF_FS is not set
1967 +
1968 +#
1969 +# DOS/FAT/NT Filesystems
1970 +#
1971 +CONFIG_FAT_FS=y
1972 +# CONFIG_MSDOS_FS is not set
1973 +CONFIG_VFAT_FS=y
1974 +CONFIG_FAT_DEFAULT_CODEPAGE=437
1975 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1976 +# CONFIG_NTFS_FS is not set
1977 +
1978 +#
1979 +# Pseudo filesystems
1980 +#
1981 +CONFIG_PROC_FS=y
1982 +CONFIG_PROC_SYSCTL=y
1983 +CONFIG_SYSFS=y
1984 +CONFIG_TMPFS=y
1985 +# CONFIG_TMPFS_POSIX_ACL is not set
1986 +# CONFIG_HUGETLB_PAGE is not set
1987 +CONFIG_RAMFS=y
1988 +# CONFIG_CONFIGFS_FS is not set
1989 +
1990 +#
1991 +# Miscellaneous filesystems
1992 +#
1993 +# CONFIG_ADFS_FS is not set
1994 +# CONFIG_AFFS_FS is not set
1995 +# CONFIG_HFS_FS is not set
1996 +# CONFIG_HFSPLUS_FS is not set
1997 +# CONFIG_BEFS_FS is not set
1998 +# CONFIG_BFS_FS is not set
1999 +# CONFIG_EFS_FS is not set
2000 +# CONFIG_JFFS_FS is not set
2001 +# CONFIG_JFFS2_FS is not set
2002 +CONFIG_CRAMFS=y
2003 +# CONFIG_VXFS_FS is not set
2004 +# CONFIG_HPFS_FS is not set
2005 +# CONFIG_QNX4FS_FS is not set
2006 +# CONFIG_SYSV_FS is not set
2007 +# CONFIG_UFS_FS is not set
2008 +
2009 +#
2010 +# Network File Systems
2011 +#
2012 +# CONFIG_NFS_FS is not set
2013 +# CONFIG_NFSD is not set
2014 +# CONFIG_SMB_FS is not set
2015 +# CONFIG_CIFS is not set
2016 +# CONFIG_NCP_FS is not set
2017 +# CONFIG_CODA_FS is not set
2018 +# CONFIG_AFS_FS is not set
2019 +# CONFIG_9P_FS is not set
2020 +
2021 +#
2022 +# Partition Types
2023 +#
2024 +# CONFIG_PARTITION_ADVANCED is not set
2025 +CONFIG_MSDOS_PARTITION=y
2026 +
2027 +#
2028 +# Native Language Support
2029 +#
2030 +CONFIG_NLS=y
2031 +CONFIG_NLS_DEFAULT="iso8859-1"
2032 +CONFIG_NLS_CODEPAGE_437=y
2033 +# CONFIG_NLS_CODEPAGE_737 is not set
2034 +# CONFIG_NLS_CODEPAGE_775 is not set
2035 +CONFIG_NLS_CODEPAGE_850=y
2036 +# CONFIG_NLS_CODEPAGE_852 is not set
2037 +# CONFIG_NLS_CODEPAGE_855 is not set
2038 +# CONFIG_NLS_CODEPAGE_857 is not set
2039 +# CONFIG_NLS_CODEPAGE_860 is not set
2040 +# CONFIG_NLS_CODEPAGE_861 is not set
2041 +# CONFIG_NLS_CODEPAGE_862 is not set
2042 +# CONFIG_NLS_CODEPAGE_863 is not set
2043 +# CONFIG_NLS_CODEPAGE_864 is not set
2044 +# CONFIG_NLS_CODEPAGE_865 is not set
2045 +# CONFIG_NLS_CODEPAGE_866 is not set
2046 +# CONFIG_NLS_CODEPAGE_869 is not set
2047 +# CONFIG_NLS_CODEPAGE_936 is not set
2048 +# CONFIG_NLS_CODEPAGE_950 is not set
2049 +# CONFIG_NLS_CODEPAGE_932 is not set
2050 +# CONFIG_NLS_CODEPAGE_949 is not set
2051 +# CONFIG_NLS_CODEPAGE_874 is not set
2052 +# CONFIG_NLS_ISO8859_8 is not set
2053 +# CONFIG_NLS_CODEPAGE_1250 is not set
2054 +# CONFIG_NLS_CODEPAGE_1251 is not set
2055 +# CONFIG_NLS_ASCII is not set
2056 +CONFIG_NLS_ISO8859_1=y
2057 +# CONFIG_NLS_ISO8859_2 is not set
2058 +# CONFIG_NLS_ISO8859_3 is not set
2059 +# CONFIG_NLS_ISO8859_4 is not set
2060 +# CONFIG_NLS_ISO8859_5 is not set
2061 +# CONFIG_NLS_ISO8859_6 is not set
2062 +# CONFIG_NLS_ISO8859_7 is not set
2063 +# CONFIG_NLS_ISO8859_9 is not set
2064 +# CONFIG_NLS_ISO8859_13 is not set
2065 +# CONFIG_NLS_ISO8859_14 is not set
2066 +# CONFIG_NLS_ISO8859_15 is not set
2067 +# CONFIG_NLS_KOI8_R is not set
2068 +# CONFIG_NLS_KOI8_U is not set
2069 +# CONFIG_NLS_UTF8 is not set
2070 +
2071 +#
2072 +# Profiling support
2073 +#
2074 +# CONFIG_PROFILING is not set
2075 +
2076 +#
2077 +# Kernel hacking
2078 +#
2079 +# CONFIG_PRINTK_TIME is not set
2080 +CONFIG_ENABLE_MUST_CHECK=y
2081 +# CONFIG_MAGIC_SYSRQ is not set
2082 +# CONFIG_UNUSED_SYMBOLS is not set
2083 +CONFIG_DEBUG_KERNEL=y
2084 +CONFIG_LOG_BUF_SHIFT=14
2085 +CONFIG_DETECT_SOFTLOCKUP=y
2086 +# CONFIG_SCHEDSTATS is not set
2087 +# CONFIG_DEBUG_SLAB is not set
2088 +# CONFIG_DEBUG_RT_MUTEXES is not set
2089 +# CONFIG_RT_MUTEX_TESTER is not set
2090 +# CONFIG_DEBUG_SPINLOCK is not set
2091 +# CONFIG_DEBUG_MUTEXES is not set
2092 +# CONFIG_DEBUG_RWSEMS is not set
2093 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
2094 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
2095 +# CONFIG_DEBUG_KOBJECT is not set
2096 +CONFIG_DEBUG_BUGVERBOSE=y
2097 +# CONFIG_DEBUG_INFO is not set
2098 +# CONFIG_DEBUG_FS is not set
2099 +# CONFIG_DEBUG_VM is not set
2100 +# CONFIG_DEBUG_LIST is not set
2101 +CONFIG_FRAME_POINTER=y
2102 +CONFIG_FORCED_INLINING=y
2103 +# CONFIG_HEADERS_CHECK is not set
2104 +# CONFIG_RCU_TORTURE_TEST is not set
2105 +CONFIG_DEBUG_USER=y
2106 +# CONFIG_DEBUG_WAITQ is not set
2107 +# CONFIG_DEBUG_ERRORS is not set
2108 +CONFIG_DEBUG_LL=y
2109 +# CONFIG_DEBUG_ICEDCC is not set
2110 +
2111 +#
2112 +# Security options
2113 +#
2114 +# CONFIG_KEYS is not set
2115 +# CONFIG_SECURITY is not set
2116 +
2117 +#
2118 +# Cryptographic options
2119 +#
2120 +# CONFIG_CRYPTO is not set
2121 +
2122 +#
2123 +# Library routines
2124 +#
2125 +# CONFIG_CRC_CCITT is not set
2126 +# CONFIG_CRC16 is not set
2127 +CONFIG_CRC32=y
2128 +# CONFIG_LIBCRC32C is not set
2129 +CONFIG_ZLIB_INFLATE=y
2130 +CONFIG_PLIST=y
2131 diff -urN -x CVS linux-2.6.19-final/arch/arm/configs/carmeva_defconfig linux-2.6.19/arch/arm/configs/carmeva_defconfig
2132 --- linux-2.6.19-final/arch/arm/configs/carmeva_defconfig       Mon Dec  4 16:39:29 2006
2133 +++ linux-2.6.19/arch/arm/configs/carmeva_defconfig     Thu Oct 12 17:07:38 2006
2134 @@ -474,7 +474,7 @@
2135  # CONFIG_WATCHDOG is not set
2136  # CONFIG_NVRAM is not set
2137  # CONFIG_RTC is not set
2138 -# CONFIG_AT91_RTC is not set
2139 +# CONFIG_AT91RM9200_RTC is not set
2140  # CONFIG_DTLK is not set
2141  # CONFIG_R3964 is not set
2142
2143 diff -urN -x CVS linux-2.6.19-final/arch/arm/configs/csb637_defconfig linux-2.6.19/arch/arm/configs/csb637_defconfig
2144 --- linux-2.6.19-final/arch/arm/configs/csb637_defconfig        Mon Dec  4 16:39:29 2006
2145 +++ linux-2.6.19/arch/arm/configs/csb637_defconfig      Thu Oct 12 17:07:38 2006
2146 @@ -623,7 +623,7 @@
2147  # CONFIG_USBPCWATCHDOG is not set
2148  # CONFIG_NVRAM is not set
2149  CONFIG_RTC=y
2150 -# CONFIG_AT91_RTC is not set
2151 +# CONFIG_AT91RM9200_RTC is not set
2152  # CONFIG_DTLK is not set
2153  # CONFIG_R3964 is not set
2154
2155 diff -urN -x CVS linux-2.6.19-final/arch/arm/configs/kb9202_defconfig linux-2.6.19/arch/arm/configs/kb9202_defconfig
2156 --- linux-2.6.19-final/arch/arm/configs/kb9202_defconfig        Mon Dec  4 16:39:29 2006
2157 +++ linux-2.6.19/arch/arm/configs/kb9202_defconfig      Thu Oct 12 17:07:38 2006
2158 @@ -437,7 +437,7 @@
2159  # CONFIG_WATCHDOG is not set
2160  # CONFIG_NVRAM is not set
2161  # CONFIG_RTC is not set
2162 -# CONFIG_AT91_RTC is not set
2163 +# CONFIG_AT91RM9200_RTC is not set
2164  # CONFIG_DTLK is not set
2165  # CONFIG_R3964 is not set
2166
2167 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/Kconfig linux-2.6.19/arch/arm/mach-at91rm9200/Kconfig
2168 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/Kconfig Mon Dec  4 16:32:44 2006
2169 +++ linux-2.6.19/arch/arm/mach-at91rm9200/Kconfig       Wed Nov 22 09:24:11 2006
2170 @@ -2,7 +2,8 @@
2171
2172  menu "Atmel AT91 System-on-Chip"
2173
2174 -comment "Atmel AT91 Processors"
2175 +choice
2176 +       prompt "Atmel AT91 Processor"
2177
2178  config ARCH_AT91RM9200
2179         bool "AT91RM9200"
2180 @@ -13,6 +14,8 @@
2181  config ARCH_AT91SAM9261
2182         bool "AT91SAM9261"
2183
2184 +endchoice
2185 +
2186  # ----------------------------------------------------------
2187
2188  if ARCH_AT91RM9200
2189 @@ -33,7 +36,6 @@
2190           Select this if you are using Atmel's AT91RM9200-DK Development board.
2191           (Discontinued)
2192
2193 -
2194  config MACH_AT91RM9200EK
2195         bool "Atmel AT91RM9200-EK Evaluation Kit"
2196         depends on ARCH_AT91RM9200
2197 @@ -90,6 +92,13 @@
2198
2199  comment "AT91SAM9260 Board Type"
2200
2201 +config MACH_AT91SAM9260EK
2202 +       bool "Atmel AT91SAM9260-EK Evaluation Kit"
2203 +       depends on ARCH_AT91SAM9260
2204 +       help
2205 +         Select this if you are using Atmel's AT91SAM9260-EK Evaluation Kit.
2206 +         <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
2207 +
2208  endif
2209
2210  # ----------------------------------------------------------
2211 @@ -98,8 +107,31 @@
2212
2213  comment "AT91SAM9261 Board Type"
2214
2215 +config MACH_AT91SAM9261EK
2216 +       bool "Atmel AT91SAM9261-EK Evaluation Kit"
2217 +       depends on ARCH_AT91SAM9261
2218 +       help
2219 +         Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
2220 +         <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
2221 +
2222  endif
2223
2224 +# ----------------------------------------------------------
2225 +
2226 +comment "AT91 Board Options"
2227 +
2228 +config MTD_AT91_DATAFLASH_CARD
2229 +       bool "Enable DataFlash Card support"
2230 +       depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK)
2231 +       help
2232 +         Enable support for the DataFlash card.
2233 +
2234 +config MTD_NAND_AT91_BUSWIDTH_16
2235 +       bool "Enable 16-bit data bus interface to NAND flash"
2236 +       depends on (MACH_AT91SAM9261EK || MACH_AT91SAM9260EK)
2237 +       help
2238 +         On AT91SAM926x boards both types of NAND flash can be present
2239 +         (8 and 16 bit data bus width).
2240
2241  # ----------------------------------------------------------
2242
2243 @@ -111,6 +143,13 @@
2244           Select this if you need to program one or more of the PCK0..PCK3
2245           programmable clock outputs.
2246
2247 +config AT91_SLOW_CLOCK
2248 +       bool "Suspend-to-RAM uses slow clock mode (EXPERIMENTAL)"
2249 +       depends on PM && EXPERIMENTAL
2250 +       help
2251 +         Select this if you wish to put the CPU into slow clock mode
2252 +         while in the "Suspend to RAM" state, to save more power.
2253 +
2254  endmenu
2255
2256  endif
2257 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/Makefile linux-2.6.19/arch/arm/mach-at91rm9200/Makefile
2258 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/Makefile        Mon Dec  4 16:32:44 2006
2259 +++ linux-2.6.19/arch/arm/mach-at91rm9200/Makefile      Thu Nov 16 11:45:54 2006
2260 @@ -2,19 +2,20 @@
2261  # Makefile for the linux kernel.
2262  #
2263
2264 -obj-y          := clock.o irq.o gpio.o devices.o
2265 +obj-y          := clock.o irq.o gpio.o
2266  obj-m          :=
2267  obj-n          :=
2268  obj-           :=
2269
2270  obj-$(CONFIG_PM)               += pm.o
2271 +obj-$(CONFIG_AT91_SLOW_CLOCK)  += pm_slowclock.o
2272
2273  # CPU-specific support
2274 -obj-$(CONFIG_ARCH_AT91RM9200)  += at91rm9200.o at91rm9200_time.o
2275 -obj-$(CONFIG_ARCH_AT91SAM9260) +=
2276 -obj-$(CONFIG_ARCH_AT91SAM9261) +=
2277 +obj-$(CONFIG_ARCH_AT91RM9200)  += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
2278 +obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
2279 +obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
2280
2281 -# AT91RM9200 Board-specific support
2282 +# AT91RM9200 board-specific support
2283  obj-$(CONFIG_MACH_ONEARM)      += board-1arm.o
2284  obj-$(CONFIG_ARCH_AT91RM9200DK)        += board-dk.o
2285  obj-$(CONFIG_MACH_AT91RM9200EK)        += board-ek.o
2286 @@ -26,8 +27,10 @@
2287  obj-$(CONFIG_MACH_KAFA)                += board-kafa.o
2288
2289  # AT91SAM9260 board-specific support
2290 +obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
2291
2292  # AT91SAM9261 board-specific support
2293 +obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
2294
2295  # LEDs support
2296  led-$(CONFIG_ARCH_AT91RM9200DK)        += leds.o
2297 @@ -39,7 +42,7 @@
2298  obj-$(CONFIG_LEDS) += $(led-y)
2299
2300  # VGA support
2301 -#obj-$(CONFIG_FB_S1D13XXX)     += ics1523.o
2302 +obj-$(CONFIG_FB_S1D13XXX)      += ics1523.o
2303
2304
2305  ifeq ($(CONFIG_PM_DEBUG),y)
2306 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91rm9200.c linux-2.6.19/arch/arm/mach-at91rm9200/at91rm9200.c
2307 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91rm9200.c    Mon Dec  4 16:39:29 2006
2308 +++ linux-2.6.19/arch/arm/mach-at91rm9200/at91rm9200.c  Fri Nov  3 19:22:15 2006
2309 @@ -14,8 +14,10 @@
2310
2311  #include <asm/mach/arch.h>
2312  #include <asm/mach/map.h>
2313 +#include <asm/arch/at91rm9200.h>
2314 +#include <asm/arch/at91_pmc.h>
2315 +#include <asm/arch/at91_st.h>
2316
2317 -#include <asm/hardware.h>
2318  #include "generic.h"
2319  #include "clock.h"
2320
2321 @@ -26,32 +28,12 @@
2322                 .length         = SZ_4K,
2323                 .type           = MT_DEVICE,
2324         }, {
2325 -               .virtual        = AT91_VA_BASE_SPI,
2326 -               .pfn            = __phys_to_pfn(AT91RM9200_BASE_SPI),
2327 -               .length         = SZ_16K,
2328 -               .type           = MT_DEVICE,
2329 -       }, {
2330                 .virtual        = AT91_VA_BASE_EMAC,
2331                 .pfn            = __phys_to_pfn(AT91RM9200_BASE_EMAC),
2332                 .length         = SZ_16K,
2333                 .type           = MT_DEVICE,
2334         }, {
2335 -               .virtual        = AT91_VA_BASE_TWI,
2336 -               .pfn            = __phys_to_pfn(AT91RM9200_BASE_TWI),
2337 -               .length         = SZ_16K,
2338 -               .type           = MT_DEVICE,
2339 -       }, {
2340 -               .virtual        = AT91_VA_BASE_MCI,
2341 -               .pfn            = __phys_to_pfn(AT91RM9200_BASE_MCI),
2342 -               .length         = SZ_16K,
2343 -               .type           = MT_DEVICE,
2344 -       }, {
2345 -               .virtual        = AT91_VA_BASE_UDP,
2346 -               .pfn            = __phys_to_pfn(AT91RM9200_BASE_UDP),
2347 -               .length         = SZ_16K,
2348 -               .type           = MT_DEVICE,
2349 -       }, {
2350 -               .virtual        = AT91_SRAM_VIRT_BASE,
2351 +               .virtual        = AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE,
2352                 .pfn            = __phys_to_pfn(AT91RM9200_SRAM_BASE),
2353                 .length         = AT91RM9200_SRAM_SIZE,
2354                 .type           = MT_DEVICE,
2355 @@ -222,6 +204,16 @@
2356         }
2357  };
2358
2359 +static void at91rm9200_reset(void)
2360 +{
2361 +       /*
2362 +        * Perform a hardware reset with the use of the Watchdog timer.
2363 +        */
2364 +       at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
2365 +       at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
2366 +}
2367 +
2368 +
2369  /* --------------------------------------------------------------------
2370   *  AT91RM9200 processor initialization
2371   * -------------------------------------------------------------------- */
2372 @@ -230,6 +222,12 @@
2373         /* Map peripherals */
2374         iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
2375
2376 +       at91_arch_reset = at91rm9200_reset;
2377 +       at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
2378 +                       | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
2379 +                       | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
2380 +                       | (1 << AT91RM9200_ID_IRQ6);
2381 +
2382         /* Init clock subsystem */
2383         at91_clock_init(main_clock);
2384
2385 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91rm9200_devices.c linux-2.6.19/arch/arm/mach-at91rm9200/at91rm9200_devices.c
2386 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91rm9200_devices.c    Thu Jan  1 02:00:00 1970
2387 +++ linux-2.6.19/arch/arm/mach-at91rm9200/at91rm9200_devices.c  Fri Dec  1 16:10:47 2006
2388 @@ -0,0 +1,901 @@
2389 +/*
2390 + * arch/arm/mach-at91rm9200/at91rm9200_devices.c
2391 + *
2392 + *  Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
2393 + *  Copyright (C) 2005 David Brownell
2394 + *
2395 + * This program is free software; you can redistribute it and/or modify
2396 + * it under the terms of the GNU General Public License as published by
2397 + * the Free Software Foundation; either version 2 of the License, or
2398 + * (at your option) any later version.
2399 + *
2400 + */
2401 +#include <asm/mach/arch.h>
2402 +#include <asm/mach/map.h>
2403 +
2404 +#include <linux/platform_device.h>
2405 +
2406 +#include <asm/arch/board.h>
2407 +#include <asm/arch/gpio.h>
2408 +#include <asm/arch/at91rm9200.h>
2409 +#include <asm/arch/at91rm9200_mc.h>
2410 +
2411 +#include "generic.h"
2412 +
2413 +#define SZ_512 0x00000200
2414 +#define SZ_256 0x00000100
2415 +#define SZ_16  0x00000010
2416 +
2417 +/* --------------------------------------------------------------------
2418 + *  USB Host
2419 + * -------------------------------------------------------------------- */
2420 +
2421 +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2422 +static u64 ohci_dmamask = 0xffffffffUL;
2423 +static struct at91_usbh_data usbh_data;
2424 +
2425 +static struct resource usbh_resources[] = {
2426 +       [0] = {
2427 +               .start  = AT91RM9200_UHP_BASE,
2428 +               .end    = AT91RM9200_UHP_BASE + SZ_1M - 1,
2429 +               .flags  = IORESOURCE_MEM,
2430 +       },
2431 +       [1] = {
2432 +               .start  = AT91RM9200_ID_UHP,
2433 +               .end    = AT91RM9200_ID_UHP,
2434 +               .flags  = IORESOURCE_IRQ,
2435 +       },
2436 +};
2437 +
2438 +static struct platform_device at91rm9200_usbh_device = {
2439 +       .name           = "at91_ohci",
2440 +       .id             = -1,
2441 +       .dev            = {
2442 +                               .dma_mask               = &ohci_dmamask,
2443 +                               .coherent_dma_mask      = 0xffffffff,
2444 +                               .platform_data          = &usbh_data,
2445 +       },
2446 +       .resource       = usbh_resources,
2447 +       .num_resources  = ARRAY_SIZE(usbh_resources),
2448 +};
2449 +
2450 +void __init at91_add_device_usbh(struct at91_usbh_data *data)
2451 +{
2452 +       if (!data)
2453 +               return;
2454 +
2455 +       usbh_data = *data;
2456 +       platform_device_register(&at91rm9200_usbh_device);
2457 +}
2458 +#else
2459 +void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
2460 +#endif
2461 +
2462 +
2463 +/* --------------------------------------------------------------------
2464 + *  USB Device (Gadget)
2465 + * -------------------------------------------------------------------- */
2466 +
2467 +#ifdef CONFIG_USB_GADGET_AT91
2468 +static struct at91_udc_data udc_data;
2469 +
2470 +static struct resource udc_resources[] = {
2471 +       [0] = {
2472 +               .start  = AT91RM9200_BASE_UDP,
2473 +               .end    = AT91RM9200_BASE_UDP + SZ_16K - 1,
2474 +               .flags  = IORESOURCE_MEM,
2475 +       },
2476 +       [1] = {
2477 +               .start  = AT91RM9200_ID_UDP,
2478 +               .end    = AT91RM9200_ID_UDP,
2479 +               .flags  = IORESOURCE_IRQ,
2480 +       },
2481 +};
2482 +
2483 +static struct platform_device at91rm9200_udc_device = {
2484 +       .name           = "at91_udc",
2485 +       .id             = -1,
2486 +       .dev            = {
2487 +                               .platform_data          = &udc_data,
2488 +       },
2489 +       .resource       = udc_resources,
2490 +       .num_resources  = ARRAY_SIZE(udc_resources),
2491 +};
2492 +
2493 +void __init at91_add_device_udc(struct at91_udc_data *data)
2494 +{
2495 +       if (!data)
2496 +               return;
2497 +
2498 +       if (data->vbus_pin) {
2499 +               at91_set_gpio_input(data->vbus_pin, 0);
2500 +               at91_set_deglitch(data->vbus_pin, 1);
2501 +       }
2502 +       if (data->pullup_pin)
2503 +               at91_set_gpio_output(data->pullup_pin, 0);
2504 +
2505 +       udc_data = *data;
2506 +       platform_device_register(&at91rm9200_udc_device);
2507 +}
2508 +#else
2509 +void __init at91_add_device_udc(struct at91_udc_data *data) {}
2510 +#endif
2511 +
2512 +
2513 +/* --------------------------------------------------------------------
2514 + *  Ethernet
2515 + * -------------------------------------------------------------------- */
2516 +
2517 +#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
2518 +static u64 eth_dmamask = 0xffffffffUL;
2519 +static struct eth_platform_data eth_data;
2520 +
2521 +static struct resource eth_resources[] = {
2522 +       [0] = {
2523 +               .start  = AT91_VA_BASE_EMAC,
2524 +               .end    = AT91_VA_BASE_EMAC + SZ_16K - 1,
2525 +               .flags  = IORESOURCE_MEM,
2526 +       },
2527 +       [1] = {
2528 +               .start  = AT91RM9200_ID_EMAC,
2529 +               .end    = AT91RM9200_ID_EMAC,
2530 +               .flags  = IORESOURCE_IRQ,
2531 +       },
2532 +};
2533 +
2534 +static struct platform_device at91rm9200_eth_device = {
2535 +       .name           = "at91_ether",
2536 +       .id             = -1,
2537 +       .dev            = {
2538 +                               .dma_mask               = &eth_dmamask,
2539 +                               .coherent_dma_mask      = 0xffffffff,
2540 +                               .platform_data          = &eth_data,
2541 +       },
2542 +       .resource       = eth_resources,
2543 +       .num_resources  = ARRAY_SIZE(eth_resources),
2544 +};
2545 +
2546 +void __init at91_add_device_eth(struct eth_platform_data *data)
2547 +{
2548 +       if (!data)
2549 +               return;
2550 +
2551 +       if (data->phy_irq_pin) {
2552 +               at91_set_gpio_input(data->phy_irq_pin, 0);
2553 +               at91_set_deglitch(data->phy_irq_pin, 1);
2554 +       }
2555 +
2556 +       /* Pins used for MII and RMII */
2557 +       at91_set_A_periph(AT91_PIN_PA16, 0);    /* EMDIO */
2558 +       at91_set_A_periph(AT91_PIN_PA15, 0);    /* EMDC */
2559 +       at91_set_A_periph(AT91_PIN_PA14, 0);    /* ERXER */
2560 +       at91_set_A_periph(AT91_PIN_PA13, 0);    /* ERX1 */
2561 +       at91_set_A_periph(AT91_PIN_PA12, 0);    /* ERX0 */
2562 +       at91_set_A_periph(AT91_PIN_PA11, 0);    /* ECRS_ECRSDV */
2563 +       at91_set_A_periph(AT91_PIN_PA10, 0);    /* ETX1 */
2564 +       at91_set_A_periph(AT91_PIN_PA9, 0);     /* ETX0 */
2565 +       at91_set_A_periph(AT91_PIN_PA8, 0);     /* ETXEN */
2566 +       at91_set_A_periph(AT91_PIN_PA7, 0);     /* ETXCK_EREFCK */
2567 +
2568 +       if (!data->is_rmii) {
2569 +               at91_set_B_periph(AT91_PIN_PB19, 0);    /* ERXCK */
2570 +               at91_set_B_periph(AT91_PIN_PB18, 0);    /* ECOL */
2571 +               at91_set_B_periph(AT91_PIN_PB17, 0);    /* ERXDV */
2572 +               at91_set_B_periph(AT91_PIN_PB16, 0);    /* ERX3 */
2573 +               at91_set_B_periph(AT91_PIN_PB15, 0);    /* ERX2 */
2574 +               at91_set_B_periph(AT91_PIN_PB14, 0);    /* ETXER */
2575 +               at91_set_B_periph(AT91_PIN_PB13, 0);    /* ETX3 */
2576 +               at91_set_B_periph(AT91_PIN_PB12, 0);    /* ETX2 */
2577 +       }
2578 +
2579 +       eth_data = *data;
2580 +       platform_device_register(&at91rm9200_eth_device);
2581 +}
2582 +#else
2583 +void __init at91_add_device_eth(struct eth_platform_data *data) {}
2584 +#endif
2585 +
2586 +
2587 +/* --------------------------------------------------------------------
2588 + *  Compact Flash / PCMCIA
2589 + * -------------------------------------------------------------------- */
2590 +
2591 +#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
2592 +static struct at91_cf_data cf_data;
2593 +
2594 +#define CF_BASE                AT91_CHIPSELECT_4
2595 +
2596 +static struct resource cf_resources[] = {
2597 +       [0] = {
2598 +               .start  = CF_BASE,
2599 +               /* ties up CS4, CS5 and CS6 */
2600 +               .end    = CF_BASE + (0x30000000 - 1),
2601 +               .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
2602 +       },
2603 +};
2604 +
2605 +static struct platform_device at91rm9200_cf_device = {
2606 +       .name           = "at91_cf",
2607 +       .id             = -1,
2608 +       .dev            = {
2609 +                               .platform_data          = &cf_data,
2610 +       },
2611 +       .resource       = cf_resources,
2612 +       .num_resources  = ARRAY_SIZE(cf_resources),
2613 +};
2614 +
2615 +void __init at91_add_device_cf(struct at91_cf_data *data)
2616 +{
2617 +       unsigned int csa;
2618 +
2619 +       if (!data)
2620 +               return;
2621 +
2622 +       data->chipselect = 4;           /* can only use EBI ChipSelect 4 */
2623 +
2624 +       /* CF takes over CS4, CS5, CS6 */
2625 +       csa = at91_sys_read(AT91_EBI_CSA);
2626 +       at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
2627 +
2628 +       /*
2629 +        * Static memory controller timing adjustments.
2630 +        * REVISIT:  these timings are in terms of MCK cycles, so
2631 +        * when MCK changes (cpufreq etc) so must these values...
2632 +        */
2633 +       at91_sys_write(AT91_SMC_CSR(4),
2634 +                                 AT91_SMC_ACSS_STD
2635 +                               | AT91_SMC_DBW_16
2636 +                               | AT91_SMC_BAT
2637 +                               | AT91_SMC_WSEN
2638 +                               | AT91_SMC_NWS_(32)     /* wait states */
2639 +                               | AT91_SMC_RWSETUP_(6)  /* setup time */
2640 +                               | AT91_SMC_RWHOLD_(4)   /* hold time */
2641 +       );
2642 +
2643 +       /* input/irq */
2644 +       if (data->irq_pin) {
2645 +               at91_set_gpio_input(data->irq_pin, 1);
2646 +               at91_set_deglitch(data->irq_pin, 1);
2647 +       }
2648 +       at91_set_gpio_input(data->det_pin, 1);
2649 +       at91_set_deglitch(data->det_pin, 1);
2650 +
2651 +       /* outputs, initially off */
2652 +       if (data->vcc_pin)
2653 +               at91_set_gpio_output(data->vcc_pin, 0);
2654 +       at91_set_gpio_output(data->rst_pin, 0);
2655 +
2656 +       /* force poweron defaults for these pins ... */
2657 +       at91_set_A_periph(AT91_PIN_PC9, 0);     /* A25/CFRNW */
2658 +       at91_set_A_periph(AT91_PIN_PC10, 0);    /* NCS4/CFCS */
2659 +       at91_set_A_periph(AT91_PIN_PC11, 0);    /* NCS5/CFCE1 */
2660 +       at91_set_A_periph(AT91_PIN_PC12, 0);    /* NCS6/CFCE2 */
2661 +
2662 +       /* nWAIT is _not_ a default setting */
2663 +       at91_set_A_periph(AT91_PIN_PC6, 1);     /*  nWAIT */
2664 +
2665 +       cf_data = *data;
2666 +       platform_device_register(&at91rm9200_cf_device);
2667 +}
2668 +#else
2669 +void __init at91_add_device_cf(struct at91_cf_data *data) {}
2670 +#endif
2671 +
2672 +
2673 +/* --------------------------------------------------------------------
2674 + *  MMC / SD
2675 + * -------------------------------------------------------------------- */
2676 +
2677 +#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
2678 +static u64 mmc_dmamask = 0xffffffffUL;
2679 +static struct at91_mmc_data mmc_data;
2680 +
2681 +static struct resource mmc_resources[] = {
2682 +       [0] = {
2683 +               .start  = AT91RM9200_BASE_MCI,
2684 +               .end    = AT91RM9200_BASE_MCI + SZ_16K - 1,
2685 +               .flags  = IORESOURCE_MEM,
2686 +       },
2687 +       [1] = {
2688 +               .start  = AT91RM9200_ID_MCI,
2689 +               .end    = AT91RM9200_ID_MCI,
2690 +               .flags  = IORESOURCE_IRQ,
2691 +       },
2692 +};
2693 +
2694 +static struct platform_device at91rm9200_mmc_device = {
2695 +       .name           = "at91_mci",
2696 +       .id             = -1,
2697 +       .dev            = {
2698 +                               .dma_mask               = &mmc_dmamask,
2699 +                               .coherent_dma_mask      = 0xffffffff,
2700 +                               .platform_data          = &mmc_data,
2701 +       },
2702 +       .resource       = mmc_resources,
2703 +       .num_resources  = ARRAY_SIZE(mmc_resources),
2704 +};
2705 +
2706 +void __init at91_add_device_mmc(struct at91_mmc_data *data)
2707 +{
2708 +       if (!data)
2709 +               return;
2710 +
2711 +       /* input/irq */
2712 +       if (data->det_pin) {
2713 +               at91_set_gpio_input(data->det_pin, 1);
2714 +               at91_set_deglitch(data->det_pin, 1);
2715 +       }
2716 +       if (data->wp_pin)
2717 +               at91_set_gpio_input(data->wp_pin, 1);
2718 +       if (data->vcc_pin)
2719 +               at91_set_gpio_output(data->vcc_pin, 0);
2720 +
2721 +       /* CLK */
2722 +       at91_set_A_periph(AT91_PIN_PA27, 0);
2723 +
2724 +       if (data->slot_b) {
2725 +               /* CMD */
2726 +               at91_set_B_periph(AT91_PIN_PA8, 1);
2727 +
2728 +               /* DAT0, maybe DAT1..DAT3 */
2729 +               at91_set_B_periph(AT91_PIN_PA9, 1);
2730 +               if (data->wire4) {
2731 +                       at91_set_B_periph(AT91_PIN_PA10, 1);
2732 +                       at91_set_B_periph(AT91_PIN_PA11, 1);
2733 +                       at91_set_B_periph(AT91_PIN_PA12, 1);
2734 +               }
2735 +       } else {
2736 +               /* CMD */
2737 +               at91_set_A_periph(AT91_PIN_PA28, 1);
2738 +
2739 +               /* DAT0, maybe DAT1..DAT3 */
2740 +               at91_set_A_periph(AT91_PIN_PA29, 1);
2741 +               if (data->wire4) {
2742 +                       at91_set_B_periph(AT91_PIN_PB3, 1);
2743 +                       at91_set_B_periph(AT91_PIN_PB4, 1);
2744 +                       at91_set_B_periph(AT91_PIN_PB5, 1);
2745 +               }
2746 +       }
2747 +
2748 +       mmc_data = *data;
2749 +       platform_device_register(&at91rm9200_mmc_device);
2750 +}
2751 +#else
2752 +void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
2753 +#endif
2754 +
2755 +
2756 +/* --------------------------------------------------------------------
2757 + *  NAND / SmartMedia
2758 + * -------------------------------------------------------------------- */
2759 +
2760 +#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
2761 +static struct at91_nand_data nand_data;
2762 +
2763 +#define NAND_BASE      AT91_CHIPSELECT_3
2764 +
2765 +static struct resource nand_resources[] = {
2766 +       {
2767 +               .start  = NAND_BASE,
2768 +               .end    = NAND_BASE + SZ_8M - 1,
2769 +               .flags  = IORESOURCE_MEM,
2770 +       }
2771 +};
2772 +
2773 +static struct platform_device at91rm9200_nand_device = {
2774 +       .name           = "at91_nand",
2775 +       .id             = -1,
2776 +       .dev            = {
2777 +                               .platform_data  = &nand_data,
2778 +       },
2779 +       .resource       = nand_resources,
2780 +       .num_resources  = ARRAY_SIZE(nand_resources),
2781 +};
2782 +
2783 +void __init at91_add_device_nand(struct at91_nand_data *data)
2784 +{
2785 +       unsigned int csa;
2786 +
2787 +       if (!data)
2788 +               return;
2789 +
2790 +       /* enable the address range of CS3 */
2791 +       csa = at91_sys_read(AT91_EBI_CSA);
2792 +       at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
2793 +
2794 +       /* set the bus interface characteristics */
2795 +       at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
2796 +               | AT91_SMC_NWS_(5)
2797 +               | AT91_SMC_TDF_(1)
2798 +               | AT91_SMC_RWSETUP_(0)  /* tDS Data Set up Time 30 - ns */
2799 +               | AT91_SMC_RWHOLD_(1)   /* tDH Data Hold Time 20 - ns */
2800 +       );
2801 +
2802 +       /* enable pin */
2803 +       if (data->enable_pin)
2804 +               at91_set_gpio_output(data->enable_pin, 1);
2805 +
2806 +       /* ready/busy pin */
2807 +       if (data->rdy_pin)
2808 +               at91_set_gpio_input(data->rdy_pin, 1);
2809 +
2810 +       /* card detect pin */
2811 +       if (data->det_pin)
2812 +               at91_set_gpio_input(data->det_pin, 1);
2813 +
2814 +       at91_set_A_periph(AT91_PIN_PC1, 0);             /* SMOE */
2815 +       at91_set_A_periph(AT91_PIN_PC3, 0);             /* SMWE */
2816 +
2817 +       nand_data = *data;
2818 +       platform_device_register(&at91rm9200_nand_device);
2819 +}
2820 +#else
2821 +void __init at91_add_device_nand(struct at91_nand_data *data) {}
2822 +#endif
2823 +
2824 +
2825 +/* --------------------------------------------------------------------
2826 + *  TWI (i2c)
2827 + * -------------------------------------------------------------------- */
2828 +
2829 +#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
2830 +
2831 +static struct resource twi_resources[] = {
2832 +       [0] = {
2833 +               .start  = AT91RM9200_BASE_TWI,
2834 +               .end    = AT91RM9200_BASE_TWI + SZ_16K - 1,
2835 +               .flags  = IORESOURCE_MEM,
2836 +       },
2837 +       [1] = {
2838 +               .start  = AT91RM9200_ID_TWI,
2839 +               .end    = AT91RM9200_ID_TWI,
2840 +               .flags  = IORESOURCE_IRQ,
2841 +       },
2842 +};
2843 +
2844 +static struct platform_device at91rm9200_twi_device = {
2845 +       .name           = "at91_i2c",
2846 +       .id             = -1,
2847 +       .resource       = twi_resources,
2848 +       .num_resources  = ARRAY_SIZE(twi_resources),
2849 +};
2850 +
2851 +void __init at91_add_device_i2c(void)
2852 +{
2853 +       /* pins used for TWI interface */
2854 +       at91_set_A_periph(AT91_PIN_PA25, 0);            /* TWD */
2855 +       at91_set_multi_drive(AT91_PIN_PA25, 1);
2856 +
2857 +       at91_set_A_periph(AT91_PIN_PA26, 0);            /* TWCK */
2858 +       at91_set_multi_drive(AT91_PIN_PA26, 1);
2859 +
2860 +       platform_device_register(&at91rm9200_twi_device);
2861 +}
2862 +#else
2863 +void __init at91_add_device_i2c(void) {}
2864 +#endif
2865 +
2866 +
2867 +/* --------------------------------------------------------------------
2868 + *  SPI
2869 + * -------------------------------------------------------------------- */
2870 +
2871 +#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE)
2872 +static u64 spi_dmamask = 0xffffffffUL;
2873 +
2874 +static struct resource spi_resources[] = {
2875 +       [0] = {
2876 +               .start  = AT91RM9200_BASE_SPI,
2877 +               .end    = AT91RM9200_BASE_SPI + SZ_16K - 1,
2878 +               .flags  = IORESOURCE_MEM,
2879 +       },
2880 +       [1] = {
2881 +               .start  = AT91RM9200_ID_SPI,
2882 +               .end    = AT91RM9200_ID_SPI,
2883 +               .flags  = IORESOURCE_IRQ,
2884 +       },
2885 +};
2886 +
2887 +static struct platform_device at91rm9200_spi_device = {
2888 +       .name           = "at91_spi",
2889 +       .id             = 0,
2890 +       .dev            = {
2891 +                               .dma_mask               = &spi_dmamask,
2892 +                               .coherent_dma_mask      = 0xffffffff,
2893 +       },
2894 +       .resource       = spi_resources,
2895 +       .num_resources  = ARRAY_SIZE(spi_resources),
2896 +};
2897 +
2898 +static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
2899 +
2900 +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
2901 +{
2902 +       int i;
2903 +       unsigned long cs_pin;
2904 +
2905 +       at91_set_A_periph(AT91_PIN_PA0, 0);     /* MISO */
2906 +       at91_set_A_periph(AT91_PIN_PA1, 0);     /* MOSI */
2907 +       at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPCK */
2908 +
2909 +       /* Enable SPI chip-selects */
2910 +       for (i = 0; i < nr_devices; i++) {
2911 +               if (devices[i].controller_data)
2912 +                       cs_pin = (unsigned long) devices[i].controller_data;
2913 +               else
2914 +                       cs_pin = spi_standard_cs[devices[i].chip_select];
2915 +
2916 +#ifdef CONFIG_SPI_AT91_MANUAL_CS
2917 +               at91_set_gpio_output(cs_pin, 1);
2918 +#else
2919 +               at91_set_A_periph(cs_pin, 0);
2920 +#endif
2921 +
2922 +               /* pass chip-select pin to driver */
2923 +               devices[i].controller_data = (void *) cs_pin;
2924 +       }
2925 +
2926 +       spi_register_board_info(devices, nr_devices);
2927 +       at91_clock_associate("spi_clk", &at91rm9200_spi_device.dev, "spi");
2928 +       platform_device_register(&at91rm9200_spi_device);
2929 +}
2930 +#else
2931 +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
2932 +#endif
2933 +
2934 +
2935 +/* --------------------------------------------------------------------
2936 + *  RTC
2937 + * -------------------------------------------------------------------- */
2938 +
2939 +#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
2940 +static struct platform_device at91rm9200_rtc_device = {
2941 +       .name           = "at91_rtc",
2942 +       .id             = -1,
2943 +       .num_resources  = 0,
2944 +};
2945 +
2946 +static void __init at91_add_device_rtc(void)
2947 +{
2948 +       platform_device_register(&at91rm9200_rtc_device);
2949 +}
2950 +#else
2951 +static void __init at91_add_device_rtc(void) {}
2952 +#endif
2953 +
2954 +
2955 +/* --------------------------------------------------------------------
2956 + *  Watchdog
2957 + * -------------------------------------------------------------------- */
2958 +
2959 +#if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
2960 +static struct platform_device at91rm9200_wdt_device = {
2961 +       .name           = "at91_wdt",
2962 +       .id             = -1,
2963 +       .num_resources  = 0,
2964 +};
2965 +
2966 +static void __init at91_add_device_watchdog(void)
2967 +{
2968 +       platform_device_register(&at91rm9200_wdt_device);
2969 +}
2970 +#else
2971 +static void __init at91_add_device_watchdog(void) {}
2972 +#endif
2973 +
2974 +
2975 +/* --------------------------------------------------------------------
2976 + *  LEDs
2977 + * -------------------------------------------------------------------- */
2978 +
2979 +#if defined(CONFIG_LEDS)
2980 +u8 at91_leds_cpu;
2981 +u8 at91_leds_timer;
2982 +
2983 +void __init at91_init_leds(u8 cpu_led, u8 timer_led)
2984 +{
2985 +       at91_leds_cpu   = cpu_led;
2986 +       at91_leds_timer = timer_led;
2987 +}
2988 +#else
2989 +void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
2990 +#endif
2991 +
2992 +
2993 +#if defined(CONFIG_NEW_LEDS)
2994 +
2995 +static struct platform_device at91_leds = {
2996 +       .name           = "at91_leds",
2997 +       .id             = -1,
2998 +};
2999 +
3000 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
3001 +{
3002 +       if (!nr)
3003 +               return;
3004 +
3005 +       at91_leds.dev.platform_data = leds;
3006 +
3007 +       for ( ; nr; nr--, leds++) {
3008 +               leds->index = nr;       /* first record stores number of leds */
3009 +               at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
3010 +       }
3011 +
3012 +       platform_device_register(&at91_leds);
3013 +}
3014 +#else
3015 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
3016 +#endif
3017 +
3018 +
3019 +/* --------------------------------------------------------------------
3020 + *  UART
3021 + * -------------------------------------------------------------------- */
3022 +
3023 +#if defined(CONFIG_SERIAL_ATMEL)
3024 +static struct resource dbgu_resources[] = {
3025 +       [0] = {
3026 +               .start  = AT91_VA_BASE_SYS + AT91_DBGU,
3027 +               .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
3028 +               .flags  = IORESOURCE_MEM,
3029 +       },
3030 +       [1] = {
3031 +               .start  = AT91_ID_SYS,
3032 +               .end    = AT91_ID_SYS,
3033 +               .flags  = IORESOURCE_IRQ,
3034 +       },
3035 +};
3036 +
3037 +static struct atmel_uart_data dbgu_data = {
3038 +       .use_dma_tx     = 0,
3039 +       .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
3040 +       .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
3041 +};
3042 +
3043 +static struct platform_device at91rm9200_dbgu_device = {
3044 +       .name           = "atmel_usart",
3045 +       .id             = 0,
3046 +       .dev            = {
3047 +                               .platform_data  = &dbgu_data,
3048 +                               .coherent_dma_mask = 0xffffffff,
3049 +       },
3050 +       .resource       = dbgu_resources,
3051 +       .num_resources  = ARRAY_SIZE(dbgu_resources),
3052 +};
3053 +
3054 +static inline void configure_dbgu_pins(void)
3055 +{
3056 +       at91_set_A_periph(AT91_PIN_PA30, 0);            /* DRXD */
3057 +       at91_set_A_periph(AT91_PIN_PA31, 1);            /* DTXD */
3058 +}
3059 +
3060 +static struct resource uart0_resources[] = {
3061 +       [0] = {
3062 +               .start  = AT91RM9200_BASE_US0,
3063 +               .end    = AT91RM9200_BASE_US0 + SZ_16K - 1,
3064 +               .flags  = IORESOURCE_MEM,
3065 +       },
3066 +       [1] = {
3067 +               .start  = AT91RM9200_ID_US0,
3068 +               .end    = AT91RM9200_ID_US0,
3069 +               .flags  = IORESOURCE_IRQ,
3070 +       },
3071 +};
3072 +
3073 +static struct atmel_uart_data uart0_data = {
3074 +       .use_dma_tx     = 1,
3075 +       .use_dma_rx     = 1,
3076 +};
3077 +
3078 +static struct platform_device at91rm9200_uart0_device = {
3079 +       .name           = "atmel_usart",
3080 +       .id             = 1,
3081 +       .dev            = {
3082 +                               .platform_data  = &uart0_data,
3083 +                               .coherent_dma_mask = 0xffffffff,
3084 +       },
3085 +       .resource       = uart0_resources,
3086 +       .num_resources  = ARRAY_SIZE(uart0_resources),
3087 +};
3088 +
3089 +static inline void configure_usart0_pins(void)
3090 +{
3091 +       at91_set_A_periph(AT91_PIN_PA17, 1);            /* TXD0 */
3092 +       at91_set_A_periph(AT91_PIN_PA18, 0);            /* RXD0 */
3093 +       at91_set_A_periph(AT91_PIN_PA20, 0);            /* CTS0 */
3094 +
3095 +       /*
3096 +        * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
3097 +        *  We need to drive the pin manually.  Default is off (RTS is active low).
3098 +        */
3099 +       at91_set_gpio_output(AT91_PIN_PA21, 1);
3100 +}
3101 +
3102 +static struct resource uart1_resources[] = {
3103 +       [0] = {
3104 +               .start  = AT91RM9200_BASE_US1,
3105 +               .end    = AT91RM9200_BASE_US1 + SZ_16K - 1,
3106 +               .flags  = IORESOURCE_MEM,
3107 +       },
3108 +       [1] = {
3109 +               .start  = AT91RM9200_ID_US1,
3110 +               .end    = AT91RM9200_ID_US1,
3111 +               .flags  = IORESOURCE_IRQ,
3112 +       },
3113 +};
3114 +
3115 +static struct atmel_uart_data uart1_data = {
3116 +       .use_dma_tx     = 1,
3117 +       .use_dma_rx     = 1,
3118 +};
3119 +
3120 +static struct platform_device at91rm9200_uart1_device = {
3121 +       .name           = "atmel_usart",
3122 +       .id             = 2,
3123 +       .dev            = {
3124 +                               .platform_data  = &uart1_data,
3125 +                               .coherent_dma_mask = 0xffffffff,
3126 +       },
3127 +       .resource       = uart1_resources,
3128 +       .num_resources  = ARRAY_SIZE(uart1_resources),
3129 +};
3130 +
3131 +static inline void configure_usart1_pins(void)
3132 +{
3133 +       at91_set_A_periph(AT91_PIN_PB18, 0);            /* RI1 */
3134 +       at91_set_A_periph(AT91_PIN_PB19, 0);            /* DTR1 */
3135 +       at91_set_A_periph(AT91_PIN_PB20, 1);            /* TXD1 */
3136 +       at91_set_A_periph(AT91_PIN_PB21, 0);            /* RXD1 */
3137 +       at91_set_A_periph(AT91_PIN_PB23, 0);            /* DCD1 */
3138 +       at91_set_A_periph(AT91_PIN_PB24, 0);            /* CTS1 */
3139 +       at91_set_A_periph(AT91_PIN_PB25, 0);            /* DSR1 */
3140 +       at91_set_A_periph(AT91_PIN_PB26, 0);            /* RTS1 */
3141 +}
3142 +
3143 +static struct resource uart2_resources[] = {
3144 +       [0] = {
3145 +               .start  = AT91RM9200_BASE_US2,
3146 +               .end    = AT91RM9200_BASE_US2 + SZ_16K - 1,
3147 +               .flags  = IORESOURCE_MEM,
3148 +       },
3149 +       [1] = {
3150 +               .start  = AT91RM9200_ID_US2,
3151 +               .end    = AT91RM9200_ID_US2,
3152 +               .flags  = IORESOURCE_IRQ,
3153 +       },
3154 +};
3155 +
3156 +static struct atmel_uart_data uart2_data = {
3157 +       .use_dma_tx     = 1,
3158 +       .use_dma_rx     = 1,
3159 +};
3160 +
3161 +static struct platform_device at91rm9200_uart2_device = {
3162 +       .name           = "atmel_usart",
3163 +       .id             = 3,
3164 +       .dev            = {
3165 +                               .platform_data  = &uart2_data,
3166 +                               .coherent_dma_mask = 0xffffffff,
3167 +       },
3168 +       .resource       = uart2_resources,
3169 +       .num_resources  = ARRAY_SIZE(uart2_resources),
3170 +};
3171 +
3172 +static inline void configure_usart2_pins(void)
3173 +{
3174 +       at91_set_A_periph(AT91_PIN_PA22, 0);            /* RXD2 */
3175 +       at91_set_A_periph(AT91_PIN_PA23, 1);            /* TXD2 */
3176 +}
3177 +
3178 +static struct resource uart3_resources[] = {
3179 +       [0] = {
3180 +               .start  = AT91RM9200_BASE_US3,
3181 +               .end    = AT91RM9200_BASE_US3 + SZ_16K - 1,
3182 +               .flags  = IORESOURCE_MEM,
3183 +       },
3184 +       [1] = {
3185 +               .start  = AT91RM9200_ID_US3,
3186 +               .end    = AT91RM9200_ID_US3,
3187 +               .flags  = IORESOURCE_IRQ,
3188 +       },
3189 +};
3190 +
3191 +static struct atmel_uart_data uart3_data = {
3192 +       .use_dma_tx     = 1,
3193 +       .use_dma_rx     = 1,
3194 +};
3195 +
3196 +static struct platform_device at91rm9200_uart3_device = {
3197 +       .name           = "atmel_usart",
3198 +       .id             = 4,
3199 +       .dev            = {
3200 +                               .platform_data  = &uart3_data,
3201 +                               .coherent_dma_mask = 0xffffffff,
3202 +       },
3203 +       .resource       = uart3_resources,
3204 +       .num_resources  = ARRAY_SIZE(uart3_resources),
3205 +};
3206 +
3207 +static inline void configure_usart3_pins(void)
3208 +{
3209 +       at91_set_B_periph(AT91_PIN_PA5, 1);             /* TXD3 */
3210 +       at91_set_B_periph(AT91_PIN_PA6, 0);             /* RXD3 */
3211 +}
3212 +
3213 +struct platform_device *at91_uarts[ATMEL_MAX_UART];    /* the UARTs to use */
3214 +struct platform_device *atmel_default_console_device;  /* the serial console device */
3215 +
3216 +void __init at91_init_serial(struct at91_uart_config *config)
3217 +{
3218 +       int i;
3219 +
3220 +       /* Fill in list of supported UARTs */
3221 +       for (i = 0; i < config->nr_tty; i++) {
3222 +               switch (config->tty_map[i]) {
3223 +                       case 0:
3224 +                               configure_usart0_pins();
3225 +                               at91_uarts[i] = &at91rm9200_uart0_device;
3226 +                               at91_clock_associate("usart0_clk", &at91rm9200_uart0_device.dev, "usart");
3227 +                               break;
3228 +                       case 1:
3229 +                               configure_usart1_pins();
3230 +                               at91_uarts[i] = &at91rm9200_uart1_device;
3231 +                               at91_clock_associate("usart1_clk", &at91rm9200_uart1_device.dev, "usart");
3232 +                               break;
3233 +                       case 2:
3234 +                               configure_usart2_pins();
3235 +                               at91_uarts[i] = &at91rm9200_uart2_device;
3236 +                               at91_clock_associate("usart2_clk", &at91rm9200_uart2_device.dev, "usart");
3237 +                               break;
3238 +                       case 3:
3239 +                               configure_usart3_pins();
3240 +                               at91_uarts[i] = &at91rm9200_uart3_device;
3241 +                               at91_clock_associate("usart3_clk", &at91rm9200_uart3_device.dev, "usart");
3242 +                               break;
3243 +                       case 4:
3244 +                               configure_dbgu_pins();
3245 +                               at91_uarts[i] = &at91rm9200_dbgu_device;
3246 +                               at91_clock_associate("mck", &at91rm9200_dbgu_device.dev, "usart");
3247 +                               break;
3248 +                       default:
3249 +                               continue;
3250 +               }
3251 +               at91_uarts[i]->id = i;          /* update ID number to mapped ID */
3252 +       }
3253 +
3254 +       /* Set serial console device */
3255 +       if (config->console_tty < ATMEL_MAX_UART)
3256 +               atmel_default_console_device = at91_uarts[config->console_tty];
3257 +       if (!atmel_default_console_device)
3258 +               printk(KERN_INFO "AT91: No default serial console defined.\n");
3259 +}
3260 +
3261 +void __init at91_add_device_serial(void)
3262 +{
3263 +       int i;
3264 +
3265 +       for (i = 0; i < ATMEL_MAX_UART; i++) {
3266 +               if (at91_uarts[i])
3267 +                       platform_device_register(at91_uarts[i]);
3268 +       }
3269 +}
3270 +#else
3271 +void __init at91_init_serial(struct at91_uart_config *config) {}
3272 +void __init at91_add_device_serial(void) {}
3273 +#endif
3274 +
3275 +
3276 +/* -------------------------------------------------------------------- */
3277 +
3278 +/*
3279 + * These devices are always present and don't need any board-specific
3280 + * setup.
3281 + */
3282 +static int __init at91_add_standard_devices(void)
3283 +{
3284 +       at91_add_device_rtc();
3285 +       at91_add_device_watchdog();
3286 +       return 0;
3287 +}
3288 +
3289 +arch_initcall(at91_add_standard_devices);
3290 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91rm9200_time.c linux-2.6.19/arch/arm/mach-at91rm9200/at91rm9200_time.c
3291 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91rm9200_time.c       Mon Dec  4 16:39:29 2006
3292 +++ linux-2.6.19/arch/arm/mach-at91rm9200/at91rm9200_time.c     Thu Nov 16 11:41:09 2006
3293 @@ -30,6 +30,8 @@
3294  #include <asm/io.h>
3295  #include <asm/mach/time.h>
3296
3297 +#include <asm/arch/at91_st.h>
3298 +
3299  static unsigned long last_crtr;
3300
3301  /*
3302 @@ -99,6 +101,9 @@
3303         /* Set Period Interval timer */
3304         at91_sys_write(AT91_ST_PIMR, LATCH);
3305
3306 +       /* Clear any pending interrupts */
3307 +       (void) at91_sys_read(AT91_ST_SR);
3308 +
3309         /* Enable Period Interval Timer interrupt */
3310         at91_sys_write(AT91_ST_IER, AT91_ST_PITS);
3311  }
3312 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9260.c linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9260.c
3313 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9260.c   Thu Jan  1 02:00:00 1970
3314 +++ linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9260.c Mon Nov 20 10:52:16 2006
3315 @@ -0,0 +1,294 @@
3316 +/*
3317 + * arch/arm/mach-at91rm9200/at91sam9260.c
3318 + *
3319 + *  Copyright (C) 2006 SAN People
3320 + *
3321 + * This program is free software; you can redistribute it and/or modify
3322 + * it under the terms of the GNU General Public License as published by
3323 + * the Free Software Foundation; either version 2 of the License, or
3324 + * (at your option) any later version.
3325 + *
3326 + */
3327 +
3328 +#include <linux/module.h>
3329 +
3330 +#include <asm/mach/arch.h>
3331 +#include <asm/mach/map.h>
3332 +#include <asm/arch/at91sam9260.h>
3333 +#include <asm/arch/at91_pmc.h>
3334 +
3335 +#include "generic.h"
3336 +#include "clock.h"
3337 +
3338 +static struct map_desc at91sam9260_io_desc[] __initdata = {
3339 +       {
3340 +               .virtual        = AT91_VA_BASE_SYS,
3341 +               .pfn            = __phys_to_pfn(AT91_BASE_SYS),
3342 +               .length         = SZ_16K,
3343 +               .type           = MT_DEVICE,
3344 +       }, {
3345 +               .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
3346 +               .pfn            = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
3347 +               .length         = AT91SAM9260_SRAM0_SIZE,
3348 +               .type           = MT_DEVICE,
3349 +       }, {
3350 +               .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
3351 +               .pfn            = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
3352 +               .length         = AT91SAM9260_SRAM1_SIZE,
3353 +               .type           = MT_DEVICE,
3354 +       },
3355 +};
3356 +
3357 +/* --------------------------------------------------------------------
3358 + *  Clocks
3359 + * -------------------------------------------------------------------- */
3360 +
3361 +/*
3362 + * The peripheral clocks.
3363 + */
3364 +static struct clk pioA_clk = {
3365 +       .name           = "pioA_clk",
3366 +       .pmc_mask       = 1 << AT91SAM9260_ID_PIOA,
3367 +       .type           = CLK_TYPE_PERIPHERAL,
3368 +};
3369 +static struct clk pioB_clk = {
3370 +       .name           = "pioB_clk",
3371 +       .pmc_mask       = 1 << AT91SAM9260_ID_PIOB,
3372 +       .type           = CLK_TYPE_PERIPHERAL,
3373 +};
3374 +static struct clk pioC_clk = {
3375 +       .name           = "pioC_clk",
3376 +       .pmc_mask       = 1 << AT91SAM9260_ID_PIOC,
3377 +       .type           = CLK_TYPE_PERIPHERAL,
3378 +};
3379 +static struct clk adc_clk = {
3380 +       .name           = "adc_clk",
3381 +       .pmc_mask       = 1 << AT91SAM9260_ID_ADC,
3382 +       .type           = CLK_TYPE_PERIPHERAL,
3383 +};
3384 +static struct clk usart0_clk = {
3385 +       .name           = "usart0_clk",
3386 +       .pmc_mask       = 1 << AT91SAM9260_ID_US0,
3387 +       .type           = CLK_TYPE_PERIPHERAL,
3388 +};
3389 +static struct clk usart1_clk = {
3390 +       .name           = "usart1_clk",
3391 +       .pmc_mask       = 1 << AT91SAM9260_ID_US1,
3392 +       .type           = CLK_TYPE_PERIPHERAL,
3393 +};
3394 +static struct clk usart2_clk = {
3395 +       .name           = "usart2_clk",
3396 +       .pmc_mask       = 1 << AT91SAM9260_ID_US2,
3397 +       .type           = CLK_TYPE_PERIPHERAL,
3398 +};
3399 +static struct clk mmc_clk = {
3400 +       .name           = "mci_clk",
3401 +       .pmc_mask       = 1 << AT91SAM9260_ID_MCI,
3402 +       .type           = CLK_TYPE_PERIPHERAL,
3403 +};
3404 +static struct clk udc_clk = {
3405 +       .name           = "udc_clk",
3406 +       .pmc_mask       = 1 << AT91SAM9260_ID_UDP,
3407 +       .type           = CLK_TYPE_PERIPHERAL,
3408 +};
3409 +static struct clk twi_clk = {
3410 +       .name           = "twi_clk",
3411 +       .pmc_mask       = 1 << AT91SAM9260_ID_TWI,
3412 +       .type           = CLK_TYPE_PERIPHERAL,
3413 +};
3414 +static struct clk spi0_clk = {
3415 +       .name           = "spi0_clk",
3416 +       .pmc_mask       = 1 << AT91SAM9260_ID_SPI0,
3417 +       .type           = CLK_TYPE_PERIPHERAL,
3418 +};
3419 +static struct clk spi1_clk = {
3420 +       .name           = "spi1_clk",
3421 +       .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
3422 +       .type           = CLK_TYPE_PERIPHERAL,
3423 +};
3424 +static struct clk ohci_clk = {
3425 +       .name           = "ohci_clk",
3426 +       .pmc_mask       = 1 << AT91SAM9260_ID_UHP,
3427 +       .type           = CLK_TYPE_PERIPHERAL,
3428 +};
3429 +static struct clk ether_clk = {
3430 +       .name           = "ether_clk",
3431 +       .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
3432 +       .type           = CLK_TYPE_PERIPHERAL,
3433 +};
3434 +static struct clk isi_clk = {
3435 +       .name           = "isi_clk",
3436 +       .pmc_mask       = 1 << AT91SAM9260_ID_ISI,
3437 +       .type           = CLK_TYPE_PERIPHERAL,
3438 +};
3439 +static struct clk usart3_clk = {
3440 +       .name           = "usart3_clk",
3441 +       .pmc_mask       = 1 << AT91SAM9260_ID_US3,
3442 +       .type           = CLK_TYPE_PERIPHERAL,
3443 +};
3444 +static struct clk usart4_clk = {
3445 +       .name           = "usart4_clk",
3446 +       .pmc_mask       = 1 << AT91SAM9260_ID_US4,
3447 +       .type           = CLK_TYPE_PERIPHERAL,
3448 +};
3449 +static struct clk usart5_clk = {
3450 +       .name           = "usart5_clk",
3451 +       .pmc_mask       = 1 << AT91SAM9260_ID_US5,
3452 +       .type           = CLK_TYPE_PERIPHERAL,
3453 +};
3454 +
3455 +static struct clk *periph_clocks[] __initdata = {
3456 +       &pioA_clk,
3457 +       &pioB_clk,
3458 +       &pioC_clk,
3459 +       &adc_clk,
3460 +       &usart0_clk,
3461 +       &usart1_clk,
3462 +       &usart2_clk,
3463 +       &mmc_clk,
3464 +       &udc_clk,
3465 +       &twi_clk,
3466 +       &spi0_clk,
3467 +       &spi1_clk,
3468 +       // ssc
3469 +       // tc0 .. tc2
3470 +       &ohci_clk,
3471 +       &ether_clk,
3472 +       &isi_clk,
3473 +       &usart3_clk,
3474 +       &usart4_clk,
3475 +       &usart5_clk,
3476 +       // tc3 .. tc5
3477 +       // irq0 .. irq2
3478 +};
3479 +
3480 +/*
3481 + * The two programmable clocks.
3482 + * You must configure pin multiplexing to bring these signals out.
3483 + */
3484 +static struct clk pck0 = {
3485 +       .name           = "pck0",
3486 +       .pmc_mask       = AT91_PMC_PCK0,
3487 +       .type           = CLK_TYPE_PROGRAMMABLE,
3488 +       .id             = 0,
3489 +};
3490 +static struct clk pck1 = {
3491 +       .name           = "pck1",
3492 +       .pmc_mask       = AT91_PMC_PCK1,
3493 +       .type           = CLK_TYPE_PROGRAMMABLE,
3494 +       .id             = 1,
3495 +};
3496 +
3497 +static void __init at91sam9260_register_clocks(void)
3498 +{
3499 +       int i;
3500 +
3501 +       for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
3502 +               clk_register(periph_clocks[i]);
3503 +
3504 +       clk_register(&pck0);
3505 +       clk_register(&pck1);
3506 +}
3507 +
3508 +/* --------------------------------------------------------------------
3509 + *  GPIO
3510 + * -------------------------------------------------------------------- */
3511 +
3512 +static struct at91_gpio_bank at91sam9260_gpio[] = {
3513 +       {
3514 +               .id             = AT91SAM9260_ID_PIOA,
3515 +               .offset         = AT91_PIOA,
3516 +               .clock          = &pioA_clk,
3517 +       }, {
3518 +               .id             = AT91SAM9260_ID_PIOB,
3519 +               .offset         = AT91_PIOB,
3520 +               .clock          = &pioB_clk,
3521 +       }, {
3522 +               .id             = AT91SAM9260_ID_PIOC,
3523 +               .offset         = AT91_PIOC,
3524 +               .clock          = &pioC_clk,
3525 +       }
3526 +};
3527 +
3528 +static void at91sam9260_reset(void)
3529 +{
3530 +#warning "Implement CPU reset"
3531 +}
3532 +
3533 +
3534 +/* --------------------------------------------------------------------
3535 + *  AT91SAM9260 processor initialization
3536 + * -------------------------------------------------------------------- */
3537 +
3538 +void __init at91sam9260_initialize(unsigned long main_clock)
3539 +{
3540 +       /* Map peripherals */
3541 +       iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
3542 +
3543 +       at91_arch_reset = at91sam9260_reset;
3544 +       at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
3545 +                       | (1 << AT91SAM9260_ID_IRQ2);
3546 +
3547 +       /* Init clock subsystem */
3548 +       at91_clock_init(main_clock);
3549 +
3550 +       /* Register the processor-specific clocks */
3551 +       at91sam9260_register_clocks();
3552 +
3553 +       /* Register GPIO subsystem */
3554 +       at91_gpio_init(at91sam9260_gpio, 3);
3555 +}
3556 +
3557 +/* --------------------------------------------------------------------
3558 + *  Interrupt initialization
3559 + * -------------------------------------------------------------------- */
3560 +
3561 +/*
3562 + * The default interrupt priority levels (0 = lowest, 7 = highest).
3563 + */
3564 +static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
3565 +       7,      /* Advanced Interrupt Controller */
3566 +       7,      /* System Peripherals */
3567 +       0,      /* Parallel IO Controller A */
3568 +       0,      /* Parallel IO Controller B */
3569 +       0,      /* Parallel IO Controller C */
3570 +       0,      /* Analog-to-Digital Converter */
3571 +       6,      /* USART 0 */
3572 +       6,      /* USART 1 */
3573 +       6,      /* USART 2 */
3574 +       0,      /* Multimedia Card Interface */
3575 +       4,      /* USB Device Port */
3576 +       0,      /* Two-Wire Interface */
3577 +       6,      /* Serial Peripheral Interface 0 */
3578 +       6,      /* Serial Peripheral Interface 1 */
3579 +       5,      /* Serial Synchronous Controller */
3580 +       0,
3581 +       0,
3582 +       0,      /* Timer Counter 0 */
3583 +       0,      /* Timer Counter 1 */
3584 +       0,      /* Timer Counter 2 */
3585 +       3,      /* USB Host port */
3586 +       3,      /* Ethernet */
3587 +       0,      /* Image Sensor Interface */
3588 +       6,      /* USART 3 */
3589 +       6,      /* USART 4 */
3590 +       6,      /* USART 5 */
3591 +       0,      /* Timer Counter 3 */
3592 +       0,      /* Timer Counter 4 */
3593 +       0,      /* Timer Counter 5 */
3594 +       0,      /* Advanced Interrupt Controller */
3595 +       0,      /* Advanced Interrupt Controller */
3596 +       0,      /* Advanced Interrupt Controller */
3597 +};
3598 +
3599 +void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])
3600 +{
3601 +       if (!priority)
3602 +               priority = at91sam9260_default_irq_priority;
3603 +
3604 +       /* Initialize the AIC interrupt controller */
3605 +       at91_aic_init(priority);
3606 +
3607 +       /* Enable GPIO interrupts */
3608 +       at91_gpio_irq_setup();
3609 +}
3610 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9260_devices.c linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9260_devices.c
3611 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9260_devices.c   Thu Jan  1 02:00:00 1970
3612 +++ linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9260_devices.c Thu Nov 23 16:37:24 2006
3613 @@ -0,0 +1,892 @@
3614 +/*
3615 + * arch/arm/mach-at91rm9200/at91sam9260_devices.c
3616 + *
3617 + *  Copyright (C) 2006 Atmel
3618 + *
3619 + * This program is free software; you can redistribute it and/or modify
3620 + * it under the terms of the GNU General Public License as published by
3621 + * the Free Software Foundation; either version 2 of the License, or
3622 + * (at your option) any later version.
3623 + *
3624 + */
3625 +#include <asm/mach/arch.h>
3626 +#include <asm/mach/map.h>
3627 +
3628 +#include <linux/platform_device.h>
3629 +
3630 +#include <asm/arch/board.h>
3631 +#include <asm/arch/gpio.h>
3632 +#include <asm/arch/at91sam9260.h>
3633 +#include <asm/arch/at91sam926x_mc.h>
3634 +
3635 +#include "generic.h"
3636 +
3637 +#define SZ_512 0x00000200
3638 +#define SZ_256 0x00000100
3639 +#define SZ_16  0x00000010
3640 +
3641 +/* --------------------------------------------------------------------
3642 + *  USB Host
3643 + * -------------------------------------------------------------------- */
3644 +
3645 +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
3646 +static u64 ohci_dmamask = 0xffffffffUL;
3647 +static struct at91_usbh_data usbh_data;
3648 +
3649 +static struct resource usbh_resources[] = {
3650 +       [0] = {
3651 +               .start  = AT91SAM9260_UHP_BASE,
3652 +               .end    = AT91SAM9260_UHP_BASE + SZ_1M - 1,
3653 +               .flags  = IORESOURCE_MEM,
3654 +       },
3655 +       [1] = {
3656 +               .start  = AT91SAM9260_ID_UHP,
3657 +               .end    = AT91SAM9260_ID_UHP,
3658 +               .flags  = IORESOURCE_IRQ,
3659 +       },
3660 +};
3661 +
3662 +static struct platform_device at91_usbh_device = {
3663 +       .name           = "at91_ohci",
3664 +       .id             = -1,
3665 +       .dev            = {
3666 +                               .dma_mask               = &ohci_dmamask,
3667 +                               .coherent_dma_mask      = 0xffffffff,
3668 +                               .platform_data          = &usbh_data,
3669 +       },
3670 +       .resource       = usbh_resources,
3671 +       .num_resources  = ARRAY_SIZE(usbh_resources),
3672 +};
3673 +
3674 +void __init at91_add_device_usbh(struct at91_usbh_data *data)
3675 +{
3676 +       if (!data)
3677 +               return;
3678 +
3679 +       usbh_data = *data;
3680 +       platform_device_register(&at91_usbh_device);
3681 +}
3682 +#else
3683 +void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
3684 +#endif
3685 +
3686 +
3687 +/* --------------------------------------------------------------------
3688 + *  USB Device (Gadget)
3689 + * -------------------------------------------------------------------- */
3690 +
3691 +#ifdef CONFIG_USB_GADGET_AT91
3692 +static struct at91_udc_data udc_data;
3693 +
3694 +static struct resource udc_resources[] = {
3695 +       [0] = {
3696 +               .start  = AT91SAM9260_BASE_UDP,
3697 +               .end    = AT91SAM9260_BASE_UDP + SZ_16K - 1,
3698 +               .flags  = IORESOURCE_MEM,
3699 +       },
3700 +       [1] = {
3701 +               .start  = AT91SAM9260_ID_UDP,
3702 +               .end    = AT91SAM9260_ID_UDP,
3703 +               .flags  = IORESOURCE_IRQ,
3704 +       },
3705 +};
3706 +
3707 +static struct platform_device at91_udc_device = {
3708 +       .name           = "at91_udc",
3709 +       .id             = -1,
3710 +       .dev            = {
3711 +                               .platform_data          = &udc_data,
3712 +       },
3713 +       .resource       = udc_resources,
3714 +       .num_resources  = ARRAY_SIZE(udc_resources),
3715 +};
3716 +
3717 +void __init at91_add_device_udc(struct at91_udc_data *data)
3718 +{
3719 +       if (!data)
3720 +               return;
3721 +
3722 +       if (data->vbus_pin) {
3723 +               at91_set_gpio_input(data->vbus_pin, 0);
3724 +               at91_set_deglitch(data->vbus_pin, 1);
3725 +       }
3726 +
3727 +       /* Pullup pin is handled internally by USB device peripheral */
3728 +
3729 +       udc_data = *data;
3730 +       platform_device_register(&at91_udc_device);
3731 +}
3732 +#else
3733 +void __init at91_add_device_udc(struct at91_udc_data *data) {}
3734 +#endif
3735 +
3736 +
3737 +/* --------------------------------------------------------------------
3738 + *  Ethernet
3739 + * -------------------------------------------------------------------- */
3740 +
3741 +#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
3742 +static u64 eth_dmamask = 0xffffffffUL;
3743 +static struct eth_platform_data eth_data;
3744 +
3745 +static struct resource eth_resources[] = {
3746 +       [0] = {
3747 +               .start  = AT91SAM9260_BASE_EMAC,
3748 +               .end    = AT91SAM9260_BASE_EMAC + SZ_16K - 1,
3749 +               .flags  = IORESOURCE_MEM,
3750 +       },
3751 +       [1] = {
3752 +               .start  = AT91SAM9260_ID_EMAC,
3753 +               .end    = AT91SAM9260_ID_EMAC,
3754 +               .flags  = IORESOURCE_IRQ,
3755 +       },
3756 +};
3757 +
3758 +static struct platform_device at91sam9260_eth_device = {
3759 +       .name           = "macb",
3760 +       .id             = -1,
3761 +       .dev            = {
3762 +                               .dma_mask               = &eth_dmamask,
3763 +                               .coherent_dma_mask      = 0xffffffff,
3764 +                               .platform_data          = &eth_data,
3765 +       },
3766 +       .resource       = eth_resources,
3767 +       .num_resources  = ARRAY_SIZE(eth_resources),
3768 +};
3769 +
3770 +void __init at91_add_device_eth(struct eth_platform_data *data)
3771 +{
3772 +       if (!data)
3773 +               return;
3774 +
3775 +       if (data->phy_irq_pin) {
3776 +               at91_set_gpio_input(data->phy_irq_pin, 0);
3777 +               at91_set_deglitch(data->phy_irq_pin, 1);
3778 +       }
3779 +
3780 +       /* Pins used for MII and RMII */
3781 +       at91_set_A_periph(AT91_PIN_PA19, 0);    /* ETXCK_EREFCK */
3782 +       at91_set_A_periph(AT91_PIN_PA17, 0);    /* ERXDV */
3783 +       at91_set_A_periph(AT91_PIN_PA14, 0);    /* ERX0 */
3784 +       at91_set_A_periph(AT91_PIN_PA15, 0);    /* ERX1 */
3785 +       at91_set_A_periph(AT91_PIN_PA18, 0);    /* ERXER */
3786 +       at91_set_A_periph(AT91_PIN_PA16, 0);    /* ETXEN */
3787 +       at91_set_A_periph(AT91_PIN_PA12, 0);    /* ETX0 */
3788 +       at91_set_A_periph(AT91_PIN_PA13, 0);    /* ETX1 */
3789 +       at91_set_A_periph(AT91_PIN_PA21, 0);    /* EMDIO */
3790 +       at91_set_A_periph(AT91_PIN_PA20, 0);    /* EMDC */
3791 +
3792 +       if (!data->is_rmii) {
3793 +               at91_set_B_periph(AT91_PIN_PA28, 0);    /* ECRS */
3794 +               at91_set_B_periph(AT91_PIN_PA29, 0);    /* ECOL */
3795 +               at91_set_B_periph(AT91_PIN_PA25, 0);    /* ERX2 */
3796 +               at91_set_B_periph(AT91_PIN_PA26, 0);    /* ERX3 */
3797 +               at91_set_B_periph(AT91_PIN_PA27, 0);    /* ERXCK */
3798 +               at91_set_B_periph(AT91_PIN_PA23, 0);    /* ETX2 */
3799 +               at91_set_B_periph(AT91_PIN_PA24, 0);    /* ETX3 */
3800 +               at91_set_B_periph(AT91_PIN_PA22, 0);    /* ETXER */
3801 +       }
3802 +
3803 +       eth_data = *data;
3804 +       platform_device_register(&at91sam9260_eth_device);
3805 +}
3806 +#else
3807 +void __init at91_add_device_eth(struct eth_platform_data *data) {}
3808 +#endif
3809 +
3810 +
3811 +/* --------------------------------------------------------------------
3812 + *  MMC / SD
3813 + * -------------------------------------------------------------------- */
3814 +
3815 +#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
3816 +static u64 mmc_dmamask = 0xffffffffUL;
3817 +static struct at91_mmc_data mmc_data;
3818 +
3819 +static struct resource mmc_resources[] = {
3820 +       [0] = {
3821 +               .start  = AT91SAM9260_BASE_MCI,
3822 +               .end    = AT91SAM9260_BASE_MCI + SZ_16K - 1,
3823 +               .flags  = IORESOURCE_MEM,
3824 +       },
3825 +       [1] = {
3826 +               .start  = AT91SAM9260_ID_MCI,
3827 +               .end    = AT91SAM9260_ID_MCI,
3828 +               .flags  = IORESOURCE_IRQ,
3829 +       },
3830 +};
3831 +
3832 +static struct platform_device at91sam9260_mmc_device = {
3833 +       .name           = "at91_mci",
3834 +       .id             = -1,
3835 +       .dev            = {
3836 +                               .dma_mask               = &mmc_dmamask,
3837 +                               .coherent_dma_mask      = 0xffffffff,
3838 +                               .platform_data          = &mmc_data,
3839 +       },
3840 +       .resource       = mmc_resources,
3841 +       .num_resources  = ARRAY_SIZE(mmc_resources),
3842 +};
3843 +
3844 +void __init at91_add_device_mmc(struct at91_mmc_data *data)
3845 +{
3846 +       if (!data)
3847 +               return;
3848 +
3849 +       /* input/irq */
3850 +       if (data->det_pin) {
3851 +               at91_set_gpio_input(data->det_pin, 1);
3852 +               at91_set_deglitch(data->det_pin, 1);
3853 +       }
3854 +       if (data->wp_pin)
3855 +               at91_set_gpio_input(data->wp_pin, 1);
3856 +       if (data->vcc_pin)
3857 +               at91_set_gpio_output(data->vcc_pin, 0);
3858 +
3859 +       /* CLK */
3860 +       at91_set_A_periph(AT91_PIN_PA8, 0);
3861 +
3862 +       if (data->slot_b) {
3863 +               /* CMD */
3864 +               at91_set_B_periph(AT91_PIN_PA1, 1);
3865 +
3866 +               /* DAT0, maybe DAT1..DAT3 */
3867 +               at91_set_B_periph(AT91_PIN_PA0, 1);
3868 +               if (data->wire4) {
3869 +                       at91_set_B_periph(AT91_PIN_PA5, 1);
3870 +                       at91_set_B_periph(AT91_PIN_PA4, 1);
3871 +                       at91_set_B_periph(AT91_PIN_PA3, 1);
3872 +               }
3873 +       } else {
3874 +               /* CMD */
3875 +               at91_set_A_periph(AT91_PIN_PA7, 1);
3876 +
3877 +               /* DAT0, maybe DAT1..DAT3 */
3878 +               at91_set_A_periph(AT91_PIN_PA6, 1);
3879 +               if (data->wire4) {
3880 +                       at91_set_A_periph(AT91_PIN_PA9, 1);
3881 +                       at91_set_A_periph(AT91_PIN_PA10, 1);
3882 +                       at91_set_A_periph(AT91_PIN_PA11, 1);
3883 +               }
3884 +       }
3885 +
3886 +       mmc_data = *data;
3887 +       platform_device_register(&at91sam9260_mmc_device);
3888 +}
3889 +#else
3890 +void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
3891 +#endif
3892 +
3893 +
3894 +/* --------------------------------------------------------------------
3895 + *  NAND / SmartMedia
3896 + * -------------------------------------------------------------------- */
3897 +
3898 +#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
3899 +static struct at91_nand_data nand_data;
3900 +
3901 +#define NAND_BASE      AT91_CHIPSELECT_3
3902 +
3903 +static struct resource nand_resources[] = {
3904 +       {
3905 +               .start  = NAND_BASE,
3906 +               .end    = NAND_BASE + SZ_8M - 1,
3907 +               .flags  = IORESOURCE_MEM,
3908 +       }
3909 +};
3910 +
3911 +static struct platform_device at91sam9260_nand_device = {
3912 +       .name           = "at91_nand",
3913 +       .id             = -1,
3914 +       .dev            = {
3915 +                               .platform_data  = &nand_data,
3916 +       },
3917 +       .resource       = nand_resources,
3918 +       .num_resources  = ARRAY_SIZE(nand_resources),
3919 +};
3920 +
3921 +void __init at91_add_device_nand(struct at91_nand_data *data)
3922 +{
3923 +       unsigned long csa, mode;
3924 +
3925 +       if (!data)
3926 +               return;
3927 +
3928 +       csa = at91_sys_read(AT91_MATRIX_EBICSA);
3929 +       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC);
3930 +
3931 +       /* set the bus interface characteristics */
3932 +       at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
3933 +                       | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
3934 +
3935 +       at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
3936 +                       | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
3937 +
3938 +       at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
3939 +
3940 +       if (data->bus_width_16)
3941 +               mode = AT91_SMC_DBW_16;
3942 +       else
3943 +               mode = AT91_SMC_DBW_8;
3944 +       at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
3945 +
3946 +       /* enable pin */
3947 +       if (data->enable_pin)
3948 +               at91_set_gpio_output(data->enable_pin, 1);
3949 +
3950 +       /* ready/busy pin */
3951 +       if (data->rdy_pin)
3952 +               at91_set_gpio_input(data->rdy_pin, 1);
3953 +
3954 +       /* card detect pin */
3955 +       if (data->det_pin)
3956 +               at91_set_gpio_input(data->det_pin, 1);
3957 +
3958 +       nand_data = *data;
3959 +       platform_device_register(&at91sam9260_nand_device);
3960 +}
3961 +#else
3962 +void __init at91_add_device_nand(struct at91_nand_data *data) {}
3963 +#endif
3964 +
3965 +
3966 +/* --------------------------------------------------------------------
3967 + *  TWI (i2c)
3968 + * -------------------------------------------------------------------- */
3969 +
3970 +#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
3971 +
3972 +static struct resource twi_resources[] = {
3973 +       [0] = {
3974 +               .start  = AT91SAM9260_BASE_TWI,
3975 +               .end    = AT91SAM9260_BASE_TWI + SZ_16K - 1,
3976 +               .flags  = IORESOURCE_MEM,
3977 +       },
3978 +       [1] = {
3979 +               .start  = AT91SAM9260_ID_TWI,
3980 +               .end    = AT91SAM9260_ID_TWI,
3981 +               .flags  = IORESOURCE_IRQ,
3982 +       },
3983 +};
3984 +
3985 +static struct platform_device at91sam9260_twi_device = {
3986 +       .name           = "at91_i2c",
3987 +       .id             = -1,
3988 +       .resource       = twi_resources,
3989 +       .num_resources  = ARRAY_SIZE(twi_resources),
3990 +};
3991 +
3992 +void __init at91_add_device_i2c(void)
3993 +{
3994 +       /* pins used for TWI interface */
3995 +       at91_set_A_periph(AT91_PIN_PA23, 0);            /* TWD */
3996 +       at91_set_multi_drive(AT91_PIN_PA23, 1);
3997 +
3998 +       at91_set_A_periph(AT91_PIN_PA24, 0);            /* TWCK */
3999 +       at91_set_multi_drive(AT91_PIN_PA24, 1);
4000 +
4001 +       platform_device_register(&at91sam9260_twi_device);
4002 +}
4003 +#else
4004 +void __init at91_add_device_i2c(void) {}
4005 +#endif
4006 +
4007 +
4008 +/* --------------------------------------------------------------------
4009 + *  SPI
4010 + * -------------------------------------------------------------------- */
4011 +
4012 +#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
4013 +static u64 spi_dmamask = 0xffffffffUL;
4014 +
4015 +static struct resource spi0_resources[] = {
4016 +       [0] = {
4017 +               .start  = AT91SAM9260_BASE_SPI0,
4018 +               .end    = AT91SAM9260_BASE_SPI0 + SZ_16K - 1,
4019 +               .flags  = IORESOURCE_MEM,
4020 +       },
4021 +       [1] = {
4022 +               .start  = AT91SAM9260_ID_SPI0,
4023 +               .end    = AT91SAM9260_ID_SPI0,
4024 +               .flags  = IORESOURCE_IRQ,
4025 +       },
4026 +};
4027 +
4028 +static struct platform_device at91sam9260_spi0_device = {
4029 +       .name           = "atmel_spi",
4030 +       .id             = 0,
4031 +       .dev            = {
4032 +                               .dma_mask               = &spi_dmamask,
4033 +                               .coherent_dma_mask      = 0xffffffff,
4034 +       },
4035 +       .resource       = spi0_resources,
4036 +       .num_resources  = ARRAY_SIZE(spi0_resources),
4037 +};
4038 +
4039 +static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 };
4040 +
4041 +static struct resource spi1_resources[] = {
4042 +       [0] = {
4043 +               .start  = AT91SAM9260_BASE_SPI1,
4044 +               .end    = AT91SAM9260_BASE_SPI1 + SZ_16K - 1,
4045 +               .flags  = IORESOURCE_MEM,
4046 +       },
4047 +       [1] = {
4048 +               .start  = AT91SAM9260_ID_SPI1,
4049 +               .end    = AT91SAM9260_ID_SPI1,
4050 +               .flags  = IORESOURCE_IRQ,
4051 +       },
4052 +};
4053 +
4054 +static struct platform_device at91sam9260_spi1_device = {
4055 +       .name           = "atmel_spi",
4056 +       .id             = 1,
4057 +       .dev            = {
4058 +                               .dma_mask               = &spi_dmamask,
4059 +                               .coherent_dma_mask      = 0xffffffff,
4060 +       },
4061 +       .resource       = spi1_resources,
4062 +       .num_resources  = ARRAY_SIZE(spi1_resources),
4063 +};
4064 +
4065 +static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 };
4066 +
4067 +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
4068 +{
4069 +       int i;
4070 +       unsigned long cs_pin;
4071 +       short enable_spi0 = 0;
4072 +       short enable_spi1 = 0;
4073 +
4074 +       /* Choose SPI chip-selects */
4075 +       for (i = 0; i < nr_devices; i++) {
4076 +               if (devices[i].controller_data)
4077 +                       cs_pin = (unsigned long) devices[i].controller_data;
4078 +               else if (devices[i].bus_num == 0)
4079 +                       cs_pin = spi0_standard_cs[devices[i].chip_select];
4080 +               else
4081 +                       cs_pin = spi1_standard_cs[devices[i].chip_select];
4082 +
4083 +               if (devices[i].bus_num == 0)
4084 +                       enable_spi0 = 1;
4085 +               else
4086 +                       enable_spi1 = 1;
4087 +
4088 +               /* enable chip-select pin */
4089 +               at91_set_gpio_output(cs_pin, 1);
4090 +
4091 +               /* pass chip-select pin to driver */
4092 +               devices[i].controller_data = (void *) cs_pin;
4093 +       }
4094 +
4095 +       spi_register_board_info(devices, nr_devices);
4096 +
4097 +       /* Configure SPI bus(es) */
4098 +       if (enable_spi0) {
4099 +               at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
4100 +               at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
4101 +               at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI1_SPCK */
4102 +
4103 +               at91_clock_associate("spi0_clk", &at91sam9260_spi0_device.dev, "spi_clk");
4104 +               platform_device_register(&at91sam9260_spi0_device);
4105 +       }
4106 +       if (enable_spi1) {
4107 +               at91_set_A_periph(AT91_PIN_PB0, 0);     /* SPI1_MISO */
4108 +               at91_set_A_periph(AT91_PIN_PB1, 0);     /* SPI1_MOSI */
4109 +               at91_set_A_periph(AT91_PIN_PB2, 0);     /* SPI1_SPCK */
4110 +
4111 +               at91_clock_associate("spi1_clk", &at91sam9260_spi1_device.dev, "spi_clk");
4112 +               platform_device_register(&at91sam9260_spi1_device);
4113 +       }
4114 +}
4115 +#else
4116 +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
4117 +#endif
4118 +
4119 +
4120 +/* --------------------------------------------------------------------
4121 + *  LEDs
4122 + * -------------------------------------------------------------------- */
4123 +
4124 +#if defined(CONFIG_LEDS)
4125 +u8 at91_leds_cpu;
4126 +u8 at91_leds_timer;
4127 +
4128 +void __init at91_init_leds(u8 cpu_led, u8 timer_led)
4129 +{
4130 +       at91_leds_cpu   = cpu_led;
4131 +       at91_leds_timer = timer_led;
4132 +}
4133 +#else
4134 +void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
4135 +#endif
4136 +
4137 +
4138 +#if defined(CONFIG_NEW_LEDS)
4139 +
4140 +static struct platform_device at91_leds = {
4141 +       .name           = "at91_leds",
4142 +       .id             = -1,
4143 +};
4144 +
4145 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
4146 +{
4147 +       if (!nr)
4148 +               return;
4149 +
4150 +       at91_leds.dev.platform_data = leds;
4151 +
4152 +       for ( ; nr; nr--, leds++) {
4153 +               leds->index = nr;       /* first record stores number of leds */
4154 +               at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
4155 +       }
4156 +
4157 +       platform_device_register(&at91_leds);
4158 +}
4159 +#else
4160 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
4161 +#endif
4162 +
4163 +
4164 +/* --------------------------------------------------------------------
4165 + *  UART
4166 + * -------------------------------------------------------------------- */
4167 +#if defined(CONFIG_SERIAL_ATMEL)
4168 +static struct resource dbgu_resources[] = {
4169 +       [0] = {
4170 +               .start  = AT91_VA_BASE_SYS + AT91_DBGU,
4171 +               .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
4172 +               .flags  = IORESOURCE_MEM,
4173 +       },
4174 +       [1] = {
4175 +               .start  = AT91_ID_SYS,
4176 +               .end    = AT91_ID_SYS,
4177 +               .flags  = IORESOURCE_IRQ,
4178 +       },
4179 +};
4180 +
4181 +static struct atmel_uart_data dbgu_data = {
4182 +       .use_dma_tx     = 0,
4183 +       .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
4184 +       .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
4185 +};
4186 +
4187 +static struct platform_device at91sam9260_dbgu_device = {
4188 +       .name           = "atmel_usart",
4189 +       .id             = 0,
4190 +       .dev            = {
4191 +                               .platform_data  = &dbgu_data,
4192 +                               .coherent_dma_mask = 0xffffffff,
4193 +       },
4194 +       .resource       = dbgu_resources,
4195 +       .num_resources  = ARRAY_SIZE(dbgu_resources),
4196 +};
4197 +
4198 +static inline void configure_dbgu_pins(void)
4199 +{
4200 +       at91_set_A_periph(AT91_PIN_PB14, 0);            /* DRXD */
4201 +       at91_set_A_periph(AT91_PIN_PB15, 1);            /* DTXD */
4202 +}
4203 +
4204 +static struct resource uart0_resources[] = {
4205 +       [0] = {
4206 +               .start  = AT91SAM9260_BASE_US0,
4207 +               .end    = AT91SAM9260_BASE_US0 + SZ_16K - 1,
4208 +               .flags  = IORESOURCE_MEM,
4209 +       },
4210 +       [1] = {
4211 +               .start  = AT91SAM9260_ID_US0,
4212 +               .end    = AT91SAM9260_ID_US0,
4213 +               .flags  = IORESOURCE_IRQ,
4214 +       },
4215 +};
4216 +
4217 +static struct atmel_uart_data uart0_data = {
4218 +       .use_dma_tx     = 1,
4219 +       .use_dma_rx     = 1,
4220 +};
4221 +
4222 +static struct platform_device at91sam9260_uart0_device = {
4223 +       .name           = "atmel_usart",
4224 +       .id             = 1,
4225 +       .dev            = {
4226 +                               .platform_data  = &uart0_data,
4227 +                               .coherent_dma_mask = 0xffffffff,
4228 +       },
4229 +       .resource       = uart0_resources,
4230 +       .num_resources  = ARRAY_SIZE(uart0_resources),
4231 +};
4232 +
4233 +static inline void configure_usart0_pins(void)
4234 +{
4235 +       at91_set_A_periph(AT91_PIN_PB4, 1);             /* TXD0 */
4236 +       at91_set_A_periph(AT91_PIN_PB5, 0);             /* RXD0 */
4237 +       at91_set_A_periph(AT91_PIN_PB26, 0);            /* RTS0 */
4238 +       at91_set_A_periph(AT91_PIN_PB27, 0);            /* CTS0 */
4239 +       at91_set_A_periph(AT91_PIN_PB24, 0);            /* DTR0 */
4240 +       at91_set_A_periph(AT91_PIN_PB22, 0);            /* DSR0 */
4241 +       at91_set_A_periph(AT91_PIN_PB23, 0);            /* DCD0 */
4242 +       at91_set_A_periph(AT91_PIN_PB25, 0);            /* RI0 */
4243 +}
4244 +
4245 +static struct resource uart1_resources[] = {
4246 +       [0] = {
4247 +               .start  = AT91SAM9260_BASE_US1,
4248 +               .end    = AT91SAM9260_BASE_US1 + SZ_16K - 1,
4249 +               .flags  = IORESOURCE_MEM,
4250 +       },
4251 +       [1] = {
4252 +               .start  = AT91SAM9260_ID_US1,
4253 +               .end    = AT91SAM9260_ID_US1,
4254 +               .flags  = IORESOURCE_IRQ,
4255 +       },
4256 +};
4257 +
4258 +static struct atmel_uart_data uart1_data = {
4259 +       .use_dma_tx     = 1,
4260 +       .use_dma_rx     = 1,
4261 +};
4262 +
4263 +static struct platform_device at91sam9260_uart1_device = {
4264 +       .name           = "atmel_usart",
4265 +       .id             = 2,
4266 +       .dev            = {
4267 +                               .platform_data  = &uart1_data,
4268 +                               .coherent_dma_mask = 0xffffffff,
4269 +       },
4270 +       .resource       = uart1_resources,
4271 +       .num_resources  = ARRAY_SIZE(uart1_resources),
4272 +};
4273 +
4274 +static inline void configure_usart1_pins(void)
4275 +{
4276 +       at91_set_A_periph(AT91_PIN_PB6, 1);             /* TXD1 */
4277 +       at91_set_A_periph(AT91_PIN_PB7, 0);             /* RXD1 */
4278 +       at91_set_A_periph(AT91_PIN_PB28, 0);            /* RTS1 */
4279 +       at91_set_A_periph(AT91_PIN_PB29, 0);            /* CTS1 */
4280 +}
4281 +
4282 +static struct resource uart2_resources[] = {
4283 +       [0] = {
4284 +               .start  = AT91SAM9260_BASE_US2,
4285 +               .end    = AT91SAM9260_BASE_US2 + SZ_16K - 1,
4286 +               .flags  = IORESOURCE_MEM,
4287 +       },
4288 +       [1] = {
4289 +               .start  = AT91SAM9260_ID_US2,
4290 +               .end    = AT91SAM9260_ID_US2,
4291 +               .flags  = IORESOURCE_IRQ,
4292 +       },
4293 +};
4294 +
4295 +static struct atmel_uart_data uart2_data = {
4296 +       .use_dma_tx     = 1,
4297 +       .use_dma_rx     = 1,
4298 +};
4299 +
4300 +static struct platform_device at91sam9260_uart2_device = {
4301 +       .name           = "atmel_usart",
4302 +       .id             = 3,
4303 +       .dev            = {
4304 +                               .platform_data  = &uart2_data,
4305 +                               .coherent_dma_mask = 0xffffffff,
4306 +       },
4307 +       .resource       = uart2_resources,
4308 +       .num_resources  = ARRAY_SIZE(uart2_resources),
4309 +};
4310 +
4311 +static inline void configure_usart2_pins(void)
4312 +{
4313 +       at91_set_A_periph(AT91_PIN_PB8, 1);             /* TXD2 */
4314 +       at91_set_A_periph(AT91_PIN_PB9, 0);             /* RXD2 */
4315 +}
4316 +
4317 +static struct resource uart3_resources[] = {
4318 +       [0] = {
4319 +               .start  = AT91SAM9260_BASE_US3,
4320 +               .end    = AT91SAM9260_BASE_US3 + SZ_16K - 1,
4321 +               .flags  = IORESOURCE_MEM,
4322 +       },
4323 +       [1] = {
4324 +               .start  = AT91SAM9260_ID_US3,
4325 +               .end    = AT91SAM9260_ID_US3,
4326 +               .flags  = IORESOURCE_IRQ,
4327 +       },
4328 +};
4329 +
4330 +static struct atmel_uart_data uart3_data = {
4331 +       .use_dma_tx     = 1,
4332 +       .use_dma_rx     = 1,
4333 +};
4334 +
4335 +static struct platform_device at91sam9260_uart3_device = {
4336 +       .name           = "atmel_usart",
4337 +       .id             = 4,
4338 +       .dev            = {
4339 +                               .platform_data  = &uart3_data,
4340 +                               .coherent_dma_mask = 0xffffffff,
4341 +       },
4342 +       .resource       = uart3_resources,
4343 +       .num_resources  = ARRAY_SIZE(uart3_resources),
4344 +};
4345 +
4346 +static inline void configure_usart3_pins(void)
4347 +{
4348 +       at91_set_A_periph(AT91_PIN_PB10, 1);            /* TXD3 */
4349 +       at91_set_A_periph(AT91_PIN_PB11, 0);            /* RXD3 */
4350 +}
4351 +
4352 +static struct resource uart4_resources[] = {
4353 +       [0] = {
4354 +               .start  = AT91SAM9260_BASE_US4,
4355 +               .end    = AT91SAM9260_BASE_US4 + SZ_16K - 1,
4356 +               .flags  = IORESOURCE_MEM,
4357 +       },
4358 +       [1] = {
4359 +               .start  = AT91SAM9260_ID_US4,
4360 +               .end    = AT91SAM9260_ID_US4,
4361 +               .flags  = IORESOURCE_IRQ,
4362 +       },
4363 +};
4364 +
4365 +static struct atmel_uart_data uart4_data = {
4366 +       .use_dma_tx     = 1,
4367 +       .use_dma_rx     = 1,
4368 +};
4369 +
4370 +static struct platform_device at91sam9260_uart4_device = {
4371 +       .name           = "atmel_usart",
4372 +       .id             = 5,
4373 +       .dev            = {
4374 +                               .platform_data  = &uart4_data,
4375 +                               .coherent_dma_mask = 0xffffffff,
4376 +       },
4377 +       .resource       = uart4_resources,
4378 +       .num_resources  = ARRAY_SIZE(uart4_resources),
4379 +};
4380 +
4381 +static inline void configure_usart4_pins(void)
4382 +{
4383 +       at91_set_B_periph(AT91_PIN_PA31, 1);            /* TXD4 */
4384 +       at91_set_B_periph(AT91_PIN_PA30, 0);            /* RXD4 */
4385 +}
4386 +
4387 +static struct resource uart5_resources[] = {
4388 +       [0] = {
4389 +               .start  = AT91SAM9260_BASE_US5,
4390 +               .end    = AT91SAM9260_BASE_US5 + SZ_16K - 1,
4391 +               .flags  = IORESOURCE_MEM,
4392 +       },
4393 +       [1] = {
4394 +               .start  = AT91SAM9260_ID_US5,
4395 +               .end    = AT91SAM9260_ID_US5,
4396 +               .flags  = IORESOURCE_IRQ,
4397 +       },
4398 +};
4399 +
4400 +static struct atmel_uart_data uart5_data = {
4401 +       .use_dma_tx     = 1,
4402 +       .use_dma_rx     = 1,
4403 +};
4404 +
4405 +static struct platform_device at91sam9260_uart5_device = {
4406 +       .name           = "atmel_usart",
4407 +       .id             = 6,
4408 +       .dev            = {
4409 +                               .platform_data  = &uart5_data,
4410 +                               .coherent_dma_mask = 0xffffffff,
4411 +       },
4412 +       .resource       = uart5_resources,
4413 +       .num_resources  = ARRAY_SIZE(uart5_resources),
4414 +};
4415 +
4416 +static inline void configure_usart5_pins(void)
4417 +{
4418 +       at91_set_A_periph(AT91_PIN_PB12, 1);            /* TXD5 */
4419 +       at91_set_A_periph(AT91_PIN_PB13, 0);            /* RXD5 */
4420 +}
4421 +
4422 +struct platform_device *at91_uarts[ATMEL_MAX_UART];    /* the UARTs to use */
4423 +struct platform_device *atmel_default_console_device;  /* the serial console device */
4424 +
4425 +void __init at91_init_serial(struct at91_uart_config *config)
4426 +{
4427 +       int i;
4428 +
4429 +       /* Fill in list of supported UARTs */
4430 +       for (i = 0; i < config->nr_tty; i++) {
4431 +               switch (config->tty_map[i]) {
4432 +                       case 0:
4433 +                               configure_usart0_pins();
4434 +                               at91_uarts[i] = &at91sam9260_uart0_device;
4435 +                               at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart");
4436 +                               break;
4437 +                       case 1:
4438 +                               configure_usart1_pins();
4439 +                               at91_uarts[i] = &at91sam9260_uart1_device;
4440 +                               at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart");
4441 +                               break;
4442 +                       case 2:
4443 +                               configure_usart2_pins();
4444 +                               at91_uarts[i] = &at91sam9260_uart2_device;
4445 +                               at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart");
4446 +                               break;
4447 +                       case 3:
4448 +                               configure_usart3_pins();
4449 +                               at91_uarts[i] = &at91sam9260_uart3_device;
4450 +                               at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart");
4451 +                               break;
4452 +                       case 4:
4453 +                               configure_usart4_pins();
4454 +                               at91_uarts[i] = &at91sam9260_uart4_device;
4455 +                               at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart");
4456 +                               break;
4457 +                       case 5:
4458 +                               configure_usart5_pins();
4459 +                               at91_uarts[i] = &at91sam9260_uart5_device;
4460 +                               at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart");
4461 +                               break;
4462 +                       case 6:
4463 +                               configure_dbgu_pins();
4464 +                               at91_uarts[i] = &at91sam9260_dbgu_device;
4465 +                               at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart");
4466 +                               break;
4467 +                       default:
4468 +                               continue;
4469 +               }
4470 +               at91_uarts[i]->id = i;          /* update ID number to mapped ID */
4471 +       }
4472 +
4473 +       /* Set serial console device */
4474 +       if (config->console_tty < ATMEL_MAX_UART)
4475 +               atmel_default_console_device = at91_uarts[config->console_tty];
4476 +       if (!atmel_default_console_device)
4477 +               printk(KERN_INFO "AT91: No default serial console defined.\n");
4478 +}
4479 +
4480 +void __init at91_add_device_serial(void)
4481 +{
4482 +       int i;
4483 +
4484 +       for (i = 0; i < ATMEL_MAX_UART; i++) {
4485 +               if (at91_uarts[i])
4486 +                       platform_device_register(at91_uarts[i]);
4487 +       }
4488 +}
4489 +#else
4490 +void __init at91_init_serial(struct at91_uart_config *config) {}
4491 +void __init at91_add_device_serial(void) {}
4492 +#endif
4493 +
4494 +
4495 +/* -------------------------------------------------------------------- */
4496 +/*
4497 + * These devices are always present and don't need any board-specific
4498 + * setup.
4499 + */
4500 +static int __init at91_add_standard_devices(void)
4501 +{
4502 +       return 0;
4503 +}
4504 +
4505 +arch_initcall(at91_add_standard_devices);
4506 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9261.c linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9261.c
4507 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9261.c   Thu Jan  1 02:00:00 1970
4508 +++ linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9261.c Thu Nov 23 15:41:39 2006
4509 @@ -0,0 +1,289 @@
4510 +/*
4511 + * arch/arm/mach-at91rm9200/at91sam9261.c
4512 + *
4513 + *  Copyright (C) 2005 SAN People
4514 + *
4515 + * This program is free software; you can redistribute it and/or modify
4516 + * it under the terms of the GNU General Public License as published by
4517 + * the Free Software Foundation; either version 2 of the License, or
4518 + * (at your option) any later version.
4519 + *
4520 + */
4521 +
4522 +#include <linux/module.h>
4523 +
4524 +#include <asm/mach/arch.h>
4525 +#include <asm/mach/map.h>
4526 +#include <asm/arch/at91sam9261.h>
4527 +#include <asm/arch/at91_pmc.h>
4528 +
4529 +#include "generic.h"
4530 +#include "clock.h"
4531 +
4532 +static struct map_desc at91sam9261_io_desc[] __initdata = {
4533 +       {
4534 +               .virtual        = AT91_VA_BASE_SYS,
4535 +               .pfn            = __phys_to_pfn(AT91_BASE_SYS),
4536 +               .length         = SZ_16K,
4537 +               .type           = MT_DEVICE,
4538 +       }, {
4539 +               .virtual        = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
4540 +               .pfn            = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
4541 +               .length         = AT91SAM9261_SRAM_SIZE,
4542 +               .type           = MT_DEVICE,
4543 +       },
4544 +};
4545 +
4546 +/* --------------------------------------------------------------------
4547 + *  Clocks
4548 + * -------------------------------------------------------------------- */
4549 +
4550 +/*
4551 + * The peripheral clocks.
4552 + */
4553 +static struct clk pioA_clk = {
4554 +       .name           = "pioA_clk",
4555 +       .pmc_mask       = 1 << AT91SAM9261_ID_PIOA,
4556 +       .type           = CLK_TYPE_PERIPHERAL,
4557 +};
4558 +static struct clk pioB_clk = {
4559 +       .name           = "pioB_clk",
4560 +       .pmc_mask       = 1 << AT91SAM9261_ID_PIOB,
4561 +       .type           = CLK_TYPE_PERIPHERAL,
4562 +};
4563 +static struct clk pioC_clk = {
4564 +       .name           = "pioC_clk",
4565 +       .pmc_mask       = 1 << AT91SAM9261_ID_PIOC,
4566 +       .type           = CLK_TYPE_PERIPHERAL,
4567 +};
4568 +static struct clk usart0_clk = {
4569 +       .name           = "usart0_clk",
4570 +       .pmc_mask       = 1 << AT91SAM9261_ID_US0,
4571 +       .type           = CLK_TYPE_PERIPHERAL,
4572 +};
4573 +static struct clk usart1_clk = {
4574 +       .name           = "usart1_clk",
4575 +       .pmc_mask       = 1 << AT91SAM9261_ID_US1,
4576 +       .type           = CLK_TYPE_PERIPHERAL,
4577 +};
4578 +static struct clk usart2_clk = {
4579 +       .name           = "usart2_clk",
4580 +       .pmc_mask       = 1 << AT91SAM9261_ID_US2,
4581 +       .type           = CLK_TYPE_PERIPHERAL,
4582 +};
4583 +static struct clk mmc_clk = {
4584 +       .name           = "mci_clk",
4585 +       .pmc_mask       = 1 << AT91SAM9261_ID_MCI,
4586 +       .type           = CLK_TYPE_PERIPHERAL,
4587 +};
4588 +static struct clk udc_clk = {
4589 +       .name           = "udc_clk",
4590 +       .pmc_mask       = 1 << AT91SAM9261_ID_UDP,
4591 +       .type           = CLK_TYPE_PERIPHERAL,
4592 +};
4593 +static struct clk twi_clk = {
4594 +       .name           = "twi_clk",
4595 +       .pmc_mask       = 1 << AT91SAM9261_ID_TWI,
4596 +       .type           = CLK_TYPE_PERIPHERAL,
4597 +};
4598 +static struct clk spi0_clk = {
4599 +       .name           = "spi0_clk",
4600 +       .pmc_mask       = 1 << AT91SAM9261_ID_SPI0,
4601 +       .type           = CLK_TYPE_PERIPHERAL,
4602 +};
4603 +static struct clk spi1_clk = {
4604 +       .name           = "spi1_clk",
4605 +       .pmc_mask       = 1 << AT91SAM9261_ID_SPI1,
4606 +       .type           = CLK_TYPE_PERIPHERAL,
4607 +};
4608 +static struct clk ohci_clk = {
4609 +       .name           = "ohci_clk",
4610 +       .pmc_mask       = 1 << AT91SAM9261_ID_UHP,
4611 +       .type           = CLK_TYPE_PERIPHERAL,
4612 +};
4613 +static struct clk lcdc_clk = {
4614 +       .name           = "lcdc_clk",
4615 +       .pmc_mask       = 1 << AT91SAM9261_ID_LCDC,
4616 +       .type           = CLK_TYPE_PERIPHERAL,
4617 +};
4618 +
4619 +static struct clk *periph_clocks[] __initdata = {
4620 +       &pioA_clk,
4621 +       &pioB_clk,
4622 +       &pioC_clk,
4623 +       &usart0_clk,
4624 +       &usart1_clk,
4625 +       &usart2_clk,
4626 +       &mmc_clk,
4627 +       &udc_clk,
4628 +       &twi_clk,
4629 +       &spi0_clk,
4630 +       &spi1_clk,
4631 +       // ssc 0 .. ssc2
4632 +       // tc0 .. tc2
4633 +       &ohci_clk,
4634 +       &lcdc_clk,
4635 +       // irq0 .. irq2
4636 +};
4637 +
4638 +/*
4639 + * The four programmable clocks.
4640 + * You must configure pin multiplexing to bring these signals out.
4641 + */
4642 +static struct clk pck0 = {
4643 +       .name           = "pck0",
4644 +       .pmc_mask       = AT91_PMC_PCK0,
4645 +       .type           = CLK_TYPE_PROGRAMMABLE,
4646 +       .id             = 0,
4647 +};
4648 +static struct clk pck1 = {
4649 +       .name           = "pck1",
4650 +       .pmc_mask       = AT91_PMC_PCK1,
4651 +       .type           = CLK_TYPE_PROGRAMMABLE,
4652 +       .id             = 1,
4653 +};
4654 +static struct clk pck2 = {
4655 +       .name           = "pck2",
4656 +       .pmc_mask       = AT91_PMC_PCK2,
4657 +       .type           = CLK_TYPE_PROGRAMMABLE,
4658 +       .id             = 2,
4659 +};
4660 +static struct clk pck3 = {
4661 +       .name           = "pck3",
4662 +       .pmc_mask       = AT91_PMC_PCK3,
4663 +       .type           = CLK_TYPE_PROGRAMMABLE,
4664 +       .id             = 3,
4665 +};
4666 +
4667 +/* HClocks */
4668 +static struct clk hck0 = {
4669 +       .name           = "hck0",
4670 +       .pmc_mask       = AT91_PMC_HCK0,
4671 +       .type           = CLK_TYPE_SYSTEM,
4672 +       .id             = 0,
4673 +};
4674 +static struct clk hck1 = {
4675 +       .name           = "hck1",
4676 +       .pmc_mask       = AT91_PMC_HCK1,
4677 +       .type           = CLK_TYPE_SYSTEM,
4678 +       .id             = 1,
4679 +};
4680 +
4681 +static void __init at91sam9261_register_clocks(void)
4682 +{
4683 +       int i;
4684 +
4685 +       for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
4686 +               clk_register(periph_clocks[i]);
4687 +
4688 +       clk_register(&pck0);
4689 +       clk_register(&pck1);
4690 +       clk_register(&pck2);
4691 +       clk_register(&pck3);
4692 +
4693 +       clk_register(&hck0);
4694 +       clk_register(&hck1);
4695 +}
4696 +
4697 +/* --------------------------------------------------------------------
4698 + *  GPIO
4699 + * -------------------------------------------------------------------- */
4700 +
4701 +static struct at91_gpio_bank at91sam9261_gpio[] = {
4702 +       {
4703 +               .id             = AT91SAM9261_ID_PIOA,
4704 +               .offset         = AT91_PIOA,
4705 +               .clock          = &pioA_clk,
4706 +       }, {
4707 +               .id             = AT91SAM9261_ID_PIOB,
4708 +               .offset         = AT91_PIOB,
4709 +               .clock          = &pioB_clk,
4710 +       }, {
4711 +               .id             = AT91SAM9261_ID_PIOC,
4712 +               .offset         = AT91_PIOC,
4713 +               .clock          = &pioC_clk,
4714 +       }
4715 +};
4716 +
4717 +static void at91sam9261_reset(void)
4718 +{
4719 +#warning "Implement CPU reset"
4720 +}
4721 +
4722 +
4723 +/* --------------------------------------------------------------------
4724 + *  AT91SAM9261 processor initialization
4725 + * -------------------------------------------------------------------- */
4726 +
4727 +void __init at91sam9261_initialize(unsigned long main_clock)
4728 +{
4729 +       /* Map peripherals */
4730 +       iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
4731 +
4732 +       at91_arch_reset = at91sam9261_reset;
4733 +       at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
4734 +                       | (1 << AT91SAM9261_ID_IRQ2);
4735 +
4736 +       /* Init clock subsystem */
4737 +       at91_clock_init(main_clock);
4738 +
4739 +       /* Register the processor-specific clocks */
4740 +       at91sam9261_register_clocks();
4741 +
4742 +       /* Register GPIO subsystem */
4743 +       at91_gpio_init(at91sam9261_gpio, 3);
4744 +}
4745 +
4746 +/* --------------------------------------------------------------------
4747 + *  Interrupt initialization
4748 + * -------------------------------------------------------------------- */
4749 +
4750 +/*
4751 + * The default interrupt priority levels (0 = lowest, 7 = highest).
4752 + */
4753 +static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
4754 +       7,      /* Advanced Interrupt Controller */
4755 +       7,      /* System Peripherals */
4756 +       0,      /* Parallel IO Controller A */
4757 +       0,      /* Parallel IO Controller B */
4758 +       0,      /* Parallel IO Controller C */
4759 +       0,
4760 +       6,      /* USART 0 */
4761 +       6,      /* USART 1 */
4762 +       6,      /* USART 2 */
4763 +       0,      /* Multimedia Card Interface */
4764 +       4,      /* USB Device Port */
4765 +       0,      /* Two-Wire Interface */
4766 +       6,      /* Serial Peripheral Interface 0 */
4767 +       6,      /* Serial Peripheral Interface 1 */
4768 +       5,      /* Serial Synchronous Controller 0 */
4769 +       5,      /* Serial Synchronous Controller 1 */
4770 +       5,      /* Serial Synchronous Controller 2 */
4771 +       0,      /* Timer Counter 0 */
4772 +       0,      /* Timer Counter 1 */
4773 +       0,      /* Timer Counter 2 */
4774 +       3,      /* USB Host port */
4775 +       3,      /* LCD Controller */
4776 +       0,
4777 +       0,
4778 +       0,
4779 +       0,
4780 +       0,
4781 +       0,
4782 +       0,
4783 +       0,      /* Advanced Interrupt Controller */
4784 +       0,      /* Advanced Interrupt Controller */
4785 +       0,      /* Advanced Interrupt Controller */
4786 +};
4787 +
4788 +void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS])
4789 +{
4790 +       if (!priority)
4791 +               priority = at91sam9261_default_irq_priority;
4792 +
4793 +       /* Initialize the AIC interrupt controller */
4794 +       at91_aic_init(priority);
4795 +
4796 +       /* Enable GPIO interrupts */
4797 +       at91_gpio_irq_setup();
4798 +}
4799 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9261_devices.c linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9261_devices.c
4800 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9261_devices.c   Thu Jan  1 02:00:00 1970
4801 +++ linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9261_devices.c Sat Nov 25 11:14:00 2006
4802 @@ -0,0 +1,767 @@
4803 +/*
4804 + * arch/arm/mach-at91rm9200/at91sam9261_devices.c
4805 + *
4806 + *  Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
4807 + *  Copyright (C) 2005 David Brownell
4808 + *
4809 + * This program is free software; you can redistribute it and/or modify
4810 + * it under the terms of the GNU General Public License as published by
4811 + * the Free Software Foundation; either version 2 of the License, or
4812 + * (at your option) any later version.
4813 + *
4814 + */
4815 +#include <asm/mach/arch.h>
4816 +#include <asm/mach/map.h>
4817 +
4818 +#include <linux/platform_device.h>
4819 +
4820 +#include <asm/arch/board.h>
4821 +#include <asm/arch/gpio.h>
4822 +#include <asm/arch/at91sam9261.h>
4823 +#include <asm/arch/at91sam9261_matrix.h>
4824 +#include <asm/arch/at91sam926x_mc.h>
4825 +
4826 +#include "generic.h"
4827 +
4828 +#define SZ_512 0x00000200
4829 +#define SZ_256 0x00000100
4830 +#define SZ_16  0x00000010
4831 +
4832 +/* --------------------------------------------------------------------
4833 + *  USB Host
4834 + * -------------------------------------------------------------------- */
4835 +
4836 +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
4837 +static u64 ohci_dmamask = 0xffffffffUL;
4838 +static struct at91_usbh_data usbh_data;
4839 +
4840 +static struct resource usbh_resources[] = {
4841 +       [0] = {
4842 +               .start  = AT91SAM9261_UHP_BASE,
4843 +               .end    = AT91SAM9261_UHP_BASE + SZ_1M - 1,
4844 +               .flags  = IORESOURCE_MEM,
4845 +       },
4846 +       [1] = {
4847 +               .start  = AT91SAM9261_ID_UHP,
4848 +               .end    = AT91SAM9261_ID_UHP,
4849 +               .flags  = IORESOURCE_IRQ,
4850 +       },
4851 +};
4852 +
4853 +static struct platform_device at91sam9261_usbh_device = {
4854 +       .name           = "at91_ohci",
4855 +       .id             = -1,
4856 +       .dev            = {
4857 +                               .dma_mask               = &ohci_dmamask,
4858 +                               .coherent_dma_mask      = 0xffffffff,
4859 +                               .platform_data          = &usbh_data,
4860 +       },
4861 +       .resource       = usbh_resources,
4862 +       .num_resources  = ARRAY_SIZE(usbh_resources),
4863 +};
4864 +
4865 +void __init at91_add_device_usbh(struct at91_usbh_data *data)
4866 +{
4867 +       if (!data)
4868 +               return;
4869 +
4870 +       usbh_data = *data;
4871 +       platform_device_register(&at91sam9261_usbh_device);
4872 +}
4873 +#else
4874 +void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
4875 +#endif
4876 +
4877 +
4878 +/* --------------------------------------------------------------------
4879 + *  USB Device (Gadget)
4880 + * -------------------------------------------------------------------- */
4881 +
4882 +#ifdef CONFIG_USB_GADGET_AT91
4883 +static struct at91_udc_data udc_data;
4884 +
4885 +static struct resource udc_resources[] = {
4886 +       [0] = {
4887 +               .start  = AT91SAM9261_BASE_UDP,
4888 +               .end    = AT91SAM9261_BASE_UDP + SZ_16K - 1,
4889 +               .flags  = IORESOURCE_MEM,
4890 +       },
4891 +       [1] = {
4892 +               .start  = AT91SAM9261_ID_UDP,
4893 +               .end    = AT91SAM9261_ID_UDP,
4894 +               .flags  = IORESOURCE_IRQ,
4895 +       },
4896 +};
4897 +
4898 +static struct platform_device at91sam9261_udc_device = {
4899 +       .name           = "at91_udc",
4900 +       .id             = -1,
4901 +       .dev            = {
4902 +                               .platform_data          = &udc_data,
4903 +       },
4904 +       .resource       = udc_resources,
4905 +       .num_resources  = ARRAY_SIZE(udc_resources),
4906 +};
4907 +
4908 +void __init at91_add_device_udc(struct at91_udc_data *data)
4909 +{
4910 +       unsigned long x;
4911 +
4912 +       if (!data)
4913 +               return;
4914 +
4915 +       if (data->vbus_pin) {
4916 +               at91_set_gpio_input(data->vbus_pin, 0);
4917 +               at91_set_deglitch(data->vbus_pin, 1);
4918 +       }
4919 +
4920 +       /* Pullup pin is handled internally */
4921 +       x = at91_sys_read(AT91_MATRIX_USBPUCR);
4922 +       at91_sys_write(AT91_MATRIX_USBPUCR, x | AT91_MATRIX_USBPUCR_PUON);
4923 +
4924 +       udc_data = *data;
4925 +       platform_device_register(&at91sam9261_udc_device);
4926 +}
4927 +#else
4928 +void __init at91_add_device_udc(struct at91_udc_data *data) {}
4929 +#endif
4930 +
4931 +/* --------------------------------------------------------------------
4932 + *  MMC / SD
4933 + * -------------------------------------------------------------------- */
4934 +
4935 +#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
4936 +static u64 mmc_dmamask = 0xffffffffUL;
4937 +static struct at91_mmc_data mmc_data;
4938 +
4939 +static struct resource mmc_resources[] = {
4940 +       [0] = {
4941 +               .start  = AT91SAM9261_BASE_MCI,
4942 +               .end    = AT91SAM9261_BASE_MCI + SZ_16K - 1,
4943 +               .flags  = IORESOURCE_MEM,
4944 +       },
4945 +       [1] = {
4946 +               .start  = AT91SAM9261_ID_MCI,
4947 +               .end    = AT91SAM9261_ID_MCI,
4948 +               .flags  = IORESOURCE_IRQ,
4949 +       },
4950 +};
4951 +
4952 +static struct platform_device at91sam9261_mmc_device = {
4953 +       .name           = "at91_mci",
4954 +       .id             = -1,
4955 +       .dev            = {
4956 +                               .dma_mask               = &mmc_dmamask,
4957 +                               .coherent_dma_mask      = 0xffffffff,
4958 +                               .platform_data          = &mmc_data,
4959 +       },
4960 +       .resource       = mmc_resources,
4961 +       .num_resources  = ARRAY_SIZE(mmc_resources),
4962 +};
4963 +
4964 +void __init at91_add_device_mmc(struct at91_mmc_data *data)
4965 +{
4966 +       if (!data)
4967 +               return;
4968 +
4969 +       /* input/irq */
4970 +       if (data->det_pin) {
4971 +               at91_set_gpio_input(data->det_pin, 1);
4972 +               at91_set_deglitch(data->det_pin, 1);
4973 +       }
4974 +       if (data->wp_pin)
4975 +               at91_set_gpio_input(data->wp_pin, 1);
4976 +       if (data->vcc_pin)
4977 +               at91_set_gpio_output(data->vcc_pin, 0);
4978 +
4979 +       /* CLK */
4980 +       at91_set_B_periph(AT91_PIN_PA2, 0);
4981 +
4982 +       /* CMD */
4983 +       at91_set_B_periph(AT91_PIN_PA1, 1);
4984 +
4985 +       /* DAT0, maybe DAT1..DAT3 */
4986 +       at91_set_B_periph(AT91_PIN_PA0, 1);
4987 +       if (data->wire4) {
4988 +               at91_set_B_periph(AT91_PIN_PA4, 1);
4989 +               at91_set_B_periph(AT91_PIN_PA5, 1);
4990 +               at91_set_B_periph(AT91_PIN_PA6, 1);
4991 +       }
4992 +
4993 +       mmc_data = *data;
4994 +       platform_device_register(&at91sam9261_mmc_device);
4995 +}
4996 +#else
4997 +void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
4998 +#endif
4999 +
5000 +
5001 +/* --------------------------------------------------------------------
5002 + *  NAND / SmartMedia
5003 + * -------------------------------------------------------------------- */
5004 +
5005 +#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
5006 +static struct at91_nand_data nand_data;
5007 +
5008 +#define NAND_BASE      AT91_CHIPSELECT_3
5009 +
5010 +static struct resource nand_resources[] = {
5011 +       {
5012 +               .start  = NAND_BASE,
5013 +               .end    = NAND_BASE + SZ_256M - 1,
5014 +               .flags  = IORESOURCE_MEM,
5015 +       }
5016 +};
5017 +
5018 +static struct platform_device at91_nand_device = {
5019 +       .name           = "at91_nand",
5020 +       .id             = -1,
5021 +       .dev            = {
5022 +                               .platform_data  = &nand_data,
5023 +       },
5024 +       .resource       = nand_resources,
5025 +       .num_resources  = ARRAY_SIZE(nand_resources),
5026 +};
5027 +
5028 +void __init at91_add_device_nand(struct at91_nand_data *data)
5029 +{
5030 +       unsigned long csa, mode;
5031 +
5032 +       if (!data)
5033 +               return;
5034 +
5035 +       csa = at91_sys_read(AT91_MATRIX_EBICSA);
5036 +       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC);
5037 +
5038 +       /* set the bus interface characteristics */
5039 +       at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
5040 +                       | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
5041 +
5042 +       at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
5043 +                       | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
5044 +
5045 +       at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
5046 +
5047 +       if (data->bus_width_16)
5048 +               mode = AT91_SMC_DBW_16;
5049 +       else
5050 +               mode = AT91_SMC_DBW_8;
5051 +       at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
5052 +
5053 +       /* enable pin */
5054 +       if (data->enable_pin)
5055 +               at91_set_gpio_output(data->enable_pin, 1);
5056 +
5057 +       /* ready/busy pin */
5058 +       if (data->rdy_pin)
5059 +               at91_set_gpio_input(data->rdy_pin, 1);
5060 +
5061 +       /* card detect pin */
5062 +       if (data->det_pin)
5063 +               at91_set_gpio_input(data->det_pin, 1);
5064 +
5065 +       at91_set_A_periph(AT91_PIN_PC0, 0);             /* NANDOE */
5066 +       at91_set_A_periph(AT91_PIN_PC1, 0);             /* NANDWE */
5067 +
5068 +       nand_data = *data;
5069 +       platform_device_register(&at91_nand_device);
5070 +}
5071 +
5072 +#else
5073 +void __init at91_add_device_nand(struct at91_nand_data *data) {}
5074 +#endif
5075 +
5076 +
5077 +/* --------------------------------------------------------------------
5078 + *  TWI (i2c)
5079 + * -------------------------------------------------------------------- */
5080 +
5081 +#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
5082 +
5083 +static struct resource twi_resources[] = {
5084 +       [0] = {
5085 +               .start  = AT91SAM9261_BASE_TWI,
5086 +               .end    = AT91SAM9261_BASE_TWI + SZ_16K - 1,
5087 +               .flags  = IORESOURCE_MEM,
5088 +       },
5089 +       [1] = {
5090 +               .start  = AT91SAM9261_ID_TWI,
5091 +               .end    = AT91SAM9261_ID_TWI,
5092 +               .flags  = IORESOURCE_IRQ,
5093 +       },
5094 +};
5095 +
5096 +static struct platform_device at91sam9261_twi_device = {
5097 +       .name           = "at91_i2c",
5098 +       .id             = -1,
5099 +       .resource       = twi_resources,
5100 +       .num_resources  = ARRAY_SIZE(twi_resources),
5101 +};
5102 +
5103 +void __init at91_add_device_i2c(void)
5104 +{
5105 +       /* pins used for TWI interface */
5106 +       at91_set_A_periph(AT91_PIN_PA7, 0);             /* TWD */
5107 +       at91_set_multi_drive(AT91_PIN_PA7, 1);
5108 +
5109 +       at91_set_A_periph(AT91_PIN_PA8, 0);             /* TWCK */
5110 +       at91_set_multi_drive(AT91_PIN_PA8, 1);
5111 +
5112 +       platform_device_register(&at91sam9261_twi_device);
5113 +}
5114 +#else
5115 +void __init at91_add_device_i2c(void) {}
5116 +#endif
5117 +
5118 +
5119 +/* --------------------------------------------------------------------
5120 + *  SPI
5121 + * -------------------------------------------------------------------- */
5122 +
5123 +#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
5124 +static u64 spi_dmamask = 0xffffffffUL;
5125 +
5126 +static struct resource spi0_resources[] = {
5127 +       [0] = {
5128 +               .start  = AT91SAM9261_BASE_SPI0,
5129 +               .end    = AT91SAM9261_BASE_SPI0 + SZ_16K - 1,
5130 +               .flags  = IORESOURCE_MEM,
5131 +       },
5132 +       [1] = {
5133 +               .start  = AT91SAM9261_ID_SPI0,
5134 +               .end    = AT91SAM9261_ID_SPI0,
5135 +               .flags  = IORESOURCE_IRQ,
5136 +       },
5137 +};
5138 +
5139 +static struct platform_device at91sam9261_spi0_device = {
5140 +       .name           = "atmel_spi",
5141 +       .id             = 0,
5142 +       .dev            = {
5143 +                               .dma_mask               = &spi_dmamask,
5144 +                               .coherent_dma_mask      = 0xffffffff,
5145 +       },
5146 +       .resource       = spi0_resources,
5147 +       .num_resources  = ARRAY_SIZE(spi0_resources),
5148 +};
5149 +
5150 +static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
5151 +
5152 +static struct resource spi1_resources[] = {
5153 +       [0] = {
5154 +               .start  = AT91SAM9261_BASE_SPI1,
5155 +               .end    = AT91SAM9261_BASE_SPI1 + SZ_16K - 1,
5156 +               .flags  = IORESOURCE_MEM,
5157 +       },
5158 +       [1] = {
5159 +               .start  = AT91SAM9261_ID_SPI1,
5160 +               .end    = AT91SAM9261_ID_SPI1,
5161 +               .flags  = IORESOURCE_IRQ,
5162 +       },
5163 +};
5164 +
5165 +static struct platform_device at91sam9261_spi1_device = {
5166 +       .name           = "atmel_spi",
5167 +       .id             = 1,
5168 +       .dev            = {
5169 +                               .dma_mask               = &spi_dmamask,
5170 +                               .coherent_dma_mask      = 0xffffffff,
5171 +       },
5172 +       .resource       = spi1_resources,
5173 +       .num_resources  = ARRAY_SIZE(spi1_resources),
5174 +};
5175 +
5176 +static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 };
5177 +
5178 +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
5179 +{
5180 +       int i;
5181 +       unsigned long cs_pin;
5182 +       short enable_spi0 = 0;
5183 +       short enable_spi1 = 0;
5184 +
5185 +       /* Choose SPI chip-selects */
5186 +       for (i = 0; i < nr_devices; i++) {
5187 +               if (devices[i].controller_data)
5188 +                       cs_pin = (unsigned long) devices[i].controller_data;
5189 +               else if (devices[i].bus_num == 0)
5190 +                       cs_pin = spi0_standard_cs[devices[i].chip_select];
5191 +               else
5192 +                       cs_pin = spi1_standard_cs[devices[i].chip_select];
5193 +
5194 +               if (devices[i].bus_num == 0)
5195 +                       enable_spi0 = 1;
5196 +               else
5197 +                       enable_spi1 = 1;
5198 +
5199 +               /* enable chip-select pin */
5200 +               at91_set_gpio_output(cs_pin, 1);
5201 +
5202 +               /* pass chip-select pin to driver */
5203 +               devices[i].controller_data = (void *) cs_pin;
5204 +       }
5205 +
5206 +       spi_register_board_info(devices, nr_devices);
5207 +
5208 +       /* Configure SPI bus(es) */
5209 +       if (enable_spi0) {
5210 +               at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
5211 +               at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
5212 +               at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
5213 +
5214 +               at91_clock_associate("spi0_clk", &at91sam9261_spi0_device.dev, "spi_clk");
5215 +               platform_device_register(&at91sam9261_spi0_device);
5216 +       }
5217 +       if (enable_spi1) {
5218 +               at91_set_A_periph(AT91_PIN_PB30, 0);    /* SPI1_MISO */
5219 +               at91_set_A_periph(AT91_PIN_PB31, 0);    /* SPI1_MOSI */
5220 +               at91_set_A_periph(AT91_PIN_PB29, 0);    /* SPI1_SPCK */
5221 +
5222 +               at91_clock_associate("spi1_clk", &at91sam9261_spi1_device.dev, "spi_clk");
5223 +               platform_device_register(&at91sam9261_spi1_device);
5224 +       }
5225 +}
5226 +#else
5227 +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
5228 +#endif
5229 +
5230 +
5231 +/* --------------------------------------------------------------------
5232 + *  LCD Controller
5233 + * -------------------------------------------------------------------- */
5234 +
5235 +#if defined(CONFIG_FB_AT91) || defined(CONFIG_FB_AT91_MODULE)
5236 +static u64 lcdc_dmamask = 0xffffffffUL;
5237 +static struct at91fb_info lcdc_data;
5238 +
5239 +static struct resource lcdc_resources[] = {
5240 +       [0] = {
5241 +               .start  = AT91SAM9261_LCDC_BASE,
5242 +               .end    = AT91SAM9261_LCDC_BASE + SZ_4K - 1,
5243 +               .flags  = IORESOURCE_MEM,
5244 +       },
5245 +       [1] = {
5246 +               .start  = AT91SAM9261_ID_LCDC,
5247 +               .end    = AT91SAM9261_ID_LCDC,
5248 +               .flags  = IORESOURCE_IRQ,
5249 +       },
5250 +#if defined(CONFIG_FB_INTSRAM)
5251 +       [2] = {
5252 +               .start  = AT91SAM9261_SRAM_BASE,
5253 +               .end    = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1,
5254 +               .flags  = IORESOURCE_MEM,
5255 +       },
5256 +#endif
5257 +};
5258 +
5259 +static struct platform_device at91_lcdc_device = {
5260 +       .name           = "at91-fb",
5261 +       .id             = 0,
5262 +       .dev            = {
5263 +                               .dma_mask               = &lcdc_dmamask,
5264 +                               .coherent_dma_mask      = 0xffffffff,
5265 +                               .platform_data          = &lcdc_data,
5266 +       },
5267 +       .resource       = lcdc_resources,
5268 +       .num_resources  = ARRAY_SIZE(lcdc_resources),
5269 +};
5270 +
5271 +void __init at91_add_device_lcdc(struct at91fb_info *data)
5272 +{
5273 +       if (!data) {
5274 +               return;
5275 +       }
5276 +
5277 +       at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
5278 +       at91_set_A_periph(AT91_PIN_PB2, 0);     /* LCDDOTCK */
5279 +       at91_set_A_periph(AT91_PIN_PB3, 0);     /* LCDDEN */
5280 +       at91_set_A_periph(AT91_PIN_PB4, 0);     /* LCDCC */
5281 +       at91_set_A_periph(AT91_PIN_PB7, 0);     /* LCDD2 */
5282 +       at91_set_A_periph(AT91_PIN_PB8, 0);     /* LCDD3 */
5283 +       at91_set_A_periph(AT91_PIN_PB9, 0);     /* LCDD4 */
5284 +       at91_set_A_periph(AT91_PIN_PB10, 0);    /* LCDD5 */
5285 +       at91_set_A_periph(AT91_PIN_PB11, 0);    /* LCDD6 */
5286 +       at91_set_A_periph(AT91_PIN_PB12, 0);    /* LCDD7 */
5287 +       at91_set_A_periph(AT91_PIN_PB15, 0);    /* LCDD10 */
5288 +       at91_set_A_periph(AT91_PIN_PB16, 0);    /* LCDD11 */
5289 +       at91_set_A_periph(AT91_PIN_PB17, 0);    /* LCDD12 */
5290 +       at91_set_A_periph(AT91_PIN_PB18, 0);    /* LCDD13 */
5291 +       at91_set_A_periph(AT91_PIN_PB19, 0);    /* LCDD14 */
5292 +       at91_set_A_periph(AT91_PIN_PB20, 0);    /* LCDD15 */
5293 +       at91_set_B_periph(AT91_PIN_PB23, 0);    /* LCDD18 */
5294 +       at91_set_B_periph(AT91_PIN_PB24, 0);    /* LCDD19 */
5295 +       at91_set_B_periph(AT91_PIN_PB25, 0);    /* LCDD20 */
5296 +       at91_set_B_periph(AT91_PIN_PB26, 0);    /* LCDD21 */
5297 +       at91_set_B_periph(AT91_PIN_PB27, 0);    /* LCDD22 */
5298 +       at91_set_B_periph(AT91_PIN_PB28, 0);    /* LCDD23 */
5299 +
5300 +       lcdc_data = *data;
5301 +       platform_device_register(&at91_lcdc_device);
5302 +}
5303 +#else
5304 +void __init at91_add_device_lcdc(struct at91fb_info *data) {}
5305 +#endif
5306 +
5307 +
5308 +/* --------------------------------------------------------------------
5309 + *  LEDs
5310 + * -------------------------------------------------------------------- */
5311 +
5312 +#if defined(CONFIG_LEDS)
5313 +u8 at91_leds_cpu;
5314 +u8 at91_leds_timer;
5315 +
5316 +void __init at91_init_leds(u8 cpu_led, u8 timer_led)
5317 +{
5318 +       at91_leds_cpu   = cpu_led;
5319 +       at91_leds_timer = timer_led;
5320 +}
5321 +#else
5322 +void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
5323 +#endif
5324 +
5325 +
5326 +#if defined(CONFIG_NEW_LEDS)
5327 +
5328 +static struct platform_device at91_leds = {
5329 +       .name           = "at91_leds",
5330 +       .id             = -1,
5331 +};
5332 +
5333 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
5334 +{
5335 +       if (!nr)
5336 +               return;
5337 +
5338 +       at91_leds.dev.platform_data = leds;
5339 +
5340 +       for ( ; nr; nr--, leds++) {
5341 +               leds->index = nr;       /* first record stores number of leds */
5342 +               at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
5343 +       }
5344 +
5345 +       platform_device_register(&at91_leds);
5346 +}
5347 +#else
5348 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
5349 +#endif
5350 +
5351 +
5352 +/* --------------------------------------------------------------------
5353 + *  UART
5354 + * -------------------------------------------------------------------- */
5355 +
5356 +#if defined(CONFIG_SERIAL_ATMEL)
5357 +static struct resource dbgu_resources[] = {
5358 +       [0] = {
5359 +               .start  = AT91_VA_BASE_SYS + AT91_DBGU,
5360 +               .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
5361 +               .flags  = IORESOURCE_MEM,
5362 +       },
5363 +       [1] = {
5364 +               .start  = AT91_ID_SYS,
5365 +               .end    = AT91_ID_SYS,
5366 +               .flags  = IORESOURCE_IRQ,
5367 +       },
5368 +};
5369 +
5370 +static struct atmel_uart_data dbgu_data = {
5371 +       .use_dma_tx     = 0,
5372 +       .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
5373 +       .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
5374 +};
5375 +
5376 +static struct platform_device at91sam9261_dbgu_device = {
5377 +       .name           = "atmel_usart",
5378 +       .id             = 0,
5379 +       .dev            = {
5380 +                               .platform_data  = &dbgu_data,
5381 +                               .coherent_dma_mask = 0xffffffff,
5382 +       },
5383 +       .resource       = dbgu_resources,
5384 +       .num_resources  = ARRAY_SIZE(dbgu_resources),
5385 +};
5386 +
5387 +static inline void configure_dbgu_pins(void)
5388 +{
5389 +       at91_set_A_periph(AT91_PIN_PA9, 0);             /* DRXD */
5390 +       at91_set_A_periph(AT91_PIN_PA10, 1);            /* DTXD */
5391 +}
5392 +
5393 +static struct resource uart0_resources[] = {
5394 +       [0] = {
5395 +               .start  = AT91SAM9261_BASE_US0,
5396 +               .end    = AT91SAM9261_BASE_US0 + SZ_16K - 1,
5397 +               .flags  = IORESOURCE_MEM,
5398 +       },
5399 +       [1] = {
5400 +               .start  = AT91SAM9261_ID_US0,
5401 +               .end    = AT91SAM9261_ID_US0,
5402 +               .flags  = IORESOURCE_IRQ,
5403 +       },
5404 +};
5405 +
5406 +static struct atmel_uart_data uart0_data = {
5407 +       .use_dma_tx     = 1,
5408 +       .use_dma_rx     = 1,
5409 +};
5410 +
5411 +static struct platform_device at91sam9261_uart0_device = {
5412 +       .name           = "atmel_usart",
5413 +       .id             = 1,
5414 +       .dev            = {
5415 +                               .platform_data  = &uart0_data,
5416 +                               .coherent_dma_mask = 0xffffffff,
5417 +       },
5418 +       .resource       = uart0_resources,
5419 +       .num_resources  = ARRAY_SIZE(uart0_resources),
5420 +};
5421 +
5422 +static inline void configure_usart0_pins(void)
5423 +{
5424 +       at91_set_A_periph(AT91_PIN_PC8, 1);             /* TXD0 */
5425 +       at91_set_A_periph(AT91_PIN_PC9, 0);             /* RXD0 */
5426 +       at91_set_A_periph(AT91_PIN_PC10, 0);            /* RTS0 */
5427 +       at91_set_A_periph(AT91_PIN_PC11, 0);            /* CTS0 */
5428 +}
5429 +
5430 +static struct resource uart1_resources[] = {
5431 +       [0] = {
5432 +               .start  = AT91SAM9261_BASE_US1,
5433 +               .end    = AT91SAM9261_BASE_US1 + SZ_16K - 1,
5434 +               .flags  = IORESOURCE_MEM,
5435 +       },
5436 +       [1] = {
5437 +               .start  = AT91SAM9261_ID_US1,
5438 +               .end    = AT91SAM9261_ID_US1,
5439 +               .flags  = IORESOURCE_IRQ,
5440 +       },
5441 +};
5442 +
5443 +static struct atmel_uart_data uart1_data = {
5444 +       .use_dma_tx     = 1,
5445 +       .use_dma_rx     = 1,
5446 +};
5447 +
5448 +static struct platform_device at91sam9261_uart1_device = {
5449 +       .name           = "atmel_usart",
5450 +       .id             = 2,
5451 +       .dev            = {
5452 +                               .platform_data  = &uart1_data,
5453 +                               .coherent_dma_mask = 0xffffffff,
5454 +       },
5455 +       .resource       = uart1_resources,
5456 +       .num_resources  = ARRAY_SIZE(uart1_resources),
5457 +};
5458 +
5459 +static inline void configure_usart1_pins(void)
5460 +{
5461 +       at91_set_A_periph(AT91_PIN_PC12, 1);            /* TXD1 */
5462 +       at91_set_A_periph(AT91_PIN_PC13, 0);            /* RXD1 */
5463 +}
5464 +
5465 +static struct resource uart2_resources[] = {
5466 +       [0] = {
5467 +               .start  = AT91SAM9261_BASE_US2,
5468 +               .end    = AT91SAM9261_BASE_US2 + SZ_16K - 1,
5469 +               .flags  = IORESOURCE_MEM,
5470 +       },
5471 +       [1] = {
5472 +               .start  = AT91SAM9261_ID_US2,
5473 +               .end    = AT91SAM9261_ID_US2,
5474 +               .flags  = IORESOURCE_IRQ,
5475 +       },
5476 +};
5477 +
5478 +static struct atmel_uart_data uart2_data = {
5479 +       .use_dma_tx     = 1,
5480 +       .use_dma_rx     = 1,
5481 +};
5482 +
5483 +static struct platform_device at91sam9261_uart2_device = {
5484 +       .name           = "atmel_usart",
5485 +       .id             = 3,
5486 +       .dev            = {
5487 +                               .platform_data  = &uart2_data,
5488 +                               .coherent_dma_mask = 0xffffffff,
5489 +       },
5490 +       .resource       = uart2_resources,
5491 +       .num_resources  = ARRAY_SIZE(uart2_resources),
5492 +};
5493 +
5494 +static inline void configure_usart2_pins(void)
5495 +{
5496 +       at91_set_A_periph(AT91_PIN_PC15, 0);            /* RXD2 */
5497 +       at91_set_A_periph(AT91_PIN_PC14, 1);            /* TXD2 */
5498 +}
5499 +
5500 +struct platform_device *at91_uarts[ATMEL_MAX_UART];    /* the UARTs to use */
5501 +struct platform_device *atmel_default_console_device;  /* the serial console device */
5502 +
5503 +void __init at91_init_serial(struct at91_uart_config *config)
5504 +{
5505 +       int i;
5506 +
5507 +       /* Fill in list of supported UARTs */
5508 +       for (i = 0; i < config->nr_tty; i++) {
5509 +               switch (config->tty_map[i]) {
5510 +                       case 0:
5511 +                               configure_usart0_pins();
5512 +                               at91_uarts[i] = &at91sam9261_uart0_device;
5513 +                               at91_clock_associate("usart0_clk", &at91sam9261_uart0_device.dev, "usart");
5514 +                               break;
5515 +                       case 1:
5516 +                               configure_usart1_pins();
5517 +                               at91_uarts[i] = &at91sam9261_uart1_device;
5518 +                               at91_clock_associate("usart1_clk", &at91sam9261_uart1_device.dev, "usart");
5519 +                               break;
5520 +                       case 2:
5521 +                               configure_usart2_pins();
5522 +                               at91_uarts[i] = &at91sam9261_uart2_device;
5523 +                               at91_clock_associate("usart2_clk", &at91sam9261_uart2_device.dev, "usart");
5524 +                               break;
5525 +                       case 3:
5526 +                               configure_dbgu_pins();
5527 +                               at91_uarts[i] = &at91sam9261_dbgu_device;
5528 +                               at91_clock_associate("mck", &at91sam9261_dbgu_device.dev, "usart");
5529 +                               break;
5530 +                       default:
5531 +                               continue;
5532 +               }
5533 +               at91_uarts[i]->id = i;          /* update ID number to mapped ID */
5534 +       }
5535 +
5536 +       /* Set serial console device */
5537 +       if (config->console_tty < ATMEL_MAX_UART)
5538 +               atmel_default_console_device = at91_uarts[config->console_tty];
5539 +       if (!atmel_default_console_device)
5540 +               printk(KERN_INFO "AT91: No default serial console defined.\n");
5541 +}
5542 +
5543 +void __init at91_add_device_serial(void)
5544 +{
5545 +       int i;
5546 +
5547 +       for (i = 0; i < ATMEL_MAX_UART; i++) {
5548 +               if (at91_uarts[i])
5549 +                       platform_device_register(at91_uarts[i]);
5550 +       }
5551 +}
5552 +#else
5553 +void __init at91_init_serial(struct at91_uart_config *config) {}
5554 +void __init at91_add_device_serial(void) {}
5555 +#endif
5556 +
5557 +
5558 +/* -------------------------------------------------------------------- */
5559 +
5560 +/*
5561 + * These devices are always present and don't need any board-specific
5562 + * setup.
5563 + */
5564 +static int __init at91_add_standard_devices(void)
5565 +{
5566 +       return 0;
5567 +}
5568 +
5569 +arch_initcall(at91_add_standard_devices);
5570 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam926x_time.c linux-2.6.19/arch/arm/mach-at91rm9200/at91sam926x_time.c
5571 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam926x_time.c      Thu Jan  1 02:00:00 1970
5572 +++ linux-2.6.19/arch/arm/mach-at91rm9200/at91sam926x_time.c    Mon Nov 20 10:52:16 2006
5573 @@ -0,0 +1,114 @@
5574 +/*
5575 + * linux/arch/arm/mach-at91rm9200/at91sam926x_time.c
5576 + *
5577 + * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
5578 + * Revision     2005 M. Nicolas Diremdjian, ATMEL Rousset, France
5579 + *
5580 + * This program is free software; you can redistribute it and/or modify
5581 + * it under the terms of the GNU General Public License version 2 as
5582 + * published by the Free Software Foundation.
5583 + */
5584 +
5585 +#include <linux/init.h>
5586 +#include <linux/interrupt.h>
5587 +#include <linux/irq.h>
5588 +#include <linux/kernel.h>
5589 +#include <linux/sched.h>
5590 +#include <linux/time.h>
5591 +
5592 +#include <asm/hardware.h>
5593 +#include <asm/io.h>
5594 +#include <asm/mach/time.h>
5595 +
5596 +#include <asm/arch/at91_pit.h>
5597 +
5598 +
5599 +#define PIT_CPIV(x)    ((x) & AT91_PIT_CPIV)
5600 +#define PIT_PICNT(x)   (((x) & AT91_PIT_PICNT) >> 20)
5601 +
5602 +/*
5603 + * Returns number of microseconds since last timer interrupt.  Note that interrupts
5604 + * will have been disabled by do_gettimeofday()
5605 + *  'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
5606 + *  'tick' is usecs per jiffy (linux/timex.h).
5607 + */
5608 +static unsigned long at91sam926x_gettimeoffset(void)
5609 +{
5610 +       unsigned long elapsed;
5611 +       unsigned long t = at91_sys_read(AT91_PIT_PIIR);
5612 +
5613 +       elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t);         /* hardware clock cycles */
5614 +
5615 +       return (unsigned long)(elapsed * 1000000) / LATCH;
5616 +}
5617 +
5618 +/*
5619 + * IRQ handler for the timer.
5620 + */
5621 +static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
5622 +{
5623 +       volatile long nr_ticks;
5624 +
5625 +       if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) {       /* This is a shared interrupt */
5626 +               write_seqlock(&xtime_lock);
5627 +
5628 +               /* Get number to ticks performed before interrupt and clear PIT interrupt */
5629 +               nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
5630 +               do {
5631 +                       timer_tick();
5632 +                       nr_ticks--;
5633 +               } while (nr_ticks);
5634 +
5635 +               write_sequnlock(&xtime_lock);
5636 +               return IRQ_HANDLED;
5637 +       } else
5638 +               return IRQ_NONE;                /* not handled */
5639 +}
5640 +
5641 +static struct irqaction at91sam926x_timer_irq = {
5642 +       .name           = "at91_tick",
5643 +       .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER,
5644 +       .handler        = at91sam926x_timer_interrupt
5645 +};
5646 +
5647 +void at91sam926x_timer_reset(void)
5648 +{
5649 +       /* Disable timer */
5650 +       at91_sys_write(AT91_PIT_MR, 0);
5651 +
5652 +       /* Clear any pending interrupts */
5653 +       (void) at91_sys_read(AT91_PIT_PIVR);
5654 +
5655 +       /* Set Period Interval timer and enable its interrupt */
5656 +       at91_sys_write(AT91_PIT_MR, (LATCH & AT91_PIT_PIV) | AT91_PIT_PITIEN | AT91_PIT_PITEN);
5657 +}
5658 +
5659 +/*
5660 + * Set up timer interrupt.
5661 + */
5662 +void __init at91sam926x_timer_init(void)
5663 +{
5664 +       /* Initialize and enable the timer */
5665 +       at91sam926x_timer_reset();
5666 +
5667 +       /* Make IRQs happen for the system timer. */
5668 +       setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq);
5669 +}
5670 +
5671 +#ifdef CONFIG_PM
5672 +static void at91sam926x_timer_suspend(void)
5673 +{
5674 +       /* Disable timer */
5675 +       at91_sys_write(AT91_PIT_MR, 0);
5676 +}
5677 +#else
5678 +#define at91sam926x_timer_suspend      NULL
5679 +#endif
5680 +
5681 +struct sys_timer at91sam926x_timer = {
5682 +       .init           = at91sam926x_timer_init,
5683 +       .offset         = at91sam926x_gettimeoffset,
5684 +       .suspend        = at91sam926x_timer_suspend,
5685 +       .resume         = at91sam926x_timer_reset,
5686 +};
5687 +
5688 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-1arm.c linux-2.6.19/arch/arm/mach-at91rm9200/board-1arm.c
5689 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-1arm.c    Mon Dec  4 16:39:29 2006
5690 +++ linux-2.6.19/arch/arm/mach-at91rm9200/board-1arm.c  Thu Nov 23 15:50:12 2006
5691 @@ -64,7 +64,7 @@
5692         at91rm9200_init_interrupts(NULL);
5693  }
5694
5695 -static struct at91_eth_data __initdata onearm_eth_data = {
5696 +static struct eth_platform_data __initdata onearm_eth_data = {
5697         .phy_irq_pin    = AT91_PIN_PC4,
5698         .is_rmii        = 1,
5699  };
5700 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-carmeva.c linux-2.6.19/arch/arm/mach-at91rm9200/board-carmeva.c
5701 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-carmeva.c Mon Dec  4 16:39:29 2006
5702 +++ linux-2.6.19/arch/arm/mach-at91rm9200/board-carmeva.c       Thu Nov 23 15:50:12 2006
5703 @@ -65,8 +65,7 @@
5704         at91rm9200_init_interrupts(NULL);
5705  }
5706
5707 -
5708 -static struct at91_eth_data __initdata carmeva_eth_data = {
5709 +static struct eth_platform_data __initdata carmeva_eth_data = {
5710         .phy_irq_pin    = AT91_PIN_PC4,
5711         .is_rmii        = 1,
5712  };
5713 @@ -89,8 +88,33 @@
5714  // };
5715
5716  static struct at91_mmc_data __initdata carmeva_mmc_data = {
5717 -       .is_b           = 0,
5718 +       .slot_b         = 0,
5719         .wire4          = 1,
5720 +       .det_pin        = AT91_PIN_PB10,
5721 +       .wp_pin         = AT91_PIN_PC14,
5722 +};
5723 +
5724 +static struct spi_board_info carmeva_spi_devices[] = {
5725 +       { /* DataFlash chip */
5726 +               .modalias = "mtd_dataflash",
5727 +               .chip_select  = 0,
5728 +               .max_speed_hz = 10 * 1000 * 1000,
5729 +       },
5730 +       { /* User accessable spi - cs1 (250KHz) */
5731 +               .modalias = "spi-cs1",
5732 +               .chip_select  = 1,
5733 +               .max_speed_hz = 250 *  1000,
5734 +       },
5735 +       { /* User accessable spi - cs2 (1MHz) */
5736 +               .modalias = "spi-cs2",
5737 +               .chip_select  = 2,
5738 +               .max_speed_hz = 1 * 1000 *  1000,
5739 +       },
5740 +       { /* User accessable spi - cs3 (10MHz) */
5741 +               .modalias = "spi-cs3",
5742 +               .chip_select  = 3,
5743 +               .max_speed_hz = 10 * 1000 *  1000,
5744 +       },
5745  };
5746
5747  static void __init carmeva_board_init(void)
5748 @@ -105,10 +129,10 @@
5749         at91_add_device_udc(&carmeva_udc_data);
5750         /* I2C */
5751         at91_add_device_i2c();
5752 +       /* SPI */
5753 +       at91_add_device_spi(carmeva_spi_devices, ARRAY_SIZE(carmeva_spi_devices));
5754         /* Compact Flash */
5755  //     at91_add_device_cf(&carmeva_cf_data);
5756 -       /* SPI */
5757 -//     at91_add_device_spi(NULL, 0);
5758         /* MMC */
5759         at91_add_device_mmc(&carmeva_mmc_data);
5760  }
5761 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-csb337.c linux-2.6.19/arch/arm/mach-at91rm9200/board-csb337.c
5762 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-csb337.c  Mon Dec  4 16:39:29 2006
5763 +++ linux-2.6.19/arch/arm/mach-at91rm9200/board-csb337.c        Thu Nov 23 15:50:12 2006
5764 @@ -68,7 +68,7 @@
5765         at91rm9200_init_interrupts(NULL);
5766  }
5767
5768 -static struct at91_eth_data __initdata csb337_eth_data = {
5769 +static struct eth_platform_data __initdata csb337_eth_data = {
5770         .phy_irq_pin    = AT91_PIN_PC2,
5771         .is_rmii        = 0,
5772  };
5773 @@ -99,7 +99,7 @@
5774
5775  static struct at91_mmc_data __initdata csb337_mmc_data = {
5776         .det_pin        = AT91_PIN_PD5,
5777 -       .is_b           = 0,
5778 +       .slot_b         = 0,
5779         .wire4          = 1,
5780         .wp_pin         = AT91_PIN_PD6,
5781  };
5782 @@ -112,6 +112,23 @@
5783         },
5784  };
5785
5786 +static struct at91_gpio_led csb337_leds[] = {
5787 +       {
5788 +               .name           = "led0",
5789 +               .gpio           = AT91_PIN_PB0,
5790 +               .trigger        = "heartbeat",
5791 +       },
5792 +       {
5793 +               .name           = "led1",
5794 +               .gpio           = AT91_PIN_PB1,
5795 +               .trigger        = "timer",
5796 +       },
5797 +       {
5798 +               .name           = "led2",
5799 +               .gpio           = AT91_PIN_PB2,
5800 +       }
5801 +};
5802 +
5803  static void __init csb337_board_init(void)
5804  {
5805         /* Serial */
5806 @@ -131,6 +148,8 @@
5807         at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices));
5808         /* MMC */
5809         at91_add_device_mmc(&csb337_mmc_data);
5810 +       /* LEDS */
5811 +       at91_gpio_leds(csb337_leds, ARRAY_SIZE(csb337_leds));
5812  }
5813
5814  MACHINE_START(CSB337, "Cogent CSB337")
5815 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-csb637.c linux-2.6.19/arch/arm/mach-at91rm9200/board-csb637.c
5816 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-csb637.c  Mon Dec  4 16:39:29 2006
5817 +++ linux-2.6.19/arch/arm/mach-at91rm9200/board-csb637.c        Thu Nov 23 15:50:12 2006
5818 @@ -67,7 +67,7 @@
5819         at91rm9200_init_interrupts(NULL);
5820  }
5821
5822 -static struct at91_eth_data __initdata csb637_eth_data = {
5823 +static struct eth_platform_data __initdata csb637_eth_data = {
5824         .phy_irq_pin    = AT91_PIN_PC0,
5825         .is_rmii        = 0,
5826  };
5827 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-dk.c linux-2.6.19/arch/arm/mach-at91rm9200/board-dk.c
5828 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-dk.c      Mon Dec  4 16:39:29 2006
5829 +++ linux-2.6.19/arch/arm/mach-at91rm9200/board-dk.c    Thu Nov 23 15:50:12 2006
5830 @@ -27,6 +27,7 @@
5831  #include <linux/module.h>
5832  #include <linux/platform_device.h>
5833  #include <linux/spi/spi.h>
5834 +#include <linux/mtd/physmap.h>
5835
5836  #include <asm/hardware.h>
5837  #include <asm/setup.h>
5838 @@ -39,6 +40,7 @@
5839
5840  #include <asm/arch/board.h>
5841  #include <asm/arch/gpio.h>
5842 +#include <asm/arch/at91rm9200_mc.h>
5843
5844  #include "generic.h"
5845
5846 @@ -71,7 +73,186 @@
5847         at91rm9200_init_interrupts(NULL);
5848  }
5849
5850 -static struct at91_eth_data __initdata dk_eth_data = {
5851 +#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
5852 +#include <video/s1d13xxxfb.h>
5853 +#include <asm/arch/ics1523.h>
5854 +
5855 +/* EPSON S1D13806 FB */
5856 +#define AT91_FB_REG_BASE       0x30000000L
5857 +#define AT91_FB_REG_SIZE       0x200
5858 +#define AT91_FB_VMEM_BASE      0x30200000L
5859 +#define AT91_FB_VMEM_SIZE      0x140000L
5860 +
5861 +static void __init dk_init_video(void)
5862 +{
5863 +       /* NWAIT Signal */
5864 +       at91_set_A_periph(AT91_PIN_PC6, 0);
5865 +
5866 +       /* Initialization of the Static Memory Controller for Chip Select 2 */
5867 +       at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16                 /* 16 bit */
5868 +                               | AT91_SMC_WSEN | AT91_SMC_NWS_(4)      /* wait states */
5869 +                               | AT91_SMC_TDF_(1)                      /* float time */
5870 +       );
5871 +
5872 +       AT91F_ICS1523_clockinit();
5873 +}
5874 +
5875 +/* CRT:    (active)   640x480 60Hz (PCLK=CLKI=25.175MHz)
5876 +   Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz) */
5877 +static const struct s1d13xxxfb_regval dk_s1dfb_initregs[] = {
5878 +       {S1DREG_MISC,                   0x00},  /* Enable Memory/Register select bit */
5879 +       {S1DREG_COM_DISP_MODE,          0x00},  /* disable display output */
5880 +       {S1DREG_GPIO_CNF0,              0x00},
5881 +       {S1DREG_GPIO_CNF1,              0x00},
5882 +       {S1DREG_GPIO_CTL0,              0x08},
5883 +       {S1DREG_GPIO_CTL1,              0x00},
5884 +       {S1DREG_CLK_CNF,                0x01},  /* no divide, MCLK source is CLKI3 0x02*/
5885 +       {S1DREG_LCD_CLK_CNF,            0x00},
5886 +       {S1DREG_CRT_CLK_CNF,            0x00},
5887 +       {S1DREG_MPLUG_CLK_CNF,          0x00},
5888 +       {S1DREG_CPU2MEM_WST_SEL,        0x01},  /* 2*period(MCLK) - 4ns > period(BCLK) */
5889 +       {S1DREG_SDRAM_REF_RATE,         0x03},  /* 32768 <= MCLK <= 50000 (MHz) */
5890 +       {S1DREG_SDRAM_TC0,              0x00},  /* MCLK source freq (MHz): */
5891 +       {S1DREG_SDRAM_TC1,              0x01},  /* 42 <= MCLK <= 50 */
5892 +       {S1DREG_MEM_CNF,                0x80},  /* SDRAM Initialization - needed before mem access */
5893 +       {S1DREG_PANEL_TYPE,             0x25},  /* std TFT 16bit, 8bit SCP format 2, single passive LCD */
5894 +       {S1DREG_MOD_RATE,               0x00},  /* toggle every FPFRAME */
5895 +       {S1DREG_LCD_DISP_HWIDTH,        0x4F},  /* 680 pix */
5896 +       {S1DREG_LCD_NDISP_HPER,         0x12},  /* 152 pix */
5897 +       {S1DREG_TFT_FPLINE_START,       0x01},  /* 13 pix */
5898 +       {S1DREG_TFT_FPLINE_PWIDTH,      0x0B},  /* 96 pix */
5899 +       {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},
5900 +       {S1DREG_LCD_DISP_VHEIGHT1,      0x01},  /* 480 lines */
5901 +       {S1DREG_LCD_NDISP_VPER,         0x2C},  /* 44 lines */
5902 +       {S1DREG_TFT_FPFRAME_START,      0x0A},  /* 10 lines */
5903 +       {S1DREG_TFT_FPFRAME_PWIDTH,     0x01},  /* 2 lines */
5904 +       {S1DREG_LCD_DISP_MODE,          0x05},  /* 16 bpp */
5905 +       {S1DREG_LCD_MISC,               0x00},  /* dithering enabled, dual panel buffer enabled */
5906 +       {S1DREG_LCD_DISP_START0,        0x00},
5907 +       {S1DREG_LCD_DISP_START1,        0xC8},
5908 +       {S1DREG_LCD_DISP_START2,        0x00},
5909 +       {S1DREG_LCD_MEM_OFF0,           0x80},
5910 +       {S1DREG_LCD_MEM_OFF1,           0x02},
5911 +       {S1DREG_LCD_PIX_PAN,            0x00},
5912 +       {S1DREG_LCD_DISP_FIFO_HTC,      0x3B},
5913 +       {S1DREG_LCD_DISP_FIFO_LTC,      0x3C},
5914 +       {S1DREG_CRT_DISP_HWIDTH,        0x4F},  /* 680 pix */
5915 +       {S1DREG_CRT_NDISP_HPER,         0x13},  /* 160 pix */
5916 +       {S1DREG_CRT_HRTC_START,         0x01},  /* 13 pix */
5917 +       {S1DREG_CRT_HRTC_PWIDTH,        0x0B},  /* 96 pix */
5918 +       {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},
5919 +       {S1DREG_CRT_DISP_VHEIGHT1,      0x01},  /* 480 lines */
5920 +       {S1DREG_CRT_NDISP_VPER,         0x2B},  /* 44 lines */
5921 +       {S1DREG_CRT_VRTC_START,         0x09},  /* 10 lines */
5922 +       {S1DREG_CRT_VRTC_PWIDTH,        0x01},  /* 2 lines */
5923 +       {S1DREG_TV_OUT_CTL,             0x10},
5924 +       {S1DREG_CRT_DISP_MODE,          0x05},  /* 16 bpp */
5925 +       {S1DREG_CRT_DISP_START0,        0x00},
5926 +       {S1DREG_CRT_DISP_START1,        0x00},
5927 +       {S1DREG_CRT_DISP_START2,        0x00},
5928 +       {S1DREG_CRT_MEM_OFF0,           0x80},
5929 +       {S1DREG_CRT_MEM_OFF1,           0x02},
5930 +       {S1DREG_CRT_PIX_PAN,            0x00},
5931 +       {S1DREG_CRT_DISP_FIFO_HTC,      0x3B},
5932 +       {S1DREG_CRT_DISP_FIFO_LTC,      0x3C},
5933 +       {S1DREG_LCD_CUR_CTL,            0x00},  /* inactive */
5934 +       {S1DREG_LCD_CUR_START,          0x01},
5935 +       {S1DREG_LCD_CUR_XPOS0,          0x00},
5936 +       {S1DREG_LCD_CUR_XPOS1,          0x00},
5937 +       {S1DREG_LCD_CUR_YPOS0,          0x00},
5938 +       {S1DREG_LCD_CUR_YPOS1,          0x00},
5939 +       {S1DREG_LCD_CUR_BCTL0,          0x00},
5940 +       {S1DREG_LCD_CUR_GCTL0,          0x00},
5941 +       {S1DREG_LCD_CUR_RCTL0,          0x00},
5942 +       {S1DREG_LCD_CUR_BCTL1,          0x1F},
5943 +       {S1DREG_LCD_CUR_GCTL1,          0x3F},
5944 +       {S1DREG_LCD_CUR_RCTL1,          0x1F},
5945 +       {S1DREG_LCD_CUR_FIFO_HTC,       0x00},
5946 +       {S1DREG_CRT_CUR_CTL,            0x00},  /* inactive */
5947 +       {S1DREG_CRT_CUR_START,          0x01},
5948 +       {S1DREG_CRT_CUR_XPOS0,          0x00},
5949 +       {S1DREG_CRT_CUR_XPOS1,          0x00},
5950 +       {S1DREG_CRT_CUR_YPOS0,          0x00},
5951 +       {S1DREG_CRT_CUR_YPOS1,          0x00},
5952 +       {S1DREG_CRT_CUR_BCTL0,          0x00},
5953 +       {S1DREG_CRT_CUR_GCTL0,          0x00},
5954 +       {S1DREG_CRT_CUR_RCTL0,          0x00},
5955 +       {S1DREG_CRT_CUR_BCTL1,          0x1F},
5956 +       {S1DREG_CRT_CUR_GCTL1,          0x3F},
5957 +       {S1DREG_CRT_CUR_RCTL1,          0x1F},
5958 +       {S1DREG_CRT_CUR_FIFO_HTC,       0x00},
5959 +       {S1DREG_BBLT_CTL0,              0x00},
5960 +       {S1DREG_BBLT_CTL0,              0x00},
5961 +       {S1DREG_BBLT_CC_EXP,            0x00},
5962 +       {S1DREG_BBLT_OP,                0x00},
5963 +       {S1DREG_BBLT_SRC_START0,        0x00},
5964 +       {S1DREG_BBLT_SRC_START1,        0x00},
5965 +       {S1DREG_BBLT_SRC_START2,        0x00},
5966 +       {S1DREG_BBLT_DST_START0,        0x00},
5967 +       {S1DREG_BBLT_DST_START1,        0x00},
5968 +       {S1DREG_BBLT_DST_START2,        0x00},
5969 +       {S1DREG_BBLT_MEM_OFF0,          0x00},
5970 +       {S1DREG_BBLT_MEM_OFF1,          0x00},
5971 +       {S1DREG_BBLT_WIDTH0,            0x00},
5972 +       {S1DREG_BBLT_WIDTH1,            0x00},
5973 +       {S1DREG_BBLT_HEIGHT0,           0x00},
5974 +       {S1DREG_BBLT_HEIGHT1,           0x00},
5975 +       {S1DREG_BBLT_BGC0,              0x00},
5976 +       {S1DREG_BBLT_BGC1,              0x00},
5977 +       {S1DREG_BBLT_FGC0,              0x00},
5978 +       {S1DREG_BBLT_FGC1,              0x00},
5979 +       {S1DREG_LKUP_MODE,              0x00},  /* LCD LUT r | LCD and CRT/TV LUT w */
5980 +       {S1DREG_LKUP_ADDR,              0x00},
5981 +       {S1DREG_PS_CNF,                 0x00},  /* Power Save disable */
5982 +       {S1DREG_PS_STATUS,              0x02},  /* LCD Panel down, mem up */
5983 +       {S1DREG_CPU2MEM_WDOGT,          0x00},
5984 +       {S1DREG_COM_DISP_MODE,          0x02},  /* enable CRT display output */
5985 +};
5986 +
5987 +static struct s1d13xxxfb_pdata dk_s1dfb_pdata = {
5988 +       .initregs               = dk_s1dfb_initregs,
5989 +       .initregssize           = ARRAY_SIZE(dk_s1dfb_initregs),
5990 +       .platform_init_video    = dk_init_video,
5991 +};
5992 +
5993 +static u64 s1dfb_dmamask = 0xffffffffUL;
5994 +
5995 +static struct resource dk_s1dfb_resource[] = {
5996 +       [0] = { /* video mem */
5997 +               .name   = "s1d13806 memory",
5998 +               .start  = AT91_FB_VMEM_BASE,
5999 +               .end    = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
6000 +               .flags  = IORESOURCE_MEM,
6001 +       },
6002 +       [1] = { /* video registers */
6003 +               .name   = "s1d13806 registers",
6004 +               .start  = AT91_FB_REG_BASE,
6005 +               .end    = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
6006 +               .flags  = IORESOURCE_MEM,
6007 +       },
6008 +};
6009 +
6010 +static struct platform_device dk_s1dfb_device = {
6011 +       .name           = "s1d13806fb",
6012 +       .id             = -1,
6013 +       .dev            = {
6014 +                       .dma_mask               = &s1dfb_dmamask,
6015 +                       .coherent_dma_mask      = 0xffffffff,
6016 +                       .platform_data          = &dk_s1dfb_pdata,
6017 +       },
6018 +       .resource       = dk_s1dfb_resource,
6019 +       .num_resources  = ARRAY_SIZE(dk_s1dfb_resource),
6020 +};
6021 +
6022 +static void __init dk_add_device_video(void)
6023 +{
6024 +       platform_device_register(&dk_s1dfb_device);
6025 +}
6026 +#else
6027 +static void __init dk_add_device_video(void) {}
6028 +#endif
6029 +
6030 +static struct eth_platform_data __initdata dk_eth_data = {
6031         .phy_irq_pin    = AT91_PIN_PC4,
6032         .is_rmii        = 1,
6033  };
6034 @@ -93,7 +274,7 @@
6035  };
6036
6037  static struct at91_mmc_data __initdata dk_mmc_data = {
6038 -       .is_b           = 0,
6039 +       .slot_b         = 0,
6040         .wire4          = 1,
6041  };
6042
6043 @@ -145,6 +326,37 @@
6044         .partition_info = nand_partitions,
6045  };
6046
6047 +#define DK_FLASH_BASE  AT91_CHIPSELECT_0
6048 +#define DK_FLASH_SIZE  0x200000
6049 +
6050 +static struct physmap_flash_data dk_flash_data = {
6051 +       .width  = 2,
6052 +};
6053 +
6054 +static struct resource dk_flash_resource = {
6055 +       .start          = DK_FLASH_BASE,
6056 +       .end            = DK_FLASH_BASE + DK_FLASH_SIZE - 1,
6057 +       .flags          = IORESOURCE_MEM,
6058 +};
6059 +
6060 +static struct platform_device dk_flash = {
6061 +       .name           = "physmap-flash",
6062 +       .id             = 0,
6063 +       .dev            = {
6064 +                               .platform_data  = &dk_flash_data,
6065 +                       },
6066 +       .resource       = &dk_flash_resource,
6067 +       .num_resources  = 1,
6068 +};
6069 +
6070 +static struct at91_gpio_led dk_leds[] = {
6071 +       {
6072 +               .name           = "led0",
6073 +               .gpio           = AT91_PIN_PB2,
6074 +               .trigger        = "timer",
6075 +       }
6076 +};
6077 +
6078  static void __init dk_board_init(void)
6079  {
6080         /* Serial */
6081 @@ -172,8 +384,12 @@
6082  #endif
6083         /* NAND */
6084         at91_add_device_nand(&dk_nand_data);
6085 +       /* NOR Flash */
6086 +       platform_device_register(&dk_flash);
6087 +       /* LEDs */
6088 +       at91_gpio_leds(dk_leds, ARRAY_SIZE(dk_leds));
6089         /* VGA */
6090 -//     dk_add_device_video();
6091 +       dk_add_device_video();
6092  }
6093
6094  MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
6095 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-eb9200.c linux-2.6.19/arch/arm/mach-at91rm9200/board-eb9200.c
6096 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-eb9200.c  Mon Dec  4 16:39:29 2006
6097 +++ linux-2.6.19/arch/arm/mach-at91rm9200/board-eb9200.c        Thu Nov 23 15:50:12 2006
6098 @@ -65,7 +65,7 @@
6099         at91rm9200_init_interrupts(NULL);
6100  }
6101
6102 -static struct at91_eth_data __initdata eb9200_eth_data = {
6103 +static struct eth_platform_data __initdata eb9200_eth_data = {
6104         .phy_irq_pin    = AT91_PIN_PC4,
6105         .is_rmii        = 1,
6106  };
6107 @@ -87,7 +87,7 @@
6108  };
6109
6110  static struct at91_mmc_data __initdata eb9200_mmc_data = {
6111 -       .is_b           = 0,
6112 +       .slot_b         = 0,
6113         .wire4          = 1,
6114  };
6115
6116 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-ek.c linux-2.6.19/arch/arm/mach-at91rm9200/board-ek.c
6117 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-ek.c      Mon Dec  4 16:39:29 2006
6118 +++ linux-2.6.19/arch/arm/mach-at91rm9200/board-ek.c    Thu Nov 23 15:50:12 2006
6119 @@ -27,6 +27,7 @@
6120  #include <linux/module.h>
6121  #include <linux/platform_device.h>
6122  #include <linux/spi/spi.h>
6123 +#include <linux/mtd/physmap.h>
6124
6125  #include <asm/hardware.h>
6126  #include <asm/setup.h>
6127 @@ -39,6 +40,7 @@
6128
6129  #include <asm/arch/board.h>
6130  #include <asm/arch/gpio.h>
6131 +#include <asm/arch/at91rm9200_mc.h>
6132
6133  #include "generic.h"
6134
6135 @@ -71,7 +73,188 @@
6136         at91rm9200_init_interrupts(NULL);
6137  }
6138
6139 -static struct at91_eth_data __initdata ek_eth_data = {
6140 +#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
6141 +#include <video/s1d13xxxfb.h>
6142 +#include <asm/arch/ics1523.h>
6143 +
6144 +/* EPSON S1D13806 FB */
6145 +#define AT91_FB_REG_BASE       0x40000000L
6146 +#define        AT91_FB_REG_SIZE        0x200
6147 +#define AT91_FB_VMEM_BASE      0x40200000L
6148 +#define AT91_FB_VMEM_SIZE      0x140000L
6149 +
6150 +static void __init ek_init_video(void)
6151 +{
6152 +       /* NWAIT Signal */
6153 +       at91_set_A_periph(AT91_PIN_PC6, 0);
6154 +
6155 +       /* Initialization of the Static Memory Controller for Chip Select 3 */
6156 +       at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_DBW_16                 /* 16 bit */
6157 +                               | AT91_SMC_WSEN | AT91_SMC_NWS_(5)      /* wait states */
6158 +                               | AT91_SMC_TDF_(1)                      /* float time */
6159 +       );
6160 +
6161 +       AT91F_ICS1523_clockinit();
6162 +}
6163 +
6164 +/* CRT:    (active)   640x480 60Hz (PCLK=CLKI=25.175MHz)
6165 +   Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz) */
6166 +static const struct s1d13xxxfb_regval ek_s1dfb_initregs[] = {
6167 +       {S1DREG_MISC,                   0x00},  /* Enable Memory/Register select bit */
6168 +       {S1DREG_COM_DISP_MODE,          0x00},  /* disable display output */
6169 +       {S1DREG_GPIO_CNF0,              0xFF},  // 0x00
6170 +       {S1DREG_GPIO_CNF1,              0x1F},  // 0x08
6171 +       {S1DREG_GPIO_CTL0,              0x00},
6172 +       {S1DREG_GPIO_CTL1,              0x00},
6173 +       {S1DREG_CLK_CNF,                0x01},  /* no divide, MCLK source is CLKI3 0x02*/
6174 +       {S1DREG_LCD_CLK_CNF,            0x00},
6175 +       {S1DREG_CRT_CLK_CNF,            0x00},
6176 +       {S1DREG_MPLUG_CLK_CNF,          0x00},
6177 +       {S1DREG_CPU2MEM_WST_SEL,        0x01},  /* 2*period(MCLK) - 4ns > period(BCLK) */
6178 +       {S1DREG_SDRAM_REF_RATE,         0x03},  /* 32768 <= MCLK <= 50000 (MHz) */
6179 +       {S1DREG_SDRAM_TC0,              0x00},  /* MCLK source freq (MHz): */
6180 +       {S1DREG_SDRAM_TC1,              0x01},  /* 42 <= MCLK <= 50 */
6181 +       {S1DREG_MEM_CNF,                0x80},  /* SDRAM Initialization - needed before mem access */
6182 +       {S1DREG_PANEL_TYPE,             0x25},  /* std TFT 16bit, 8bit SCP format 2, single passive LCD */
6183 +       {S1DREG_MOD_RATE,               0x00},  /* toggle every FPFRAME */
6184 +       {S1DREG_LCD_DISP_HWIDTH,        0x4F},  /* 680 pix */
6185 +       {S1DREG_LCD_NDISP_HPER,         0x12},  /* 152 pix */
6186 +       {S1DREG_TFT_FPLINE_START,       0x01},  /* 13 pix */
6187 +       {S1DREG_TFT_FPLINE_PWIDTH,      0x0B},  /* 96 pix */
6188 +       {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},
6189 +       {S1DREG_LCD_DISP_VHEIGHT1,      0x01},  /* 480 lines */
6190 +       {S1DREG_LCD_NDISP_VPER,         0x2C},  /* 44 lines */
6191 +       {S1DREG_TFT_FPFRAME_START,      0x0A},  /* 10 lines */
6192 +       {S1DREG_TFT_FPFRAME_PWIDTH,     0x01},  /* 2 lines */
6193 +       {S1DREG_LCD_DISP_MODE,          0x05},  /* 16 bpp */
6194 +       {S1DREG_LCD_MISC,               0x00},  /* dithering enabled, dual panel buffer enabled */
6195 +       {S1DREG_LCD_DISP_START0,        0x00},
6196 +       {S1DREG_LCD_DISP_START1,        0xC8},
6197 +       {S1DREG_LCD_DISP_START2,        0x00},
6198 +       {S1DREG_LCD_MEM_OFF0,           0x80},
6199 +       {S1DREG_LCD_MEM_OFF1,           0x02},
6200 +       {S1DREG_LCD_PIX_PAN,            0x00},
6201 +       {S1DREG_LCD_DISP_FIFO_HTC,      0x3B},
6202 +       {S1DREG_LCD_DISP_FIFO_LTC,      0x3C},
6203 +       {S1DREG_CRT_DISP_HWIDTH,        0x4F},  /* 680 pix */
6204 +       {S1DREG_CRT_NDISP_HPER,         0x13},  /* 160 pix */
6205 +       {S1DREG_CRT_HRTC_START,         0x01},  /* 13 pix */
6206 +       {S1DREG_CRT_HRTC_PWIDTH,        0x0B},  /* 96 pix */
6207 +       {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},
6208 +       {S1DREG_CRT_DISP_VHEIGHT1,      0x01},  /* 480 lines */
6209 +       {S1DREG_CRT_NDISP_VPER,         0x2B},  /* 44 lines */
6210 +       {S1DREG_CRT_VRTC_START,         0x09},  /* 10 lines */
6211 +       {S1DREG_CRT_VRTC_PWIDTH,        0x01},  /* 2 lines */
6212 +       {S1DREG_TV_OUT_CTL,             0x10},
6213 +       {0x005E,                        0x9F},
6214 +       {0x005F,                        0x00},
6215 +       {S1DREG_CRT_DISP_MODE,          0x05},  /* 16 bpp */
6216 +       {S1DREG_CRT_DISP_START0,        0x00},
6217 +       {S1DREG_CRT_DISP_START1,        0x00},
6218 +       {S1DREG_CRT_DISP_START2,        0x00},
6219 +       {S1DREG_CRT_MEM_OFF0,           0x80},
6220 +       {S1DREG_CRT_MEM_OFF1,           0x02},
6221 +       {S1DREG_CRT_PIX_PAN,            0x00},
6222 +       {S1DREG_CRT_DISP_FIFO_HTC,      0x3B},
6223 +       {S1DREG_CRT_DISP_FIFO_LTC,      0x3C},
6224 +       {S1DREG_LCD_CUR_CTL,            0x00},  /* inactive */
6225 +       {S1DREG_LCD_CUR_START,          0x01},
6226 +       {S1DREG_LCD_CUR_XPOS0,          0x00},
6227 +       {S1DREG_LCD_CUR_XPOS1,          0x00},
6228 +       {S1DREG_LCD_CUR_YPOS0,          0x00},
6229 +       {S1DREG_LCD_CUR_YPOS1,          0x00},
6230 +       {S1DREG_LCD_CUR_BCTL0,          0x00},
6231 +       {S1DREG_LCD_CUR_GCTL0,          0x00},
6232 +       {S1DREG_LCD_CUR_RCTL0,          0x00},
6233 +       {S1DREG_LCD_CUR_BCTL1,          0x1F},
6234 +       {S1DREG_LCD_CUR_GCTL1,          0x3F},
6235 +       {S1DREG_LCD_CUR_RCTL1,          0x1F},
6236 +       {S1DREG_LCD_CUR_FIFO_HTC,       0x00},
6237 +       {S1DREG_CRT_CUR_CTL,            0x00},  /* inactive */
6238 +       {S1DREG_CRT_CUR_START,          0x01},
6239 +       {S1DREG_CRT_CUR_XPOS0,          0x00},
6240 +       {S1DREG_CRT_CUR_XPOS1,          0x00},
6241 +       {S1DREG_CRT_CUR_YPOS0,          0x00},
6242 +       {S1DREG_CRT_CUR_YPOS1,          0x00},
6243 +       {S1DREG_CRT_CUR_BCTL0,          0x00},
6244 +       {S1DREG_CRT_CUR_GCTL0,          0x00},
6245 +       {S1DREG_CRT_CUR_RCTL0,          0x00},
6246 +       {S1DREG_CRT_CUR_BCTL1,          0x1F},
6247 +       {S1DREG_CRT_CUR_GCTL1,          0x3F},
6248 +       {S1DREG_CRT_CUR_RCTL1,          0x1F},
6249 +       {S1DREG_CRT_CUR_FIFO_HTC,       0x00},
6250 +       {S1DREG_BBLT_CTL0,              0x00},
6251 +       {S1DREG_BBLT_CTL0,              0x00},
6252 +       {S1DREG_BBLT_CC_EXP,            0x00},
6253 +       {S1DREG_BBLT_OP,                0x00},
6254 +       {S1DREG_BBLT_SRC_START0,        0x00},
6255 +       {S1DREG_BBLT_SRC_START1,        0x00},
6256 +       {S1DREG_BBLT_SRC_START2,        0x00},
6257 +       {S1DREG_BBLT_DST_START0,        0x00},
6258 +       {S1DREG_BBLT_DST_START1,        0x00},
6259 +       {S1DREG_BBLT_DST_START2,        0x00},
6260 +       {S1DREG_BBLT_MEM_OFF0,          0x00},
6261 +       {S1DREG_BBLT_MEM_OFF1,          0x00},
6262 +       {S1DREG_BBLT_WIDTH0,            0x00},
6263 +       {S1DREG_BBLT_WIDTH1,            0x00},
6264 +       {S1DREG_BBLT_HEIGHT0,           0x00},
6265 +       {S1DREG_BBLT_HEIGHT1,           0x00},
6266 +       {S1DREG_BBLT_BGC0,              0x00},
6267 +       {S1DREG_BBLT_BGC1,              0x00},
6268 +       {S1DREG_BBLT_FGC0,              0x00},
6269 +       {S1DREG_BBLT_FGC1,              0x00},
6270 +       {S1DREG_LKUP_MODE,              0x00},  /* LCD LUT r | LCD and CRT/TV LUT w */
6271 +       {S1DREG_LKUP_ADDR,              0x00},
6272 +       {S1DREG_PS_CNF,                 0x10},  /* Power Save disable */
6273 +       {S1DREG_PS_STATUS,              0x02},  /* LCD Panel down, mem up */
6274 +       {S1DREG_CPU2MEM_WDOGT,          0x00},
6275 +       {S1DREG_COM_DISP_MODE,          0x02},  /* enable CRT display output */
6276 +};
6277 +
6278 +static struct s1d13xxxfb_pdata ek_s1dfb_pdata = {
6279 +       .initregs               = ek_s1dfb_initregs,
6280 +       .initregssize           = ARRAY_SIZE(ek_s1dfb_initregs),
6281 +       .platform_init_video    = ek_init_video,
6282 +};
6283 +
6284 +static u64 s1dfb_dmamask = 0xffffffffUL;
6285 +
6286 +static struct resource ek_s1dfb_resource[] = {
6287 +       [0] = { /* video mem */
6288 +               .name   = "s1d13806 memory",
6289 +               .start  = AT91_FB_VMEM_BASE,
6290 +               .end    = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
6291 +               .flags  = IORESOURCE_MEM,
6292 +       },
6293 +       [1] = { /* video registers */
6294 +               .name   = "s1d13806 registers",
6295 +               .start  = AT91_FB_REG_BASE,
6296 +               .end    = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
6297 +               .flags  = IORESOURCE_MEM,
6298 +       },
6299 +};
6300 +
6301 +static struct platform_device ek_s1dfb_device = {
6302 +       .name           = "s1d13806fb",
6303 +       .id             = -1,
6304 +       .dev            = {
6305 +                       .dma_mask               = &s1dfb_dmamask,
6306 +                       .coherent_dma_mask      = 0xffffffff,
6307 +                       .platform_data          = &ek_s1dfb_pdata,
6308 +       },
6309 +       .resource       = ek_s1dfb_resource,
6310 +       .num_resources  = ARRAY_SIZE(ek_s1dfb_resource),
6311 +};
6312 +
6313 +static void __init ek_add_device_video(void)
6314 +{
6315 +       platform_device_register(&ek_s1dfb_device);
6316 +}
6317 +#else
6318 +static void __init ek_add_device_video(void) {}
6319 +#endif
6320 +
6321 +static struct eth_platform_data __initdata ek_eth_data = {
6322         .phy_irq_pin    = AT91_PIN_PC4,
6323         .is_rmii        = 1,
6324  };
6325 @@ -87,7 +270,7 @@
6326
6327  static struct at91_mmc_data __initdata ek_mmc_data = {
6328         .det_pin        = AT91_PIN_PB27,
6329 -       .is_b           = 0,
6330 +       .slot_b         = 0,
6331         .wire4          = 1,
6332         .wp_pin         = AT91_PIN_PA17,
6333  };
6334 @@ -107,6 +290,42 @@
6335  #endif
6336  };
6337
6338 +#define EK_FLASH_BASE  AT91_CHIPSELECT_0
6339 +#define EK_FLASH_SIZE  0x200000
6340 +
6341 +static struct physmap_flash_data ek_flash_data = {
6342 +       .width  = 2,
6343 +};
6344 +
6345 +static struct resource ek_flash_resource = {
6346 +       .start          = EK_FLASH_BASE,
6347 +       .end            = EK_FLASH_BASE + EK_FLASH_SIZE - 1,
6348 +       .flags          = IORESOURCE_MEM,
6349 +};
6350 +
6351 +static struct platform_device ek_flash = {
6352 +       .name           = "physmap-flash",
6353 +       .id             = 0,
6354 +       .dev            = {
6355 +                               .platform_data  = &ek_flash_data,
6356 +                       },
6357 +       .resource       = &ek_flash_resource,
6358 +       .num_resources  = 1,
6359 +};
6360 +
6361 +static struct at91_gpio_led ek_leds[] = {
6362 +       {
6363 +               .name           = "led0",
6364 +               .gpio           = AT91_PIN_PB1,
6365 +               .trigger        = "heartbeat",
6366 +       },
6367 +       {
6368 +               .name           = "led1",
6369 +               .gpio           = AT91_PIN_PB2,
6370 +               .trigger        = "timer",
6371 +       }
6372 +};
6373 +
6374  static void __init ek_board_init(void)
6375  {
6376         /* Serial */
6377 @@ -130,8 +349,12 @@
6378         at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
6379         at91_add_device_mmc(&ek_mmc_data);
6380  #endif
6381 +       /* NOR Flash */
6382 +       platform_device_register(&ek_flash);
6383 +       /* LEDs */
6384 +       at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
6385         /* VGA */
6386 -//     ek_add_device_video();
6387 +       ek_add_device_video();
6388  }
6389
6390  MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
6391 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-kafa.c linux-2.6.19/arch/arm/mach-at91rm9200/board-kafa.c
6392 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-kafa.c    Mon Dec  4 16:39:29 2006
6393 +++ linux-2.6.19/arch/arm/mach-at91rm9200/board-kafa.c  Thu Nov 23 15:50:12 2006
6394 @@ -67,7 +67,7 @@
6395         at91rm9200_init_interrupts(NULL);
6396  }
6397
6398 -static struct at91_eth_data __initdata kafa_eth_data = {
6399 +static struct eth_platform_data __initdata kafa_eth_data = {
6400         .phy_irq_pin    = AT91_PIN_PC4,
6401         .is_rmii        = 0,
6402  };
6403 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-kb9202.c linux-2.6.19/arch/arm/mach-at91rm9200/board-kb9202.c
6404 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-kb9202.c  Mon Dec  4 16:39:29 2006
6405 +++ linux-2.6.19/arch/arm/mach-at91rm9200/board-kb9202.c        Thu Nov 23 15:50:12 2006
6406 @@ -68,7 +68,7 @@
6407         at91rm9200_init_interrupts(NULL);
6408  }
6409
6410 -static struct at91_eth_data __initdata kb9202_eth_data = {
6411 +static struct eth_platform_data __initdata kb9202_eth_data = {
6412         .phy_irq_pin    = AT91_PIN_PB29,
6413         .is_rmii        = 0,
6414  };
6415 @@ -84,7 +84,7 @@
6416
6417  static struct at91_mmc_data __initdata kb9202_mmc_data = {
6418         .det_pin        = AT91_PIN_PB2,
6419 -       .is_b           = 0,
6420 +       .slot_b         = 0,
6421         .wire4          = 1,
6422  };
6423
6424 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-sam9260ek.c linux-2.6.19/arch/arm/mach-at91rm9200/board-sam9260ek.c
6425 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-sam9260ek.c       Thu Jan  1 02:00:00 1970
6426 +++ linux-2.6.19/arch/arm/mach-at91rm9200/board-sam9260ek.c     Sat Nov 25 10:47:45 2006
6427 @@ -0,0 +1,201 @@
6428 +/*
6429 + * linux/arch/arm/mach-at91rm9200/board-ek.c
6430 + *
6431 + *  Copyright (C) 2005 SAN People
6432 + *  Copyright (C) 2006 Atmel
6433 + *
6434 + * This program is free software; you can redistribute it and/or modify
6435 + * it under the terms of the GNU General Public License as published by
6436 + * the Free Software Foundation; either version 2 of the License, or
6437 + * (at your option) any later version.
6438 + *
6439 + * This program is distributed in the hope that it will be useful,
6440 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6441 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6442 + * GNU General Public License for more details.
6443 + *
6444 + * You should have received a copy of the GNU General Public License
6445 + * along with this program; if not, write to the Free Software
6446 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6447 + */
6448 +
6449 +#include <linux/types.h>
6450 +#include <linux/init.h>
6451 +#include <linux/mm.h>
6452 +#include <linux/module.h>
6453 +#include <linux/platform_device.h>
6454 +#include <linux/spi/spi.h>
6455 +
6456 +#include <asm/hardware.h>
6457 +#include <asm/setup.h>
6458 +#include <asm/mach-types.h>
6459 +#include <asm/irq.h>
6460 +
6461 +#include <asm/mach/arch.h>
6462 +#include <asm/mach/map.h>
6463 +#include <asm/mach/irq.h>
6464 +
6465 +#include <asm/arch/board.h>
6466 +#include <asm/arch/gpio.h>
6467 +#include <asm/arch/at91sam926x_mc.h>
6468 +
6469 +#include "generic.h"
6470 +
6471 +
6472 +/*
6473 + * Serial port configuration.
6474 + *    0 .. 5 = USART0 .. USART5
6475 + *    6      = DBGU
6476 + */
6477 +static struct at91_uart_config __initdata ek_uart_config = {
6478 +       .console_tty    = 0,                            /* ttyS0 */
6479 +       .nr_tty         = 3,
6480 +       .tty_map        = { 6, 0, 1, -1, -1, -1, -1 }   /* ttyS0, ..., ttyS6 */
6481 +};
6482 +
6483 +static void __init ek_map_io(void)
6484 +{
6485 +       /* Initialize processor: 18.432 MHz crystal */
6486 +       at91sam9260_initialize(18432000);
6487 +
6488 +       /* Setup the serial ports and console */
6489 +       at91_init_serial(&ek_uart_config);
6490 +}
6491 +
6492 +static void __init ek_init_irq(void)
6493 +{
6494 +       at91sam9260_init_interrupts(NULL);
6495 +}
6496 +
6497 +
6498 +/*
6499 + * USB Host port
6500 + */
6501 +static struct at91_usbh_data __initdata ek_usbh_data = {
6502 +       .ports          = 2,
6503 +};
6504 +
6505 +/*
6506 + * USB Device port
6507 + */
6508 +static struct at91_udc_data __initdata ek_udc_data = {
6509 +       .vbus_pin       = AT91_PIN_PC5,
6510 +       .pullup_pin     = 0,            /* pull-up driven by UDC */
6511 +};
6512 +
6513 +
6514 +/*
6515 + * SPI devices.
6516 + */
6517 +static struct spi_board_info ek_spi_devices[] = {
6518 +#if !defined(CONFIG_MMC_AT91)
6519 +       {       /* DataFlash chip */
6520 +               .modalias       = "mtd_dataflash",
6521 +               .chip_select    = 1,
6522 +               .max_speed_hz   = 15 * 1000 * 1000,
6523 +               .bus_num        = 0,
6524 +       },
6525 +#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
6526 +       {       /* DataFlash card */
6527 +               .modalias       = "mtd_dataflash",
6528 +               .chip_select    = 0,
6529 +               .max_speed_hz   = 15 * 1000 * 1000,
6530 +               .bus_num        = 0,
6531 +       },
6532 +#endif
6533 +#endif
6534 +#if defined(CONFIG_SND_AT73C213)
6535 +       {       /* AT73C213 DAC */
6536 +               .modalias       = "snd_at73c213",
6537 +               .chip_select    = 0,
6538 +               .max_speed_hz   = 10 * 1000 * 1000,
6539 +               .bus_num        = 1,
6540 +       },
6541 +#endif
6542 +};
6543 +
6544 +
6545 +/*
6546 + * MACB Ethernet device
6547 + */
6548 +static struct __initdata eth_platform_data ek_macb_data = {
6549 +       .is_rmii        = 1,
6550 +};
6551 +
6552 +
6553 +/*
6554 + * NAND flash
6555 + */
6556 +static struct mtd_partition __initdata ek_nand_partition[] = {
6557 +       {
6558 +               .name   = "Partition 1",
6559 +               .offset = 0,
6560 +               .size   = 256 * 1024,
6561 +       },
6562 +       {
6563 +               .name   = "Partition 2",
6564 +               .offset = 256 * 1024,
6565 +               .size   = MTDPART_SIZ_FULL,
6566 +       },
6567 +};
6568 +
6569 +static struct mtd_partition *nand_partitions(int size, int *num_partitions)
6570 +{
6571 +       *num_partitions = ARRAY_SIZE(ek_nand_partition);
6572 +       return ek_nand_partition;
6573 +}
6574 +
6575 +static struct at91_nand_data __initdata ek_nand_data = {
6576 +       .ale            = 21,
6577 +       .cle            = 22,
6578 +//     .det_pin        = ... not connected
6579 +       .rdy_pin        = AT91_PIN_PC13,
6580 +       .enable_pin     = AT91_PIN_PC14,
6581 +       .partition_info = nand_partitions,
6582 +#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
6583 +       .bus_width_16   = 1,
6584 +#else
6585 +       .bus_width_16   = 0,
6586 +#endif
6587 +};
6588 +
6589 +
6590 +/*
6591 + * MCI (SD/MMC)
6592 + */
6593 +static struct at91_mmc_data __initdata ek_mmc_data = {
6594 +       .slot_b         = 1,
6595 +       .wire4          = 1,
6596 +//     .det_pin        = ... not connected
6597 +//     .wp_pin         = ... not connected
6598 +//     .vcc_pin        = ... not connected
6599 +};
6600 +
6601 +static void __init ek_board_init(void)
6602 +{
6603 +       /* Serial */
6604 +       at91_add_device_serial();
6605 +       /* USB Host */
6606 +       at91_add_device_usbh(&ek_usbh_data);
6607 +       /* USB Device */
6608 +       at91_add_device_udc(&ek_udc_data);
6609 +       /* SPI */
6610 +       at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
6611 +       /* NAND */
6612 +       at91_add_device_nand(&ek_nand_data);
6613 +       /* Ethernet */
6614 +       at91_add_device_eth(&ek_macb_data);
6615 +       /* MMC */
6616 +       at91_add_device_mmc(&ek_mmc_data);
6617 +}
6618 +
6619 +MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
6620 +       /* Maintainer: Atmel */
6621 +       .phys_io        = AT91_BASE_SYS,
6622 +       .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
6623 +       .boot_params    = AT91_SDRAM_BASE + 0x100,
6624 +       .timer          = &at91sam926x_timer,
6625 +       .map_io         = ek_map_io,
6626 +       .init_irq       = ek_init_irq,
6627 +       .init_machine   = ek_board_init,
6628 +MACHINE_END
6629 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-sam9261ek.c linux-2.6.19/arch/arm/mach-at91rm9200/board-sam9261ek.c
6630 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-sam9261ek.c       Thu Jan  1 02:00:00 1970
6631 +++ linux-2.6.19/arch/arm/mach-at91rm9200/board-sam9261ek.c     Sat Nov 25 11:07:44 2006
6632 @@ -0,0 +1,259 @@
6633 +/*
6634 + * linux/arch/arm/mach-at91rm9200/board-ek.c
6635 + *
6636 + *  Copyright (C) 2005 SAN People
6637 + *  Copyright (C) 2006 Atmel
6638 + *
6639 + * This program is free software; you can redistribute it and/or modify
6640 + * it under the terms of the GNU General Public License as published by
6641 + * the Free Software Foundation; either version 2 of the License, or
6642 + * (at your option) any later version.
6643 + *
6644 + * This program is distributed in the hope that it will be useful,
6645 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6646 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6647 + * GNU General Public License for more details.
6648 + *
6649 + * You should have received a copy of the GNU General Public License
6650 + * along with this program; if not, write to the Free Software
6651 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6652 + */
6653 +
6654 +#include <linux/types.h>
6655 +#include <linux/init.h>
6656 +#include <linux/mm.h>
6657 +#include <linux/module.h>
6658 +#include <linux/platform_device.h>
6659 +#include <linux/spi/spi.h>
6660 +#include <linux/dm9000.h>
6661 +
6662 +#include <asm/hardware.h>
6663 +#include <asm/setup.h>
6664 +#include <asm/mach-types.h>
6665 +#include <asm/irq.h>
6666 +
6667 +#include <asm/mach/arch.h>
6668 +#include <asm/mach/map.h>
6669 +#include <asm/mach/irq.h>
6670 +
6671 +#include <asm/arch/board.h>
6672 +#include <asm/arch/gpio.h>
6673 +#include <asm/arch/at91sam926x_mc.h>
6674 +
6675 +#include "generic.h"
6676 +
6677 +
6678 +/*
6679 + * Serial port configuration.
6680 + *    0 .. 2 = USART0 .. USART2
6681 + *    3      = DBGU
6682 + */
6683 +static struct at91_uart_config __initdata ek_uart_config = {
6684 +       .console_tty    = 0,                            /* ttyS0 */
6685 +       .nr_tty         = 1,
6686 +       .tty_map        = { 3, -1, -1, -1 }             /* ttyS0, ..., ttyS3 */
6687 +};
6688 +
6689 +static void __init ek_map_io(void)
6690 +{
6691 +       /* Initialize processor: 18.432 MHz crystal */
6692 +       at91sam9261_initialize(18432000);
6693 +
6694 +       /* Setup the serial ports and console */
6695 +       at91_init_serial(&ek_uart_config);
6696 +}
6697 +
6698 +static void __init ek_init_irq(void)
6699 +{
6700 +       at91sam9261_init_interrupts(NULL);
6701 +}
6702 +
6703 +
6704 +/*
6705 + * DM9000 ethernet device
6706 + */
6707 +#if defined(CONFIG_DM9000)
6708 +static struct resource at91sam9261_dm9000_resource[] = {
6709 +       [0] = {
6710 +               .start  = AT91_CHIPSELECT_2,
6711 +               .end    = AT91_CHIPSELECT_2 + 3,
6712 +               .flags  = IORESOURCE_MEM
6713 +       },
6714 +       [1] = {
6715 +               .start  = AT91_CHIPSELECT_2 + 0x44,
6716 +               .end    = AT91_CHIPSELECT_2 + 0xFF,
6717 +               .flags  = IORESOURCE_MEM
6718 +       },
6719 +       [2] = {
6720 +               .start  = AT91_PIN_PC11,
6721 +               .end    = AT91_PIN_PC11,
6722 +               .flags  = IORESOURCE_IRQ
6723 +       }
6724 +};
6725 +
6726 +static struct dm9000_plat_data dm9000_platdata = {
6727 +       .flags          = DM9000_PLATF_16BITONLY,
6728 +};
6729 +
6730 +static struct platform_device at91sam9261_dm9000_device = {
6731 +       .name           = "dm9000",
6732 +       .id             = 0,
6733 +       .num_resources  = ARRAY_SIZE(at91sam9261_dm9000_resource),
6734 +       .resource       = at91sam9261_dm9000_resource,
6735 +       .dev            = {
6736 +               .platform_data  = &dm9000_platdata,
6737 +       }
6738 +};
6739 +
6740 +static void __init ek_add_device_dm9000(void)
6741 +{
6742 +       /*
6743 +        * Configure Chip-Select 2 on SMC for the DM9000.
6744 +        * Note: These timings were calculated for MASTER_CLOCK = 100000000
6745 +        *  according to the DM9000 timings.
6746 +        */
6747 +       at91_sys_write(AT91_SMC_SETUP(2), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
6748 +       at91_sys_write(AT91_SMC_PULSE(2), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
6749 +       at91_sys_write(AT91_SMC_CYCLE(2), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
6750 +       at91_sys_write(AT91_SMC_MODE(2), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
6751 +
6752 +       /* Configure Reset signal as output */
6753 +       at91_set_gpio_output(AT91_PIN_PC10, 0);
6754 +
6755 +       /* Configure Interrupt pin as input, no pull-up */
6756 +       at91_set_gpio_input(AT91_PIN_PC11, 0);
6757 +
6758 +       platform_device_register(&at91sam9261_dm9000_device);
6759 +}
6760 +#else
6761 +static void __init ek_add_device_dm9000(void) {}
6762 +#endif /* CONFIG_DM9000 */
6763 +
6764 +
6765 +/*
6766 + * USB Host Port
6767 + */
6768 +static struct at91_usbh_data __initdata ek_usbh_data = {
6769 +       .ports          = 2,
6770 +};
6771 +
6772 +
6773 +/*
6774 + * USB Device Port
6775 + */
6776 +static struct at91_udc_data __initdata ek_udc_data = {
6777 +       .vbus_pin       = AT91_PIN_PB29,
6778 +       .pullup_pin     = 0,            /* pull-up driven by UDC */
6779 +};
6780 +
6781 +
6782 +/*
6783 + * MCI (SD/MMC)
6784 + */
6785 +static struct at91_mmc_data __initdata ek_mmc_data = {
6786 +       .wire4          = 1,
6787 +//     .det_pin        = ... not connected
6788 +//     .wp_pin         = ... not connected
6789 +//     .vcc_pin        = ... not connected
6790 +};
6791 +
6792 +
6793 +/*
6794 + * NAND flash
6795 + */
6796 +static struct mtd_partition __initdata ek_nand_partition[] = {
6797 +       {
6798 +               .name   = "Partition 1",
6799 +               .offset = 0,
6800 +               .size   = 256 * 1024,
6801 +       },
6802 +       {
6803 +               .name   = "Partition 2",
6804 +               .offset = 256 * 1024 ,
6805 +               .size   = MTDPART_SIZ_FULL,
6806 +       },
6807 +};
6808 +
6809 +static struct mtd_partition *nand_partitions(int size, int *num_partitions)
6810 +{
6811 +       *num_partitions = ARRAY_SIZE(ek_nand_partition);
6812 +       return ek_nand_partition;
6813 +}
6814 +
6815 +static struct at91_nand_data __initdata ek_nand_data = {
6816 +       .ale            = 22,
6817 +       .cle            = 21,
6818 +//     .det_pin        = ... not connected
6819 +       .rdy_pin        = AT91_PIN_PC15,
6820 +       .enable_pin     = AT91_PIN_PC14,
6821 +       .partition_info = nand_partitions,
6822 +#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
6823 +       .bus_width_16   = 1,
6824 +#else
6825 +       .bus_width_16   = 0,
6826 +#endif
6827 +};
6828 +
6829 +/*
6830 + * SPI devices
6831 + */
6832 +static struct spi_board_info ek_spi_devices[] = {
6833 +       {       /* DataFlash chip */
6834 +               .modalias       = "mtd_dataflash",
6835 +               .chip_select    = 0,
6836 +               .max_speed_hz   = 15 * 1000 * 1000,
6837 +               .bus_num        = 0,
6838 +       },
6839 +#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
6840 +       {       /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */
6841 +               .modalias       = "mtd_dataflash",
6842 +               .chip_select    = 3,
6843 +               .max_speed_hz   = 15 * 1000 * 1000,
6844 +               .bus_num        = 0,
6845 +       },
6846 +#elif defined(CONFIG_SND_AT73C213)
6847 +       {       /* AT73C213 DAC */
6848 +               .modalias       = "snd_at73c213",
6849 +               .chip_select    = 3,
6850 +               .max_speed_hz   = 10 * 1000 * 1000,
6851 +               .bus_num        = 0,
6852 +       },
6853 +#endif
6854 +};
6855 +
6856 +
6857 +static void __init ek_board_init(void)
6858 +{
6859 +       /* Serial */
6860 +       at91_add_device_serial();
6861 +       /* USB Host */
6862 +       at91_add_device_usbh(&ek_usbh_data);
6863 +       /* USB Device */
6864 +       at91_add_device_udc(&ek_udc_data);
6865 +       /* I2C */
6866 +       at91_add_device_i2c();
6867 +       /* NAND */
6868 +       at91_add_device_nand(&ek_nand_data);
6869 +       /* DM9000 ethernet */
6870 +       ek_add_device_dm9000();
6871 +
6872 +       /* spi0 and mmc/sd share the same PIO pins */
6873 +#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
6874 +       /* SPI */
6875 +       at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
6876 +#else
6877 +       /* MMC */
6878 +       at91_add_device_mmc(&ek_mmc_data);
6879 +#endif
6880 +}
6881 +
6882 +MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
6883 +       /* Maintainer: Atmel */
6884 +       .phys_io        = AT91_BASE_SYS,
6885 +       .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
6886 +       .boot_params    = AT91_SDRAM_BASE + 0x100,
6887 +       .timer          = &at91sam926x_timer,
6888 +       .map_io         = ek_map_io,
6889 +       .init_irq       = ek_init_irq,
6890 +       .init_machine   = ek_board_init,
6891 +MACHINE_END
6892 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/clock.c linux-2.6.19/arch/arm/mach-at91rm9200/clock.c
6893 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/clock.c Mon Dec  4 16:39:29 2006
6894 +++ linux-2.6.19/arch/arm/mach-at91rm9200/clock.c       Thu Nov 23 15:37:15 2006
6895 @@ -28,6 +28,8 @@
6896  #include <asm/mach-types.h>
6897
6898  #include <asm/hardware.h>
6899 +#include <asm/arch/at91_pmc.h>
6900 +#include <asm/arch/cpu.h>
6901
6902  #include "clock.h"
6903
6904 @@ -41,6 +43,7 @@
6905  #define clk_is_primary(x)      ((x)->type & CLK_TYPE_PRIMARY)
6906  #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
6907  #define clk_is_peripheral(x)   ((x)->type & CLK_TYPE_PERIPHERAL)
6908 +#define clk_is_sys(x)          ((x)->type & CLK_TYPE_SYSTEM)
6909
6910
6911  static LIST_HEAD(clocks);
6912 @@ -114,13 +117,11 @@
6913  static struct clk udpck = {
6914         .name           = "udpck",
6915         .parent         = &pllb,
6916 -       .pmc_mask       = AT91_PMC_UDP,
6917         .mode           = pmc_sys_mode,
6918  };
6919  static struct clk uhpck = {
6920         .name           = "uhpck",
6921         .parent         = &pllb,
6922 -       .pmc_mask       = AT91_PMC_UHP,
6923         .mode           = pmc_sys_mode,
6924  };
6925
6926 @@ -374,6 +375,7 @@
6927         seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
6928
6929         seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
6930 +#warning "Hard-coded PCK"
6931         for (i = 0; i < 4; i++)
6932                 seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
6933         seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
6934 @@ -434,6 +436,12 @@
6935                 clk->mode = pmc_periph_mode;
6936                 list_add_tail(&clk->node, &clocks);
6937         }
6938 +       else if (clk_is_sys(clk)) {
6939 +               clk->parent = &mck;
6940 +               clk->mode = pmc_sys_mode;
6941 +
6942 +               list_add_tail(&clk->node, &clocks);
6943 +       }
6944  #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
6945         else if (clk_is_programmable(clk)) {
6946                 clk->mode = pmc_sys_mode;
6947 @@ -586,9 +594,21 @@
6948          */
6949         at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
6950         pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
6951 -       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_UDP);
6952 +       if (cpu_is_at91rm9200()) {
6953 +               uhpck.pmc_mask = AT91RM9200_PMC_UHP;
6954 +               udpck.pmc_mask = AT91RM9200_PMC_UDP;
6955 +               at91_sys_write(AT91_PMC_SCDR, AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP);
6956 +               at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
6957 +       } else if (cpu_is_at91sam9260()) {
6958 +               uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
6959 +               udpck.pmc_mask = AT91SAM926x_PMC_UDP;
6960 +               at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP);
6961 +       } else if (cpu_is_at91sam9261()) {
6962 +               uhpck.pmc_mask = (AT91SAM926x_PMC_UHP | AT91_PMC_HCK0);
6963 +               udpck.pmc_mask = AT91SAM926x_PMC_UDP;
6964 +               at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91_PMC_HCK0 | AT91SAM926x_PMC_UDP);
6965 +       }
6966         at91_sys_write(AT91_CKGR_PLLBR, 0);
6967 -       at91_sys_write(AT91_PMC_SCER, AT91_PMC_MCKUDP);
6968
6969         udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
6970         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
6971 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/clock.h linux-2.6.19/arch/arm/mach-at91rm9200/clock.h
6972 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/clock.h Mon Dec  4 16:39:29 2006
6973 +++ linux-2.6.19/arch/arm/mach-at91rm9200/clock.h       Thu Nov 23 15:40:21 2006
6974 @@ -10,6 +10,7 @@
6975  #define CLK_TYPE_PLL           0x2
6976  #define CLK_TYPE_PROGRAMMABLE  0x4
6977  #define CLK_TYPE_PERIPHERAL    0x8
6978 +#define CLK_TYPE_SYSTEM                0x10
6979
6980
6981  struct clk {
6982 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/devices.c linux-2.6.19/arch/arm/mach-at91rm9200/devices.c
6983 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/devices.c       Mon Dec  4 16:39:29 2006
6984 +++ linux-2.6.19/arch/arm/mach-at91rm9200/devices.c     Thu Jan  1 02:00:00 1970
6985 @@ -1,813 +0,0 @@
6986 -/*
6987 - * arch/arm/mach-at91rm9200/devices.c
6988 - *
6989 - *  Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
6990 - *  Copyright (C) 2005 David Brownell
6991 - *
6992 - * This program is free software; you can redistribute it and/or modify
6993 - * it under the terms of the GNU General Public License as published by
6994 - * the Free Software Foundation; either version 2 of the License, or
6995 - * (at your option) any later version.
6996 - *
6997 - */
6998 -#include <asm/mach/arch.h>
6999 -#include <asm/mach/map.h>
7000 -
7001 -#include <linux/platform_device.h>
7002 -
7003 -#include <asm/hardware.h>
7004 -#include <asm/arch/board.h>
7005 -#include <asm/arch/gpio.h>
7006 -
7007 -#include "generic.h"
7008 -
7009 -#define SZ_512 0x00000200
7010 -#define SZ_256 0x00000100
7011 -#define SZ_16  0x00000010
7012 -
7013 -/* --------------------------------------------------------------------
7014 - *  USB Host
7015 - * -------------------------------------------------------------------- */
7016 -
7017 -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
7018 -static u64 ohci_dmamask = 0xffffffffUL;
7019 -static struct at91_usbh_data usbh_data;
7020 -
7021 -static struct resource at91_usbh_resources[] = {
7022 -       [0] = {
7023 -               .start  = AT91RM9200_UHP_BASE,
7024 -               .end    = AT91RM9200_UHP_BASE + SZ_1M - 1,
7025 -               .flags  = IORESOURCE_MEM,
7026 -       },
7027 -       [1] = {
7028 -               .start  = AT91RM9200_ID_UHP,
7029 -               .end    = AT91RM9200_ID_UHP,
7030 -               .flags  = IORESOURCE_IRQ,
7031 -       },
7032 -};
7033 -
7034 -static struct platform_device at91rm9200_usbh_device = {
7035 -       .name           = "at91_ohci",
7036 -       .id             = -1,
7037 -       .dev            = {
7038 -                               .dma_mask               = &ohci_dmamask,
7039 -                               .coherent_dma_mask      = 0xffffffff,
7040 -                               .platform_data          = &usbh_data,
7041 -       },
7042 -       .resource       = at91_usbh_resources,
7043 -       .num_resources  = ARRAY_SIZE(at91_usbh_resources),
7044 -};
7045 -
7046 -void __init at91_add_device_usbh(struct at91_usbh_data *data)
7047 -{
7048 -       if (!data)
7049 -               return;
7050 -
7051 -       usbh_data = *data;
7052 -       platform_device_register(&at91rm9200_usbh_device);
7053 -}
7054 -#else
7055 -void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
7056 -#endif
7057 -
7058 -
7059 -/* --------------------------------------------------------------------
7060 - *  USB Device (Gadget)
7061 - * -------------------------------------------------------------------- */
7062 -
7063 -#ifdef CONFIG_USB_GADGET_AT91
7064 -static struct at91_udc_data udc_data;
7065 -
7066 -static struct resource at91_udc_resources[] = {
7067 -       [0] = {
7068 -               .start  = AT91RM9200_BASE_UDP,
7069 -               .end    = AT91RM9200_BASE_UDP + SZ_16K - 1,
7070 -               .flags  = IORESOURCE_MEM,
7071 -       },
7072 -       [1] = {
7073 -               .start  = AT91RM9200_ID_UDP,
7074 -               .end    = AT91RM9200_ID_UDP,
7075 -               .flags  = IORESOURCE_IRQ,
7076 -       },
7077 -};
7078 -
7079 -static struct platform_device at91rm9200_udc_device = {
7080 -       .name           = "at91_udc",
7081 -       .id             = -1,
7082 -       .dev            = {
7083 -                               .platform_data          = &udc_data,
7084 -       },
7085 -       .resource       = at91_udc_resources,
7086 -       .num_resources  = ARRAY_SIZE(at91_udc_resources),
7087 -};
7088 -
7089 -void __init at91_add_device_udc(struct at91_udc_data *data)
7090 -{
7091 -       if (!data)
7092 -               return;
7093 -
7094 -       if (data->vbus_pin) {
7095 -               at91_set_gpio_input(data->vbus_pin, 0);
7096 -               at91_set_deglitch(data->vbus_pin, 1);
7097 -       }
7098 -       if (data->pullup_pin)
7099 -               at91_set_gpio_output(data->pullup_pin, 0);
7100 -
7101 -       udc_data = *data;
7102 -       platform_device_register(&at91rm9200_udc_device);
7103 -}
7104 -#else
7105 -void __init at91_add_device_udc(struct at91_udc_data *data) {}
7106 -#endif
7107 -
7108 -
7109 -/* --------------------------------------------------------------------
7110 - *  Ethernet
7111 - * -------------------------------------------------------------------- */
7112 -
7113 -#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
7114 -static u64 eth_dmamask = 0xffffffffUL;
7115 -static struct at91_eth_data eth_data;
7116 -
7117 -static struct resource at91_eth_resources[] = {
7118 -       [0] = {
7119 -               .start  = AT91_VA_BASE_EMAC,
7120 -               .end    = AT91_VA_BASE_EMAC + SZ_16K - 1,
7121 -               .flags  = IORESOURCE_MEM,
7122 -       },
7123 -       [1] = {
7124 -               .start  = AT91RM9200_ID_EMAC,
7125 -               .end    = AT91RM9200_ID_EMAC,
7126 -               .flags  = IORESOURCE_IRQ,
7127 -       },
7128 -};
7129 -
7130 -static struct platform_device at91rm9200_eth_device = {
7131 -       .name           = "at91_ether",
7132 -       .id             = -1,
7133 -       .dev            = {
7134 -                               .dma_mask               = &eth_dmamask,
7135 -                               .coherent_dma_mask      = 0xffffffff,
7136 -                               .platform_data          = &eth_data,
7137 -       },
7138 -       .resource       = at91_eth_resources,
7139 -       .num_resources  = ARRAY_SIZE(at91_eth_resources),
7140 -};
7141 -
7142 -void __init at91_add_device_eth(struct at91_eth_data *data)
7143 -{
7144 -       if (!data)
7145 -               return;
7146 -
7147 -       if (data->phy_irq_pin) {
7148 -               at91_set_gpio_input(data->phy_irq_pin, 0);
7149 -               at91_set_deglitch(data->phy_irq_pin, 1);
7150 -       }
7151 -
7152 -       /* Pins used for MII and RMII */
7153 -       at91_set_A_periph(AT91_PIN_PA16, 0);    /* EMDIO */
7154 -       at91_set_A_periph(AT91_PIN_PA15, 0);    /* EMDC */
7155 -       at91_set_A_periph(AT91_PIN_PA14, 0);    /* ERXER */
7156 -       at91_set_A_periph(AT91_PIN_PA13, 0);    /* ERX1 */
7157 -       at91_set_A_periph(AT91_PIN_PA12, 0);    /* ERX0 */
7158 -       at91_set_A_periph(AT91_PIN_PA11, 0);    /* ECRS_ECRSDV */
7159 -       at91_set_A_periph(AT91_PIN_PA10, 0);    /* ETX1 */
7160 -       at91_set_A_periph(AT91_PIN_PA9, 0);     /* ETX0 */
7161 -       at91_set_A_periph(AT91_PIN_PA8, 0);     /* ETXEN */
7162 -       at91_set_A_periph(AT91_PIN_PA7, 0);     /* ETXCK_EREFCK */
7163 -
7164 -       if (!data->is_rmii) {
7165 -               at91_set_B_periph(AT91_PIN_PB19, 0);    /* ERXCK */
7166 -               at91_set_B_periph(AT91_PIN_PB18, 0);    /* ECOL */
7167 -               at91_set_B_periph(AT91_PIN_PB17, 0);    /* ERXDV */
7168 -               at91_set_B_periph(AT91_PIN_PB16, 0);    /* ERX3 */
7169 -               at91_set_B_periph(AT91_PIN_PB15, 0);    /* ERX2 */
7170 -               at91_set_B_periph(AT91_PIN_PB14, 0);    /* ETXER */
7171 -               at91_set_B_periph(AT91_PIN_PB13, 0);    /* ETX3 */
7172 -               at91_set_B_periph(AT91_PIN_PB12, 0);    /* ETX2 */
7173 -       }
7174 -
7175 -       eth_data = *data;
7176 -       platform_device_register(&at91rm9200_eth_device);
7177 -}
7178 -#else
7179 -void __init at91_add_device_eth(struct at91_eth_data *data) {}
7180 -#endif
7181 -
7182 -
7183 -/* --------------------------------------------------------------------
7184 - *  Compact Flash / PCMCIA
7185 - * -------------------------------------------------------------------- */
7186 -
7187 -#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
7188 -static struct at91_cf_data cf_data;
7189 -
7190 -static struct resource at91_cf_resources[] = {
7191 -       [0] = {
7192 -               .start  = AT91_CF_BASE,
7193 -               /* ties up CS4, CS5 and CS6 */
7194 -               .end    = AT91_CF_BASE + (0x30000000 - 1),
7195 -               .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
7196 -       },
7197 -};
7198 -
7199 -static struct platform_device at91rm9200_cf_device = {
7200 -       .name           = "at91_cf",
7201 -       .id             = -1,
7202 -       .dev            = {
7203 -                               .platform_data          = &cf_data,
7204 -       },
7205 -       .resource       = at91_cf_resources,
7206 -       .num_resources  = ARRAY_SIZE(at91_cf_resources),
7207 -};
7208 -
7209 -void __init at91_add_device_cf(struct at91_cf_data *data)
7210 -{
7211 -       if (!data)
7212 -               return;
7213 -
7214 -       /* input/irq */
7215 -       if (data->irq_pin) {
7216 -               at91_set_gpio_input(data->irq_pin, 1);
7217 -               at91_set_deglitch(data->irq_pin, 1);
7218 -       }
7219 -       at91_set_gpio_input(data->det_pin, 1);
7220 -       at91_set_deglitch(data->det_pin, 1);
7221 -
7222 -       /* outputs, initially off */
7223 -       if (data->vcc_pin)
7224 -               at91_set_gpio_output(data->vcc_pin, 0);
7225 -       at91_set_gpio_output(data->rst_pin, 0);
7226 -
7227 -       /* force poweron defaults for these pins ... */
7228 -       at91_set_A_periph(AT91_PIN_PC9, 0);     /* A25/CFRNW */
7229 -       at91_set_A_periph(AT91_PIN_PC10, 0);    /* NCS4/CFCS */
7230 -       at91_set_A_periph(AT91_PIN_PC11, 0);    /* NCS5/CFCE1 */
7231 -       at91_set_A_periph(AT91_PIN_PC12, 0);    /* NCS6/CFCE2 */
7232 -
7233 -       cf_data = *data;
7234 -       platform_device_register(&at91rm9200_cf_device);
7235 -}
7236 -#else
7237 -void __init at91_add_device_cf(struct at91_cf_data *data) {}
7238 -#endif
7239 -
7240 -
7241 -/* --------------------------------------------------------------------
7242 - *  MMC / SD
7243 - * -------------------------------------------------------------------- */
7244 -
7245 -#if defined(CONFIG_MMC_AT91RM9200) || defined(CONFIG_MMC_AT91RM9200_MODULE)
7246 -static u64 mmc_dmamask = 0xffffffffUL;
7247 -static struct at91_mmc_data mmc_data;
7248 -
7249 -static struct resource at91_mmc_resources[] = {
7250 -       [0] = {
7251 -               .start  = AT91RM9200_BASE_MCI,
7252 -               .end    = AT91RM9200_BASE_MCI + SZ_16K - 1,
7253 -               .flags  = IORESOURCE_MEM,
7254 -       },
7255 -       [1] = {
7256 -               .start  = AT91RM9200_ID_MCI,
7257 -               .end    = AT91RM9200_ID_MCI,
7258 -               .flags  = IORESOURCE_IRQ,
7259 -       },
7260 -};
7261 -
7262 -static struct platform_device at91rm9200_mmc_device = {
7263 -       .name           = "at91_mci",
7264 -       .id             = -1,
7265 -       .dev            = {
7266 -                               .dma_mask               = &mmc_dmamask,
7267 -                               .coherent_dma_mask      = 0xffffffff,
7268 -                               .platform_data          = &mmc_data,
7269 -       },
7270 -       .resource       = at91_mmc_resources,
7271 -       .num_resources  = ARRAY_SIZE(at91_mmc_resources),
7272 -};
7273 -
7274 -void __init at91_add_device_mmc(struct at91_mmc_data *data)
7275 -{
7276 -       if (!data)
7277 -               return;
7278 -
7279 -       /* input/irq */
7280 -       if (data->det_pin) {
7281 -               at91_set_gpio_input(data->det_pin, 1);
7282 -               at91_set_deglitch(data->det_pin, 1);
7283 -       }
7284 -       if (data->wp_pin)
7285 -               at91_set_gpio_input(data->wp_pin, 1);
7286 -
7287 -       /* CLK */
7288 -       at91_set_A_periph(AT91_PIN_PA27, 0);
7289 -
7290 -       if (data->is_b) {
7291 -               /* CMD */
7292 -               at91_set_B_periph(AT91_PIN_PA8, 0);
7293 -
7294 -               /* DAT0, maybe DAT1..DAT3 */
7295 -               at91_set_B_periph(AT91_PIN_PA9, 0);
7296 -               if (data->wire4) {
7297 -                       at91_set_B_periph(AT91_PIN_PA10, 0);
7298 -                       at91_set_B_periph(AT91_PIN_PA11, 0);
7299 -                       at91_set_B_periph(AT91_PIN_PA12, 0);
7300 -               }
7301 -       } else {
7302 -               /* CMD */
7303 -               at91_set_A_periph(AT91_PIN_PA28, 0);
7304 -
7305 -               /* DAT0, maybe DAT1..DAT3 */
7306 -               at91_set_A_periph(AT91_PIN_PA29, 0);
7307 -               if (data->wire4) {
7308 -                       at91_set_B_periph(AT91_PIN_PB3, 0);
7309 -                       at91_set_B_periph(AT91_PIN_PB4, 0);
7310 -                       at91_set_B_periph(AT91_PIN_PB5, 0);
7311 -               }
7312 -       }
7313 -
7314 -       mmc_data = *data;
7315 -       platform_device_register(&at91rm9200_mmc_device);
7316 -}
7317 -#else
7318 -void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
7319 -#endif
7320 -
7321 -
7322 -/* --------------------------------------------------------------------
7323 - *  NAND / SmartMedia
7324 - * -------------------------------------------------------------------- */
7325 -
7326 -#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
7327 -static struct at91_nand_data nand_data;
7328 -
7329 -static struct resource at91_nand_resources[] = {
7330 -       {
7331 -               .start  = AT91_SMARTMEDIA_BASE,
7332 -               .end    = AT91_SMARTMEDIA_BASE + SZ_8M - 1,
7333 -               .flags  = IORESOURCE_MEM,
7334 -       }
7335 -};
7336 -
7337 -static struct platform_device at91_nand_device = {
7338 -       .name           = "at91_nand",
7339 -       .id             = -1,
7340 -       .dev            = {
7341 -                               .platform_data  = &nand_data,
7342 -       },
7343 -       .resource       = at91_nand_resources,
7344 -       .num_resources  = ARRAY_SIZE(at91_nand_resources),
7345 -};
7346 -
7347 -void __init at91_add_device_nand(struct at91_nand_data *data)
7348 -{
7349 -       if (!data)
7350 -               return;
7351 -
7352 -       /* enable pin */
7353 -       if (data->enable_pin)
7354 -               at91_set_gpio_output(data->enable_pin, 1);
7355 -
7356 -       /* ready/busy pin */
7357 -       if (data->rdy_pin)
7358 -               at91_set_gpio_input(data->rdy_pin, 1);
7359 -
7360 -       /* card detect pin */
7361 -       if (data->det_pin)
7362 -               at91_set_gpio_input(data->det_pin, 1);
7363 -
7364 -       at91_set_A_periph(AT91_PIN_PC1, 0);             /* SMOE */
7365 -       at91_set_A_periph(AT91_PIN_PC3, 0);             /* SMWE */
7366 -
7367 -       nand_data = *data;
7368 -       platform_device_register(&at91_nand_device);
7369 -}
7370 -#else
7371 -void __init at91_add_device_nand(struct at91_nand_data *data) {}
7372 -#endif
7373 -
7374 -
7375 -/* --------------------------------------------------------------------
7376 - *  TWI (i2c)
7377 - * -------------------------------------------------------------------- */
7378 -
7379 -#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
7380 -static struct platform_device at91rm9200_twi_device = {
7381 -       .name           = "at91_i2c",
7382 -       .id             = -1,
7383 -       .num_resources  = 0,
7384 -};
7385 -
7386 -void __init at91_add_device_i2c(void)
7387 -{
7388 -       /* pins used for TWI interface */
7389 -       at91_set_A_periph(AT91_PIN_PA25, 0);            /* TWD */
7390 -       at91_set_multi_drive(AT91_PIN_PA25, 1);
7391 -
7392 -       at91_set_A_periph(AT91_PIN_PA26, 0);            /* TWCK */
7393 -       at91_set_multi_drive(AT91_PIN_PA26, 1);
7394 -
7395 -       platform_device_register(&at91rm9200_twi_device);
7396 -}
7397 -#else
7398 -void __init at91_add_device_i2c(void) {}
7399 -#endif
7400 -
7401 -
7402 -/* --------------------------------------------------------------------
7403 - *  SPI
7404 - * -------------------------------------------------------------------- */
7405 -
7406 -#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE)
7407 -static u64 spi_dmamask = 0xffffffffUL;
7408 -
7409 -static struct resource at91_spi_resources[] = {
7410 -       [0] = {
7411 -               .start  = AT91RM9200_BASE_SPI,
7412 -               .end    = AT91RM9200_BASE_SPI + SZ_16K - 1,
7413 -               .flags  = IORESOURCE_MEM,
7414 -       },
7415 -       [1] = {
7416 -               .start  = AT91RM9200_ID_SPI,
7417 -               .end    = AT91RM9200_ID_SPI,
7418 -               .flags  = IORESOURCE_IRQ,
7419 -       },
7420 -};
7421 -
7422 -static struct platform_device at91rm9200_spi_device = {
7423 -       .name           = "at91_spi",
7424 -       .id             = 0,
7425 -       .dev            = {
7426 -               .dma_mask               = &spi_dmamask,
7427 -               .coherent_dma_mask      = 0xffffffff,
7428 -       },
7429 -       .resource       = at91_spi_resources,
7430 -       .num_resources  = ARRAY_SIZE(at91_spi_resources),
7431 -};
7432 -
7433 -static const unsigned at91_spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
7434 -
7435 -void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
7436 -{
7437 -       int i;
7438 -       unsigned long cs_pin;
7439 -
7440 -       at91_set_A_periph(AT91_PIN_PA0, 0);     /* MISO */
7441 -       at91_set_A_periph(AT91_PIN_PA1, 0);     /* MOSI */
7442 -       at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPCK */
7443 -
7444 -       /* Enable SPI chip-selects */
7445 -       for (i = 0; i < nr_devices; i++) {
7446 -               if (devices[i].controller_data)
7447 -                       cs_pin = (unsigned long) devices[i].controller_data;
7448 -               else
7449 -                       cs_pin = at91_spi_standard_cs[devices[i].chip_select];
7450 -
7451 -#ifdef CONFIG_SPI_AT91_MANUAL_CS
7452 -               at91_set_gpio_output(cs_pin, 1);
7453 -#else
7454 -               at91_set_A_periph(cs_pin, 0);
7455 -#endif
7456 -
7457 -               /* pass chip-select pin to driver */
7458 -               devices[i].controller_data = (void *) cs_pin;
7459 -       }
7460 -
7461 -       spi_register_board_info(devices, nr_devices);
7462 -       at91_clock_associate("spi0_clk", &at91rm9200_spi_device.dev, "spi");
7463 -       platform_device_register(&at91rm9200_spi_device);
7464 -}
7465 -#else
7466 -void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
7467 -#endif
7468 -
7469 -
7470 -/* --------------------------------------------------------------------
7471 - *  RTC
7472 - * -------------------------------------------------------------------- */
7473 -
7474 -#if defined(CONFIG_RTC_DRV_AT91) || defined(CONFIG_RTC_DRV_AT91_MODULE)
7475 -static struct platform_device at91rm9200_rtc_device = {
7476 -       .name           = "at91_rtc",
7477 -       .id             = -1,
7478 -       .num_resources  = 0,
7479 -};
7480 -
7481 -static void __init at91_add_device_rtc(void)
7482 -{
7483 -       platform_device_register(&at91rm9200_rtc_device);
7484 -}
7485 -#else
7486 -static void __init at91_add_device_rtc(void) {}
7487 -#endif
7488 -
7489 -
7490 -/* --------------------------------------------------------------------
7491 - *  Watchdog
7492 - * -------------------------------------------------------------------- */
7493 -
7494 -#if defined(CONFIG_AT91_WATCHDOG) || defined(CONFIG_AT91_WATCHDOG_MODULE)
7495 -static struct platform_device at91rm9200_wdt_device = {
7496 -       .name           = "at91_wdt",
7497 -       .id             = -1,
7498 -       .num_resources  = 0,
7499 -};
7500 -
7501 -static void __init at91_add_device_watchdog(void)
7502 -{
7503 -       platform_device_register(&at91rm9200_wdt_device);
7504 -}
7505 -#else
7506 -static void __init at91_add_device_watchdog(void) {}
7507 -#endif
7508 -
7509 -
7510 -/* --------------------------------------------------------------------
7511 - *  LEDs
7512 - * -------------------------------------------------------------------- */
7513 -
7514 -#if defined(CONFIG_LEDS)
7515 -u8 at91_leds_cpu;
7516 -u8 at91_leds_timer;
7517 -
7518 -void __init at91_init_leds(u8 cpu_led, u8 timer_led)
7519 -{
7520 -       at91_leds_cpu   = cpu_led;
7521 -       at91_leds_timer = timer_led;
7522 -}
7523 -#else
7524 -void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
7525 -#endif
7526 -
7527 -
7528 -/* --------------------------------------------------------------------
7529 - *  UART
7530 - * -------------------------------------------------------------------- */
7531 -
7532 -#if defined(CONFIG_SERIAL_ATMEL)
7533 -static struct resource dbgu_resources[] = {
7534 -       [0] = {
7535 -               .start  = AT91_VA_BASE_SYS + AT91_DBGU,
7536 -               .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
7537 -               .flags  = IORESOURCE_MEM,
7538 -       },
7539 -       [1] = {
7540 -               .start  = AT91_ID_SYS,
7541 -               .end    = AT91_ID_SYS,
7542 -               .flags  = IORESOURCE_IRQ,
7543 -       },
7544 -};
7545 -
7546 -static struct atmel_uart_data dbgu_data = {
7547 -       .use_dma_tx     = 0,
7548 -       .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
7549 -       .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
7550 -};
7551 -
7552 -static struct platform_device at91rm9200_dbgu_device = {
7553 -       .name           = "atmel_usart",
7554 -       .id             = 0,
7555 -       .dev            = {
7556 -                               .platform_data  = &dbgu_data,
7557 -                               .coherent_dma_mask = 0xffffffff,
7558 -       },
7559 -       .resource       = dbgu_resources,
7560 -       .num_resources  = ARRAY_SIZE(dbgu_resources),
7561 -};
7562 -
7563 -static inline void configure_dbgu_pins(void)
7564 -{
7565 -       at91_set_A_periph(AT91_PIN_PA30, 0);            /* DRXD */
7566 -       at91_set_A_periph(AT91_PIN_PA31, 1);            /* DTXD */
7567 -}
7568 -
7569 -static struct resource uart0_resources[] = {
7570 -       [0] = {
7571 -               .start  = AT91RM9200_BASE_US0,
7572 -               .end    = AT91RM9200_BASE_US0 + SZ_16K - 1,
7573 -               .flags  = IORESOURCE_MEM,
7574 -       },
7575 -       [1] = {
7576 -               .start  = AT91RM9200_ID_US0,
7577 -               .end    = AT91RM9200_ID_US0,
7578 -               .flags  = IORESOURCE_IRQ,
7579 -       },
7580 -};
7581 -
7582 -static struct atmel_uart_data uart0_data = {
7583 -       .use_dma_tx     = 1,
7584 -       .use_dma_rx     = 1,
7585 -};
7586 -
7587 -static struct platform_device at91rm9200_uart0_device = {
7588 -       .name           = "atmel_usart",
7589 -       .id             = 1,
7590 -       .dev            = {
7591 -                               .platform_data  = &uart0_data,
7592 -                               .coherent_dma_mask = 0xffffffff,
7593 -       },
7594 -       .resource       = uart0_resources,
7595 -       .num_resources  = ARRAY_SIZE(uart0_resources),
7596 -};
7597 -
7598 -static inline void configure_usart0_pins(void)
7599 -{
7600 -       at91_set_A_periph(AT91_PIN_PA17, 1);            /* TXD0 */
7601 -       at91_set_A_periph(AT91_PIN_PA18, 0);            /* RXD0 */
7602 -       at91_set_A_periph(AT91_PIN_PA20, 0);            /* CTS0 */
7603 -
7604 -       /*
7605 -        * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
7606 -        *  We need to drive the pin manually.  Default is off (RTS is active low).
7607 -        */
7608 -       at91_set_gpio_output(AT91_PIN_PA21, 1);
7609 -}
7610 -
7611 -static struct resource uart1_resources[] = {
7612 -       [0] = {
7613 -               .start  = AT91RM9200_BASE_US1,
7614 -               .end    = AT91RM9200_BASE_US1 + SZ_16K - 1,
7615 -               .flags  = IORESOURCE_MEM,
7616 -       },
7617 -       [1] = {
7618 -               .start  = AT91RM9200_ID_US1,
7619 -               .end    = AT91RM9200_ID_US1,
7620 -               .flags  = IORESOURCE_IRQ,
7621 -       },
7622 -};
7623 -
7624 -static struct atmel_uart_data uart1_data = {
7625 -       .use_dma_tx     = 1,
7626 -       .use_dma_rx     = 1,
7627 -};
7628 -
7629 -static struct platform_device at91rm9200_uart1_device = {
7630 -       .name           = "atmel_usart",
7631 -       .id             = 2,
7632 -       .dev            = {
7633 -                               .platform_data  = &uart1_data,
7634 -                               .coherent_dma_mask = 0xffffffff,
7635 -       },
7636 -       .resource       = uart1_resources,
7637 -       .num_resources  = ARRAY_SIZE(uart1_resources),
7638 -};
7639 -
7640 -static inline void configure_usart1_pins(void)
7641 -{
7642 -       at91_set_A_periph(AT91_PIN_PB18, 0);            /* RI1 */
7643 -       at91_set_A_periph(AT91_PIN_PB19, 0);            /* DTR1 */
7644 -       at91_set_A_periph(AT91_PIN_PB20, 1);            /* TXD1 */
7645 -       at91_set_A_periph(AT91_PIN_PB21, 0);            /* RXD1 */
7646 -       at91_set_A_periph(AT91_PIN_PB23, 0);            /* DCD1 */
7647 -       at91_set_A_periph(AT91_PIN_PB24, 0);            /* CTS1 */
7648 -       at91_set_A_periph(AT91_PIN_PB25, 0);            /* DSR1 */
7649 -       at91_set_A_periph(AT91_PIN_PB26, 0);            /* RTS1 */
7650 -}
7651 -
7652 -static struct resource uart2_resources[] = {
7653 -       [0] = {
7654 -               .start  = AT91RM9200_BASE_US2,
7655 -               .end    = AT91RM9200_BASE_US2 + SZ_16K - 1,
7656 -               .flags  = IORESOURCE_MEM,
7657 -       },
7658 -       [1] = {
7659 -               .start  = AT91RM9200_ID_US2,
7660 -               .end    = AT91RM9200_ID_US2,
7661 -               .flags  = IORESOURCE_IRQ,
7662 -       },
7663 -};
7664 -
7665 -static struct atmel_uart_data uart2_data = {
7666 -       .use_dma_tx     = 1,
7667 -       .use_dma_rx     = 1,
7668 -};
7669 -
7670 -static struct platform_device at91rm9200_uart2_device = {
7671 -       .name           = "atmel_usart",
7672 -       .id             = 3,
7673 -       .dev            = {
7674 -                               .platform_data  = &uart2_data,
7675 -                               .coherent_dma_mask = 0xffffffff,
7676 -       },
7677 -       .resource       = uart2_resources,
7678 -       .num_resources  = ARRAY_SIZE(uart2_resources),
7679 -};
7680 -
7681 -static inline void configure_usart2_pins(void)
7682 -{
7683 -       at91_set_A_periph(AT91_PIN_PA22, 0);            /* RXD2 */
7684 -       at91_set_A_periph(AT91_PIN_PA23, 1);            /* TXD2 */
7685 -}
7686 -
7687 -static struct resource uart3_resources[] = {
7688 -       [0] = {
7689 -               .start  = AT91RM9200_BASE_US3,
7690 -               .end    = AT91RM9200_BASE_US3 + SZ_16K - 1,
7691 -               .flags  = IORESOURCE_MEM,
7692 -       },
7693 -       [1] = {
7694 -               .start  = AT91RM9200_ID_US3,
7695 -               .end    = AT91RM9200_ID_US3,
7696 -               .flags  = IORESOURCE_IRQ,
7697 -       },
7698 -};
7699 -
7700 -static struct atmel_uart_data uart3_data = {
7701 -       .use_dma_tx     = 1,
7702 -       .use_dma_rx     = 1,
7703 -};
7704 -
7705 -static struct platform_device at91rm9200_uart3_device = {
7706 -       .name           = "atmel_usart",
7707 -       .id             = 4,
7708 -       .dev            = {
7709 -                               .platform_data  = &uart3_data,
7710 -                               .coherent_dma_mask = 0xffffffff,
7711 -       },
7712 -       .resource       = uart3_resources,
7713 -       .num_resources  = ARRAY_SIZE(uart3_resources),
7714 -};
7715 -
7716 -static inline void configure_usart3_pins(void)
7717 -{
7718 -       at91_set_B_periph(AT91_PIN_PA5, 1);             /* TXD3 */
7719 -       at91_set_B_periph(AT91_PIN_PA6, 0);             /* RXD3 */
7720 -}
7721 -
7722 -struct platform_device *at91_uarts[ATMEL_MAX_UART];    /* the UARTs to use */
7723 -struct platform_device *atmel_default_console_device;  /* the serial console device */
7724 -
7725 -void __init at91_init_serial(struct at91_uart_config *config)
7726 -{
7727 -       int i;
7728 -
7729 -       /* Fill in list of supported UARTs */
7730 -       for (i = 0; i < config->nr_tty; i++) {
7731 -               switch (config->tty_map[i]) {
7732 -                       case 0:
7733 -                               configure_usart0_pins();
7734 -                               at91_uarts[i] = &at91rm9200_uart0_device;
7735 -                               at91_clock_associate("usart0_clk", &at91rm9200_uart0_device.dev, "usart");
7736 -                               break;
7737 -                       case 1:
7738 -                               configure_usart1_pins();
7739 -                               at91_uarts[i] = &at91rm9200_uart1_device;
7740 -                               at91_clock_associate("usart1_clk", &at91rm9200_uart1_device.dev, "usart");
7741 -                               break;
7742 -                       case 2:
7743 -                               configure_usart2_pins();
7744 -                               at91_uarts[i] = &at91rm9200_uart2_device;
7745 -                               at91_clock_associate("usart2_clk", &at91rm9200_uart2_device.dev, "usart");
7746 -                               break;
7747 -                       case 3:
7748 -                               configure_usart3_pins();
7749 -                               at91_uarts[i] = &at91rm9200_uart3_device;
7750 -                               at91_clock_associate("usart3_clk", &at91rm9200_uart3_device.dev, "usart");
7751 -                               break;
7752 -                       case 4:
7753 -                               configure_dbgu_pins();
7754 -                               at91_uarts[i] = &at91rm9200_dbgu_device;
7755 -                               at91_clock_associate("mck", &at91rm9200_dbgu_device.dev, "usart");
7756 -                               break;
7757 -                       default:
7758 -                               continue;
7759 -               }
7760 -               at91_uarts[i]->id = i;          /* update ID number to mapped ID */
7761 -       }
7762 -
7763 -       /* Set serial console device */
7764 -       if (config->console_tty < ATMEL_MAX_UART)
7765 -               atmel_default_console_device = at91_uarts[config->console_tty];
7766 -       if (!atmel_default_console_device)
7767 -               printk(KERN_INFO "AT91: No default serial console defined.\n");
7768 -}
7769 -
7770 -void __init at91_add_device_serial(void)
7771 -{
7772 -       int i;
7773 -
7774 -       for (i = 0; i < ATMEL_MAX_UART; i++) {
7775 -               if (at91_uarts[i])
7776 -                       platform_device_register(at91_uarts[i]);
7777 -       }
7778 -}
7779 -#else
7780 -void __init at91_init_serial(struct at91_uart_config *config) {}
7781 -void __init at91_add_device_serial(void) {}
7782 -#endif
7783 -
7784 -
7785 -/* -------------------------------------------------------------------- */
7786 -
7787 -/*
7788 - * These devices are always present and don't need any board-specific
7789 - * setup.
7790 - */
7791 -static int __init at91_add_standard_devices(void)
7792 -{
7793 -       at91_add_device_rtc();
7794 -       at91_add_device_watchdog();
7795 -       return 0;
7796 -}
7797 -
7798 -arch_initcall(at91_add_standard_devices);
7799 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/generic.h linux-2.6.19/arch/arm/mach-at91rm9200/generic.h
7800 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/generic.h       Mon Dec  4 16:39:29 2006
7801 +++ linux-2.6.19/arch/arm/mach-at91rm9200/generic.h     Wed Nov 15 09:01:27 2006
7802 @@ -10,14 +10,19 @@
7803
7804   /* Processors */
7805  extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks);
7806 +extern void __init at91sam9260_initialize(unsigned long main_clock);
7807 +extern void __init at91sam9261_initialize(unsigned long main_clock);
7808
7809   /* Interrupts */
7810  extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
7811 +extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
7812 +extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
7813  extern void __init at91_aic_init(unsigned int priority[]);
7814
7815   /* Timer */
7816  struct sys_timer;
7817  extern struct sys_timer at91rm9200_timer;
7818 +extern struct sys_timer at91sam926x_timer;
7819
7820   /* Clocks */
7821  extern int __init at91_clock_init(unsigned long main_clock);
7822 @@ -39,3 +44,6 @@
7823  };
7824  extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
7825  extern void __init at91_gpio_irq_setup(void);
7826 +
7827 +extern void (*at91_arch_reset)(void);
7828 +extern int at91_extern_irq;
7829 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/gpio.c linux-2.6.19/arch/arm/mach-at91rm9200/gpio.c
7830 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/gpio.c  Mon Dec  4 16:39:29 2006
7831 +++ linux-2.6.19/arch/arm/mach-at91rm9200/gpio.c        Wed Nov  1 12:37:25 2006
7832 @@ -19,6 +19,8 @@
7833
7834  #include <asm/io.h>
7835  #include <asm/hardware.h>
7836 +#include <asm/arch/at91_pio.h>
7837 +#include <asm/arch/at91_pmc.h>
7838  #include <asm/arch/gpio.h>
7839
7840  #include "generic.h"
7841 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/ics1523.c linux-2.6.19/arch/arm/mach-at91rm9200/ics1523.c
7842 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/ics1523.c       Thu Jan  1 02:00:00 1970
7843 +++ linux-2.6.19/arch/arm/mach-at91rm9200/ics1523.c     Tue Oct 24 14:59:00 2006
7844 @@ -0,0 +1,227 @@
7845 +/*
7846 + * arch/arm/mach-at91rm9200/ics1523.c
7847 + *
7848 + *  Copyright (C) 2003 ATMEL Rousset
7849 + *
7850 + * This program is free software; you can redistribute it and/or modify
7851 + * it under the terms of the GNU General Public License as published by
7852 + * the Free Software Foundation; either version 2 of the License, or
7853 + * (at your option) any later version.
7854 + *
7855 + * This program is distributed in the hope that it will be useful,
7856 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7857 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
7858 + * GNU General Public License for more details.
7859 + *
7860 + * You should have received a copy of the GNU General Public License
7861 + * along with this program; if not, write to the Free Software
7862 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
7863 + */
7864 +
7865 +#include <asm/hardware.h>
7866 +#include <asm/io.h>
7867 +#include <linux/delay.h>
7868 +
7869 +#include <asm/arch/ics1523.h>
7870 +#include <asm/arch/at91_twi.h>
7871 +#include <asm/arch/gpio.h>
7872 +
7873 +/* TWI Errors */
7874 +#define        AT91_TWI_ERROR  (AT91_TWI_NACK | AT91_TWI_UNRE | AT91_TWI_OVRE)
7875 +
7876 +
7877 +//-----------------------------------------------------------------------------
7878 +//
7879 +// TWI Register access
7880 +//
7881 +//-----------------------------------------------------------------------------
7882 +
7883 +static inline unsigned long at91_twi_read(unsigned int reg)
7884 +{
7885 +       void __iomem *twi_base = (void __iomem *)AT91_VA_BASE_TWI;
7886 +
7887 +       return __raw_readl(twi_base + reg);
7888 +}
7889 +
7890 +static inline void at91_twi_write(unsigned int reg, unsigned long value)
7891 +{
7892 +       void __iomem *twi_base = (void __iomem *)AT91_VA_BASE_TWI;
7893 +
7894 +       __raw_writel(value, twi_base + reg);
7895 +}
7896 +
7897 +//-----------------------------------------------------------------------------
7898 +//
7899 +// Initialization of TWI CLOCK
7900 +//
7901 +//-----------------------------------------------------------------------------
7902 +
7903 +static void AT91F_SetTwiClock(unsigned int mck_khz)
7904 +{
7905 +       int sclock;
7906 +
7907 +       /* Here, CKDIV = 1 and CHDIV = CLDIV  ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
7908 +       sclock = (10*mck_khz /ICS_TRANSFER_RATE);
7909 +       if (sclock % 10 >= 5)
7910 +               sclock = (sclock /10) - 5;
7911 +       else
7912 +               sclock = (sclock /10)- 6;
7913 +       sclock = (sclock + (4 - sclock %4)) >> 2;       // div 4
7914 +
7915 +       at91_twi_write(AT91_TWI_CWGR, 0x00010000 | sclock | (sclock << 8));
7916 +}
7917 +
7918 +//-----------------------------------------------------------------------------
7919 +//
7920 +// Read a byte with TWI Interface from the Clock Generator ICS1523
7921 +//
7922 +//-----------------------------------------------------------------------------
7923 +
7924 +static int AT91F_ICS1523_ReadByte(unsigned char reg_address, unsigned char *data_in)
7925 +{
7926 +       int Status, nb_trial;
7927 +
7928 +       at91_twi_write(AT91_TWI_MMR, AT91_TWI_MREAD | AT91_TWI_IADRSZ_1 | ((ICS_ADD << 16) & AT91_TWI_DADR));
7929 +       at91_twi_write(AT91_TWI_IADR, reg_address);
7930 +       at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
7931 +
7932 +       // Program temporizing period (300us)
7933 +       udelay(300);
7934 +
7935 +       // Wait TXcomplete ...
7936 +       nb_trial = 0;
7937 +       Status = at91_twi_read(AT91_TWI_SR);
7938 +       while (!(Status & AT91_TWI_TXCOMP) && (nb_trial < 10)) {
7939 +               nb_trial++;
7940 +               Status = at91_twi_read(AT91_TWI_SR);
7941 +       }
7942 +
7943 +       if (Status & AT91_TWI_TXCOMP) {
7944 +               *data_in = (unsigned char) at91_twi_read(AT91_TWI_RHR);
7945 +               return ((int) ICS1523_ACCESS_OK);
7946 +       }
7947 +       return ((int) ICS1523_ACCESS_ERROR);
7948 +}
7949 +
7950 +//-----------------------------------------------------------------------------
7951 +//
7952 +// Write a byte with TWI Interface to the Clock Generator ICS1523
7953 +//
7954 +//-----------------------------------------------------------------------------
7955 +
7956 +static int AT91F_ICS1523_WriteByte(unsigned char reg_address, unsigned char data_out)
7957 +{
7958 +       int Status, nb_trial;
7959 +
7960 +       at91_twi_write(AT91_TWI_MMR, AT91_TWI_IADRSZ_1 | ((ICS_ADD << 16) & AT91_TWI_DADR));
7961 +       at91_twi_write(AT91_TWI_IADR, reg_address);
7962 +       at91_twi_write(AT91_TWI_THR, data_out);
7963 +       at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
7964 +
7965 +       // Program temporizing period (300us)
7966 +       udelay(300);
7967 +
7968 +       nb_trial = 0;
7969 +       Status = at91_twi_read(AT91_TWI_SR);
7970 +       while (!(Status & AT91_TWI_TXCOMP) && (nb_trial < 10)) {
7971 +               nb_trial++;
7972 +               if (Status & AT91_TWI_ERROR) {
7973 +                       // Si Under run OR NACK Start again
7974 +                       at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
7975 +
7976 +                       //  Program temporizing period (300us)
7977 +                       udelay(300);
7978 +               }
7979 +               Status = at91_twi_read(AT91_TWI_SR);
7980 +       };
7981 +
7982 +       if (Status & AT91_TWI_TXCOMP)
7983 +               return ((int) ICS1523_ACCESS_OK);
7984 +       else
7985 +               return ((int) ICS1523_ACCESS_ERROR);
7986 +}
7987 +
7988 +//-----------------------------------------------------------------------------
7989 +//
7990 +// Initialization of the Clock Generator ICS1523
7991 +//
7992 +//-----------------------------------------------------------------------------
7993 +
7994 +int AT91F_ICS1523_clockinit(void)
7995 +{
7996 +       int             ack, nb_trial, error_status;
7997 +       unsigned int    status = 0xffffffff;
7998 +       struct clk      *twi_clk;
7999 +
8000 +       error_status = (int) ICS1523_ACCESS_OK;
8001 +
8002 +       /* pins used for TWI interface */
8003 +       at91_set_A_periph(AT91_PIN_PA25, 0);            /* TWD */
8004 +       at91_set_multi_drive(AT91_PIN_PA25, 1);
8005 +       at91_set_A_periph(AT91_PIN_PA26, 0);            /* TWCK */
8006 +       at91_set_multi_drive(AT91_PIN_PA26, 1);
8007 +
8008 +       // Enable the TWI clock.
8009 +       twi_clk = clk_get(NULL, "twi_clk");
8010 +       if (IS_ERR(twi_clk))
8011 +               return ICS1523_ACCESS_ERROR;
8012 +       clk_enable(twi_clk);
8013 +
8014 +       // Disable interrupts
8015 +       at91_twi_write(AT91_TWI_IDR, -1);
8016 +
8017 +       // Reset peripheral
8018 +       at91_twi_write(AT91_TWI_CR, AT91_TWI_SWRST);
8019 +
8020 +       // Set Master mode
8021 +       at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN);
8022 +
8023 +       // Set TWI Clock Waveform Generator Register
8024 +       AT91F_SetTwiClock(60000);     // MCK in KHz = 60000 KHz
8025 +
8026 +       // ICS1523 Initialisation
8027 +       ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_ICR, (unsigned char) 0);
8028 +       error_status |= ack;
8029 +       ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_OE, (unsigned char) (ICS_OEF | ICS_OET2 | ICS_OETCK));
8030 +       error_status |= ack;
8031 +       ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_OD, (unsigned char) (ICS_INSEL | 0x7F));
8032 +       error_status |= ack;
8033 +       ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_DPAO, (unsigned char) 0);
8034 +       error_status |= ack;
8035 +
8036 +       nb_trial = 0;
8037 +       do {
8038 +               nb_trial++;
8039 +               ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_ICR, (unsigned char) (ICS_ENDLS | ICS_ENPLS | ICS_PDEN /*| ICS_FUNCSEL*/));
8040 +               error_status |= ack;
8041 +               ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_LCR, (unsigned char) (ICS_PSD | ICS_PFD));
8042 +               error_status |= ack;
8043 +               ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_FD0, (unsigned char) 0x39) ; /* 0x7A */
8044 +               error_status |= ack;
8045 +               ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_FD1, (unsigned char) 0x00);
8046 +               error_status |= ack;
8047 +               ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_SWRST, (unsigned char) (ICS_PLLR));
8048 +               error_status |= ack;
8049 +
8050 +               // Program 1ms temporizing period
8051 +               mdelay(1);
8052 +
8053 +               AT91F_ICS1523_ReadByte ((unsigned char) ICS_SR, (char *)&status);
8054 +       } while (!((unsigned int) status & (unsigned int) ICS_PLLLOCK) && (nb_trial < 10));
8055 +
8056 +       ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_DPAC, (unsigned char) 0x03) ; /* 0x01 */
8057 +       error_status |= ack;
8058 +       ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_SWRST, (unsigned char) (ICS_DPAR));
8059 +       error_status |= ack;
8060 +
8061 +       /* Program 1ms temporizing period */
8062 +       mdelay(1);
8063 +
8064 +       ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_DPAO, (unsigned char) 0x00);
8065 +       error_status |= ack;
8066 +
8067 +       /* Program 1ms temporizing period */
8068 +       mdelay(1);
8069 +
8070 +       return (error_status);
8071 +}
8072 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/irq.c linux-2.6.19/arch/arm/mach-at91rm9200/irq.c
8073 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/irq.c   Mon Dec  4 16:39:29 2006
8074 +++ linux-2.6.19/arch/arm/mach-at91rm9200/irq.c Wed Nov  1 12:40:39 2006
8075 @@ -47,6 +47,10 @@
8076         at91_sys_write(AT91_AIC_IECR, 1 << irq);
8077  }
8078
8079 +unsigned int at91_extern_irq;
8080 +
8081 +#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
8082 +
8083  static int at91_aic_set_type(unsigned irq, unsigned type)
8084  {
8085         unsigned int smr, srctype;
8086 @@ -59,14 +63,16 @@
8087                 srctype = AT91_AIC_SRCTYPE_RISING;
8088                 break;
8089         case IRQT_LOW:
8090 -               if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0))  /* only supported on external interrupts */
8091 +               if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))         /* only supported on external interrupts */
8092 +                       srctype = AT91_AIC_SRCTYPE_LOW;
8093 +               else
8094                         return -EINVAL;
8095 -               srctype = AT91_AIC_SRCTYPE_LOW;
8096                 break;
8097         case IRQT_FALLING:
8098 -               if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0))  /* only supported on external interrupts */
8099 +               if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))         /* only supported on external interrupts */
8100 +                       srctype = AT91_AIC_SRCTYPE_FALLING;
8101 +               else
8102                         return -EINVAL;
8103 -               srctype = AT91_AIC_SRCTYPE_FALLING;
8104                 break;
8105         default:
8106                 return -EINVAL;
8107 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/pm.c linux-2.6.19/arch/arm/mach-at91rm9200/pm.c
8108 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/pm.c    Mon Dec  4 16:39:29 2006
8109 +++ linux-2.6.19/arch/arm/mach-at91rm9200/pm.c  Thu Nov 16 11:51:41 2006
8110 @@ -26,7 +26,10 @@
8111  #include <asm/mach/irq.h>
8112  #include <asm/mach-types.h>
8113
8114 +#include <asm/arch/at91_pmc.h>
8115 +#include <asm/arch/at91rm9200_mc.h>
8116  #include <asm/arch/gpio.h>
8117 +#include <asm/arch/cpu.h>
8118
8119  #include "generic.h"
8120
8121 @@ -60,6 +63,7 @@
8122   * Verify that all the clocks are correct before entering
8123   * slow-clock mode.
8124   */
8125 +#warning "SAM9260 only has 3 programmable clocks."
8126  static int at91_pm_verify_clocks(void)
8127  {
8128         unsigned long scsr;
8129 @@ -68,9 +72,15 @@
8130         scsr = at91_sys_read(AT91_PMC_SCSR);
8131
8132         /* USB must not be using PLLB */
8133 -       if ((scsr & (AT91_PMC_UHP | AT91_PMC_UDP)) != 0) {
8134 -               pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
8135 -               return 0;
8136 +       if (cpu_is_at91rm9200()) {
8137 +               if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) {
8138 +                       pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
8139 +                       return 0;
8140 +               }
8141 +       } else if (cpu_is_at91sam9261()) {
8142 +#warning "Check SAM9261 USB clocks"
8143 +       } else if (cpu_is_at91sam9260()) {
8144 +#warning "Check SAM9260 USB clocks"
8145         }
8146
8147  #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
8148 @@ -112,7 +122,6 @@
8149  static void (*slow_clock)(void);
8150
8151
8152 -
8153  static int at91_pm_enter(suspend_state_t state)
8154  {
8155         at91_gpio_suspend();
8156 @@ -123,13 +132,7 @@
8157                         (at91_sys_read(AT91_PMC_PCSR)
8158                                         | (1 << AT91_ID_FIQ)
8159                                         | (1 << AT91_ID_SYS)
8160 -                                       | (1 << AT91RM9200_ID_IRQ0)
8161 -                                       | (1 << AT91RM9200_ID_IRQ1)
8162 -                                       | (1 << AT91RM9200_ID_IRQ2)
8163 -                                       | (1 << AT91RM9200_ID_IRQ3)
8164 -                                       | (1 << AT91RM9200_ID_IRQ4)
8165 -                                       | (1 << AT91RM9200_ID_IRQ5)
8166 -                                       | (1 << AT91RM9200_ID_IRQ6))
8167 +                                       | (at91_extern_irq))
8168                                 & at91_sys_read(AT91_AIC_IMR),
8169                         state);
8170
8171 @@ -203,16 +206,23 @@
8172         .enter          = at91_pm_enter,
8173  };
8174
8175 +#ifdef CONFIG_AT91_SLOW_CLOCK
8176 +extern void at91rm9200_slow_clock(void);
8177 +extern u32 at91rm9200_slow_clock_sz;
8178 +#endif
8179 +
8180  static int __init at91_pm_init(void)
8181  {
8182 -       printk("AT91: Power Management\n");
8183 -
8184 -#ifdef CONFIG_AT91_PM_SLOW_CLOCK
8185 -       /* REVISIT allocations of SRAM should be dynamically managed.
8186 +#ifdef CONFIG_AT91_SLOW_CLOCK
8187 +       /*
8188 +        * REVISIT allocations of SRAM should be dynamically managed.
8189          * FIQ handlers and other components will want SRAM/TCM too...
8190          */
8191 -       slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K));
8192 +       slow_clock = (void *) (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE + (3 * SZ_4K));
8193         memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz);
8194 +       printk("AT91: Power Management (with slow clock mode)\n");
8195 +#else
8196 +       printk("AT91: Power Management\n");
8197  #endif
8198
8199         /* Disable SDRAM low-power mode.  Cannot be used with self-refresh. */
8200 diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/pm_slowclock.S linux-2.6.19/arch/arm/mach-at91rm9200/pm_slowclock.S
8201 --- linux-2.6.19-final/arch/arm/mach-at91rm9200/pm_slowclock.S  Thu Jan  1 02:00:00 1970
8202 +++ linux-2.6.19/arch/arm/mach-at91rm9200/pm_slowclock.S        Thu Nov 16 11:47:10 2006
8203 @@ -0,0 +1,170 @@
8204 +/*
8205 + * arch/arm/mach-at91rm9200/pm_slow_clock.S
8206 + *
8207 + *  Copyright (C) 2006 Savin Zlobec
8208 + *
8209 + * This program is free software; you can redistribute it and/or modify
8210 + * it under the terms of the GNU General Public License version 2 as
8211 + * published by the Free Software Foundation.
8212 + *
8213 + */
8214 +
8215 +#include <linux/linkage.h>
8216 +#include <asm/hardware.h>
8217 +
8218 +#define MCKRDY_TIMEOUT         1000
8219 +#define MOSCRDY_TIMEOUT        1000
8220 +#define PLLALOCK_TIMEOUT       1000
8221 +
8222 +       .macro wait_mckrdy
8223 +       mov     r2, #MCKRDY_TIMEOUT
8224 +1:     sub     r2, r2, #1
8225 +       cmp     r2, #0
8226 +       beq     2f
8227 +       ldr     r3, [r1, #AT91_PMC_SR]
8228 +       tst     r3, #AT91_PMC_MCKRDY
8229 +       beq     1b
8230 +2:
8231 +       .endm
8232 +
8233 +       .macro wait_moscrdy
8234 +       mov     r2, #MOSCRDY_TIMEOUT
8235 +1:     sub     r2, r2, #1
8236 +       cmp     r2, #0
8237 +       beq     2f
8238 +       ldr     r3, [r1, #AT91_PMC_SR]
8239 +       tst     r3, #AT91_PMC_MOSCS
8240 +       beq     1b
8241 +2:
8242 +       .endm
8243 +
8244 +       .macro wait_pllalock
8245 +       mov     r2, #PLLALOCK_TIMEOUT
8246 +1:     sub     r2, r2, #1
8247 +       cmp     r2, #0
8248 +       beq     2f
8249 +       ldr     r3, [r1, #AT91_PMC_SR]
8250 +       tst     r3, #AT91_PMC_LOCKA
8251 +       beq     1b
8252 +2:
8253 +       .endm
8254 +
8255 +       .macro wait_plladis
8256 +       mov     r2, #PLLALOCK_TIMEOUT
8257 +1:     sub     r2, r2, #1
8258 +       cmp     r2, #0
8259 +       beq     2f
8260 +       ldr     r3, [r1, #AT91_PMC_SR]
8261 +       tst     r3, #AT91_PMC_LOCKA
8262 +       bne     1b
8263 +2:
8264 +       .endm
8265 +
8266 +       .text
8267 +
8268 +ENTRY(at91rm9200_slow_clock)
8269 +
8270 +       ldr     r1, .at91_va_base_sys
8271 +
8272 +       /* Put SDRAM in self refresh mode */
8273 +
8274 +       b       1f
8275 +       .align  5
8276 +1:     mcr     p15, 0, r0, c7, c10, 4
8277 +       mov     r2, #1
8278 +       str     r2, [r1, #AT91_SDRAMC_SRR]
8279 +
8280 +       /* Save Master clock setting */
8281 +
8282 +       ldr     r2, [r1, #AT91_PMC_MCKR]
8283 +       str     r2, .saved_mckr
8284 +
8285 +       /*
8286 +        * Set the Master clock source to slow clock
8287 +        *
8288 +        * First set the CSS field, wait for MCKRDY
8289 +        * and than set the PRES and MDIV fields.
8290 +        *
8291 +        * See eratta #2[78] for details.
8292 +        */
8293 +
8294 +       bic     r2, r2, #3
8295 +       str     r2, [r1, #AT91_PMC_MCKR]
8296 +
8297 +       wait_mckrdy
8298 +
8299 +       mov     r2, #0
8300 +       str     r2, [r1, #AT91_PMC_MCKR]
8301 +
8302 +       /* Save PLLA setting and disable it */
8303 +
8304 +       ldr     r2, [r1, #AT91_CKGR_PLLAR]
8305 +       str     r2, .saved_pllar
8306 +
8307 +       mov     r2, #0
8308 +       str     r2, [r1, #AT91_CKGR_PLLAR]
8309 +
8310 +       wait_plladis
8311 +
8312 +       /* Turn off the main oscillator */
8313 +
8314 +       ldr     r2, [r1, #AT91_CKGR_MOR]
8315 +       bic     r2, r2, #AT91_PMC_MOSCEN
8316 +       str     r2, [r1, #AT91_CKGR_MOR]
8317 +
8318 +       /* Wait for interrupt */
8319 +
8320 +       mcr     p15, 0, r0, c7, c0, 4
8321 +
8322 +       /* Turn on the main oscillator */
8323 +
8324 +       ldr     r2, [r1, #AT91_CKGR_MOR]
8325 +       orr     r2, r2, #AT91_PMC_MOSCEN
8326 +       str     r2, [r1, #AT91_CKGR_MOR]
8327 +
8328 +       wait_moscrdy
8329 +
8330 +       /* Restore PLLA setting */
8331 +
8332 +       ldr     r2, .saved_pllar
8333 +       str     r2, [r1, #AT91_CKGR_PLLAR]
8334 +
8335 +       wait_pllalock
8336 +
8337 +       /*
8338 +        * Restore master clock setting
8339 +        *
8340 +        * First set PRES if it was not 0,
8341 +        * than set CSS and MDIV fields.
8342 +        * After every change wait for
8343 +        * MCKRDY.
8344 +        *
8345 +        * See eratta #2[78] for details.
8346 +        */
8347 +
8348 +       ldr     r2, .saved_mckr
8349 +       tst     r2, #0x1C
8350 +       beq     2f
8351 +       and     r2, r2, #0x1C
8352 +       str     r2, [r1, #AT91_PMC_MCKR]
8353 +
8354 +       wait_mckrdy
8355 +
8356 +2:     ldr     r2, .saved_mckr
8357 +       str     r2, [r1, #AT91_PMC_MCKR]
8358 +
8359 +       wait_mckrdy
8360 +
8361 +       mov     pc, lr
8362 +
8363 +.saved_mckr:
8364 +       .word 0
8365 +
8366 +.saved_pllar:
8367 +       .word 0
8368 +
8369 +.at91_va_base_sys:
8370 +       .word AT91_VA_BASE_SYS
8371 +
8372 +ENTRY(at91rm9200_slow_clock_sz)
8373 +       .word .-at91rm9200_slow_clock
8374 diff -urN -x CVS linux-2.6.19-final/drivers/char/Kconfig linux-2.6.19/drivers/char/Kconfig
8375 --- linux-2.6.19-final/drivers/char/Kconfig     Mon Dec  4 16:39:54 2006
8376 +++ linux-2.6.19/drivers/char/Kconfig   Thu Nov 16 16:34:39 2006
8377 @@ -1048,5 +1048,21 @@
8378           sysfs directory, /sys/devices/platform/telco_clock, with a number of
8379           files for controlling the behavior of this hardware.
8380
8381 +config AT91_SPI
8382 +       bool "SPI driver (legacy) for AT91RM9200 processors"
8383 +       depends on ARCH_AT91RM9200
8384 +       default y
8385 +       help
8386 +         The SPI driver gives access to this serial bus on the AT91RM9200
8387 +         processor.
8388 +
8389 +config AT91_SPIDEV
8390 +       bool "SPI device interface (legacy) for AT91RM9200 processors"
8391 +       depends on ARCH_AT91RM9200 && AT91_SPI
8392 +       default n
8393 +       help
8394 +         The SPI driver gives user mode access to this serial
8395 +         bus on the AT91RM9200 processor.
8396 +
8397  endmenu
8398
8399 diff -urN -x CVS linux-2.6.19-final/drivers/char/Makefile linux-2.6.19/drivers/char/Makefile
8400 --- linux-2.6.19-final/drivers/char/Makefile    Mon Dec  4 16:39:54 2006
8401 +++ linux-2.6.19/drivers/char/Makefile  Thu Oct 12 17:07:38 2006
8402 @@ -90,6 +90,8 @@
8403  obj-$(CONFIG_GPIO_VR41XX)      += vr41xx_giu.o
8404  obj-$(CONFIG_TANBAC_TB0219)    += tb0219.o
8405  obj-$(CONFIG_TELCLOCK)         += tlclk.o
8406 +obj-$(CONFIG_AT91_SPI)         += at91_spi.o
8407 +obj-$(CONFIG_AT91_SPIDEV)      += at91_spidev.o
8408
8409  obj-$(CONFIG_WATCHDOG)         += watchdog/
8410  obj-$(CONFIG_MWAVE)            += mwave/
8411 diff -urN -x CVS linux-2.6.19-final/drivers/char/at91_spi.c linux-2.6.19/drivers/char/at91_spi.c
8412 --- linux-2.6.19-final/drivers/char/at91_spi.c  Thu Jan  1 02:00:00 1970
8413 +++ linux-2.6.19/drivers/char/at91_spi.c        Tue Oct 24 14:31:50 2006
8414 @@ -0,0 +1,336 @@
8415 +/*
8416 + * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200 (Thunder)
8417 + *
8418 + *  Copyright (C) SAN People (Pty) Ltd
8419 + *
8420 + * This program is free software; you can redistribute it and/or
8421 + * modify it under the terms of the GNU General Public License
8422 + * as published by the Free Software Foundation; either version
8423 + * 2 of the License, or (at your option) any later version.
8424 + */
8425 +
8426 +#include <linux/init.h>
8427 +#include <linux/dma-mapping.h>
8428 +#include <linux/module.h>
8429 +#include <linux/sched.h>
8430 +#include <linux/completion.h>
8431 +#include <linux/interrupt.h>
8432 +#include <linux/clk.h>
8433 +#include <linux/platform_device.h>
8434 +#include <asm/io.h>
8435 +#include <asm/semaphore.h>
8436 +
8437 +#include <asm/arch/at91_spi.h>
8438 +#include <asm/arch/at91_pdc.h>
8439 +#include <asm/arch/board.h>
8440 +#include <asm/arch/spi.h>
8441 +
8442 +#undef DEBUG_SPI
8443 +
8444 +static struct spi_local spi_dev[NR_SPI_DEVICES];       /* state of the SPI devices */
8445 +static int spi_enabled = 0;
8446 +static struct semaphore spi_lock;                      /* protect access to SPI bus */
8447 +static int current_device = -1;                                /* currently selected SPI device */
8448 +static struct clk *spi_clk;                            /* SPI clock */
8449 +static void __iomem *spi_base;                         /* SPI peripheral base-address */
8450 +
8451 +DECLARE_COMPLETION(transfer_complete);
8452 +
8453 +
8454 +#define at91_spi_read(reg)             __raw_readl(spi_base + (reg))
8455 +#define at91_spi_write(reg, val)       __raw_writel((val), spi_base + (reg))
8456 +
8457 +
8458 +/* ......................................................................... */
8459 +
8460 +/*
8461 + * Access and enable the SPI bus.
8462 + * This MUST be called before any transfers are performed.
8463 + */
8464 +void spi_access_bus(short device)
8465 +{
8466 +       /* Ensure that requested device is valid */
8467 +       if ((device < 0) || (device >= NR_SPI_DEVICES))
8468 +               panic("at91_spi: spi_access_bus called with invalid device");
8469 +
8470 +       if (spi_enabled == 0) {
8471 +               clk_enable(spi_clk);                            /* Enable Peripheral clock */
8472 +               at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIEN);    /* Enable SPI */
8473 +#ifdef DEBUG_SPI
8474 +               printk("SPI on\n");
8475 +#endif
8476 +       }
8477 +       spi_enabled++;
8478 +
8479 +       /* Lock the SPI bus */
8480 +       down(&spi_lock);
8481 +       current_device = device;
8482 +
8483 +       /* Configure SPI bus for device */
8484 +       at91_spi_write(AT91_SPI_MR, AT91_SPI_MSTR | AT91_SPI_MODFDIS | (spi_dev[device].pcs << 16));
8485 +}
8486 +
8487 +/*
8488 + * Relinquish control of the SPI bus.
8489 + */
8490 +void spi_release_bus(short device)
8491 +{
8492 +       if (device != current_device)
8493 +               panic("at91_spi: spi_release called with invalid device");
8494 +
8495 +       /* Release the SPI bus */
8496 +       current_device = -1;
8497 +       up(&spi_lock);
8498 +
8499 +       spi_enabled--;
8500 +       if (spi_enabled == 0) {
8501 +               at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIDIS);   /* Disable SPI */
8502 +               clk_disable(spi_clk);                           /* Disable Peripheral clock */
8503 +#ifdef DEBUG_SPI
8504 +               printk("SPI off\n");
8505 +#endif
8506 +       }
8507 +}
8508 +
8509 +/*
8510 + * Perform a data transfer over the SPI bus
8511 + */
8512 +int spi_transfer(struct spi_transfer_list* list)
8513 +{
8514 +       struct spi_local *device = (struct spi_local *) &spi_dev[current_device];
8515 +       int tx_size;
8516 +
8517 +       if (!list)
8518 +               panic("at91_spi: spi_transfer called with NULL transfer list");
8519 +       if (current_device == -1)
8520 +               panic("at91_spi: spi_transfer called without acquiring bus");
8521 +
8522 +#ifdef DEBUG_SPI
8523 +       printk("SPI transfer start [%i]\n", list->nr_transfers);
8524 +#endif
8525 +
8526 +       /* If we are in 16-bit mode, we need to modify what we pass to the PDC */
8527 +       tx_size = (at91_spi_read(AT91_SPI_CSR(current_device)) & AT91_SPI_BITS_16) ? 2 : 1;
8528 +
8529 +       /* Store transfer list */
8530 +       device->xfers = list;
8531 +       list->curr = 0;
8532 +
8533 +       /* Assume there must be at least one transfer */
8534 +       device->tx = dma_map_single(NULL, list->tx[0], list->txlen[0], DMA_TO_DEVICE);
8535 +       device->rx = dma_map_single(NULL, list->rx[0], list->rxlen[0], DMA_FROM_DEVICE);
8536 +
8537 +       /* Program PDC registers */
8538 +       at91_spi_write(AT91_PDC_TPR, device->tx);
8539 +       at91_spi_write(AT91_PDC_RPR, device->rx);
8540 +       at91_spi_write(AT91_PDC_TCR, list->txlen[0] / tx_size);
8541 +       at91_spi_write(AT91_PDC_RCR, list->rxlen[0] / tx_size);
8542 +
8543 +       /* Is there a second transfer? */
8544 +       if (list->nr_transfers > 1) {
8545 +               device->txnext = dma_map_single(NULL, list->tx[1], list->txlen[1], DMA_TO_DEVICE);
8546 +               device->rxnext = dma_map_single(NULL, list->rx[1], list->rxlen[1], DMA_FROM_DEVICE);
8547 +
8548 +               /* Program Next PDC registers */
8549 +               at91_spi_write(AT91_PDC_TNPR, device->txnext);
8550 +               at91_spi_write(AT91_PDC_RNPR, device->rxnext);
8551 +               at91_spi_write(AT91_PDC_TNCR, list->txlen[1] / tx_size);
8552 +               at91_spi_write(AT91_PDC_RNCR, list->rxlen[1] / tx_size);
8553 +       }
8554 +       else {
8555 +               device->txnext = 0;
8556 +               device->rxnext = 0;
8557 +               at91_spi_write(AT91_PDC_TNCR, 0);
8558 +               at91_spi_write(AT91_PDC_RNCR, 0);
8559 +       }
8560 +
8561 +       // TODO: If we are doing consecutive transfers (at high speed, or
8562 +       //   small buffers), then it might be worth modifying the 'Delay between
8563 +       //   Consecutive Transfers' in the CSR registers.
8564 +       //   This is an issue if we cannot chain the next buffer fast enough
8565 +       //   in the interrupt handler.
8566 +
8567 +       /* Enable transmitter and receiver */
8568 +       at91_spi_write(AT91_PDC_PTCR, AT91_PDC_RXTEN | AT91_PDC_TXTEN);
8569 +
8570 +       at91_spi_write(AT91_SPI_IER, AT91_SPI_ENDRX);           /* enable buffer complete interrupt */
8571 +       wait_for_completion(&transfer_complete);
8572 +
8573 +#ifdef DEBUG_SPI
8574 +       printk("SPI transfer end\n");
8575 +#endif
8576 +
8577 +       return 0;
8578 +}
8579 +
8580 +/* ......................................................................... */
8581 +
8582 +/*
8583 + * Handle interrupts from the SPI controller.
8584 + */
8585 +static irqreturn_t at91spi_interrupt(int irq, void *dev_id)
8586 +{
8587 +       unsigned int status;
8588 +       struct spi_local *device = (struct spi_local *) &spi_dev[current_device];
8589 +       struct spi_transfer_list *list = device->xfers;
8590 +
8591 +#ifdef DEBUG_SPI
8592 +       printk("SPI interrupt %i\n", current_device);
8593 +#endif
8594 +
8595 +       if (!list)
8596 +               panic("at91_spi: spi_interrupt with a NULL transfer list");
8597 +
8598 +               status = at91_spi_read(AT91_SPI_SR) & at91_spi_read(AT91_SPI_IMR);      /* read status */
8599 +
8600 +       dma_unmap_single(NULL, device->tx, list->txlen[list->curr], DMA_TO_DEVICE);
8601 +       dma_unmap_single(NULL, device->rx, list->rxlen[list->curr], DMA_FROM_DEVICE);
8602 +
8603 +       device->tx = device->txnext;    /* move next transfer to current transfer */
8604 +       device->rx = device->rxnext;
8605 +
8606 +       list->curr = list->curr + 1;
8607 +       if (list->curr == list->nr_transfers) {         /* all transfers complete */
8608 +               at91_spi_write(AT91_SPI_IDR, AT91_SPI_ENDRX);           /* disable interrupt */
8609 +
8610 +               /* Disable transmitter and receiver */
8611 +               at91_spi_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
8612 +
8613 +               device->xfers = NULL;
8614 +               complete(&transfer_complete);
8615 +       }
8616 +       else if (list->curr+1 == list->nr_transfers) {  /* no more next transfers */
8617 +               device->txnext = 0;
8618 +               device->rxnext = 0;
8619 +               at91_spi_write(AT91_PDC_TNCR, 0);
8620 +               at91_spi_write(AT91_PDC_RNCR, 0);
8621 +       }
8622 +       else {
8623 +               int i = (list->curr)+1;
8624 +
8625 +               /* If we are in 16-bit mode, we need to modify what we pass to the PDC */
8626 +               int tx_size = (at91_spi_read(AT91_SPI_CSR(current_device)) & AT91_SPI_BITS_16) ? 2 : 1;
8627 +
8628 +               device->txnext = dma_map_single(NULL, list->tx[i], list->txlen[i], DMA_TO_DEVICE);
8629 +               device->rxnext = dma_map_single(NULL, list->rx[i], list->rxlen[i], DMA_FROM_DEVICE);
8630 +               at91_spi_write(AT91_PDC_TNPR, device->txnext);
8631 +               at91_spi_write(AT91_PDC_RNPR, device->rxnext);
8632 +               at91_spi_write(AT91_PDC_TNCR, list->txlen[i] / tx_size);
8633 +               at91_spi_write(AT91_PDC_RNCR, list->rxlen[i] / tx_size);
8634 +       }
8635 +       return IRQ_HANDLED;
8636 +}
8637 +
8638 +/* ......................................................................... */
8639 +
8640 +/*
8641 + * Initialize the SPI controller
8642 + */
8643 +static int __init at91spi_probe(struct platform_device *pdev)
8644 +{
8645 +       int i;
8646 +       unsigned long scbr;
8647 +       struct resource *res;
8648 +
8649 +       init_MUTEX(&spi_lock);
8650 +
8651 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8652 +       if (!res)
8653 +               return -ENXIO;
8654 +
8655 +       if (!request_mem_region(res->start, res->end - res->start + 1, "at91_spi"))
8656 +               return -EBUSY;
8657 +
8658 +       spi_base = ioremap(res->start, res->end - res->start + 1);
8659 +       if (!spi_base) {
8660 +               release_mem_region(res->start, res->end - res->start + 1);
8661 +               return -ENOMEM;
8662 +       }
8663 +
8664 +       spi_clk = clk_get(NULL, "spi_clk");
8665 +       if (IS_ERR(spi_clk)) {
8666 +               printk(KERN_ERR "at91_spi: no clock defined\n");
8667 +               iounmap(spi_base);
8668 +               release_mem_region(res->start, res->end - res->start + 1);
8669 +               return -ENODEV;
8670 +       }
8671 +
8672 +       at91_spi_write(AT91_SPI_CR, AT91_SPI_SWRST);    /* software reset of SPI controller */
8673 +
8674 +       /*
8675 +        * Calculate the correct SPI baud-rate divisor.
8676 +        */
8677 +       scbr = clk_get_rate(spi_clk) / (2 * DEFAULT_SPI_CLK);
8678 +       scbr = scbr + 1;                /* round up */
8679 +
8680 +       printk(KERN_INFO "at91_spi: Baud rate set to %ld\n", clk_get_rate(spi_clk) / (2 * scbr));
8681 +
8682 +       /* Set Chip Select registers to good defaults */
8683 +       for (i = 0; i < 4; i++) {
8684 +               at91_spi_write(AT91_SPI_CSR(i), AT91_SPI_CPOL | AT91_SPI_BITS_8 | (16 << 16) | (scbr << 8));
8685 +       }
8686 +
8687 +       at91_spi_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
8688 +
8689 +       memset(&spi_dev, 0, sizeof(spi_dev));
8690 +       spi_dev[0].pcs = 0xE;
8691 +       spi_dev[1].pcs = 0xD;
8692 +       spi_dev[2].pcs = 0xB;
8693 +       spi_dev[3].pcs = 0x7;
8694 +
8695 +       if (request_irq(AT91RM9200_ID_SPI, at91spi_interrupt, 0, "spi", NULL)) {
8696 +               clk_put(spi_clk);
8697 +               iounmap(spi_base);
8698 +               release_mem_region(res->start, res->end - res->start + 1);
8699 +               return -EBUSY;
8700 +       }
8701 +
8702 +       at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIEN);            /* Enable SPI */
8703 +
8704 +       return 0;
8705 +}
8706 +
8707 +static int __devexit at91spi_remove(struct platform_device *pdev)
8708 +{
8709 +       struct resource *res;
8710 +
8711 +       at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIDIS);           /* Disable SPI */
8712 +       clk_put(spi_clk);
8713 +
8714 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8715 +       iounmap(spi_base);
8716 +       release_mem_region(res->start, res->end - res->start + 1);
8717 +
8718 +       free_irq(AT91RM9200_ID_SPI, 0);
8719 +       return 0;
8720 +}
8721 +
8722 +static struct platform_driver at91spi_driver = {
8723 +       .probe          = at91spi_probe,
8724 +       .remove         = __devexit_p(at91spi_remove),
8725 +       .driver         = {
8726 +               .name   = "at91_spi",
8727 +               .owner  = THIS_MODULE,
8728 +       },
8729 +};
8730 +
8731 +static int __init at91spi_init(void)
8732 +{
8733 +       return platform_driver_register(&at91spi_driver);
8734 +}
8735 +
8736 +static void __exit at91spi_exit(void)
8737 +{
8738 +       platform_driver_unregister(&at91spi_driver);
8739 +}
8740 +
8741 +EXPORT_SYMBOL(spi_access_bus);
8742 +EXPORT_SYMBOL(spi_release_bus);
8743 +EXPORT_SYMBOL(spi_transfer);
8744 +
8745 +module_init(at91spi_init);
8746 +module_exit(at91spi_exit);
8747 +
8748 +MODULE_LICENSE("GPL")
8749 +MODULE_AUTHOR("Andrew Victor")
8750 +MODULE_DESCRIPTION("SPI driver for Atmel AT91RM9200")
8751 diff -urN -x CVS linux-2.6.19-final/drivers/char/at91_spidev.c linux-2.6.19/drivers/char/at91_spidev.c
8752 --- linux-2.6.19-final/drivers/char/at91_spidev.c       Thu Jan  1 02:00:00 1970
8753 +++ linux-2.6.19/drivers/char/at91_spidev.c     Tue Oct 24 14:58:33 2006
8754 @@ -0,0 +1,236 @@
8755 +/*
8756 + * User-space interface to the SPI bus on Atmel AT91RM9200
8757 + *
8758 + *  Copyright (C) 2003 SAN People (Pty) Ltd
8759 + *
8760 + * Based on SPI driver by Rick Bronson
8761 + *
8762 + * This program is free software; you can redistribute it and/or
8763 + * modify it under the terms of the GNU General Public License
8764 + * as published by the Free Software Foundation; either version
8765 + * 2 of the License, or (at your option) any later version.
8766 + */
8767 +
8768 +#include <linux/module.h>
8769 +#include <linux/init.h>
8770 +#include <linux/slab.h>
8771 +#include <linux/highmem.h>
8772 +#include <linux/pagemap.h>
8773 +#include <asm/arch/spi.h>
8774 +
8775 +#ifdef CONFIG_DEVFS_FS
8776 +#include <linux/devfs_fs_kernel.h>
8777 +#endif
8778 +
8779 +
8780 +#undef DEBUG_SPIDEV
8781 +
8782 +/* ......................................................................... */
8783 +
8784 +/*
8785 + * Read or Write to SPI bus.
8786 + */
8787 +static ssize_t spidev_rd_wr(struct file *file, char *buf, size_t count, loff_t *offset)
8788 +{
8789 +       unsigned int spi_device = (unsigned int) file->private_data;
8790 +
8791 +       struct mm_struct * mm;
8792 +       struct page ** maplist;
8793 +       struct spi_transfer_list* list;
8794 +       int    pgcount;
8795 +
8796 +       unsigned int ofs, pagelen;
8797 +       int res, i, err;
8798 +
8799 +       if (!count) {
8800 +               return 0;
8801 +       }
8802 +
8803 +       list = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL);
8804 +       if (!list) {
8805 +               return -ENOMEM;
8806 +       }
8807 +
8808 +       mm = current->mm;
8809 +
8810 +       pgcount = ((unsigned long)buf+count+PAGE_SIZE-1)/PAGE_SIZE - (unsigned long)buf/PAGE_SIZE;
8811 +
8812 +       if (pgcount >= MAX_SPI_TRANSFERS) {
8813 +               kfree(list);
8814 +               return -EFBIG;
8815 +       }
8816 +
8817 +       maplist = kmalloc (pgcount * sizeof (struct page *), GFP_KERNEL);
8818 +
8819 +       if (!maplist) {
8820 +               kfree(list);
8821 +               return -ENOMEM;
8822 +       }
8823 +       flush_cache_all();
8824 +       down_read(&mm->mmap_sem);
8825 +       err= get_user_pages(current, mm, (unsigned long)buf, pgcount, 1, 0, maplist, NULL);
8826 +       up_read(&mm->mmap_sem);
8827 +
8828 +       if (err < 0) {
8829 +               kfree(list);
8830 +               kfree(maplist);
8831 +               return err;
8832 +       }
8833 +       pgcount = err;
8834 +
8835 +#ifdef DEBUG_SPIDEV
8836 +       printk("spidev_rd_rw: %i %i\n", count, pgcount);
8837 +#endif
8838 +
8839 +       /* Set default return value = transfer length */
8840 +       res = count;
8841 +
8842 +       /*
8843 +        * At this point, the virtual area buf[0] .. buf[count-1] will have
8844 +        * corresponding pages mapped in the physical memory and locked until
8845 +        * we unmap the kiobuf.  The pages cannot be swapped out or moved
8846 +        * around.
8847 +        */
8848 +       ofs = (unsigned long) buf & (PAGE_SIZE -1);
8849 +       pagelen = PAGE_SIZE - ofs;
8850 +       if (count < pagelen)
8851 +               pagelen = count;
8852 +
8853 +       for (i = 0; i < pgcount; i++) {
8854 +               flush_dcache_page(maplist[i]);
8855 +
8856 +               list->tx[i] = list->rx[i] = page_address(maplist[i]) + ofs;
8857 +               list->txlen[i] = list->rxlen[i] = pagelen;
8858 +
8859 +#ifdef DEBUG_SPIDEV
8860 +               printk("  %i: %x  (%i)\n", i, list->tx[i], list->txlen[i]);
8861 +#endif
8862 +
8863 +               ofs = 0;        /* all subsequent transfers start at beginning of a page */
8864 +               count = count - pagelen;
8865 +               pagelen = (count < PAGE_SIZE) ? count : PAGE_SIZE;
8866 +       }
8867 +       list->nr_transfers = pgcount;
8868 +
8869 +       /* Perform transfer on SPI bus */
8870 +       spi_access_bus(spi_device);
8871 +       spi_transfer(list);
8872 +       spi_release_bus(spi_device);
8873 +
8874 +       while (pgcount--) {
8875 +               page_cache_release (maplist[pgcount]);
8876 +       }
8877 +       flush_cache_all();
8878 +
8879 +       kfree(maplist);
8880 +       kfree(list);
8881 +
8882 +       return res;
8883 +}
8884 +
8885 +static int spidev_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
8886 +{
8887 +       int spi_device = MINOR(inode->i_rdev);
8888 +
8889 +       if (spi_device >= NR_SPI_DEVICES)
8890 +               return -ENODEV;
8891 +
8892 +       // TODO: This interface can be used to configure the SPI bus.
8893 +       // Configurable options could include: Speed, Clock Polarity, Clock Phase
8894 +
8895 +       switch(cmd) {
8896 +               default:
8897 +                       return -ENOIOCTLCMD;
8898 +       }
8899 +}
8900 +
8901 +/*
8902 + * Open the SPI device
8903 + */
8904 +static int spidev_open(struct inode *inode, struct file *file)
8905 +{
8906 +       unsigned int spi_device = MINOR(inode->i_rdev);
8907 +
8908 +       if (spi_device >= NR_SPI_DEVICES)
8909 +               return -ENODEV;
8910 +
8911 +       /*
8912 +        * 'private_data' is actually a pointer, but we overload it with the
8913 +        * value we want to store.
8914 +        */
8915 +       file->private_data = (void *)spi_device;
8916 +
8917 +       return 0;
8918 +}
8919 +
8920 +/*
8921 + * Close the SPI device
8922 + */
8923 +static int spidev_close(struct inode *inode, struct file *file)
8924 +{
8925 +       return 0;
8926 +}
8927 +
8928 +/* ......................................................................... */
8929 +
8930 +static struct file_operations spidev_fops = {
8931 +       .owner          = THIS_MODULE,
8932 +       .llseek         = no_llseek,
8933 +       .read           = spidev_rd_wr,
8934 +       .write          = (int (*) (struct file *file, const char *buf, size_t count, loff_t *offset))spidev_rd_wr,
8935 +       .ioctl          = spidev_ioctl,
8936 +       .open           = spidev_open,
8937 +       .release        = spidev_close,
8938 +};
8939 +
8940 +/*
8941 + * Install the SPI /dev interface driver
8942 + */
8943 +static int __init at91_spidev_init(void)
8944 +{
8945 +#ifdef CONFIG_DEVFS_FS
8946 +       int i;
8947 +#endif
8948 +
8949 +       if (register_chrdev(SPI_MAJOR, "spi", &spidev_fops)) {
8950 +               printk(KERN_ERR "at91_spidev: Unable to get major %d for SPI bus\n", SPI_MAJOR);
8951 +               return -EIO;
8952 +       }
8953 +
8954 +#ifdef CONFIG_DEVFS_FS
8955 +       devfs_mk_dir("spi");
8956 +       for (i = 0; i < NR_SPI_DEVICES; i++) {
8957 +               devfs_mk_cdev(MKDEV(SPI_MAJOR, i), S_IFCHR | S_IRUSR | S_IWUSR, "spi/%d",i);
8958 +       }
8959 +#endif
8960 +       printk(KERN_INFO "AT91 SPI driver loaded\n");
8961 +
8962 +       return 0;
8963 +}
8964 +
8965 +/*
8966 + * Remove the SPI /dev interface driver
8967 + */
8968 +static void __exit at91_spidev_exit(void)
8969 +{
8970 +#ifdef CONFIG_DEVFS_FS
8971 +       int i;
8972 +       for (i = 0; i < NR_SPI_DEVICES; i++) {
8973 +               devfs_remove("spi/%d", i);
8974 +       }
8975 +
8976 +       devfs_remove("spi");
8977 +#endif
8978 +
8979 +       if (unregister_chrdev(SPI_MAJOR, "spi")) {
8980 +               printk(KERN_ERR "at91_spidev: Unable to release major %d for SPI bus\n", SPI_MAJOR);
8981 +               return;
8982 +       }
8983 +}
8984 +
8985 +module_init(at91_spidev_init);
8986 +module_exit(at91_spidev_exit);
8987 +
8988 +MODULE_LICENSE("GPL")
8989 +MODULE_AUTHOR("Andrew Victor")
8990 +MODULE_DESCRIPTION("SPI /dev interface for Atmel AT91RM9200")
8991 diff -urN -x CVS linux-2.6.19-final/drivers/char/watchdog/at91rm9200_wdt.c linux-2.6.19/drivers/char/watchdog/at91rm9200_wdt.c
8992 --- linux-2.6.19-final/drivers/char/watchdog/at91rm9200_wdt.c   Mon Dec  4 16:39:59 2006
8993 +++ linux-2.6.19/drivers/char/watchdog/at91rm9200_wdt.c Wed Nov  8 12:40:58 2006
8994 @@ -21,6 +21,7 @@
8995  #include <linux/watchdog.h>
8996  #include <asm/bitops.h>
8997  #include <asm/uaccess.h>
8998 +#include <asm/arch/at91_st.h>
8999
9000
9001  #define WDT_DEFAULT_TIME       5       /* seconds */
9002 diff -urN -x CVS linux-2.6.19-final/drivers/i2c/busses/Kconfig linux-2.6.19/drivers/i2c/busses/Kconfig
9003 --- linux-2.6.19-final/drivers/i2c/busses/Kconfig       Mon Dec  4 16:40:01 2006
9004 +++ linux-2.6.19/drivers/i2c/busses/Kconfig     Thu Oct 12 17:07:38 2006
9005 @@ -74,6 +74,13 @@
9006           This driver can also be built as a module.  If so, the module
9007           will be called i2c-amd8111.
9008
9009 +config I2C_AT91
9010 +       tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
9011 +       depends on I2C && ARCH_AT91 && EXPERIMENTAL
9012 +       help
9013 +         This supports the use of the I2C interface on Atmel AT91
9014 +         processors.
9015 +
9016  config I2C_AU1550
9017         tristate "Au1550/Au1200 SMBus interface"
9018         depends on I2C && (SOC_AU1550 || SOC_AU1200)
9019 @@ -520,6 +527,14 @@
9020           This driver can also be built as a module.  If so, the module
9021           will be called i2c-voodoo3.
9022
9023 +config I2C_PCA
9024 +       tristate "PCA9564"
9025 +       depends on I2C
9026 +       select I2C_ALGOPCA
9027 +       help
9028 +         This driver support the Philips PCA 9564 Parallel bus to I2C
9029 +         bus controller.
9030 +
9031  config I2C_PCA_ISA
9032         tristate "PCA9564 on an ISA bus"
9033         depends on I2C
9034 diff -urN -x CVS linux-2.6.19-final/drivers/i2c/busses/Makefile linux-2.6.19/drivers/i2c/busses/Makefile
9035 --- linux-2.6.19-final/drivers/i2c/busses/Makefile      Mon Dec  4 16:40:01 2006
9036 +++ linux-2.6.19/drivers/i2c/busses/Makefile    Thu Oct 12 17:07:38 2006
9037 @@ -8,6 +8,7 @@
9038  obj-$(CONFIG_I2C_AMD756)       += i2c-amd756.o
9039  obj-$(CONFIG_I2C_AMD756_S4882) += i2c-amd756-s4882.o
9040  obj-$(CONFIG_I2C_AMD8111)      += i2c-amd8111.o
9041 +obj-$(CONFIG_I2C_AT91)         += i2c-at91.o
9042  obj-$(CONFIG_I2C_AU1550)       += i2c-au1550.o
9043  obj-$(CONFIG_I2C_ELEKTOR)      += i2c-elektor.o
9044  obj-$(CONFIG_I2C_HYDRA)                += i2c-hydra.o
9045 @@ -27,6 +28,7 @@
9046  obj-$(CONFIG_I2C_OMAP)         += i2c-omap.o
9047  obj-$(CONFIG_I2C_PARPORT)      += i2c-parport.o
9048  obj-$(CONFIG_I2C_PARPORT_LIGHT)        += i2c-parport-light.o
9049 +obj-$(CONFIG_I2C_PCA)          += i2c-pca.o
9050  obj-$(CONFIG_I2C_PCA_ISA)      += i2c-pca-isa.o
9051  obj-$(CONFIG_I2C_PIIX4)                += i2c-piix4.o
9052  obj-$(CONFIG_I2C_PROSAVAGE)    += i2c-prosavage.o
9053 diff -urN -x CVS linux-2.6.19-final/drivers/i2c/busses/i2c-at91.c linux-2.6.19/drivers/i2c/busses/i2c-at91.c
9054 --- linux-2.6.19-final/drivers/i2c/busses/i2c-at91.c    Thu Jan  1 02:00:00 1970
9055 +++ linux-2.6.19/drivers/i2c/busses/i2c-at91.c  Fri Nov 10 09:18:41 2006
9056 @@ -0,0 +1,325 @@
9057 +/*
9058 +    i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
9059 +
9060 +    Copyright (C) 2004 Rick Bronson
9061 +    Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
9062 +
9063 +    Borrowed heavily from original work by:
9064 +    Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
9065 +
9066 +    This program is free software; you can redistribute it and/or modify
9067 +    it under the terms of the GNU General Public License as published by
9068 +    the Free Software Foundation; either version 2 of the License, or
9069 +    (at your option) any later version.
9070 +*/
9071 +
9072 +#include <linux/module.h>
9073 +#include <linux/version.h>
9074 +#include <linux/kernel.h>
9075 +#include <linux/slab.h>
9076 +#include <linux/pci.h>
9077 +#include <linux/types.h>
9078 +#include <linux/delay.h>
9079 +#include <linux/i2c.h>
9080 +#include <linux/init.h>
9081 +#include <linux/clk.h>
9082 +#include <linux/platform_device.h>
9083 +
9084 +#include <asm/io.h>
9085 +
9086 +#include <asm/arch/at91_twi.h>
9087 +#include <asm/arch/board.h>
9088 +#include <asm/arch/cpu.h>
9089 +
9090 +#define TWI_CLOCK              100000          /* Hz. max 400 Kbits/sec */
9091 +
9092 +
9093 +static struct clk *twi_clk;
9094 +static void __iomem *twi_base;
9095 +
9096 +#define at91_twi_read(reg)             __raw_readl(twi_base + (reg))
9097 +#define at91_twi_write(reg, val)       __raw_writel((val), twi_base + (reg))
9098 +
9099 +
9100 +/*
9101 + * Initialize the TWI hardware registers.
9102 + */
9103 +static void __devinit at91_twi_hwinit(void)
9104 +{
9105 +       unsigned long cdiv, ckdiv;
9106 +
9107 +       at91_twi_write(AT91_TWI_IDR, 0xffffffff);       /* Disable all interrupts */
9108 +       at91_twi_write(AT91_TWI_CR, AT91_TWI_SWRST);    /* Reset peripheral */
9109 +       at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN);     /* Set Master mode */
9110 +
9111 +       /* Calcuate clock dividers */
9112 +       cdiv = (clk_get_rate(twi_clk) / (2 * TWI_CLOCK)) - 3;
9113 +       cdiv = cdiv + 1;        /* round up */
9114 +       ckdiv = 0;
9115 +       while (cdiv > 255) {
9116 +               ckdiv++;
9117 +               cdiv = cdiv >> 1;
9118 +       }
9119 +
9120 +       if (cpu_is_at91rm9200()) {                      /* AT91RM9200 Errata #22 */
9121 +               if (ckdiv > 5) {
9122 +                       printk(KERN_ERR "AT91 I2C: Invalid TWI_CLOCK value!\n");
9123 +                       ckdiv = 5;
9124 +               }
9125 +       }
9126 +
9127 +       at91_twi_write(AT91_TWI_CWGR, (ckdiv << 16) | (cdiv << 8) | cdiv);
9128 +}
9129 +
9130 +/*
9131 + * Poll the i2c status register until the specified bit is set.
9132 + * Returns 0 if timed out (100 msec).
9133 + */
9134 +static short at91_poll_status(unsigned long bit)
9135 +{
9136 +       int loop_cntr = 10000;
9137 +
9138 +       do {
9139 +               udelay(10);
9140 +       } while (!(at91_twi_read(AT91_TWI_SR) & bit) && (--loop_cntr > 0));
9141 +
9142 +       return (loop_cntr > 0);
9143 +}
9144 +
9145 +static int xfer_read(struct i2c_adapter *adap, unsigned char *buf, int length)
9146 +{
9147 +       /* Send Start */
9148 +       at91_twi_write(AT91_TWI_CR, AT91_TWI_START);
9149 +
9150 +       /* Read data */
9151 +       while (length--) {
9152 +               if (!length)    /* need to send Stop before reading last byte */
9153 +                       at91_twi_write(AT91_TWI_CR, AT91_TWI_STOP);
9154 +               if (!at91_poll_status(AT91_TWI_RXRDY)) {
9155 +                       dev_dbg(&adap->dev, "RXRDY timeout\n");
9156 +                       return -ETIMEDOUT;
9157 +               }
9158 +               *buf++ = (at91_twi_read(AT91_TWI_RHR) & 0xff);
9159 +       }
9160 +
9161 +       return 0;
9162 +}
9163 +
9164 +static int xfer_write(struct i2c_adapter *adap, unsigned char *buf, int length)
9165 +{
9166 +       /* Load first byte into transmitter */
9167 +       at91_twi_write(AT91_TWI_THR, *buf++);
9168 +
9169 +       /* Send Start */
9170 +       at91_twi_write(AT91_TWI_CR, AT91_TWI_START);
9171 +
9172 +       do {
9173 +               if (!at91_poll_status(AT91_TWI_TXRDY)) {
9174 +                       dev_dbg(&adap->dev, "TXRDY timeout\n");
9175 +                       return -ETIMEDOUT;
9176 +               }
9177 +
9178 +               length--;       /* byte was transmitted */
9179 +
9180 +               if (length > 0)         /* more data to send? */
9181 +                       at91_twi_write(AT91_TWI_THR, *buf++);
9182 +       } while (length);
9183 +
9184 +       /* Send Stop */
9185 +       at91_twi_write(AT91_TWI_CR, AT91_TWI_STOP);
9186 +
9187 +       return 0;
9188 +}
9189 +
9190 +/*
9191 + * Generic i2c master transfer entrypoint.
9192 + *
9193 + * Note: We do not use Atmel's feature of storing the "internal device address".
9194 + * Instead the "internal device address" has to be written using a seperate
9195 + * i2c message.
9196 + * http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2004-September/024411.html
9197 + */
9198 +static int at91_xfer(struct i2c_adapter *adap, struct i2c_msg *pmsg, int num)
9199 +{
9200 +       int i, ret;
9201 +
9202 +       dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
9203 +
9204 +       for (i = 0; i < num; i++) {
9205 +               dev_dbg(&adap->dev, " #%d: %sing %d byte%s %s 0x%02x\n", i,
9206 +                       pmsg->flags & I2C_M_RD ? "read" : "writ",
9207 +                       pmsg->len, pmsg->len > 1 ? "s" : "",
9208 +                       pmsg->flags & I2C_M_RD ? "from" : "to", pmsg->addr);
9209 +
9210 +               at91_twi_write(AT91_TWI_MMR, (pmsg->addr << 16)
9211 +                       | ((pmsg->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0));
9212 +
9213 +               if (pmsg->len && pmsg->buf) {   /* sanity check */
9214 +                       if (pmsg->flags & I2C_M_RD)
9215 +                               ret = xfer_read(adap, pmsg->buf, pmsg->len);
9216 +                       else
9217 +                               ret = xfer_write(adap, pmsg->buf, pmsg->len);
9218 +
9219 +                       if (ret)
9220 +                               return ret;
9221 +
9222 +                       /* Wait until transfer is finished */
9223 +                       if (!at91_poll_status(AT91_TWI_TXCOMP)) {
9224 +                               dev_dbg(&adap->dev, "TXCOMP timeout\n");
9225 +                               return -ETIMEDOUT;
9226 +                       }
9227 +               }
9228 +               dev_dbg(&adap->dev, "transfer complete\n");
9229 +               pmsg++;         /* next message */
9230 +       }
9231 +       return i;
9232 +}
9233 +
9234 +/*
9235 + * Return list of supported functionality.
9236 + */
9237 +static u32 at91_func(struct i2c_adapter *adapter)
9238 +{
9239 +       return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
9240 +}
9241 +
9242 +static struct i2c_algorithm at91_algorithm = {
9243 +       .master_xfer    = at91_xfer,
9244 +       .functionality  = at91_func,
9245 +};
9246 +
9247 +/*
9248 + * Main initialization routine.
9249 + */
9250 +static int __devinit at91_i2c_probe(struct platform_device *pdev)
9251 +{
9252 +       struct i2c_adapter *adapter;
9253 +       struct resource *res;
9254 +       int rc;
9255 +
9256 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9257 +       if (!res)
9258 +               return -ENXIO;
9259 +
9260 +       if (!request_mem_region(res->start, res->end - res->start + 1, "at91_i2c"))
9261 +               return -EBUSY;
9262 +
9263 +       twi_base = ioremap(res->start, res->end - res->start + 1);
9264 +       if (!twi_base) {
9265 +               rc = -ENOMEM;
9266 +               goto fail0;
9267 +       }
9268 +
9269 +       twi_clk = clk_get(NULL, "twi_clk");
9270 +       if (IS_ERR(twi_clk)) {
9271 +               dev_err(&pdev->dev, "no clock defined\n");
9272 +               rc = -ENODEV;
9273 +               goto fail1;
9274 +       }
9275 +
9276 +       adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
9277 +       if (adapter == NULL) {
9278 +               dev_err(&pdev->dev, "can't allocate inteface!\n");
9279 +               rc = -ENOMEM;
9280 +               goto fail2;
9281 +       }
9282 +       sprintf(adapter->name, "AT91");
9283 +       adapter->algo = &at91_algorithm;
9284 +       adapter->class = I2C_CLASS_HWMON;
9285 +       adapter->dev.parent = &pdev->dev;
9286 +
9287 +       platform_set_drvdata(pdev, adapter);
9288 +
9289 +       clk_enable(twi_clk);            /* enable peripheral clock */
9290 +       at91_twi_hwinit();              /* initialize TWI controller */
9291 +
9292 +       rc = i2c_add_adapter(adapter);
9293 +       if (rc) {
9294 +               dev_err(&pdev->dev, "Adapter %s registration failed\n",
9295 +                               adapter->name);
9296 +               goto fail3;
9297 +       }
9298 +
9299 +       dev_info(&pdev->dev, "AT91 i2c bus driver.\n");
9300 +       return 0;
9301 +
9302 +fail3:
9303 +       platform_set_drvdata(pdev, NULL);
9304 +       kfree(adapter);
9305 +       clk_disable(twi_clk);
9306 +fail2:
9307 +       clk_put(twi_clk);
9308 +fail1:
9309 +       iounmap(twi_base);
9310 +fail0:
9311 +       release_mem_region(res->start, res->end - res->start + 1);
9312 +
9313 +       return rc;
9314 +}
9315 +
9316 +static int __devexit at91_i2c_remove(struct platform_device *pdev)
9317 +{
9318 +       struct i2c_adapter *adapter = platform_get_drvdata(pdev);
9319 +       struct resource *res;
9320 +       int rc;
9321 +
9322 +       rc = i2c_del_adapter(adapter);
9323 +       platform_set_drvdata(pdev, NULL);
9324 +
9325 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9326 +       iounmap(twi_base);
9327 +       release_mem_region(res->start, res->end - res->start + 1);
9328 +
9329 +       clk_disable(twi_clk);           /* disable peripheral clock */
9330 +       clk_put(twi_clk);
9331 +
9332 +       return rc;
9333 +}
9334 +
9335 +#ifdef CONFIG_PM
9336 +
9337 +/* NOTE: could save a few mA by keeping clock off outside of at91_xfer... */
9338 +
9339 +static int at91_i2c_suspend(struct platform_device *pdev, pm_message_t mesg)
9340 +{
9341 +       clk_disable(twi_clk);
9342 +       return 0;
9343 +}
9344 +
9345 +static int at91_i2c_resume(struct platform_device *pdev)
9346 +{
9347 +       return clk_enable(twi_clk);
9348 +}
9349 +
9350 +#else
9351 +#define at91_i2c_suspend       NULL
9352 +#define at91_i2c_resume                NULL
9353 +#endif
9354 +
9355 +static struct platform_driver at91_i2c_driver = {
9356 +       .probe          = at91_i2c_probe,
9357 +       .remove         = __devexit_p(at91_i2c_remove),
9358 +       .suspend        = at91_i2c_suspend,
9359 +       .resume         = at91_i2c_resume,
9360 +       .driver         = {
9361 +               .name   = "at91_i2c",
9362 +               .owner  = THIS_MODULE,
9363 +       },
9364 +};
9365 +
9366 +static int __init at91_i2c_init(void)
9367 +{
9368 +       return platform_driver_register(&at91_i2c_driver);
9369 +}
9370 +
9371 +static void __exit at91_i2c_exit(void)
9372 +{
9373 +       platform_driver_unregister(&at91_i2c_driver);
9374 +}
9375 +
9376 +module_init(at91_i2c_init);
9377 +module_exit(at91_i2c_exit);
9378 +
9379 +MODULE_AUTHOR("Rick Bronson");
9380 +MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
9381 +MODULE_LICENSE("GPL");
9382 diff -urN -x CVS linux-2.6.19-final/drivers/i2c/busses/i2c-pca.c linux-2.6.19/drivers/i2c/busses/i2c-pca.c
9383 --- linux-2.6.19-final/drivers/i2c/busses/i2c-pca.c     Thu Jan  1 02:00:00 1970
9384 +++ linux-2.6.19/drivers/i2c/busses/i2c-pca.c   Mon Oct 16 16:10:42 2006
9385 @@ -0,0 +1,202 @@
9386 +/*
9387 + *  Platform driver for PCA9564 I2C bus controller.
9388 + *
9389 + *  (C) 2006 Andrew Victor
9390 + *
9391 + *  Based on i2c-pca-isa.c driver for PCA9564 on ISA boards
9392 + *    Copyright (C) 2004 Arcom Control Systems
9393 + *
9394 + *  This program is free software; you can redistribute it and/or modify
9395 + *  it under the terms of the GNU General Public License as published by
9396 + *  the Free Software Foundation; either version 2 of the License, or
9397 + *  (at your option) any later version.
9398 + *
9399 + *  This program is distributed in the hope that it will be useful,
9400 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
9401 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
9402 + *  GNU General Public License for more details.
9403 + *
9404 + *  You should have received a copy of the GNU General Public License
9405 + *  along with this program; if not, write to the Free Software
9406 + *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
9407 + */
9408 +
9409 +#include <linux/kernel.h>
9410 +#include <linux/module.h>
9411 +#include <linux/moduleparam.h>
9412 +#include <linux/delay.h>
9413 +#include <linux/init.h>
9414 +#include <linux/interrupt.h>
9415 +#include <linux/wait.h>
9416 +#include <linux/platform_device.h>
9417 +
9418 +#include <linux/i2c.h>
9419 +#include <linux/i2c-algo-pca.h>
9420 +
9421 +#include <asm/io.h>
9422 +
9423 +#include "../algos/i2c-algo-pca.h"
9424 +
9425 +#define PCA_OWN_ADDRESS                0x55    /* our address for slave mode */
9426 +#define PCA_CLOCK              I2C_PCA_CON_59kHz
9427 +
9428 +//#define DEBUG_IO
9429 +
9430 +#define PCA_IO_SIZE 4
9431 +
9432 +static void __iomem *base_addr;
9433 +static int irq;
9434 +static wait_queue_head_t pca_wait;
9435 +
9436 +static int pca_getown(struct i2c_algo_pca_data *adap)
9437 +{
9438 +       return PCA_OWN_ADDRESS;
9439 +}
9440 +
9441 +static int pca_getclock(struct i2c_algo_pca_data *adap)
9442 +{
9443 +       return PCA_CLOCK;
9444 +}
9445 +
9446 +static void pca_writebyte(struct i2c_algo_pca_data *adap, int reg, int val)
9447 +{
9448 +#ifdef DEBUG_IO
9449 +       static char *names[] = { "T/O", "DAT", "ADR", "CON" };
9450 +       printk("*** write %s at %#lx <= %#04x\n", names[reg], (unsigned long) base_addr+reg, val);
9451 +#endif
9452 +       outb(val, base_addr+reg);
9453 +}
9454 +
9455 +static int pca_readbyte(struct i2c_algo_pca_data *adap, int reg)
9456 +{
9457 +       int res = inb(base_addr+reg);
9458 +#ifdef DEBUG_IO
9459 +       {
9460 +               static char *names[] = { "STA", "DAT", "ADR", "CON" };
9461 +               printk("*** read  %s => %#04x\n", names[reg], res);
9462 +       }
9463 +#endif
9464 +       return res;
9465 +}
9466 +
9467 +static int pca_waitforinterrupt(struct i2c_algo_pca_data *adap)
9468 +{
9469 +       int ret = 0;
9470 +
9471 +       if (irq > -1) {
9472 +               ret = wait_event_interruptible(pca_wait,
9473 +                               pca_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI);
9474 +       } else {
9475 +               while ((pca_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI) == 0)
9476 +                       udelay(100);
9477 +       }
9478 +       return ret;
9479 +}
9480 +
9481 +static irqreturn_t pca_handler(int this_irq, void *dev_id)
9482 +{
9483 +       wake_up_interruptible(&pca_wait);
9484 +       return IRQ_HANDLED;
9485 +}
9486 +
9487 +static struct i2c_algo_pca_data pca_i2c_data = {
9488 +       .get_own                = pca_getown,
9489 +       .get_clock              = pca_getclock,
9490 +       .write_byte             = pca_writebyte,
9491 +       .read_byte              = pca_readbyte,
9492 +       .wait_for_interrupt     = pca_waitforinterrupt,
9493 +};
9494 +
9495 +static struct i2c_adapter pca_i2c_ops = {
9496 +       .owner          = THIS_MODULE,
9497 +       .id             = I2C_HW_A_PLAT,
9498 +       .algo_data      = &pca_i2c_data,
9499 +       .name           = "PCA9564",
9500 +};
9501 +
9502 +static int __devinit pca_i2c_probe(struct platform_device *pdev)
9503 +{
9504 +       struct resource *res;
9505 +
9506 +       init_waitqueue_head(&pca_wait);
9507 +
9508 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9509 +       if (!res)
9510 +               return -ENODEV;
9511 +
9512 +       if (!request_mem_region(res->start, PCA_IO_SIZE, "PCA9564"))
9513 +               return -ENXIO;
9514 +
9515 +       base_addr = ioremap(res->start, PCA_IO_SIZE);
9516 +       if (base_addr == NULL)
9517 +               goto out_region;
9518 +
9519 +       irq = platform_get_irq(pdev, 0);
9520 +       if (irq > -1) {
9521 +               if (request_irq(irq, pca_handler, 0, "pca9564", NULL) < 0) {
9522 +                       printk(KERN_ERR "i2c-pca: Request irq%d failed\n", irq);
9523 +                       goto out_remap;
9524 +               }
9525 +       }
9526 +
9527 +       if (i2c_pca_add_bus(&pca_i2c_ops) < 0) {
9528 +               printk(KERN_ERR "i2c-pca: Failed to add i2c bus\n");
9529 +               goto out_irq;
9530 +       }
9531 +
9532 +       return 0;
9533 +
9534 + out_irq:
9535 +       if (irq > -1)
9536 +               free_irq(irq, &pca_i2c_ops);
9537 +
9538 + out_remap:
9539 +       iounmap(base_addr);
9540 +
9541 + out_region:
9542 +       release_mem_region(res->start, PCA_IO_SIZE);
9543 +       return -ENODEV;
9544 +}
9545 +
9546 +static int __devexit pca_i2c_remove(struct platform_device *pdev)
9547 +{
9548 +       struct resource *res;
9549 +
9550 +       i2c_pca_del_bus(&pca_i2c_ops);
9551 +
9552 +       if (irq > 0)
9553 +               free_irq(irq, NULL);
9554 +
9555 +       iounmap(base_addr);
9556 +
9557 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9558 +       release_mem_region(res->start, PCA_IO_SIZE);
9559 +
9560 +       return 0;
9561 +}
9562 +
9563 +static struct platform_driver pca_i2c_driver = {
9564 +       .probe          = pca_i2c_probe,
9565 +       .remove         = __devexit_p(pca_i2c_remove),
9566 +       .driver         = {
9567 +               .name   = "pca9564",
9568 +               .owner  = THIS_MODULE,
9569 +       },
9570 +};
9571 +
9572 +static int __init pca_i2c_init(void)
9573 +{
9574 +       return platform_driver_register(&pca_i2c_driver);
9575 +}
9576 +
9577 +static void __exit pca_i2c_exit(void)
9578 +{
9579 +       platform_driver_unregister(&pca_i2c_driver);
9580 +}
9581 +
9582 +module_init(pca_i2c_init);
9583 +module_exit(pca_i2c_exit);
9584 +
9585 +MODULE_AUTHOR("Andrew Victor");
9586 +MODULE_DESCRIPTION("PCA9564 platform driver");
9587 +MODULE_LICENSE("GPL");
9588 diff -urN -x CVS linux-2.6.19-final/drivers/leds/Kconfig linux-2.6.19/drivers/leds/Kconfig
9589 --- linux-2.6.19-final/drivers/leds/Kconfig     Mon Dec  4 16:33:34 2006
9590 +++ linux-2.6.19/drivers/leds/Kconfig   Thu Nov 16 17:15:16 2006
9591 @@ -76,6 +76,13 @@
9592           This option enables support for the Soekris net4801 and net4826 error
9593           LED.
9594
9595 +config LEDS_AT91
9596 +       tristate "LED support using AT91 GPIOs"
9597 +       depends LEDS_CLASS && ARCH_AT91 && !LEDS
9598 +       help
9599 +         This option enables support for LEDs connected to GPIO lines
9600 +         on AT91-based boards.
9601 +
9602  comment "LED Triggers"
9603
9604  config LEDS_TRIGGERS
9605 diff -urN -x CVS linux-2.6.19-final/drivers/leds/Makefile linux-2.6.19/drivers/leds/Makefile
9606 --- linux-2.6.19-final/drivers/leds/Makefile    Mon Dec  4 16:33:34 2006
9607 +++ linux-2.6.19/drivers/leds/Makefile  Thu Nov 16 12:52:06 2006
9608 @@ -13,6 +13,7 @@
9609  obj-$(CONFIG_LEDS_S3C24XX)             += leds-s3c24xx.o
9610  obj-$(CONFIG_LEDS_AMS_DELTA)           += leds-ams-delta.o
9611  obj-$(CONFIG_LEDS_NET48XX)             += leds-net48xx.o
9612 +obj-$(CONFIG_LEDS_AT91)                        += leds-at91.o
9613
9614  # LED Triggers
9615  obj-$(CONFIG_LEDS_TRIGGER_TIMER)       += ledtrig-timer.o
9616 diff -urN -x CVS linux-2.6.19-final/drivers/leds/leds-at91.c linux-2.6.19/drivers/leds/leds-at91.c
9617 --- linux-2.6.19-final/drivers/leds/leds-at91.c Thu Jan  1 02:00:00 1970
9618 +++ linux-2.6.19/drivers/leds/leds-at91.c       Mon Nov 20 11:02:21 2006
9619 @@ -0,0 +1,140 @@
9620 +/*
9621 + * AT91 GPIO based LED driver
9622 + *
9623 + * Copyright (C) 2006 David Brownell
9624 + *
9625 + * This program is free software; you can redistribute it and/or modify
9626 + * it under the terms of the GNU General Public License version 2 as
9627 + * published by the Free Software Foundation.
9628 + */
9629 +
9630 +#include <linux/kernel.h>
9631 +#include <linux/init.h>
9632 +#include <linux/platform_device.h>
9633 +#include <linux/leds.h>
9634 +
9635 +#include <asm/arch/board.h>
9636 +#include <asm/arch/gpio.h>
9637 +
9638 +static LIST_HEAD(at91_led_list);       /* list of AT91 LEDs */
9639 +
9640 +struct at91_led {
9641 +       struct led_classdev     cdev;
9642 +       struct list_head        list;
9643 +       struct at91_gpio_led    *led_data;
9644 +};
9645 +
9646 +/*
9647 + * Change the state of the LED.
9648 + */
9649 +static void at91_led_set(struct led_classdev *cdev, enum led_brightness value)
9650 +{
9651 +       struct at91_led *led = container_of(cdev, struct at91_led, cdev);
9652 +       short           active = (value == LED_OFF);
9653 +
9654 +       if (led->led_data->flags & 1)   /* active high/low? */
9655 +               active = !active;
9656 +       at91_set_gpio_value(led->led_data->gpio, value == LED_OFF);
9657 +}
9658 +
9659 +static int __devexit at91_led_remove(struct platform_device *pdev)
9660 +{
9661 +       struct at91_led         *led;
9662 +
9663 +       list_for_each_entry (led, &at91_led_list, list)
9664 +               led_classdev_unregister(&led->cdev);
9665 +
9666 +#warning "Free allocated memory"
9667 +       // TODO: Free memory.   kfree(led);
9668 +
9669 +       return 0;
9670 +}
9671 +
9672 +static int __init at91_led_probe(struct platform_device *pdev)
9673 +{
9674 +       int                     status = 0;
9675 +       struct at91_gpio_led    *pdata = pdev->dev.platform_data;
9676 +       unsigned                nr_leds;
9677 +       struct at91_led         *led;
9678 +
9679 +       if (!pdata)
9680 +               return -ENODEV;
9681 +
9682 +       nr_leds = pdata->index;         /* first index stores number of LEDs */
9683 +
9684 +       while (nr_leds--) {
9685 +               led = kzalloc(sizeof(struct at91_led), GFP_KERNEL);
9686 +               if (!led) {
9687 +                       dev_err(&pdev->dev, "No memory for device\n");
9688 +                       status = -ENOMEM;
9689 +                       goto cleanup;
9690 +               }
9691 +               led->led_data = pdata;
9692 +               led->cdev.name = pdata->name;
9693 +               led->cdev.brightness_set = at91_led_set,
9694 +               led->cdev.default_trigger = pdata->trigger;
9695 +
9696 +               status = led_classdev_register(&pdev->dev, &led->cdev);
9697 +               if (status < 0) {
9698 +                       dev_err(&pdev->dev, "led_classdev_register failed - %d\n", status);
9699 +cleanup:
9700 +                       at91_led_remove(pdev);
9701 +                       break;
9702 +               }
9703 +               list_add(&led->list, &at91_led_list);
9704 +               pdata++;
9705 +       }
9706 +       return status;
9707 +}
9708 +
9709 +#ifdef CONFIG_PM
9710 +static int at91_led_suspend(struct platform_device *dev, pm_message_t state)
9711 +{
9712 +       struct at91_led *led;
9713 +
9714 +       list_for_each_entry (led, &at91_led_list, list)
9715 +               led_classdev_suspend(&led->cdev);
9716 +
9717 +       return 0;
9718 +}
9719 +
9720 +static int at91_led_resume(struct platform_device *dev)
9721 +{
9722 +       struct at91_led *led;
9723 +
9724 +       list_for_each_entry (led, &at91_led_list, list)
9725 +               led_classdev_resume(&led->cdev);
9726 +
9727 +       return 0;
9728 +}
9729 +#else
9730 +#define        at91_led_suspend        NULL
9731 +#define        at91_led_resume         NULL
9732 +#endif
9733 +
9734 +static struct platform_driver at91_led_driver = {
9735 +       .probe          = at91_led_probe,
9736 +       .remove         = __devexit_p(at91_led_remove),
9737 +       .suspend        = at91_led_suspend,
9738 +       .resume         = at91_led_resume,
9739 +       .driver         = {
9740 +               .name   = "at91_leds",
9741 +               .owner  = THIS_MODULE,
9742 +       },
9743 +};
9744 +
9745 +static int __init at91_led_init(void)
9746 +{
9747 +       return platform_driver_register(&at91_led_driver);
9748 +}
9749 +module_init(at91_led_init);
9750 +
9751 +static void __exit at91_led_exit(void)
9752 +{
9753 +       platform_driver_unregister(&at91_led_driver);
9754 +}
9755 +module_exit(at91_led_exit);
9756 +
9757 +MODULE_DESCRIPTION("AT91 GPIO LED driver");
9758 +MODULE_AUTHOR("David Brownell");
9759 +MODULE_LICENSE("GPL");
9760 diff -urN -x CVS linux-2.6.19-final/drivers/mmc/Kconfig linux-2.6.19/drivers/mmc/Kconfig
9761 --- linux-2.6.19-final/drivers/mmc/Kconfig      Mon Dec  4 16:40:13 2006
9762 +++ linux-2.6.19/drivers/mmc/Kconfig    Thu Nov  9 14:16:55 2006
9763 @@ -91,11 +91,11 @@
9764
9765           If unsure, say N.
9766
9767 -config MMC_AT91RM9200
9768 -       tristate "AT91RM9200 SD/MMC Card Interface support"
9769 -       depends on ARCH_AT91RM9200 && MMC
9770 +config MMC_AT91
9771 +       tristate "AT91 SD/MMC Card Interface support"
9772 +       depends on ARCH_AT91 && MMC
9773         help
9774 -         This selects the AT91RM9200 MCI controller.
9775 +         This selects the AT91 MCI controller.
9776
9777           If unsure, say N.
9778
9779 diff -urN -x CVS linux-2.6.19-final/drivers/mmc/Makefile linux-2.6.19/drivers/mmc/Makefile
9780 --- linux-2.6.19-final/drivers/mmc/Makefile     Mon Dec  4 16:40:13 2006
9781 +++ linux-2.6.19/drivers/mmc/Makefile   Thu Nov  9 14:17:47 2006
9782 @@ -22,7 +22,7 @@
9783  obj-$(CONFIG_MMC_WBSD)         += wbsd.o
9784  obj-$(CONFIG_MMC_AU1X)         += au1xmmc.o
9785  obj-$(CONFIG_MMC_OMAP)         += omap.o
9786 -obj-$(CONFIG_MMC_AT91RM9200)   += at91_mci.o
9787 +obj-$(CONFIG_MMC_AT91)         += at91_mci.o
9788  obj-$(CONFIG_MMC_TIFM_SD)      += tifm_sd.o
9789
9790  mmc_core-y := mmc.o mmc_sysfs.o
9791 diff -urN -x CVS linux-2.6.19-final/drivers/mmc/at91_mci.c linux-2.6.19/drivers/mmc/at91_mci.c
9792 --- linux-2.6.19-final/drivers/mmc/at91_mci.c   Mon Dec  4 16:40:13 2006
9793 +++ linux-2.6.19/drivers/mmc/at91_mci.c Sat Nov 25 11:00:45 2006
9794 @@ -1,5 +1,5 @@
9795  /*
9796 - *  linux/drivers/mmc/at91_mci.c - ATMEL AT91RM9200 MCI Driver
9797 + *  linux/drivers/mmc/at91_mci.c - ATMEL AT91 MCI Driver
9798   *
9799   *  Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
9800   *
9801 @@ -11,7 +11,7 @@
9802   */
9803
9804  /*
9805 -   This is the AT91RM9200 MCI driver that has been tested with both MMC cards
9806 +   This is the AT91 MCI driver that has been tested with both MMC cards
9807     and SD-cards.  Boards that support write protect are now supported.
9808     The CCAT91SBC001 board does not support SD cards.
9809
9810 @@ -38,8 +38,8 @@
9811       controller to manage the transfers.
9812
9813       A read is done from the controller directly to the scatterlist passed in from the request.
9814 -     Due to a bug in the controller, when a read is completed, all the words are byte
9815 -     swapped in the scatterlist buffers.
9816 +     Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte
9817 +     swapped in the scatterlist buffers.  AT91SAM926x are not affected by this bug.
9818
9819       The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
9820
9821 @@ -72,42 +72,27 @@
9822  #include <asm/irq.h>
9823  #include <asm/mach/mmc.h>
9824  #include <asm/arch/board.h>
9825 +#include <asm/arch/cpu.h>
9826  #include <asm/arch/gpio.h>
9827 -#include <asm/arch/at91rm9200_mci.h>
9828 -#include <asm/arch/at91rm9200_pdc.h>
9829 +#include <asm/arch/at91_mci.h>
9830 +#include <asm/arch/at91_pdc.h>
9831
9832  #define DRIVER_NAME "at91_mci"
9833
9834  #undef SUPPORT_4WIRE
9835
9836 -static struct clk *mci_clk;
9837 +#define FL_SENT_COMMAND        (1 << 0)
9838 +#define FL_SENT_STOP   (1 << 1)
9839
9840 -#define FL_SENT_COMMAND (1 << 0)
9841 -#define FL_SENT_STOP (1 << 1)
9842 +#define AT91_MCI_ERRORS        (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE       \
9843 +                       | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE       \
9844 +                       | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
9845
9846 +#define at91_mci_read(host, reg)       __raw_readl((host)->baseaddr + (reg))
9847 +#define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg))
9848
9849
9850  /*
9851 - * Read from a MCI register.
9852 - */
9853 -static inline unsigned long at91_mci_read(unsigned int reg)
9854 -{
9855 -       void __iomem *mci_base = (void __iomem *)AT91_VA_BASE_MCI;
9856 -
9857 -       return __raw_readl(mci_base + reg);
9858 -}
9859 -
9860 -/*
9861 - * Write to a MCI register.
9862 - */
9863 -static inline void at91_mci_write(unsigned int reg, unsigned long value)
9864 -{
9865 -        void __iomem *mci_base = (void __iomem *)AT91_VA_BASE_MCI;
9866 -
9867 -        __raw_writel(value, mci_base + reg);
9868 -}
9869 -
9870 -/*
9871   * Low level type for this driver
9872   */
9873  struct at91mci_host
9874 @@ -116,9 +101,14 @@
9875         struct mmc_command *cmd;
9876         struct mmc_request *request;
9877
9878 +       void __iomem *baseaddr;
9879 +       int irq;
9880 +
9881         struct at91_mmc_data *board;
9882         int present;
9883
9884 +       struct clk *mci_clk;
9885 +
9886         /*
9887          * Flag indicating when the command has been sent. This is used to
9888          * work out whether or not to send the stop
9889 @@ -158,7 +148,6 @@
9890         for (i = 0; i < len; i++) {
9891                 struct scatterlist *sg;
9892                 int amount;
9893 -               int index;
9894                 unsigned int *sgbuffer;
9895
9896                 sg = &data->sg[i];
9897 @@ -166,10 +155,15 @@
9898                 sgbuffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
9899                 amount = min(size, sg->length);
9900                 size -= amount;
9901 -               amount /= 4;
9902 -
9903 -               for (index = 0; index < amount; index++)
9904 -                       *dmabuf++ = swab32(sgbuffer[index]);
9905 +
9906 +               if (cpu_is_at91rm9200()) {      /* AT91RM9200 errata */
9907 +                       int index;
9908 +
9909 +                       for (index = 0; index < (amount / 4); index++)
9910 +                               *dmabuf++ = swab32(sgbuffer[index]);
9911 +               }
9912 +               else
9913 +                       memcpy(dmabuf, sgbuffer, amount);
9914
9915                 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
9916
9917 @@ -217,13 +211,13 @@
9918
9919                 /* Check to see if this needs filling */
9920                 if (i == 0) {
9921 -                       if (at91_mci_read(AT91_PDC_RCR) != 0) {
9922 +                       if (at91_mci_read(host, AT91_PDC_RCR) != 0) {
9923                                 pr_debug("Transfer active in current\n");
9924                                 continue;
9925                         }
9926                 }
9927                 else {
9928 -                       if (at91_mci_read(AT91_PDC_RNCR) != 0) {
9929 +                       if (at91_mci_read(host, AT91_PDC_RNCR) != 0) {
9930                                 pr_debug("Transfer active in next\n");
9931                                 continue;
9932                         }
9933 @@ -240,12 +234,12 @@
9934                 pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length);
9935
9936                 if (i == 0) {
9937 -                       at91_mci_write(AT91_PDC_RPR, sg->dma_address);
9938 -                       at91_mci_write(AT91_PDC_RCR, sg->length / 4);
9939 +                       at91_mci_write(host, AT91_PDC_RPR, sg->dma_address);
9940 +                       at91_mci_write(host, AT91_PDC_RCR, sg->length / 4);
9941                 }
9942                 else {
9943 -                       at91_mci_write(AT91_PDC_RNPR, sg->dma_address);
9944 -                       at91_mci_write(AT91_PDC_RNCR, sg->length / 4);
9945 +                       at91_mci_write(host, AT91_PDC_RNPR, sg->dma_address);
9946 +                       at91_mci_write(host, AT91_PDC_RNCR, sg->length / 4);
9947                 }
9948         }
9949
9950 @@ -276,8 +270,6 @@
9951
9952         while (host->in_use_index < host->transfer_index) {
9953                 unsigned int *buffer;
9954 -               int index;
9955 -               int len;
9956
9957                 struct scatterlist *sg;
9958
9959 @@ -295,11 +287,14 @@
9960
9961                 data->bytes_xfered += sg->length;
9962
9963 -               len = sg->length / 4;
9964 -
9965 -               for (index = 0; index < len; index++) {
9966 -                       buffer[index] = swab32(buffer[index]);
9967 +               if (cpu_is_at91rm9200()) {      /* AT91RM9200 errata */
9968 +                       int index;
9969 +
9970 +                       for (index = 0; index < (sg->length / 4); index++) {
9971 +                               buffer[index] = swab32(buffer[index]);
9972 +                       }
9973                 }
9974 +
9975                 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
9976                 flush_dcache_page(sg->page);
9977         }
9978 @@ -308,57 +303,34 @@
9979         if (host->transfer_index < data->sg_len)
9980                 at91mci_pre_dma_read(host);
9981         else {
9982 -               at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF);
9983 -               at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
9984 +               at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF);
9985 +               at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
9986         }
9987
9988         pr_debug("post dma read done\n");
9989  }
9990
9991 -/*
9992 - * Handle transmitted data
9993 - */
9994 -static void at91_mci_handle_transmitted(struct at91mci_host *host)
9995 -{
9996 -       struct mmc_command *cmd;
9997 -       struct mmc_data *data;
9998 -
9999 -       pr_debug("Handling the transmit\n");
10000 -
10001 -       /* Disable the transfer */
10002 -       at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
10003 -
10004 -       /* Now wait for cmd ready */
10005 -       at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE);
10006 -       at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
10007 -
10008 -       cmd = host->cmd;
10009 -       if (!cmd) return;
10010 -
10011 -       data = cmd->data;
10012 -       if (!data) return;
10013 -
10014 -       data->bytes_xfered = host->total_length;
10015 -}
10016
10017  /*
10018   * Enable the controller
10019   */
10020 -static void at91_mci_enable(void)
10021 +static void at91_mci_enable(struct at91mci_host *host)
10022  {
10023 -       at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
10024 -       at91_mci_write(AT91_MCI_IDR, 0xFFFFFFFF);
10025 -       at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
10026 -       at91_mci_write(AT91_MCI_MR, 0x834A);
10027 -       at91_mci_write(AT91_MCI_SDCR, 0x0);
10028 +       at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
10029 +       at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
10030 +       at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
10031 +       at91_mci_write(host, AT91_MCI_MR, AT91_MCI_PDCMODE | 0x34a);
10032 +
10033 +       /* use Slot A or B (only one at same time) */
10034 +       at91_mci_write(host, AT91_MCI_SDCR,  host->board->slot_b);
10035  }
10036
10037  /*
10038   * Disable the controller
10039   */
10040 -static void at91_mci_disable(void)
10041 +static void at91_mci_disable(struct at91mci_host *host)
10042  {
10043 -       at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
10044 +       at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
10045  }
10046
10047  /*
10048 @@ -378,13 +350,13 @@
10049
10050         /* Not sure if this is needed */
10051  #if 0
10052 -       if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
10053 +       if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
10054                 pr_debug("Clearing timeout\n");
10055 -               at91_mci_write(AT91_MCI_ARGR, 0);
10056 -               at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD);
10057 -               while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
10058 +               at91_mci_write(host, AT91_MCI_ARGR, 0);
10059 +               at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD);
10060 +               while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
10061                         /* spin */
10062 -                       pr_debug("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR));
10063 +                       pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR));
10064                 }
10065         }
10066  #endif
10067 @@ -431,32 +403,32 @@
10068         /*
10069          * Set the arguments and send the command
10070          */
10071 -       pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08lX)\n",
10072 -               cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR));
10073 +       pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
10074 +               cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR));
10075
10076         if (!data) {
10077 -               at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
10078 -               at91_mci_write(AT91_PDC_RPR, 0);
10079 -               at91_mci_write(AT91_PDC_RCR, 0);
10080 -               at91_mci_write(AT91_PDC_RNPR, 0);
10081 -               at91_mci_write(AT91_PDC_RNCR, 0);
10082 -               at91_mci_write(AT91_PDC_TPR, 0);
10083 -               at91_mci_write(AT91_PDC_TCR, 0);
10084 -               at91_mci_write(AT91_PDC_TNPR, 0);
10085 -               at91_mci_write(AT91_PDC_TNCR, 0);
10086 +               at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
10087 +               at91_mci_write(host, AT91_PDC_RPR, 0);
10088 +               at91_mci_write(host, AT91_PDC_RCR, 0);
10089 +               at91_mci_write(host, AT91_PDC_RNPR, 0);
10090 +               at91_mci_write(host, AT91_PDC_RNCR, 0);
10091 +               at91_mci_write(host, AT91_PDC_TPR, 0);
10092 +               at91_mci_write(host, AT91_PDC_TCR, 0);
10093 +               at91_mci_write(host, AT91_PDC_TNPR, 0);
10094 +               at91_mci_write(host, AT91_PDC_TNCR, 0);
10095
10096 -               at91_mci_write(AT91_MCI_ARGR, cmd->arg);
10097 -               at91_mci_write(AT91_MCI_CMDR, cmdr);
10098 +               at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
10099 +               at91_mci_write(host, AT91_MCI_CMDR, cmdr);
10100                 return AT91_MCI_CMDRDY;
10101         }
10102
10103 -       mr = at91_mci_read(AT91_MCI_MR) & 0x7fff;       /* zero block length and PDC mode */
10104 -       at91_mci_write(AT91_MCI_MR, mr | (block_length << 16) | AT91_MCI_PDCMODE);
10105 +       mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; /* zero block length and PDC mode */
10106 +       at91_mci_write(host, AT91_MCI_MR, mr | (block_length << 16) | AT91_MCI_PDCMODE);
10107
10108         /*
10109          * Disable the PDC controller
10110          */
10111 -       at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
10112 +       at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
10113
10114         if (cmdr & AT91_MCI_TRCMD_START) {
10115                 data->bytes_xfered = 0;
10116 @@ -478,15 +450,15 @@
10117                          */
10118                         host->total_length = block_length * blocks;
10119                         host->buffer = dma_alloc_coherent(NULL,
10120 -                                                 host->total_length,
10121 -                                                 &host->physical_address, GFP_KERNEL);
10122 +                                               host->total_length,
10123 +                                               &host->physical_address, GFP_KERNEL);
10124
10125                         at91mci_sg_to_dma(host, data);
10126
10127                         pr_debug("Transmitting %d bytes\n", host->total_length);
10128
10129 -                       at91_mci_write(AT91_PDC_TPR, host->physical_address);
10130 -                       at91_mci_write(AT91_PDC_TCR, host->total_length / 4);
10131 +                       at91_mci_write(host, AT91_PDC_TPR, host->physical_address);
10132 +                       at91_mci_write(host, AT91_PDC_TCR, host->total_length / 4);
10133                         ier = AT91_MCI_TXBUFE;
10134                 }
10135         }
10136 @@ -496,14 +468,14 @@
10137          * the data sheet says
10138          */
10139
10140 -       at91_mci_write(AT91_MCI_ARGR, cmd->arg);
10141 -       at91_mci_write(AT91_MCI_CMDR, cmdr);
10142 +       at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
10143 +       at91_mci_write(host, AT91_MCI_CMDR, cmdr);
10144
10145         if (cmdr & AT91_MCI_TRCMD_START) {
10146                 if (cmdr & AT91_MCI_TRDIR)
10147 -                       at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN);
10148 +                       at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTEN);
10149                 else
10150 -                       at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN);
10151 +                       at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_TXTEN);
10152         }
10153         return ier;
10154  }
10155 @@ -520,7 +492,7 @@
10156         pr_debug("setting ier to %08X\n", ier);
10157
10158         /* Stop on errors or the required value */
10159 -       at91_mci_write(AT91_MCI_IER, 0xffff0000 | ier);
10160 +       at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier);
10161  }
10162
10163  /*
10164 @@ -548,26 +520,24 @@
10165         struct mmc_command *cmd = host->cmd;
10166         unsigned int status;
10167
10168 -       at91_mci_write(AT91_MCI_IDR, 0xffffffff);
10169 +       at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
10170
10171 -       cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0));
10172 -       cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1));
10173 -       cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2));
10174 -       cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3));
10175 +       cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0));
10176 +       cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1));
10177 +       cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2));
10178 +       cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3));
10179
10180         if (host->buffer) {
10181                 dma_free_coherent(NULL, host->total_length, host->buffer, host->physical_address);
10182                 host->buffer = NULL;
10183         }
10184
10185 -       status = at91_mci_read(AT91_MCI_SR);
10186 +       status = at91_mci_read(host, AT91_MCI_SR);
10187
10188         pr_debug("Status = %08X [%08X %08X %08X %08X]\n",
10189                  status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
10190
10191 -       if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE |
10192 -                       AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE |
10193 -                       AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)) {
10194 +       if (status & AT91_MCI_ERRORS) {
10195                 if ((status & AT91_MCI_RCRCE) &&
10196                         ((cmd->opcode == MMC_SEND_OP_COND) || (cmd->opcode == SD_APP_OP_COND))) {
10197                         cmd->error = MMC_ERR_NONE;
10198 @@ -605,24 +575,50 @@
10199  }
10200
10201  /*
10202 + * Handle transmitted data
10203 + */
10204 +static void at91_mci_handle_transmitted(struct at91mci_host *host)
10205 +{
10206 +       struct mmc_command *cmd;
10207 +       struct mmc_data *data;
10208 +
10209 +       pr_debug("Handling the transmit\n");
10210 +
10211 +       /* Disable the transfer */
10212 +       at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
10213 +
10214 +       /* Now wait for cmd ready */
10215 +       at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE);
10216 +       at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
10217 +
10218 +       cmd = host->cmd;
10219 +       if (!cmd) return;
10220 +
10221 +       data = cmd->data;
10222 +       if (!data) return;
10223 +
10224 +       data->bytes_xfered = host->total_length;
10225 +}
10226 +
10227 +/*
10228   * Set the IOS
10229   */
10230  static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
10231  {
10232         int clkdiv;
10233         struct at91mci_host *host = mmc_priv(mmc);
10234 -       unsigned long at91_master_clock = clk_get_rate(mci_clk);
10235 +       unsigned long at91_master_clock = clk_get_rate(host->mci_clk);
10236
10237         host->bus_mode = ios->bus_mode;
10238
10239         if (ios->clock == 0) {
10240                 /* Disable the MCI controller */
10241 -               at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS);
10242 +               at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS);
10243                 clkdiv = 0;
10244         }
10245         else {
10246                 /* Enable the MCI controller */
10247 -               at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
10248 +               at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
10249
10250                 if ((at91_master_clock % (ios->clock * 2)) == 0)
10251                         clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
10252 @@ -634,25 +630,25 @@
10253         }
10254         if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
10255                 pr_debug("MMC: Setting controller bus width to 4\n");
10256 -               at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
10257 +               at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
10258         }
10259         else {
10260                 pr_debug("MMC: Setting controller bus width to 1\n");
10261 -               at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
10262 +               at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
10263         }
10264
10265         /* Set the clock divider */
10266 -       at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
10267 +       at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
10268
10269         /* maybe switch power to the card */
10270         if (host->board->vcc_pin) {
10271                 switch (ios->power_mode) {
10272                         case MMC_POWER_OFF:
10273 -                               at91_set_gpio_output(host->board->vcc_pin, 0);
10274 +                               at91_set_gpio_value(host->board->vcc_pin, 0);
10275                                 break;
10276                         case MMC_POWER_UP:
10277                         case MMC_POWER_ON:
10278 -                               at91_set_gpio_output(host->board->vcc_pin, 1);
10279 +                               at91_set_gpio_value(host->board->vcc_pin, 1);
10280                                 break;
10281                 }
10282         }
10283 @@ -665,39 +661,40 @@
10284  {
10285         struct at91mci_host *host = devid;
10286         int completed = 0;
10287 +       unsigned int int_status, int_mask;
10288
10289 -       unsigned int int_status;
10290 +       int_status = at91_mci_read(host, AT91_MCI_SR);
10291 +       int_mask = at91_mci_read(host, AT91_MCI_IMR);
10292
10293 -       int_status = at91_mci_read(AT91_MCI_SR);
10294 -       pr_debug("MCI irq: status = %08X, %08lX, %08lX\n", int_status, at91_mci_read(AT91_MCI_IMR),
10295 -               int_status & at91_mci_read(AT91_MCI_IMR));
10296 -
10297 -       if ((int_status & at91_mci_read(AT91_MCI_IMR)) & 0xffff0000)
10298 -               completed = 1;
10299 +       pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
10300 +               int_status & int_mask);
10301
10302 -       int_status &= at91_mci_read(AT91_MCI_IMR);
10303 +       int_status = int_status & int_mask;
10304
10305 -       if (int_status & AT91_MCI_UNRE)
10306 -               pr_debug("MMC: Underrun error\n");
10307 -       if (int_status & AT91_MCI_OVRE)
10308 -               pr_debug("MMC: Overrun error\n");
10309 -       if (int_status & AT91_MCI_DTOE)
10310 -               pr_debug("MMC: Data timeout\n");
10311 -       if (int_status & AT91_MCI_DCRCE)
10312 -               pr_debug("MMC: CRC error in data\n");
10313 -       if (int_status & AT91_MCI_RTOE)
10314 -               pr_debug("MMC: Response timeout\n");
10315 -       if (int_status & AT91_MCI_RENDE)
10316 -               pr_debug("MMC: Response end bit error\n");
10317 -       if (int_status & AT91_MCI_RCRCE)
10318 -               pr_debug("MMC: Response CRC error\n");
10319 -       if (int_status & AT91_MCI_RDIRE)
10320 -               pr_debug("MMC: Response direction error\n");
10321 -       if (int_status & AT91_MCI_RINDE)
10322 -               pr_debug("MMC: Response index error\n");
10323 +       if (int_status & AT91_MCI_ERRORS) {
10324 +               completed = 1;
10325 +
10326 +               if (int_status & AT91_MCI_UNRE)
10327 +                       pr_debug("MMC: Underrun error\n");
10328 +               if (int_status & AT91_MCI_OVRE)
10329 +                       pr_debug("MMC: Overrun error\n");
10330 +               if (int_status & AT91_MCI_DTOE)
10331 +                       pr_debug("MMC: Data timeout\n");
10332 +               if (int_status & AT91_MCI_DCRCE)
10333 +                       pr_debug("MMC: CRC error in data\n");
10334 +               if (int_status & AT91_MCI_RTOE)
10335 +                       pr_debug("MMC: Response timeout\n");
10336 +               if (int_status & AT91_MCI_RENDE)
10337 +                       pr_debug("MMC: Response end bit error\n");
10338 +               if (int_status & AT91_MCI_RCRCE)
10339 +                       pr_debug("MMC: Response CRC error\n");
10340 +               if (int_status & AT91_MCI_RDIRE)
10341 +                       pr_debug("MMC: Response direction error\n");
10342 +               if (int_status & AT91_MCI_RINDE)
10343 +                       pr_debug("MMC: Response index error\n");
10344 +       } else {
10345 +               /* Only continue processing if no errors */
10346
10347 -       /* Only continue processing if no errors */
10348 -       if (!completed) {
10349                 if (int_status & AT91_MCI_TXBUFE) {
10350                         pr_debug("TX buffer empty\n");
10351                         at91_mci_handle_transmitted(host);
10352 @@ -705,12 +702,11 @@
10353
10354                 if (int_status & AT91_MCI_RXBUFF) {
10355                         pr_debug("RX buffer full\n");
10356 -                       at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY);
10357 +                       at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY);
10358                 }
10359
10360 -               if (int_status & AT91_MCI_ENDTX) {
10361 +               if (int_status & AT91_MCI_ENDTX)
10362                         pr_debug("Transmit has ended\n");
10363 -               }
10364
10365                 if (int_status & AT91_MCI_ENDRX) {
10366                         pr_debug("Receive has ended\n");
10367 @@ -719,37 +715,33 @@
10368
10369                 if (int_status & AT91_MCI_NOTBUSY) {
10370                         pr_debug("Card is ready\n");
10371 -                       at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY);
10372 +                       at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY);
10373                 }
10374
10375 -               if (int_status & AT91_MCI_DTIP) {
10376 +               if (int_status & AT91_MCI_DTIP)
10377                         pr_debug("Data transfer in progress\n");
10378 -               }
10379
10380 -               if (int_status & AT91_MCI_BLKE) {
10381 +               if (int_status & AT91_MCI_BLKE)
10382                         pr_debug("Block transfer has ended\n");
10383 -               }
10384
10385 -               if (int_status & AT91_MCI_TXRDY) {
10386 +               if (int_status & AT91_MCI_TXRDY)
10387                         pr_debug("Ready to transmit\n");
10388 -               }
10389
10390 -               if (int_status & AT91_MCI_RXRDY) {
10391 +               if (int_status & AT91_MCI_RXRDY)
10392                         pr_debug("Ready to receive\n");
10393 -               }
10394
10395                 if (int_status & AT91_MCI_CMDRDY) {
10396                         pr_debug("Command ready\n");
10397                         completed = 1;
10398                 }
10399         }
10400 -       at91_mci_write(AT91_MCI_IDR, int_status);
10401
10402         if (completed) {
10403                 pr_debug("Completed command\n");
10404 -               at91_mci_write(AT91_MCI_IDR, 0xffffffff);
10405 +               at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
10406                 at91mci_completed_command(host);
10407 -       }
10408 +       } else
10409 +               at91_mci_write(host, AT91_MCI_IDR, int_status);
10410
10411         return IRQ_HANDLED;
10412  }
10413 @@ -769,7 +761,7 @@
10414                         present ? "insert" : "remove");
10415                 if (!present) {
10416                         pr_debug("****** Resetting SD-card bus width ******\n");
10417 -                       at91_mci_write(AT91_MCI_SDCR, 0);
10418 +                       at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
10419                 }
10420                 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
10421         }
10422 @@ -806,15 +798,22 @@
10423  {
10424         struct mmc_host *mmc;
10425         struct at91mci_host *host;
10426 +       struct resource *res;
10427         int ret;
10428
10429         pr_debug("Probe MCI devices\n");
10430 -       at91_mci_disable();
10431 -       at91_mci_enable();
10432 +
10433 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
10434 +       if (!res)
10435 +               return -ENXIO;
10436 +
10437 +       if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME))
10438 +               return -EBUSY;
10439
10440         mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev);
10441         if (!mmc) {
10442                 pr_debug("Failed to allocate mmc host\n");
10443 +               release_mem_region(res->start, res->end - res->start + 1);
10444                 return -ENOMEM;
10445         }
10446
10447 @@ -822,7 +821,7 @@
10448         mmc->f_min = 375000;
10449         mmc->f_max = 25000000;
10450         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
10451 -       mmc->caps = MMC_CAP_BYTEBLOCK;
10452 +       mmc->caps = MMC_CAP_BYTEBLOCK | MMC_CAP_MULTIWRITE;
10453
10454         host = mmc_priv(mmc);
10455         host->mmc = mmc;
10456 @@ -833,29 +832,50 @@
10457  #ifdef SUPPORT_4WIRE
10458                 mmc->caps |= MMC_CAP_4_BIT_DATA;
10459  #else
10460 -               printk("MMC: 4 wire bus mode not supported by this driver - using 1 wire\n");
10461 +               printk("AT91 MMC: 4 wire bus mode not supported by this driver - using 1 wire\n");
10462  #endif
10463         }
10464
10465         /*
10466          * Get Clock
10467          */
10468 -       mci_clk = clk_get(&pdev->dev, "mci_clk");
10469 -       if (IS_ERR(mci_clk)) {
10470 +       host->mci_clk = clk_get(&pdev->dev, "mci_clk");
10471 +       if (IS_ERR(host->mci_clk)) {
10472                 printk(KERN_ERR "AT91 MMC: no clock defined.\n");
10473                 mmc_free_host(mmc);
10474 +               release_mem_region(res->start, res->end - res->start + 1);
10475                 return -ENODEV;
10476         }
10477 -       clk_enable(mci_clk);                    /* Enable the peripheral clock */
10478 +
10479 +       /*
10480 +        * Map I/O region
10481 +        */
10482 +       host->baseaddr = ioremap(res->start, res->end - res->start + 1);
10483 +       if (!host->baseaddr) {
10484 +               clk_put(host->mci_clk);
10485 +               release_mem_region(res->start, res->end - res->start + 1);
10486 +               mmc_free_host(mmc);
10487 +               return -ENOMEM;
10488 +       }
10489 +
10490 +       /*
10491 +        * Reset hardware
10492 +        */
10493 +       clk_enable(host->mci_clk);      /* Enable the peripheral clock */
10494 +       at91_mci_disable(host);
10495 +       at91_mci_enable(host);
10496
10497         /*
10498          * Allocate the MCI interrupt
10499          */
10500 -       ret = request_irq(AT91RM9200_ID_MCI, at91_mci_irq, IRQF_SHARED, DRIVER_NAME, host);
10501 +       host->irq = platform_get_irq(pdev, 0);
10502 +       ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED, DRIVER_NAME, host);
10503         if (ret) {
10504 -               printk(KERN_ERR "Failed to request MCI interrupt\n");
10505 -               clk_disable(mci_clk);
10506 -               clk_put(mci_clk);
10507 +               printk(KERN_ERR "AT91 MMC: Failed to request MCI interrupt\n");
10508 +               clk_disable(host->mci_clk);
10509 +               clk_put(host->mci_clk);
10510 +               iounmap(host->baseaddr);
10511 +               release_mem_region(res->start, res->end - res->start + 1);
10512                 mmc_free_host(mmc);
10513                 return ret;
10514         }
10515 @@ -879,10 +899,10 @@
10516                 ret = request_irq(host->board->det_pin, at91_mmc_det_irq,
10517                                 0, DRIVER_NAME, host);
10518                 if (ret)
10519 -                       printk(KERN_ERR "couldn't allocate MMC detect irq\n");
10520 +                       printk(KERN_ERR "AT91 MMC: Couldn't allocate MMC detect irq\n");
10521         }
10522
10523 -       pr_debug(KERN_INFO "Added MCI driver\n");
10524 +       pr_debug("Added MCI driver\n");
10525
10526         return 0;
10527  }
10528 @@ -894,6 +914,7 @@
10529  {
10530         struct mmc_host *mmc = platform_get_drvdata(pdev);
10531         struct at91mci_host *host;
10532 +       struct resource *res;
10533
10534         if (!mmc)
10535                 return -1;
10536 @@ -905,16 +926,19 @@
10537                 cancel_delayed_work(&host->mmc->detect);
10538         }
10539
10540 +       at91_mci_disable(host);
10541         mmc_remove_host(mmc);
10542 -       at91_mci_disable();
10543 -       free_irq(AT91RM9200_ID_MCI, host);
10544 -       mmc_free_host(mmc);
10545 +       free_irq(host->irq, host);
10546
10547 -       clk_disable(mci_clk);                           /* Disable the peripheral clock */
10548 -       clk_put(mci_clk);
10549 +       iounmap(host->baseaddr);
10550 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
10551 +       release_mem_region(res->start, res->end - res->start + 1);
10552
10553 -       platform_set_drvdata(pdev, NULL);
10554 +       clk_disable(host->mci_clk);                     /* Disable the peripheral clock */
10555 +       clk_put(host->mci_clk);
10556
10557 +       mmc_free_host(mmc);
10558 +       platform_set_drvdata(pdev, NULL);
10559         pr_debug("MCI Removed\n");
10560
10561         return 0;
10562 diff -urN -x CVS linux-2.6.19-final/drivers/mtd/devices/Kconfig linux-2.6.19/drivers/mtd/devices/Kconfig
10563 --- linux-2.6.19-final/drivers/mtd/devices/Kconfig      Mon Dec  4 16:40:13 2006
10564 +++ linux-2.6.19/drivers/mtd/devices/Kconfig    Wed Nov 22 09:22:03 2006
10565 @@ -267,5 +267,11 @@
10566           LinuxBIOS or if you need to recover a DiskOnChip Millennium on which
10567           you have managed to wipe the first block.
10568
10569 -endmenu
10570 +config MTD_AT91_DATAFLASH
10571 +       tristate "AT91RM9200 DataFlash AT45DBxxx (legacy driver)"
10572 +       depends on MTD && ARCH_AT91RM9200 && AT91_SPI
10573 +       help
10574 +         This enables access to the DataFlash (AT45DBxxx) on the AT91RM9200.
10575 +         If you have such a board, say 'Y'.
10576
10577 +endmenu
10578 diff -urN -x CVS linux-2.6.19-final/drivers/mtd/devices/Makefile linux-2.6.19/drivers/mtd/devices/Makefile
10579 --- linux-2.6.19-final/drivers/mtd/devices/Makefile     Mon Dec  4 16:33:42 2006
10580 +++ linux-2.6.19/drivers/mtd/devices/Makefile   Thu Oct 12 17:07:39 2006
10581 @@ -17,3 +17,4 @@
10582  obj-$(CONFIG_MTD_BLOCK2MTD)    += block2mtd.o
10583  obj-$(CONFIG_MTD_DATAFLASH)    += mtd_dataflash.o
10584  obj-$(CONFIG_MTD_M25P80)       += m25p80.o
10585 +obj-$(CONFIG_MTD_AT91_DATAFLASH)+= at91_dataflash.o
10586 diff -urN -x CVS linux-2.6.19-final/drivers/mtd/devices/at91_dataflash.c linux-2.6.19/drivers/mtd/devices/at91_dataflash.c
10587 --- linux-2.6.19-final/drivers/mtd/devices/at91_dataflash.c     Thu Jan  1 02:00:00 1970
10588 +++ linux-2.6.19/drivers/mtd/devices/at91_dataflash.c   Mon Dec  4 16:12:44 2006
10589 @@ -0,0 +1,640 @@
10590 +/*
10591 + * Atmel DataFlash driver for Atmel AT91RM9200 (Thunder)
10592 + *
10593 + *  Copyright (C) SAN People (Pty) Ltd
10594 + *
10595 + * This program is free software; you can redistribute it and/or
10596 + * modify it under the terms of the GNU General Public License
10597 + * as published by the Free Software Foundation; either version
10598 + * 2 of the License, or (at your option) any later version.
10599 +*/
10600 +
10601 +#include <linux/module.h>
10602 +#include <linux/init.h>
10603 +#include <linux/slab.h>
10604 +#include <linux/pci.h>
10605 +#include <linux/mtd/mtd.h>
10606 +#include <linux/mtd/partitions.h>
10607 +
10608 +#include <asm/arch/spi.h>
10609 +
10610 +#undef DEBUG_DATAFLASH
10611 +
10612 +#define DATAFLASH_MAX_DEVICES  4       /* max number of dataflash devices */
10613 +#undef DATAFLASH_ALWAYS_ADD_DEVICE     /* always add whole device when using partitions? */
10614 +
10615 +#define OP_READ_CONTINUOUS     0xE8
10616 +#define OP_READ_PAGE           0xD2
10617 +#define OP_READ_BUFFER1                0xD4
10618 +#define OP_READ_BUFFER2                0xD6
10619 +#define OP_READ_STATUS         0xD7
10620 +
10621 +#define OP_ERASE_PAGE          0x81
10622 +#define OP_ERASE_BLOCK         0x50
10623 +
10624 +#define OP_TRANSFER_BUF1       0x53
10625 +#define OP_TRANSFER_BUF2       0x55
10626 +#define OP_COMPARE_BUF1                0x60
10627 +#define OP_COMPARE_BUF2                0x61
10628 +
10629 +#define OP_PROGRAM_VIA_BUF1    0x82
10630 +#define OP_PROGRAM_VIA_BUF2    0x85
10631 +
10632 +struct dataflash_local
10633 +{
10634 +       int spi;                        /* SPI chip-select number */
10635 +
10636 +       unsigned int page_size;         /* number of bytes per page */
10637 +       unsigned short page_offset;     /* page offset in flash address */
10638 +};
10639 +
10640 +
10641 +/* Detected DataFlash devices */
10642 +static struct mtd_info* mtd_devices[DATAFLASH_MAX_DEVICES];
10643 +static int nr_devices = 0;
10644 +
10645 +/* ......................................................................... */
10646 +
10647 +#ifdef CONFIG_MTD_PARTITIONS
10648 +
10649 +static struct mtd_partition static_partitions_2M[] =
10650 +{
10651 +       {
10652 +               .name           = "bootloader",
10653 +               .offset         = 0,
10654 +               .size           = 1 * 32 * 8 * 528,     /* 1st sector = 32 blocks * 8 pages * 528 bytes */
10655 +               .mask_flags     = MTD_WRITEABLE,        /* read-only */
10656 +       },
10657 +       {
10658 +               .name           = "kernel",
10659 +               .offset         = MTDPART_OFS_NXTBLK,
10660 +               .size           = 6 * 32 * 8 * 528,     /* 6 sectors */
10661 +       },
10662 +       {
10663 +               .name           = "filesystem",
10664 +               .offset         = MTDPART_OFS_NXTBLK,
10665 +               .size           = MTDPART_SIZ_FULL,     /* rest = 9 sectors */
10666 +       }
10667 +};
10668 +
10669 +static struct mtd_partition static_partitions_4M[] =
10670 +{
10671 +       {
10672 +               .name           = "bootloader",
10673 +               .offset         = 0,
10674 +               .size           = 1 * 64 * 8 * 528,     /* 1st sector = 64 blocks * 8 pages * 528 bytes */
10675 +               .mask_flags     = MTD_WRITEABLE,        /* read-only */
10676 +       },
10677 +       {
10678 +               .name           = "kernel",
10679 +               .offset         = MTDPART_OFS_NXTBLK,
10680 +               .size           = 4 * 64 * 8 * 528,     /* 4 sectors */
10681 +       },
10682 +       {
10683 +               .name           = "filesystem",
10684 +               .offset         = MTDPART_OFS_NXTBLK,
10685 +               .size           = MTDPART_SIZ_FULL,     /* rest = 11 sectors */
10686 +       }
10687 +};
10688 +
10689 +#if defined(CONFIG_MACH_KAFA)
10690 +static struct mtd_partition static_partitions_8M[] =
10691 +{
10692 +       {
10693 +               name:           "romboot",
10694 +               offset:         0,
10695 +               size:           16 * 1056,      /* 160 Kb */
10696 +               mask_flags:     MTD_WRITEABLE,          /* read-only */
10697 +       },
10698 +       {
10699 +               name:           "uboot",
10700 +               offset:         MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
10701 +               size:           128 * 1056,             /* 1 MB  */
10702 +       },
10703 +       {
10704 +               name:           "kernel",
10705 +               offset:         MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
10706 +               size:           1024 * 1056,            /* 1 MB  */
10707 +       },
10708 +       {
10709 +               name:           "filesystem",
10710 +               offset:         MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
10711 +               size:           MTDPART_SIZ_FULL,
10712 +       }
10713 +};
10714 +
10715 +#else
10716 +
10717 +static struct mtd_partition static_partitions_8M[] =
10718 +{
10719 +       {
10720 +               .name           = "bootloader",
10721 +               .offset         = 0,
10722 +               .size           = 1 * 32 * 8 * 1056,    /* 1st sector = 32 blocks * 8 pages * 1056 bytes */
10723 +               .mask_flags     = MTD_WRITEABLE,        /* read-only */
10724 +       },
10725 +       {
10726 +               .name           = "kernel",
10727 +               .offset         = MTDPART_OFS_NXTBLK,
10728 +               .size           = 5 * 32 * 8 * 1056,    /* 5 sectors */
10729 +       },
10730 +       {
10731 +               .name           = "filesystem",
10732 +               .offset         = MTDPART_OFS_NXTBLK,
10733 +               .size           = MTDPART_SIZ_FULL,     /* rest = 26 sectors */
10734 +       }
10735 +};
10736 +#endif
10737 +
10738 +static const char *part_probes[] = { "cmdlinepart", NULL, };
10739 +
10740 +#endif
10741 +
10742 +/* ......................................................................... */
10743 +
10744 +/* Allocate a single SPI transfer descriptor.  We're assuming that if multiple
10745 +   SPI transfers occur at the same time, spi_access_bus() will serialize them.
10746 +   If this is not valid, then either (i) each dataflash 'priv' structure
10747 +   needs it's own transfer descriptor, (ii) we lock this one, or (iii) use
10748 +   another mechanism.   */
10749 +static struct spi_transfer_list* spi_transfer_desc;
10750 +
10751 +/*
10752 + * Perform a SPI transfer to access the DataFlash device.
10753 + */
10754 +static int do_spi_transfer(int nr, char* tx, int tx_len, char* rx, int rx_len,
10755 +               char* txnext, int txnext_len, char* rxnext, int rxnext_len)
10756 +{
10757 +       struct spi_transfer_list* list = spi_transfer_desc;
10758 +
10759 +       list->tx[0] = tx;       list->txlen[0] = tx_len;
10760 +       list->rx[0] = rx;       list->rxlen[0] = rx_len;
10761 +
10762 +       list->tx[1] = txnext;   list->txlen[1] = txnext_len;
10763 +       list->rx[1] = rxnext;   list->rxlen[1] = rxnext_len;
10764 +
10765 +       list->nr_transfers = nr;
10766 +
10767 +       return spi_transfer(list);
10768 +}
10769 +
10770 +/* ......................................................................... */
10771 +
10772 +/*
10773 + * Poll the DataFlash device until it is READY.
10774 + */
10775 +static void at91_dataflash_waitready(void)
10776 +{
10777 +       char* command = kmalloc(2, GFP_KERNEL);
10778 +
10779 +       if (!command)
10780 +               return;
10781 +
10782 +       do {
10783 +               command[0] = OP_READ_STATUS;
10784 +               command[1] = 0;
10785 +
10786 +               do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0);
10787 +       } while ((command[1] & 0x80) == 0);
10788 +
10789 +       kfree(command);
10790 +}
10791 +
10792 +/*
10793 + * Return the status of the DataFlash device.
10794 + */
10795 +static unsigned short at91_dataflash_status(void)
10796 +{
10797 +       unsigned short status;
10798 +       char* command = kmalloc(2, GFP_KERNEL);
10799 +
10800 +       if (!command)
10801 +               return 0;
10802 +
10803 +       command[0] = OP_READ_STATUS;
10804 +       command[1] = 0;
10805 +
10806 +       do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0);
10807 +       status = command[1];
10808 +
10809 +       kfree(command);
10810 +       return status;
10811 +}
10812 +
10813 +/* ......................................................................... */
10814 +
10815 +/*
10816 + * Erase blocks of flash.
10817 + */
10818 +static int at91_dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
10819 +{
10820 +       struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
10821 +       unsigned int pageaddr;
10822 +       char* command;
10823 +
10824 +#ifdef DEBUG_DATAFLASH
10825 +       printk("dataflash_erase: addr=%i len=%i\n", instr->addr, instr->len);
10826 +#endif
10827 +
10828 +       /* Sanity checks */
10829 +       if (instr->addr + instr->len > mtd->size)
10830 +               return -EINVAL;
10831 +       if ((instr->len % mtd->erasesize != 0) || (instr->len % priv->page_size != 0))
10832 +               return -EINVAL;
10833 +       if ((instr->addr % priv->page_size) != 0)
10834 +               return -EINVAL;
10835 +
10836 +       command = kmalloc(4, GFP_KERNEL);
10837 +       if (!command)
10838 +               return -ENOMEM;
10839 +
10840 +       while (instr->len > 0) {
10841 +               /* Calculate flash page address */
10842 +               pageaddr = (instr->addr / priv->page_size) << priv->page_offset;
10843 +
10844 +               command[0] = OP_ERASE_PAGE;
10845 +               command[1] = (pageaddr & 0x00FF0000) >> 16;
10846 +               command[2] = (pageaddr & 0x0000FF00) >> 8;
10847 +               command[3] = 0;
10848 +#ifdef DEBUG_DATAFLASH
10849 +               printk("ERASE: (%x) %x %x %x [%i]\n", command[0], command[1], command[2], command[3], pageaddr);
10850 +#endif
10851 +
10852 +               /* Send command to SPI device */
10853 +               spi_access_bus(priv->spi);
10854 +               do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
10855 +
10856 +               at91_dataflash_waitready();             /* poll status until ready */
10857 +               spi_release_bus(priv->spi);
10858 +
10859 +               instr->addr += priv->page_size;         /* next page */
10860 +               instr->len -= priv->page_size;
10861 +       }
10862 +
10863 +       kfree(command);
10864 +
10865 +       /* Inform MTD subsystem that erase is complete */
10866 +       instr->state = MTD_ERASE_DONE;
10867 +       if (instr->callback)
10868 +               instr->callback(instr);
10869 +
10870 +       return 0;
10871 +}
10872 +
10873 +/*
10874 + * Read from the DataFlash device.
10875 + *   from   : Start offset in flash device
10876 + *   len    : Amount to read
10877 + *   retlen : About of data actually read
10878 + *   buf    : Buffer containing the data
10879 + */
10880 +static int at91_dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
10881 +{
10882 +       struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
10883 +       unsigned int addr;
10884 +       char* command;
10885 +
10886 +#ifdef DEBUG_DATAFLASH
10887 +       printk("dataflash_read: %lli .. %lli\n", from, from+len);
10888 +#endif
10889 +
10890 +       *retlen = 0;
10891 +
10892 +       /* Sanity checks */
10893 +       if (!len)
10894 +               return 0;
10895 +       if (from + len > mtd->size)
10896 +               return -EINVAL;
10897 +
10898 +       /* Calculate flash page/byte address */
10899 +       addr = (((unsigned)from / priv->page_size) << priv->page_offset) + ((unsigned)from % priv->page_size);
10900 +
10901 +       command = kmalloc(8, GFP_KERNEL);
10902 +       if (!command)
10903 +               return -ENOMEM;
10904 +
10905 +       command[0] = OP_READ_CONTINUOUS;
10906 +       command[1] = (addr & 0x00FF0000) >> 16;
10907 +       command[2] = (addr & 0x0000FF00) >> 8;
10908 +       command[3] = (addr & 0x000000FF);
10909 +#ifdef DEBUG_DATAFLASH
10910 +       printk("READ: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
10911 +#endif
10912 +
10913 +       /* Send command to SPI device */
10914 +       spi_access_bus(priv->spi);
10915 +       do_spi_transfer(2, command, 8, command, 8, buf, len, buf, len);
10916 +       spi_release_bus(priv->spi);
10917 +
10918 +       *retlen = len;
10919 +       kfree(command);
10920 +       return 0;
10921 +}
10922 +
10923 +/*
10924 + * Write to the DataFlash device.
10925 + *   to     : Start offset in flash device
10926 + *   len    : Amount to write
10927 + *   retlen : Amount of data actually written
10928 + *   buf    : Buffer containing the data
10929 + */
10930 +static int at91_dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf)
10931 +{
10932 +       struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
10933 +       unsigned int pageaddr, addr, offset, writelen;
10934 +       size_t remaining;
10935 +       u_char *writebuf;
10936 +       unsigned short status;
10937 +       int res = 0;
10938 +       char* command;
10939 +       char* tmpbuf = NULL;
10940 +
10941 +#ifdef DEBUG_DATAFLASH
10942 +       printk("dataflash_write: %lli .. %lli\n", to, to+len);
10943 +#endif
10944 +
10945 +       *retlen = 0;
10946 +
10947 +       /* Sanity checks */
10948 +       if (!len)
10949 +               return 0;
10950 +       if (to + len > mtd->size)
10951 +               return -EINVAL;
10952 +
10953 +       command = kmalloc(4, GFP_KERNEL);
10954 +       if (!command)
10955 +               return -ENOMEM;
10956 +
10957 +       pageaddr = ((unsigned)to / priv->page_size);
10958 +       offset = ((unsigned)to % priv->page_size);
10959 +       if (offset + len > priv->page_size)
10960 +               writelen = priv->page_size - offset;
10961 +       else
10962 +               writelen = len;
10963 +       writebuf = (u_char *)buf;
10964 +       remaining = len;
10965 +
10966 +       /* Allocate temporary buffer */
10967 +       tmpbuf = kmalloc(priv->page_size, GFP_KERNEL);
10968 +       if (!tmpbuf) {
10969 +               kfree(command);
10970 +               return -ENOMEM;
10971 +       }
10972 +
10973 +       /* Gain access to the SPI bus */
10974 +       spi_access_bus(priv->spi);
10975 +
10976 +       while (remaining > 0) {
10977 +#ifdef DEBUG_DATAFLASH
10978 +               printk("write @ %i:%i len=%i\n", pageaddr, offset, writelen);
10979 +#endif
10980 +
10981 +               /* (1) Transfer to Buffer1 */
10982 +               if (writelen != priv->page_size) {
10983 +                       addr = pageaddr << priv->page_offset;
10984 +                       command[0] = OP_TRANSFER_BUF1;
10985 +                       command[1] = (addr & 0x00FF0000) >> 16;
10986 +                       command[2] = (addr & 0x0000FF00) >> 8;
10987 +                       command[3] = 0;
10988 +#ifdef DEBUG_DATAFLASH
10989 +                       printk("TRANSFER: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
10990 +#endif
10991 +                       do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
10992 +                       at91_dataflash_waitready();
10993 +               }
10994 +
10995 +               /* (2) Program via Buffer1 */
10996 +               addr = (pageaddr << priv->page_offset) + offset;
10997 +               command[0] = OP_PROGRAM_VIA_BUF1;
10998 +               command[1] = (addr & 0x00FF0000) >> 16;
10999 +               command[2] = (addr & 0x0000FF00) >> 8;
11000 +               command[3] = (addr & 0x000000FF);
11001 +#ifdef DEBUG_DATAFLASH
11002 +               printk("PROGRAM: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
11003 +#endif
11004 +               do_spi_transfer(2, command, 4, command, 4, writebuf, writelen, tmpbuf, writelen);
11005 +               at91_dataflash_waitready();
11006 +
11007 +               /* (3) Compare to Buffer1 */
11008 +               addr = pageaddr << priv->page_offset;
11009 +               command[0] = OP_COMPARE_BUF1;
11010 +               command[1] = (addr & 0x00FF0000) >> 16;
11011 +               command[2] = (addr & 0x0000FF00) >> 8;
11012 +               command[3] = 0;
11013 +#ifdef DEBUG_DATAFLASH
11014 +               printk("COMPARE: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
11015 +#endif
11016 +               do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
11017 +               at91_dataflash_waitready();
11018 +
11019 +               /* Get result of the compare operation */
11020 +               status = at91_dataflash_status();
11021 +               if ((status & 0x40) == 1) {
11022 +                       printk("at91_dataflash: Write error on page %i\n", pageaddr);
11023 +                       remaining = 0;
11024 +                       res = -EIO;
11025 +               }
11026 +
11027 +               remaining = remaining - writelen;
11028 +               pageaddr++;
11029 +               offset = 0;
11030 +               writebuf += writelen;
11031 +               *retlen += writelen;
11032 +
11033 +               if (remaining > priv->page_size)
11034 +                       writelen = priv->page_size;
11035 +               else
11036 +                       writelen = remaining;
11037 +       }
11038 +
11039 +       /* Release SPI bus */
11040 +       spi_release_bus(priv->spi);
11041 +
11042 +       kfree(tmpbuf);
11043 +       kfree(command);
11044 +       return res;
11045 +}
11046 +
11047 +/* ......................................................................... */
11048 +
11049 +/*
11050 + * Initialize and register DataFlash device with MTD subsystem.
11051 + */
11052 +static int __init add_dataflash(int channel, char *name, int IDsize,
11053 +               int nr_pages, int pagesize, int pageoffset)
11054 +{
11055 +       struct mtd_info *device;
11056 +       struct dataflash_local *priv;
11057 +#ifdef CONFIG_MTD_PARTITIONS
11058 +       struct mtd_partition *mtd_parts = 0;
11059 +       int mtd_parts_nr = 0;
11060 +#endif
11061 +
11062 +       if (nr_devices >= DATAFLASH_MAX_DEVICES) {
11063 +               printk(KERN_ERR "at91_dataflash: Too many devices detected\n");
11064 +               return 0;
11065 +       }
11066 +
11067 +       device = kmalloc(sizeof(struct mtd_info) + strlen(name) + 8, GFP_KERNEL);
11068 +       if (!device)
11069 +               return -ENOMEM;
11070 +       memset(device, 0, sizeof(struct mtd_info));
11071 +
11072 +       device->name = (char *)&device[1];
11073 +       sprintf(device->name, "%s.spi%d", name, channel);
11074 +       device->size = nr_pages * pagesize;
11075 +       device->erasesize = pagesize;
11076 +       device->writesize = pagesize;
11077 +       device->owner = THIS_MODULE;
11078 +       device->type = MTD_DATAFLASH;
11079 +       device->flags = MTD_WRITEABLE;
11080 +       device->erase = at91_dataflash_erase;
11081 +       device->read = at91_dataflash_read;
11082 +       device->write = at91_dataflash_write;
11083 +
11084 +       priv = (struct dataflash_local *) kmalloc(sizeof(struct dataflash_local), GFP_KERNEL);
11085 +       if (!priv) {
11086 +               kfree(device);
11087 +               return -ENOMEM;
11088 +       }
11089 +       memset(priv, 0, sizeof(struct dataflash_local));
11090 +
11091 +       priv->spi = channel;
11092 +       priv->page_size = pagesize;
11093 +       priv->page_offset = pageoffset;
11094 +       device->priv = priv;
11095 +
11096 +       mtd_devices[nr_devices] = device;
11097 +       nr_devices++;
11098 +       printk("at91_dataflash: %s detected [spi%i] (%i bytes)\n", name, channel, device->size);
11099 +
11100 +#ifdef CONFIG_MTD_PARTITIONS
11101 +#ifdef CONFIG_MTD_CMDLINE_PARTS
11102 +       mtd_parts_nr = parse_mtd_partitions(device, part_probes, &mtd_parts, 0);
11103 +#endif
11104 +       if (mtd_parts_nr <= 0) {
11105 +               switch (IDsize) {
11106 +                       case SZ_2M:
11107 +                               mtd_parts = static_partitions_2M;
11108 +                               mtd_parts_nr = ARRAY_SIZE(static_partitions_2M);
11109 +                               break;
11110 +                       case SZ_4M:
11111 +                               mtd_parts = static_partitions_4M;
11112 +                               mtd_parts_nr = ARRAY_SIZE(static_partitions_4M);
11113 +                               break;
11114 +                       case SZ_8M:
11115 +                               mtd_parts = static_partitions_8M;
11116 +                               mtd_parts_nr = ARRAY_SIZE(static_partitions_8M);
11117 +                               break;
11118 +               }
11119 +       }
11120 +
11121 +       if (mtd_parts_nr > 0) {
11122 +#ifdef DATAFLASH_ALWAYS_ADD_DEVICE
11123 +               add_mtd_device(device);
11124 +#endif
11125 +               return add_mtd_partitions(device, mtd_parts, mtd_parts_nr);
11126 +       }
11127 +#endif
11128 +       return add_mtd_device(device);          /* add whole device */
11129 +}
11130 +
11131 +/*
11132 + * Detect and initialize DataFlash device connected to specified SPI channel.
11133 + *
11134 + *   Device            Density         ID code                 Nr Pages        Page Size       Page offset
11135 + *   AT45DB011B        1Mbit   (128K)  xx0011xx (0x0c)         512             264             9
11136 + *   AT45DB021B        2Mbit   (256K)  xx0101xx (0x14)         1025            264             9
11137 + *   AT45DB041B        4Mbit   (512K)  xx0111xx (0x1c)         2048            264             9
11138 + *   AT45DB081B        8Mbit   (1M)    xx1001xx (0x24)         4096            264             9
11139 + *   AT45DB0161B       16Mbit  (2M)    xx1011xx (0x2c)         4096            528             10
11140 + *   AT45DB0321B       32Mbit  (4M)    xx1101xx (0x34)         8192            528             10
11141 + *   AT45DB0642        64Mbit  (8M)    xx1111xx (0x3c)         8192            1056            11
11142 + *   AT45DB1282        128Mbit (16M)   xx0100xx (0x10)         16384           1056            11
11143 + */
11144 +static int __init at91_dataflash_detect(int channel)
11145 +{
11146 +       int res = 0;
11147 +       unsigned short status;
11148 +
11149 +       spi_access_bus(channel);
11150 +       status = at91_dataflash_status();
11151 +       spi_release_bus(channel);
11152 +       if (status != 0xff) {                   /* no dataflash device there */
11153 +               switch (status & 0x3c) {
11154 +                       case 0x0c:      /* 0 0 1 1 */
11155 +                               res = add_dataflash(channel, "AT45DB011B", SZ_128K, 512, 264, 9);
11156 +                               break;
11157 +                       case 0x14:      /* 0 1 0 1 */
11158 +                               res = add_dataflash(channel, "AT45DB021B", SZ_256K, 1025, 264, 9);
11159 +                               break;
11160 +                       case 0x1c:      /* 0 1 1 1 */
11161 +                               res = add_dataflash(channel, "AT45DB041B", SZ_512K, 2048, 264, 9);
11162 +                               break;
11163 +                       case 0x24:      /* 1 0 0 1 */
11164 +                               res = add_dataflash(channel, "AT45DB081B", SZ_1M, 4096, 264, 9);
11165 +                               break;
11166 +                       case 0x2c:      /* 1 0 1 1 */
11167 +                               res = add_dataflash(channel, "AT45DB161B", SZ_2M, 4096, 528, 10);
11168 +                               break;
11169 +                       case 0x34:      /* 1 1 0 1 */
11170 +                               res = add_dataflash(channel, "AT45DB321B", SZ_4M, 8192, 528, 10);
11171 +                               break;
11172 +                       case 0x3c:      /* 1 1 1 1 */
11173 +                               res = add_dataflash(channel, "AT45DB642", SZ_8M, 8192, 1056, 11);
11174 +                               break;
11175 +// Currently unsupported since Atmel removed the "Main Memory Program via Buffer" commands.
11176 +//                     case 0x10:      /* 0 1 0 0 */
11177 +//                             res = add_dataflash(channel, "AT45DB1282", SZ_16M, 16384, 1056, 11);
11178 +//                             break;
11179 +                       default:
11180 +                               printk(KERN_ERR "at91_dataflash: Unknown device (%x)\n", status & 0x3c);
11181 +               }
11182 +       }
11183 +
11184 +       return res;
11185 +}
11186 +
11187 +static int __init at91_dataflash_init(void)
11188 +{
11189 +       spi_transfer_desc = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL);
11190 +       if (!spi_transfer_desc)
11191 +               return -ENOMEM;
11192 +
11193 +       /* DataFlash (SPI chip select 0) */
11194 +       at91_dataflash_detect(0);
11195 +
11196 +#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
11197 +       /* DataFlash card (SPI chip select 3) */
11198 +       at91_dataflash_detect(3);
11199 +#endif
11200 +
11201 +       return 0;
11202 +}
11203 +
11204 +static void __exit at91_dataflash_exit(void)
11205 +{
11206 +       int i;
11207 +
11208 +       for (i = 0; i < DATAFLASH_MAX_DEVICES; i++) {
11209 +               if (mtd_devices[i]) {
11210 +#ifdef CONFIG_MTD_PARTITIONS
11211 +                       del_mtd_partitions(mtd_devices[i]);
11212 +#else
11213 +                       del_mtd_device(mtd_devices[i]);
11214 +#endif
11215 +                       kfree(mtd_devices[i]->priv);
11216 +                       kfree(mtd_devices[i]);
11217 +               }
11218 +       }
11219 +       nr_devices = 0;
11220 +       kfree(spi_transfer_desc);
11221 +}
11222 +
11223 +
11224 +module_init(at91_dataflash_init);
11225 +module_exit(at91_dataflash_exit);
11226 +
11227 +MODULE_LICENSE("GPL");
11228 +MODULE_AUTHOR("Andrew Victor");
11229 +MODULE_DESCRIPTION("DataFlash driver for Atmel AT91RM9200");
11230 diff -urN -x CVS linux-2.6.19-final/drivers/mtd/devices/mtd_dataflash.c linux-2.6.19/drivers/mtd/devices/mtd_dataflash.c
11231 --- linux-2.6.19-final/drivers/mtd/devices/mtd_dataflash.c      Mon Dec  4 16:33:42 2006
11232 +++ linux-2.6.19/drivers/mtd/devices/mtd_dataflash.c    Mon Dec  4 16:12:32 2006
11233 @@ -480,7 +480,7 @@
11234         device->writesize = pagesize;
11235         device->owner = THIS_MODULE;
11236         device->type = MTD_DATAFLASH;
11237 -       device->flags = MTD_CAP_NORFLASH;
11238 +       device->flags = MTD_WRITEABLE;
11239         device->erase = dataflash_erase;
11240         device->read = dataflash_read;
11241         device->write = dataflash_write;
11242 diff -urN -x CVS linux-2.6.19-final/drivers/mtd/maps/Kconfig linux-2.6.19/drivers/mtd/maps/Kconfig
11243 --- linux-2.6.19-final/drivers/mtd/maps/Kconfig Mon Dec  4 16:40:13 2006
11244 +++ linux-2.6.19/drivers/mtd/maps/Kconfig       Mon Nov 20 10:49:27 2006
11245 @@ -622,5 +622,25 @@
11246
11247           This selection automatically selects the map_ram driver.
11248
11249 +config MTD_CSB337
11250 +       bool "Flash mapped on Cogent CSB337"
11251 +       depends on MTD && MACH_CSB337
11252 +       help
11253 +         This enables access to the flash chip on the Cogent CSB337
11254 +         single board computer.  The default behavior of the startup
11255 +         script the comes with BSPs for that board is to pass the address
11256 +         of a file romfs.img, which is assumed to be a romfs filesystem image
11257 +         to be used as the initial root filesystem.
11258 +
11259 +config MTD_CSB637
11260 +       bool "Flash mapped on Cogent CSB637"
11261 +       depends on MTD && MACH_CSB637
11262 +       help
11263 +         This enables access to the flash chip on the Cogent CSB637
11264 +         single board computer.  The default behavior of the startup
11265 +         script the comes with BSPs for that board is to pass the address
11266 +         of a file romfs.img, which is assumed to be a romfs filesystem image
11267 +         to be used as the initial root filesystem.
11268 +
11269  endmenu
11270
11271 diff -urN -x CVS linux-2.6.19-final/drivers/mtd/maps/Makefile linux-2.6.19/drivers/mtd/maps/Makefile
11272 --- linux-2.6.19-final/drivers/mtd/maps/Makefile        Mon Dec  4 16:40:13 2006
11273 +++ linux-2.6.19/drivers/mtd/maps/Makefile      Mon Nov 20 10:49:37 2006
11274 @@ -70,3 +70,5 @@
11275  obj-$(CONFIG_MTD_OMAP_NOR)     += omap_nor.o
11276  obj-$(CONFIG_MTD_MTX1)         += mtx-1_flash.o
11277  obj-$(CONFIG_MTD_TQM834x)      += tqm834x.o
11278 +obj-$(CONFIG_MTD_CSB337)       += csbxxx.o
11279 +obj-$(CONFIG_MTD_CSB637)       += csbxxx.o
11280 diff -urN -x CVS linux-2.6.19-final/drivers/mtd/maps/csbxxx.c linux-2.6.19/drivers/mtd/maps/csbxxx.c
11281 --- linux-2.6.19-final/drivers/mtd/maps/csbxxx.c        Thu Jan  1 02:00:00 1970
11282 +++ linux-2.6.19/drivers/mtd/maps/csbxxx.c      Tue Oct 24 08:53:30 2006
11283 @@ -0,0 +1,143 @@
11284 +/*
11285 + * Map driver for the Cogent CSBxxx boards.
11286 + *
11287 + * Author:     Bill Gatliff
11288 + * Copyright:  (C) 2005 Bill Gatliff <bgat@billgatliff.com>
11289 + *
11290 + * This program is free software; you can redistribute it and/or modify
11291 + * it under the terms of the GNU General Public License version 2 as
11292 + * published by the Free Software Foundation.
11293 + */
11294 +
11295 +#include <linux/module.h>
11296 +#include <linux/types.h>
11297 +#include <linux/kernel.h>
11298 +#include <linux/init.h>
11299 +#include <linux/dma-mapping.h>
11300 +#include <linux/mtd/mtd.h>
11301 +#include <linux/mtd/map.h>
11302 +#include <linux/mtd/partitions.h>
11303 +#include <asm/io.h>
11304 +#include <asm/hardware.h>
11305 +
11306 +#define MTDID "flash00"
11307 +#define MSG_PREFIX "csbxxx: "
11308 +
11309 +#if defined(CONFIG_MACH_CSB337) || defined(CONFIG_MACH_CSB637)
11310 +#define WINDOW_ADDR 0x10000000
11311 +#define WINDOW_SIZE 0x1000000
11312 +#else
11313 +#error TODO: the MTD map you need goes here...
11314 +#endif
11315 +
11316 +/*
11317 + * default map definition
11318 + * (generally overridden on the command line)
11319 + */
11320 +static struct mtd_partition csbxxx_partitions[] = {
11321 +       {
11322 +               .name           = "uMON flash",
11323 +               .size           = WINDOW_SIZE,
11324 +               .mask_flags     = MTD_WRITEABLE         /* force read-only */
11325 +       },
11326 +};
11327 +
11328 +static void csbxxx_map_inval_cache(struct map_info *map, unsigned long from, ssize_t len)
11329 +{
11330 +       consistent_sync((char *)map->cached + from, len, DMA_FROM_DEVICE);
11331 +}
11332 +static struct map_info csbxxx_map = {
11333 +       .size           = WINDOW_SIZE,
11334 +       .phys           = WINDOW_ADDR,
11335 +       .inval_cache    = csbxxx_map_inval_cache,
11336 +       .bankwidth      = 2,
11337 +       .name           = MTDID,
11338 +};
11339 +
11340 +static const char *probes[] = { "cmdlinepart", NULL };
11341 +
11342 +static struct mtd_info *mymtd = 0;
11343 +static int mtd_parts_nb = 0;
11344 +static struct mtd_partition *mtd_parts = 0;
11345 +
11346 +static int __init init_csbxxx(void)
11347 +{
11348 +       int ret = 0;
11349 +       const char *part_type = 0;
11350 +
11351 +       csbxxx_map.virt = ioremap(csbxxx_map.phys, WINDOW_SIZE);
11352 +       if (!csbxxx_map.virt) {
11353 +               printk(KERN_WARNING "Failed to ioremap %s, MTD disabled\n", csbxxx_map.name);
11354 +               ret = -ENOMEM;
11355 +               goto err;
11356 +       }
11357 +       csbxxx_map.cached = ioremap_cached(csbxxx_map.phys, WINDOW_SIZE);
11358 +       if (!csbxxx_map.cached)
11359 +               printk(KERN_WARNING "Failed to ioremap cached %s\n", csbxxx_map.name);
11360 +
11361 +       simple_map_init(&csbxxx_map);
11362 +
11363 +       printk(KERN_NOTICE "Probing %s at physical address 0x%08lx (%d-bit bankwidth)\n",
11364 +                       csbxxx_map.name, csbxxx_map.phys, csbxxx_map.bankwidth * 8);
11365 +
11366 +       mymtd = do_map_probe("cfi_probe", &csbxxx_map);
11367 +       if (!mymtd)
11368 +               goto err;
11369 +
11370 +       mymtd->owner = THIS_MODULE;
11371 +
11372 +       mtd_parts_nb = parse_mtd_partitions(mymtd, probes, &mtd_parts, 0);
11373 +
11374 +#ifdef CONFIG_MTD_PARTITIONS
11375 +       if (mtd_parts_nb > 0)
11376 +               part_type = "command line";
11377 +       else if (mtd_parts_nb == 0) {
11378 +               mtd_parts = csbxxx_partitions;
11379 +               mtd_parts_nb = ARRAY_SIZE(csbxxx_partitions);
11380 +               part_type = "static";
11381 +       }
11382 +       else
11383 +               goto err;
11384 +
11385 +       if (mtd_parts_nb == 0)
11386 +               printk(KERN_NOTICE MSG_PREFIX "no partition info available\n");
11387 +       else {
11388 +               printk(KERN_NOTICE MSG_PREFIX "using %s partition definition\n", part_type);
11389 +               add_mtd_partitions(mymtd, mtd_parts, mtd_parts_nb);
11390 +       }
11391 +#else
11392 +       add_mtd_device(mymtd);
11393 +#endif
11394 +
11395 +       return 0;
11396 +
11397 +err:
11398 +       if (csbxxx_map.virt)
11399 +               iounmap(csbxxx_map.virt);
11400 +       if (csbxxx_map.cached)
11401 +               iounmap(csbxxx_map.cached);
11402 +       if (!ret)
11403 +               ret = -EIO;
11404 +
11405 +       return ret;
11406 +}
11407 +
11408 +static void __exit cleanup_csbxxx(void)
11409 +{
11410 +       if (!mymtd)
11411 +               return;
11412 +
11413 +       del_mtd_partitions(mymtd);
11414 +
11415 +       map_destroy(mymtd);
11416 +       iounmap((void *)csbxxx_map.virt);
11417 +       if (csbxxx_map.cached)
11418 +               iounmap(csbxxx_map.cached);
11419 +}
11420 +
11421 +module_init(init_csbxxx);
11422 +module_exit(cleanup_csbxxx);
11423 +
11424 +MODULE_LICENSE("GPL");
11425 +MODULE_AUTHOR("Bill Gatliff <bgat@billgatliff.com>");
11426 +MODULE_DESCRIPTION("MTD map driver for Cogent CSBXXX");
11427 diff -urN -x CVS linux-2.6.19-final/drivers/mtd/nand/Kconfig linux-2.6.19/drivers/mtd/nand/Kconfig
11428 --- linux-2.6.19-final/drivers/mtd/nand/Kconfig Mon Dec  4 16:40:13 2006
11429 +++ linux-2.6.19/drivers/mtd/nand/Kconfig       Thu Oct 12 17:07:39 2006
11430 @@ -232,6 +232,13 @@
11431
11432           If you say "m", the module will be called "cs553x_nand.ko".
11433
11434 +config MTD_NAND_AT91
11435 +       bool "Support for NAND Flash / SmartMedia on AT91"
11436 +       depends on MTD_NAND && ARCH_AT91
11437 +       help
11438 +         Enables support for NAND Flash / Smart Media Card interface
11439 +         on Atmel AT91 processors.
11440 +
11441  config MTD_NAND_NANDSIM
11442         tristate "Support for NAND Flash Simulator"
11443         depends on MTD_NAND && MTD_PARTITIONS
11444 diff -urN -x CVS linux-2.6.19-final/drivers/mtd/nand/Makefile linux-2.6.19/drivers/mtd/nand/Makefile
11445 --- linux-2.6.19-final/drivers/mtd/nand/Makefile        Mon Dec  4 16:33:43 2006
11446 +++ linux-2.6.19/drivers/mtd/nand/Makefile      Thu Oct 12 17:07:39 2006
11447 @@ -22,5 +22,6 @@
11448  obj-$(CONFIG_MTD_NAND_NANDSIM)         += nandsim.o
11449  obj-$(CONFIG_MTD_NAND_CS553X)          += cs553x_nand.o
11450  obj-$(CONFIG_MTD_NAND_NDFC)            += ndfc.o
11451 +obj-$(CONFIG_MTD_NAND_AT91)            += at91_nand.o
11452
11453  nand-objs = nand_base.o nand_bbt.o
11454 diff -urN -x CVS linux-2.6.19-final/drivers/mtd/nand/at91_nand.c linux-2.6.19/drivers/mtd/nand/at91_nand.c
11455 --- linux-2.6.19-final/drivers/mtd/nand/at91_nand.c     Thu Jan  1 02:00:00 1970
11456 +++ linux-2.6.19/drivers/mtd/nand/at91_nand.c   Wed Nov 15 08:12:22 2006
11457 @@ -0,0 +1,223 @@
11458 +/*
11459 + * drivers/mtd/nand/at91_nand.c
11460 + *
11461 + *  Copyright (C) 2003 Rick Bronson
11462 + *
11463 + *  Derived from drivers/mtd/nand/autcpu12.c
11464 + *      Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
11465 + *
11466 + *  Derived from drivers/mtd/spia.c
11467 + *      Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
11468 + *
11469 + * This program is free software; you can redistribute it and/or modify
11470 + * it under the terms of the GNU General Public License version 2 as
11471 + * published by the Free Software Foundation.
11472 + *
11473 + */
11474 +
11475 +#include <linux/slab.h>
11476 +#include <linux/module.h>
11477 +#include <linux/platform_device.h>
11478 +#include <linux/mtd/mtd.h>
11479 +#include <linux/mtd/nand.h>
11480 +#include <linux/mtd/partitions.h>
11481 +
11482 +#include <asm/io.h>
11483 +#include <asm/sizes.h>
11484 +
11485 +#include <asm/hardware.h>
11486 +#include <asm/arch/board.h>
11487 +#include <asm/arch/gpio.h>
11488 +
11489 +struct at91_nand_host {
11490 +       struct nand_chip        nand_chip;
11491 +       struct mtd_info         mtd;
11492 +       void __iomem            *io_base;
11493 +       struct at91_nand_data   *board;
11494 +};
11495 +
11496 +/*
11497 + * Hardware specific access to control-lines
11498 + */
11499 +static void at91_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
11500 +{
11501 +       struct nand_chip *nand_chip = mtd->priv;
11502 +       struct at91_nand_host *host = nand_chip->priv;
11503 +
11504 +       if (cmd == NAND_CMD_NONE)
11505 +               return;
11506 +
11507 +       if (ctrl & NAND_CLE)
11508 +               writeb(cmd, host->io_base + (1 << host->board->cle));
11509 +       else
11510 +               writeb(cmd, host->io_base + (1 << host->board->ale));
11511 +}
11512 +
11513 +/*
11514 + * Read the Device Ready pin.
11515 + */
11516 +static int at91_nand_device_ready(struct mtd_info *mtd)
11517 +{
11518 +       struct nand_chip *nand_chip = mtd->priv;
11519 +       struct at91_nand_host *host = nand_chip->priv;
11520 +
11521 +       return at91_get_gpio_value(host->board->rdy_pin);
11522 +}
11523 +
11524 +/*
11525 + * Enable NAND.
11526 + */
11527 +static void at91_nand_enable(struct at91_nand_host *host)
11528 +{
11529 +       if (host->board->enable_pin)
11530 +               at91_set_gpio_value(host->board->enable_pin, 0);
11531 +}
11532 +
11533 +/*
11534 + * Disable NAND.
11535 + */
11536 +static void at91_nand_disable(struct at91_nand_host *host)
11537 +{
11538 +       if (host->board->enable_pin)
11539 +               at91_set_gpio_value(host->board->enable_pin, 1);
11540 +}
11541 +
11542 +/*
11543 + * Probe for the NAND device.
11544 + */
11545 +static int __init at91_nand_probe(struct platform_device *pdev)
11546 +{
11547 +       struct at91_nand_host *host;
11548 +       struct mtd_info *mtd;
11549 +       struct nand_chip *nand_chip;
11550 +       int res;
11551 +
11552 +#ifdef CONFIG_MTD_PARTITIONS
11553 +       struct mtd_partition *partitions = NULL;
11554 +       int num_partitions = 0;
11555 +#endif
11556 +
11557 +       /* Allocate memory for the device structure (and zero it) */
11558 +       host = kzalloc(sizeof(struct at91_nand_host), GFP_KERNEL);
11559 +       if (!host) {
11560 +               printk(KERN_ERR "at91_nand: failed to allocate device structure.\n");
11561 +               return -ENOMEM;
11562 +       }
11563 +
11564 +       host->io_base = ioremap(pdev->resource[0].start,
11565 +                               pdev->resource[0].end - pdev->resource[0].start + 1);
11566 +       if (host->io_base == NULL) {
11567 +               printk(KERN_ERR "at91_nand: ioremap failed\n");
11568 +               kfree(host);
11569 +               return -EIO;
11570 +       }
11571 +
11572 +       mtd = &host->mtd;
11573 +       nand_chip = &host->nand_chip;
11574 +       host->board = pdev->dev.platform_data;
11575 +
11576 +       nand_chip->priv = host;         /* link the private data structures */
11577 +       mtd->priv = nand_chip;
11578 +       mtd->owner = THIS_MODULE;
11579 +
11580 +       /* Set address of NAND IO lines */
11581 +       nand_chip->IO_ADDR_R = host->io_base;
11582 +       nand_chip->IO_ADDR_W = host->io_base;
11583 +       nand_chip->cmd_ctrl = at91_nand_cmd_ctrl;
11584 +       nand_chip->dev_ready = at91_nand_device_ready;
11585 +       nand_chip->ecc.mode = NAND_ECC_SOFT;    /* enable ECC */
11586 +       nand_chip->chip_delay = 20;             /* 20us command delay time */
11587 +
11588 +       if (host->board->bus_width_16)          /* 16-bit bus width */
11589 +               nand_chip->options |= NAND_BUSWIDTH_16;
11590 +
11591 +       platform_set_drvdata(pdev, host);
11592 +       at91_nand_enable(host);
11593 +
11594 +       if (host->board->det_pin) {
11595 +               if (at91_get_gpio_value(host->board->det_pin)) {
11596 +                       printk ("No SmartMedia card inserted.\n");
11597 +                       res = ENXIO;
11598 +                       goto out;
11599 +               }
11600 +       }
11601 +
11602 +       /* Scan to find existance of the device */
11603 +       if (nand_scan(mtd, 1)) {
11604 +               res = -ENXIO;
11605 +               goto out;
11606 +       }
11607 +
11608 +#ifdef CONFIG_MTD_PARTITIONS
11609 +       if (host->board->partition_info)
11610 +               partitions = host->board->partition_info(mtd->size, &num_partitions);
11611 +
11612 +       if ((!partitions) || (num_partitions == 0)) {
11613 +               printk(KERN_ERR "at91_nand: No parititions defined, or unsupported device.\n");
11614 +               res = ENXIO;
11615 +               goto release;
11616 +       }
11617 +
11618 +       res = add_mtd_partitions(mtd, partitions, num_partitions);
11619 +#else
11620 +       res = add_mtd_device(mtd);
11621 +#endif
11622 +
11623 +       if (!res)
11624 +               return res;
11625 +
11626 +release:
11627 +       nand_release(mtd);
11628 +out:
11629 +       at91_nand_disable(host);
11630 +       platform_set_drvdata(pdev, NULL);
11631 +       iounmap(host->io_base);
11632 +       kfree(host);
11633 +       return res;
11634 +}
11635 +
11636 +/*
11637 + * Remove a NAND device.
11638 + */
11639 +static int __devexit at91_nand_remove(struct platform_device *pdev)
11640 +{
11641 +       struct at91_nand_host *host = platform_get_drvdata(pdev);
11642 +       struct mtd_info *mtd = &host->mtd;
11643 +
11644 +       nand_release(mtd);
11645 +
11646 +       at91_nand_disable(host);
11647 +
11648 +       iounmap(host->io_base);
11649 +       kfree(host);
11650 +
11651 +       return 0;
11652 +}
11653 +
11654 +static struct platform_driver at91_nand_driver = {
11655 +       .probe          = at91_nand_probe,
11656 +       .remove         = at91_nand_remove,
11657 +       .driver         = {
11658 +               .name   = "at91_nand",
11659 +               .owner  = THIS_MODULE,
11660 +       },
11661 +};
11662 +
11663 +static int __init at91_nand_init(void)
11664 +{
11665 +       return platform_driver_register(&at91_nand_driver);
11666 +}
11667 +
11668 +
11669 +static void __exit at91_nand_exit(void)
11670 +{
11671 +       platform_driver_unregister(&at91_nand_driver);
11672 +}
11673 +
11674 +
11675 +module_init(at91_nand_init);
11676 +module_exit(at91_nand_exit);
11677 +
11678 +MODULE_LICENSE("GPL");
11679 +MODULE_AUTHOR("Rick Bronson");
11680 +MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91RM9200");
11681 diff -urN -x CVS linux-2.6.19-final/drivers/net/arm/at91_ether.c linux-2.6.19/drivers/net/arm/at91_ether.c
11682 --- linux-2.6.19-final/drivers/net/arm/at91_ether.c     Mon Dec  4 16:40:14 2006
11683 +++ linux-2.6.19/drivers/net/arm/at91_ether.c   Thu Nov 23 15:50:12 2006
11684 @@ -41,9 +41,6 @@
11685  #define DRV_NAME       "at91_ether"
11686  #define DRV_VERSION    "1.0"
11687
11688 -static struct net_device *at91_dev;
11689 -
11690 -static struct timer_list check_timer;
11691  #define LINK_POLL_INTERVAL     (HZ)
11692
11693  /* ..................................................................... */
11694 @@ -252,8 +249,8 @@
11695                  * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
11696                  * or board does not have it connected.
11697                  */
11698 -               check_timer.expires = jiffies + LINK_POLL_INTERVAL;
11699 -               add_timer(&check_timer);
11700 +               lp->check_timer.expires = jiffies + LINK_POLL_INTERVAL;
11701 +               add_timer(&lp->check_timer);
11702                 return;
11703         }
11704
11705 @@ -300,7 +297,7 @@
11706
11707         irq_number = lp->board_data.phy_irq_pin;
11708         if (!irq_number) {
11709 -               del_timer_sync(&check_timer);
11710 +               del_timer_sync(&lp->check_timer);
11711                 return;
11712         }
11713
11714 @@ -362,13 +359,14 @@
11715  static void at91ether_check_link(unsigned long dev_id)
11716  {
11717         struct net_device *dev = (struct net_device *) dev_id;
11718 +       struct at91_private *lp = (struct at91_private *) dev->priv;
11719
11720         enable_mdi();
11721         update_linkspeed(dev, 1);
11722         disable_mdi();
11723
11724 -       check_timer.expires = jiffies + LINK_POLL_INTERVAL;
11725 -       add_timer(&check_timer);
11726 +       lp->check_timer.expires = jiffies + LINK_POLL_INTERVAL;
11727 +       add_timer(&lp->check_timer);
11728  }
11729
11730  /* ......................... ADDRESS MANAGEMENT ........................ */
11731 @@ -857,14 +855,13 @@
11732         while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
11733                 p_recv = dlist->recv_buf[lp->rxBuffIndex];
11734                 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff;      /* Length of frame including FCS */
11735 -               skb = alloc_skb(pktlen + 2, GFP_ATOMIC);
11736 +               skb = dev_alloc_skb(pktlen + 2);
11737                 if (skb != NULL) {
11738                         skb_reserve(skb, 2);
11739                         memcpy(skb_put(skb, pktlen), p_recv, pktlen);
11740
11741                         skb->dev = dev;
11742                         skb->protocol = eth_type_trans(skb, dev);
11743 -                       skb->len = pktlen;
11744                         dev->last_rx = jiffies;
11745                         lp->stats.rx_bytes += pktlen;
11746                         netif_rx(skb);
11747 @@ -927,27 +924,43 @@
11748         return IRQ_HANDLED;
11749  }
11750
11751 +#ifdef CONFIG_NET_POLL_CONTROLLER
11752 +static void at91ether_poll_controller(struct net_device *dev)
11753 +{
11754 +       unsigned long flags;
11755 +
11756 +       local_irq_save(flags);
11757 +       at91ether_interrupt(dev->irq, dev, NULL);
11758 +       local_irq_restore(flags);
11759 +}
11760 +#endif
11761 +
11762  /*
11763   * Initialize the ethernet interface
11764   */
11765  static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address,
11766                         struct platform_device *pdev, struct clk *ether_clk)
11767  {
11768 -       struct at91_eth_data *board_data = pdev->dev.platform_data;
11769 +       struct eth_platform_data *board_data = pdev->dev.platform_data;
11770         struct net_device *dev;
11771         struct at91_private *lp;
11772         unsigned int val;
11773 -       int res;
11774 -
11775 -       if (at91_dev)                   /* already initialized */
11776 -               return 0;
11777 +       struct resource *res;
11778 +       int ret;
11779
11780         dev = alloc_etherdev(sizeof(struct at91_private));
11781         if (!dev)
11782                 return -ENOMEM;
11783
11784 -       dev->base_addr = AT91_VA_BASE_EMAC;
11785 -       dev->irq = AT91RM9200_ID_EMAC;
11786 +       /* Get I/O base address and IRQ */
11787 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
11788 +       if (!res) {
11789 +               free_netdev(dev);
11790 +               return -ENODEV;
11791 +       }
11792 +       dev->base_addr = res->start;
11793 +       dev->irq = platform_get_irq(pdev, 0);
11794 +
11795         SET_MODULE_OWNER(dev);
11796
11797         /* Install the interrupt handler */
11798 @@ -979,6 +992,9 @@
11799         dev->set_mac_address = set_mac_address;
11800         dev->ethtool_ops = &at91ether_ethtool_ops;
11801         dev->do_ioctl = at91ether_ioctl;
11802 +#ifdef CONFIG_NET_POLL_CONTROLLER
11803 +       dev->poll_controller = at91ether_poll_controller;
11804 +#endif
11805
11806         SET_NETDEV_DEV(dev, &pdev->dev);
11807
11808 @@ -1017,14 +1033,13 @@
11809         lp->phy_address = phy_address;  /* MDI address of PHY */
11810
11811         /* Register the network interface */
11812 -       res = register_netdev(dev);
11813 -       if (res) {
11814 +       ret = register_netdev(dev);
11815 +       if (ret) {
11816                 free_irq(dev->irq, dev);
11817                 free_netdev(dev);
11818                 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
11819 -               return res;
11820 +               return ret;
11821         }
11822 -       at91_dev = dev;
11823
11824         /* Determine current link speed */
11825         spin_lock_irq(&lp->lock);
11826 @@ -1036,9 +1051,9 @@
11827
11828         /* If board has no PHY IRQ, use a timer to poll the PHY */
11829         if (!lp->board_data.phy_irq_pin) {
11830 -               init_timer(&check_timer);
11831 -               check_timer.data = (unsigned long)dev;
11832 -               check_timer.function = at91ether_check_link;
11833 +               init_timer(&lp->check_timer);
11834 +               lp->check_timer.data = (unsigned long)dev;
11835 +               lp->check_timer.function = at91ether_check_link;
11836         }
11837
11838         /* Display ethernet banner */
11839 @@ -1115,15 +1130,16 @@
11840
11841  static int __devexit at91ether_remove(struct platform_device *pdev)
11842  {
11843 -       struct at91_private *lp = (struct at91_private *) at91_dev->priv;
11844 +       struct net_device *dev = platform_get_drvdata(pdev);
11845 +       struct at91_private *lp = (struct at91_private *) dev->priv;
11846
11847 -       unregister_netdev(at91_dev);
11848 -       free_irq(at91_dev->irq, at91_dev);
11849 +       unregister_netdev(dev);
11850 +       free_irq(dev->irq, dev);
11851         dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
11852         clk_put(lp->ether_clk);
11853
11854 -       free_netdev(at91_dev);
11855 -       at91_dev = NULL;
11856 +       platform_set_drvdata(pdev, NULL);
11857 +       free_netdev(dev);
11858         return 0;
11859  }
11860
11861 @@ -1131,8 +1147,8 @@
11862
11863  static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
11864  {
11865 -       struct at91_private *lp = (struct at91_private *) at91_dev->priv;
11866         struct net_device *net_dev = platform_get_drvdata(pdev);
11867 +       struct at91_private *lp = (struct at91_private *) net_dev->priv;
11868         int phy_irq = lp->board_data.phy_irq_pin;
11869
11870         if (netif_running(net_dev)) {
11871 @@ -1149,8 +1165,8 @@
11872
11873  static int at91ether_resume(struct platform_device *pdev)
11874  {
11875 -       struct at91_private *lp = (struct at91_private *) at91_dev->priv;
11876         struct net_device *net_dev = platform_get_drvdata(pdev);
11877 +       struct at91_private *lp = (struct at91_private *) net_dev->priv;
11878         int phy_irq = lp->board_data.phy_irq_pin;
11879
11880         if (netif_running(net_dev)) {
11881 diff -urN -x CVS linux-2.6.19-final/drivers/net/arm/at91_ether.h linux-2.6.19/drivers/net/arm/at91_ether.h
11882 --- linux-2.6.19-final/drivers/net/arm/at91_ether.h     Mon Dec  4 16:33:44 2006
11883 +++ linux-2.6.19/drivers/net/arm/at91_ether.h   Thu Nov 23 15:50:12 2006
11884 @@ -79,7 +79,7 @@
11885  {
11886         struct net_device_stats stats;
11887         struct mii_if_info mii;                 /* ethtool support */
11888 -       struct at91_eth_data board_data;        /* board-specific configuration */
11889 +       struct eth_platform_data board_data;    /* board-specific configuration */
11890         struct clk *ether_clk;                  /* clock */
11891
11892         /* PHY */
11893 @@ -87,6 +87,7 @@
11894         spinlock_t lock;                        /* lock for MDI interface */
11895         short phy_media;                        /* media interface type */
11896         unsigned short phy_address;             /* 5-bit MDI address of PHY (0..31) */
11897 +       struct timer_list check_timer;          /* Poll link status */
11898
11899         /* Transmit */
11900         struct sk_buff *skb;                    /* holds skb until xmit interrupt completes */
11901 diff -urN -x CVS linux-2.6.19-final/drivers/pcmcia/at91_cf.c linux-2.6.19/drivers/pcmcia/at91_cf.c
11902 --- linux-2.6.19-final/drivers/pcmcia/at91_cf.c Mon Dec  4 16:40:25 2006
11903 +++ linux-2.6.19/drivers/pcmcia/at91_cf.c       Thu Nov 16 17:27:11 2006
11904 @@ -23,19 +23,20 @@
11905  #include <asm/io.h>
11906  #include <asm/sizes.h>
11907
11908 -#include <asm/arch/at91rm9200.h>
11909  #include <asm/arch/board.h>
11910  #include <asm/arch/gpio.h>
11911 +#include <asm/arch/at91rm9200_mc.h>
11912
11913
11914  /*
11915   * A0..A10 work in each range; A23 indicates I/O space;  A25 is CFRNW;
11916   * some other bit in {A24,A22..A11} is nREG to flag memory access
11917   * (vs attributes).  So more than 2KB/region would just be waste.
11918 + * Note: These are offsets from the physical base address.
11919   */
11920 -#define        CF_ATTR_PHYS    (AT91_CF_BASE)
11921 -#define        CF_IO_PHYS      (AT91_CF_BASE  + (1 << 23))
11922 -#define        CF_MEM_PHYS     (AT91_CF_BASE  + 0x017ff800)
11923 +#define        CF_ATTR_PHYS    (0)
11924 +#define        CF_IO_PHYS      (1 << 23)
11925 +#define        CF_MEM_PHYS     (0x017ff800)
11926
11927  /*--------------------------------------------------------------------------*/
11928
11929 @@ -48,6 +49,8 @@
11930
11931         struct platform_device  *pdev;
11932         struct at91_cf_data     *board;
11933 +
11934 +       unsigned long           phys_baseaddr;
11935  };
11936
11937  #define        SZ_2K                   (2 * SZ_1K)
11938 @@ -154,9 +157,8 @@
11939
11940         /*
11941          * Use 16 bit accesses unless/until we need 8-bit i/o space.
11942 -        * Always set CSR4 ... PCMCIA won't always unmap things.
11943          */
11944 -       csr = at91_sys_read(AT91_SMC_CSR(4)) & ~AT91_SMC_DBW;
11945 +       csr = at91_sys_read(AT91_SMC_CSR(cf->board->chipselect)) & ~AT91_SMC_DBW;
11946
11947         /*
11948          * NOTE: this CF controller ignores IOIS16, so we can't really do
11949 @@ -168,14 +170,14 @@
11950          * some cards only like that way to get at the odd byte, despite
11951          * CF 3.0 spec table 35 also giving the D8-D15 option.
11952          */
11953 -       if (!(io->flags & (MAP_16BIT|MAP_AUTOSZ))) {
11954 +       if (!(io->flags & (MAP_16BIT | MAP_AUTOSZ))) {
11955                 csr |= AT91_SMC_DBW_8;
11956                 pr_debug("%s: 8bit i/o bus\n", driver_name);
11957         } else {
11958                 csr |= AT91_SMC_DBW_16;
11959                 pr_debug("%s: 16bit i/o bus\n", driver_name);
11960         }
11961 -       at91_sys_write(AT91_SMC_CSR(4), csr);
11962 +       at91_sys_write(AT91_SMC_CSR(cf->board->chipselect), csr);
11963
11964         io->start = cf->socket.io_offset;
11965         io->stop = io->start + SZ_2K - 1;
11966 @@ -194,11 +196,11 @@
11967
11968         cf = container_of(s, struct at91_cf_socket, socket);
11969
11970 -       map->flags &= MAP_ACTIVE|MAP_ATTRIB|MAP_16BIT;
11971 +       map->flags &= (MAP_ACTIVE | MAP_ATTRIB | MAP_16BIT);
11972         if (map->flags & MAP_ATTRIB)
11973 -               map->static_start = CF_ATTR_PHYS;
11974 +               map->static_start = cf->phys_baseaddr + CF_ATTR_PHYS;
11975         else
11976 -               map->static_start = CF_MEM_PHYS;
11977 +               map->static_start = cf->phys_baseaddr + CF_MEM_PHYS;
11978
11979         return 0;
11980  }
11981 @@ -219,7 +221,6 @@
11982         struct at91_cf_socket   *cf;
11983         struct at91_cf_data     *board = pdev->dev.platform_data;
11984         struct resource         *io;
11985 -       unsigned int            csa;
11986         int                     status;
11987
11988         if (!board || !board->det_pin || !board->rst_pin)
11989 @@ -235,33 +236,11 @@
11990
11991         cf->board = board;
11992         cf->pdev = pdev;
11993 +       cf->phys_baseaddr = io->start;
11994         platform_set_drvdata(pdev, cf);
11995
11996 -       /* CF takes over CS4, CS5, CS6 */
11997 -       csa = at91_sys_read(AT91_EBI_CSA);
11998 -       at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
11999 -
12000 -       /* nWAIT is _not_ a default setting */
12001 -       (void) at91_set_A_periph(AT91_PIN_PC6, 1);      /*  nWAIT */
12002 -
12003 -       /*
12004 -        * Static memory controller timing adjustments.
12005 -        * REVISIT:  these timings are in terms of MCK cycles, so
12006 -        * when MCK changes (cpufreq etc) so must these values...
12007 -        */
12008 -       at91_sys_write(AT91_SMC_CSR(4),
12009 -                                 AT91_SMC_ACSS_STD
12010 -                               | AT91_SMC_DBW_16
12011 -                               | AT91_SMC_BAT
12012 -                               | AT91_SMC_WSEN
12013 -                               | AT91_SMC_NWS_(32)     /* wait states */
12014 -                               | AT91_SMC_RWSETUP_(6)  /* setup time */
12015 -                               | AT91_SMC_RWHOLD_(4)   /* hold time */
12016 -       );
12017 -
12018         /* must be a GPIO; ergo must trigger on both edges */
12019 -       status = request_irq(board->det_pin, at91_cf_irq,
12020 -                       IRQF_SAMPLE_RANDOM, driver_name, cf);
12021 +       status = request_irq(board->det_pin, at91_cf_irq, 0, driver_name, cf);
12022         if (status < 0)
12023                 goto fail0;
12024         device_init_wakeup(&pdev->dev, 1);
12025 @@ -282,14 +261,18 @@
12026                 cf->socket.pci_irq = NR_IRQS + 1;
12027
12028         /* pcmcia layer only remaps "real" memory not iospace */
12029 -       cf->socket.io_offset = (unsigned long) ioremap(CF_IO_PHYS, SZ_2K);
12030 -       if (!cf->socket.io_offset)
12031 +       cf->socket.io_offset = (unsigned long) ioremap(cf->phys_baseaddr + CF_IO_PHYS, SZ_2K);
12032 +       if (!cf->socket.io_offset) {
12033 +               status = -ENXIO;
12034                 goto fail1;
12035 +       }
12036
12037 -       /* reserve CS4, CS5, and CS6 regions; but use just CS4 */
12038 +       /* reserve chip-select regions */
12039         if (!request_mem_region(io->start, io->end + 1 - io->start,
12040 -                               driver_name))
12041 +                               driver_name)) {
12042 +               status = -ENXIO;
12043                 goto fail1;
12044 +       }
12045
12046         pr_info("%s: irqs det #%d, io #%d\n", driver_name,
12047                 board->det_pin, board->irq_pin);
12048 @@ -319,9 +302,7 @@
12049  fail0a:
12050         device_init_wakeup(&pdev->dev, 0);
12051         free_irq(board->det_pin, cf);
12052 -       device_init_wakeup(&pdev->dev, 0);
12053  fail0:
12054 -       at91_sys_write(AT91_EBI_CSA, csa);
12055         kfree(cf);
12056         return status;
12057  }
12058 @@ -331,19 +312,15 @@
12059         struct at91_cf_socket   *cf = platform_get_drvdata(pdev);
12060         struct at91_cf_data     *board = cf->board;
12061         struct resource         *io = cf->socket.io[0].res;
12062 -       unsigned int            csa;
12063
12064         pcmcia_unregister_socket(&cf->socket);
12065         if (board->irq_pin)
12066                 free_irq(board->irq_pin, cf);
12067 -       free_irq(board->det_pin, cf);
12068         device_init_wakeup(&pdev->dev, 0);
12069 +       free_irq(board->det_pin, cf);
12070         iounmap((void __iomem *) cf->socket.io_offset);
12071         release_mem_region(io->start, io->end + 1 - io->start);
12072
12073 -       csa = at91_sys_read(AT91_EBI_CSA);
12074 -       at91_sys_write(AT91_EBI_CSA, csa & ~AT91_EBI_CS4A);
12075 -
12076         kfree(cf);
12077         return 0;
12078  }
12079 diff -urN -x CVS linux-2.6.19-final/drivers/rtc/Kconfig linux-2.6.19/drivers/rtc/Kconfig
12080 --- linux-2.6.19-final/drivers/rtc/Kconfig      Mon Dec  4 16:40:27 2006
12081 +++ linux-2.6.19/drivers/rtc/Kconfig    Thu Oct 12 17:07:39 2006
12082 @@ -280,7 +280,7 @@
12083           To compile this driver as a module, choose M here: the
12084           module will be called rtc-pl031.
12085
12086 -config RTC_DRV_AT91
12087 +config RTC_DRV_AT91RM9200
12088         tristate "AT91RM9200"
12089         depends on RTC_CLASS && ARCH_AT91RM9200
12090         help
12091 diff -urN -x CVS linux-2.6.19-final/drivers/rtc/Makefile linux-2.6.19/drivers/rtc/Makefile
12092 --- linux-2.6.19-final/drivers/rtc/Makefile     Mon Dec  4 16:40:27 2006
12093 +++ linux-2.6.19/drivers/rtc/Makefile   Fri Oct 13 10:49:07 2006
12094 @@ -34,5 +34,5 @@
12095  obj-$(CONFIG_RTC_DRV_PL031)    += rtc-pl031.o
12096  obj-$(CONFIG_RTC_DRV_MAX6902)  += rtc-max6902.o
12097  obj-$(CONFIG_RTC_DRV_V3020)    += rtc-v3020.o
12098 -obj-$(CONFIG_RTC_DRV_AT91)     += rtc-at91.o
12099 +obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
12100  obj-$(CONFIG_RTC_DRV_SH)       += rtc-sh.o
12101 diff -urN -x CVS linux-2.6.19-final/drivers/rtc/rtc-at91.c linux-2.6.19/drivers/rtc/rtc-at91.c
12102 --- linux-2.6.19-final/drivers/rtc/rtc-at91.c   Mon Dec  4 16:40:27 2006
12103 +++ linux-2.6.19/drivers/rtc/rtc-at91.c Thu Jan  1 02:00:00 1970
12104 @@ -1,429 +0,0 @@
12105 -/*
12106 - *     Real Time Clock interface for Linux on Atmel AT91RM9200
12107 - *
12108 - *     Copyright (C) 2002 Rick Bronson
12109 - *
12110 - *     Converted to RTC class model by Andrew Victor
12111 - *
12112 - *     Ported to Linux 2.6 by Steven Scholz
12113 - *     Based on s3c2410-rtc.c Simtec Electronics
12114 - *
12115 - *     Based on sa1100-rtc.c by Nils Faerber
12116 - *     Based on rtc.c by Paul Gortmaker
12117 - *
12118 - *     This program is free software; you can redistribute it and/or
12119 - *     modify it under the terms of the GNU General Public License
12120 - *     as published by the Free Software Foundation; either version
12121 - *     2 of the License, or (at your option) any later version.
12122 - *
12123 - */
12124 -
12125 -#include <linux/module.h>
12126 -#include <linux/kernel.h>
12127 -#include <linux/platform_device.h>
12128 -#include <linux/time.h>
12129 -#include <linux/rtc.h>
12130 -#include <linux/bcd.h>
12131 -#include <linux/interrupt.h>
12132 -#include <linux/ioctl.h>
12133 -#include <linux/completion.h>
12134 -
12135 -#include <asm/uaccess.h>
12136 -#include <asm/rtc.h>
12137 -
12138 -#include <asm/mach/time.h>
12139 -
12140 -
12141 -#define AT91_RTC_FREQ          1
12142 -#define AT91_RTC_EPOCH         1900UL  /* just like arch/arm/common/rtctime.c */
12143 -
12144 -static DECLARE_COMPLETION(at91_rtc_updated);
12145 -static unsigned int at91_alarm_year = AT91_RTC_EPOCH;
12146 -
12147 -/*
12148 - * Decode time/date into rtc_time structure
12149 - */
12150 -static void at91_rtc_decodetime(unsigned int timereg, unsigned int calreg,
12151 -                               struct rtc_time *tm)
12152 -{
12153 -       unsigned int time, date;
12154 -
12155 -       /* must read twice in case it changes */
12156 -       do {
12157 -               time = at91_sys_read(timereg);
12158 -               date = at91_sys_read(calreg);
12159 -       } while ((time != at91_sys_read(timereg)) ||
12160 -                       (date != at91_sys_read(calreg)));
12161 -
12162 -       tm->tm_sec  = BCD2BIN((time & AT91_RTC_SEC) >> 0);
12163 -       tm->tm_min  = BCD2BIN((time & AT91_RTC_MIN) >> 8);
12164 -       tm->tm_hour = BCD2BIN((time & AT91_RTC_HOUR) >> 16);
12165 -
12166 -       /*
12167 -        * The Calendar Alarm register does not have a field for
12168 -        * the year - so these will return an invalid value.  When an
12169 -        * alarm is set, at91_alarm_year wille store the current year.
12170 -        */
12171 -       tm->tm_year  = BCD2BIN(date & AT91_RTC_CENT) * 100;     /* century */
12172 -       tm->tm_year += BCD2BIN((date & AT91_RTC_YEAR) >> 8);    /* year */
12173 -
12174 -       tm->tm_wday = BCD2BIN((date & AT91_RTC_DAY) >> 21) - 1; /* day of the week [0-6], Sunday=0 */
12175 -       tm->tm_mon  = BCD2BIN((date & AT91_RTC_MONTH) >> 16) - 1;
12176 -       tm->tm_mday = BCD2BIN((date & AT91_RTC_DATE) >> 24);
12177 -}
12178 -
12179 -/*
12180 - * Read current time and date in RTC
12181 - */
12182 -static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
12183 -{
12184 -       at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, tm);
12185 -       tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
12186 -       tm->tm_year = tm->tm_year - 1900;
12187 -
12188 -       pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
12189 -               1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
12190 -               tm->tm_hour, tm->tm_min, tm->tm_sec);
12191 -
12192 -       return 0;
12193 -}
12194 -
12195 -/*
12196 - * Set current time and date in RTC
12197 - */
12198 -static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
12199 -{
12200 -       unsigned long cr;
12201 -
12202 -       pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
12203 -               1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
12204 -               tm->tm_hour, tm->tm_min, tm->tm_sec);
12205 -
12206 -       /* Stop Time/Calendar from counting */
12207 -       cr = at91_sys_read(AT91_RTC_CR);
12208 -       at91_sys_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
12209 -
12210 -       at91_sys_write(AT91_RTC_IER, AT91_RTC_ACKUPD);
12211 -       wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
12212 -       at91_sys_write(AT91_RTC_IDR, AT91_RTC_ACKUPD);
12213 -
12214 -       at91_sys_write(AT91_RTC_TIMR,
12215 -                         BIN2BCD(tm->tm_sec) << 0
12216 -                       | BIN2BCD(tm->tm_min) << 8
12217 -                       | BIN2BCD(tm->tm_hour) << 16);
12218 -
12219 -       at91_sys_write(AT91_RTC_CALR,
12220 -                         BIN2BCD((tm->tm_year + 1900) / 100)   /* century */
12221 -                       | BIN2BCD(tm->tm_year % 100) << 8       /* year */
12222 -                       | BIN2BCD(tm->tm_mon + 1) << 16         /* tm_mon starts at zero */
12223 -                       | BIN2BCD(tm->tm_wday + 1) << 21        /* day of the week [0-6], Sunday=0 */
12224 -                       | BIN2BCD(tm->tm_mday) << 24);
12225 -
12226 -       /* Restart Time/Calendar */
12227 -       cr = at91_sys_read(AT91_RTC_CR);
12228 -       at91_sys_write(AT91_RTC_CR, cr & ~(AT91_RTC_UPDCAL | AT91_RTC_UPDTIM));
12229 -
12230 -       return 0;
12231 -}
12232 -
12233 -/*
12234 - * Read alarm time and date in RTC
12235 - */
12236 -static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
12237 -{
12238 -       struct rtc_time *tm = &alrm->time;
12239 -
12240 -       at91_rtc_decodetime(AT91_RTC_TIMALR, AT91_RTC_CALALR, tm);
12241 -       tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
12242 -       tm->tm_year = at91_alarm_year - 1900;
12243 -
12244 -       pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
12245 -               1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
12246 -               tm->tm_hour, tm->tm_min, tm->tm_sec);
12247 -
12248 -       return 0;
12249 -}
12250 -
12251 -/*
12252 - * Set alarm time and date in RTC
12253 - */
12254 -static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
12255 -{
12256 -       struct rtc_time tm;
12257 -
12258 -       at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, &tm);
12259 -
12260 -       at91_alarm_year = tm.tm_year;
12261 -
12262 -       tm.tm_hour = alrm->time.tm_hour;
12263 -       tm.tm_min = alrm->time.tm_min;
12264 -       tm.tm_sec = alrm->time.tm_sec;
12265 -
12266 -       at91_sys_write(AT91_RTC_TIMALR,
12267 -                 BIN2BCD(tm.tm_sec) << 0
12268 -               | BIN2BCD(tm.tm_min) << 8
12269 -               | BIN2BCD(tm.tm_hour) << 16
12270 -               | AT91_RTC_HOUREN | AT91_RTC_MINEN | AT91_RTC_SECEN);
12271 -       at91_sys_write(AT91_RTC_CALALR,
12272 -                 BIN2BCD(tm.tm_mon + 1) << 16          /* tm_mon starts at zero */
12273 -               | BIN2BCD(tm.tm_mday) << 24
12274 -               | AT91_RTC_DATEEN | AT91_RTC_MTHEN);
12275 -
12276 -       pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
12277 -               at91_alarm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour,
12278 -               tm.tm_min, tm.tm_sec);
12279 -
12280 -       return 0;
12281 -}
12282 -
12283 -/*
12284 - * Handle commands from user-space
12285 - */
12286 -static int at91_rtc_ioctl(struct device *dev, unsigned int cmd,
12287 -                       unsigned long arg)
12288 -{
12289 -       int ret = 0;
12290 -
12291 -       pr_debug("%s(): cmd=%08x, arg=%08lx.\n", __FUNCTION__, cmd, arg);
12292 -
12293 -       switch (cmd) {
12294 -       case RTC_AIE_OFF:       /* alarm off */
12295 -               at91_sys_write(AT91_RTC_IDR, AT91_RTC_ALARM);
12296 -               break;
12297 -       case RTC_AIE_ON:        /* alarm on */
12298 -               at91_sys_write(AT91_RTC_IER, AT91_RTC_ALARM);
12299 -               break;
12300 -       case RTC_UIE_OFF:       /* update off */
12301 -       case RTC_PIE_OFF:       /* periodic off */
12302 -               at91_sys_write(AT91_RTC_IDR, AT91_RTC_SECEV);
12303 -               break;
12304 -       case RTC_UIE_ON:        /* update on */
12305 -       case RTC_PIE_ON:        /* periodic on */
12306 -               at91_sys_write(AT91_RTC_IER, AT91_RTC_SECEV);
12307 -               break;
12308 -       case RTC_IRQP_READ:     /* read periodic alarm frequency */
12309 -               ret = put_user(AT91_RTC_FREQ, (unsigned long *) arg);
12310 -               break;
12311 -       case RTC_IRQP_SET:      /* set periodic alarm frequency */
12312 -               if (arg != AT91_RTC_FREQ)
12313 -                       ret = -EINVAL;
12314 -               break;
12315 -       default:
12316 -               ret = -ENOIOCTLCMD;
12317 -               break;
12318 -       }
12319 -
12320 -       return ret;
12321 -}
12322 -
12323 -/*
12324 - * Provide additional RTC information in /proc/driver/rtc
12325 - */
12326 -static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
12327 -{
12328 -       unsigned long imr = at91_sys_read(AT91_RTC_IMR);
12329 -
12330 -       seq_printf(seq, "alarm_IRQ\t: %s\n",
12331 -                       (imr & AT91_RTC_ALARM) ? "yes" : "no");
12332 -       seq_printf(seq, "update_IRQ\t: %s\n",
12333 -                       (imr & AT91_RTC_ACKUPD) ? "yes" : "no");
12334 -       seq_printf(seq, "periodic_IRQ\t: %s\n",
12335 -                       (imr & AT91_RTC_SECEV) ? "yes" : "no");
12336 -       seq_printf(seq, "periodic_freq\t: %ld\n",
12337 -                       (unsigned long) AT91_RTC_FREQ);
12338 -
12339 -       return 0;
12340 -}
12341 -
12342 -/*
12343 - * IRQ handler for the RTC
12344 - */
12345 -static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
12346 -{
12347 -       struct platform_device *pdev = dev_id;
12348 -       struct rtc_device *rtc = platform_get_drvdata(pdev);
12349 -       unsigned int rtsr;
12350 -       unsigned long events = 0;
12351 -
12352 -       rtsr = at91_sys_read(AT91_RTC_SR) & at91_sys_read(AT91_RTC_IMR);
12353 -       if (rtsr) {             /* this interrupt is shared!  Is it ours? */
12354 -               if (rtsr & AT91_RTC_ALARM)
12355 -                       events |= (RTC_AF | RTC_IRQF);
12356 -               if (rtsr & AT91_RTC_SECEV)
12357 -                       events |= (RTC_UF | RTC_IRQF);
12358 -               if (rtsr & AT91_RTC_ACKUPD)
12359 -                       complete(&at91_rtc_updated);
12360 -
12361 -               at91_sys_write(AT91_RTC_SCCR, rtsr);    /* clear status reg */
12362 -
12363 -               rtc_update_irq(&rtc->class_dev, 1, events);
12364 -
12365 -               pr_debug("%s(): num=%ld, events=0x%02lx\n", __FUNCTION__,
12366 -                       events >> 8, events & 0x000000FF);
12367 -
12368 -               return IRQ_HANDLED;
12369 -       }
12370 -       return IRQ_NONE;                /* not handled */
12371 -}
12372 -
12373 -static const struct rtc_class_ops at91_rtc_ops = {
12374 -       .ioctl          = at91_rtc_ioctl,
12375 -       .read_time      = at91_rtc_readtime,
12376 -       .set_time       = at91_rtc_settime,
12377 -       .read_alarm     = at91_rtc_readalarm,
12378 -       .set_alarm      = at91_rtc_setalarm,
12379 -       .proc           = at91_rtc_proc,
12380 -};
12381 -
12382 -/*
12383 - * Initialize and install RTC driver
12384 - */
12385 -static int __init at91_rtc_probe(struct platform_device *pdev)
12386 -{
12387 -       struct rtc_device *rtc;
12388 -       int ret;
12389 -
12390 -       at91_sys_write(AT91_RTC_CR, 0);
12391 -       at91_sys_write(AT91_RTC_MR, 0);         /* 24 hour mode */
12392 -
12393 -       /* Disable all interrupts */
12394 -       at91_sys_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
12395 -                                       AT91_RTC_SECEV | AT91_RTC_TIMEV |
12396 -                                       AT91_RTC_CALEV);
12397 -
12398 -       ret = request_irq(AT91_ID_SYS, at91_rtc_interrupt,
12399 -                               IRQF_DISABLED | IRQF_SHARED,
12400 -                               "at91_rtc", pdev);
12401 -       if (ret) {
12402 -               printk(KERN_ERR "at91_rtc: IRQ %d already in use.\n",
12403 -                               AT91_ID_SYS);
12404 -               return ret;
12405 -       }
12406 -
12407 -       rtc = rtc_device_register(pdev->name, &pdev->dev,
12408 -                               &at91_rtc_ops, THIS_MODULE);
12409 -       if (IS_ERR(rtc)) {
12410 -               free_irq(AT91_ID_SYS, pdev);
12411 -               return PTR_ERR(rtc);
12412 -       }
12413 -       platform_set_drvdata(pdev, rtc);
12414 -       device_init_wakeup(&pdev->dev, 1);
12415 -
12416 -       printk(KERN_INFO "AT91 Real Time Clock driver.\n");
12417 -       return 0;
12418 -}
12419 -
12420 -/*
12421 - * Disable and remove the RTC driver
12422 - */
12423 -static int __devexit at91_rtc_remove(struct platform_device *pdev)
12424 -{
12425 -       struct rtc_device *rtc = platform_get_drvdata(pdev);
12426 -
12427 -       /* Disable all interrupts */
12428 -       at91_sys_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
12429 -                                       AT91_RTC_SECEV | AT91_RTC_TIMEV |
12430 -                                       AT91_RTC_CALEV);
12431 -       free_irq(AT91_ID_SYS, pdev);
12432 -
12433 -       rtc_device_unregister(rtc);
12434 -       platform_set_drvdata(pdev, NULL);
12435 -       device_init_wakeup(&pdev->dev, 0);
12436 -
12437 -       return 0;
12438 -}
12439 -
12440 -#ifdef CONFIG_PM
12441 -
12442 -/* AT91RM9200 RTC Power management control */
12443 -
12444 -static struct timespec at91_rtc_delta;
12445 -static u32 at91_rtc_imr;
12446 -
12447 -static int at91_rtc_suspend(struct platform_device *pdev, pm_message_t state)
12448 -{
12449 -       struct rtc_time tm;
12450 -       struct timespec time;
12451 -
12452 -       time.tv_nsec = 0;
12453 -
12454 -       /* calculate time delta for suspend */
12455 -       at91_rtc_readtime(&pdev->dev, &tm);
12456 -       rtc_tm_to_time(&tm, &time.tv_sec);
12457 -       save_time_delta(&at91_rtc_delta, &time);
12458 -
12459 -       /* this IRQ is shared with DBGU and other hardware which isn't
12460 -        * necessarily doing PM like we are...
12461 -        */
12462 -       at91_rtc_imr = at91_sys_read(AT91_RTC_IMR)
12463 -                       & (AT91_RTC_ALARM|AT91_RTC_SECEV);
12464 -       if (at91_rtc_imr) {
12465 -               if (device_may_wakeup(&pdev->dev))
12466 -                       enable_irq_wake(AT91_ID_SYS);
12467 -               else
12468 -                       at91_sys_write(AT91_RTC_IDR, at91_rtc_imr);
12469 -       }
12470 -
12471 -       pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
12472 -               1900 + tm.tm_year, tm.tm_mon, tm.tm_mday,
12473 -               tm.tm_hour, tm.tm_min, tm.tm_sec);
12474 -
12475 -       return 0;
12476 -}
12477 -
12478 -static int at91_rtc_resume(struct platform_device *pdev)
12479 -{
12480 -       struct rtc_time tm;
12481 -       struct timespec time;
12482 -
12483 -       time.tv_nsec = 0;
12484 -
12485 -       at91_rtc_readtime(&pdev->dev, &tm);
12486 -       rtc_tm_to_time(&tm, &time.tv_sec);
12487 -       restore_time_delta(&at91_rtc_delta, &time);
12488 -
12489 -       if (at91_rtc_imr) {
12490 -               if (device_may_wakeup(&pdev->dev))
12491 -                       disable_irq_wake(AT91_ID_SYS);
12492 -               else
12493 -                       at91_sys_write(AT91_RTC_IER, at91_rtc_imr);
12494 -       }
12495 -
12496 -       pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
12497 -               1900 + tm.tm_year, tm.tm_mon, tm.tm_mday,
12498 -               tm.tm_hour, tm.tm_min, tm.tm_sec);
12499 -
12500 -       return 0;
12501 -}
12502 -#else
12503 -#define at91_rtc_suspend NULL
12504 -#define at91_rtc_resume  NULL
12505 -#endif
12506 -
12507 -static struct platform_driver at91_rtc_driver = {
12508 -       .probe          = at91_rtc_probe,
12509 -       .remove         = at91_rtc_remove,
12510 -       .suspend        = at91_rtc_suspend,
12511 -       .resume         = at91_rtc_resume,
12512 -       .driver         = {
12513 -               .name   = "at91_rtc",
12514 -               .owner  = THIS_MODULE,
12515 -       },
12516 -};
12517 -
12518 -static int __init at91_rtc_init(void)
12519 -{
12520 -       return platform_driver_register(&at91_rtc_driver);
12521 -}
12522 -
12523 -static void __exit at91_rtc_exit(void)
12524 -{
12525 -       platform_driver_unregister(&at91_rtc_driver);
12526 -}
12527 -
12528 -module_init(at91_rtc_init);
12529 -module_exit(at91_rtc_exit);
12530 -
12531 -MODULE_AUTHOR("Rick Bronson");
12532 -MODULE_DESCRIPTION("RTC driver for Atmel AT91RM9200");
12533 -MODULE_LICENSE("GPL");
12534 diff -urN -x CVS linux-2.6.19-final/drivers/rtc/rtc-at91rm9200.c linux-2.6.19/drivers/rtc/rtc-at91rm9200.c
12535 --- linux-2.6.19-final/drivers/rtc/rtc-at91rm9200.c     Thu Jan  1 02:00:00 1970
12536 +++ linux-2.6.19/drivers/rtc/rtc-at91rm9200.c   Thu Nov 30 09:08:25 2006
12537 @@ -0,0 +1,430 @@
12538 +/*
12539 + *     Real Time Clock interface for Linux on Atmel AT91RM9200
12540 + *
12541 + *     Copyright (C) 2002 Rick Bronson
12542 + *
12543 + *     Converted to RTC class model by Andrew Victor
12544 + *
12545 + *     Ported to Linux 2.6 by Steven Scholz
12546 + *     Based on s3c2410-rtc.c Simtec Electronics
12547 + *
12548 + *     Based on sa1100-rtc.c by Nils Faerber
12549 + *     Based on rtc.c by Paul Gortmaker
12550 + *
12551 + *     This program is free software; you can redistribute it and/or
12552 + *     modify it under the terms of the GNU General Public License
12553 + *     as published by the Free Software Foundation; either version
12554 + *     2 of the License, or (at your option) any later version.
12555 + *
12556 + */
12557 +
12558 +#include <linux/module.h>
12559 +#include <linux/kernel.h>
12560 +#include <linux/platform_device.h>
12561 +#include <linux/time.h>
12562 +#include <linux/rtc.h>
12563 +#include <linux/bcd.h>
12564 +#include <linux/interrupt.h>
12565 +#include <linux/ioctl.h>
12566 +#include <linux/completion.h>
12567 +
12568 +#include <asm/uaccess.h>
12569 +#include <asm/rtc.h>
12570 +
12571 +#include <asm/mach/time.h>
12572 +#include <asm/arch/at91_rtc.h>
12573 +
12574 +
12575 +#define AT91_RTC_FREQ          1
12576 +#define AT91_RTC_EPOCH         1900UL  /* just like arch/arm/common/rtctime.c */
12577 +
12578 +static DECLARE_COMPLETION(at91_rtc_updated);
12579 +static unsigned int at91_alarm_year = AT91_RTC_EPOCH;
12580 +
12581 +/*
12582 + * Decode time/date into rtc_time structure
12583 + */
12584 +static void at91_rtc_decodetime(unsigned int timereg, unsigned int calreg,
12585 +                               struct rtc_time *tm)
12586 +{
12587 +       unsigned int time, date;
12588 +
12589 +       /* must read twice in case it changes */
12590 +       do {
12591 +               time = at91_sys_read(timereg);
12592 +               date = at91_sys_read(calreg);
12593 +       } while ((time != at91_sys_read(timereg)) ||
12594 +                       (date != at91_sys_read(calreg)));
12595 +
12596 +       tm->tm_sec  = BCD2BIN((time & AT91_RTC_SEC) >> 0);
12597 +       tm->tm_min  = BCD2BIN((time & AT91_RTC_MIN) >> 8);
12598 +       tm->tm_hour = BCD2BIN((time & AT91_RTC_HOUR) >> 16);
12599 +
12600 +       /*
12601 +        * The Calendar Alarm register does not have a field for
12602 +        * the year - so these will return an invalid value.  When an
12603 +        * alarm is set, at91_alarm_year wille store the current year.
12604 +        */
12605 +       tm->tm_year  = BCD2BIN(date & AT91_RTC_CENT) * 100;     /* century */
12606 +       tm->tm_year += BCD2BIN((date & AT91_RTC_YEAR) >> 8);    /* year */
12607 +
12608 +       tm->tm_wday = BCD2BIN((date & AT91_RTC_DAY) >> 21) - 1; /* day of the week [0-6], Sunday=0 */
12609 +       tm->tm_mon  = BCD2BIN((date & AT91_RTC_MONTH) >> 16) - 1;
12610 +       tm->tm_mday = BCD2BIN((date & AT91_RTC_DATE) >> 24);
12611 +}
12612 +
12613 +/*
12614 + * Read current time and date in RTC
12615 + */
12616 +static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
12617 +{
12618 +       at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, tm);
12619 +       tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
12620 +       tm->tm_year = tm->tm_year - 1900;
12621 +
12622 +       pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
12623 +               1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
12624 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
12625 +
12626 +       return 0;
12627 +}
12628 +
12629 +/*
12630 + * Set current time and date in RTC
12631 + */
12632 +static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
12633 +{
12634 +       unsigned long cr;
12635 +
12636 +       pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
12637 +               1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
12638 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
12639 +
12640 +       /* Stop Time/Calendar from counting */
12641 +       cr = at91_sys_read(AT91_RTC_CR);
12642 +       at91_sys_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
12643 +
12644 +       at91_sys_write(AT91_RTC_IER, AT91_RTC_ACKUPD);
12645 +       wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
12646 +       at91_sys_write(AT91_RTC_IDR, AT91_RTC_ACKUPD);
12647 +
12648 +       at91_sys_write(AT91_RTC_TIMR,
12649 +                         BIN2BCD(tm->tm_sec) << 0
12650 +                       | BIN2BCD(tm->tm_min) << 8
12651 +                       | BIN2BCD(tm->tm_hour) << 16);
12652 +
12653 +       at91_sys_write(AT91_RTC_CALR,
12654 +                         BIN2BCD((tm->tm_year + 1900) / 100)   /* century */
12655 +                       | BIN2BCD(tm->tm_year % 100) << 8       /* year */
12656 +                       | BIN2BCD(tm->tm_mon + 1) << 16         /* tm_mon starts at zero */
12657 +                       | BIN2BCD(tm->tm_wday + 1) << 21        /* day of the week [0-6], Sunday=0 */
12658 +                       | BIN2BCD(tm->tm_mday) << 24);
12659 +
12660 +       /* Restart Time/Calendar */
12661 +       cr = at91_sys_read(AT91_RTC_CR);
12662 +       at91_sys_write(AT91_RTC_CR, cr & ~(AT91_RTC_UPDCAL | AT91_RTC_UPDTIM));
12663 +
12664 +       return 0;
12665 +}
12666 +
12667 +/*
12668 + * Read alarm time and date in RTC
12669 + */
12670 +static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
12671 +{
12672 +       struct rtc_time *tm = &alrm->time;
12673 +
12674 +       at91_rtc_decodetime(AT91_RTC_TIMALR, AT91_RTC_CALALR, tm);
12675 +       tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
12676 +       tm->tm_year = at91_alarm_year - 1900;
12677 +
12678 +       pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
12679 +               1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
12680 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
12681 +
12682 +       return 0;
12683 +}
12684 +
12685 +/*
12686 + * Set alarm time and date in RTC
12687 + */
12688 +static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
12689 +{
12690 +       struct rtc_time tm;
12691 +
12692 +       at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, &tm);
12693 +
12694 +       at91_alarm_year = tm.tm_year;
12695 +
12696 +       tm.tm_hour = alrm->time.tm_hour;
12697 +       tm.tm_min = alrm->time.tm_min;
12698 +       tm.tm_sec = alrm->time.tm_sec;
12699 +
12700 +       at91_sys_write(AT91_RTC_TIMALR,
12701 +                 BIN2BCD(tm.tm_sec) << 0
12702 +               | BIN2BCD(tm.tm_min) << 8
12703 +               | BIN2BCD(tm.tm_hour) << 16
12704 +               | AT91_RTC_HOUREN | AT91_RTC_MINEN | AT91_RTC_SECEN);
12705 +       at91_sys_write(AT91_RTC_CALALR,
12706 +                 BIN2BCD(tm.tm_mon + 1) << 16          /* tm_mon starts at zero */
12707 +               | BIN2BCD(tm.tm_mday) << 24
12708 +               | AT91_RTC_DATEEN | AT91_RTC_MTHEN);
12709 +
12710 +       pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
12711 +               at91_alarm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour,
12712 +               tm.tm_min, tm.tm_sec);
12713 +
12714 +       return 0;
12715 +}
12716 +
12717 +/*
12718 + * Handle commands from user-space
12719 + */
12720 +static int at91_rtc_ioctl(struct device *dev, unsigned int cmd,
12721 +                       unsigned long arg)
12722 +{
12723 +       int ret = 0;
12724 +
12725 +       pr_debug("%s(): cmd=%08x, arg=%08lx.\n", __FUNCTION__, cmd, arg);
12726 +
12727 +       switch (cmd) {
12728 +       case RTC_AIE_OFF:       /* alarm off */
12729 +               at91_sys_write(AT91_RTC_IDR, AT91_RTC_ALARM);
12730 +               break;
12731 +       case RTC_AIE_ON:        /* alarm on */
12732 +               at91_sys_write(AT91_RTC_IER, AT91_RTC_ALARM);
12733 +               break;
12734 +       case RTC_UIE_OFF:       /* update off */
12735 +       case RTC_PIE_OFF:       /* periodic off */
12736 +               at91_sys_write(AT91_RTC_IDR, AT91_RTC_SECEV);
12737 +               break;
12738 +       case RTC_UIE_ON:        /* update on */
12739 +       case RTC_PIE_ON:        /* periodic on */
12740 +               at91_sys_write(AT91_RTC_IER, AT91_RTC_SECEV);
12741 +               break;
12742 +       case RTC_IRQP_READ:     /* read periodic alarm frequency */
12743 +               ret = put_user(AT91_RTC_FREQ, (unsigned long *) arg);
12744 +               break;
12745 +       case RTC_IRQP_SET:      /* set periodic alarm frequency */
12746 +               if (arg != AT91_RTC_FREQ)
12747 +                       ret = -EINVAL;
12748 +               break;
12749 +       default:
12750 +               ret = -ENOIOCTLCMD;
12751 +               break;
12752 +       }
12753 +
12754 +       return ret;
12755 +}
12756 +
12757 +/*
12758 + * Provide additional RTC information in /proc/driver/rtc
12759 + */
12760 +static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
12761 +{
12762 +       unsigned long imr = at91_sys_read(AT91_RTC_IMR);
12763 +
12764 +       seq_printf(seq, "alarm_IRQ\t: %s\n",
12765 +                       (imr & AT91_RTC_ALARM) ? "yes" : "no");
12766 +       seq_printf(seq, "update_IRQ\t: %s\n",
12767 +                       (imr & AT91_RTC_ACKUPD) ? "yes" : "no");
12768 +       seq_printf(seq, "periodic_IRQ\t: %s\n",
12769 +                       (imr & AT91_RTC_SECEV) ? "yes" : "no");
12770 +       seq_printf(seq, "periodic_freq\t: %ld\n",
12771 +                       (unsigned long) AT91_RTC_FREQ);
12772 +
12773 +       return 0;
12774 +}
12775 +
12776 +/*
12777 + * IRQ handler for the RTC
12778 + */
12779 +static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
12780 +{
12781 +       struct platform_device *pdev = dev_id;
12782 +       struct rtc_device *rtc = platform_get_drvdata(pdev);
12783 +       unsigned int rtsr;
12784 +       unsigned long events = 0;
12785 +
12786 +       rtsr = at91_sys_read(AT91_RTC_SR) & at91_sys_read(AT91_RTC_IMR);
12787 +       if (rtsr) {             /* this interrupt is shared!  Is it ours? */
12788 +               if (rtsr & AT91_RTC_ALARM)
12789 +                       events |= (RTC_AF | RTC_IRQF);
12790 +               if (rtsr & AT91_RTC_SECEV)
12791 +                       events |= (RTC_UF | RTC_IRQF);
12792 +               if (rtsr & AT91_RTC_ACKUPD)
12793 +                       complete(&at91_rtc_updated);
12794 +
12795 +               at91_sys_write(AT91_RTC_SCCR, rtsr);    /* clear status reg */
12796 +
12797 +               rtc_update_irq(&rtc->class_dev, 1, events);
12798 +
12799 +               pr_debug("%s(): num=%ld, events=0x%02lx\n", __FUNCTION__,
12800 +                       events >> 8, events & 0x000000FF);
12801 +
12802 +               return IRQ_HANDLED;
12803 +       }
12804 +       return IRQ_NONE;                /* not handled */
12805 +}
12806 +
12807 +static const struct rtc_class_ops at91_rtc_ops = {
12808 +       .ioctl          = at91_rtc_ioctl,
12809 +       .read_time      = at91_rtc_readtime,
12810 +       .set_time       = at91_rtc_settime,
12811 +       .read_alarm     = at91_rtc_readalarm,
12812 +       .set_alarm      = at91_rtc_setalarm,
12813 +       .proc           = at91_rtc_proc,
12814 +};
12815 +
12816 +/*
12817 + * Initialize and install RTC driver
12818 + */
12819 +static int __init at91_rtc_probe(struct platform_device *pdev)
12820 +{
12821 +       struct rtc_device *rtc;
12822 +       int ret;
12823 +
12824 +       at91_sys_write(AT91_RTC_CR, 0);
12825 +       at91_sys_write(AT91_RTC_MR, 0);         /* 24 hour mode */
12826 +
12827 +       /* Disable all interrupts */
12828 +       at91_sys_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
12829 +                                       AT91_RTC_SECEV | AT91_RTC_TIMEV |
12830 +                                       AT91_RTC_CALEV);
12831 +
12832 +       ret = request_irq(AT91_ID_SYS, at91_rtc_interrupt,
12833 +                               IRQF_DISABLED | IRQF_SHARED,
12834 +                               "at91_rtc", pdev);
12835 +       if (ret) {
12836 +               printk(KERN_ERR "at91_rtc: IRQ %d already in use.\n",
12837 +                               AT91_ID_SYS);
12838 +               return ret;
12839 +       }
12840 +
12841 +       rtc = rtc_device_register(pdev->name, &pdev->dev,
12842 +                               &at91_rtc_ops, THIS_MODULE);
12843 +       if (IS_ERR(rtc)) {
12844 +               free_irq(AT91_ID_SYS, pdev);
12845 +               return PTR_ERR(rtc);
12846 +       }
12847 +       platform_set_drvdata(pdev, rtc);
12848 +       device_init_wakeup(&pdev->dev, 1);
12849 +
12850 +       printk(KERN_INFO "AT91 Real Time Clock driver.\n");
12851 +       return 0;
12852 +}
12853 +
12854 +/*
12855 + * Disable and remove the RTC driver
12856 + */
12857 +static int __devexit at91_rtc_remove(struct platform_device *pdev)
12858 +{
12859 +       struct rtc_device *rtc = platform_get_drvdata(pdev);
12860 +
12861 +       /* Disable all interrupts */
12862 +       at91_sys_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
12863 +                                       AT91_RTC_SECEV | AT91_RTC_TIMEV |
12864 +                                       AT91_RTC_CALEV);
12865 +       free_irq(AT91_ID_SYS, pdev);
12866 +
12867 +       rtc_device_unregister(rtc);
12868 +       platform_set_drvdata(pdev, NULL);
12869 +       device_init_wakeup(&pdev->dev, 0);
12870 +
12871 +       return 0;
12872 +}
12873 +
12874 +#ifdef CONFIG_PM
12875 +
12876 +/* AT91RM9200 RTC Power management control */
12877 +
12878 +static struct timespec at91_rtc_delta;
12879 +static u32 at91_rtc_imr;
12880 +
12881 +static int at91_rtc_suspend(struct platform_device *pdev, pm_message_t state)
12882 +{
12883 +       struct rtc_time tm;
12884 +       struct timespec time;
12885 +
12886 +       time.tv_nsec = 0;
12887 +
12888 +       /* calculate time delta for suspend */
12889 +       at91_rtc_readtime(&pdev->dev, &tm);
12890 +       rtc_tm_to_time(&tm, &time.tv_sec);
12891 +       save_time_delta(&at91_rtc_delta, &time);
12892 +
12893 +       /* this IRQ is shared with DBGU and other hardware which isn't
12894 +        * necessarily doing PM like we are...
12895 +        */
12896 +       at91_rtc_imr = at91_sys_read(AT91_RTC_IMR)
12897 +                       & (AT91_RTC_ALARM|AT91_RTC_SECEV);
12898 +       if (at91_rtc_imr) {
12899 +               if (device_may_wakeup(&pdev->dev))
12900 +                       enable_irq_wake(AT91_ID_SYS);
12901 +               else
12902 +                       at91_sys_write(AT91_RTC_IDR, at91_rtc_imr);
12903 +       }
12904 +
12905 +       pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
12906 +               1900 + tm.tm_year, tm.tm_mon, tm.tm_mday,
12907 +               tm.tm_hour, tm.tm_min, tm.tm_sec);
12908 +
12909 +       return 0;
12910 +}
12911 +
12912 +static int at91_rtc_resume(struct platform_device *pdev)
12913 +{
12914 +       struct rtc_time tm;
12915 +       struct timespec time;
12916 +
12917 +       time.tv_nsec = 0;
12918 +
12919 +       at91_rtc_readtime(&pdev->dev, &tm);
12920 +       rtc_tm_to_time(&tm, &time.tv_sec);
12921 +       restore_time_delta(&at91_rtc_delta, &time);
12922 +
12923 +       if (at91_rtc_imr) {
12924 +               if (device_may_wakeup(&pdev->dev))
12925 +                       disable_irq_wake(AT91_ID_SYS);
12926 +               else
12927 +                       at91_sys_write(AT91_RTC_IER, at91_rtc_imr);
12928 +       }
12929 +
12930 +       pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
12931 +               1900 + tm.tm_year, tm.tm_mon, tm.tm_mday,
12932 +               tm.tm_hour, tm.tm_min, tm.tm_sec);
12933 +
12934 +       return 0;
12935 +}
12936 +#else
12937 +#define at91_rtc_suspend NULL
12938 +#define at91_rtc_resume  NULL
12939 +#endif
12940 +
12941 +static struct platform_driver at91_rtc_driver = {
12942 +       .probe          = at91_rtc_probe,
12943 +       .remove         = at91_rtc_remove,
12944 +       .suspend        = at91_rtc_suspend,
12945 +       .resume         = at91_rtc_resume,
12946 +       .driver         = {
12947 +               .name   = "at91_rtc",
12948 +               .owner  = THIS_MODULE,
12949 +       },
12950 +};
12951 +
12952 +static int __init at91_rtc_init(void)
12953 +{
12954 +       return platform_driver_register(&at91_rtc_driver);
12955 +}
12956 +
12957 +static void __exit at91_rtc_exit(void)
12958 +{
12959 +       platform_driver_unregister(&at91_rtc_driver);
12960 +}
12961 +
12962 +module_init(at91_rtc_init);
12963 +module_exit(at91_rtc_exit);
12964 +
12965 +MODULE_AUTHOR("Rick Bronson");
12966 +MODULE_DESCRIPTION("RTC driver for Atmel AT91RM9200");
12967 +MODULE_LICENSE("GPL");
12968 diff -urN -x CVS linux-2.6.19-final/drivers/serial/atmel_serial.c linux-2.6.19/drivers/serial/atmel_serial.c
12969 --- linux-2.6.19-final/drivers/serial/atmel_serial.c    Mon Dec  4 16:40:48 2006
12970 +++ linux-2.6.19/drivers/serial/atmel_serial.c  Fri Nov 10 09:17:31 2006
12971 @@ -1,5 +1,5 @@
12972  /*
12973 - *  linux/drivers/char/at91_serial.c
12974 + *  linux/drivers/char/atmel_serial.c
12975   *
12976   *  Driver for Atmel AT91 / AT32 Serial ports
12977   *  Copyright (C) 2003 Rick Bronson
12978 @@ -7,6 +7,8 @@
12979   *  Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
12980   *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
12981   *
12982 + *  DMA support added by Chip Coldwell.
12983 + *
12984   * This program is free software; you can redistribute it and/or modify
12985   * it under the terms of the GNU General Public License as published by
12986   * the Free Software Foundation; either version 2 of the License, or
12987 @@ -33,19 +35,25 @@
12988  #include <linux/sysrq.h>
12989  #include <linux/tty_flip.h>
12990  #include <linux/platform_device.h>
12991 +#include <linux/dma-mapping.h>
12992
12993  #include <asm/io.h>
12994
12995 -#include <asm/arch/at91rm9200_pdc.h>
12996  #include <asm/mach/serial_at91.h>
12997  #include <asm/arch/board.h>
12998 +#include <asm/arch/at91_pdc.h>
12999  #ifdef CONFIG_ARM
13000 -#include <asm/arch/system.h>
13001 +#include <asm/arch/cpu.h>
13002  #include <asm/arch/gpio.h>
13003  #endif
13004
13005  #include "atmel_serial.h"
13006
13007 +#define SUPPORT_PDC
13008 +#define PDC_BUFFER_SIZE                (L1_CACHE_BYTES << 3)
13009 +#warning "Revisit"
13010 +#define PDC_RX_TIMEOUT         (3 * 10)                /* 3 bytes */
13011 +
13012  #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13013  #define SUPPORT_SYSRQ
13014  #endif
13015 @@ -89,23 +97,30 @@
13016  // #define UART_GET_CR(port)   readl((port)->membase + ATMEL_US_CR)            // is write-only
13017
13018   /* PDC registers */
13019 -#define UART_PUT_PTCR(port,v)  writel(v, (port)->membase + ATMEL_PDC_PTCR)
13020 -#define UART_GET_PTSR(port)    readl((port)->membase + ATMEL_PDC_PTSR)
13021 +#define UART_PUT_PTCR(port,v)  writel(v, (port)->membase + AT91_PDC_PTCR)
13022 +#define UART_GET_PTSR(port)    readl((port)->membase + AT91_PDC_PTSR)
13023
13024 -#define UART_PUT_RPR(port,v)   writel(v, (port)->membase + ATMEL_PDC_RPR)
13025 -#define UART_GET_RPR(port)     readl((port)->membase + ATMEL_PDC_RPR)
13026 -#define UART_PUT_RCR(port,v)   writel(v, (port)->membase + ATMEL_PDC_RCR)
13027 -#define UART_PUT_RNPR(port,v)  writel(v, (port)->membase + ATMEL_PDC_RNPR)
13028 -#define UART_PUT_RNCR(port,v)  writel(v, (port)->membase + ATMEL_PDC_RNCR)
13029 -
13030 -#define UART_PUT_TPR(port,v)   writel(v, (port)->membase + ATMEL_PDC_TPR)
13031 -#define UART_PUT_TCR(port,v)   writel(v, (port)->membase + ATMEL_PDC_TCR)
13032 -//#define UART_PUT_TNPR(port,v)        writel(v, (port)->membase + ATMEL_PDC_TNPR)
13033 -//#define UART_PUT_TNCR(port,v)        writel(v, (port)->membase + ATMEL_PDC_TNCR)
13034 +#define UART_PUT_RPR(port,v)   writel(v, (port)->membase + AT91_PDC_RPR)
13035 +#define UART_GET_RPR(port)     readl((port)->membase + AT91_PDC_RPR)
13036 +#define UART_PUT_RCR(port,v)   writel(v, (port)->membase + AT91_PDC_RCR)
13037 +#define UART_PUT_RNPR(port,v)  writel(v, (port)->membase + AT91_PDC_RNPR)
13038 +#define UART_PUT_RNCR(port,v)  writel(v, (port)->membase + AT91_PDC_RNCR)
13039 +
13040 +#define UART_PUT_TPR(port,v)   writel(v, (port)->membase + AT91_PDC_TPR)
13041 +#define UART_PUT_TCR(port,v)   writel(v, (port)->membase + AT91_PDC_TCR)
13042 +//#define UART_PUT_TNPR(port,v)        writel(v, (port)->membase + AT91_PDC_TNPR)
13043 +//#define UART_PUT_TNCR(port,v)        writel(v, (port)->membase + AT91_PDC_TNCR)
13044
13045  static int (*atmel_open_hook)(struct uart_port *);
13046  static void (*atmel_close_hook)(struct uart_port *);
13047
13048 +struct atmel_dma_buffer {
13049 +       unsigned char   *buf;
13050 +       dma_addr_t      dma_addr;
13051 +       size_t          dma_size;
13052 +       unsigned int    ofs;
13053 +};
13054 +
13055  /*
13056   * We wrap our port structure around the generic uart_port.
13057   */
13058 @@ -113,10 +128,20 @@
13059         struct uart_port        uart;           /* uart */
13060         struct clk              *clk;           /* uart clock */
13061         unsigned short          suspended;      /* is port suspended? */
13062 +
13063 +       short                   use_dma_rx;     /* enable PDC receiver */
13064 +       short                   pdc_rx_idx;     /* current PDC RX buffer */
13065 +       struct atmel_dma_buffer pdc_rx[2];      /* PDC receier */
13066 +
13067 +       short                   use_dma_tx;     /* enable PDC transmitter */
13068 +       struct atmel_dma_buffer pdc_tx;         /* PDC transmitter */
13069  };
13070
13071  static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
13072
13073 +#define PDC_RX_BUF(port)       &(port)->pdc_rx[(port)->pdc_rx_idx]
13074 +#define PDC_RX_SWITCH(port)    (port)->pdc_rx_idx = !(port)->pdc_rx_idx
13075 +
13076  #ifdef SUPPORT_SYSRQ
13077  static struct console atmel_console;
13078  #endif
13079 @@ -137,8 +162,8 @@
13080         unsigned int control = 0;
13081         unsigned int mode;
13082
13083 -#ifdef CONFIG_ARM
13084 -       if (arch_identify() == ARCH_ID_AT91RM9200) {
13085 +#ifdef CONFIG_ARCH_AT91RM9200
13086 +       if (cpu_is_at91rm9200()) {
13087                 /*
13088                  * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21.
13089                  *  We need to drive the pin manually.
13090 @@ -204,7 +229,12 @@
13091  {
13092         struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
13093
13094 -       UART_PUT_IDR(port, ATMEL_US_TXRDY);
13095 +       if (atmel_port->use_dma_tx) {
13096 +               UART_PUT_PTCR(port, AT91_PDC_TXTDIS);           /* disable PDC transmit */
13097 +               UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
13098 +       }
13099 +       else
13100 +               UART_PUT_IDR(port, ATMEL_US_TXRDY);
13101  }
13102
13103  /*
13104 @@ -214,7 +244,17 @@
13105  {
13106         struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
13107
13108 -       UART_PUT_IER(port, ATMEL_US_TXRDY);
13109 +       if (atmel_port->use_dma_tx) {
13110 +               if (UART_GET_PTSR(port) & AT91_PDC_TXTEN)
13111 +                       /* The transmitter is already running.  Yes, we
13112 +                          really need this.*/
13113 +                       return;
13114 +
13115 +               UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
13116 +               UART_PUT_PTCR(port, AT91_PDC_TXTEN);            /* re-enable PDC transmit */
13117 +       }
13118 +       else
13119 +               UART_PUT_IER(port, ATMEL_US_TXRDY);
13120  }
13121
13122  /*
13123 @@ -224,7 +264,12 @@
13124  {
13125         struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
13126
13127 -       UART_PUT_IDR(port, ATMEL_US_RXRDY);
13128 +       if (atmel_port->use_dma_rx) {
13129 +               UART_PUT_PTCR(port, AT91_PDC_RXTDIS);           /* disable PDC receive */
13130 +               UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
13131 +       }
13132 +       else
13133 +               UART_PUT_IDR(port, ATMEL_US_RXRDY);
13134  }
13135
13136  /*
13137 @@ -247,6 +292,134 @@
13138  }
13139
13140  /*
13141 + * Receive data via the PDC.  A buffer has been fulled.
13142 + */
13143 +static void at91_pdc_endrx(struct uart_port *port)
13144 +{
13145 +       struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
13146 +       struct tty_struct *tty = port->info->tty;
13147 +       struct atmel_dma_buffer *pdc = PDC_RX_BUF(atmel_port);
13148 +       unsigned int count;
13149 +
13150 +       count = pdc->dma_size - pdc->ofs;
13151 +       if (likely(count > 0)) {
13152 +               dma_sync_single_for_cpu(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE);
13153 +               tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
13154 +               tty_flip_buffer_push(tty);
13155 +
13156 +               port->icount.rx += count;
13157 +       }
13158 +
13159 +       /* Set this buffer as the next receive buffer */
13160 +       pdc->ofs = 0;
13161 +       UART_PUT_RNPR(port, pdc->dma_addr);
13162 +       UART_PUT_RNCR(port, pdc->dma_size);
13163 +
13164 +       /* Switch to next buffer */
13165 +       PDC_RX_SWITCH(atmel_port);              /* next PDC buffer */
13166 +}
13167 +
13168 +/*
13169 + * Receive data via the PDC.  At least one byte was received, but the
13170 + * buffer was not full when the inter-character timeout expired.
13171 + */
13172 +static void at91_pdc_timeout(struct uart_port *port)
13173 +{
13174 +       struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
13175 +       struct tty_struct *tty = port->info->tty;
13176 +       struct atmel_dma_buffer *pdc = PDC_RX_BUF(atmel_port);
13177 +       /* unsigned */ int ofs, count;
13178 +
13179 +       ofs = UART_GET_RPR(port) - pdc->dma_addr;       /* current DMA adress */
13180 +       count = ofs - pdc->ofs;
13181 +
13182 +       if (likely(count > 0)) {
13183 +               dma_sync_single_for_cpu(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE);
13184 +               tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
13185 +               tty_flip_buffer_push(tty);
13186 +
13187 +               pdc->ofs = ofs;
13188 +               port->icount.rx += count;
13189 +       }
13190 +
13191 +       /* reset the UART timeout */
13192 +       UART_PUT_CR(port, ATMEL_US_STTTO);
13193 +}
13194 +
13195 +/*
13196 + * Deal with parity, framing and overrun errors.
13197 + */
13198 +static void at91_pdc_rxerr(struct uart_port *port, unsigned int status)
13199 +{
13200 +       /* clear error */
13201 +       UART_PUT_CR(port, ATMEL_US_RSTSTA);
13202 +
13203 +       if (status & ATMEL_US_RXBRK) {
13204 +               status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);    /* ignore side-effect */
13205 +               port->icount.brk++;
13206 +       }
13207 +       if (status & ATMEL_US_PARE)
13208 +               port->icount.parity++;
13209 +       if (status & ATMEL_US_FRAME)
13210 +               port->icount.frame++;
13211 +       if (status & ATMEL_US_OVRE)
13212 +               port->icount.overrun++;
13213 +}
13214 +
13215 +/*
13216 + * A transmission via the PDC is complete.
13217 + */
13218 +static void at91_pdc_endtx(struct uart_port *port)
13219 +{
13220 +       struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
13221 +       struct circ_buf *xmit = &port->info->xmit;
13222 +       struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
13223 +
13224 +       xmit->tail += pdc->ofs;
13225 +       if (xmit->tail >= SERIAL_XMIT_SIZE)
13226 +               xmit->tail -= SERIAL_XMIT_SIZE;
13227 +
13228 +       port->icount.tx += pdc->ofs;
13229 +       pdc->ofs = 0;
13230 +
13231 +       if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
13232 +               uart_write_wakeup(port);
13233 +}
13234 +
13235 +/*
13236 + * The PDC transmitter is idle, so either start the next transfer or
13237 + * disable the transmitter.
13238 + */
13239 +static void at91_pdc_txbufe(struct uart_port *port)
13240 +{
13241 +       struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
13242 +       struct circ_buf *xmit = &port->info->xmit;
13243 +       struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
13244 +       int count;
13245 +
13246 +       if (!uart_circ_empty(xmit)) {
13247 +               /* more to transmit - setup next transfer */
13248 +               UART_PUT_PTCR(port, AT91_PDC_TXTDIS);                   /* disable PDC transmit */
13249 +               dma_sync_single_for_device(port->dev, pdc->dma_addr, pdc->dma_size, DMA_TO_DEVICE);
13250 +
13251 +               if (xmit->tail < xmit->head)
13252 +                       count = xmit->head - xmit->tail;
13253 +               else
13254 +                       count = SERIAL_XMIT_SIZE - xmit->tail;
13255 +               pdc->ofs = count;
13256 +
13257 +               UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
13258 +               UART_PUT_TCR(port, count);
13259 +               UART_PUT_PTCR(port, AT91_PDC_TXTEN);                    /* re-enable PDC transmit */
13260 +       }
13261 +       else {
13262 +               /* nothing left to transmit - disable the transmitter */
13263 +               UART_PUT_PTCR(port, AT91_PDC_TXTDIS);                   /* disable PDC transmit */
13264 +               UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
13265 +       }
13266 +}
13267 +
13268 +/*
13269   * Characters received (called from interrupt handler)
13270   */
13271  static void atmel_rx_chars(struct uart_port *port)
13272 @@ -348,6 +521,14 @@
13273         status = UART_GET_CSR(port);
13274         pending = status & UART_GET_IMR(port);
13275         while (pending) {
13276 +               /* PDC receive */
13277 +               if (pending & ATMEL_US_ENDRX)
13278 +                       at91_pdc_endrx(port);
13279 +               if (pending & ATMEL_US_TIMEOUT)
13280 +                       at91_pdc_timeout(port);
13281 +               if (atmel_port->use_dma_rx && pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | ATMEL_US_FRAME | ATMEL_US_PARE))
13282 +                       at91_pdc_rxerr(port, pending);
13283 +
13284                 /* Interrupt receive */
13285                 if (pending & ATMEL_US_RXRDY)
13286                         atmel_rx_chars(port);
13287 @@ -362,6 +543,12 @@
13288                 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC))
13289                         wake_up_interruptible(&port->info->delta_msr_wait);
13290
13291 +               /* PDC transmit */
13292 +               if (pending & ATMEL_US_ENDTX)
13293 +                       at91_pdc_endtx(port);
13294 +               if (pending & ATMEL_US_TXBUFE)
13295 +                       at91_pdc_txbufe(port);
13296 +
13297                 /* Interrupt transmit */
13298                 if (pending & ATMEL_US_TXRDY)
13299                         atmel_tx_chars(port);
13300 @@ -399,6 +586,47 @@
13301                 return retval;
13302         }
13303
13304 +       /*
13305 +        * Initialize DMA (if necessary)
13306 +        */
13307 +       if (atmel_port->use_dma_rx) {
13308 +               int i;
13309 +
13310 +               for (i = 0; i < 2; i++) {
13311 +                       struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
13312 +
13313 +                       pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
13314 +                       if (pdc->buf == NULL) {
13315 +                               if (i != 0) {
13316 +                                       dma_unmap_single(port->dev, atmel_port->pdc_rx[0].dma_addr, PDC_BUFFER_SIZE, DMA_FROM_DEVICE);
13317 +                                       kfree(atmel_port->pdc_rx[0].buf);
13318 +                               }
13319 +                               free_irq(port->irq, port);
13320 +                               return -ENOMEM;
13321 +                       }
13322 +                       pdc->dma_addr = dma_map_single(port->dev, pdc->buf, PDC_BUFFER_SIZE, DMA_FROM_DEVICE);
13323 +                       pdc->dma_size = PDC_BUFFER_SIZE;
13324 +                       pdc->ofs = 0;
13325 +               }
13326 +
13327 +               atmel_port->pdc_rx_idx = 0;
13328 +
13329 +               UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
13330 +               UART_PUT_RCR(port, PDC_BUFFER_SIZE);
13331 +
13332 +               UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
13333 +               UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
13334 +       }
13335 +       if (atmel_port->use_dma_tx) {
13336 +               struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
13337 +               struct circ_buf *xmit = &port->info->xmit;
13338 +
13339 +               pdc->buf = xmit->buf;
13340 +               pdc->dma_addr = dma_map_single(port->dev, pdc->buf, SERIAL_XMIT_SIZE, DMA_TO_DEVICE);
13341 +               pdc->dma_size = SERIAL_XMIT_SIZE;
13342 +               pdc->ofs = 0;
13343 +       }
13344 +
13345         /*
13346          * If there is a specific "open" function (to register
13347          * control line interrupts)
13348 @@ -417,7 +645,15 @@
13349         UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
13350         UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);               /* enable xmit & rcvr */
13351
13352 -       UART_PUT_IER(port, ATMEL_US_RXRDY);             /* enable receive only */
13353 +       if (atmel_port->use_dma_rx) {
13354 +               UART_PUT_RTOR(port, PDC_RX_TIMEOUT);            /* set UART timeout */
13355 +               UART_PUT_CR(port, ATMEL_US_STTTO);
13356 +
13357 +               UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
13358 +               UART_PUT_PTCR(port, AT91_PDC_RXTEN);            /* enable PDC controller */
13359 +       }
13360 +       else
13361 +               UART_PUT_IER(port, ATMEL_US_RXRDY);             /* enable receive only */
13362
13363         return 0;
13364  }
13365 @@ -430,6 +666,25 @@
13366         struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
13367
13368         /*
13369 +        * Shut-down the DMA.
13370 +        */
13371 +       if (atmel_port->use_dma_rx) {
13372 +               int i;
13373 +
13374 +               for (i = 0; i < 2; i++) {
13375 +                       struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
13376 +
13377 +                       dma_unmap_single(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE);
13378 +                       kfree(pdc->buf);
13379 +               }
13380 +       }
13381 +       if (atmel_port->use_dma_tx) {
13382 +               struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
13383 +
13384 +               dma_unmap_single(port->dev, pdc->dma_addr, pdc->dma_size, DMA_TO_DEVICE);
13385 +       }
13386 +
13387 +       /*
13388          * Disable all interrupts, port and break condition.
13389          */
13390         UART_PUT_CR(port, ATMEL_US_RSTSTA);
13391 @@ -480,6 +735,7 @@
13392   */
13393  static void atmel_set_termios(struct uart_port *port, struct termios * termios, struct termios * old)
13394  {
13395 +       struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
13396         unsigned long flags;
13397         unsigned int mode, imr, quot, baud;
13398
13399 @@ -533,6 +789,9 @@
13400         if (termios->c_iflag & (BRKINT | PARMRK))
13401                 port->read_status_mask |= ATMEL_US_RXBRK;
13402
13403 +       if (atmel_port->use_dma_rx)     /* need to enable error interrupts */
13404 +               UART_PUT_IER(port, port->read_status_mask);
13405 +
13406         /*
13407          * Characters to ignore
13408          */
13409 @@ -711,6 +970,11 @@
13410                 clk_enable(atmel_port->clk);
13411                 port->uartclk = clk_get_rate(atmel_port->clk);
13412         }
13413 +
13414 +#ifdef SUPPORT_PDC
13415 +       atmel_port->use_dma_rx = data->use_dma_rx;
13416 +       atmel_port->use_dma_tx = data->use_dma_tx;
13417 +#endif
13418  }
13419
13420  /*
13421 diff -urN -x CVS linux-2.6.19-final/drivers/serial/atmel_serial.h linux-2.6.19/drivers/serial/atmel_serial.h
13422 --- linux-2.6.19-final/drivers/serial/atmel_serial.h    Mon Dec  4 16:40:48 2006
13423 +++ linux-2.6.19/drivers/serial/atmel_serial.h  Wed Nov  8 12:29:58 2006
13424 @@ -31,8 +31,8 @@
13425  #define                ATMEL_US_RSTIT          (1 << 13)               /* Reset Iterations */
13426  #define                ATMEL_US_RSTNACK        (1 << 14)               /* Reset Non Acknowledge */
13427  #define                ATMEL_US_RETTO          (1 << 15)               /* Rearm Time-out */
13428 -#define                ATMEL_US_DTREN          (1 << 16)               /* Data Terminal Ready Enable */
13429 -#define                ATMEL_US_DTRDIS         (1 << 17)               /* Data Terminal Ready Disable */
13430 +#define                ATMEL_US_DTREN          (1 << 16)               /* Data Terminal Ready Enable [AT91RM9200 only] */
13431 +#define                ATMEL_US_DTRDIS         (1 << 17)               /* Data Terminal Ready Disable [AT91RM9200 only] */
13432  #define                ATMEL_US_RTSEN          (1 << 18)               /* Request To Send Enable */
13433  #define                ATMEL_US_RTSDIS         (1 << 19)               /* Request To Send Disable */
13434
13435 @@ -92,9 +92,9 @@
13436  #define                ATMEL_US_TXBUFE         (1 << 11)               /* Transmission Buffer Empty */
13437  #define                ATMEL_US_RXBUFF         (1 << 12)               /* Reception Buffer Full */
13438  #define                ATMEL_US_NACK           (1 << 13)               /* Non Acknowledge */
13439 -#define                ATMEL_US_RIIC           (1 << 16)               /* Ring Indicator Input Change */
13440 -#define                ATMEL_US_DSRIC          (1 << 17)               /* Data Set Ready Input Change */
13441 -#define                ATMEL_US_DCDIC          (1 << 18)               /* Data Carrier Detect Input Change */
13442 +#define                ATMEL_US_RIIC           (1 << 16)               /* Ring Indicator Input Change [AT91RM9200 only] */
13443 +#define                ATMEL_US_DSRIC          (1 << 17)               /* Data Set Ready Input Change [AT91RM9200 only] */
13444 +#define                ATMEL_US_DCDIC          (1 << 18)               /* Data Carrier Detect Input Change [AT91RM9200 only] */
13445  #define                ATMEL_US_CTSIC          (1 << 19)               /* Clear to Send Input Change */
13446  #define                ATMEL_US_RI             (1 << 20)               /* RI */
13447  #define                ATMEL_US_DSR            (1 << 21)               /* DSR */
13448 @@ -106,6 +106,7 @@
13449  #define ATMEL_US_CSR           0x14                    /* Channel Status Register */
13450  #define ATMEL_US_RHR           0x18                    /* Receiver Holding Register */
13451  #define ATMEL_US_THR           0x1c                    /* Transmitter Holding Register */
13452 +#define        ATMEL_US_SYNH           (1 << 15)               /* Transmit/Receive Sync [AT91SAM9261 only] */
13453
13454  #define ATMEL_US_BRGR          0x20                    /* Baud Rate Generator Register */
13455  #define                ATMEL_US_CD             (0xffff << 0)           /* Clock Divider */
13456 diff -urN -x CVS linux-2.6.19-final/drivers/spi/Kconfig linux-2.6.19/drivers/spi/Kconfig
13457 --- linux-2.6.19-final/drivers/spi/Kconfig      Mon Dec  4 16:29:01 2006
13458 +++ linux-2.6.19/drivers/spi/Kconfig    Wed Nov 15 14:54:04 2006
13459 @@ -51,6 +51,13 @@
13460  comment "SPI Master Controller Drivers"
13461         depends on SPI_MASTER
13462
13463 +config SPI_ATMEL
13464 +       tristate "Atmel SPI Controller"
13465 +       depends on (ARCH_AT91 || AVR32) && SPI_MASTER
13466 +       help
13467 +         This selects a driver for the Atmel SPI Controller, present on
13468 +         many AT32 (AVR32) and AT91 (ARM) chips.
13469 +
13470  config SPI_BITBANG
13471         tristate "Bitbanging SPI master"
13472         depends on SPI_MASTER && EXPERIMENTAL
13473 @@ -75,6 +82,25 @@
13474           inexpensive battery powered microcontroller evaluation board.
13475           This same cable can be used to flash new firmware.
13476
13477 +config SPI_AT91
13478 +       tristate "AT91 SPI Master"
13479 +       depends on SPI_MASTER && ARCH_AT91 && !SPI_ATMEL && EXPERIMENTAL
13480 +       select SPI_BITBANG
13481 +       select SPI_AT91_MANUAL_CS
13482 +       help
13483 +         This is dumb PIO bitbanging driver for the Atmel
13484 +         AT91RM9200 and AT91SAM926x processors.
13485 +         (Someone should provide a drop-in replacemnt of this code,
13486 +         using the native SPI hardware and its DMA controller).
13487 +
13488 +config SPI_AT91_MANUAL_CS
13489 +       bool
13490 +       depends on ARCH_AT91RM9200
13491 +       help
13492 +         Works around an AT91RM9200 problem whereby the SPI chip-select
13493 +         will be wrongly disabled.  The workaround uses those pins as
13494 +         GPIOs instead of letting the SPI controller manage them.
13495 +
13496  config SPI_MPC83xx
13497         tristate "Freescale MPC83xx SPI controller"
13498         depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
13499 diff -urN -x CVS linux-2.6.19-final/drivers/spi/Makefile linux-2.6.19/drivers/spi/Makefile
13500 --- linux-2.6.19-final/drivers/spi/Makefile     Mon Dec  4 16:29:01 2006
13501 +++ linux-2.6.19/drivers/spi/Makefile   Wed Nov 15 14:54:35 2006
13502 @@ -17,6 +17,8 @@
13503  obj-$(CONFIG_SPI_MPC83xx)              += spi_mpc83xx.o
13504  obj-$(CONFIG_SPI_S3C24XX_GPIO)         += spi_s3c24xx_gpio.o
13505  obj-$(CONFIG_SPI_S3C24XX)              += spi_s3c24xx.o
13506 +obj-$(CONFIG_SPI_AT91)                 += spi_at91_bitbang.o
13507 +obj-$(CONFIG_SPI_ATMEL)                        += atmel_spi.o
13508  #      ... add above this line ...
13509
13510  # SPI protocol drivers (device/link on bus)
13511 diff -urN -x CVS linux-2.6.19-final/drivers/spi/atmel_spi.c linux-2.6.19/drivers/spi/atmel_spi.c
13512 --- linux-2.6.19-final/drivers/spi/atmel_spi.c  Thu Jan  1 02:00:00 1970
13513 +++ linux-2.6.19/drivers/spi/atmel_spi.c        Wed Nov 22 09:22:22 2006
13514 @@ -0,0 +1,684 @@
13515 +/*
13516 + * Driver for Atmel AT32 and AT91 SPI Controllers
13517 + *
13518 + * Copyright (C) 2006 Atmel Corporation
13519 + *
13520 + * This program is free software; you can redistribute it and/or modify
13521 + * it under the terms of the GNU General Public License version 2 as
13522 + * published by the Free Software Foundation.
13523 + */
13524 +
13525 +#include <linux/kernel.h>
13526 +#include <linux/init.h>
13527 +#include <linux/clk.h>
13528 +#include <linux/module.h>
13529 +#include <linux/platform_device.h>
13530 +#include <linux/delay.h>
13531 +#include <linux/dma-mapping.h>
13532 +#include <linux/err.h>
13533 +#include <linux/interrupt.h>
13534 +#include <linux/spi/spi.h>
13535 +
13536 +#include <asm/io.h>
13537 +#include <asm/arch/board.h>
13538 +#include <asm/arch/gpio.h>
13539 +#include <asm/arch/at91_pdc.h>
13540 +
13541 +#include "atmel_spi.h"
13542 +
13543 +#define spi_readl(port, reg)           __raw_readl((port)->regs + (reg))
13544 +#define spi_writel(port, reg, value)   __raw_writel((value), (port)->regs + (reg))
13545 +
13546 +/*
13547 + * The core SPI transfer engine just talks to a register bank to set up
13548 + * DMA transfers; transfer queue progress is driven by IRQs.  The clock
13549 + * framework provides the base clock, subdivided for each spi_device.
13550 + *
13551 + * Newer controllers, marked with "new_1" flag, have:
13552 + *  - CR.LASTXFER
13553 + *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
13554 + *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
13555 + *  - SPI_CSRx.CSAAT
13556 + *  - SPI_CSRx.SBCR allows faster clocking
13557 + */
13558 +struct atmel_spi {
13559 +       spinlock_t              lock;
13560 +
13561 +       void __iomem            *regs;
13562 +       int                     irq;
13563 +       struct clk              *clk;
13564 +       struct platform_device  *pdev;
13565 +       unsigned                new_1:1;
13566 +
13567 +       u8                      stopping;
13568 +       struct list_head        queue;
13569 +       struct spi_transfer     *current_transfer;
13570 +       unsigned long           remaining_bytes;
13571 +
13572 +       void                    *buffer;
13573 +       dma_addr_t              buffer_dma;
13574 +};
13575 +
13576 +#define BUFFER_SIZE            PAGE_SIZE
13577 +#define INVALID_DMA_ADDRESS    0xffffffff
13578 +
13579 +/*
13580 + * TODO: We really want to use the same GPIO API on both architectures.
13581 + */
13582 +#ifdef CONFIG_ARM
13583 +
13584 +static inline int request_gpio(unsigned int pin)
13585 +{
13586 +       return 0;
13587 +}
13588 +
13589 +static inline void free_gpio(unsigned int pin)
13590 +{
13591 +
13592 +}
13593 +
13594 +static inline void gpio_set_value(unsigned int pin, int value)
13595 +{
13596 +       at91_set_gpio_value(pin, value);
13597 +}
13598 +
13599 +static inline void gpio_set_output_enable(unsigned int pin, int enabled)
13600 +{
13601 +       at91_set_gpio_output(pin, enabled);
13602 +}
13603 +
13604 +static inline void gpio_set_pullup_enable(unsigned int pin, int enabled)
13605 +{
13606 +
13607 +}
13608 +#endif
13609 +
13610 +/*
13611 + * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
13612 + * they assume that spi slave device state will not change on deselect, so
13613 + * that automagic deselection is OK.  Not so!  Workaround uses nCSx pins
13614 + * as GPIOs; or newer controllers have CSAAT and friends.
13615 + *
13616 + * Since the CSAAT functionality is a bit weird on newer controllers
13617 + * as well, we use GPIO to control nCSx pins on all controllers.
13618 + */
13619 +
13620 +static inline void cs_activate(struct spi_device *spi)
13621 +{
13622 +       unsigned gpio = (unsigned) spi->controller_data;
13623 +
13624 +       dev_dbg(&spi->dev, "activate %u\n", gpio);
13625 +       gpio_set_value(gpio, 0);
13626 +}
13627 +
13628 +static inline void cs_deactivate(struct spi_device *spi)
13629 +{
13630 +       unsigned gpio = (unsigned) spi->controller_data;
13631 +
13632 +       dev_dbg(&spi->dev, "DEactivate %u\n", gpio);
13633 +       gpio_set_value(gpio, 1);
13634 +}
13635 +
13636 +/*
13637 + * Submit next transfer for DMA.
13638 + * lock is held, spi irq is blocked
13639 + */
13640 +static void atmel_spi_next_xfer(struct spi_master *master,
13641 +                               struct spi_message *msg)
13642 +{
13643 +       struct atmel_spi        *as = spi_master_get_devdata(master);
13644 +       struct spi_transfer     *xfer;
13645 +       u32                     imr = 0;
13646 +       u32                     len;
13647 +       dma_addr_t              tx_dma, rx_dma;
13648 +
13649 +       xfer = as->current_transfer;
13650 +       if (!xfer || as->remaining_bytes == 0) {
13651 +               if (xfer)
13652 +                       xfer = list_entry(xfer->transfer_list.next,
13653 +                                         struct spi_transfer, transfer_list);
13654 +               else
13655 +                       xfer = list_entry(msg->transfers.next, struct spi_transfer,
13656 +                                         transfer_list);
13657 +               as->remaining_bytes = xfer->len;
13658 +               as->current_transfer = xfer;
13659 +       }
13660 +
13661 +       len = as->remaining_bytes;
13662 +
13663 +       tx_dma = xfer->tx_dma;
13664 +       rx_dma = xfer->rx_dma;
13665 +
13666 +       if (rx_dma == INVALID_DMA_ADDRESS) {
13667 +               rx_dma = as->buffer_dma;
13668 +               if (len > BUFFER_SIZE)
13669 +                       len = BUFFER_SIZE;
13670 +       }
13671 +       if (tx_dma == INVALID_DMA_ADDRESS) {
13672 +               if (xfer->tx_buf) {
13673 +                       tx_dma = as->buffer_dma;
13674 +                       if (len > BUFFER_SIZE)
13675 +                               len = BUFFER_SIZE;
13676 +                       memcpy(as->buffer, xfer->tx_buf, len);
13677 +                       dma_sync_single_for_device(&as->pdev->dev,
13678 +                                                  as->buffer_dma, len,
13679 +                                                  DMA_TO_DEVICE);
13680 +               } else {
13681 +                       /* Send undefined data; rx_dma is handy */
13682 +                       tx_dma = rx_dma;
13683 +               }
13684 +       }
13685 +
13686 +       spi_writel(as, AT91_PDC_RPR, rx_dma);
13687 +       spi_writel(as, AT91_PDC_TPR, tx_dma);
13688 +
13689 +       as->remaining_bytes -= len;
13690 +       if (msg->spi->bits_per_word > 8)
13691 +               len >>= 1;
13692 +
13693 +       /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer"
13694 +        * mechanism might help avoid the IRQ latency between transfers
13695 +        *
13696 +        * We're also waiting for ENDRX before we start the next
13697 +        * transfer because we need to handle some difficult timing
13698 +        * issues otherwise. If we wait for ENDTX in one transfer and
13699 +        * then starts waiting for ENDRX in the next, it's difficult
13700 +        * to tell the difference between the ENDRX interrupt we're
13701 +        * actually waiting for and the ENDRX interrupt of the
13702 +        * previous transfer.
13703 +        *
13704 +        * It should be doable, though. Just not now...
13705 +        */
13706 +       spi_writel(as, AT91_PDC_TNCR, 0);
13707 +       spi_writel(as, AT91_PDC_RNCR, 0);
13708 +       imr = ATMEL_SPI_ENDRX;
13709 +
13710 +       dev_dbg(&msg->spi->dev,
13711 +               "start xfer %p: len %u tx %p/%08x rx %p/%08x imr %08x\n",
13712 +               xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
13713 +               xfer->rx_buf, xfer->rx_dma, imr);
13714 +
13715 +       wmb();
13716 +       spi_writel(as, AT91_PDC_TCR, len);
13717 +       spi_writel(as, AT91_PDC_RCR, len);
13718 +       spi_writel(as, AT91_PDC_PTCR, AT91_PDC_TXTEN | AT91_PDC_RXTEN);
13719 +       spi_writel(as, ATMEL_SPI_IER, imr);
13720 +}
13721 +
13722 +static void atmel_spi_next_message(struct spi_master *master)
13723 +{
13724 +       struct atmel_spi        *as = spi_master_get_devdata(master);
13725 +       struct spi_message      *msg;
13726 +       u32                     mr;
13727 +
13728 +       BUG_ON(as->current_transfer);
13729 +
13730 +       msg = list_entry(as->queue.next, struct spi_message, queue);
13731 +
13732 +       /* Select the chip */
13733 +       mr = spi_readl(as, ATMEL_SPI_MR) & ~ATMEL_SPI_PCS;
13734 +       spi_writel(as, ATMEL_SPI_MR, mr | ATMEL_SPI_PCS_(msg->spi->chip_select));
13735 +       cs_activate(msg->spi);
13736 +
13737 +       atmel_spi_next_xfer(master, msg);
13738 +}
13739 +
13740 +static void atmel_spi_dma_map_xfer(struct atmel_spi *as,
13741 +                                  struct spi_transfer *xfer)
13742 +{
13743 +       xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
13744 +       if (!(xfer->len & (L1_CACHE_BYTES - 1))) {
13745 +               if (xfer->tx_buf
13746 +                   && !((unsigned long)xfer->tx_buf & (L1_CACHE_BYTES - 1)))
13747 +                       xfer->tx_dma = dma_map_single(&as->pdev->dev,
13748 +                                                     xfer->tx_buf,
13749 +                                                     xfer->len,
13750 +                                                     DMA_TO_DEVICE);
13751 +               if (xfer->rx_buf
13752 +                   && !((unsigned long)xfer->rx_buf & (L1_CACHE_BYTES - 1)))
13753 +                       xfer->rx_dma = dma_map_single(&as->pdev->dev,
13754 +                                                     xfer->rx_buf,
13755 +                                                     xfer->len,
13756 +                                                     DMA_FROM_DEVICE);
13757 +       }
13758 +}
13759 +
13760 +static irqreturn_t
13761 +atmel_spi_interrupt(int irq, void *dev_id)
13762 +{
13763 +       struct spi_master       *master = dev_id;
13764 +       struct atmel_spi        *as = spi_master_get_devdata(master);
13765 +       struct spi_message      *msg;
13766 +       struct spi_transfer     *xfer;
13767 +       u32                     status, pending, imr;
13768 +       int                     ret = IRQ_NONE;
13769 +
13770 +       imr = spi_readl(as, ATMEL_SPI_IMR);
13771 +       status = spi_readl(as, ATMEL_SPI_SR);
13772 +       pending = status & imr;
13773 +       pr_debug("spi irq: stat %05x imr %05x pend %05x\n", status, imr, pending);
13774 +
13775 +       if (pending & (ATMEL_SPI_ENDTX | ATMEL_SPI_ENDRX)) {
13776 +               ret = IRQ_HANDLED;
13777 +
13778 +               spi_writel(as, ATMEL_SPI_IDR, pending);
13779 +               spin_lock(&as->lock);
13780 +
13781 +               xfer = as->current_transfer;
13782 +               msg = list_entry(as->queue.next, struct spi_message, queue);
13783 +
13784 +               /*
13785 +                * If the rx buffer wasn't aligned, we used a bounce
13786 +                * buffer for the transfer. Copy the data back and
13787 +                * make the bounce buffer ready for re-use.
13788 +                */
13789 +               if (xfer->rx_buf && xfer->rx_dma == INVALID_DMA_ADDRESS) {
13790 +                       unsigned int len = xfer->len;
13791 +                       if (len > BUFFER_SIZE)
13792 +                               len = BUFFER_SIZE;
13793 +
13794 +                       dma_sync_single_for_cpu(&as->pdev->dev, as->buffer_dma,
13795 +                                               len, DMA_FROM_DEVICE);
13796 +                       memcpy((xfer->rx_buf + xfer->len
13797 +                               - len - as->remaining_bytes),
13798 +                              as->buffer, len);
13799 +               }
13800 +
13801 +
13802 +               if (as->remaining_bytes == 0) {
13803 +                       msg->actual_length += xfer->len;
13804 +
13805 +                       if (!msg->is_dma_mapped) {
13806 +                               if (xfer->tx_dma != INVALID_DMA_ADDRESS)
13807 +                                       dma_unmap_single(master->cdev.dev,
13808 +                                                        xfer->tx_dma,
13809 +                                                        xfer->len,
13810 +                                                        DMA_TO_DEVICE);
13811 +                               if (xfer->rx_dma != INVALID_DMA_ADDRESS)
13812 +                                       dma_unmap_single(master->cdev.dev,
13813 +                                                        xfer->rx_dma,
13814 +                                                        xfer->len,
13815 +                                                        DMA_FROM_DEVICE);
13816 +                       }
13817 +
13818 +                       /* REVISIT: udelay in irq is unfriendly */
13819 +                       if (xfer->delay_usecs)
13820 +                               udelay(xfer->delay_usecs);
13821 +
13822 +                       if (msg->transfers.prev == &xfer->transfer_list) {
13823 +
13824 +                               /* report completed message */
13825 +                               cs_deactivate(msg->spi);
13826 +                               list_del(&msg->queue);
13827 +                               msg->status = 0;
13828 +
13829 +                               dev_dbg(master->cdev.dev,
13830 +                                       "xfer complete: %u bytes transferred\n",
13831 +                                       msg->actual_length);
13832 +
13833 +                               spin_unlock(&as->lock);
13834 +                               msg->complete(msg->context);
13835 +                               spin_lock(&as->lock);
13836 +
13837 +                               as->current_transfer = NULL;
13838 +
13839 +                               /* continue; complete() may have queued requests */
13840 +                               if (list_empty(&as->queue) || as->stopping)
13841 +                                       spi_writel(as, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
13842 +                               else
13843 +                                       atmel_spi_next_message(master);
13844 +                       } else {
13845 +                               if (xfer->cs_change) {
13846 +                                       cs_deactivate(msg->spi);
13847 +                                       udelay(1);
13848 +                                       cs_activate(msg->spi);
13849 +                               }
13850 +
13851 +                               /*
13852 +                                * Not done yet. Submit the next transfer.
13853 +                                *
13854 +                                * FIXME handle protocol options for xfer
13855 +                                */
13856 +                               atmel_spi_next_xfer(master, msg);
13857 +                       }
13858 +               } else {
13859 +                       /*
13860 +                        * Keep going, we still have data to send in
13861 +                        * the current transfer.
13862 +                        */
13863 +                       atmel_spi_next_xfer(master, msg);
13864 +               }
13865 +               spin_unlock(&as->lock);
13866 +       }
13867 +
13868 +       return ret;
13869 +}
13870 +
13871 +#define MAX_SCBR       0xff
13872 +
13873 +static int atmel_spi_setup(struct spi_device *spi)
13874 +{
13875 +       struct atmel_spi        *as;
13876 +       u32                     scbr, csr;
13877 +       unsigned int            bits = spi->bits_per_word;
13878 +       unsigned long           bus_hz, sck_hz;
13879 +       unsigned int            npcs_pin;
13880 +       int                     ret;
13881 +
13882 +       as = spi_master_get_devdata(spi->master);
13883 +
13884 +       if (as->stopping)
13885 +               return -ESHUTDOWN;
13886 +
13887 +       if (spi->chip_select > spi->master->num_chipselect) {
13888 +               dev_dbg(&spi->dev,
13889 +                               "setup: invalid chipselect %u (%u defined)\n",
13890 +                               spi->chip_select, spi->master->num_chipselect);
13891 +               return -EINVAL;
13892 +       }
13893 +
13894 +       if (bits == 0)
13895 +               bits = 8;
13896 +       if (bits < 8 || bits > 16) {
13897 +               dev_dbg(&spi->dev,
13898 +                               "setup: invalid bits_per_word %u (8 to 16)\n",
13899 +                               bits);
13900 +               return -EINVAL;
13901 +       }
13902 +
13903 +       if (spi->mode & (SPI_CS_HIGH | SPI_LSB_FIRST)) {
13904 +               dev_dbg(&spi->dev, "setup: unsupported mode %u\n", spi->mode);
13905 +               return -EINVAL;
13906 +       }
13907 +
13908 +       /* speed zero convention is used by some upper layers */
13909 +       bus_hz = clk_get_rate(as->clk);
13910 +       if (spi->max_speed_hz) {
13911 +               /* assume div32/fdiv/mbz == 0 */
13912 +               if (!as->new_1)
13913 +                       bus_hz /= 2;
13914 +               scbr = ((bus_hz + spi->max_speed_hz - 1)
13915 +                       / spi->max_speed_hz);
13916 +               if (scbr > MAX_SCBR) {
13917 +                       dev_dbg(&spi->dev, "setup: %d Hz too slow, scbr %u\n",
13918 +                                       spi->max_speed_hz, scbr);
13919 +                       return -EINVAL;
13920 +               }
13921 +       } else
13922 +               scbr = 0xff;
13923 +       sck_hz = bus_hz / scbr;
13924 +
13925 +       csr = ATMEL_SPI_SCBR_(scbr) | ATMEL_SPI_BITS_(bits);
13926 +       if (spi->mode & SPI_CPOL)
13927 +               csr |= ATMEL_SPI_CPOL;
13928 +       if (!(spi->mode & SPI_CPHA))
13929 +               csr |= ATMEL_SPI_NCPHA;
13930 +
13931 +       /* TODO: DLYBS and DLYBCT */
13932 +       csr |= ATMEL_SPI_DLYBS_(10);
13933 +       csr |= ATMEL_SPI_DLYBCT_(10);
13934 +
13935 +       npcs_pin = (unsigned int)spi->controller_data;
13936 +       if (!spi->controller_state) {
13937 +               ret = request_gpio(npcs_pin);
13938 +               if (ret)
13939 +                       return ret;
13940 +               spi->controller_state = (void *)npcs_pin;
13941 +       }
13942 +
13943 +       gpio_set_value(npcs_pin, 1);
13944 +       gpio_set_output_enable(npcs_pin, 1);
13945 +       gpio_set_pullup_enable(npcs_pin, 0);
13946 +
13947 +       dev_dbg(&spi->dev,
13948 +               "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
13949 +               sck_hz, bits, spi->mode, spi->chip_select, csr);
13950 +
13951 +       spi_writel(as, ATMEL_SPI_CSR(spi->chip_select), csr);
13952 +
13953 +       return 0;
13954 +}
13955 +
13956 +static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
13957 +{
13958 +       struct atmel_spi        *as;
13959 +       struct spi_transfer     *xfer;
13960 +       unsigned long           flags;
13961 +       struct device           *controller = spi->master->cdev.dev;
13962 +
13963 +       as = spi_master_get_devdata(spi->master);
13964 +
13965 +       dev_dbg(controller, "new message %p submitted for %s\n",
13966 +                       msg, spi->dev.bus_id);
13967 +
13968 +       if (unlikely(list_empty(&msg->transfers)
13969 +                       || !spi->max_speed_hz))
13970 +               return -EINVAL;
13971 +
13972 +       if (as->stopping)
13973 +               return -ESHUTDOWN;
13974 +
13975 +       list_for_each_entry(xfer, &msg->transfers, transfer_list) {
13976 +               if (!(xfer->tx_buf || xfer->rx_buf)) {
13977 +                       dev_dbg(&spi->dev, "missing rx or tx buf\n");
13978 +                       return -EINVAL;
13979 +               }
13980 +
13981 +               /* FIXME implement these protocol options!! */
13982 +               if (xfer->bits_per_word || xfer->speed_hz) {
13983 +                       dev_dbg(&spi->dev, "no protocol options yet\n");
13984 +                       return -ENOPROTOOPT;
13985 +               }
13986 +       }
13987 +
13988 +       /* scrub dcache "early" */
13989 +       if (!msg->is_dma_mapped) {
13990 +               list_for_each_entry(xfer, &msg->transfers, transfer_list)
13991 +                       atmel_spi_dma_map_xfer(as, xfer);
13992 +       }
13993 +
13994 +       list_for_each_entry(xfer, &msg->transfers, transfer_list) {
13995 +               dev_dbg(controller,
13996 +                       "  xfer %p: len %u tx %p/%08x rx %p/%08x\n",
13997 +                       xfer, xfer->len,
13998 +                       xfer->tx_buf, xfer->tx_dma,
13999 +                       xfer->rx_buf, xfer->rx_dma);
14000 +       }
14001 +
14002 +       msg->status = -EINPROGRESS;
14003 +       msg->actual_length = 0;
14004 +
14005 +       spin_lock_irqsave(&as->lock, flags);
14006 +       list_add_tail(&msg->queue, &as->queue);
14007 +       if (!as->current_transfer)
14008 +               atmel_spi_next_message(spi->master);
14009 +       spin_unlock_irqrestore(&as->lock, flags);
14010 +
14011 +       return 0;
14012 +}
14013 +
14014 +static void atmel_spi_cleanup(const struct spi_device *spi)
14015 +{
14016 +       if (spi->controller_state)
14017 +               free_gpio((unsigned int)spi->controller_data);
14018 +}
14019 +
14020 +/*-------------------------------------------------------------------------*/
14021 +
14022 +static int __devinit atmel_spi_probe(struct platform_device *pdev)
14023 +{
14024 +       struct resource         *regs;
14025 +       int                     irq;
14026 +       struct clk              *clk;
14027 +       int                     ret = -ENOMEM;
14028 +       struct spi_master       *master;
14029 +       struct atmel_spi        *as;
14030 +
14031 +       regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
14032 +       if (!regs)
14033 +               return -ENXIO;
14034 +
14035 +       irq = platform_get_irq(pdev, 0);
14036 +       if (irq < 0)
14037 +               return irq;
14038 +
14039 +       clk = clk_get(&pdev->dev, "spi_clk");
14040 +       if (IS_ERR(clk))
14041 +               return PTR_ERR(clk);
14042 +
14043 +       /* setup spi core then atmel-specific driver state */
14044 +       master = spi_alloc_master(&pdev->dev, sizeof *as);
14045 +       if (!master)
14046 +               goto out_free;
14047 +
14048 +       master->bus_num = pdev->id;
14049 +       master->num_chipselect = 4;
14050 +       master->setup = atmel_spi_setup;
14051 +       master->transfer = atmel_spi_transfer;
14052 +       master->cleanup = atmel_spi_cleanup;
14053 +       platform_set_drvdata(pdev, master);
14054 +
14055 +       as = spi_master_get_devdata(master);
14056 +
14057 +       as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
14058 +                                       &as->buffer_dma, GFP_KERNEL);
14059 +       if (!as->buffer)
14060 +               goto out_free;
14061 +
14062 +       spin_lock_init(&as->lock);
14063 +       INIT_LIST_HEAD(&as->queue);
14064 +       as->pdev = pdev;
14065 +       as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
14066 +       if (!as->regs)
14067 +               goto out_free_buffer;
14068 +       as->irq = irq;
14069 +       as->clk = clk;
14070 +#if !defined(CONFIG_ARCH_AT91RM9200)
14071 +       /* if (!cpu_is_at91rm9200()) */
14072 +               as->new_1 = 1;
14073 +#endif
14074 +
14075 +       ret = request_irq(irq, atmel_spi_interrupt, 0,
14076 +                       pdev->dev.bus_id, master);
14077 +       if (ret)
14078 +               goto out_unmap_regs;
14079 +
14080 +       /* Initialize the hardware */
14081 +       clk_enable(clk);
14082 +       spi_writel(as, ATMEL_SPI_CR, ATMEL_SPI_SWRST);
14083 +       spi_writel(as, ATMEL_SPI_MR, ATMEL_SPI_MSTR | ATMEL_SPI_MODFDIS);
14084 +       spi_writel(as, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
14085 +       spi_writel(as, ATMEL_SPI_CR, ATMEL_SPI_SPIEN);
14086 +
14087 +       /* go! */
14088 +       dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
14089 +                       (unsigned long)regs->start, irq);
14090 +
14091 +       ret = spi_register_master(master);
14092 +       if (ret)
14093 +               goto out_reset_hw;
14094 +
14095 +       return 0;
14096 +
14097 +out_reset_hw:
14098 +       spi_writel(as, ATMEL_SPI_CR, ATMEL_SPI_SWRST);
14099 +       clk_disable(clk);
14100 +       free_irq(irq, master);
14101 +out_unmap_regs:
14102 +       iounmap(as->regs);
14103 +out_free_buffer:
14104 +       dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
14105 +                         as->buffer_dma);
14106 +out_free:
14107 +       clk_put(clk);
14108 +       spi_master_put(master);
14109 +       return ret;
14110 +}
14111 +
14112 +static int __devexit atmel_spi_remove(struct platform_device *pdev)
14113 +{
14114 +       struct spi_master       *master = platform_get_drvdata(pdev);
14115 +       struct atmel_spi        *as = spi_master_get_devdata(master);
14116 +       struct spi_message      *msg;
14117 +
14118 +       /* reset the hardware and block queue progress */
14119 +       spin_lock_irq(&as->lock);
14120 +       as->stopping = 1;
14121 +       spi_writel(as, ATMEL_SPI_CR, ATMEL_SPI_SWRST);
14122 +       spi_readl(as, ATMEL_SPI_SR);
14123 +       spin_unlock_irq(&as->lock);
14124 +
14125 +       /* Terminate remaining queued transfers */
14126 +       list_for_each_entry(msg, &as->queue, queue) {
14127 +               /* REVISIT unmapping the dma is sort of a NOP on ARM,
14128 +                * but we shouldn't depend on that...
14129 +                */
14130 +               msg->status = -ESHUTDOWN;
14131 +               msg->complete(msg->context);
14132 +       }
14133 +
14134 +       dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
14135 +                         as->buffer_dma);
14136 +
14137 +       clk_disable(as->clk);
14138 +       clk_put(as->clk);
14139 +       free_irq(as->irq, master);
14140 +       iounmap(as->regs);
14141 +
14142 +       spi_unregister_master(master);
14143 +
14144 +       return 0;
14145 +}
14146 +
14147 +#ifdef CONFIG_PM
14148 +
14149 +static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
14150 +{
14151 +       struct spi_master       *master = platform_get_drvdata(pdev);
14152 +       struct atmel_spi        *as = spi_master_get_devdata(master);
14153 +
14154 +       clk_disable(as->clk);
14155 +       return 0;
14156 +}
14157 +
14158 +static int atmel_spi_resume(struct platform_device *pdev)
14159 +{
14160 +       struct spi_master       *master = platform_get_drvdata(pdev);
14161 +       struct atmel_spi        *as = spi_master_get_devdata(master);
14162 +
14163 +       clk_enable(as->clk);
14164 +       return 0;
14165 +}
14166 +
14167 +#else
14168 +#define        atmel_spi_suspend       NULL
14169 +#define        atmel_spi_resume        NULL
14170 +#endif
14171 +
14172 +
14173 +static struct platform_driver atmel_spi_driver = {
14174 +       .driver         = {
14175 +               .name   = "atmel_spi",
14176 +               .owner  = THIS_MODULE,
14177 +       },
14178 +       .probe          = atmel_spi_probe,
14179 +       .suspend        = atmel_spi_suspend,
14180 +       .resume         = atmel_spi_resume,
14181 +       .remove         = __devexit_p(atmel_spi_remove),
14182 +};
14183 +
14184 +static int __init atmel_spi_init(void)
14185 +{
14186 +       return platform_driver_register(&atmel_spi_driver);
14187 +}
14188 +module_init(atmel_spi_init);
14189 +
14190 +static void __exit atmel_spi_exit(void)
14191 +{
14192 +       platform_driver_unregister(&atmel_spi_driver);
14193 +}
14194 +module_exit(atmel_spi_exit);
14195 +
14196 +MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
14197 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
14198 +MODULE_LICENSE("GPL");
14199 diff -urN -x CVS linux-2.6.19-final/drivers/spi/atmel_spi.h linux-2.6.19/drivers/spi/atmel_spi.h
14200 --- linux-2.6.19-final/drivers/spi/atmel_spi.h  Thu Jan  1 02:00:00 1970
14201 +++ linux-2.6.19/drivers/spi/atmel_spi.h        Wed Nov 15 16:40:00 2006
14202 @@ -0,0 +1,86 @@
14203 +/*
14204 + * drivers/spi/atmel_spi.h
14205 + *
14206 + * Copyright (C) 2005 Ivan Kokshaysky
14207 + * Copyright (C) SAN People
14208 + *
14209 + * Serial Peripheral Interface (SPI) registers.
14210 + * Based on AT91RM9200 datasheet revision E.
14211 + *
14212 + * This program is free software; you can redistribute it and/or modify
14213 + * it under the terms of the GNU General Public License as published by
14214 + * the Free Software Foundation; either version 2 of the License, or
14215 + * (at your option) any later version.
14216 + */
14217 +
14218 +#ifndef ATMEL_SPI_H
14219 +#define ATMEL_SPI_H
14220 +
14221 +#define ATMEL_SPI_CR           0x00            /* Control Register */
14222 +#define                ATMEL_SPI_SPIEN         (1 <<  0)               /* SPI Enable */
14223 +#define                ATMEL_SPI_SPIDIS        (1 <<  1)               /* SPI Disable */
14224 +#define                ATMEL_SPI_SWRST         (1 <<  7)               /* SPI Software Reset */
14225 +#define                ATMEL_SPI_LASTXFER      (1 << 24)               /* Last Transfer [SAM9261 only] */
14226 +
14227 +#define ATMEL_SPI_MR           0x04            /* Mode Register */
14228 +#define                ATMEL_SPI_MSTR          (1    <<  0)            /* Master/Slave Mode */
14229 +#define                ATMEL_SPI_PS            (1    <<  1)            /* Peripheral Select */
14230 +#define                        ATMEL_SPI_PS_FIXED      (0 << 1)
14231 +#define                        ATMEL_SPI_PS_VARIABLE   (1 << 1)
14232 +#define                ATMEL_SPI_PCSDEC        (1    <<  2)            /* Chip Select Decode */
14233 +#define                ATMEL_SPI_DIV32         (1    <<  3)            /* Clock Selection [AT91RM9200 only] */
14234 +#define                ATMEL_SPI_MODFDIS       (1    <<  4)            /* Mode Fault Detection */
14235 +#define                ATMEL_SPI_LLB           (1    <<  7)            /* Local Loopback Enable */
14236 +#define                ATMEL_SPI_PCS           (0xf  << 16)            /* Peripheral Chip Select */
14237 +#define                        ATMEL_SPI_PCS_(x)       (~(1 << (x+16)) & ATMEL_SPI_PCS)
14238 +#define                ATMEL_SPI_DLYBCS        (0xff << 24)            /* Delay Between Chip Selects */
14239 +
14240 +#define ATMEL_SPI_RDR          0x08                    /* Receive Data Register */
14241 +#define                ATMEL_SPI_RD            (0xffff <<  0)          /* Receive Data */
14242 +#define                ATMEL_SPI_PCS           (0xf    << 16)          /* Peripheral Chip Select */
14243 +
14244 +#define ATMEL_SPI_TDR          0x0c                    /* Transmit Data Register */
14245 +#define                ATMEL_SPI_TD            (0xffff <<  0)          /* Transmit Data */
14246 +#define                ATMEL_SPI_PCS           (0xf    << 16)          /* Peripheral Chip Select */
14247 +#define                ATMEL_SPI_LASTXFER      (1      << 24)          /* Last Transfer [SAM9261 only] */
14248 +
14249 +#define ATMEL_SPI_SR           0x10                    /* Status Register */
14250 +#define                ATMEL_SPI_RDRF          (1 <<  0)               /* Receive Data Register Full */
14251 +#define                ATMEL_SPI_TDRE          (1 <<  1)               /* Transmit Data Register Full */
14252 +#define                ATMEL_SPI_MODF          (1 <<  2)               /* Mode Fault Error */
14253 +#define                ATMEL_SPI_OVRES         (1 <<  3)               /* Overrun Error Status */
14254 +#define                ATMEL_SPI_ENDRX         (1 <<  4)               /* End of RX buffer */
14255 +#define                ATMEL_SPI_ENDTX         (1 <<  5)               /* End of TX buffer */
14256 +#define                ATMEL_SPI_RXBUFF        (1 <<  6)               /* RX Buffer Full */
14257 +#define                ATMEL_SPI_TXBUFE        (1 <<  7)               /* TX Buffer Empty */
14258 +#define                ATMEL_SPI_NSSR          (1 <<  8)               /* NSS Rising [SAM9261 only] */
14259 +#define                ATMEL_SPI_TXEMPTY       (1 <<  9)               /* Transmission Register Empty [SAM9261 only] */
14260 +#define                ATMEL_SPI_SPIENS        (1 << 16)               /* SPI Enable Status */
14261 +
14262 +#define ATMEL_SPI_IER          0x14                    /* Interrupt Enable Register */
14263 +#define ATMEL_SPI_IDR          0x18                    /* Interrupt Disable Register */
14264 +#define ATMEL_SPI_IMR          0x1c                    /* Interrupt Mask Register */
14265 +
14266 +#define ATMEL_SPI_CSR(n)       (0x30 + ((n) * 4))      /* Chip Select Registers 0-3 */
14267 +#define                ATMEL_SPI_CPOL          (1    <<  0)            /* Clock Polarity */
14268 +#define                ATMEL_SPI_NCPHA         (1    <<  1)            /* Clock Phase */
14269 +#define                ATMEL_SPI_CSAAT         (1    <<  3)            /* Chip Select Active After Transfer [SAM9261 only] */
14270 +#define                ATMEL_SPI_BITS          (0xf  <<  4)            /* Bits Per Transfer */
14271 +#define                        ATMEL_SPI_BITS_8        (0 << 4)
14272 +#define                        ATMEL_SPI_BITS_9        (1 << 4)
14273 +#define                        ATMEL_SPI_BITS_10       (2 << 4)
14274 +#define                        ATMEL_SPI_BITS_11       (3 << 4)
14275 +#define                        ATMEL_SPI_BITS_12       (4 << 4)
14276 +#define                        ATMEL_SPI_BITS_13       (5 << 4)
14277 +#define                        ATMEL_SPI_BITS_14       (6 << 4)
14278 +#define                        ATMEL_SPI_BITS_15       (7 << 4)
14279 +#define                        ATMEL_SPI_BITS_16       (8 << 4)
14280 +#define                        ATMEL_SPI_BITS_(x)      ((x - 8) << 4)
14281 +#define                ATMEL_SPI_SCBR          (0xff <<  8)            /* Serial Clock Baud Rate */
14282 +#define                        ATMEL_SPI_SCBR_(x)      ((x) << 8)
14283 +#define                ATMEL_SPI_DLYBS         (0xff << 16)            /* Delay before SPCK */
14284 +#define                        ATMEL_SPI_DLYBS_(x)     ((x) << 16)
14285 +#define                ATMEL_SPI_DLYBCT        (0xff << 24)            /* Delay between Consecutive Transfers */
14286 +#define                        ATMEL_SPI_DLYBCT_(x)    ((x) << 24)
14287 +
14288 +#endif
14289 diff -urN -x CVS linux-2.6.19-final/drivers/spi/spi_at91_bitbang.c linux-2.6.19/drivers/spi/spi_at91_bitbang.c
14290 --- linux-2.6.19-final/drivers/spi/spi_at91_bitbang.c   Thu Jan  1 02:00:00 1970
14291 +++ linux-2.6.19/drivers/spi/spi_at91_bitbang.c Thu Oct 12 17:07:39 2006
14292 @@ -0,0 +1,207 @@
14293 +/*
14294 + * at91_spi.c - at91 SPI driver (BOOTSTRAP/BITBANG VERSION)
14295 + *
14296 + * Copyright (C) 2006 David Brownell
14297 + *
14298 + * This program is free software; you can redistribute it and/or modify
14299 + * it under the terms of the GNU General Public License as published by
14300 + * the Free Software Foundation; either version 2 of the License, or
14301 + * (at your option) any later version.
14302 + *
14303 + * This program is distributed in the hope that it will be useful,
14304 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
14305 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14306 + * GNU General Public License for more details.
14307 + *
14308 + * You should have received a copy of the GNU General Public License
14309 + * along with this program; if not, write to the Free Software
14310 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
14311 + */
14312 +#include <linux/kernel.h>
14313 +#include <linux/init.h>
14314 +#include <linux/platform_device.h>
14315 +
14316 +#include <linux/spi/spi.h>
14317 +#include <linux/spi/spi_bitbang.h>
14318 +
14319 +#include <asm/arch/gpio.h>
14320 +
14321 +
14322 +/*
14323 + * FIXME this bitbanging version is just to help bootstrap systems until
14324 + * there's a native SPI+IRQ+DMA controller driver ... such a driver should
14325 + * be a drop-in replacement for this one, and much faster.
14326 + *
14327 + * remember:
14328 + *
14329 + *     - other at91 parts (like at91sam9) have multiple controllers
14330 + *       and different pin muxing; this version is at91rm9200 specfic.
14331 + *
14332 + *     - at91sam9261 SPI0 pins are directly muxed with MMC/SD pins.
14333 + *
14334 + *     - rm9200 spi chipselects drop wrongly, so the native driver
14335 + *       will need to use gpios much like this does.
14336 + *
14337 + *     - real hardware only allows 8..16 bits per word, while this
14338 + *       bitbanger allows 1..32 (incompatible superset).
14339 + *
14340 + *     - this disregards clock parameters.  with inlined gpio calls,
14341 + *       gcc 3.4.4 produces about 1.5 mbit/sec, more than 2x faster
14342 + *       than using the subroutined veresion from txrx_word().
14343 + *
14344 + *     - suspend/resume and <linux/clk.h> support is missing ...
14345 + */
14346 +
14347 +#define        spi_miso_bit    AT91_PIN_PA0
14348 +#define        spi_mosi_bit    AT91_PIN_PA1
14349 +#define        spi_sck_bit     AT91_PIN_PA2
14350 +
14351 +struct at91_spi {
14352 +       struct spi_bitbang      bitbang;
14353 +       struct platform_device  *pdev;
14354 +};
14355 +
14356 +/*----------------------------------------------------------------------*/
14357 +
14358 +static inline void setsck(struct spi_device *spi, int is_on)
14359 +{
14360 +       at91_set_gpio_value(spi_sck_bit, is_on);
14361 +}
14362 +
14363 +static inline void setmosi(struct spi_device *spi, int is_on)
14364 +{
14365 +       at91_set_gpio_value(spi_mosi_bit, is_on);
14366 +}
14367 +
14368 +static inline int getmiso(struct spi_device *spi)
14369 +{
14370 +       return at91_get_gpio_value(spi_miso_bit);
14371 +}
14372 +
14373 +static void at91_spi_chipselect(struct spi_device *spi, int is_active)
14374 +{
14375 +       unsigned long cs = (unsigned long) spi->controller_data;
14376 +
14377 +       /* set default clock polarity */
14378 +       if (is_active)
14379 +               setsck(spi, spi->mode & SPI_CPOL);
14380 +
14381 +       /* only support active-low (default) */
14382 +       at91_set_gpio_value(cs, !is_active);
14383 +}
14384 +
14385 +/*
14386 + * NOTE:  this is "as fast as we can"; it should be a function of
14387 + * the device clock ...
14388 + */
14389 +#define        spidelay(X)     do{} while(0)
14390 +
14391 +#define        EXPAND_BITBANG_TXRX
14392 +#include <linux/spi/spi_bitbang.h>
14393 +
14394 +static u32 at91_spi_txrx_word_mode0(struct spi_device *spi,
14395 +               unsigned nsecs, u32 word, u8 bits)
14396 +{
14397 +       return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, 8);
14398 +}
14399 +
14400 +static u32 at91_spi_txrx_word_mode1(struct spi_device *spi,
14401 +               unsigned nsecs, u32 word, u8 bits)
14402 +{
14403 +       return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, 8);
14404 +}
14405 +
14406 +static u32 at91_spi_txrx_word_mode2(struct spi_device *spi,
14407 +               unsigned nsecs, u32 word, u8 bits)
14408 +{
14409 +       return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, 8);
14410 +}
14411 +
14412 +static u32 at91_spi_txrx_word_mode3(struct spi_device *spi,
14413 +               unsigned nsecs, u32 word, u8 bits)
14414 +{
14415 +       return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, 8);
14416 +}
14417 +
14418 +/*----------------------------------------------------------------------*/
14419 +
14420 +static int __init at91_spi_probe(struct platform_device *pdev)
14421 +{
14422 +       int                     status;
14423 +       struct spi_master       *master;
14424 +       struct at91_spi         *at91_spi;
14425 +
14426 +       if (pdev->id != 0)      /* SPI0 bus */
14427 +               return -EINVAL;
14428 +
14429 +       master = spi_alloc_master(&pdev->dev, sizeof *at91_spi);
14430 +       if (!master)
14431 +               return -ENOMEM;
14432 +
14433 +       at91_spi = spi_master_get_devdata(master);
14434 +       at91_spi->pdev = pdev;
14435 +       platform_set_drvdata(pdev, at91_spi);
14436 +
14437 +       /* SPI and bitbang hookup */
14438 +       master->bus_num = 0;
14439 +       master->num_chipselect = 4;
14440 +
14441 +       at91_spi->bitbang.master = spi_master_get(master);
14442 +       at91_spi->bitbang.chipselect = at91_spi_chipselect;
14443 +       at91_spi->bitbang.txrx_word[SPI_MODE_0] = at91_spi_txrx_word_mode0;
14444 +       at91_spi->bitbang.txrx_word[SPI_MODE_1] = at91_spi_txrx_word_mode1;
14445 +       at91_spi->bitbang.txrx_word[SPI_MODE_2] = at91_spi_txrx_word_mode2;
14446 +       at91_spi->bitbang.txrx_word[SPI_MODE_3] = at91_spi_txrx_word_mode3;
14447 +
14448 +       status = spi_bitbang_start(&at91_spi->bitbang);
14449 +       if (status < 0)
14450 +               (void) spi_master_put(at91_spi->bitbang.master);
14451 +
14452 +       return status;
14453 +}
14454 +
14455 +static int __exit at91_spi_remove(struct platform_device *pdev)
14456 +{
14457 +       struct at91_spi *at91_spi = platform_get_drvdata(pdev);
14458 +       int status;
14459 +
14460 +       /* stop() unregisters child devices too */
14461 +       status = spi_bitbang_stop(&at91_spi->bitbang);
14462 +       (void) spi_master_put(at91_spi->bitbang.master);
14463 +
14464 +       platform_set_drvdata(pdev, NULL);
14465 +       return status;
14466 +}
14467 +
14468 +static struct platform_driver at91_spi_driver = {
14469 +       .probe          = at91_spi_probe,
14470 +       .remove         = __exit_p(at91_spi_remove),
14471 +       .driver         = {
14472 +               .name   = "at91_spi",
14473 +               .owner  = THIS_MODULE,
14474 +       },
14475 +};
14476 +
14477 +static int __init at91_spi_init(void)
14478 +{
14479 +       at91_set_gpio_output(spi_sck_bit, 0);
14480 +       at91_set_gpio_output(spi_mosi_bit, 0);
14481 +       at91_set_gpio_input(spi_miso_bit, 1 /* pullup */);
14482 +
14483 +       /* register driver */
14484 +       return platform_driver_register(&at91_spi_driver);
14485 +}
14486 +
14487 +static void __exit at91_spi_exit(void)
14488 +{
14489 +       platform_driver_unregister(&at91_spi_driver);
14490 +}
14491 +
14492 +device_initcall(at91_spi_init);
14493 +module_exit(at91_spi_exit);
14494 +
14495 +MODULE_ALIAS("at91_spi.0");
14496 +
14497 +MODULE_DESCRIPTION("AT91 SPI support (BOOTSTRAP/BITBANG VERSION)");
14498 +MODULE_AUTHOR("David Brownell");
14499 +MODULE_LICENSE("GPL");
14500 diff -urN -x CVS linux-2.6.19-final/drivers/usb/Kconfig linux-2.6.19/drivers/usb/Kconfig
14501 --- linux-2.6.19-final/drivers/usb/Kconfig      Mon Dec  4 16:40:49 2006
14502 +++ linux-2.6.19/drivers/usb/Kconfig    Thu Oct 12 17:07:39 2006
14503 @@ -24,7 +24,7 @@
14504         default y if ARCH_S3C2410
14505         default y if PXA27x
14506         default y if ARCH_EP93XX
14507 -       default y if (ARCH_AT91RM9200 || ARCH_AT91SAM9261)
14508 +       default y if ARCH_AT91
14509         default y if ARCH_PNX4008
14510         # PPC:
14511         default y if STB03xxx
14512 diff -urN -x CVS linux-2.6.19-final/drivers/usb/gadget/Kconfig linux-2.6.19/drivers/usb/gadget/Kconfig
14513 --- linux-2.6.19-final/drivers/usb/gadget/Kconfig       Mon Dec  4 16:40:49 2006
14514 +++ linux-2.6.19/drivers/usb/gadget/Kconfig     Thu Oct 12 17:07:39 2006
14515 @@ -189,7 +189,7 @@
14516
14517  config USB_GADGET_AT91
14518         boolean "AT91 USB Device Port"
14519 -       depends on ARCH_AT91RM9200
14520 +       depends on ARCH_AT91
14521         select USB_GADGET_SELECTED
14522         help
14523            Many Atmel AT91 processors (such as the AT91RM2000) have a
14524 diff -urN -x CVS linux-2.6.19-final/drivers/usb/gadget/at91_udc.c linux-2.6.19/drivers/usb/gadget/at91_udc.c
14525 --- linux-2.6.19-final/drivers/usb/gadget/at91_udc.c    Mon Dec  4 16:40:49 2006
14526 +++ linux-2.6.19/drivers/usb/gadget/at91_udc.c  Wed Nov 15 11:33:30 2006
14527 @@ -43,14 +43,16 @@
14528  #include <linux/usb_gadget.h>
14529
14530  #include <asm/byteorder.h>
14531 +#include <asm/hardware.h>
14532  #include <asm/io.h>
14533  #include <asm/irq.h>
14534  #include <asm/system.h>
14535  #include <asm/mach-types.h>
14536
14537 -#include <asm/arch/hardware.h>
14538  #include <asm/arch/gpio.h>
14539  #include <asm/arch/board.h>
14540 +#include <asm/arch/cpu.h>
14541 +#include <asm/arch/at91sam9261_matrix.h>
14542
14543  #include "at91_udc.h"
14544
14545 @@ -78,27 +80,9 @@
14546  static const char driver_name [] = "at91_udc";
14547  static const char ep0name[] = "ep0";
14548
14549 -/*-------------------------------------------------------------------------*/
14550
14551 -/*
14552 - * Read from a UDP register.
14553 - */
14554 -static inline unsigned long at91_udp_read(unsigned int reg)
14555 -{
14556 -       void __iomem *udp_base = (void __iomem *)AT91_VA_BASE_UDP;
14557 -
14558 -       return __raw_readl(udp_base + reg);
14559 -}
14560 -
14561 -/*
14562 - * Write to a UDP register.
14563 - */
14564 -static inline void at91_udp_write(unsigned int reg, unsigned long value)
14565 -{
14566 -       void __iomem *udp_base = (void __iomem *)AT91_VA_BASE_UDP;
14567 -
14568 -       __raw_writel(value, udp_base + reg);
14569 -}
14570 +#define at91_udp_read(dev, reg)                __raw_readl((dev)->udp_baseaddr + (reg))
14571 +#define at91_udp_write(dev, reg, val)  __raw_writel((val), (dev)->udp_baseaddr + (reg))
14572
14573  /*-------------------------------------------------------------------------*/
14574
14575 @@ -210,13 +194,13 @@
14576                 return 0;
14577         }
14578
14579 -       tmp = at91_udp_read(AT91_UDP_FRM_NUM);
14580 +       tmp = at91_udp_read(udc, AT91_UDP_FRM_NUM);
14581         seq_printf(s, "frame %05x:%s%s frame=%d\n", tmp,
14582                 (tmp & AT91_UDP_FRM_OK) ? " ok" : "",
14583                 (tmp & AT91_UDP_FRM_ERR) ? " err" : "",
14584                 (tmp & AT91_UDP_NUM));
14585
14586 -       tmp = at91_udp_read(AT91_UDP_GLB_STAT);
14587 +       tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT);
14588         seq_printf(s, "glbstate %02x:%s" FOURBITS "\n", tmp,
14589                 (tmp & AT91_UDP_RMWUPE) ? " rmwupe" : "",
14590                 (tmp & AT91_UDP_RSMINPR) ? " rsminpr" : "",
14591 @@ -224,13 +208,13 @@
14592                 (tmp & AT91_UDP_CONFG) ? " confg" : "",
14593                 (tmp & AT91_UDP_FADDEN) ? " fadden" : "");
14594
14595 -       tmp = at91_udp_read(AT91_UDP_FADDR);
14596 +       tmp = at91_udp_read(udc, AT91_UDP_FADDR);
14597         seq_printf(s, "faddr   %03x:%s fadd=%d\n", tmp,
14598                 (tmp & AT91_UDP_FEN) ? " fen" : "",
14599                 (tmp & AT91_UDP_FADD));
14600
14601 -       proc_irq_show(s, "imr   ", at91_udp_read(AT91_UDP_IMR));
14602 -       proc_irq_show(s, "isr   ", at91_udp_read(AT91_UDP_ISR));
14603 +       proc_irq_show(s, "imr   ", at91_udp_read(udc, AT91_UDP_IMR));
14604 +       proc_irq_show(s, "isr   ", at91_udp_read(udc, AT91_UDP_ISR));
14605
14606         if (udc->enabled && udc->vbus) {
14607                 proc_ep_show(s, &udc->ep[0]);
14608 @@ -286,6 +270,7 @@
14609  static void done(struct at91_ep *ep, struct at91_request *req, int status)
14610  {
14611         unsigned        stopped = ep->stopped;
14612 +       struct at91_udc *udc = ep->udc;
14613
14614         list_del_init(&req->queue);
14615         if (req->req.status == -EINPROGRESS)
14616 @@ -300,8 +285,8 @@
14617         ep->stopped = stopped;
14618
14619         /* ep0 is always ready; other endpoints need a non-empty queue */
14620 -       if (list_empty(&ep->queue) && ep->int_mask != (1 << 0))
14621 -               at91_udp_write(AT91_UDP_IDR, ep->int_mask);
14622 +       if (list_empty(&ep->queue) && (ep->id != 0))
14623 +               at91_udp_write(udc, AT91_UDP_IDR, 1 << ep->id);
14624  }
14625
14626  /*-------------------------------------------------------------------------*/
14627 @@ -554,8 +539,8 @@
14628          * reset/init endpoint fifo.  NOTE:  leaves fifo_bank alone,
14629          * since endpoint resets don't reset hw pingpong state.
14630          */
14631 -       at91_udp_write(AT91_UDP_RST_EP, ep->int_mask);
14632 -       at91_udp_write(AT91_UDP_RST_EP, 0);
14633 +       at91_udp_write(dev, AT91_UDP_RST_EP, 1 << ep->id);
14634 +       at91_udp_write(dev, AT91_UDP_RST_EP, 0);
14635
14636         local_irq_restore(flags);
14637         return 0;
14638 @@ -564,6 +549,7 @@
14639  static int at91_ep_disable (struct usb_ep * _ep)
14640  {
14641         struct at91_ep  *ep = container_of(_ep, struct at91_ep, ep);
14642 +       struct at91_udc *udc = ep->udc;
14643         unsigned long   flags;
14644
14645         if (ep == &ep->udc->ep[0])
14646 @@ -579,8 +565,8 @@
14647
14648         /* reset fifos and endpoint */
14649         if (ep->udc->clocked) {
14650 -               at91_udp_write(AT91_UDP_RST_EP, ep->int_mask);
14651 -               at91_udp_write(AT91_UDP_RST_EP, 0);
14652 +               at91_udp_write(udc, AT91_UDP_RST_EP, 1 << ep->id);
14653 +               at91_udp_write(udc, AT91_UDP_RST_EP, 0);
14654                 __raw_writel(0, ep->creg);
14655         }
14656
14657 @@ -695,10 +681,10 @@
14658                          * reconfigures the endpoints.
14659                          */
14660                         if (dev->wait_for_config_ack) {
14661 -                               tmp = at91_udp_read(AT91_UDP_GLB_STAT);
14662 +                               tmp = at91_udp_read(dev, AT91_UDP_GLB_STAT);
14663                                 tmp ^= AT91_UDP_CONFG;
14664                                 VDBG("toggle config\n");
14665 -                               at91_udp_write(AT91_UDP_GLB_STAT, tmp);
14666 +                               at91_udp_write(dev, AT91_UDP_GLB_STAT, tmp);
14667                         }
14668                         if (req->req.length == 0) {
14669  ep0_in_status:
14670 @@ -727,7 +713,7 @@
14671
14672         if (req && !status) {
14673                 list_add_tail (&req->queue, &ep->queue);
14674 -               at91_udp_write(AT91_UDP_IER, ep->int_mask);
14675 +               at91_udp_write(dev, AT91_UDP_IER, 1 << ep->id);
14676         }
14677  done:
14678         local_irq_restore(flags);
14679 @@ -758,6 +744,7 @@
14680  static int at91_ep_set_halt(struct usb_ep *_ep, int value)
14681  {
14682         struct at91_ep  *ep = container_of(_ep, struct at91_ep, ep);
14683 +       struct at91_udc *udc = ep->udc;
14684         u32 __iomem     *creg;
14685         u32             csr;
14686         unsigned long   flags;
14687 @@ -785,8 +772,8 @@
14688                         csr |= AT91_UDP_FORCESTALL;
14689                         VDBG("halt %s\n", ep->ep.name);
14690                 } else {
14691 -                       at91_udp_write(AT91_UDP_RST_EP, ep->int_mask);
14692 -                       at91_udp_write(AT91_UDP_RST_EP, 0);
14693 +                       at91_udp_write(udc, AT91_UDP_RST_EP, 1 << ep->id);
14694 +                       at91_udp_write(udc, AT91_UDP_RST_EP, 0);
14695                         csr &= ~AT91_UDP_FORCESTALL;
14696                 }
14697                 __raw_writel(csr, creg);
14698 @@ -813,9 +800,11 @@
14699
14700  static int at91_get_frame(struct usb_gadget *gadget)
14701  {
14702 +       struct at91_udc *udc = to_udc(gadget);
14703 +
14704         if (!to_udc(gadget)->clocked)
14705                 return -EINVAL;
14706 -       return at91_udp_read(AT91_UDP_FRM_NUM) & AT91_UDP_NUM;
14707 +       return at91_udp_read(udc, AT91_UDP_FRM_NUM) & AT91_UDP_NUM;
14708  }
14709
14710  static int at91_wakeup(struct usb_gadget *gadget)
14711 @@ -833,11 +822,11 @@
14712
14713         /* NOTE:  some "early versions" handle ESR differently ... */
14714
14715 -       glbstate = at91_udp_read(AT91_UDP_GLB_STAT);
14716 +       glbstate = at91_udp_read(udc, AT91_UDP_GLB_STAT);
14717         if (!(glbstate & AT91_UDP_ESR))
14718                 goto done;
14719         glbstate |= AT91_UDP_ESR;
14720 -       at91_udp_write(AT91_UDP_GLB_STAT, glbstate);
14721 +       at91_udp_write(udc, AT91_UDP_GLB_STAT, glbstate);
14722
14723  done:
14724         local_irq_restore(flags);
14725 @@ -861,6 +850,7 @@
14726                 ep->stopped = 0;
14727                 ep->fifo_bank = 0;
14728                 ep->ep.maxpacket = ep->maxpacket;
14729 +               ep->creg = (void __iomem *) udc->udp_baseaddr + AT91_UDP_CSR(i);
14730                 // initialiser une queue par endpoint
14731                 INIT_LIST_HEAD(&ep->queue);
14732         }
14733 @@ -915,14 +905,25 @@
14734         if (!udc->enabled || !udc->vbus)
14735                 is_on = 0;
14736         DBG("%sactive\n", is_on ? "" : "in");
14737 +
14738         if (is_on) {
14739                 clk_on(udc);
14740 -               at91_udp_write(AT91_UDP_TXVC, 0);
14741 -               at91_set_gpio_value(udc->board.pullup_pin, 1);
14742 -       } else  {
14743 +               at91_udp_write(udc, AT91_UDP_TXVC, 0);
14744 +               if (cpu_is_at91rm9200())
14745 +                       at91_set_gpio_value(udc->board.pullup_pin, 1);
14746 +               else if (cpu_is_at91sam9260())
14747 +                       at91_udp_write(udc, AT91_UDP_TXVC, (at91_udp_read(udc, AT91_UDP_TXVC) | AT91_UDP_TXVC_PUON));
14748 +               else if (cpu_is_at91sam9261())
14749 +                       at91_sys_write(AT91_MATRIX_USBPUCR, (at91_sys_read(AT91_MATRIX_USBPUCR) | AT91_MATRIX_USBPUCR_PUON));
14750 +       } else {
14751                 stop_activity(udc);
14752 -               at91_udp_write(AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
14753 -               at91_set_gpio_value(udc->board.pullup_pin, 0);
14754 +               at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
14755 +               if (cpu_is_at91rm9200())
14756 +                       at91_set_gpio_value(udc->board.pullup_pin, 0);
14757 +               else if (cpu_is_at91sam9260())
14758 +                       at91_udp_write(udc, AT91_UDP_TXVC, (at91_udp_read(udc, AT91_UDP_TXVC) & ~AT91_UDP_TXVC_PUON));
14759 +               else if (cpu_is_at91sam9261())
14760 +                       at91_sys_write(AT91_MATRIX_USBPUCR, (at91_sys_read(AT91_MATRIX_USBPUCR) & ~AT91_MATRIX_USBPUCR_PUON));
14761                 clk_off(udc);
14762         }
14763  }
14764 @@ -1086,7 +1087,7 @@
14765
14766         case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8)
14767                         | USB_REQ_SET_CONFIGURATION:
14768 -               tmp = at91_udp_read(AT91_UDP_GLB_STAT) & AT91_UDP_CONFG;
14769 +               tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT) & AT91_UDP_CONFG;
14770                 if (pkt.r.wValue)
14771                         udc->wait_for_config_ack = (tmp == 0);
14772                 else
14773 @@ -1103,7 +1104,7 @@
14774         case ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8)
14775                         | USB_REQ_GET_STATUS:
14776                 tmp = (udc->selfpowered << USB_DEVICE_SELF_POWERED);
14777 -               if (at91_udp_read(AT91_UDP_GLB_STAT) & AT91_UDP_ESR)
14778 +               if (at91_udp_read(udc, AT91_UDP_GLB_STAT) & AT91_UDP_ESR)
14779                         tmp |= (1 << USB_DEVICE_REMOTE_WAKEUP);
14780                 PACKET("get device status\n");
14781                 __raw_writeb(tmp, dreg);
14782 @@ -1114,17 +1115,17 @@
14783                         | USB_REQ_SET_FEATURE:
14784                 if (w_value != USB_DEVICE_REMOTE_WAKEUP)
14785                         goto stall;
14786 -               tmp = at91_udp_read(AT91_UDP_GLB_STAT);
14787 +               tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT);
14788                 tmp |= AT91_UDP_ESR;
14789 -               at91_udp_write(AT91_UDP_GLB_STAT, tmp);
14790 +               at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp);
14791                 goto succeed;
14792         case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8)
14793                         | USB_REQ_CLEAR_FEATURE:
14794                 if (w_value != USB_DEVICE_REMOTE_WAKEUP)
14795                         goto stall;
14796 -               tmp = at91_udp_read(AT91_UDP_GLB_STAT);
14797 +               tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT);
14798                 tmp &= ~AT91_UDP_ESR;
14799 -               at91_udp_write(AT91_UDP_GLB_STAT, tmp);
14800 +               at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp);
14801                 goto succeed;
14802
14803         /*
14804 @@ -1206,8 +1207,8 @@
14805                 } else if (ep->is_in)
14806                         goto stall;
14807
14808 -               at91_udp_write(AT91_UDP_RST_EP, ep->int_mask);
14809 -               at91_udp_write(AT91_UDP_RST_EP, 0);
14810 +               at91_udp_write(udc, AT91_UDP_RST_EP, 1 << ep->id);
14811 +               at91_udp_write(udc, AT91_UDP_RST_EP, 0);
14812                 tmp = __raw_readl(ep->creg);
14813                 tmp |= CLR_FX;
14814                 tmp &= ~(SET_FX | AT91_UDP_FORCESTALL);
14815 @@ -1300,13 +1301,13 @@
14816                         if (udc->wait_for_addr_ack) {
14817                                 u32     tmp;
14818
14819 -                               at91_udp_write(AT91_UDP_FADDR,
14820 +                               at91_udp_write(udc, AT91_UDP_FADDR,
14821                                                 AT91_UDP_FEN | udc->addr);
14822 -                               tmp = at91_udp_read(AT91_UDP_GLB_STAT);
14823 +                               tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT);
14824                                 tmp &= ~AT91_UDP_FADDEN;
14825                                 if (udc->addr)
14826                                         tmp |= AT91_UDP_FADDEN;
14827 -                               at91_udp_write(AT91_UDP_GLB_STAT, tmp);
14828 +                               at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp);
14829
14830                                 udc->wait_for_addr_ack = 0;
14831                                 VDBG("address %d\n", udc->addr);
14832 @@ -1374,28 +1375,28 @@
14833         while (rescans--) {
14834                 u32 status;
14835
14836 -               status = at91_udp_read(AT91_UDP_ISR)
14837 -                       & at91_udp_read(AT91_UDP_IMR);
14838 +               status = at91_udp_read(udc, AT91_UDP_ISR)
14839 +                       & at91_udp_read(udc, AT91_UDP_IMR);
14840                 if (!status)
14841                         break;
14842
14843                 /* USB reset irq:  not maskable */
14844                 if (status & AT91_UDP_ENDBUSRES) {
14845 -                       at91_udp_write(AT91_UDP_IDR, ~MINIMUS_INTERRUPTUS);
14846 -                       at91_udp_write(AT91_UDP_IER, MINIMUS_INTERRUPTUS);
14847 +                       at91_udp_write(udc, AT91_UDP_IDR, ~MINIMUS_INTERRUPTUS);
14848 +                       at91_udp_write(udc, AT91_UDP_IER, MINIMUS_INTERRUPTUS);
14849                         /* Atmel code clears this irq twice */
14850 -                       at91_udp_write(AT91_UDP_ICR, AT91_UDP_ENDBUSRES);
14851 -                       at91_udp_write(AT91_UDP_ICR, AT91_UDP_ENDBUSRES);
14852 +                       at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_ENDBUSRES);
14853 +                       at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_ENDBUSRES);
14854                         VDBG("end bus reset\n");
14855                         udc->addr = 0;
14856                         stop_activity(udc);
14857
14858                         /* enable ep0 */
14859 -                       at91_udp_write(AT91_UDP_CSR(0),
14860 +                       at91_udp_write(udc, AT91_UDP_CSR(0),
14861                                         AT91_UDP_EPEDS | AT91_UDP_EPTYPE_CTRL);
14862                         udc->gadget.speed = USB_SPEED_FULL;
14863                         udc->suspended = 0;
14864 -                       at91_udp_write(AT91_UDP_IER, AT91_UDP_EP(0));
14865 +                       at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_EP(0));
14866
14867                         /*
14868                          * NOTE:  this driver keeps clocks off unless the
14869 @@ -1406,9 +1407,9 @@
14870
14871                 /* host initiated suspend (3+ms bus idle) */
14872                 } else if (status & AT91_UDP_RXSUSP) {
14873 -                       at91_udp_write(AT91_UDP_IDR, AT91_UDP_RXSUSP);
14874 -                       at91_udp_write(AT91_UDP_IER, AT91_UDP_RXRSM);
14875 -                       at91_udp_write(AT91_UDP_ICR, AT91_UDP_RXSUSP);
14876 +                       at91_udp_write(udc, AT91_UDP_IDR, AT91_UDP_RXSUSP);
14877 +                       at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_RXRSM);
14878 +                       at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_RXSUSP);
14879                         // VDBG("bus suspend\n");
14880                         if (udc->suspended)
14881                                 continue;
14882 @@ -1425,9 +1426,9 @@
14883
14884                 /* host initiated resume */
14885                 } else if (status & AT91_UDP_RXRSM) {
14886 -                       at91_udp_write(AT91_UDP_IDR, AT91_UDP_RXRSM);
14887 -                       at91_udp_write(AT91_UDP_IER, AT91_UDP_RXSUSP);
14888 -                       at91_udp_write(AT91_UDP_ICR, AT91_UDP_RXRSM);
14889 +                       at91_udp_write(udc, AT91_UDP_IDR, AT91_UDP_RXRSM);
14890 +                       at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_RXSUSP);
14891 +                       at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_RXRSM);
14892                         // VDBG("bus resume\n");
14893                         if (!udc->suspended)
14894                                 continue;
14895 @@ -1479,17 +1480,16 @@
14896                 }
14897         },
14898         .ep[0] = {
14899 +               .id             = 0,
14900                 .ep = {
14901                         .name   = ep0name,
14902                         .ops    = &at91_ep_ops,
14903                 },
14904                 .udc            = &controller,
14905                 .maxpacket      = 8,
14906 -               .creg           = (void __iomem *)(AT91_VA_BASE_UDP
14907 -                                       + AT91_UDP_CSR(0)),
14908 -               .int_mask       = 1 << 0,
14909         },
14910         .ep[1] = {
14911 +               .id             = 1,
14912                 .ep = {
14913                         .name   = "ep1",
14914                         .ops    = &at91_ep_ops,
14915 @@ -1497,11 +1497,9 @@
14916                 .udc            = &controller,
14917                 .is_pingpong    = 1,
14918                 .maxpacket      = 64,
14919 -               .creg           = (void __iomem *)(AT91_VA_BASE_UDP
14920 -                                       + AT91_UDP_CSR(1)),
14921 -               .int_mask       = 1 << 1,
14922         },
14923         .ep[2] = {
14924 +               .id             = 2,
14925                 .ep = {
14926                         .name   = "ep2",
14927                         .ops    = &at91_ep_ops,
14928 @@ -1509,11 +1507,9 @@
14929                 .udc            = &controller,
14930                 .is_pingpong    = 1,
14931                 .maxpacket      = 64,
14932 -               .creg           = (void __iomem *)(AT91_VA_BASE_UDP
14933 -                                       + AT91_UDP_CSR(2)),
14934 -               .int_mask       = 1 << 2,
14935         },
14936         .ep[3] = {
14937 +               .id             = 3,
14938                 .ep = {
14939                         /* could actually do bulk too */
14940                         .name   = "ep3-int",
14941 @@ -1521,11 +1517,9 @@
14942                 },
14943                 .udc            = &controller,
14944                 .maxpacket      = 8,
14945 -               .creg           = (void __iomem *)(AT91_VA_BASE_UDP
14946 -                                       + AT91_UDP_CSR(3)),
14947 -               .int_mask       = 1 << 3,
14948         },
14949         .ep[4] = {
14950 +               .id             = 4,
14951                 .ep = {
14952                         .name   = "ep4",
14953                         .ops    = &at91_ep_ops,
14954 @@ -1533,11 +1527,9 @@
14955                 .udc            = &controller,
14956                 .is_pingpong    = 1,
14957                 .maxpacket      = 256,
14958 -               .creg           = (void __iomem *)(AT91_VA_BASE_UDP
14959 -                                       + AT91_UDP_CSR(4)),
14960 -               .int_mask       = 1 << 4,
14961         },
14962         .ep[5] = {
14963 +               .id             = 5,
14964                 .ep = {
14965                         .name   = "ep5",
14966                         .ops    = &at91_ep_ops,
14967 @@ -1545,9 +1537,6 @@
14968                 .udc            = &controller,
14969                 .is_pingpong    = 1,
14970                 .maxpacket      = 256,
14971 -               .creg           = (void __iomem *)(AT91_VA_BASE_UDP
14972 -                                       + AT91_UDP_CSR(5)),
14973 -               .int_mask       = 1 << 5,
14974         },
14975         /* ep6 and ep7 are also reserved (custom silicon might use them) */
14976  };
14977 @@ -1616,7 +1605,7 @@
14978
14979         local_irq_disable();
14980         udc->enabled = 0;
14981 -       at91_udp_write(AT91_UDP_IDR, ~0);
14982 +       at91_udp_write(udc, AT91_UDP_IDR, ~0);
14983         pullup(udc, 0);
14984         local_irq_enable();
14985
14986 @@ -1641,6 +1630,7 @@
14987         struct device   *dev = &pdev->dev;
14988         struct at91_udc *udc;
14989         int             retval;
14990 +       struct resource *res;
14991
14992         if (!dev->platform_data) {
14993                 /* small (so we copy it) but critical! */
14994 @@ -1658,7 +1648,11 @@
14995                 return -ENODEV;
14996         }
14997
14998 -       if (!request_mem_region(AT91RM9200_BASE_UDP, SZ_16K, driver_name)) {
14999 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
15000 +       if (!res)
15001 +               return -ENXIO;
15002 +
15003 +       if (!request_mem_region(res->start, res->end - res->start + 1, driver_name)) {
15004                 DBG("someone's using UDC memory\n");
15005                 return -EBUSY;
15006         }
15007 @@ -1668,15 +1662,23 @@
15008         udc->gadget.dev.parent = dev;
15009         udc->board = *(struct at91_udc_data *) dev->platform_data;
15010         udc->pdev = pdev;
15011 -       udc_reinit(udc);
15012         udc->enabled = 0;
15013
15014 +       udc->udp_baseaddr = ioremap(res->start, res->end - res->start + 1);
15015 +       if (!udc->udp_baseaddr) {
15016 +               release_mem_region(res->start, res->end - res->start + 1);
15017 +               return -ENOMEM;
15018 +       }
15019 +
15020 +       udc_reinit(udc);
15021 +
15022         /* get interface and function clocks */
15023         udc->iclk = clk_get(dev, "udc_clk");
15024         udc->fclk = clk_get(dev, "udpck");
15025         if (IS_ERR(udc->iclk) || IS_ERR(udc->fclk)) {
15026                 DBG("clocks missing\n");
15027 -               return -ENODEV;
15028 +               retval = -ENODEV;
15029 +               goto fail0;
15030         }
15031
15032         retval = device_register(&udc->gadget.dev);
15033 @@ -1685,8 +1687,10 @@
15034
15035         /* don't do anything until we have both gadget driver and VBUS */
15036         clk_enable(udc->iclk);
15037 -       at91_udp_write(AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
15038 -       at91_udp_write(AT91_UDP_IDR, 0xffffffff);
15039 +       at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
15040 +       at91_udp_write(udc, AT91_UDP_IDR, 0xffffffff);
15041 +       /* Clear all pending interrupts - UDP may be used by bootloader. */
15042 +       at91_udp_write(udc, AT91_UDP_ICR, 0xffffffff);
15043         clk_disable(udc->iclk);
15044
15045         /* request UDC and maybe VBUS irqs */
15046 @@ -1698,6 +1702,11 @@
15047                 goto fail1;
15048         }
15049         if (udc->board.vbus_pin > 0) {
15050 +               /*
15051 +                * Get the initial state of VBUS - we cannot expect
15052 +                * a pending interrupt.
15053 +                */
15054 +               udc->vbus = at91_get_gpio_value(udc->board.vbus_pin);
15055                 if (request_irq(udc->board.vbus_pin, at91_vbus_irq,
15056                                 IRQF_DISABLED, driver_name, udc)) {
15057                         DBG("request vbus irq %d failed\n",
15058 @@ -1720,7 +1729,7 @@
15059  fail1:
15060         device_unregister(&udc->gadget.dev);
15061  fail0:
15062 -       release_mem_region(AT91RM9200_BASE_UDP, SZ_16K);
15063 +       release_mem_region(res->start, res->end - res->start + 1);
15064         DBG("%s probe failed, %d\n", driver_name, retval);
15065         return retval;
15066  }
15067 @@ -1728,6 +1737,7 @@
15068  static int __devexit at91udc_remove(struct platform_device *pdev)
15069  {
15070         struct at91_udc *udc = platform_get_drvdata(pdev);
15071 +       struct resource *res;
15072
15073         DBG("remove\n");
15074
15075 @@ -1742,7 +1752,10 @@
15076                 free_irq(udc->board.vbus_pin, udc);
15077         free_irq(udc->udp_irq, udc);
15078         device_unregister(&udc->gadget.dev);
15079 -       release_mem_region(AT91RM9200_BASE_UDP, SZ_16K);
15080 +
15081 +       iounmap(udc->udp_baseaddr);
15082 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
15083 +       release_mem_region(res->start, res->end - res->start + 1);
15084
15085         clk_put(udc->iclk);
15086         clk_put(udc->fclk);
15087 diff -urN -x CVS linux-2.6.19-final/drivers/usb/gadget/at91_udc.h linux-2.6.19/drivers/usb/gadget/at91_udc.h
15088 --- linux-2.6.19-final/drivers/usb/gadget/at91_udc.h    Mon Dec  4 16:34:04 2006
15089 +++ linux-2.6.19/drivers/usb/gadget/at91_udc.h  Thu Nov 16 17:30:01 2006
15090 @@ -51,10 +51,10 @@
15091  #define     AT91_UDP_EP(n)     (1 << (n))      /* Endpoint Interrupt Status */
15092  #define     AT91_UDP_RXSUSP    (1 <<  8)       /* USB Suspend Interrupt Status */
15093  #define     AT91_UDP_RXRSM     (1 <<  9)       /* USB Resume Interrupt Status */
15094 -#define     AT91_UDP_EXTRSM    (1 << 10)       /* External Resume Interrupt Status */
15095 +#define     AT91_UDP_EXTRSM    (1 << 10)       /* External Resume Interrupt Status [AT91RM9200 only] */
15096  #define     AT91_UDP_SOFINT    (1 << 11)       /* Start of Frame Interrupt Status */
15097  #define     AT91_UDP_ENDBUSRES (1 << 12)       /* End of Bus Reset Interrpt Status */
15098 -#define     AT91_UDP_WAKEUP    (1 << 13)       /* USB Wakeup Interrupt Status */
15099 +#define     AT91_UDP_WAKEUP    (1 << 13)       /* USB Wakeup Interrupt Status [AT91RM9200 only] */
15100
15101  #define AT91_UDP_ICR           0x20            /* Interrupt Clear Register */
15102  #define AT91_UDP_RST_EP                0x28            /* Reset Endpoint Register */
15103 @@ -84,7 +84,7 @@
15104
15105  #define AT91_UDP_TXVC          0x74            /* Transceiver Control Register */
15106  #define     AT91_UDP_TXVC_TXVDIS (1 << 8)      /* Transceiver Disable */
15107 -
15108 +#define            AT91_UDP_TXVC_PUON   (1 << 9)       /* PullUp On [AT91SAM9260 only] */
15109
15110  /*-------------------------------------------------------------------------*/
15111
15112 @@ -105,10 +105,10 @@
15113         struct usb_ep                   ep;
15114         struct list_head                queue;
15115         struct at91_udc                 *udc;
15116 +       u8                              id;
15117         void __iomem                    *creg;
15118
15119         unsigned                        maxpacket:16;
15120 -       u8                              int_mask;
15121         unsigned                        is_pingpong:1;
15122
15123         unsigned                        stopped:1;
15124 @@ -141,6 +141,7 @@
15125         struct clk                      *iclk, *fclk;
15126         struct platform_device          *pdev;
15127         struct proc_dir_entry           *pde;
15128 +       void __iomem                    *udp_baseaddr;
15129         int                             udp_irq;
15130  };
15131
15132 diff -urN -x CVS linux-2.6.19-final/drivers/usb/host/ohci-at91.c linux-2.6.19/drivers/usb/host/ohci-at91.c
15133 --- linux-2.6.19-final/drivers/usb/host/ohci-at91.c     Mon Dec  4 16:40:49 2006
15134 +++ linux-2.6.19/drivers/usb/host/ohci-at91.c   Mon Oct 16 17:19:45 2006
15135 @@ -187,7 +187,6 @@
15136  {
15137         struct at91_usbh_data   *board = hcd->self.controller->platform_data;
15138         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
15139 -       struct usb_device       *root = hcd->self.root_hub;
15140         int                     ret;
15141
15142         if ((ret = ohci_init(ohci)) < 0)
15143 diff -urN -x CVS linux-2.6.19-final/drivers/usb/host/ohci-hcd.c linux-2.6.19/drivers/usb/host/ohci-hcd.c
15144 --- linux-2.6.19-final/drivers/usb/host/ohci-hcd.c      Mon Dec  4 16:40:49 2006
15145 +++ linux-2.6.19/drivers/usb/host/ohci-hcd.c    Thu Nov 30 09:08:25 2006
15146 @@ -935,7 +935,7 @@
15147  #include "ohci-ppc-soc.c"
15148  #endif
15149
15150 -#if defined(CONFIG_ARCH_AT91RM9200) || defined(CONFIG_ARCH_AT91SAM9261)
15151 +#ifdef CONFIG_ARCH_AT91
15152  #include "ohci-at91.c"
15153  #endif
15154
15155 @@ -952,8 +952,7 @@
15156        || defined (CONFIG_ARCH_EP93XX) \
15157        || defined (CONFIG_SOC_AU1X00) \
15158        || defined (CONFIG_USB_OHCI_HCD_PPC_SOC) \
15159 -      || defined (CONFIG_ARCH_AT91RM9200) \
15160 -      || defined (CONFIG_ARCH_AT91SAM9261) \
15161 +      || defined (CONFIG_ARCH_AT91) \
15162        || defined (CONFIG_ARCH_PNX4008) \
15163         )
15164  #error "missing bus glue for ohci-hcd"
15165 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_aic.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_aic.h
15166 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_aic.h       Thu Jan  1 02:00:00 1970
15167 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_aic.h     Tue Oct 24 16:14:13 2006
15168 @@ -0,0 +1,53 @@
15169 +/*
15170 + * include/asm-arm/arch-at91rm9200/at91_aic.h
15171 + *
15172 + * Copyright (C) 2005 Ivan Kokshaysky
15173 + * Copyright (C) SAN People
15174 + *
15175 + * Advanced Interrupt Controller (AIC) - System peripherals registers.
15176 + * Based on AT91RM9200 datasheet revision E.
15177 + *
15178 + * This program is free software; you can redistribute it and/or modify
15179 + * it under the terms of the GNU General Public License as published by
15180 + * the Free Software Foundation; either version 2 of the License, or
15181 + * (at your option) any later version.
15182 + */
15183 +
15184 +#ifndef AT91_AIC_H
15185 +#define AT91_AIC_H
15186 +
15187 +#define AT91_AIC_SMR(n)                (AT91_AIC + ((n) * 4))  /* Source Mode Registers 0-31 */
15188 +#define                AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
15189 +#define                AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
15190 +#define                        AT91_AIC_SRCTYPE_LOW            (0 << 5)
15191 +#define                        AT91_AIC_SRCTYPE_FALLING        (1 << 5)
15192 +#define                        AT91_AIC_SRCTYPE_HIGH           (2 << 5)
15193 +#define                        AT91_AIC_SRCTYPE_RISING         (3 << 5)
15194 +
15195 +#define AT91_AIC_SVR(n)                (AT91_AIC + 0x80 + ((n) * 4))   /* Source Vector Registers 0-31 */
15196 +#define AT91_AIC_IVR           (AT91_AIC + 0x100)      /* Interrupt Vector Register */
15197 +#define AT91_AIC_FVR           (AT91_AIC + 0x104)      /* Fast Interrupt Vector Register */
15198 +#define AT91_AIC_ISR           (AT91_AIC + 0x108)      /* Interrupt Status Register */
15199 +#define                AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
15200 +
15201 +#define AT91_AIC_IPR           (AT91_AIC + 0x10c)      /* Interrupt Pending Register */
15202 +#define AT91_AIC_IMR           (AT91_AIC + 0x110)      /* Interrupt Mask Register */
15203 +#define AT91_AIC_CISR          (AT91_AIC + 0x114)      /* Core Interrupt Status Register */
15204 +#define                AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
15205 +#define                AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
15206 +
15207 +#define AT91_AIC_IECR          (AT91_AIC + 0x120)      /* Interrupt Enable Command Register */
15208 +#define AT91_AIC_IDCR          (AT91_AIC + 0x124)      /* Interrupt Disable Command Register */
15209 +#define AT91_AIC_ICCR          (AT91_AIC + 0x128)      /* Interrupt Clear Command Register */
15210 +#define AT91_AIC_ISCR          (AT91_AIC + 0x12c)      /* Interrupt Set Command Register */
15211 +#define AT91_AIC_EOICR         (AT91_AIC + 0x130)      /* End of Interrupt Command Register */
15212 +#define AT91_AIC_SPU           (AT91_AIC + 0x134)      /* Spurious Interrupt Vector Register */
15213 +#define AT91_AIC_DCR           (AT91_AIC + 0x138)      /* Debug Control Register */
15214 +#define                AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
15215 +#define                AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
15216 +
15217 +#define AT91_AIC_FFER          (AT91_AIC + 0x140)      /* Fast Forcing Enable Register [SAM9 only] */
15218 +#define AT91_AIC_FFDR          (AT91_AIC + 0x144)      /* Fast Forcing Disable Register [SAM9 only] */
15219 +#define AT91_AIC_FFSR          (AT91_AIC + 0x148)      /* Fast Forcing Status Register [SAM9 only] */
15220 +
15221 +#endif
15222 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_dbgu.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_dbgu.h
15223 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_dbgu.h      Thu Jan  1 02:00:00 1970
15224 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_dbgu.h    Tue Oct 24 16:03:07 2006
15225 @@ -0,0 +1,45 @@
15226 +/*
15227 + * include/asm-arm/arch-at91rm9200/at91_dbgu.h
15228 + *
15229 + * Copyright (C) 2005 Ivan Kokshaysky
15230 + * Copyright (C) SAN People
15231 + *
15232 + * Debug Unit (DBGU) - System peripherals registers.
15233 + * Based on AT91RM9200 datasheet revision E.
15234 + *
15235 + * This program is free software; you can redistribute it and/or modify
15236 + * it under the terms of the GNU General Public License as published by
15237 + * the Free Software Foundation; either version 2 of the License, or
15238 + * (at your option) any later version.
15239 + */
15240 +
15241 +#ifndef AT91_DBGU_H
15242 +#define AT91_DBGU_H
15243 +
15244 +#define AT91_DBGU_CR           (AT91_DBGU + 0x00)      /* Control Register */
15245 +#define AT91_DBGU_MR           (AT91_DBGU + 0x04)      /* Mode Register */
15246 +#define AT91_DBGU_IER          (AT91_DBGU + 0x08)      /* Interrupt Enable Register */
15247 +#define                AT91_DBGU_TXRDY         (1 << 1)                /* Transmitter Ready */
15248 +#define                AT91_DBGU_TXEMPTY       (1 << 9)                /* Transmitter Empty */
15249 +#define AT91_DBGU_IDR          (AT91_DBGU + 0x0c)      /* Interrupt Disable Register */
15250 +#define AT91_DBGU_IMR          (AT91_DBGU + 0x10)      /* Interrupt Mask Register */
15251 +#define AT91_DBGU_SR           (AT91_DBGU + 0x14)      /* Status Register */
15252 +#define AT91_DBGU_RHR          (AT91_DBGU + 0x18)      /* Receiver Holding Register */
15253 +#define AT91_DBGU_THR          (AT91_DBGU + 0x1c)      /* Transmitter Holding Register */
15254 +#define AT91_DBGU_BRGR         (AT91_DBGU + 0x20)      /* Baud Rate Generator Register */
15255 +
15256 +#define AT91_DBGU_CIDR         (AT91_DBGU + 0x40)      /* Chip ID Register */
15257 +#define AT91_DBGU_EXID         (AT91_DBGU + 0x44)      /* Chip ID Extension Register */
15258 +#define                AT91_CIDR_VERSION       (0x1f << 0)             /* Version of the Device */
15259 +#define                AT91_CIDR_EPROC         (7    << 5)             /* Embedded Processor */
15260 +#define                AT91_CIDR_NVPSIZ        (0xf  << 8)             /* Nonvolatile Program Memory Size */
15261 +#define                AT91_CIDR_NVPSIZ2       (0xf  << 12)            /* Second Nonvolatile Program Memory Size */
15262 +#define                AT91_CIDR_SRAMSIZ       (0xf  << 16)            /* Internal SRAM Size */
15263 +#define                AT91_CIDR_ARCH          (0xff << 20)            /* Architecture Identifier */
15264 +#define                AT91_CIDR_NVPTYP        (7    << 28)            /* Nonvolatile Program Memory Type */
15265 +#define                AT91_CIDR_EXT           (1    << 31)            /* Extension Flag */
15266 +
15267 +#define AT91_DBGU_FNR          (AT91_DBGU + 0x48)      /* Force NTRST Register [SAM9 only] */
15268 +#define                AT91_DBGU_FNTRST        (1 << 0)                /* Force NTRST */
15269 +
15270 +#endif
15271 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_ecc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_ecc.h
15272 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_ecc.h       Thu Jan  1 02:00:00 1970
15273 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_ecc.h     Wed Nov 15 11:56:12 2006
15274 @@ -0,0 +1,38 @@
15275 +/*
15276 + * include/asm-arm/arch-at91rm9200/at91_ecc.h
15277 + *
15278 + * Error Corrected Code Controller (ECC) - System peripherals regsters.
15279 + * Based on AT91SAM9260 datasheet revision B.
15280 + *
15281 + * This program is free software; you can redistribute it and/or modify it
15282 + * under the terms of the GNU General Public License as published by the
15283 + * Free Software Foundation; either version 2 of the License, or (at your
15284 + * option) any later version.
15285 + */
15286 +
15287 +#ifndef AT91_ECC_H
15288 +#define AT91_ECC_H
15289 +
15290 +#define AT91_ECC_CR            (AT91_ECC + 0x00)       /* Control register */
15291 +#define                AT91_ECC_RST            (1 << 0)                /* Reset parity */
15292 +
15293 +#define AT91_ECC_MR            (AT91_ECC + 0x04)       /* Mode register */
15294 +#define                AT91_ECC_PAGESIZE       (3 << 0)                /* Page Size */
15295 +#define                        AT91_ECC_PAGESIZE_528           (0)
15296 +#define                        AT91_ECC_PAGESIZE_1056          (1)
15297 +#define                        AT91_ECC_PAGESIZE_2112          (2)
15298 +#define                        AT91_ECC_PAGESIZE_4224          (3)
15299 +
15300 +#define AT91_ECC_SR            (AT91_ECC + 0x08)       /* Status register */
15301 +#define                AT91_ECC_RECERR         (1 << 0)                /* Recoverable Error */
15302 +#define                AT91_ECC_ECCERR         (1 << 1)                /* ECC Single Bit Error */
15303 +#define                AT91_ECC_MULERR         (1 << 2)                /* Multiple Errors */
15304 +
15305 +#define AT91_ECC_PR            (AT91_ECC + 0x0c)       /* Parity register */
15306 +#define                AT91_ECC_BITADDR        (0xf << 0)              /* Bit Error Address */
15307 +#define                AT91_ECC_WORDADDR       (0xfff << 4)            /* Word Error Address */
15308 +
15309 +#define AT91_ECC_NPR           (AT91_ECC + 0x10)       /* NParity register */
15310 +#define                AT91_ECC_NPARITY        (0xffff << 0)           /* NParity */
15311 +
15312 +#endif
15313 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_lcdc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_lcdc.h
15314 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_lcdc.h      Thu Jan  1 02:00:00 1970
15315 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_lcdc.h    Sat Nov 25 11:06:19 2006
15316 @@ -0,0 +1,148 @@
15317 +/*
15318 + * include/asm-arm/arch-at91rm9200/at91_lcdc.h
15319 + *
15320 + * LCD Controller (LCDC).
15321 + * Based on AT91SAM9261 datasheet revision E.
15322 + *
15323 + * This program is free software; you can redistribute it and/or modify
15324 + * it under the terms of the GNU General Public License as published by
15325 + * the Free Software Foundation; either version 2 of the License, or
15326 + * (at your option) any later version.
15327 + */
15328 +
15329 +#ifndef AT91_LCDC_H
15330 +#define AT91_LCDC_H
15331 +
15332 +#define AT91_LCDC_DMABADDR1    0x00            /* DMA Base Address Register 1 */
15333 +#define AT91_LCDC_DMABADDR2    0x04            /* DMA Base Address Register 2 */
15334 +#define AT91_LCDC_DMAFRMPT1    0x08            /* DMA Frame Pointer Register 1 */
15335 +#define AT91_LCDC_DMAFRMPT2    0x0c            /* DMA Frame Pointer Register 2 */
15336 +#define AT91_LCDC_DMAFRMADD1   0x10            /* DMA Frame Address Register 1 */
15337 +#define AT91_LCDC_DMAFRMADD2   0x14            /* DMA Frame Address Register 2 */
15338 +
15339 +#define AT91_LCDC_DMAFRMCFG    0x18            /* DMA Frame Configuration Register */
15340 +#define                AT91_LCDC_FRSIZE        (0x7fffff <<  0)        /* Frame Size */
15341 +#define                AT91_LCDC_BLENGTH       (0x7f     << 24)        /* Burst Length */
15342 +
15343 +#define AT91_LCDC_DMACON       0x1c            /* DMA Control Register */
15344 +#define                AT91_LCDC_DMAEN         (0x1 << 0)      /* DMA Enable */
15345 +#define                AT91_LCDC_DMARST        (0x1 << 1)      /* DMA Reset */
15346 +#define                AT91_LCDC_DMABUSY       (0x1 << 2)      /* DMA Busy */
15347 +
15348 +#define AT91_LCDC_LCDCON1      0x0800          /* LCD Control Register 1 */
15349 +#define                AT91_LCDC_BYPASS        (1     <<  0)   /* Bypass lcd_dotck divider */
15350 +#define                AT91_LCDC_CLKVAL        (0x1ff << 12)   /* Clock Divider */
15351 +#define                AT91_LCDC_LINCNT        (0x7ff << 21)   /* Line Counter */
15352 +
15353 +#define AT91_LCDC_LCDCON2      0x0804          /* LCD Control Register 2 */
15354 +#define                AT91_LCDC_DISTYPE       (3 << 0)        /* Display Type */
15355 +#define                        AT91_LCDC_DISTYPE_STNMONO       (0 << 0)
15356 +#define                        AT91_LCDC_DISTYPE_STNCOLOR      (1 << 0)
15357 +#define                        AT91_LCDC_DISTYPE_TFT           (2 << 0)
15358 +#define                AT91_LCDC_SCANMOD       (1 << 2)        /* Scan Mode */
15359 +#define                        AT91_LCDC_SCANMOD_SINGLE        (0 << 2)
15360 +#define                        AT91_LCDC_SCANMOD_DUAL          (1 << 2)
15361 +#define                AT91_LCDC_IFWIDTH       (3 << 3)        /*Interface Width */
15362 +#define                        AT91_LCDC_IFWIDTH_4             (0 << 3)
15363 +#define                        AT91_LCDC_IFWIDTH_8             (1 << 3)
15364 +#define                        AT91_LCDC_IFWIDTH_16            (2 << 3)
15365 +#define                AT91_LCDC_PIXELSIZE     (7 << 5)        /* Bits per pixel */
15366 +#define                        AT91_LCDC_PIXELSIZE_1           (0 << 5)
15367 +#define                        AT91_LCDC_PIXELSIZE_2           (1 << 5)
15368 +#define                        AT91_LCDC_PIXELSIZE_4           (2 << 5)
15369 +#define                        AT91_LCDC_PIXELSIZE_8           (3 << 5)
15370 +#define                        AT91_LCDC_PIXELSIZE_16          (4 << 5)
15371 +#define                        AT91_LCDC_PIXELSIZE_24          (5 << 5)
15372 +#define                AT91_LCDC_INVVD         (1 << 8)        /* LCD Data polarity */
15373 +#define                        AT91_LCDC_INVVD_NORMAL          (0 << 8)
15374 +#define                        AT91_LCDC_INVVD_INVERTED        (1 << 8)
15375 +#define                AT91_LCDC_INVFRAME      (1 << 9 )       /* LCD VSync polarity */
15376 +#define                        AT91_LCDC_INVFRAME_NORMAL       (0 << 9)
15377 +#define                        AT91_LCDC_INVFRAME_INVERTED     (1 << 9)
15378 +#define                AT91_LCDC_INVLINE       (1 << 10)       /* LCD HSync polarity */
15379 +#define                        AT91_LCDC_INVLINE_NORMAL        (0 << 10)
15380 +#define                        AT91_LCDC_INVLINE_INVERTED      (1 << 10)
15381 +#define                AT91_LCDC_INVCLK        (1 << 11)       /* LCD dotclk polarity */
15382 +#define                        AT91_LCDC_INVCLK_NORMAL         (0 << 11)
15383 +#define                        AT91_LCDC_INVCLK_INVERTED       (1 << 11)
15384 +#define                AT91_LCDC_INVDVAL       (1 << 12)       /* LCD dval polarity */
15385 +#define                        AT91_LCDC_INVDVAL_NORMAL        (0 << 12)
15386 +#define                        AT91_LCDC_INVDVAL_INVERTED      (1 << 12)
15387 +#define                AT91_LCDC_CLKMOD        (1 << 15)       /* LCD dotclk mode */
15388 +#define                        AT91_LCDC_CLKMOD_ACTIVEDISPLAY  (0 << 15)
15389 +#define                        AT91_LCDC_CLKMOD_ALWAYSACTIVE   (1 << 15)
15390 +#define                AT91_LCDC_MEMOR         (1 << 31)       /* Memory Ordering Format */
15391 +#define                        AT91_LCDC_MEMOR_BIG             (0 << 31)
15392 +#define                        AT91_LCDC_MEMOR_LITTLE          (1 << 31)
15393 +
15394 +#define AT91_LCDC_TIM1         0x0808          /* LCD Timing Register 1 */
15395 +#define                AT91_LCDC_VFP           (0xff <<  0)    /* Vertical Front Porch */
15396 +#define                AT91_LCDC_VBP           (0xff <<  8)    /* Vertical Back Porch */
15397 +#define                AT91_LCDC_VPW           (0x3f << 16)    /* Vertical Synchronization Pulse Width */
15398 +#define                AT91_LCDC_VHDLY         (0xf  << 24)    /* Vertical to Horizontal Delay */
15399 +
15400 +#define AT91_LCDC_TIM2         0x080c          /* LCD Timing Register 2 */
15401 +#define                AT91_LCDC_HBP           (0xff  <<  0)   /* Horizontal Back Porch */
15402 +#define                AT91_LCDC_HPW           (0x3f  <<  8)   /* Horizontal Synchronization Pulse Width */
15403 +#define                AT91_LCDC_HFP           (0x7ff << 21)   /* Horizontal Front Porch */
15404 +
15405 +#define AT91_LCDC_LCDFRMCFG    0x0810          /* LCD Frame Configuration Register */
15406 +#define                AT91_LCDC_LINEVAL       (0x7ff <<  0)   /* Vertical Size of LCD Module */
15407 +#define                AT91_LCDC_HOZVAL        (0x7ff << 21)   /* Horizontal Size of LCD Module */
15408 +
15409 +#define AT91_LCDC_FIFO         0x0814          /* LCD FIFO Register */
15410 +#define                AT91_LCDC_FIFOTH        (0xffff)        /* FIFO Threshold */
15411 +
15412 +#define AT91_LCDC_DP1_2                0x081c          /* Dithering Pattern DP1_2 Register */
15413 +#define AT91_LCDC_DP4_7                0x0820          /* Dithering Pattern DP4_7 Register */
15414 +#define AT91_LCDC_DP3_5                0x0824          /* Dithering Pattern DP3_5 Register */
15415 +#define AT91_LCDC_DP2_3                0x0828          /* Dithering Pattern DP2_3 Register */
15416 +#define AT91_LCDC_DP5_7                0x082c          /* Dithering Pattern DP5_7 Register */
15417 +#define AT91_LCDC_DP3_4                0x0830          /* Dithering Pattern DP3_4 Register */
15418 +#define AT91_LCDC_DP4_5                0x0834          /* Dithering Pattern DP4_5 Register */
15419 +#define AT91_LCDC_DP6_7                0x0838          /* Dithering Pattern DP6_7 Register */
15420 +#define                AT91_LCDC_DP1_2_VAL     (0xff)
15421 +#define                AT91_LCDC_DP4_7_VAL     (0xfffffff)
15422 +#define                AT91_LCDC_DP3_5_VAL     (0xfffff)
15423 +#define                AT91_LCDC_DP2_3_VAL     (0xfff)
15424 +#define                AT91_LCDC_DP5_7_VAL     (0xfffffff)
15425 +#define                AT91_LCDC_DP3_4_VAL     (0xffff)
15426 +#define                AT91_LCDC_DP4_5_VAL     (0xfffff)
15427 +#define                AT91_LCDC_DP6_7_VAL     (0xfffffff)
15428 +
15429 +#define AT91_LCDC_PWRCON       0x083c          /* Power Control Register */
15430 +#define                AT91_LCDC_PWR           (1    <<  0)    /* LCD Module Power Control */
15431 +#define                AT91_LCDC_GUARDT        (0x7f <<  1)    /* Delay in Frame Period */
15432 +#define                AT91_LCDC_BUSY          (1    << 31)    /* LCD Busy */
15433 +
15434 +#define AT91_LCDC_CONTRAST_CTR 0x0840          /* Contrast Control Register */
15435 +#define                AT91_LCDC_PS            (3 << 0)        /* Contrast Counter Prescaler */
15436 +#define                        AT91_LCDC_PS_DIV1               (0 << 0)
15437 +#define                        AT91_LCDC_PS_DIV2               (1 << 0)
15438 +#define                        AT91_LCDC_PS_DIV4               (2 << 0)
15439 +#define                        AT91_LCDC_PS_DIV8               (3 << 0)
15440 +#define                AT91_LCDC_POL           (1 << 2)        /* Polarity of output Pulse */
15441 +#define                        AT91_LCDC_POL_NEGATIVE          (0 << 2)
15442 +#define                        AT91_LCDC_POL_POSITIVE          (1 << 2)
15443 +#define                AT91_LCDC_ENA           (1 << 3)        /* PWM generator Control */
15444 +#define                        AT91_LCDC_ENA_PWMDISABLE        (0 << 3)
15445 +#define                        AT91_LCDC_ENA_PWMENABLE         (1 << 3)
15446 +
15447 +#define AT91_LCDC_CONTRAST_VAL 0x0844          /* Contrast Value Register */
15448 +#define                AT91_LCDC_CVAL          (0xff)          /* PWM compare value */
15449 +
15450 +#define AT91_LCDC_IER          0x0848          /* Interrupt Enable Register */
15451 +#define AT91_LCDC_IDR          0x084c          /* Interrupt Disable Register */
15452 +#define AT91_LCDC_IMR          0x0850          /* Interrupt Mask Register */
15453 +#define AT91_LCDC_ISR          0x0854          /* Interrupt Enable Register */
15454 +#define AT91_LCDC_ICR          0x0858          /* Interrupt Clear Register */
15455 +#define                AT91_LCDC_LNI           (1 << 0)        /* Line Interrupt */
15456 +#define                AT91_LCDC_LSTLNI        (1 << 1)        /* Last Line Interrupt */
15457 +#define                AT91_LCDC_EOFI          (1 << 2)        /* DMA End Of Frame Interrupt */
15458 +#define                AT91_LCDC_UFLWI         (1 << 4)        /* FIFO Underflow Interrupt */
15459 +#define                AT91_LCDC_OWRI          (1 << 5)        /* FIFO Overwrite Interrupt */
15460 +#define                AT91_LCDC_MERI          (1 << 6)        /* DMA Memory Error Interrupt */
15461 +
15462 +#define AT91_LCDC_LUT_(n)      (0x0c00 + ((n)*4))      /* Palette Entry 0..255 */
15463 +
15464 +#endif
15465 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_mci.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_mci.h
15466 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_mci.h       Thu Jan  1 02:00:00 1970
15467 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_mci.h     Mon Nov  6 12:20:14 2006
15468 @@ -0,0 +1,106 @@
15469 +/*
15470 + * include/asm-arm/arch-at91rm9200/at91_mci.h
15471 + *
15472 + * Copyright (C) 2005 Ivan Kokshaysky
15473 + * Copyright (C) SAN People
15474 + *
15475 + * MultiMedia Card Interface (MCI) registers.
15476 + * Based on AT91RM9200 datasheet revision F.
15477 + *
15478 + * This program is free software; you can redistribute it and/or modify
15479 + * it under the terms of the GNU General Public License as published by
15480 + * the Free Software Foundation; either version 2 of the License, or
15481 + * (at your option) any later version.
15482 + */
15483 +
15484 +#ifndef AT91_MCI_H
15485 +#define AT91_MCI_H
15486 +
15487 +#define AT91_MCI_CR            0x00            /* Control Register */
15488 +#define                AT91_MCI_MCIEN          (1 <<  0)       /* Multi-Media Interface Enable */
15489 +#define                AT91_MCI_MCIDIS         (1 <<  1)       /* Multi-Media Interface Disable */
15490 +#define                AT91_MCI_PWSEN          (1 <<  2)       /* Power Save Mode Enable */
15491 +#define                AT91_MCI_PWSDIS         (1 <<  3)       /* Power Save Mode Disable */
15492 +#define                AT91_MCI_SWRST          (1 <<  7)       /* Software Reset */
15493 +
15494 +#define AT91_MCI_MR            0x04            /* Mode Register */
15495 +#define                AT91_MCI_CLKDIV         (0xff  <<  0)   /* Clock Divider */
15496 +#define                AT91_MCI_PWSDIV         (7     <<  8)   /* Power Saving Divider */
15497 +#define                AT91_MCI_PDCPADV        (1     << 14)   /* PDC Padding Value */
15498 +#define                AT91_MCI_PDCMODE        (1     << 15)   /* PDC-orientated Mode */
15499 +#define                AT91_MCI_BLKLEN         (0xfff << 18)   /* Data Block Length */
15500 +
15501 +#define AT91_MCI_DTOR          0x08            /* Data Timeout Register */
15502 +#define                AT91_MCI_DTOCYC         (0xf << 0)      /* Data Timeout Cycle Number */
15503 +#define                AT91_MCI_DTOMUL         (7   << 4)      /* Data Timeout Multiplier */
15504 +#define                AT91_MCI_DTOMUL_1               (0 <<  4)
15505 +#define                AT91_MCI_DTOMUL_16              (1 <<  4)
15506 +#define                AT91_MCI_DTOMUL_128             (2 <<  4)
15507 +#define                AT91_MCI_DTOMUL_256             (3 <<  4)
15508 +#define                AT91_MCI_DTOMUL_1K              (4 <<  4)
15509 +#define                AT91_MCI_DTOMUL_4K              (5 <<  4)
15510 +#define                AT91_MCI_DTOMUL_64K             (6 <<  4)
15511 +#define                AT91_MCI_DTOMUL_1M              (7 <<  4)
15512 +
15513 +#define AT91_MCI_SDCR          0x0c            /* SD Card Register */
15514 +#define                AT91_MCI_SDCSEL         (3 << 0)        /* SD Card Selector */
15515 +#define                AT91_MCI_SDCBUS         (1 << 7)        /* 1-bit or 4-bit bus */
15516 +
15517 +#define AT91_MCI_ARGR          0x10            /* Argument Register */
15518 +
15519 +#define AT91_MCI_CMDR          0x14            /* Command Register */
15520 +#define                AT91_MCI_CMDNB          (0x3f << 0)     /* Command Number */
15521 +#define                AT91_MCI_RSPTYP         (3    << 6)     /* Response Type */
15522 +#define                        AT91_MCI_RSPTYP_NONE    (0 <<  6)
15523 +#define                        AT91_MCI_RSPTYP_48      (1 <<  6)
15524 +#define                        AT91_MCI_RSPTYP_136     (2 <<  6)
15525 +#define                AT91_MCI_SPCMD          (7    << 8)     /* Special Command */
15526 +#define                        AT91_MCI_SPCMD_NONE     (0 <<  8)
15527 +#define                        AT91_MCI_SPCMD_INIT     (1 <<  8)
15528 +#define                        AT91_MCI_SPCMD_SYNC     (2 <<  8)
15529 +#define                        AT91_MCI_SPCMD_ICMD     (4 <<  8)
15530 +#define                        AT91_MCI_SPCMD_IRESP    (5 <<  8)
15531 +#define                AT91_MCI_OPDCMD         (1 << 11)       /* Open Drain Command */
15532 +#define                AT91_MCI_MAXLAT         (1 << 12)       /* Max Latency for Command to Response */
15533 +#define                AT91_MCI_TRCMD          (3 << 16)       /* Transfer Command */
15534 +#define                        AT91_MCI_TRCMD_NONE     (0 << 16)
15535 +#define                        AT91_MCI_TRCMD_START    (1 << 16)
15536 +#define                        AT91_MCI_TRCMD_STOP     (2 << 16)
15537 +#define                AT91_MCI_TRDIR          (1 << 18)       /* Transfer Direction */
15538 +#define                AT91_MCI_TRTYP          (3 << 19)       /* Transfer Type */
15539 +#define                        AT91_MCI_TRTYP_BLOCK    (0 << 19)
15540 +#define                        AT91_MCI_TRTYP_MULTIPLE (1 << 19)
15541 +#define                        AT91_MCI_TRTYP_STREAM   (2 << 19)
15542 +
15543 +#define AT91_MCI_RSPR(n)       (0x20 + ((n) * 4))      /* Response Registers 0-3 */
15544 +#define AT91_MCR_RDR           0x30            /* Receive Data Register */
15545 +#define AT91_MCR_TDR           0x34            /* Transmit Data Register */
15546 +
15547 +#define AT91_MCI_SR            0x40            /* Status Register */
15548 +#define                AT91_MCI_CMDRDY         (1 <<  0)       /* Command Ready */
15549 +#define                AT91_MCI_RXRDY          (1 <<  1)       /* Receiver Ready */
15550 +#define                AT91_MCI_TXRDY          (1 <<  2)       /* Transmit Ready */
15551 +#define                AT91_MCI_BLKE           (1 <<  3)       /* Data Block Ended */
15552 +#define                AT91_MCI_DTIP           (1 <<  4)       /* Data Transfer in Progress */
15553 +#define                AT91_MCI_NOTBUSY        (1 <<  5)       /* Data Not Busy */
15554 +#define                AT91_MCI_ENDRX          (1 <<  6)       /* End of RX Buffer */
15555 +#define                AT91_MCI_ENDTX          (1 <<  7)       /* End fo TX Buffer */
15556 +#define                AT91_MCI_SDIOIRQA       (1 <<  8)       /* SDIO Interrupt for Slot A */
15557 +#define                At91_MCI_SDIOIRQB       (1 <<  9)       /* SDIO Interrupt for Slot B [AT91RM9200 only] */
15558 +#define                AT91_MCI_RXBUFF         (1 << 14)       /* RX Buffer Full */
15559 +#define                AT91_MCI_TXBUFE         (1 << 15)       /* TX Buffer Empty */
15560 +#define                AT91_MCI_RINDE          (1 << 16)       /* Response Index Error */
15561 +#define                AT91_MCI_RDIRE          (1 << 17)       /* Response Direction Error */
15562 +#define                AT91_MCI_RCRCE          (1 << 18)       /* Response CRC Error */
15563 +#define                AT91_MCI_RENDE          (1 << 19)       /* Response End Bit Error */
15564 +#define                AT91_MCI_RTOE           (1 << 20)       /* Reponse Time-out Error */
15565 +#define                AT91_MCI_DCRCE          (1 << 21)       /* Data CRC Error */
15566 +#define                AT91_MCI_DTOE           (1 << 22)       /* Data Time-out Error */
15567 +#define                AT91_MCI_OVRE           (1 << 30)       /* Overrun */
15568 +#define                AT91_MCI_UNRE           (1 << 31)       /* Underrun */
15569 +
15570 +#define AT91_MCI_IER           0x44            /* Interrupt Enable Register */
15571 +#define AT91_MCI_IDR           0x48            /* Interrupt Disable Register */
15572 +#define AT91_MCI_IMR           0x4c            /* Interrupt Mask Register */
15573 +
15574 +#endif
15575 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pdc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pdc.h
15576 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pdc.h       Thu Jan  1 02:00:00 1970
15577 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pdc.h     Tue Oct 24 14:28:55 2006
15578 @@ -0,0 +1,36 @@
15579 +/*
15580 + * include/asm-arm/arch-at91rm9200/at91_pdc.h
15581 + *
15582 + * Copyright (C) 2005 Ivan Kokshaysky
15583 + * Copyright (C) SAN People
15584 + *
15585 + * Peripheral Data Controller (PDC) registers.
15586 + * Based on AT91RM9200 datasheet revision E.
15587 + *
15588 + * This program is free software; you can redistribute it and/or modify
15589 + * it under the terms of the GNU General Public License as published by
15590 + * the Free Software Foundation; either version 2 of the License, or
15591 + * (at your option) any later version.
15592 + */
15593 +
15594 +#ifndef AT91_PDC_H
15595 +#define AT91_PDC_H
15596 +
15597 +#define AT91_PDC_RPR           0x100   /* Receive Pointer Register */
15598 +#define AT91_PDC_RCR           0x104   /* Receive Counter Register */
15599 +#define AT91_PDC_TPR           0x108   /* Transmit Pointer Register */
15600 +#define AT91_PDC_TCR           0x10c   /* Transmit Counter Register */
15601 +#define AT91_PDC_RNPR          0x110   /* Receive Next Pointer Register */
15602 +#define AT91_PDC_RNCR          0x114   /* Receive Next Counter Register */
15603 +#define AT91_PDC_TNPR          0x118   /* Transmit Next Pointer Register */
15604 +#define AT91_PDC_TNCR          0x11c   /* Transmit Next Counter Register */
15605 +
15606 +#define AT91_PDC_PTCR          0x120   /* Transfer Control Register */
15607 +#define                AT91_PDC_RXTEN          (1 << 0)        /* Receiver Transfer Enable */
15608 +#define                AT91_PDC_RXTDIS         (1 << 1)        /* Receiver Transfer Disable */
15609 +#define                AT91_PDC_TXTEN          (1 << 8)        /* Transmitter Transfer Enable */
15610 +#define                AT91_PDC_TXTDIS         (1 << 9)        /* Transmitter Transfer Disable */
15611 +
15612 +#define AT91_PDC_PTSR          0x124   /* Transfer Status Register */
15613 +
15614 +#endif
15615 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pio.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pio.h
15616 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pio.h       Thu Jan  1 02:00:00 1970
15617 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pio.h     Tue Oct 24 15:47:04 2006
15618 @@ -0,0 +1,49 @@
15619 +/*
15620 + * include/asm-arm/arch-at91rm9200/at91_pio.h
15621 + *
15622 + * Copyright (C) 2005 Ivan Kokshaysky
15623 + * Copyright (C) SAN People
15624 + *
15625 + * Parallel I/O Controller (PIO) - System peripherals registers.
15626 + * Based on AT91RM9200 datasheet revision E.
15627 + *
15628 + * This program is free software; you can redistribute it and/or modify
15629 + * it under the terms of the GNU General Public License as published by
15630 + * the Free Software Foundation; either version 2 of the License, or
15631 + * (at your option) any later version.
15632 + */
15633 +
15634 +#ifndef AT91_PIO_H
15635 +#define AT91_PIO_H
15636 +
15637 +#define PIO_PER                0x00    /* Enable Register */
15638 +#define PIO_PDR                0x04    /* Disable Register */
15639 +#define PIO_PSR                0x08    /* Status Register */
15640 +#define PIO_OER                0x10    /* Output Enable Register */
15641 +#define PIO_ODR                0x14    /* Output Disable Register */
15642 +#define PIO_OSR                0x18    /* Output Status Register */
15643 +#define PIO_IFER       0x20    /* Glitch Input Filter Enable */
15644 +#define PIO_IFDR       0x24    /* Glitch Input Filter Disable */
15645 +#define PIO_IFSR       0x28    /* Glitch Input Filter Status */
15646 +#define PIO_SODR       0x30    /* Set Output Data Register */
15647 +#define PIO_CODR       0x34    /* Clear Output Data Register */
15648 +#define PIO_ODSR       0x38    /* Output Data Status Register */
15649 +#define PIO_PDSR       0x3c    /* Pin Data Status Register */
15650 +#define PIO_IER                0x40    /* Interrupt Enable Register */
15651 +#define PIO_IDR                0x44    /* Interrupt Disable Register */
15652 +#define PIO_IMR                0x48    /* Interrupt Mask Register */
15653 +#define PIO_ISR                0x4c    /* Interrupt Status Register */
15654 +#define PIO_MDER       0x50    /* Multi-driver Enable Register */
15655 +#define PIO_MDDR       0x54    /* Multi-driver Disable Register */
15656 +#define PIO_MDSR       0x58    /* Multi-driver Status Register */
15657 +#define PIO_PUDR       0x60    /* Pull-up Disable Register */
15658 +#define PIO_PUER       0x64    /* Pull-up Enable Register */
15659 +#define PIO_PUSR       0x68    /* Pull-up Status Register */
15660 +#define PIO_ASR                0x70    /* Peripheral A Select Register */
15661 +#define PIO_BSR                0x74    /* Peripheral B Select Register */
15662 +#define PIO_ABSR       0x78    /* AB Status Register */
15663 +#define PIO_OWER       0xa0    /* Output Write Enable Register */
15664 +#define PIO_OWDR       0xa4    /* Output Write Disable Register */
15665 +#define PIO_OWSR       0xa8    /* Output Write Status Register */
15666 +
15667 +#endif
15668 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pit.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pit.h
15669 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pit.h       Thu Jan  1 02:00:00 1970
15670 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pit.h     Thu Nov  9 15:09:54 2006
15671 @@ -0,0 +1,29 @@
15672 +/*
15673 + * include/asm-arm/arch-at91rm9200/at91_pit.h
15674 + *
15675 + * Periodic Interval Timer (PIT) - System peripherals regsters.
15676 + * Based on AT91SAM9261 datasheet revision D.
15677 + *
15678 + * This program is free software; you can redistribute it and/or modify
15679 + * it under the terms of the GNU General Public License as published by
15680 + * the Free Software Foundation; either version 2 of the License, or
15681 + * (at your option) any later version.
15682 + */
15683 +
15684 +#ifndef AT91_PIT_H
15685 +#define AT91_PIT_H
15686 +
15687 +#define AT91_PIT_MR            (AT91_PIT + 0x00)       /* Mode Register */
15688 +#define                AT91_PIT_PITIEN         (1 << 25)               /* Timer Interrupt Enable */
15689 +#define                AT91_PIT_PITEN          (1 << 24)               /* Timer Enabled */
15690 +#define                AT91_PIT_PIV            (0xfffff)               /* Periodic Interval Value */
15691 +
15692 +#define AT91_PIT_SR            (AT91_PIT + 0x04)       /* Status Register */
15693 +#define                AT91_PIT_PITS           (1 << 0)                /* Timer Status */
15694 +
15695 +#define AT91_PIT_PIVR          (AT91_PIT + 0x08)       /* Periodic Interval Value Register */
15696 +#define AT91_PIT_PIIR          (AT91_PIT + 0x0c)       /* Periodic Interval Image Register */
15697 +#define                AT91_PIT_PICNT          (0xfff << 20)           /* Interval Counter */
15698 +#define                AT91_PIT_CPIV           (0xfffff)               /* Inverval Value */
15699 +
15700 +#endif
15701 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pmc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pmc.h
15702 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pmc.h       Thu Jan  1 02:00:00 1970
15703 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pmc.h     Thu Nov  9 09:03:41 2006
15704 @@ -0,0 +1,92 @@
15705 +/*
15706 + * include/asm-arm/arch-at91rm9200/at91_pmc.h
15707 + *
15708 + * Copyright (C) 2005 Ivan Kokshaysky
15709 + * Copyright (C) SAN People
15710 + *
15711 + * Power Management Controller (PMC) - System peripherals registers.
15712 + * Based on AT91RM9200 datasheet revision E.
15713 + *
15714 + * This program is free software; you can redistribute it and/or modify
15715 + * it under the terms of the GNU General Public License as published by
15716 + * the Free Software Foundation; either version 2 of the License, or
15717 + * (at your option) any later version.
15718 + */
15719 +
15720 +#ifndef AT91_PMC_H
15721 +#define AT91_PMC_H
15722 +
15723 +#define        AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
15724 +#define        AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
15725 +
15726 +#define        AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
15727 +#define                AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
15728 +#define                AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
15729 +#define                AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
15730 +#define                AT91RM9200_PMC_UHP      (1 <<  4)               /* USB Host Port Clock [AT91RM9200 only] */
15731 +#define                AT91SAM926x_PMC_UHP     (1 <<  6)               /* USB Host Port Clock [AT91SAM926x only] */
15732 +#define                AT91SAM926x_PMC_UDP     (1 <<  7)               /* USB Devcice Port Clock [AT91SAM926x only] */
15733 +#define                AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
15734 +#define                AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
15735 +#define                AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
15736 +#define                AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
15737 +#define                AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
15738 +#define                AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
15739 +
15740 +#define        AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
15741 +#define        AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
15742 +#define        AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
15743 +
15744 +#define        AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register */
15745 +#define                AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
15746 +#define                AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [AT91SAM926x only] */
15747 +#define                AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
15748 +
15749 +#define        AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
15750 +#define                AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
15751 +#define                AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
15752 +
15753 +#define        AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
15754 +#define        AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
15755 +#define                AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
15756 +#define                AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
15757 +#define                AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
15758 +#define                AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
15759 +#define                AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
15760 +
15761 +#define        AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
15762 +#define                AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
15763 +#define                        AT91_PMC_CSS_SLOW               (0 << 0)
15764 +#define                        AT91_PMC_CSS_MAIN               (1 << 0)
15765 +#define                        AT91_PMC_CSS_PLLA               (2 << 0)
15766 +#define                        AT91_PMC_CSS_PLLB               (3 << 0)
15767 +#define                AT91_PMC_PRES           (7 <<  2)               /* Master Clock Prescaler */
15768 +#define                AT91_PMC_PRES_1                 (0 << 2)
15769 +#define                        AT91_PMC_PRES_2                 (1 << 2)
15770 +#define                        AT91_PMC_PRES_4                 (2 << 2)
15771 +#define                        AT91_PMC_PRES_8                 (3 << 2)
15772 +#define                        AT91_PMC_PRES_16                (4 << 2)
15773 +#define                        AT91_PMC_PRES_32                (5 << 2)
15774 +#define                        AT91_PMC_PRES_64                (6 << 2)
15775 +#define                AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
15776 +#define                        AT91_PMC_MDIV_1                 (0 << 8)
15777 +#define                        AT91_PMC_MDIV_2                 (1 << 8)
15778 +#define                        AT91_PMC_MDIV_3                 (2 << 8)
15779 +#define                        AT91_PMC_MDIV_4                 (3 << 8)
15780 +
15781 +#define        AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-3 Registers */
15782 +
15783 +#define        AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
15784 +#define        AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
15785 +#define        AT91_PMC_SR             (AT91_PMC + 0x68)       /* Status Register */
15786 +#define                AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
15787 +#define                AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
15788 +#define                AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
15789 +#define                AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
15790 +#define                AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
15791 +#define                AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
15792 +#define                AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
15793 +#define                AT91_PMC_PCK3RDY        (1 << 11)               /* Programmable Clock 3 */
15794 +#define        AT91_PMC_IMR            (AT91_PMC + 0x6c)       /* Interrupt Mask Register */
15795 +
15796 +#endif
15797 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_rstc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_rstc.h
15798 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_rstc.h      Thu Jan  1 02:00:00 1970
15799 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_rstc.h    Thu Nov  2 15:59:35 2006
15800 @@ -0,0 +1,39 @@
15801 +/*
15802 + * include/asm-arm/arch-at91rm9200/at91_rstc.h
15803 + *
15804 + * Reset Controller (RSTC) - System peripherals regsters.
15805 + * Based on AT91SAM9261 datasheet revision D.
15806 + *
15807 + * This program is free software; you can redistribute it and/or modify
15808 + * it under the terms of the GNU General Public License as published by
15809 + * the Free Software Foundation; either version 2 of the License, or
15810 + * (at your option) any later version.
15811 + */
15812 +
15813 +#ifndef AT91_RSTC_H
15814 +#define AT91_RSTC_H
15815 +
15816 +#define AT91_RSTC_CR           (AT91_RSTC + 0x00)      /* Reset Controller Control Register */
15817 +#define                AT91_RSTC_PROCRST       (1 << 0)                /* Processor Reset */
15818 +#define                AT91_RSTC_PERRST        (1 << 2)                /* Peripheral Reset */
15819 +#define                AT91_RSTC_EXTRST        (1 << 3)                /* External Reset */
15820 +#define                AT01_RSTC_KEY           (0xff << 24)            /* KEY Password */
15821 +
15822 +#define AT91_RSTC_SR           (AT91_RSTC + 0x04)      /* Reset Controller Status Register */
15823 +#define                AT91_RSTC_URSTS         (1 << 0)                /* User Reset Status */
15824 +#define                AT91_RSTC_RSTTYP        (7 << 8)                /* Reset Type */
15825 +#define                        AT91_RSTC_RSTTYP_GENERAL        (0 << 8)
15826 +#define                        AT91_RSTC_RSTTYP_WAKEUP         (1 << 8)
15827 +#define                        AT91_RSTC_RSTTYP_WATCHDOG       (2 << 8)
15828 +#define                        AT91_RSTC_RSTTYP_SOFTWARE       (3 << 8)
15829 +#define                        AT91_RSTC_RSTTYP_USER   (4 << 8)
15830 +#define                AT91_RSTC_NRSTL         (1 << 16)               /* NRST Pin Level */
15831 +#define                AT91_RSTC_SRCMP         (1 << 17)               /* Software Reset Command in Progress */
15832 +
15833 +#define AT91_RSTC_MR           (AT91_RSTC + 0x08)      /* Reset Controller Mode Register */
15834 +#define                AT91_RSTC_URSTEN        (1 << 0)                /* User Reset Enable */
15835 +#define                AT91_RSTC_URSTIEN       (1 << 4)                /* User Reset Interrupt Enable */
15836 +#define                AT91_RSTC_ERSTL         (0xf << 8)              /* External Reset Length */
15837 +#define                AT91_RSTC_KEY           (0xff << 24)            /* KEY Password */
15838 +
15839 +#endif
15840 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_rtc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_rtc.h
15841 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_rtc.h       Thu Jan  1 02:00:00 1970
15842 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_rtc.h     Tue Oct 24 15:41:59 2006
15843 @@ -0,0 +1,75 @@
15844 +/*
15845 + * include/asm-arm/arch-at91rm9200/at91_rtc.h
15846 + *
15847 + * Copyright (C) 2005 Ivan Kokshaysky
15848 + * Copyright (C) SAN People
15849 + *
15850 + * Real Time Clock (RTC) - System peripheral registers.
15851 + * Based on AT91RM9200 datasheet revision E.
15852 + *
15853 + * This program is free software; you can redistribute it and/or modify
15854 + * it under the terms of the GNU General Public License as published by
15855 + * the Free Software Foundation; either version 2 of the License, or
15856 + * (at your option) any later version.
15857 + */
15858 +
15859 +#ifndef AT91_RTC_H
15860 +#define AT91_RTC_H
15861 +
15862 +#define        AT91_RTC_CR             (AT91_RTC + 0x00)       /* Control Register */
15863 +#define                AT91_RTC_UPDTIM         (1 <<  0)               /* Update Request Time Register */
15864 +#define                AT91_RTC_UPDCAL         (1 <<  1)               /* Update Request Calendar Register */
15865 +#define                AT91_RTC_TIMEVSEL       (3 <<  8)               /* Time Event Selection */
15866 +#define                        AT91_RTC_TIMEVSEL_MINUTE        (0 << 8)
15867 +#define                AT91_RTC_TIMEVSEL_HOUR          (1 << 8)
15868 +#define                AT91_RTC_TIMEVSEL_DAY24         (2 << 8)
15869 +#define                AT91_RTC_TIMEVSEL_DAY12         (3 << 8)
15870 +#define                AT91_RTC_CALEVSEL       (3 << 16)               /* Calendar Event Selection */
15871 +#define                AT91_RTC_CALEVSEL_WEEK          (0 << 16)
15872 +#define                AT91_RTC_CALEVSEL_MONTH         (1 << 16)
15873 +#define                AT91_RTC_CALEVSEL_YEAR          (2 << 16)
15874 +
15875 +#define        AT91_RTC_MR             (AT91_RTC + 0x04)       /* Mode Register */
15876 +#define        AT91_RTC_HRMOD          (1 <<  0)               /* 12/24 Hour Mode */
15877 +
15878 +#define        AT91_RTC_TIMR           (AT91_RTC + 0x08)       /* Time Register */
15879 +#define                AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
15880 +#define                AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
15881 +#define                AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
15882 +#define                AT91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
15883 +
15884 +#define        AT91_RTC_CALR           (AT91_RTC + 0x0c)       /* Calendar Register */
15885 +#define                AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
15886 +#define                AT91_RTC_YEAR           (0xff <<  8)            /* Current Year */
15887 +#define                AT91_RTC_MONTH          (0x1f << 16)            /* Current Month */
15888 +#define                AT91_RTC_DAY            (7    << 21)            /* Current Day */
15889 +#define                AT91_RTC_DATE           (0x3f << 24)            /* Current Date */
15890 +
15891 +#define        AT91_RTC_TIMALR         (AT91_RTC + 0x10)       /* Time Alarm Register */
15892 +#define                AT91_RTC_SECEN          (1 <<  7)               /* Second Alarm Enable */
15893 +#define                AT91_RTC_MINEN          (1 << 15)               /* Minute Alarm Enable */
15894 +#define                AT91_RTC_HOUREN         (1 << 23)               /* Hour Alarm Enable */
15895 +
15896 +#define        AT91_RTC_CALALR         (AT91_RTC + 0x14)       /* Calendar Alarm Register */
15897 +#define                AT91_RTC_MTHEN          (1 << 23)               /* Month Alarm Enable */
15898 +#define                AT91_RTC_DATEEN         (1 << 31)               /* Date Alarm Enable */
15899 +
15900 +#define        AT91_RTC_SR             (AT91_RTC + 0x18)       /* Status Register */
15901 +#define                AT91_RTC_ACKUPD         (1 <<  0)               /* Acknowledge for Update */
15902 +#define                AT91_RTC_ALARM          (1 <<  1)               /* Alarm Flag */
15903 +#define                AT91_RTC_SECEV          (1 <<  2)               /* Second Event */
15904 +#define                AT91_RTC_TIMEV          (1 <<  3)               /* Time Event */
15905 +#define                AT91_RTC_CALEV          (1 <<  4)               /* Calendar Event */
15906 +
15907 +#define        AT91_RTC_SCCR           (AT91_RTC + 0x1c)       /* Status Clear Command Register */
15908 +#define        AT91_RTC_IER            (AT91_RTC + 0x20)       /* Interrupt Enable Register */
15909 +#define        AT91_RTC_IDR            (AT91_RTC + 0x24)       /* Interrupt Disable Register */
15910 +#define        AT91_RTC_IMR            (AT91_RTC + 0x28)       /* Interrupt Mask Register */
15911 +
15912 +#define        AT91_RTC_VER            (AT91_RTC + 0x2c)       /* Valid Entry Register */
15913 +#define                AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
15914 +#define                AT91_RTC_NVCAL          (1 <<  1)               /* Non valid Calendar */
15915 +#define                AT91_RTC_NVTIMALR       (1 <<  2)               /* Non valid Time Alarm */
15916 +#define                AT91_RTC_NVCALALR       (1 <<  3)               /* Non valid Calendar Alarm */
15917 +
15918 +#endif
15919 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_rtt.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_rtt.h
15920 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_rtt.h       Thu Jan  1 02:00:00 1970
15921 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_rtt.h     Thu Nov  9 15:09:30 2006
15922 @@ -0,0 +1,32 @@
15923 +/*
15924 + * include/asm-arm/arch-at91rm9200/at91_rtt.h
15925 + *
15926 + * Real-time Timer (RTT) - System peripherals regsters.
15927 + * Based on AT91SAM9261 datasheet revision D.
15928 + *
15929 + * This program is free software; you can redistribute it and/or modify
15930 + * it under the terms of the GNU General Public License as published by
15931 + * the Free Software Foundation; either version 2 of the License, or
15932 + * (at your option) any later version.
15933 + */
15934 +
15935 +#ifndef AT91_RTT_H
15936 +#define AT91_RTT_H
15937 +
15938 +#define AT91_RTT_MR            (AT91_RTT + 0x00)       /* Real-time Mode Register */
15939 +#define                AT91_RTT_RTPRES         (0xffff << 0)           /* Real-time Timer Prescaler Value */
15940 +#define                AT91_RTT_ALMIEN         (1 << 16)               /* Alarm Interrupt Enable */
15941 +#define                AT91_RTT_RTTINCIEN      (1 << 17)               /* Real Time Timer Increment Interrupt Enable */
15942 +#define                AT91_RTT_RTTRST         (1 << 18)               /* Real Time Timer Restart */
15943 +
15944 +#define AT91_RTT_AR            (AT91_RTT + 0x04)       /* Real-time Alarm Register */
15945 +#define                AT91_RTT_ALMV           (0xffffffff)            /* Alarm Value */
15946 +
15947 +#define AT91_RTT_VR            (AT91_RTT + 0x08)       /* Real-time Value Register */
15948 +#define                AT91_RTT_CRTV           (0xffffffff)            /* Current Real-time Value */
15949 +
15950 +#define AT91_RTT_SR            (AT91_RTT + 0x0c)       /* Real-time Status Register */
15951 +#define                AT91_RTT_ALMS           (1 << 0)                /* Real-time Alarm Status */
15952 +#define                AT91_RTT_RTTINC         (1 << 1)                /* Real-time Timer Increment */
15953 +
15954 +#endif
15955 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_shdwc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_shdwc.h
15956 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_shdwc.h     Thu Jan  1 02:00:00 1970
15957 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_shdwc.h   Thu Nov  9 15:08:30 2006
15958 @@ -0,0 +1,33 @@
15959 +/*
15960 + * include/asm-arm/arch-at91rm9200/at91_shdwc.h
15961 + *
15962 + * Shutdown Controller (SHDWC) - System peripherals regsters.
15963 + * Based on AT91SAM9261 datasheet revision D.
15964 + *
15965 + * This program is free software; you can redistribute it and/or modify
15966 + * it under the terms of the GNU General Public License as published by
15967 + * the Free Software Foundation; either version 2 of the License, or
15968 + * (at your option) any later version.
15969 + */
15970 +
15971 +#ifndef AT91_SHDWC_H
15972 +#define AT91_SHDWC_H
15973 +
15974 +#define AT91_SHDW_CR           (AT91_SHDWC + 0x00)     /* Shut Down Control Register */
15975 +#define                AT91_SHDW_SHDW          (1    << 0)             /* Processor Reset */
15976 +#define                AT91_SHDW_KEY           (0xff << 24)            /* KEY Password */
15977 +
15978 +#define AT91_SHDW_MR           (AT91_SHDWC + 0x04)     /* Shut Down Mode Register */
15979 +#define                AT91_SHDW_WKMODE0       (3 << 0)                /* Wake-up 0 Mode Selection */
15980 +#define                        AT91_SHDW_WKMODE0_NONE          0
15981 +#define                        AT91_SHDW_WKMODE0_HIGH          1
15982 +#define                        AT91_SHDW_WKMODE0_LOW           2
15983 +#define                        AT91_SHDW_WKMODE0_ANYLEVEL      3
15984 +#define                AT91_SHDW_CPTWK0        (0xf << 4)              /* Counter On Wake Up 0 */
15985 +#define                AT91_SHDW_RTTWKEN       (1   << 16)             /* Real Time Timer Wake-up Enable */
15986 +
15987 +#define AT91_SHDW_SR           (AT91_SHDWC + 0x08)     /* Shut Down Status Register */
15988 +#define                AT91_SHDW_WAKEUP0       (1 <<  0)               /* Wake-up 0 Status */
15989 +#define                AT91_SHDW_RTTWK         (1 << 16)               /* Real-time Timer Wake-up */
15990 +
15991 +#endif
15992 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_spi.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_spi.h
15993 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_spi.h       Thu Jan  1 02:00:00 1970
15994 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_spi.h     Wed Nov 15 16:58:25 2006
15995 @@ -0,0 +1,81 @@
15996 +/*
15997 + * include/asm-arm/arch-at91rm9200/at91_spi.h
15998 + *
15999 + * Copyright (C) 2005 Ivan Kokshaysky
16000 + * Copyright (C) SAN People
16001 + *
16002 + * Serial Peripheral Interface (SPI) registers.
16003 + * Based on AT91RM9200 datasheet revision E.
16004 + *
16005 + * This program is free software; you can redistribute it and/or modify
16006 + * it under the terms of the GNU General Public License as published by
16007 + * the Free Software Foundation; either version 2 of the License, or
16008 + * (at your option) any later version.
16009 + */
16010 +
16011 +#ifndef AT91_SPI_H
16012 +#define AT91_SPI_H
16013 +
16014 +#define AT91_SPI_CR                    0x00            /* Control Register */
16015 +#define                AT91_SPI_SPIEN          (1 <<  0)               /* SPI Enable */
16016 +#define                AT91_SPI_SPIDIS         (1 <<  1)               /* SPI Disable */
16017 +#define                AT91_SPI_SWRST          (1 <<  7)               /* SPI Software Reset */
16018 +#define                AT91_SPI_LASTXFER       (1 << 24)               /* Last Transfer [SAM9261 only] */
16019 +
16020 +#define AT91_SPI_MR                    0x04            /* Mode Register */
16021 +#define                AT91_SPI_MSTR           (1    <<  0)            /* Master/Slave Mode */
16022 +#define                AT91_SPI_PS             (1    <<  1)            /* Peripheral Select */
16023 +#define                        AT91_SPI_PS_FIXED       (0 << 1)
16024 +#define                        AT91_SPI_PS_VARIABLE    (1 << 1)
16025 +#define                AT91_SPI_PCSDEC         (1    <<  2)            /* Chip Select Decode */
16026 +#define                AT91_SPI_DIV32          (1    <<  3)            /* Clock Selection [AT91RM9200 only] */
16027 +#define                AT91_SPI_MODFDIS        (1    <<  4)            /* Mode Fault Detection */
16028 +#define                AT91_SPI_LLB            (1    <<  7)            /* Local Loopback Enable */
16029 +#define                AT91_SPI_PCS            (0xf  << 16)            /* Peripheral Chip Select */
16030 +#define                AT91_SPI_DLYBCS         (0xff << 24)            /* Delay Between Chip Selects */
16031 +
16032 +#define AT91_SPI_RDR           0x08                    /* Receive Data Register */
16033 +#define                AT91_SPI_RD             (0xffff <<  0)          /* Receive Data */
16034 +#define                AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
16035 +
16036 +#define AT91_SPI_TDR           0x0c                    /* Transmit Data Register */
16037 +#define                AT91_SPI_TD             (0xffff <<  0)          /* Transmit Data */
16038 +#define                AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
16039 +#define                AT91_SPI_LASTXFER       (1      << 24)          /* Last Transfer [SAM9261 only] */
16040 +
16041 +#define AT91_SPI_SR            0x10                    /* Status Register */
16042 +#define                AT91_SPI_RDRF           (1 <<  0)               /* Receive Data Register Full */
16043 +#define                AT91_SPI_TDRE           (1 <<  1)               /* Transmit Data Register Full */
16044 +#define                AT91_SPI_MODF           (1 <<  2)               /* Mode Fault Error */
16045 +#define                AT91_SPI_OVRES          (1 <<  3)               /* Overrun Error Status */
16046 +#define                AT91_SPI_ENDRX          (1 <<  4)               /* End of RX buffer */
16047 +#define                AT91_SPI_ENDTX          (1 <<  5)               /* End of TX buffer */
16048 +#define                AT91_SPI_RXBUFF         (1 <<  6)               /* RX Buffer Full */
16049 +#define                AT91_SPI_TXBUFE         (1 <<  7)               /* TX Buffer Empty */
16050 +#define                AT91_SPI_NSSR           (1 <<  8)               /* NSS Rising [SAM9261 only] */
16051 +#define                AT91_SPI_TXEMPTY        (1 <<  9)               /* Transmission Register Empty [SAM9261 only] */
16052 +#define                AT91_SPI_SPIENS         (1 << 16)               /* SPI Enable Status */
16053 +
16054 +#define AT91_SPI_IER           0x14                    /* Interrupt Enable Register */
16055 +#define AT91_SPI_IDR           0x18                    /* Interrupt Disable Register */
16056 +#define AT91_SPI_IMR           0x1c                    /* Interrupt Mask Register */
16057 +
16058 +#define AT91_SPI_CSR(n)                (0x30 + ((n) * 4))      /* Chip Select Registers 0-3 */
16059 +#define                AT91_SPI_CPOL           (1    <<  0)            /* Clock Polarity */
16060 +#define                AT91_SPI_NCPHA          (1    <<  1)            /* Clock Phase */
16061 +#define                AT91_SPI_CSAAT          (1    <<  3)            /* Chip Select Active After Transfer [SAM9261 only] */
16062 +#define                AT91_SPI_BITS           (0xf  <<  4)            /* Bits Per Transfer */
16063 +#define                        AT91_SPI_BITS_8         (0 << 4)
16064 +#define                        AT91_SPI_BITS_9         (1 << 4)
16065 +#define                        AT91_SPI_BITS_10        (2 << 4)
16066 +#define                        AT91_SPI_BITS_11        (3 << 4)
16067 +#define                        AT91_SPI_BITS_12        (4 << 4)
16068 +#define                        AT91_SPI_BITS_13        (5 << 4)
16069 +#define                        AT91_SPI_BITS_14        (6 << 4)
16070 +#define                        AT91_SPI_BITS_15        (7 << 4)
16071 +#define                        AT91_SPI_BITS_16        (8 << 4)
16072 +#define                AT91_SPI_SCBR           (0xff <<  8)            /* Serial Clock Baud Rate */
16073 +#define                AT91_SPI_DLYBS          (0xff << 16)            /* Delay before SPCK */
16074 +#define                AT91_SPI_DLYBCT         (0xff << 24)            /* Delay between Consecutive Transfers */
16075 +
16076 +#endif
16077 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_ssc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_ssc.h
16078 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_ssc.h       Thu Jan  1 02:00:00 1970
16079 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_ssc.h     Mon Nov  6 12:40:23 2006
16080 @@ -0,0 +1,106 @@
16081 +/*
16082 + * include/asm-arm/arch-at91rm9200/at91_ssc.h
16083 + *
16084 + * Copyright (C) SAN People
16085 + *
16086 + * Serial Synchronous Controller (SSC) registers.
16087 + * Based on AT91RM9200 datasheet revision E.
16088 + *
16089 + * This program is free software; you can redistribute it and/or modify
16090 + * it under the terms of the GNU General Public License as published by
16091 + * the Free Software Foundation; either version 2 of the License, or
16092 + * (at your option) any later version.
16093 + */
16094 +
16095 +#ifndef AT91_SSC_H
16096 +#define AT91_SSC_H
16097 +
16098 +#define AT91_SSC_CR            0x00    /* Control Register */
16099 +#define                AT91_SSC_RXEN           (1 <<  0)       /* Receive Enable */
16100 +#define                AT91_SSC_RXDIS          (1 <<  1)       /* Receive Disable */
16101 +#define                AT91_SSC_TXEN           (1 <<  8)       /* Transmit Enable */
16102 +#define                AT91_SSC_TXDIS          (1 <<  9)       /* Transmit Disable */
16103 +#define                AT91_SSC_SWRST          (1 << 15)       /* Software Reset */
16104 +
16105 +#define AT91_SSC_CMR           0x04    /* Clock Mode Register */
16106 +#define                AT91_SSC_CMR_DIV        (0xfff << 0)    /* Clock Divider */
16107 +
16108 +#define AT91_SSC_RCMR          0x10    /* Receive Clock Mode Register */
16109 +#define                AT91_SSC_CKS            (3    <<  0)    /* Clock Selection */
16110 +#define                        AT91_SSC_CKS_DIV                (0 << 0)
16111 +#define                        AT91_SSC_CKS_CLOCK              (1 << 0)
16112 +#define                        AT91_SSC_CKS_PIN                (2 << 0)
16113 +#define                AT91_SSC_CKO            (7    <<  2)    /* Clock Output Mode Selection */
16114 +#define                        AT91_SSC_CKO_NONE               (0 << 2)
16115 +#define                        AT91_SSC_CKO_CONTINUOUS         (1 << 2)
16116 +#define                AT91_SSC_CKI            (1    <<  5)    /* Clock Inversion */
16117 +#define                        AT91_SSC_CKI_FALLING            (0 << 5)
16118 +#define                        AT91_SSC_CK_RISING              (1 << 5)
16119 +#define                AT91_SSC_CKG            (1    <<  6)    /* Receive Clock Gating Selection [AT91SAM9261 only] */
16120 +#define                        AT91_SSC_CKG_NONE               (0 << 6)
16121 +#define                        AT91_SSC_CKG_RFLOW              (1 << 6)
16122 +#define                        AT91_SSC_CKG_RFHIGH             (2 << 6)
16123 +#define                AT91_SSC_START          (0xf  <<  8)    /* Start Selection */
16124 +#define                        AT91_SSC_START_CONTINUOUS       (0 << 8)
16125 +#define                        AT91_SSC_START_TX_RX            (1 << 8)
16126 +#define                        AT91_SSC_START_LOW_RF           (2 << 8)
16127 +#define                        AT91_SSC_START_HIGH_RF          (3 << 8)
16128 +#define                        AT91_SSC_START_FALLING_RF       (4 << 8)
16129 +#define                        AT91_SSC_START_RISING_RF        (5 << 8)
16130 +#define                        AT91_SSC_START_LEVEL_RF         (6 << 8)
16131 +#define                        AT91_SSC_START_EDGE_RF          (7 << 8)
16132 +#define                AT91_SSC_STOP           (1    << 12)    /* Receive Stop Selection [AT91SAM9261 only] */
16133 +#define                AT91_SSC_STTDLY         (0xff << 16)    /* Start Delay */
16134 +#define                AT91_SSC_PERIOD         (0xff << 24)    /* Period Divider Selection */
16135 +
16136 +#define AT91_SSC_RFMR          0x14    /* Receive Frame Mode Register */
16137 +#define                AT91_SSC_DATALEN        (0x1f <<  0)    /* Data Length */
16138 +#define                AT91_SSC_LOOP           (1    <<  5)    /* Loop Mode */
16139 +#define                AT91_SSC_MSBF           (1    <<  7)    /* Most Significant Bit First */
16140 +#define                AT91_SSC_DATNB          (0xf  <<  8)    /* Data Number per Frame */
16141 +#define                AT91_SSC_FSLEN          (0xf  << 16)    /* Frame Sync Length */
16142 +#define                AT91_SSC_FSOS           (7    << 20)    /* Frame Sync Output Selection */
16143 +#define                        AT91_SSC_FSOS_NONE              (0 << 20)
16144 +#define                        AT91_SSC_FSOS_NEGATIVE          (1 << 20)
16145 +#define                        AT91_SSC_FSOS_POSITIVE          (2 << 20)
16146 +#define                        AT91_SSC_FSOS_LOW               (3 << 20)
16147 +#define                        AT91_SSC_FSOS_HIGH              (4 << 20)
16148 +#define                        AT91_SSC_FSOS_TOGGLE            (5 << 20)
16149 +#define                AT91_SSC_FSEDGE         (1    << 24)    /* Frame Sync Edge Detection */
16150 +#define                        AT91_SSC_FSEDGE_POSITIVE        (0 << 24)
16151 +#define                        AT91_SSC_FSEDGE_NEGATIVE        (1 << 24)
16152 +
16153 +#define AT91_SSC_TCMR          0x18    /* Transmit Clock Mode Register */
16154 +#define AT91_SSC_TFMR          0x1c    /* Transmit Fram Mode Register */
16155 +#define                AT91_SSC_DATDEF         (1 <<  5)       /* Data Default Value */
16156 +#define                AT91_SSC_FSDEN          (1 << 23)       /* Frame Sync Data Enable */
16157 +
16158 +#define AT91_SSC_RHR           0x20    /* Receive Holding Register */
16159 +#define AT91_SSC_THR           0x24    /* Transmit Holding Register */
16160 +#define AT91_SSC_RSHR          0x30    /* Receive Sync Holding Register */
16161 +#define AT91_SSC_TSHR          0x34    /* Transmit Sync Holding Register */
16162 +
16163 +#define AT91_SSC_RC0R          0x38    /* Receive Compare 0 Register [AT91SAM9261 only] */
16164 +#define AT91_SSC_RC1R          0x3c    /* Receive Compare 1 Register [AT91SAM9261 only] */
16165 +
16166 +#define AT91_SSC_SR            0x40    /* Status Register */
16167 +#define                AT91_SSC_TXRDY          (1 <<  0)       /* Transmit Ready */
16168 +#define                AT91_SSC_TXEMPTY        (1 <<  1)       /* Transmit Empty */
16169 +#define                AT91_SSC_ENDTX          (1 <<  2)       /* End of Transmission */
16170 +#define                AT91_SSC_TXBUFE         (1 <<  3)       /* Transmit Buffer Empty */
16171 +#define                AT91_SSC_RXRDY          (1 <<  4)       /* Receive Ready */
16172 +#define                AT91_SSC_OVRUN          (1 <<  5)       /* Receive Overrun */
16173 +#define                AT91_SSC_ENDRX          (1 <<  6)       /* End of Reception */
16174 +#define                AT91_SSC_RXBUFF         (1 <<  7)       /* Receive Buffer Full */
16175 +#define                AT91_SSC_CP0            (1 <<  8)       /* Compare 0 [AT91SAM9261 only] */
16176 +#define                AT91_SSC_CP1            (1 <<  9)       /* Compare 1 [AT91SAM9261 only] */
16177 +#define                AT91_SSC_TXSYN          (1 << 10)       /* Transmit Sync */
16178 +#define                AT91_SSC_RXSYN          (1 << 11)       /* Receive Sync */
16179 +#define                AT91_SSC_TXENA          (1 << 16)       /* Transmit Enable */
16180 +#define                AT91_SSC_RXENA          (1 << 17)       /* Receive Enable */
16181 +
16182 +#define AT91_SSC_IER           0x44    /* Interrupt Enable Register */
16183 +#define AT91_SSC_IDR           0x48    /* Interrupt Disable Register */
16184 +#define AT91_SSC_IMR           0x4c    /* Interrupt Mask Register */
16185 +
16186 +#endif
16187 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_st.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_st.h
16188 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_st.h        Thu Jan  1 02:00:00 1970
16189 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_st.h      Tue Oct 24 17:15:02 2006
16190 @@ -0,0 +1,49 @@
16191 +/*
16192 + * include/asm-arm/arch-at91rm9200/at91_st.h
16193 + *
16194 + * Copyright (C) 2005 Ivan Kokshaysky
16195 + * Copyright (C) SAN People
16196 + *
16197 + * System Timer (ST) - System peripherals registers.
16198 + * Based on AT91RM9200 datasheet revision E.
16199 + *
16200 + * This program is free software; you can redistribute it and/or modify
16201 + * it under the terms of the GNU General Public License as published by
16202 + * the Free Software Foundation; either version 2 of the License, or
16203 + * (at your option) any later version.
16204 + */
16205 +
16206 +#ifndef AT91_ST_H
16207 +#define AT91_ST_H
16208 +
16209 +#define        AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
16210 +#define        AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
16211 +
16212 +#define        AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
16213 +#define                AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
16214 +
16215 +#define        AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
16216 +#define                AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
16217 +#define                AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
16218 +#define                AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
16219 +
16220 +#define        AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
16221 +#define                AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
16222 +
16223 +#define        AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
16224 +#define                AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
16225 +#define                AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
16226 +#define                AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
16227 +#define                AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
16228 +
16229 +#define        AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
16230 +#define        AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
16231 +#define        AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
16232 +
16233 +#define        AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
16234 +#define                AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
16235 +
16236 +#define        AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
16237 +#define                AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
16238 +
16239 +#endif
16240 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_tc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_tc.h
16241 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_tc.h        Thu Jan  1 02:00:00 1970
16242 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_tc.h      Tue Oct 24 15:21:53 2006
16243 @@ -0,0 +1,146 @@
16244 +/*
16245 + * include/asm-arm/arch-at91rm9200/at91_tc.h
16246 + *
16247 + * Copyright (C) SAN People
16248 + *
16249 + * Timer/Counter Unit (TC) registers.
16250 + * Based on AT91RM9200 datasheet revision E.
16251 + *
16252 + * This program is free software; you can redistribute it and/or modify
16253 + * it under the terms of the GNU General Public License as published by
16254 + * the Free Software Foundation; either version 2 of the License, or
16255 + * (at your option) any later version.
16256 + */
16257 +
16258 +#ifndef AT91_TC_H
16259 +#define AT91_TC_H
16260 +
16261 +#define AT91_TC_BCR            0xc0            /* TC Block Control Register */
16262 +#define                AT91_TC_SYNC            (1 << 0)        /* Synchro Command */
16263 +
16264 +#define AT91_TC_BMR            0xc4            /* TC Block Mode Register */
16265 +#define                AT91_TC_TC0XC0S         (3 << 0)        /* External Clock Signal 0 Selection */
16266 +#define                        AT91_TC_TC0XC0S_TCLK0           (0 << 0)
16267 +#define                        AT91_TC_TC0XC0S_NONE            (1 << 0)
16268 +#define                        AT91_TC_TC0XC0S_TIOA1           (2 << 0)
16269 +#define                        AT91_TC_TC0XC0S_TIOA2           (3 << 0)
16270 +#define                AT91_TC_TC1XC1S         (3 << 2)        /* External Clock Signal 1 Selection */
16271 +#define                        AT91_TC_TC1XC1S_TCLK1           (0 << 2)
16272 +#define                        AT91_TC_TC1XC1S_NONE            (1 << 2)
16273 +#define                        AT91_TC_TC1XC1S_TIOA0           (2 << 2)
16274 +#define                        AT91_TC_TC1XC1S_TIOA2           (3 << 2)
16275 +#define                AT91_TC_TC2XC2S         (3 << 4)        /* External Clock Signal 2 Selection */
16276 +#define                        AT91_TC_TC2XC2S_TCLK2           (0 << 4)
16277 +#define                        AT91_TC_TC2XC2S_NONE            (1 << 4)
16278 +#define                        AT91_TC_TC2XC2S_TIOA0           (2 << 4)
16279 +#define                        AT91_TC_TC2XC2S_TIOA1           (3 << 4)
16280 +
16281 +
16282 +#define AT91_TC_CCR            0x00            /* Channel Control Register */
16283 +#define                AT91_TC_CLKEN           (1 << 0)        /* Counter Clock Enable Command */
16284 +#define                AT91_TC_CLKDIS          (1 << 1)        /* Counter CLock Disable Command */
16285 +#define                AT91_TC_SWTRG           (1 << 2)        /* Software Trigger Command */
16286 +
16287 +#define AT91_TC_CMR            0x04            /* Channel Mode Register */
16288 +#define                AT91_TC_TCCLKS          (7 << 0)        /* Capture/Waveform Mode: Clock Selection */
16289 +#define                        AT91_TC_TIMER_CLOCK1            (0 << 0)
16290 +#define                        AT91_TC_TIMER_CLOCK2            (1 << 0)
16291 +#define                        AT91_TC_TIMER_CLOCK3            (2 << 0)
16292 +#define                        AT91_TC_TIMER_CLOCK4            (3 << 0)
16293 +#define                        AT91_TC_TIMER_CLOCK5            (4 << 0)
16294 +#define                        AT91_TC_XC0                     (5 << 0)
16295 +#define                        AT91_TC_XC1                     (6 << 0)
16296 +#define                        AT91_TC_XC2                     (7 << 0)
16297 +#define                AT91_TC_CLKI            (1 << 3)        /* Capture/Waveform Mode: Clock Invert */
16298 +#define                AT91_TC_BURST           (3 << 4)        /* Capture/Waveform Mode: Burst Signal Selection */
16299 +#define                AT91_TC_LDBSTOP         (1 << 6)        /* Capture Mode: Counter Clock Stopped with TB Loading */
16300 +#define                AT91_TC_LDBDIS          (1 << 7)        /* Capture Mode: Counter Clock Disable with RB Loading */
16301 +#define                AT91_TC_ETRGEDG         (3 << 8)        /* Capture Mode: External Trigger Edge Selection */
16302 +#define                AT91_TC_ABETRG          (1 << 10)       /* Capture Mode: TIOA or TIOB External Trigger Selection */
16303 +#define                AT91_TC_CPCTRG          (1 << 14)       /* Capture Mode: RC Compare Trigger Enable */
16304 +#define                AT91_TC_WAVE            (1 << 15)       /* Capture/Waveform mode */
16305 +#define                AT91_TC_LDRA            (3 << 16)       /* Capture Mode: RA Loading Selection */
16306 +#define                AT91_TC_LDRB            (3 << 18)       /* Capture Mode: RB Loading Selection */
16307 +
16308 +#define                AT91_TC_CPCSTOP         (1 <<  6)       /* Waveform Mode: Counter Clock Stopped with RC Compare */
16309 +#define                AT91_TC_CPCDIS          (1 <<  7)       /* Waveform Mode: Counter Clock Disable with RC Compare */
16310 +#define                AT91_TC_EEVTEDG         (3 <<  8)       /* Waveform Mode: External Event Edge Selection */
16311 +#define                        AT91_TC_EEVTEDG_NONE            (0 << 8)
16312 +#define                        AT91_TC_EEVTEDG_RISING          (1 << 8)
16313 +#define                        AT91_TC_EEVTEDG_FALLING         (2 << 8)
16314 +#define                        AT91_TC_EEVTEDG_BOTH            (3 << 8)
16315 +#define                AT91_TC_EEVT            (3 << 10)       /* Waveform Mode: External Event Selection */
16316 +#define                        AT91_TC_EEVT_TIOB               (0 << 10)
16317 +#define                        AT91_TC_EEVT_XC0                (1 << 10)
16318 +#define                        AT91_TC_EEVT_XC1                (2 << 10)
16319 +#define                        AT91_TC_EEVT_XC2                (3 << 10)
16320 +#define                AT91_TC_ENETRG          (1 << 12)       /* Waveform Mode: External Event Trigger Enable */
16321 +#define                AT91_TC_WAVESEL         (3 << 13)       /* Waveform Mode: Waveform Selection */
16322 +#define                        AT91_TC_WAVESEL_UP              (0 << 13)
16323 +#define                        AT91_TC_WAVESEL_UP_AUTO         (2 << 13)
16324 +#define                        AT91_TC_WAVESEL_UPDOWN          (1 << 13)
16325 +#define                        AT91_TC_WAVESEL_UPDOWN_AUTO     (3 << 13)
16326 +#define                AT91_TC_ACPA            (3 << 16)       /* Waveform Mode: RA Compare Effect on TIOA */
16327 +#define                        AT91_TC_ACPA_NONE               (0 << 16)
16328 +#define                        AT91_TC_ACPA_SET                (1 << 16)
16329 +#define                        AT91_TC_ACPA_CLEAR              (2 << 16)
16330 +#define                        AT91_TC_ACPA_TOGGLE             (3 << 16)
16331 +#define                AT91_TC_ACPC            (3 << 18)       /* Waveform Mode: RC Compre Effect on TIOA */
16332 +#define                        AT91_TC_ACPC_NONE               (0 << 18)
16333 +#define                        AT91_TC_ACPC_SET                (1 << 18)
16334 +#define                        AT91_TC_ACPC_CLEAR              (2 << 18)
16335 +#define                        AT91_TC_ACPC_TOGGLE             (3 << 18)
16336 +#define                AT91_TC_AEEVT           (3 << 20)       /* Waveform Mode: External Event Effect on TIOA */
16337 +#define                        AT91_TC_AEEVT_NONE              (0 << 20)
16338 +#define                        AT91_TC_AEEVT_SET               (1 << 20)
16339 +#define                        AT91_TC_AEEVT_CLEAR             (2 << 20)
16340 +#define                        AT91_TC_AEEVT_TOGGLE            (3 << 20)
16341 +#define                AT91_TC_ASWTRG          (3 << 22)       /* Waveform Mode: Software Trigger Effect on TIOA */
16342 +#define                        AT91_TC_ASWTRG_NONE             (0 << 22)
16343 +#define                        AT91_TC_ASWTRG_SET              (1 << 22)
16344 +#define                        AT91_TC_ASWTRG_CLEAR            (2 << 22)
16345 +#define                        AT91_TC_ASWTRG_TOGGLE           (3 << 22)
16346 +#define                AT91_TC_BCPB            (3 << 24)       /* Waveform Mode: RB Compare Effect on TIOB */
16347 +#define                        AT91_TC_BCPB_NONE               (0 << 24)
16348 +#define                        AT91_TC_BCPB_SET                (1 << 24)
16349 +#define                        AT91_TC_BCPB_CLEAR              (2 << 24)
16350 +#define                        AT91_TC_BCPB_TOGGLE             (3 << 24)
16351 +#define                AT91_TC_BCPC            (3 << 26)       /* Waveform Mode: RC Compare Effect on TIOB */
16352 +#define                        AT91_TC_BCPC_NONE               (0 << 26)
16353 +#define                        AT91_TC_BCPC_SET                (1 << 26)
16354 +#define                        AT91_TC_BCPC_CLEAR              (2 << 26)
16355 +#define                        AT91_TC_BCPC_TOGGLE             (3 << 26)
16356 +#define                AT91_TC_BEEVT           (3 << 28)       /* Waveform Mode: External Event Effect on TIOB */
16357 +#define                        AT91_TC_BEEVT_NONE              (0 << 28)
16358 +#define                        AT91_TC_BEEVT_SET               (1 << 28)
16359 +#define                        AT91_TC_BEEVT_CLEAR             (2 << 28)
16360 +#define                        AT91_TC_BEEVT_TOGGLE            (3 << 28)
16361 +#define                AT91_TC_BSWTRG          (3 << 30)       /* Waveform Mode: Software Trigger Effect on TIOB */
16362 +#define                        AT91_TC_BSWTRG_NONE             (0 << 30)
16363 +#define                        AT91_TC_BSWTRG_SET              (1 << 30)
16364 +#define                        AT91_TC_BSWTRG_CLEAR            (2 << 30)
16365 +#define                        AT91_TC_BSWTRG_TOGGLE           (3 << 30)
16366 +
16367 +#define AT91_TC_CV             0x10            /* Counter Value */
16368 +#define AT91_TC_RA             0x14            /* Register A */
16369 +#define AT91_TC_RB             0x18            /* Register B */
16370 +#define AT91_TC_RC             0x1c            /* Register C */
16371 +
16372 +#define AT91_TC_SR             0x20            /* Status Register */
16373 +#define                AT91_TC_COVFS           (1 <<  0)       /* Counter Overflow Status */
16374 +#define                AT91_TC_LOVRS           (1 <<  1)       /* Load Overrun Status */
16375 +#define                AT91_TC_CPAS            (1 <<  2)       /* RA Compare Status */
16376 +#define                AT91_TC_CPBS            (1 <<  3)       /* RB Compare Status */
16377 +#define                AT91_TC_CPCS            (1 <<  4)       /* RC Compare Status */
16378 +#define                AT91_TC_LDRAS           (1 <<  5)       /* RA Loading Status */
16379 +#define                AT91_TC_LDRBS           (1 <<  6)       /* RB Loading Status */
16380 +#define                AT91_TC_ETRGS           (1 <<  7)       /* External Trigger Status */
16381 +#define                AT91_TC_CLKSTA          (1 << 16)       /* Clock Enabling Status */
16382 +#define                AT91_TC_MTIOA           (1 << 17)       /* TIOA Mirror */
16383 +#define                AT91_TC_MTIOB           (1 << 18)       /* TIOB Mirror */
16384 +
16385 +#define AT91_TC_IER            0x24            /* Interrupt Enable Register */
16386 +#define AT91_TC_IDR            0x28            /* Interrupt Disable Register */
16387 +#define AT91_TC_IMR            0x2c            /* Interrupt Mask Register */
16388 +
16389 +#endif
16390 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_twi.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_twi.h
16391 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_twi.h       Thu Jan  1 02:00:00 1970
16392 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_twi.h     Thu Nov  2 16:46:07 2006
16393 @@ -0,0 +1,57 @@
16394 +/*
16395 + * include/asm-arm/arch-at91rm9200/at91_twi.h
16396 + *
16397 + * Copyright (C) 2005 Ivan Kokshaysky
16398 + * Copyright (C) SAN People
16399 + *
16400 + * Two-wire Interface (TWI) registers.
16401 + * Based on AT91RM9200 datasheet revision E.
16402 + *
16403 + * This program is free software; you can redistribute it and/or modify
16404 + * it under the terms of the GNU General Public License as published by
16405 + * the Free Software Foundation; either version 2 of the License, or
16406 + * (at your option) any later version.
16407 + */
16408 +
16409 +#ifndef AT91_TWI_H
16410 +#define AT91_TWI_H
16411 +
16412 +#define        AT91_TWI_CR             0x00            /* Control Register */
16413 +#define                AT91_TWI_START          (1 <<  0)       /* Send a Start Condition */
16414 +#define                AT91_TWI_STOP           (1 <<  1)       /* Send a Stop Condition */
16415 +#define                AT91_TWI_MSEN           (1 <<  2)       /* Master Transfer Enable */
16416 +#define                AT91_TWI_MSDIS          (1 <<  3)       /* Master Transfer Disable */
16417 +#define                AT91_TWI_SWRST          (1 <<  7)       /* Software Reset */
16418 +
16419 +#define        AT91_TWI_MMR            0x04            /* Master Mode Register */
16420 +#define                AT91_TWI_IADRSZ         (3    <<  8)    /* Internal Device Address Size */
16421 +#define                        AT91_TWI_IADRSZ_NO              (0 << 8)
16422 +#define                        AT91_TWI_IADRSZ_1               (1 << 8)
16423 +#define                        AT91_TWI_IADRSZ_2               (2 << 8)
16424 +#define                        AT91_TWI_IADRSZ_3               (3 << 8)
16425 +#define                AT91_TWI_MREAD          (1    << 12)    /* Master Read Direction */
16426 +#define                AT91_TWI_DADR           (0x7f << 16)    /* Device Address */
16427 +
16428 +#define        AT91_TWI_IADR           0x0c            /* Internal Address Register */
16429 +
16430 +#define        AT91_TWI_CWGR           0x10            /* Clock Waveform Generator Register */
16431 +#define                AT91_TWI_CLDIV          (0xff <<  0)    /* Clock Low Divisor */
16432 +#define                AT91_TWI_CHDIV          (0xff <<  8)    /* Clock High Divisor */
16433 +#define                AT91_TWI_CKDIV          (7    << 16)    /* Clock Divider */
16434 +
16435 +#define        AT91_TWI_SR             0x20            /* Status Register */
16436 +#define                AT91_TWI_TXCOMP         (1 <<  0)       /* Transmission Complete */
16437 +#define                AT91_TWI_RXRDY          (1 <<  1)       /* Receive Holding Register Ready */
16438 +#define                AT91_TWI_TXRDY          (1 <<  2)       /* Transmit Holding Register Ready */
16439 +#define                AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error [AT91RM9200 only] */
16440 +#define                AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error [AT91RM9200 only] */
16441 +#define                AT91_TWI_NACK           (1 <<  8)       /* Not Acknowledged */
16442 +
16443 +#define        AT91_TWI_IER            0x24            /* Interrupt Enable Register */
16444 +#define        AT91_TWI_IDR            0x28            /* Interrupt Disable Register */
16445 +#define        AT91_TWI_IMR            0x2c            /* Interrupt Mask Register */
16446 +#define        AT91_TWI_RHR            0x30            /* Receive Holding Register */
16447 +#define        AT91_TWI_THR            0x34            /* Transmit Holding Register */
16448 +
16449 +#endif
16450 +
16451 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_wdt.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_wdt.h
16452 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_wdt.h       Thu Jan  1 02:00:00 1970
16453 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_wdt.h     Thu Nov  9 15:10:16 2006
16454 @@ -0,0 +1,34 @@
16455 +/*
16456 + * include/asm-arm/arch-at91rm9200/at91_wdt.h
16457 + *
16458 + * Watchdog Timer (WDT) - System peripherals regsters.
16459 + * Based on AT91SAM9261 datasheet revision D.
16460 + *
16461 + * This program is free software; you can redistribute it and/or modify
16462 + * it under the terms of the GNU General Public License as published by
16463 + * the Free Software Foundation; either version 2 of the License, or
16464 + * (at your option) any later version.
16465 + */
16466 +
16467 +#ifndef AT91_WDT_H
16468 +#define AT91_WDT_H
16469 +
16470 +#define AT91_WDT_CR            (AT91_WDT + 0x00)       /* Watchdog Control Register */
16471 +#define                AT91_WDT_WDRSTT         (1    << 0)             /* Restart */
16472 +#define                AT91_WDT_KEY            (0xff << 24)            /* KEY Password */
16473 +
16474 +#define AT91_WDT_MR            (AT91_WDT + 0x04)       /* Watchdog Mode Register */
16475 +#define                AT91_WDT_WDV            (0xfff << 0)            /* Counter Value */
16476 +#define                AT91_WDT_WDFIEN         (1     << 12)           /* Fault Interrupt Enable */
16477 +#define                AT91_WDT_WDRSTEN        (1     << 13)           /* Reset Processor */
16478 +#define                AT91_WDT_WDRPROC        (1     << 14)           /* Timer Restart */
16479 +#define                AT91_WDT_WDDIS          (1     << 15)           /* Watchdog Disable */
16480 +#define                AT91_WDT_WDD            (0xfff << 16)           /* Delta Value */
16481 +#define                AT91_WDT_WDDBGHLT       (1     << 28)           /* Debug Halt */
16482 +#define                AT91_WDT_WDIDLEHLT      (1     << 29)           /* Idle Halt */
16483 +
16484 +#define AT91_WDT_SR            (AT91_WDT + 0x08)       /* Watchdog Status Register */
16485 +#define                AT91_WDT_WDUNF          (1 << 0)                /* Watchdog Underflow */
16486 +#define                AT91_WDT_WDERR          (1 << 1)                /* Watchdog Error */
16487 +
16488 +#endif
16489 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200.h
16490 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200.h     Mon Dec  4 16:41:04 2006
16491 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200.h   Fri Nov 10 09:25:26 2006
16492 @@ -80,6 +80,22 @@
16493
16494
16495  /*
16496 + * System Peripherals (offset from AT91_BASE_SYS)
16497 + */
16498 +#define AT91_AIC       (0xfffff000 - AT91_BASE_SYS)    /* Advanced Interrupt Controller */
16499 +#define AT91_DBGU      (0xfffff200 - AT91_BASE_SYS)    /* Debug Unit */
16500 +#define AT91_PIOA      (0xfffff400 - AT91_BASE_SYS)    /* PIO Controller A */
16501 +#define AT91_PIOB      (0xfffff600 - AT91_BASE_SYS)    /* PIO Controller B */
16502 +#define AT91_PIOC      (0xfffff800 - AT91_BASE_SYS)    /* PIO Controller C */
16503 +#define AT91_PIOD      (0xfffffa00 - AT91_BASE_SYS)    /* PIO Controller D */
16504 +#define AT91_PMC       (0xfffffc00 - AT91_BASE_SYS)    /* Power Management Controller */
16505 +#define AT91_ST                (0xfffffd00 - AT91_BASE_SYS)    /* System Timer */
16506 +#define AT91_RTC       (0xfffffe00 - AT91_BASE_SYS)    /* Real-Time Clock */
16507 +#define AT91_MC                (0xffffff00 - AT91_BASE_SYS)    /* Memory Controllers */
16508 +
16509 +#define AT91_MATRIX    0       /* not supported */
16510 +
16511 +/*
16512   * Internal Memory.
16513   */
16514  #define AT91RM9200_ROM_BASE    0x00100000      /* Internal ROM base address */
16515 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
16516 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h  Thu Jan  1 02:00:00 1970
16517 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h        Thu Nov  2 16:54:12 2006
16518 @@ -0,0 +1,160 @@
16519 +/*
16520 + * include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
16521 + *
16522 + * Copyright (C) 2005 Ivan Kokshaysky
16523 + * Copyright (C) SAN People
16524 + *
16525 + * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
16526 + * Based on AT91RM9200 datasheet revision E.
16527 + *
16528 + * This program is free software; you can redistribute it and/or modify
16529 + * it under the terms of the GNU General Public License as published by
16530 + * the Free Software Foundation; either version 2 of the License, or
16531 + * (at your option) any later version.
16532 + */
16533 +
16534 +#ifndef AT91RM9200_MC_H
16535 +#define AT91RM9200_MC_H
16536 +
16537 +/* Memory Controller */
16538 +#define AT91_MC_RCR            (AT91_MC + 0x00)        /* MC Remap Control Register */
16539 +#define                AT91_MC_RCB             (1 <<  0)               /* Remap Command Bit */
16540 +
16541 +#define AT91_MC_ASR            (AT91_MC + 0x04)        /* MC Abort Status Register */
16542 +#define                AT91_MC_UNADD           (1 <<  0)               /* Undefined Address Abort Status */
16543 +#define                AT91_MC_MISADD          (1 <<  1)               /* Misaligned Address Abort Status */
16544 +#define                AT91_MC_ABTSZ           (3 <<  8)               /* Abort Size Status */
16545 +#define                        AT91_MC_ABTSZ_BYTE              (0 << 8)
16546 +#define                        AT91_MC_ABTSZ_HALFWORD          (1 << 8)
16547 +#define                        AT91_MC_ABTSZ_WORD              (2 << 8)
16548 +#define                AT91_MC_ABTTYP          (3 << 10)               /* Abort Type Status */
16549 +#define                        AT91_MC_ABTTYP_DATAREAD         (0 << 10)
16550 +#define                        AT91_MC_ABTTYP_DATAWRITE        (1 << 10)
16551 +#define                        AT91_MC_ABTTYP_FETCH            (2 << 10)
16552 +#define                AT91_MC_MST0            (1 << 16)               /* ARM920T Abort Source */
16553 +#define                AT91_MC_MST1            (1 << 17)               /* PDC Abort Source */
16554 +#define                AT91_MC_MST2            (1 << 18)               /* UHP Abort Source */
16555 +#define                AT91_MC_MST3            (1 << 19)               /* EMAC Abort Source */
16556 +#define                AT91_MC_SVMST0          (1 << 24)               /* Saved ARM920T Abort Source */
16557 +#define                AT91_MC_SVMST1          (1 << 25)               /* Saved PDC Abort Source */
16558 +#define                AT91_MC_SVMST2          (1 << 26)               /* Saved UHP Abort Source */
16559 +#define                AT91_MC_SVMST3          (1 << 27)               /* Saved EMAC Abort Source */
16560 +
16561 +#define AT91_MC_AASR           (AT91_MC + 0x08)        /* MC Abort Address Status Register */
16562 +
16563 +#define AT91_MC_MPR            (AT91_MC + 0x0c)        /* MC Master Priority Register */
16564 +#define                AT91_MPR_MSTP0          (7 <<  0)               /* ARM920T Priority */
16565 +#define                AT91_MPR_MSTP1          (7 <<  4)               /* PDC Priority */
16566 +#define                AT91_MPR_MSTP2          (7 <<  8)               /* UHP Priority */
16567 +#define                AT91_MPR_MSTP3          (7 << 12)               /* EMAC Priority */
16568 +
16569 +/* External Bus Interface (EBI) registers */
16570 +#define AT91_EBI_CSA           (AT91_MC + 0x60)        /* Chip Select Assignment Register */
16571 +#define                AT91_EBI_CS0A           (1 << 0)                /* Chip Select 0 Assignment */
16572 +#define                        AT91_EBI_CS0A_SMC               (0 << 0)
16573 +#define                        AT91_EBI_CS0A_BFC               (1 << 0)
16574 +#define                AT91_EBI_CS1A           (1 << 1)                /* Chip Select 1 Assignment */
16575 +#define                        AT91_EBI_CS1A_SMC               (0 << 1)
16576 +#define                        AT91_EBI_CS1A_SDRAMC            (1 << 1)
16577 +#define                AT91_EBI_CS3A           (1 << 3)                /* Chip Select 2 Assignment */
16578 +#define                        AT91_EBI_CS3A_SMC               (0 << 3)
16579 +#define                        AT91_EBI_CS3A_SMC_SMARTMEDIA    (1 << 3)
16580 +#define                AT91_EBI_CS4A           (1 << 4)                /* Chip Select 3 Assignment */
16581 +#define                        AT91_EBI_CS4A_SMC               (0 << 4)
16582 +#define                        AT91_EBI_CS4A_SMC_COMPACTFLASH  (1 << 4)
16583 +#define AT91_EBI_CFGR          (AT91_MC + 0x64)        /* Configuration Register */
16584 +#define                AT91_EBI_DBPUC          (1 << 0)                /* Data Bus Pull-Up Configuration */
16585 +
16586 +/* Static Memory Controller (SMC) registers */
16587 +#define        AT91_SMC_CSR(n)         (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
16588 +#define                AT91_SMC_NWS            (0x7f <<  0)            /* Number of Wait States */
16589 +#define                        AT91_SMC_NWS_(x)        ((x) << 0)
16590 +#define                AT91_SMC_WSEN           (1    <<  7)            /* Wait State Enable */
16591 +#define                AT91_SMC_TDF            (0xf  <<  8)            /* Data Float Time */
16592 +#define                        AT91_SMC_TDF_(x)        ((x) << 8)
16593 +#define                AT91_SMC_BAT            (1    << 12)            /* Byte Access Type */
16594 +#define                AT91_SMC_DBW            (3    << 13)            /* Data Bus Width */
16595 +#define                        AT91_SMC_DBW_16         (1 << 13)
16596 +#define                        AT91_SMC_DBW_8          (2 << 13)
16597 +#define                AT91_SMC_DPR            (1 << 15)               /* Data Read Protocol */
16598 +#define                AT91_SMC_ACSS           (3 << 16)               /* Address to Chip Select Setup */
16599 +#define                        AT91_SMC_ACSS_STD       (0 << 16)
16600 +#define                        AT91_SMC_ACSS_1         (1 << 16)
16601 +#define                        AT91_SMC_ACSS_2         (2 << 16)
16602 +#define                        AT91_SMC_ACSS_3         (3 << 16)
16603 +#define                AT91_SMC_RWSETUP        (7 << 24)               /* Read & Write Signal Time Setup */
16604 +#define                        AT91_SMC_RWSETUP_(x)    ((x) << 24)
16605 +#define                AT91_SMC_RWHOLD         (7 << 28)               /* Read & Write Signal Hold Time */
16606 +#define                        AT91_SMC_RWHOLD_(x)     ((x) << 28)
16607 +
16608 +/* SDRAM Controller registers */
16609 +#define AT91_SDRAMC_MR         (AT91_MC + 0x90)        /* Mode Register */
16610 +#define                AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
16611 +#define                        AT91_SDRAMC_MODE_NORMAL         (0 << 0)
16612 +#define                        AT91_SDRAMC_MODE_NOP            (1 << 0)
16613 +#define                        AT91_SDRAMC_MODE_PRECHARGE      (2 << 0)
16614 +#define                        AT91_SDRAMC_MODE_LMR            (3 << 0)
16615 +#define                        AT91_SDRAMC_MODE_REFRESH        (4 << 0)
16616 +#define                AT91_SDRAMC_DBW         (1   << 4)              /* Data Bus Width */
16617 +#define                        AT91_SDRAMC_DBW_32      (0 << 4)
16618 +#define                        AT91_SDRAMC_DBW_16      (1 << 4)
16619 +
16620 +#define AT91_SDRAMC_TR         (AT91_MC + 0x94)        /* Refresh Timer Register */
16621 +#define                AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Count */
16622 +
16623 +#define AT91_SDRAMC_CR         (AT91_MC + 0x98)        /* Configuration Register */
16624 +#define                AT91_SDRAMC_NC          (3   <<  0)             /* Number of Column Bits */
16625 +#define                        AT91_SDRAMC_NC_8        (0 << 0)
16626 +#define                        AT91_SDRAMC_NC_9        (1 << 0)
16627 +#define                        AT91_SDRAMC_NC_10       (2 << 0)
16628 +#define                        AT91_SDRAMC_NC_11       (3 << 0)
16629 +#define                AT91_SDRAMC_NR          (3   <<  2)             /* Number of Row Bits */
16630 +#define                        AT91_SDRAMC_NR_11       (0 << 2)
16631 +#define                        AT91_SDRAMC_NR_12       (1 << 2)
16632 +#define                        AT91_SDRAMC_NR_13       (2 << 2)
16633 +#define                AT91_SDRAMC_NB          (1   <<  4)             /* Number of Banks */
16634 +#define                        AT91_SDRAMC_NB_2        (0 << 4)
16635 +#define                        AT91_SDRAMC_NB_4        (1 << 4)
16636 +#define                AT91_SDRAMC_CAS         (3   <<  5)             /* CAS Latency */
16637 +#define                        AT91_SDRAMC_CAS_2       (2 << 5)
16638 +#define                AT91_SDRAMC_TWR         (0xf <<  7)             /* Write Recovery Delay */
16639 +#define                AT91_SDRAMC_TRC         (0xf << 11)             /* Row Cycle Delay */
16640 +#define                AT91_SDRAMC_TRP         (0xf << 15)             /* Row Precharge Delay */
16641 +#define                AT91_SDRAMC_TRCD        (0xf << 19)             /* Row to Column Delay */
16642 +#define                AT91_SDRAMC_TRAS        (0xf << 23)             /* Active to Precharge Delay */
16643 +#define                AT91_SDRAMC_TXSR        (0xf << 27)             /* Exit Self Refresh to Active Delay */
16644 +
16645 +#define AT91_SDRAMC_SRR                (AT91_MC + 0x9c)        /* Self Refresh Register */
16646 +#define AT91_SDRAMC_LPR                (AT91_MC + 0xa0)        /* Low Power Register */
16647 +#define AT91_SDRAMC_IER                (AT91_MC + 0xa4)        /* Interrupt Enable Register */
16648 +#define AT91_SDRAMC_IDR                (AT91_MC + 0xa8)        /* Interrupt Disable Register */
16649 +#define AT91_SDRAMC_IMR                (AT91_MC + 0xac)        /* Interrupt Mask Register */
16650 +#define AT91_SDRAMC_ISR                (AT91_MC + 0xb0)        /* Interrupt Status Register */
16651 +
16652 +/* Burst Flash Controller register */
16653 +#define AT91_BFC_MR            (AT91_MC + 0xc0)        /* Mode Register */
16654 +#define                AT91_BFC_BFCOM          (3   <<  0)             /* Burst Flash Controller Operating Mode */
16655 +#define                        AT91_BFC_BFCOM_DISABLED (0 << 0)
16656 +#define                        AT91_BFC_BFCOM_ASYNC    (1 << 0)
16657 +#define                        AT91_BFC_BFCOM_BURST    (2 << 0)
16658 +#define                AT91_BFC_BFCC           (3   <<  2)             /* Burst Flash Controller Clock */
16659 +#define                        AT91_BFC_BFCC_MCK       (1 << 2)
16660 +#define                        AT91_BFC_BFCC_DIV2      (2 << 2)
16661 +#define                        AT91_BFC_BFCC_DIV4      (3 << 2)
16662 +#define                AT91_BFC_AVL            (0xf <<  4)             /* Address Valid Latency */
16663 +#define                AT91_BFC_PAGES          (7   <<  8)             /* Page Size */
16664 +#define                        AT91_BFC_PAGES_NO_PAGE  (0 << 8)
16665 +#define                        AT91_BFC_PAGES_16       (1 << 8)
16666 +#define                        AT91_BFC_PAGES_32       (2 << 8)
16667 +#define                        AT91_BFC_PAGES_64       (3 << 8)
16668 +#define                        AT91_BFC_PAGES_128      (4 << 8)
16669 +#define                        AT91_BFC_PAGES_256      (5 << 8)
16670 +#define                        AT91_BFC_PAGES_512      (6 << 8)
16671 +#define                        AT91_BFC_PAGES_1024     (7 << 8)
16672 +#define                AT91_BFC_OEL            (3   << 12)             /* Output Enable Latency */
16673 +#define                AT91_BFC_BAAEN          (1   << 16)             /* Burst Address Advance Enable */
16674 +#define                AT91_BFC_BFOEH          (1   << 17)             /* Burst Flash Output Enable Handling */
16675 +#define                AT91_BFC_MUXEN          (1   << 18)             /* Multiplexed Bus Enable */
16676 +#define                AT91_BFC_RDYEN          (1   << 19)             /* Ready Enable Mode */
16677 +
16678 +#endif
16679 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h
16680 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h Mon Dec  4 16:29:13 2006
16681 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h       Thu Jan  1 02:00:00 1970
16682 @@ -1,104 +0,0 @@
16683 -/*
16684 - * include/asm-arm/arch-at91rm9200/at91rm9200_mci.h
16685 - *
16686 - * Copyright (C) 2005 Ivan Kokshaysky
16687 - * Copyright (C) SAN People
16688 - *
16689 - * MultiMedia Card Interface (MCI) registers.
16690 - * Based on AT91RM9200 datasheet revision E.
16691 - *
16692 - * This program is free software; you can redistribute it and/or modify
16693 - * it under the terms of the GNU General Public License as published by
16694 - * the Free Software Foundation; either version 2 of the License, or
16695 - * (at your option) any later version.
16696 - */
16697 -
16698 -#ifndef AT91RM9200_MCI_H
16699 -#define AT91RM9200_MCI_H
16700 -
16701 -#define AT91_MCI_CR            0x00            /* Control Register */
16702 -#define                AT91_MCI_MCIEN          (1 <<  0)       /* Multi-Media Interface Enable */
16703 -#define                AT91_MCI_MCIDIS         (1 <<  1)       /* Multi-Media Interface Disable */
16704 -#define                AT91_MCI_PWSEN          (1 <<  2)       /* Power Save Mode Enable */
16705 -#define                AT91_MCI_PWSDIS         (1 <<  3)       /* Power Save Mode Disable */
16706 -#define                AT91_MCI_SWRST          (1 <<  7)       /* Software Reset */
16707 -
16708 -#define AT91_MCI_MR            0x04            /* Mode Register */
16709 -#define                AT91_MCI_CLKDIV         (0xff  <<  0)   /* Clock Divider */
16710 -#define                AT91_MCI_PWSDIV         (3     <<  8)   /* Power Saving Divider */
16711 -#define                AT91_MCI_PDCPADV        (1     << 14)   /* PDC Padding Value */
16712 -#define                AT91_MCI_PDCMODE        (1     << 15)   /* PDC-orientated Mode */
16713 -#define                AT91_MCI_BLKLEN         (0xfff << 18)   /* Data Block Length */
16714 -
16715 -#define AT91_MCI_DTOR          0x08            /* Data Timeout Register */
16716 -#define                AT91_MCI_DTOCYC         (0xf << 0)      /* Data Timeout Cycle Number */
16717 -#define                AT91_MCI_DTOMUL         (7   << 4)      /* Data Timeout Multiplier */
16718 -#define                AT91_MCI_DTOMUL_1               (0 <<  4)
16719 -#define                AT91_MCI_DTOMUL_16              (1 <<  4)
16720 -#define                AT91_MCI_DTOMUL_128             (2 <<  4)
16721 -#define                AT91_MCI_DTOMUL_256             (3 <<  4)
16722 -#define                AT91_MCI_DTOMUL_1K              (4 <<  4)
16723 -#define                AT91_MCI_DTOMUL_4K              (5 <<  4)
16724 -#define                AT91_MCI_DTOMUL_64K             (6 <<  4)
16725 -#define                AT91_MCI_DTOMUL_1M              (7 <<  4)
16726 -
16727 -#define AT91_MCI_SDCR          0x0c            /* SD Card Register */
16728 -#define                AT91_MCI_SDCSEL         (0xf << 0)      /* SD Card Selector */
16729 -#define                AT91_MCI_SDCBUS         (1   << 7)      /* 1-bit or 4-bit bus */
16730 -
16731 -#define AT91_MCI_ARGR          0x10            /* Argument Register */
16732 -
16733 -#define AT91_MCI_CMDR          0x14            /* Command Register */
16734 -#define                AT91_MCI_CMDNB          (0x3f << 0)     /* Command Number */
16735 -#define                AT91_MCI_RSPTYP         (3    << 6)     /* Response Type */
16736 -#define                        AT91_MCI_RSPTYP_NONE    (0 <<  6)
16737 -#define                        AT91_MCI_RSPTYP_48      (1 <<  6)
16738 -#define                        AT91_MCI_RSPTYP_136     (2 <<  6)
16739 -#define                AT91_MCI_SPCMD          (7    << 8)     /* Special Command */
16740 -#define                        AT91_MCI_SPCMD_NONE     (0 <<  8)
16741 -#define                        AT91_MCI_SPCMD_INIT     (1 <<  8)
16742 -#define                        AT91_MCI_SPCMD_SYNC     (2 <<  8)
16743 -#define                        AT91_MCI_SPCMD_ICMD     (4 <<  8)
16744 -#define                        AT91_MCI_SPCMD_IRESP    (5 <<  8)
16745 -#define                AT91_MCI_OPDCMD         (1 << 11)       /* Open Drain Command */
16746 -#define                AT91_MCI_MAXLAT         (1 << 12)       /* Max Latency for Command to Response */
16747 -#define                AT91_MCI_TRCMD          (3 << 16)       /* Transfer Command */
16748 -#define                        AT91_MCI_TRCMD_NONE     (0 << 16)
16749 -#define                        AT91_MCI_TRCMD_START    (1 << 16)
16750 -#define                        AT91_MCI_TRCMD_STOP     (2 << 16)
16751 -#define                AT91_MCI_TRDIR          (1 << 18)       /* Transfer Direction */
16752 -#define                AT91_MCI_TRTYP          (3 << 19)       /* Transfer Type */
16753 -#define                        AT91_MCI_TRTYP_BLOCK    (0 << 19)
16754 -#define                        AT91_MCI_TRTYP_MULTIPLE (1 << 19)
16755 -#define                        AT91_MCI_TRTYP_STREAM   (2 << 19)
16756 -
16757 -#define AT91_MCI_RSPR(n)       (0x20 + ((n) * 4))      /* Response Registers 0-3 */
16758 -#define AT91_MCR_RDR           0x30            /* Receive Data Register */
16759 -#define AT91_MCR_TDR           0x34            /* Transmit Data Register */
16760 -
16761 -#define AT91_MCI_SR            0x40            /* Status Register */
16762 -#define                AT91_MCI_CMDRDY         (1 <<  0)       /* Command Ready */
16763 -#define                AT91_MCI_RXRDY          (1 <<  1)       /* Receiver Ready */
16764 -#define                AT91_MCI_TXRDY          (1 <<  2)       /* Transmit Ready */
16765 -#define                AT91_MCI_BLKE           (1 <<  3)       /* Data Block Ended */
16766 -#define                AT91_MCI_DTIP           (1 <<  4)       /* Data Transfer in Progress */
16767 -#define                AT91_MCI_NOTBUSY        (1 <<  5)       /* Data Not Busy */
16768 -#define                AT91_MCI_ENDRX          (1 <<  6)       /* End of RX Buffer */
16769 -#define                AT91_MCI_ENDTX          (1 <<  7)       /* End fo TX Buffer */
16770 -#define                AT91_MCI_RXBUFF         (1 << 14)       /* RX Buffer Full */
16771 -#define                AT91_MCI_TXBUFE         (1 << 15)       /* TX Buffer Empty */
16772 -#define                AT91_MCI_RINDE          (1 << 16)       /* Response Index Error */
16773 -#define                AT91_MCI_RDIRE          (1 << 17)       /* Response Direction Error */
16774 -#define                AT91_MCI_RCRCE          (1 << 18)       /* Response CRC Error */
16775 -#define                AT91_MCI_RENDE          (1 << 19)       /* Response End Bit Error */
16776 -#define                AT91_MCI_RTOE           (1 << 20)       /* Reponse Time-out Error */
16777 -#define                AT91_MCI_DCRCE          (1 << 21)       /* Data CRC Error */
16778 -#define                AT91_MCI_DTOE           (1 << 22)       /* Data Time-out Error */
16779 -#define                AT91_MCI_OVRE           (1 << 30)       /* Overrun */
16780 -#define                AT91_MCI_UNRE           (1 << 31)       /* Underrun */
16781 -
16782 -#define AT91_MCI_IER           0x44            /* Interrupt Enable Register */
16783 -#define AT91_MCI_IDR           0x48            /* Interrupt Disable Register */
16784 -#define AT91_MCI_IMR           0x4c            /* Interrupt Mask Register */
16785 -
16786 -#endif
16787 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
16788 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h Tue May 30 11:42:13 2006
16789 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h       Thu Jan  1 02:00:00 1970
16790 @@ -1,36 +0,0 @@
16791 -/*
16792 - * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
16793 - *
16794 - * Copyright (C) 2005 Ivan Kokshaysky
16795 - * Copyright (C) SAN People
16796 - *
16797 - * Peripheral Data Controller (PDC) registers.
16798 - * Based on AT91RM9200 datasheet revision E.
16799 - *
16800 - * This program is free software; you can redistribute it and/or modify
16801 - * it under the terms of the GNU General Public License as published by
16802 - * the Free Software Foundation; either version 2 of the License, or
16803 - * (at your option) any later version.
16804 - */
16805 -
16806 -#ifndef AT91RM9200_PDC_H
16807 -#define AT91RM9200_PDC_H
16808 -
16809 -#define AT91_PDC_RPR           0x100   /* Receive Pointer Register */
16810 -#define AT91_PDC_RCR           0x104   /* Receive Counter Register */
16811 -#define AT91_PDC_TPR           0x108   /* Transmit Pointer Register */
16812 -#define AT91_PDC_TCR           0x10c   /* Transmit Counter Register */
16813 -#define AT91_PDC_RNPR          0x110   /* Receive Next Pointer Register */
16814 -#define AT91_PDC_RNCR          0x114   /* Receive Next Counter Register */
16815 -#define AT91_PDC_TNPR          0x118   /* Transmit Next Pointer Register */
16816 -#define AT91_PDC_TNCR          0x11c   /* Transmit Next Counter Register */
16817 -
16818 -#define AT91_PDC_PTCR          0x120   /* Transfer Control Register */
16819 -#define                AT91_PDC_RXTEN          (1 << 0)        /* Receiver Transfer Enable */
16820 -#define                AT91_PDC_RXTDIS         (1 << 1)        /* Receiver Transfer Disable */
16821 -#define                AT91_PDC_TXTEN          (1 << 8)        /* Transmitter Transfer Enable */
16822 -#define                AT91_PDC_TXTDIS         (1 << 9)        /* Transmitter Transfer Disable */
16823 -
16824 -#define AT91_PDC_PTSR          0x124   /* Transfer Status Register */
16825 -
16826 -#endif
16827 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
16828 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h Mon Dec  4 16:34:19 2006
16829 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h       Thu Jan  1 02:00:00 1970
16830 @@ -1,81 +0,0 @@
16831 -/*
16832 - * include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
16833 - *
16834 - * Copyright (C) 2005 Ivan Kokshaysky
16835 - * Copyright (C) SAN People
16836 - *
16837 - * Serial Peripheral Interface (SPI) registers.
16838 - * Based on AT91RM9200 datasheet revision E.
16839 - *
16840 - * This program is free software; you can redistribute it and/or modify
16841 - * it under the terms of the GNU General Public License as published by
16842 - * the Free Software Foundation; either version 2 of the License, or
16843 - * (at your option) any later version.
16844 - */
16845 -
16846 -#ifndef AT91RM9200_SPI_H
16847 -#define AT91RM9200_SPI_H
16848 -
16849 -#define AT91_SPI_CR                    0x00            /* Control Register */
16850 -#define                AT91_SPI_SPIEN          (1 <<  0)               /* SPI Enable */
16851 -#define                AT91_SPI_SPIDIS         (1 <<  1)               /* SPI Disable */
16852 -#define                AT91_SPI_SWRST          (1 <<  7)               /* SPI Software Reset */
16853 -#define                AT91_SPI_LASTXFER       (1 << 24)               /* Last Transfer [SAM9261 only] */
16854 -
16855 -#define AT91_SPI_MR                    0x04            /* Mode Register */
16856 -#define                AT91_SPI_MSTR           (1    <<  0)            /* Master/Slave Mode */
16857 -#define                AT91_SPI_PS             (1    <<  1)            /* Peripheral Select */
16858 -#define                        AT91_SPI_PS_FIXED       (0 << 1)
16859 -#define                        AT91_SPI_PS_VARIABLE    (1 << 1)
16860 -#define                AT91_SPI_PCSDEC         (1    <<  2)            /* Chip Select Decode */
16861 -#define                AT91_SPI_DIV32          (1    <<  3)            /* Clock Selection */
16862 -#define                AT91_SPI_MODFDIS        (1    <<  4)            /* Mode Fault Detection */
16863 -#define                AT91_SPI_LLB            (1    <<  7)            /* Local Loopback Enable */
16864 -#define                AT91_SPI_PCS            (0xf  << 16)            /* Peripheral Chip Select */
16865 -#define                AT91_SPI_DLYBCS         (0xff << 24)            /* Delay Between Chip Selects */
16866 -
16867 -#define AT91_SPI_RDR           0x08                    /* Receive Data Register */
16868 -#define                AT91_SPI_RD             (0xffff <<  0)          /* Receive Data */
16869 -#define                AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
16870 -
16871 -#define AT91_SPI_TDR           0x0c                    /* Transmit Data Register */
16872 -#define                AT91_SPI_TD             (0xffff <<  0)          /* Transmit Data */
16873 -#define                AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
16874 -#define                AT91_SPI_LASTXFER       (1      << 24)          /* Last Transfer [SAM9261 only] */
16875 -
16876 -#define AT91_SPI_SR            0x10                    /* Status Register */
16877 -#define                AT91_SPI_RDRF           (1 <<  0)               /* Receive Data Register Full */
16878 -#define                AT91_SPI_TDRE           (1 <<  1)               /* Transmit Data Register Full */
16879 -#define                AT91_SPI_MODF           (1 <<  2)               /* Mode Fault Error */
16880 -#define                AT91_SPI_OVRES          (1 <<  3)               /* Overrun Error Status */
16881 -#define                AT91_SPI_ENDRX          (1 <<  4)               /* End of RX buffer */
16882 -#define                AT91_SPI_ENDTX          (1 <<  5)               /* End of TX buffer */
16883 -#define                AT91_SPI_RXBUFF         (1 <<  6)               /* RX Buffer Full */
16884 -#define                AT91_SPI_TXBUFE         (1 <<  7)               /* TX Buffer Empty */
16885 -#define                AT91_SPI_NSSR           (1 <<  8)               /* NSS Rising [SAM9261 only] */
16886 -#define                AT91_SPI_TXEMPTY        (1 <<  9)               /* Transmission Register Empty [SAM9261 only] */
16887 -#define                AT91_SPI_SPIENS         (1 << 16)               /* SPI Enable Status */
16888 -
16889 -#define AT91_SPI_IER           0x14                    /* Interrupt Enable Register */
16890 -#define AT91_SPI_IDR           0x18                    /* Interrupt Disable Register */
16891 -#define AT91_SPI_IMR           0x1c                    /* Interrupt Mask Register */
16892 -
16893 -#define AT91_SPI_CSR(n)                (0x30 + ((n) * 4))      /* Chip Select Registers 0-3 */
16894 -#define                AT91_SPI_CPOL           (1    <<  0)            /* Clock Polarity */
16895 -#define                AT91_SPI_NCPHA          (1    <<  1)            /* Clock Phase */
16896 -#define                AT91_SPI_CSAAT          (1    <<  3)            /* Chip Select Active After Transfer [SAM9261 only] */
16897 -#define                AT91_SPI_BITS           (0xf  <<  4)            /* Bits Per Transfer */
16898 -#define                        AT91_SPI_BITS_8         (0 << 4)
16899 -#define                        AT91_SPI_BITS_9         (1 << 4)
16900 -#define                        AT91_SPI_BITS_10        (2 << 4)
16901 -#define                        AT91_SPI_BITS_11        (3 << 4)
16902 -#define                        AT91_SPI_BITS_12        (4 << 4)
16903 -#define                        AT91_SPI_BITS_13        (5 << 4)
16904 -#define                        AT91_SPI_BITS_14        (6 << 4)
16905 -#define                        AT91_SPI_BITS_15        (7 << 4)
16906 -#define                        AT91_SPI_BITS_16        (8 << 4)
16907 -#define                AT91_SPI_SCBR           (0xff <<  8)            /* Serial Clock Baud Rate */
16908 -#define                AT91_SPI_DLYBS          (0xff << 16)            /* Delay before SPCK */
16909 -#define                AT91_SPI_DLYBCT         (0xff << 24)            /* Delay between Consecutive Transfers */
16910 -
16911 -#endif
16912 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
16913 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h Mon Dec  4 16:34:19 2006
16914 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h       Thu Jan  1 02:00:00 1970
16915 @@ -1,96 +0,0 @@
16916 -/*
16917 - * include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
16918 - *
16919 - * Copyright (C) SAN People
16920 - *
16921 - * Serial Synchronous Controller (SSC) registers.
16922 - * Based on AT91RM9200 datasheet revision E.
16923 - *
16924 - * This program is free software; you can redistribute it and/or modify
16925 - * it under the terms of the GNU General Public License as published by
16926 - * the Free Software Foundation; either version 2 of the License, or
16927 - * (at your option) any later version.
16928 - */
16929 -
16930 -#ifndef AT91RM9200_SSC_H
16931 -#define AT91RM9200_SSC_H
16932 -
16933 -#define AT91_SSC_CR            0x00    /* Control Register */
16934 -#define                AT91_SSC_RXEN           (1 <<  0)       /* Receive Enable */
16935 -#define                AT91_SSC_RXDIS          (1 <<  1)       /* Receive Disable */
16936 -#define                AT91_SSC_TXEN           (1 <<  8)       /* Transmit Enable */
16937 -#define                AT91_SSC_TXDIS          (1 <<  9)       /* Transmit Disable */
16938 -#define                AT91_SSC_SWRST          (1 << 15)       /* Software Reset */
16939 -
16940 -#define AT91_SSC_CMR           0x04    /* Clock Mode Register */
16941 -#define                AT91_SSC_CMR_DIV        (0xfff << 0)    /* Clock Divider */
16942 -
16943 -#define AT91_SSC_RCMR          0x10    /* Receive Clock Mode Register */
16944 -#define                AT91_SSC_CKS            (3    <<  0)    /* Clock Selection */
16945 -#define                        AT91_SSC_CKS_DIV                (0 << 0)
16946 -#define                        AT91_SSC_CKS_CLOCK              (1 << 0)
16947 -#define                        AT91_SSC_CKS_PIN                (2 << 0)
16948 -#define                AT91_SSC_CKO            (7    <<  2)    /* Clock Output Mode Selection */
16949 -#define                        AT91_SSC_CKO_NONE               (0 << 2)
16950 -#define                        AT91_SSC_CKO_CONTINUOUS         (1 << 2)
16951 -#define                AT91_SSC_CKI            (1    <<  5)    /* Clock Inversion */
16952 -#define                        AT91_SSC_CKI_FALLING            (0 << 5)
16953 -#define                        AT91_SSC_CK_RISING              (1 << 5)
16954 -#define                AT91_SSC_START          (0xf  <<  8)    /* Start Selection */
16955 -#define                        AT91_SSC_START_CONTINUOUS       (0 << 8)
16956 -#define                        AT91_SSC_START_TX_RX            (1 << 8)
16957 -#define                        AT91_SSC_START_LOW_RF           (2 << 8)
16958 -#define                        AT91_SSC_START_HIGH_RF          (3 << 8)
16959 -#define                        AT91_SSC_START_FALLING_RF       (4 << 8)
16960 -#define                        AT91_SSC_START_RISING_RF        (5 << 8)
16961 -#define                        AT91_SSC_START_LEVEL_RF         (6 << 8)
16962 -#define                        AT91_SSC_START_EDGE_RF          (7 << 8)
16963 -#define                AT91_SSC_STTDLY         (0xff << 16)    /* Start Delay */
16964 -#define                AT91_SSC_PERIOD         (0xff << 24)    /* Period Divider Selection */
16965 -
16966 -#define AT91_SSC_RFMR          0x14    /* Receive Frame Mode Register */
16967 -#define                AT91_SSC_DATALEN        (0x1f <<  0)    /* Data Length */
16968 -#define                AT91_SSC_LOOP           (1    <<  5)    /* Loop Mode */
16969 -#define                AT91_SSC_MSBF           (1    <<  7)    /* Most Significant Bit First */
16970 -#define                AT91_SSC_DATNB          (0xf  <<  8)    /* Data Number per Frame */
16971 -#define                AT91_SSC_FSLEN          (0xf  << 16)    /* Frame Sync Length */
16972 -#define                AT91_SSC_FSOS           (7    << 20)    /* Frame Sync Output Selection */
16973 -#define                        AT91_SSC_FSOS_NONE              (0 << 20)
16974 -#define                        AT91_SSC_FSOS_NEGATIVE          (1 << 20)
16975 -#define                        AT91_SSC_FSOS_POSITIVE          (2 << 20)
16976 -#define                        AT91_SSC_FSOS_LOW               (3 << 20)
16977 -#define                        AT91_SSC_FSOS_HIGH              (4 << 20)
16978 -#define                        AT91_SSC_FSOS_TOGGLE            (5 << 20)
16979 -#define                AT91_SSC_FSEDGE         (1    << 24)    /* Frame Sync Edge Detection */
16980 -#define                        AT91_SSC_FSEDGE_POSITIVE        (0 << 24)
16981 -#define                        AT91_SSC_FSEDGE_NEGATIVE        (1 << 24)
16982 -
16983 -#define AT91_SSC_TCMR          0x18    /* Transmit Clock Mode Register */
16984 -#define AT91_SSC_TFMR          0x1c    /* Transmit Fram Mode Register */
16985 -#define                AT91_SSC_DATDEF         (1 <<  5)       /* Data Default Value */
16986 -#define                AT91_SSC_FSDEN          (1 << 23)       /* Frame Sync Data Enable */
16987 -
16988 -#define AT91_SSC_RHR           0x20    /* Receive Holding Register */
16989 -#define AT91_SSC_THR           0x24    /* Transmit Holding Register */
16990 -#define AT91_SSC_RSHR          0x30    /* Receive Sync Holding Register */
16991 -#define AT91_SSC_TSHR          0x34    /* Transmit Sync Holding Register */
16992 -
16993 -#define AT91_SSC_SR            0x40    /* Status Register */
16994 -#define                AT91_SSC_TXRDY          (1 <<  0)       /* Transmit Ready */
16995 -#define                AT91_SSC_TXEMPTY        (1 <<  1)       /* Transmit Empty */
16996 -#define                AT91_SSC_ENDTX          (1 <<  2)       /* End of Transmission */
16997 -#define                AT91_SSC_TXBUFE         (1 <<  3)       /* Transmit Buffer Empty */
16998 -#define                AT91_SSC_RXRDY          (1 <<  4)       /* Receive Ready */
16999 -#define                AT91_SSC_OVRUN          (1 <<  5)       /* Receive Overrun */
17000 -#define                AT91_SSC_ENDRX          (1 <<  6)       /* End of Reception */
17001 -#define                AT91_SSC_RXBUFF         (1 <<  7)       /* Receive Buffer Full */
17002 -#define                AT91_SSC_TXSYN          (1 << 10)       /* Transmit Sync */
17003 -#define                AT91_SSC_RXSYN          (1 << 11)       /* Receive Sync */
17004 -#define                AT91_SSC_TXENA          (1 << 16)       /* Transmit Enable */
17005 -#define                AT91_SSC_RXENA          (1 << 17)       /* Receive Enable */
17006 -
17007 -#define AT91_SSC_IER           0x44    /* Interrupt Enable Register */
17008 -#define AT91_SSC_IDR           0x48    /* Interrupt Disable Register */
17009 -#define AT91_SSC_IMR           0x4c    /* Interrupt Mask Register */
17010 -
17011 -#endif
17012 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
17013 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h Mon Dec  4 16:41:04 2006
17014 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h       Thu Jan  1 02:00:00 1970
17015 @@ -1,438 +0,0 @@
17016 -/*
17017 - * include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
17018 - *
17019 - * Copyright (C) 2005 Ivan Kokshaysky
17020 - * Copyright (C) SAN People
17021 - *
17022 - * System peripherals registers.
17023 - * Based on AT91RM9200 datasheet revision E.
17024 - *
17025 - * This program is free software; you can redistribute it and/or modify
17026 - * it under the terms of the GNU General Public License as published by
17027 - * the Free Software Foundation; either version 2 of the License, or
17028 - * (at your option) any later version.
17029 - */
17030 -
17031 -#ifndef AT91RM9200_SYS_H
17032 -#define AT91RM9200_SYS_H
17033 -
17034 -/*
17035 - * Advanced Interrupt Controller.
17036 - */
17037 -#define AT91_AIC       0x000
17038 -
17039 -#define AT91_AIC_SMR(n)                (AT91_AIC + ((n) * 4))  /* Source Mode Registers 0-31 */
17040 -#define                AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
17041 -#define                AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
17042 -#define                        AT91_AIC_SRCTYPE_LOW            (0 << 5)
17043 -#define                        AT91_AIC_SRCTYPE_FALLING        (1 << 5)
17044 -#define                        AT91_AIC_SRCTYPE_HIGH           (2 << 5)
17045 -#define                        AT91_AIC_SRCTYPE_RISING         (3 << 5)
17046 -
17047 -#define AT91_AIC_SVR(n)                (AT91_AIC + 0x80 + ((n) * 4))   /* Source Vector Registers 0-31 */
17048 -#define AT91_AIC_IVR           (AT91_AIC + 0x100)      /* Interrupt Vector Register */
17049 -#define AT91_AIC_FVR           (AT91_AIC + 0x104)      /* Fast Interrupt Vector Register */
17050 -#define AT91_AIC_ISR           (AT91_AIC + 0x108)      /* Interrupt Status Register */
17051 -#define                AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
17052 -
17053 -#define AT91_AIC_IPR           (AT91_AIC + 0x10c)      /* Interrupt Pending Register */
17054 -#define AT91_AIC_IMR           (AT91_AIC + 0x110)      /* Interrupt Mask Register */
17055 -#define AT91_AIC_CISR          (AT91_AIC + 0x114)      /* Core Interrupt Status Register */
17056 -#define                AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
17057 -#define                AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
17058 -
17059 -#define AT91_AIC_IECR          (AT91_AIC + 0x120)      /* Interrupt Enable Command Register */
17060 -#define AT91_AIC_IDCR          (AT91_AIC + 0x124)      /* Interrupt Disable Command Register */
17061 -#define AT91_AIC_ICCR          (AT91_AIC + 0x128)      /* Interrupt Clear Command Register */
17062 -#define AT91_AIC_ISCR          (AT91_AIC + 0x12c)      /* Interrupt Set Command Register */
17063 -#define AT91_AIC_EOICR         (AT91_AIC + 0x130)      /* End of Interrupt Command Register */
17064 -#define AT91_AIC_SPU           (AT91_AIC + 0x134)      /* Spurious Interrupt Vector Register */
17065 -#define AT91_AIC_DCR           (AT91_AIC + 0x138)      /* Debug Control Register */
17066 -#define                AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
17067 -#define                AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
17068 -
17069 -
17070 -/*
17071 - * Debug Unit.
17072 - */
17073 -#define AT91_DBGU      0x200
17074 -
17075 -#define AT91_DBGU_CR           (AT91_DBGU + 0x00)      /* Control Register */
17076 -#define AT91_DBGU_MR           (AT91_DBGU + 0x04)      /* Mode Register */
17077 -#define AT91_DBGU_IER          (AT91_DBGU + 0x08)      /* Interrupt Enable Register */
17078 -#define                AT91_DBGU_TXRDY         (1 << 1)                /* Transmitter Ready */
17079 -#define                AT91_DBGU_TXEMPTY       (1 << 9)                /* Transmitter Empty */
17080 -#define AT91_DBGU_IDR          (AT91_DBGU + 0x0c)      /* Interrupt Disable Register */
17081 -#define AT91_DBGU_IMR          (AT91_DBGU + 0x10)      /* Interrupt Mask Register */
17082 -#define AT91_DBGU_SR           (AT91_DBGU + 0x14)      /* Status Register */
17083 -#define AT91_DBGU_RHR          (AT91_DBGU + 0x18)      /* Receiver Holding Register */
17084 -#define AT91_DBGU_THR          (AT91_DBGU + 0x1c)      /* Transmitter Holding Register */
17085 -#define AT91_DBGU_BRGR         (AT91_DBGU + 0x20)      /* Baud Rate Generator Register */
17086 -
17087 -#define AT91_DBGU_CIDR         (AT91_DBGU + 0x40)      /* Chip ID Register */
17088 -#define AT91_DBGU_EXID         (AT91_DBGU + 0x44)      /* Chip ID Extension Register */
17089 -#define                AT91_CIDR_VERSION       (0x1f << 0)             /* Version of the Device */
17090 -#define                AT91_CIDR_EPROC         (7    << 5)             /* Embedded Processor */
17091 -#define                AT91_CIDR_NVPSIZ        (0xf  << 8)             /* Nonvolatile Program Memory Size */
17092 -#define                AT91_CIDR_NVPSIZ2       (0xf  << 12)            /* Second Nonvolatile Program Memory Size */
17093 -#define                AT91_CIDR_SRAMSIZ       (0xf  << 16)            /* Internal SRAM Size */
17094 -#define                AT91_CIDR_ARCH          (0xff << 20)            /* Architecture Identifier */
17095 -#define                AT91_CIDR_NVPTYP        (7    << 28)            /* Nonvolatile Program Memory Type */
17096 -#define                AT91_CIDR_EXT           (1    << 31)            /* Extension Flag */
17097 -
17098 -#define AT91_AIC_FFER          (AT91_AIC + 0x140)      /* Fast Forcing Enable Register [SAM9 only] */
17099 -#define AT91_AIC_FFDR          (AT91_AIC + 0x144)      /* Fast Forcing Disable Register [SAM9 only] */
17100 -#define AT91_AIC_FFSR          (AT91_AIC + 0x148)      /* Fast Forcing Status Register [SAM9 only] */
17101 -
17102 -/*
17103 - * PIO Controllers.
17104 - */
17105 -#define AT91_PIOA      0x400
17106 -#define AT91_PIOB      0x600
17107 -#define AT91_PIOC      0x800
17108 -#define AT91_PIOD      0xa00
17109 -
17110 -#define PIO_PER                0x00    /* Enable Register */
17111 -#define PIO_PDR                0x04    /* Disable Register */
17112 -#define PIO_PSR                0x08    /* Status Register */
17113 -#define PIO_OER                0x10    /* Output Enable Register */
17114 -#define PIO_ODR                0x14    /* Output Disable Register */
17115 -#define PIO_OSR                0x18    /* Output Status Register */
17116 -#define PIO_IFER       0x20    /* Glitch Input Filter Enable */
17117 -#define PIO_IFDR       0x24    /* Glitch Input Filter Disable */
17118 -#define PIO_IFSR       0x28    /* Glitch Input Filter Status */
17119 -#define PIO_SODR       0x30    /* Set Output Data Register */
17120 -#define PIO_CODR       0x34    /* Clear Output Data Register */
17121 -#define PIO_ODSR       0x38    /* Output Data Status Register */
17122 -#define PIO_PDSR       0x3c    /* Pin Data Status Register */
17123 -#define PIO_IER                0x40    /* Interrupt Enable Register */
17124 -#define PIO_IDR                0x44    /* Interrupt Disable Register */
17125 -#define PIO_IMR                0x48    /* Interrupt Mask Register */
17126 -#define PIO_ISR                0x4c    /* Interrupt Status Register */
17127 -#define PIO_MDER       0x50    /* Multi-driver Enable Register */
17128 -#define PIO_MDDR       0x54    /* Multi-driver Disable Register */
17129 -#define PIO_MDSR       0x58    /* Multi-driver Status Register */
17130 -#define PIO_PUDR       0x60    /* Pull-up Disable Register */
17131 -#define PIO_PUER       0x64    /* Pull-up Enable Register */
17132 -#define PIO_PUSR       0x68    /* Pull-up Status Register */
17133 -#define PIO_ASR                0x70    /* Peripheral A Select Register */
17134 -#define PIO_BSR                0x74    /* Peripheral B Select Register */
17135 -#define PIO_ABSR       0x78    /* AB Status Register */
17136 -#define PIO_OWER       0xa0    /* Output Write Enable Register */
17137 -#define PIO_OWDR       0xa4    /* Output Write Disable Register */
17138 -#define PIO_OWSR       0xa8    /* Output Write Status Register */
17139 -
17140 -#define AT91_PIO_P(n)  (1 << (n))
17141 -
17142 -
17143 -/*
17144 - * Power Management Controller.
17145 - */
17146 -#define        AT91_PMC        0xc00
17147 -
17148 -#define        AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
17149 -#define        AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
17150 -
17151 -#define        AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
17152 -#define                AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
17153 -#define                AT91_PMC_UDP            (1 <<  1)               /* USB Devcice Port Clock */
17154 -#define                AT91_PMC_MCKUDP         (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend */
17155 -#define                AT91_PMC_UHP            (1 <<  4)               /* USB Host Port Clock */
17156 -#define                AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
17157 -#define                AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
17158 -#define                AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
17159 -#define                AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
17160 -
17161 -#define        AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
17162 -#define        AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
17163 -#define        AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
17164 -
17165 -#define        AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register */
17166 -#define                AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
17167 -#define                AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
17168 -
17169 -#define        AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
17170 -#define                AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
17171 -#define                AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
17172 -
17173 -#define        AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
17174 -#define        AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
17175 -#define                AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
17176 -#define                AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
17177 -#define                AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
17178 -#define                AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
17179 -#define                AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
17180 -
17181 -#define        AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
17182 -#define                AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
17183 -#define                        AT91_PMC_CSS_SLOW               (0 << 0)
17184 -#define                        AT91_PMC_CSS_MAIN               (1 << 0)
17185 -#define                        AT91_PMC_CSS_PLLA               (2 << 0)
17186 -#define                        AT91_PMC_CSS_PLLB               (3 << 0)
17187 -#define                AT91_PMC_PRES           (7 <<  2)               /* Master Clock Prescaler */
17188 -#define                AT91_PMC_PRES_1                 (0 << 2)
17189 -#define                        AT91_PMC_PRES_2                 (1 << 2)
17190 -#define                        AT91_PMC_PRES_4                 (2 << 2)
17191 -#define                        AT91_PMC_PRES_8                 (3 << 2)
17192 -#define                        AT91_PMC_PRES_16                (4 << 2)
17193 -#define                        AT91_PMC_PRES_32                (5 << 2)
17194 -#define                        AT91_PMC_PRES_64                (6 << 2)
17195 -#define                AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
17196 -#define                        AT91_PMC_MDIV_1                 (0 << 8)
17197 -#define                        AT91_PMC_MDIV_2                 (1 << 8)
17198 -#define                        AT91_PMC_MDIV_3                 (2 << 8)
17199 -#define                        AT91_PMC_MDIV_4                 (3 << 8)
17200 -
17201 -#define        AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-3 Registers */
17202 -
17203 -#define        AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
17204 -#define        AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
17205 -#define        AT91_PMC_SR             (AT91_PMC + 0x68)       /* Status Register */
17206 -#define                AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
17207 -#define                AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
17208 -#define                AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
17209 -#define                AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
17210 -#define                AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
17211 -#define                AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
17212 -#define                AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
17213 -#define                AT91_PMC_PCK3RDY        (1 << 11)               /* Programmable Clock 3 */
17214 -#define        AT91_PMC_IMR            (AT91_PMC + 0x6c)       /* Interrupt Mask Register */
17215 -
17216 -
17217 -/*
17218 - * System Timer.
17219 - */
17220 -#define        AT91_ST         0xd00
17221 -
17222 -#define        AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
17223 -#define        AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
17224 -#define        AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
17225 -#define                AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
17226 -#define        AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
17227 -#define                AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
17228 -#define                AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
17229 -#define                AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
17230 -#define        AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
17231 -#define                AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
17232 -#define        AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
17233 -#define                AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
17234 -#define                AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
17235 -#define                AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
17236 -#define                AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
17237 -#define        AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
17238 -#define        AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
17239 -#define        AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
17240 -#define        AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
17241 -#define                AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
17242 -#define        AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
17243 -#define                AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
17244 -
17245 -
17246 -/*
17247 - * Real-time Clock.
17248 - */
17249 -#define        AT91_RTC        0xe00
17250 -
17251 -#define        AT91_RTC_CR             (AT91_RTC + 0x00)       /* Control Register */
17252 -#define                AT91_RTC_UPDTIM         (1 <<  0)               /* Update Request Time Register */
17253 -#define                AT91_RTC_UPDCAL         (1 <<  1)               /* Update Request Calendar Register */
17254 -#define                AT91_RTC_TIMEVSEL       (3 <<  8)               /* Time Event Selection */
17255 -#define                        AT91_RTC_TIMEVSEL_MINUTE        (0 << 8)
17256 -#define                AT91_RTC_TIMEVSEL_HOUR          (1 << 8)
17257 -#define                AT91_RTC_TIMEVSEL_DAY24         (2 << 8)
17258 -#define                AT91_RTC_TIMEVSEL_DAY12         (3 << 8)
17259 -#define                AT91_RTC_CALEVSEL       (3 << 16)               /* Calendar Event Selection */
17260 -#define                AT91_RTC_CALEVSEL_WEEK          (0 << 16)
17261 -#define                AT91_RTC_CALEVSEL_MONTH         (1 << 16)
17262 -#define                AT91_RTC_CALEVSEL_YEAR          (2 << 16)
17263 -
17264 -#define        AT91_RTC_MR             (AT91_RTC + 0x04)       /* Mode Register */
17265 -#define        AT91_RTC_HRMOD          (1 <<  0)               /* 12/24 Hour Mode */
17266 -
17267 -#define        AT91_RTC_TIMR           (AT91_RTC + 0x08)       /* Time Register */
17268 -#define                AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
17269 -#define                AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
17270 -#define                AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
17271 -#define                AT91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
17272 -
17273 -#define        AT91_RTC_CALR           (AT91_RTC + 0x0c)       /* Calendar Register */
17274 -#define                AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
17275 -#define                AT91_RTC_YEAR           (0xff <<  8)            /* Current Year */
17276 -#define                AT91_RTC_MONTH          (0x1f << 16)            /* Current Month */
17277 -#define                AT91_RTC_DAY            (7    << 21)            /* Current Day */
17278 -#define                AT91_RTC_DATE           (0x3f << 24)            /* Current Date */
17279 -
17280 -#define        AT91_RTC_TIMALR         (AT91_RTC + 0x10)       /* Time Alarm Register */
17281 -#define                AT91_RTC_SECEN          (1 <<  7)               /* Second Alarm Enable */
17282 -#define                AT91_RTC_MINEN          (1 << 15)               /* Minute Alarm Enable */
17283 -#define                AT91_RTC_HOUREN         (1 << 23)               /* Hour Alarm Enable */
17284 -
17285 -#define        AT91_RTC_CALALR         (AT91_RTC + 0x14)       /* Calendar Alarm Register */
17286 -#define                AT91_RTC_MTHEN          (1 << 23)               /* Month Alarm Enable */
17287 -#define                AT91_RTC_DATEEN         (1 << 31)               /* Date Alarm Enable */
17288 -
17289 -#define        AT91_RTC_SR             (AT91_RTC + 0x18)       /* Status Register */
17290 -#define                AT91_RTC_ACKUPD         (1 <<  0)               /* Acknowledge for Update */
17291 -#define                AT91_RTC_ALARM          (1 <<  1)               /* Alarm Flag */
17292 -#define                AT91_RTC_SECEV          (1 <<  2)               /* Second Event */
17293 -#define                AT91_RTC_TIMEV          (1 <<  3)               /* Time Event */
17294 -#define                AT91_RTC_CALEV          (1 <<  4)               /* Calendar Event */
17295 -
17296 -#define        AT91_RTC_SCCR           (AT91_RTC + 0x1c)       /* Status Clear Command Register */
17297 -#define        AT91_RTC_IER            (AT91_RTC + 0x20)       /* Interrupt Enable Register */
17298 -#define        AT91_RTC_IDR            (AT91_RTC + 0x24)       /* Interrupt Disable Register */
17299 -#define        AT91_RTC_IMR            (AT91_RTC + 0x28)       /* Interrupt Mask Register */
17300 -
17301 -#define        AT91_RTC_VER            (AT91_RTC + 0x2c)       /* Valid Entry Register */
17302 -#define                AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
17303 -#define                AT91_RTC_NVCAL          (1 <<  1)               /* Non valid Calendar */
17304 -#define                AT91_RTC_NVTIMALR       (1 <<  2)               /* Non valid Time Alarm */
17305 -#define                AT91_RTC_NVCALALR       (1 <<  3)               /* Non valid Calendar Alarm */
17306 -
17307 -
17308 -/*
17309 - * Memory Controller.
17310 - */
17311 -#define AT91_MC                0xf00
17312 -
17313 -#define AT91_MC_RCR            (AT91_MC + 0x00)        /* MC Remap Control Register */
17314 -#define                AT91_MC_RCB             (1 <<  0)               /* Remap Command Bit */
17315 -
17316 -#define AT91_MC_ASR            (AT91_MC + 0x04)        /* MC Abort Status Register */
17317 -#define                AT91_MC_UNADD           (1 <<  0)               /* Undefined Address Abort Status */
17318 -#define                AT91_MC_MISADD          (1 <<  1)               /* Misaligned Address Abort Status */
17319 -#define                AT91_MC_ABTSZ           (3 <<  8)               /* Abort Size Status */
17320 -#define                        AT91_MC_ABTSZ_BYTE              (0 << 8)
17321 -#define                        AT91_MC_ABTSZ_HALFWORD          (1 << 8)
17322 -#define                        AT91_MC_ABTSZ_WORD              (2 << 8)
17323 -#define                AT91_MC_ABTTYP          (3 << 10)               /* Abort Type Status */
17324 -#define                        AT91_MC_ABTTYP_DATAREAD         (0 << 10)
17325 -#define                        AT91_MC_ABTTYP_DATAWRITE        (1 << 10)
17326 -#define                        AT91_MC_ABTTYP_FETCH            (2 << 10)
17327 -#define                AT91_MC_MST0            (1 << 16)               /* ARM920T Abort Source */
17328 -#define                AT91_MC_MST1            (1 << 17)               /* PDC Abort Source */
17329 -#define                AT91_MC_MST2            (1 << 18)               /* UHP Abort Source */
17330 -#define                AT91_MC_MST3            (1 << 19)               /* EMAC Abort Source */
17331 -#define                AT91_MC_SVMST0          (1 << 24)               /* Saved ARM920T Abort Source */
17332 -#define                AT91_MC_SVMST1          (1 << 25)               /* Saved PDC Abort Source */
17333 -#define                AT91_MC_SVMST2          (1 << 26)               /* Saved UHP Abort Source */
17334 -#define                AT91_MC_SVMST3          (1 << 27)               /* Saved EMAC Abort Source */
17335 -
17336 -#define AT91_MC_AASR           (AT91_MC + 0x08)        /* MC Abort Address Status Register */
17337 -
17338 -#define AT91_MC_MPR            (AT91_MC + 0x0c)        /* MC Master Priority Register */
17339 -#define                AT91_MPR_MSTP0          (7 <<  0)               /* ARM920T Priority */
17340 -#define                AT91_MPR_MSTP1          (7 <<  4)               /* PDC Priority */
17341 -#define                AT91_MPR_MSTP2          (7 <<  8)               /* UHP Priority */
17342 -#define                AT91_MPR_MSTP3          (7 << 12)               /* EMAC Priority */
17343 -
17344 -/* External Bus Interface (EBI) registers */
17345 -#define AT91_EBI_CSA           (AT91_MC + 0x60)        /* Chip Select Assignment Register */
17346 -#define                AT91_EBI_CS0A           (1 << 0)                /* Chip Select 0 Assignment */
17347 -#define                        AT91_EBI_CS0A_SMC               (0 << 0)
17348 -#define                        AT91_EBI_CS0A_BFC               (1 << 0)
17349 -#define                AT91_EBI_CS1A           (1 << 1)                /* Chip Select 1 Assignment */
17350 -#define                        AT91_EBI_CS1A_SMC               (0 << 1)
17351 -#define                        AT91_EBI_CS1A_SDRAMC            (1 << 1)
17352 -#define                AT91_EBI_CS3A           (1 << 3)                /* Chip Select 2 Assignment */
17353 -#define                        AT91_EBI_CS3A_SMC               (0 << 3)
17354 -#define                        AT91_EBI_CS3A_SMC_SMARTMEDIA    (1 << 3)
17355 -#define                AT91_EBI_CS4A           (1 << 4)                /* Chip Select 3 Assignment */
17356 -#define                        AT91_EBI_CS4A_SMC               (0 << 4)
17357 -#define                        AT91_EBI_CS4A_SMC_COMPACTFLASH  (1 << 4)
17358 -#define AT91_EBI_CFGR          (AT91_MC + 0x64)        /* Configuration Register */
17359 -#define                AT91_EBI_DBPUC          (1 << 0)                /* Data Bus Pull-Up Configuration */
17360 -
17361 -/* Static Memory Controller (SMC) registers */
17362 -#define        AT91_SMC_CSR(n)         (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
17363 -#define                AT91_SMC_NWS            (0x7f <<  0)            /* Number of Wait States */
17364 -#define                        AT91_SMC_NWS_(x)        ((x) << 0)
17365 -#define                AT91_SMC_WSEN           (1    <<  7)            /* Wait State Enable */
17366 -#define                AT91_SMC_TDF            (0xf  <<  8)            /* Data Float Time */
17367 -#define                        AT91_SMC_TDF_(x)        ((x) << 8)
17368 -#define                AT91_SMC_BAT            (1    << 12)            /* Byte Access Type */
17369 -#define                AT91_SMC_DBW            (3    << 13)            /* Data Bus Width */
17370 -#define                        AT91_SMC_DBW_16         (1 << 13)
17371 -#define                        AT91_SMC_DBW_8          (2 << 13)
17372 -#define                AT91_SMC_DPR            (1 << 15)               /* Data Read Protocol */
17373 -#define                AT91_SMC_ACSS           (3 << 16)               /* Address to Chip Select Setup */
17374 -#define                        AT91_SMC_ACSS_STD       (0 << 16)
17375 -#define                        AT91_SMC_ACSS_1         (1 << 16)
17376 -#define                        AT91_SMC_ACSS_2         (2 << 16)
17377 -#define                        AT91_SMC_ACSS_3         (3 << 16)
17378 -#define                AT91_SMC_RWSETUP        (7 << 24)               /* Read & Write Signal Time Setup */
17379 -#define                        AT91_SMC_RWSETUP_(x)    ((x) << 24)
17380 -#define                AT91_SMC_RWHOLD         (7 << 28)               /* Read & Write Signal Hold Time */
17381 -#define                        AT91_SMC_RWHOLD_(x)     ((x) << 28)
17382 -
17383 -/* SDRAM Controller registers */
17384 -#define AT91_SDRAMC_MR         (AT91_MC + 0x90)        /* Mode Register */
17385 -#define                AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
17386 -#define                        AT91_SDRAMC_MODE_NORMAL         (0 << 0)
17387 -#define                        AT91_SDRAMC_MODE_NOP            (1 << 0)
17388 -#define                        AT91_SDRAMC_MODE_PRECHARGE      (2 << 0)
17389 -#define                        AT91_SDRAMC_MODE_LMR            (3 << 0)
17390 -#define                        AT91_SDRAMC_MODE_REFRESH        (4 << 0)
17391 -#define                AT91_SDRAMC_DBW         (1   << 4)              /* Data Bus Width */
17392 -#define                        AT91_SDRAMC_DBW_32      (0 << 4)
17393 -#define                        AT91_SDRAMC_DBW_16      (1 << 4)
17394 -
17395 -#define AT91_SDRAMC_TR         (AT91_MC + 0x94)        /* Refresh Timer Register */
17396 -#define                AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Count */
17397 -
17398 -#define AT91_SDRAMC_CR         (AT91_MC + 0x98)        /* Configuration Register */
17399 -#define                AT91_SDRAMC_NC          (3   <<  0)             /* Number of Column Bits */
17400 -#define                        AT91_SDRAMC_NC_8        (0 << 0)
17401 -#define                        AT91_SDRAMC_NC_9        (1 << 0)
17402 -#define                        AT91_SDRAMC_NC_10       (2 << 0)
17403 -#define                        AT91_SDRAMC_NC_11       (3 << 0)
17404 -#define                AT91_SDRAMC_NR          (3   <<  2)             /* Number of Row Bits */
17405 -#define                        AT91_SDRAMC_NR_11       (0 << 2)
17406 -#define                        AT91_SDRAMC_NR_12       (1 << 2)
17407 -#define                        AT91_SDRAMC_NR_13       (2 << 2)
17408 -#define                AT91_SDRAMC_NB          (1   <<  4)             /* Number of Banks */
17409 -#define                        AT91_SDRAMC_NB_2        (0 << 4)
17410 -#define                        AT91_SDRAMC_NB_4        (1 << 4)
17411 -#define                AT91_SDRAMC_CAS         (3   <<  5)             /* CAS Latency */
17412 -#define                        AT91_SDRAMC_CAS_2       (2 << 5)
17413 -#define                AT91_SDRAMC_TWR         (0xf <<  7)             /* Write Recovery Delay */
17414 -#define                AT91_SDRAMC_TRC         (0xf << 11)             /* Row Cycle Delay */
17415 -#define                AT91_SDRAMC_TRP         (0xf << 15)             /* Row Precharge Delay */
17416 -#define                AT91_SDRAMC_TRCD        (0xf << 19)             /* Row to Column Delay */
17417 -#define                AT91_SDRAMC_TRAS        (0xf << 23)             /* Active to Precharge Delay */
17418 -#define                AT91_SDRAMC_TXSR        (0xf << 27)             /* Exit Self Refresh to Active Delay */
17419 -
17420 -#define AT91_SDRAMC_SRR                (AT91_MC + 0x9c)        /* Self Refresh Register */
17421 -#define AT91_SDRAMC_LPR                (AT91_MC + 0xa0)        /* Low Power Register */
17422 -#define AT91_SDRAMC_IER                (AT91_MC + 0xa4)        /* Interrupt Enable Register */
17423 -#define AT91_SDRAMC_IDR                (AT91_MC + 0xa8)        /* Interrupt Disable Register */
17424 -#define AT91_SDRAMC_IMR                (AT91_MC + 0xac)        /* Interrupt Mask Register */
17425 -#define AT91_SDRAMC_ISR                (AT91_MC + 0xb0)        /* Interrupt Status Register */
17426 -
17427 -/* Burst Flash Controller register */
17428 -#define AT91_BFC_MR            (AT91_MC + 0xc0)        /* Mode Register */
17429 -#define                AT91_BFC_BFCOM          (3   <<  0)             /* Burst Flash Controller Operating Mode */
17430 -#define                        AT91_BFC_BFCOM_DISABLED (0 << 0)
17431 -#define                        AT91_BFC_BFCOM_ASYNC    (1 << 0)
17432 -#define                        AT91_BFC_BFCOM_BURST    (2 << 0)
17433 -#define                AT91_BFC_BFCC           (3   <<  2)             /* Burst Flash Controller Clock */
17434 -#define                        AT91_BFC_BFCC_MCK       (1 << 2)
17435 -#define                        AT91_BFC_BFCC_DIV2      (2 << 2)
17436 -#define                        AT91_BFC_BFCC_DIV4      (3 << 2)
17437 -#define                AT91_BFC_AVL            (0xf <<  4)             /* Address Valid Latency */
17438 -#define                AT91_BFC_PAGES          (7   <<  8)             /* Page Size */
17439 -#define                        AT91_BFC_PAGES_NO_PAGE  (0 << 8)
17440 -#define                        AT91_BFC_PAGES_16       (1 << 8)
17441 -#define                        AT91_BFC_PAGES_32       (2 << 8)
17442 -#define                        AT91_BFC_PAGES_64       (3 << 8)
17443 -#define                        AT91_BFC_PAGES_128      (4 << 8)
17444 -#define                        AT91_BFC_PAGES_256      (5 << 8)
17445 -#define                        AT91_BFC_PAGES_512      (6 << 8)
17446 -#define                        AT91_BFC_PAGES_1024     (7 << 8)
17447 -#define                AT91_BFC_OEL            (3   << 12)             /* Output Enable Latency */
17448 -#define                AT91_BFC_BAAEN          (1   << 16)             /* Burst Address Advance Enable */
17449 -#define                AT91_BFC_BFOEH          (1   << 17)             /* Burst Flash Output Enable Handling */
17450 -#define                AT91_BFC_MUXEN          (1   << 18)             /* Multiplexed Bus Enable */
17451 -#define                AT91_BFC_RDYEN          (1   << 19)             /* Ready Enable Mode */
17452 -
17453 -#endif
17454 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
17455 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h  Mon Dec  4 16:34:19 2006
17456 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h        Thu Jan  1 02:00:00 1970
17457 @@ -1,146 +0,0 @@
17458 -/*
17459 - * include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
17460 - *
17461 - * Copyright (C) SAN People
17462 - *
17463 - * Timer/Counter Unit (TC) registers.
17464 - * Based on AT91RM9200 datasheet revision E.
17465 - *
17466 - * This program is free software; you can redistribute it and/or modify
17467 - * it under the terms of the GNU General Public License as published by
17468 - * the Free Software Foundation; either version 2 of the License, or
17469 - * (at your option) any later version.
17470 - */
17471 -
17472 -#ifndef AT91RM9200_TC_H
17473 -#define AT91RM9200_TC_H
17474 -
17475 -#define AT91_TC_BCR            0xc0            /* TC Block Control Register */
17476 -#define                AT91_TC_SYNC            (1 << 0)        /* Synchro Command */
17477 -
17478 -#define AT91_TC_BMR            0xc4            /* TC Block Mode Register */
17479 -#define                AT91_TC_TC0XC0S         (3 << 0)        /* External Clock Signal 0 Selection */
17480 -#define                        AT91_TC_TC0XC0S_TCLK0           (0 << 0)
17481 -#define                        AT91_TC_TC0XC0S_NONE            (1 << 0)
17482 -#define                        AT91_TC_TC0XC0S_TIOA1           (2 << 0)
17483 -#define                        AT91_TC_TC0XC0S_TIOA2           (3 << 0)
17484 -#define                AT91_TC_TC1XC1S         (3 << 2)        /* External Clock Signal 1 Selection */
17485 -#define                        AT91_TC_TC1XC1S_TCLK1           (0 << 2)
17486 -#define                        AT91_TC_TC1XC1S_NONE            (1 << 2)
17487 -#define                        AT91_TC_TC1XC1S_TIOA0           (2 << 2)
17488 -#define                        AT91_TC_TC1XC1S_TIOA2           (3 << 2)
17489 -#define                AT91_TC_TC2XC2S         (3 << 4)        /* External Clock Signal 2 Selection */
17490 -#define                        AT91_TC_TC2XC2S_TCLK2           (0 << 4)
17491 -#define                        AT91_TC_TC2XC2S_NONE            (1 << 4)
17492 -#define                        AT91_TC_TC2XC2S_TIOA0           (2 << 4)
17493 -#define                        AT91_TC_TC2XC2S_TIOA1           (3 << 4)
17494 -
17495 -
17496 -#define AT91_TC_CCR            0x00            /* Channel Control Register */
17497 -#define                AT91_TC_CLKEN           (1 << 0)        /* Counter Clock Enable Command */
17498 -#define                AT91_TC_CLKDIS          (1 << 1)        /* Counter CLock Disable Command */
17499 -#define                AT91_TC_SWTRG           (1 << 2)        /* Software Trigger Command */
17500 -
17501 -#define AT91_TC_CMR            0x04            /* Channel Mode Register */
17502 -#define                AT91_TC_TCCLKS          (7 << 0)        /* Capture/Waveform Mode: Clock Selection */
17503 -#define                        AT91_TC_TIMER_CLOCK1            (0 << 0)
17504 -#define                        AT91_TC_TIMER_CLOCK2            (1 << 0)
17505 -#define                        AT91_TC_TIMER_CLOCK3            (2 << 0)
17506 -#define                        AT91_TC_TIMER_CLOCK4            (3 << 0)
17507 -#define                        AT91_TC_TIMER_CLOCK5            (4 << 0)
17508 -#define                        AT91_TC_XC0                     (5 << 0)
17509 -#define                        AT91_TC_XC1                     (6 << 0)
17510 -#define                        AT91_TC_XC2                     (7 << 0)
17511 -#define                AT91_TC_CLKI            (1 << 3)        /* Capture/Waveform Mode: Clock Invert */
17512 -#define                AT91_TC_BURST           (3 << 4)        /* Capture/Waveform Mode: Burst Signal Selection */
17513 -#define                AT91_TC_LDBSTOP         (1 << 6)        /* Capture Mode: Counter Clock Stopped with TB Loading */
17514 -#define                AT91_TC_LDBDIS          (1 << 7)        /* Capture Mode: Counter Clock Disable with RB Loading */
17515 -#define                AT91_TC_ETRGEDG         (3 << 8)        /* Capture Mode: External Trigger Edge Selection */
17516 -#define                AT91_TC_ABETRG          (1 << 10)       /* Capture Mode: TIOA or TIOB External Trigger Selection */
17517 -#define                AT91_TC_CPCTRG          (1 << 14)       /* Capture Mode: RC Compare Trigger Enable */
17518 -#define                AT91_TC_WAVE            (1 << 15)       /* Capture/Waveform mode */
17519 -#define                AT91_TC_LDRA            (3 << 16)       /* Capture Mode: RA Loading Selection */
17520 -#define                AT91_TC_LDRB            (3 << 18)       /* Capture Mode: RB Loading Selection */
17521 -
17522 -#define                AT91_TC_CPCSTOP         (1 <<  6)       /* Waveform Mode: Counter Clock Stopped with RC Compare */
17523 -#define                AT91_TC_CPCDIS          (1 <<  7)       /* Waveform Mode: Counter Clock Disable with RC Compare */
17524 -#define                AT91_TC_EEVTEDG         (3 <<  8)       /* Waveform Mode: External Event Edge Selection */
17525 -#define                        AT91_TC_EEVTEDG_NONE            (0 << 8)
17526 -#define                        AT91_TC_EEVTEDG_RISING          (1 << 8)
17527 -#define                        AT91_TC_EEVTEDG_FALLING         (2 << 8)
17528 -#define                        AT91_TC_EEVTEDG_BOTH            (3 << 8)
17529 -#define                AT91_TC_EEVT            (3 << 10)       /* Waveform Mode: External Event Selection */
17530 -#define                        AT91_TC_EEVT_TIOB               (0 << 10)
17531 -#define                        AT91_TC_EEVT_XC0                (1 << 10)
17532 -#define                        AT91_TC_EEVT_XC1                (2 << 10)
17533 -#define                        AT91_TC_EEVT_XC2                (3 << 10)
17534 -#define                AT91_TC_ENETRG          (1 << 12)       /* Waveform Mode: External Event Trigger Enable */
17535 -#define                AT91_TC_WAVESEL         (3 << 13)       /* Waveform Mode: Waveform Selection */
17536 -#define                        AT91_TC_WAVESEL_UP              (0 << 13)
17537 -#define                        AT91_TC_WAVESEL_UP_AUTO         (2 << 13)
17538 -#define                        AT91_TC_WAVESEL_UPDOWN          (1 << 13)
17539 -#define                        AT91_TC_WAVESEL_UPDOWN_AUTO     (3 << 13)
17540 -#define                AT91_TC_ACPA            (3 << 16)       /* Waveform Mode: RA Compare Effect on TIOA */
17541 -#define                        AT91_TC_ACPA_NONE               (0 << 16)
17542 -#define                        AT91_TC_ACPA_SET                (1 << 16)
17543 -#define                        AT91_TC_ACPA_CLEAR              (2 << 16)
17544 -#define                        AT91_TC_ACPA_TOGGLE             (3 << 16)
17545 -#define                AT91_TC_ACPC            (3 << 18)       /* Waveform Mode: RC Compre Effect on TIOA */
17546 -#define                        AT91_TC_ACPC_NONE               (0 << 18)
17547 -#define                        AT91_TC_ACPC_SET                (1 << 18)
17548 -#define                        AT91_TC_ACPC_CLEAR              (2 << 18)
17549 -#define                        AT91_TC_ACPC_TOGGLE             (3 << 18)
17550 -#define                AT91_TC_AEEVT           (3 << 20)       /* Waveform Mode: External Event Effect on TIOA */
17551 -#define                        AT91_TC_AEEVT_NONE              (0 << 20)
17552 -#define                        AT91_TC_AEEVT_SET               (1 << 20)
17553 -#define                        AT91_TC_AEEVT_CLEAR             (2 << 20)
17554 -#define                        AT91_TC_AEEVT_TOGGLE            (3 << 20)
17555 -#define                AT91_TC_ASWTRG          (3 << 22)       /* Waveform Mode: Software Trigger Effect on TIOA */
17556 -#define                        AT91_TC_ASWTRG_NONE             (0 << 22)
17557 -#define                        AT91_TC_ASWTRG_SET              (1 << 22)
17558 -#define                        AT91_TC_ASWTRG_CLEAR            (2 << 22)
17559 -#define                        AT91_TC_ASWTRG_TOGGLE           (3 << 22)
17560 -#define                AT91_TC_BCPB            (3 << 24)       /* Waveform Mode: RB Compare Effect on TIOB */
17561 -#define                        AT91_TC_BCPB_NONE               (0 << 24)
17562 -#define                        AT91_TC_BCPB_SET                (1 << 24)
17563 -#define                        AT91_TC_BCPB_CLEAR              (2 << 24)
17564 -#define                        AT91_TC_BCPB_TOGGLE             (3 << 24)
17565 -#define                AT91_TC_BCPC            (3 << 26)       /* Waveform Mode: RC Compare Effect on TIOB */
17566 -#define                        AT91_TC_BCPC_NONE               (0 << 26)
17567 -#define                        AT91_TC_BCPC_SET                (1 << 26)
17568 -#define                        AT91_TC_BCPC_CLEAR              (2 << 26)
17569 -#define                        AT91_TC_BCPC_TOGGLE             (3 << 26)
17570 -#define                AT91_TC_BEEVT           (3 << 28)       /* Waveform Mode: External Event Effect on TIOB */
17571 -#define                        AT91_TC_BEEVT_NONE              (0 << 28)
17572 -#define                        AT91_TC_BEEVT_SET               (1 << 28)
17573 -#define                        AT91_TC_BEEVT_CLEAR             (2 << 28)
17574 -#define                        AT91_TC_BEEVT_TOGGLE            (3 << 28)
17575 -#define                AT91_TC_BSWTRG          (3 << 30)       /* Waveform Mode: Software Trigger Effect on TIOB */
17576 -#define                        AT91_TC_BSWTRG_NONE             (0 << 30)
17577 -#define                        AT91_TC_BSWTRG_SET              (1 << 30)
17578 -#define                        AT91_TC_BSWTRG_CLEAR            (2 << 30)
17579 -#define                        AT91_TC_BSWTRG_TOGGLE           (3 << 30)
17580 -
17581 -#define AT91_TC_CV             0x10            /* Counter Value */
17582 -#define AT91_TC_RA             0x14            /* Register A */
17583 -#define AT91_TC_RB             0x18            /* Register B */
17584 -#define AT91_TC_RC             0x1c            /* Register C */
17585 -
17586 -#define AT91_TC_SR             0x20            /* Status Register */
17587 -#define                AT91_TC_COVFS           (1 <<  0)       /* Counter Overflow Status */
17588 -#define                AT91_TC_LOVRS           (1 <<  1)       /* Load Overrun Status */
17589 -#define                AT91_TC_CPAS            (1 <<  2)       /* RA Compare Status */
17590 -#define                AT91_TC_CPBS            (1 <<  3)       /* RB Compare Status */
17591 -#define                AT91_TC_CPCS            (1 <<  4)       /* RC Compare Status */
17592 -#define                AT91_TC_LDRAS           (1 <<  5)       /* RA Loading Status */
17593 -#define                AT91_TC_LDRBS           (1 <<  6)       /* RB Loading Status */
17594 -#define                AT91_TC_ETRGS           (1 <<  7)       /* External Trigger Status */
17595 -#define                AT91_TC_CLKSTA          (1 << 16)       /* Clock Enabling Status */
17596 -#define                AT91_TC_MTIOA           (1 << 17)       /* TIOA Mirror */
17597 -#define                AT91_TC_MTIOB           (1 << 18)       /* TIOB Mirror */
17598 -
17599 -#define AT91_TC_IER            0x24            /* Interrupt Enable Register */
17600 -#define AT91_TC_IDR            0x28            /* Interrupt Disable Register */
17601 -#define AT91_TC_IMR            0x2c            /* Interrupt Mask Register */
17602 -
17603 -#endif
17604 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
17605 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h Mon Dec  4 16:41:04 2006
17606 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h       Thu Jan  1 02:00:00 1970
17607 @@ -1,57 +0,0 @@
17608 -/*
17609 - * include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
17610 - *
17611 - * Copyright (C) 2005 Ivan Kokshaysky
17612 - * Copyright (C) SAN People
17613 - *
17614 - * Two-wire Interface (TWI) registers.
17615 - * Based on AT91RM9200 datasheet revision E.
17616 - *
17617 - * This program is free software; you can redistribute it and/or modify
17618 - * it under the terms of the GNU General Public License as published by
17619 - * the Free Software Foundation; either version 2 of the License, or
17620 - * (at your option) any later version.
17621 - */
17622 -
17623 -#ifndef AT91RM9200_TWI_H
17624 -#define AT91RM9200_TWI_H
17625 -
17626 -#define        AT91_TWI_CR             0x00            /* Control Register */
17627 -#define                AT91_TWI_START          (1 <<  0)       /* Send a Start Condition */
17628 -#define                AT91_TWI_STOP           (1 <<  1)       /* Send a Stop Condition */
17629 -#define                AT91_TWI_MSEN           (1 <<  2)       /* Master Transfer Enable */
17630 -#define                AT91_TWI_MSDIS          (1 <<  3)       /* Master Transfer Disable */
17631 -#define                AT91_TWI_SWRST          (1 <<  7)       /* Software Reset */
17632 -
17633 -#define        AT91_TWI_MMR            0x04            /* Master Mode Register */
17634 -#define                AT91_TWI_IADRSZ         (3    <<  8)    /* Internal Device Address Size */
17635 -#define                        AT91_TWI_IADRSZ_NO              (0 << 8)
17636 -#define                        AT91_TWI_IADRSZ_1               (1 << 8)
17637 -#define                        AT91_TWI_IADRSZ_2               (2 << 8)
17638 -#define                        AT91_TWI_IADRSZ_3               (3 << 8)
17639 -#define                AT91_TWI_MREAD          (1    << 12)    /* Master Read Direction */
17640 -#define                AT91_TWI_DADR           (0x7f << 16)    /* Device Address */
17641 -
17642 -#define        AT91_TWI_IADR           0x0c            /* Internal Address Register */
17643 -
17644 -#define        AT91_TWI_CWGR           0x10            /* Clock Waveform Generator Register */
17645 -#define                AT91_TWI_CLDIV          (0xff <<  0)    /* Clock Low Divisor */
17646 -#define                AT91_TWI_CHDIV          (0xff <<  8)    /* Clock High Divisor */
17647 -#define                AT91_TWI_CKDIV          (7    << 16)    /* Clock Divider */
17648 -
17649 -#define        AT91_TWI_SR             0x20            /* Status Register */
17650 -#define                AT91_TWI_TXCOMP         (1 <<  0)       /* Transmission Complete */
17651 -#define                AT91_TWI_RXRDY          (1 <<  1)       /* Receive Holding Register Ready */
17652 -#define                AT91_TWI_TXRDY          (1 <<  2)       /* Transmit Holding Register Ready */
17653 -#define                AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error */
17654 -#define                AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error */
17655 -#define                AT91_TWI_NACK           (1 <<  8)       /* Not Acknowledged */
17656 -
17657 -#define        AT91_TWI_IER            0x24            /* Interrupt Enable Register */
17658 -#define        AT91_TWI_IDR            0x28            /* Interrupt Disable Register */
17659 -#define        AT91_TWI_IMR            0x2c            /* Interrupt Mask Register */
17660 -#define        AT91_TWI_RHR            0x30            /* Receive Holding Register */
17661 -#define        AT91_TWI_THR            0x34            /* Transmit Holding Register */
17662 -
17663 -#endif
17664 -
17665 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
17666 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h Mon Dec  4 16:34:19 2006
17667 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h       Thu Jan  1 02:00:00 1970
17668 @@ -1,77 +0,0 @@
17669 -/*
17670 - * include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
17671 - *
17672 - * Copyright (C) 2005 Ivan Kokshaysky
17673 - * Copyright (C) SAN People
17674 - *
17675 - * USB Device Port (UDP) registers.
17676 - * Based on AT91RM9200 datasheet revision E.
17677 - *
17678 - * This program is free software; you can redistribute it and/or modify
17679 - * it under the terms of the GNU General Public License as published by
17680 - * the Free Software Foundation; either version 2 of the License, or
17681 - * (at your option) any later version.
17682 - */
17683 -
17684 -#ifndef AT91RM9200_UDP_H
17685 -#define AT91RM9200_UDP_H
17686 -
17687 -#define AT91_UDP_FRM_NUM       0x00            /* Frame Number Register */
17688 -#define                AT91_UDP_NUM            (0x7ff <<  0)           /* Frame Number */
17689 -#define                AT91_UDP_FRM_ERR        (1     << 16)           /* Frame Error */
17690 -#define                AT91_UDP_FRM_OK         (1     << 17)           /* Frame OK */
17691 -
17692 -#define AT91_UDP_GLB_STAT      0x04            /* Global State Register */
17693 -#define                AT91_UDP_FADDEN         (1 <<  0)               /* Function Address Enable */
17694 -#define                AT91_UDP_CONFG          (1 <<  1)               /* Configured */
17695 -#define                AT91_UDP_ESR            (1 <<  2)               /* Enable Send Resume */
17696 -#define                AT91_UDP_RSMINPR        (1 <<  3)               /* Resume has been sent */
17697 -#define                AT91_UDP_RMWUPE         (1 <<  4)               /* Remote Wake Up Enable */
17698 -
17699 -#define AT91_UDP_FADDR         0x08            /* Function Address Register */
17700 -#define                AT91_UDP_FADD           (0x7f << 0)             /* Function Address Value */
17701 -#define                AT91_UDP_FEN            (1    << 8)             /* Function Enable */
17702 -
17703 -#define AT91_UDP_IER           0x10            /* Interrupt Enable Register */
17704 -#define AT91_UDP_IDR           0x14            /* Interrupt Disable Register */
17705 -#define AT91_UDP_IMR           0x18            /* Interrupt Mask Register */
17706 -
17707 -#define AT91_UDP_ISR           0x1c            /* Interrupt Status Register */
17708 -#define                AT91_UDP_EP(n)          (1 << (n))              /* Endpoint Interrupt Status */
17709 -#define                AT91_UDP_RXSUSP         (1 <<  8)               /* USB Suspend Interrupt Status */
17710 -#define                AT91_UDP_RXRSM          (1 <<  9)               /* USB Resume Interrupt Status */
17711 -#define                AT91_UDP_EXTRSM         (1 << 10)               /* External Resume Interrupt Status */
17712 -#define                AT91_UDP_SOFINT         (1 << 11)               /* Start of Frame Interrupt Status */
17713 -#define                AT91_UDP_ENDBUSRES      (1 << 12)               /* End of Bus Reset Interrpt Status */
17714 -#define                AT91_UDP_WAKEUP         (1 << 13)               /* USB Wakeup Interrupt Status */
17715 -
17716 -#define AT91_UDP_ICR           0x20            /* Interrupt Clear Register */
17717 -#define AT91_UDP_RST_EP                0x28            /* Reset Endpoint Register */
17718 -
17719 -#define AT91_UDP_CSR(n)                (0x30 + ((n) * 4))      /* Endpoint Control/Status Registers 0-7 */
17720 -#define                AT91_UDP_TXCOMP         (1 <<  0)               /* Generates IN packet with data previously written in DPR */
17721 -#define                AT91_UDP_RX_DATA_BK0    (1 <<  1)               /* Receive Data Bank 0 */
17722 -#define                AT91_UDP_RXSETUP        (1 <<  2)               /* Send STALL to the host */
17723 -#define                AT91_UDP_STALLSENT      (1 <<  3)               /* Stall Sent / Isochronous error (Isochronous endpoints) */
17724 -#define                AT91_UDP_TXPKTRDY       (1 <<  4)               /* Transmit Packet Ready */
17725 -#define                AT91_UDP_FORCESTALL     (1 <<  5)               /* Force Stall */
17726 -#define                AT91_UDP_RX_DATA_BK1    (1 <<  6)               /* Receive Data Bank 1 */
17727 -#define                AT91_UDP_DIR            (1 <<  7)               /* Transfer Direction */
17728 -#define                AT91_UDP_EPTYPE         (7 <<  8)               /* Endpoint Type */
17729 -#define                        AT91_UDP_EPTYPE_CTRL            (0 <<  8)
17730 -#define                        AT91_UDP_EPTYPE_ISO_OUT         (1 <<  8)
17731 -#define                        AT91_UDP_EPTYPE_BULK_OUT        (2 <<  8)
17732 -#define                        AT91_UDP_EPTYPE_INT_OUT         (3 <<  8)
17733 -#define                        AT91_UDP_EPTYPE_ISO_IN          (5 <<  8)
17734 -#define                        AT91_UDP_EPTYPE_BULK_IN         (6 <<  8)
17735 -#define                        AT91_UDP_EPTYPE_INT_IN          (7 <<  8)
17736 -#define                AT91_UDP_DTGLE          (1 << 11)               /* Data Toggle */
17737 -#define                AT91_UDP_EPEDS          (1 << 15)               /* Endpoint Enable/Disable */
17738 -#define                AT91_UDP_RXBYTECNT      (0x7ff << 16)           /* Number of bytes in FIFO */
17739 -
17740 -#define AT91_UDP_FDR(n)                (0x50 + ((n) * 4))      /* Endpoint FIFO Data Registers 0-7 */
17741 -
17742 -#define AT91_UDP_TXVC          0x74            /* Transceiver Control Register */
17743 -#define                AT91_UDP_TXVC_TXVDIS    (1 << 8)                /* Transceiver Disable */
17744 -
17745 -#endif
17746 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9260.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9260.h
17747 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9260.h    Thu Jan  1 02:00:00 1970
17748 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9260.h  Wed Nov 15 08:54:30 2006
17749 @@ -0,0 +1,125 @@
17750 +/*
17751 + * include/asm-arm/arch-at91rm9200/at91sam9260.h
17752 + *
17753 + * (C) 2006 Andrew Victor
17754 + *
17755 + * Common definitions.
17756 + * Based on AT91SAM9260 datasheet revision A (Preliminary).
17757 + *
17758 + * This program is free software; you can redistribute it and/or modify
17759 + * it under the terms of the GNU General Public License as published by
17760 + * the Free Software Foundation; either version 2 of the License, or
17761 + * (at your option) any later version.
17762 + */
17763 +
17764 +#ifndef AT91SAM9260_H
17765 +#define AT91SAM9260_H
17766 +
17767 +/*
17768 + * Peripheral identifiers/interrupts.
17769 + */
17770 +#define AT91_ID_FIQ            0       /* Advanced Interrupt Controller (FIQ) */
17771 +#define AT91_ID_SYS            1       /* System Peripherals */
17772 +#define AT91SAM9260_ID_PIOA    2       /* Parallel IO Controller A */
17773 +#define AT91SAM9260_ID_PIOB    3       /* Parallel IO Controller B */
17774 +#define AT91SAM9260_ID_PIOC    4       /* Parallel IO Controller C */
17775 +#define AT91SAM9260_ID_ADC     5       /* Analog-to-Digital Converter */
17776 +#define AT91SAM9260_ID_US0     6       /* USART 0 */
17777 +#define AT91SAM9260_ID_US1     7       /* USART 1 */
17778 +#define AT91SAM9260_ID_US2     8       /* USART 2 */
17779 +#define AT91SAM9260_ID_MCI     9       /* Multimedia Card Interface */
17780 +#define AT91SAM9260_ID_UDP     10      /* USB Device Port */
17781 +#define AT91SAM9260_ID_TWI     11      /* Two-Wire Interface */
17782 +#define AT91SAM9260_ID_SPI0    12      /* Serial Peripheral Interface 0 */
17783 +#define AT91SAM9260_ID_SPI1    13      /* Serial Peripheral Interface 1 */
17784 +#define AT91SAM9260_ID_SSC     14      /* Serial Synchronous Controller */
17785 +#define AT91SAM9260_ID_TC0     17      /* Timer Counter 0 */
17786 +#define AT91SAM9260_ID_TC1     18      /* Timer Counter 1 */
17787 +#define AT91SAM9260_ID_TC2     19      /* Timer Counter 2 */
17788 +#define AT91SAM9260_ID_UHP     20      /* USB Host port */
17789 +#define AT91SAM9260_ID_EMAC    21      /* Ethernet */
17790 +#define AT91SAM9260_ID_ISI     22      /* Image Sensor Interface */
17791 +#define AT91SAM9260_ID_US3     23      /* USART 3 */
17792 +#define AT91SAM9260_ID_US4     24      /* USART 4 */
17793 +#define AT91SAM9260_ID_US5     25      /* USART 5 */
17794 +#define AT91SAM9260_ID_TC3     26      /* Timer Counter 3 */
17795 +#define AT91SAM9260_ID_TC4     27      /* Timer Counter 4 */
17796 +#define AT91SAM9260_ID_TC5     28      /* Timer Counter 5 */
17797 +#define AT91SAM9260_ID_IRQ0    29      /* Advanced Interrupt Controller (IRQ0) */
17798 +#define AT91SAM9260_ID_IRQ1    30      /* Advanced Interrupt Controller (IRQ1) */
17799 +#define AT91SAM9260_ID_IRQ2    31      /* Advanced Interrupt Controller (IRQ2) */
17800 +
17801 +
17802 +/*
17803 + * User Peripheral physical base addresses.
17804 + */
17805 +#define AT91SAM9260_BASE_TCB0          0xfffa0000
17806 +#define AT91SAM9260_BASE_TC0           0xfffa0000
17807 +#define AT91SAM9260_BASE_TC1           0xfffa0040
17808 +#define AT91SAM9260_BASE_TC2           0xfffa0080
17809 +#define AT91SAM9260_BASE_UDP           0xfffa4000
17810 +#define AT91SAM9260_BASE_MCI           0xfffa8000
17811 +#define AT91SAM9260_BASE_TWI           0xfffac000
17812 +#define AT91SAM9260_BASE_US0           0xfffb0000
17813 +#define AT91SAM9260_BASE_US1           0xfffb4000
17814 +#define AT91SAM9260_BASE_US2           0xfffb8000
17815 +#define AT91SAM9260_BASE_SSC           0xfffbc000
17816 +#define AT91SAM9260_BASE_ISI           0xfffc0000
17817 +#define AT91SAM9260_BASE_EMAC          0xfffc4000
17818 +#define AT91SAM9260_BASE_SPI0          0xfffc8000
17819 +#define AT91SAM9260_BASE_SPI1          0xfffcc000
17820 +#define AT91SAM9260_BASE_US3           0xfffd0000
17821 +#define AT91SAM9260_BASE_US4           0xfffd4000
17822 +#define AT91SAM9260_BASE_US5           0xfffd8000
17823 +#define AT91SAM9260_BASE_TCB1          0xfffdc000
17824 +#define AT91SAM9260_BASE_TC3           0xfffdc000
17825 +#define AT91SAM9260_BASE_TC4           0xfffdc040
17826 +#define AT91SAM9260_BASE_TC5           0xfffdc080
17827 +#define AT91SAM9260_BASE_ADC           0xfffe0000
17828 +#define AT91_BASE_SYS                  0xffffe800
17829 +
17830 +/*
17831 + * System Peripherals (offset from AT91_BASE_SYS)
17832 + */
17833 +#define AT91_ECC       (0xffffe800 - AT91_BASE_SYS)
17834 +#define AT91_SDRAMC    (0xffffea00 - AT91_BASE_SYS)
17835 +#define AT91_SMC       (0xffffec00 - AT91_BASE_SYS)
17836 +#define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
17837 +#define AT91_CCFG      (0xffffef10 - AT91_BASE_SYS)
17838 +#define AT91_AIC       (0xfffff000 - AT91_BASE_SYS)
17839 +#define AT91_DBGU      (0xfffff200 - AT91_BASE_SYS)
17840 +#define AT91_PIOA      (0xfffff400 - AT91_BASE_SYS)
17841 +#define AT91_PIOB      (0xfffff600 - AT91_BASE_SYS)
17842 +#define AT91_PIOC      (0xfffff800 - AT91_BASE_SYS)
17843 +#define AT91_PMC       (0xfffffc00 - AT91_BASE_SYS)
17844 +#define AT91_RSTC      (0xfffffd00 - AT91_BASE_SYS)
17845 +#define AT91_SHDWC     (0xfffffd10 - AT91_BASE_SYS)
17846 +#define AT91_RTT       (0xfffffd20 - AT91_BASE_SYS)
17847 +#define AT91_PIT       (0xfffffd30 - AT91_BASE_SYS)
17848 +#define AT91_WDT       (0xfffffd40 - AT91_BASE_SYS)
17849 +#define AT91_GPBR      (0xfffffd50 - AT91_BASE_SYS)
17850 +
17851 +
17852 +/*
17853 + * Internal Memory.
17854 + */
17855 +#define AT91SAM9260_ROM_BASE   0x00100000      /* Internal ROM base address */
17856 +#define AT91SAM9260_ROM_SIZE   SZ_32K          /* Internal ROM size (32Kb) */
17857 +
17858 +#define AT91SAM9260_SRAM0_BASE 0x00200000      /* Internal SRAM 0 base address */
17859 +#define AT91SAM9260_SRAM0_SIZE SZ_4K           /* Internal SRAM 0 size (4Kb) */
17860 +#define AT91SAM9260_SRAM1_BASE 0x00300000      /* Internal SRAM 1 base address */
17861 +#define AT91SAM9260_SRAM1_SIZE SZ_4K           /* Internal SRAM 1 size (4Kb) */
17862 +
17863 +#define AT91SAM9260_UHP_BASE   0x00500000      /* USB Host controller */
17864 +
17865 +#if 0
17866 +/*
17867 + * PIO pin definitions (peripheral A/B multiplexing).
17868 + */
17869 +
17870 +// TODO: Add
17871 +
17872 +#endif
17873 +
17874 +#endif
17875 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
17876 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h     Thu Jan  1 02:00:00 1970
17877 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h   Thu Nov 23 17:05:07 2006
17878 @@ -0,0 +1,78 @@
17879 +/*
17880 + * include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
17881 + *
17882 + * Memory Controllers (MATRIX, EBI) - System peripherals registers.
17883 + * Based on AT91SAM9260 datasheet revision B.
17884 + *
17885 + * This program is free software; you can redistribute it and/or modify
17886 + * it under the terms of the GNU General Public License as published by
17887 + * the Free Software Foundation; either version 2 of the License, or
17888 + * (at your option) any later version.
17889 + */
17890 +
17891 +#ifndef AT91SAM9260_MATRIX_H
17892 +#define AT91SAM9260_MATRIX_H
17893 +
17894 +#define AT91_MATRIX_MCFG0      (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
17895 +#define AT91_MATRIX_MCFG1      (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
17896 +#define AT91_MATRIX_MCFG2      (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
17897 +#define AT91_MATRIX_MCFG3      (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
17898 +#define AT91_MATRIX_MCFG4      (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
17899 +#define AT91_MATRIX_MCFG5      (AT91_MATRIX + 0x04)    /* Master Configuration Register 5 */
17900 +#define                AT91_MATRIX_ULBT                (7 << 0)        /* Undefined Length Burst Type */
17901 +#define                        AT91_MATRIX_ULBT_INFINITE       (0 << 0)
17902 +#define                        AT91_MATRIX_ULBT_SINGLE         (1 << 0)
17903 +#define                        AT91_MATRIX_ULBT_FOUR           (2 << 0)
17904 +#define                        AT91_MATRIX_ULBT_EIGHT          (3 << 0)
17905 +#define                        AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
17906 +
17907 +#define AT91_MATRIX_SCFG0      (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
17908 +#define AT91_MATRIX_SCFG1      (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
17909 +#define AT91_MATRIX_SCFG2      (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
17910 +#define AT91_MATRIX_SCFG3      (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
17911 +#define AT91_MATRIX_SCFG4      (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
17912 +#define                AT91_MATRIX_SLOT_CYCLE          (0xff <<  0)    /* Maximum Number of Allowed Cycles for a Burst */
17913 +#define                AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
17914 +#define                        AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
17915 +#define                        AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
17916 +#define                        AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
17917 +#define                AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
17918 +#define                AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
17919 +#define                        AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
17920 +#define                        AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
17921 +
17922 +#define AT91_MATRIX_PRAS0      (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
17923 +#define AT91_MATRIX_PRAS1      (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
17924 +#define AT91_MATRIX_PRAS2      (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
17925 +#define AT91_MATRIX_PRAS3      (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
17926 +#define AT91_MATRIX_PRAS4      (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
17927 +#define                AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
17928 +#define                AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
17929 +#define                AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
17930 +#define                AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
17931 +#define                AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
17932 +#define                AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
17933 +
17934 +#define AT91_MATRIX_MRCR       (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
17935 +#define                AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
17936 +#define                AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
17937 +
17938 +#define AT91_MATRIX_EBICSA     (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
17939 +#define                AT91_MATRIX_CS1A                (1 << 1)         /* Chip Select 1 Assignment */
17940 +#define                        AT91_MATRIX_CS1A_SMC            (0 << 1)
17941 +#define                        AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
17942 +#define                AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
17943 +#define                        AT91_MATRIX_CS3A_SMC            (0 << 3)
17944 +#define                        AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
17945 +#define                AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
17946 +#define                        AT91_MATRIX_CS4A_SMC            (0 << 4)
17947 +#define                        AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
17948 +#define                AT91_MATRIX_CS5A                (1 << 5 )       /* Chip Select 5 Assignment */
17949 +#define                        AT91_MATRIX_CS5A_SMC            (0 << 5)
17950 +#define                        AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
17951 +#define                AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
17952 +#define                AT91_MATRIX_VDDIOMSEL           (1 << 16)       /* Memory voltage selection */
17953 +#define                        AT91_MATRIX_VDDIOMSEL_1_8V      (0 << 16)
17954 +#define                        AT91_MATRIX_VDDIOMSEL_3_3V      (1 << 16)
17955 +
17956 +#endif
17957 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9261.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9261.h
17958 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9261.h    Thu Jan  1 02:00:00 1970
17959 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9261.h  Fri Nov 10 10:08:55 2006
17960 @@ -0,0 +1,292 @@
17961 +/*
17962 + * include/asm-arm/arch-at91rm9200/at91sam9261.h
17963 + *
17964 + * Copyright (C) SAN People
17965 + *
17966 + * Common definitions.
17967 + * Based on AT91SAM9261 datasheet revision E. (Preliminary)
17968 + *
17969 + * This program is free software; you can redistribute it and/or modify
17970 + * it under the terms of the GNU General Public License as published by
17971 + * the Free Software Foundation; either version 2 of the License, or
17972 + * (at your option) any later version.
17973 + */
17974 +
17975 +#ifndef AT91SAM9261_H
17976 +#define AT91SAM9261_H
17977 +
17978 +/*
17979 + * Peripheral identifiers/interrupts.
17980 + */
17981 +#define AT91_ID_FIQ            0       /* Advanced Interrupt Controller (FIQ) */
17982 +#define AT91_ID_SYS            1       /* System Peripherals */
17983 +#define AT91SAM9261_ID_PIOA    2       /* Parallel IO Controller A */
17984 +#define AT91SAM9261_ID_PIOB    3       /* Parallel IO Controller B */
17985 +#define AT91SAM9261_ID_PIOC    4       /* Parallel IO Controller C */
17986 +#define AT91SAM9261_ID_US0     6       /* USART 0 */
17987 +#define AT91SAM9261_ID_US1     7       /* USART 1 */
17988 +#define AT91SAM9261_ID_US2     8       /* USART 2 */
17989 +#define AT91SAM9261_ID_MCI     9       /* Multimedia Card Interface */
17990 +#define AT91SAM9261_ID_UDP     10      /* USB Device Port */
17991 +#define AT91SAM9261_ID_TWI     11      /* Two-Wire Interface */
17992 +#define AT91SAM9261_ID_SPI0    12      /* Serial Peripheral Interface 0 */
17993 +#define AT91SAM9261_ID_SPI1    13      /* Serial Peripheral Interface 1 */
17994 +#define AT91SAM9261_ID_SSC0    14      /* Serial Synchronous Controller 0 */
17995 +#define AT91SAM9261_ID_SSC1    15      /* Serial Synchronous Controller 1 */
17996 +#define AT91SAM9261_ID_SSC2    16      /* Serial Synchronous Controller 2 */
17997 +#define AT91SAM9261_ID_TC0     17      /* Timer Counter 0 */
17998 +#define AT91SAM9261_ID_TC1     18      /* Timer Counter 1 */
17999 +#define AT91SAM9261_ID_TC2     19      /* Timer Counter 2 */
18000 +#define AT91SAM9261_ID_UHP     20      /* USB Host port */
18001 +#define AT91SAM9261_ID_LCDC    21      /* LDC Controller */
18002 +#define AT91SAM9261_ID_IRQ0    29      /* Advanced Interrupt Controller (IRQ0) */
18003 +#define AT91SAM9261_ID_IRQ1    30      /* Advanced Interrupt Controller (IRQ1) */
18004 +#define AT91SAM9261_ID_IRQ2    31      /* Advanced Interrupt Controller (IRQ2) */
18005 +
18006 +
18007 +/*
18008 + * User Peripheral physical base addresses.
18009 + */
18010 +#define AT91SAM9261_BASE_TCB0          0xfffa0000
18011 +#define AT91SAM9261_BASE_TC0           0xfffa0000
18012 +#define AT91SAM9261_BASE_TC1           0xfffa0040
18013 +#define AT91SAM9261_BASE_TC2           0xfffa0080
18014 +#define AT91SAM9261_BASE_UDP           0xfffa4000
18015 +#define AT91SAM9261_BASE_MCI           0xfffa8000
18016 +#define AT91SAM9261_BASE_TWI           0xfffac000
18017 +#define AT91SAM9261_BASE_US0           0xfffb0000
18018 +#define AT91SAM9261_BASE_US1           0xfffb4000
18019 +#define AT91SAM9261_BASE_US2           0xfffb8000
18020 +#define AT91SAM9261_BASE_SSC0          0xfffbc000
18021 +#define AT91SAM9261_BASE_SSC1          0xfffc0000
18022 +#define AT91SAM9261_BASE_SSC2          0xfffc4000
18023 +#define AT91SAM9261_BASE_SPI0          0xfffc8000
18024 +#define AT91SAM9261_BASE_SPI1          0xfffcc000
18025 +#define AT91_BASE_SYS                  0xffffea00
18026 +
18027 +
18028 +/*
18029 + * System Peripherals (offset from AT91_BASE_SYS)
18030 + */
18031 +#define AT91_SDRAMC    (0xffffea00 - AT91_BASE_SYS)
18032 +#define AT91_SMC       (0xffffec00 - AT91_BASE_SYS)
18033 +#define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
18034 +#define AT91_AIC       (0xfffff000 - AT91_BASE_SYS)
18035 +#define AT91_DBGU      (0xfffff200 - AT91_BASE_SYS)
18036 +#define AT91_PIOA      (0xfffff400 - AT91_BASE_SYS)
18037 +#define AT91_PIOB      (0xfffff600 - AT91_BASE_SYS)
18038 +#define AT91_PIOC      (0xfffff800 - AT91_BASE_SYS)
18039 +#define AT91_PMC       (0xfffffc00 - AT91_BASE_SYS)
18040 +#define AT91_RSTC      (0xfffffd00 - AT91_BASE_SYS)
18041 +#define AT91_SHDWC     (0xfffffd10 - AT91_BASE_SYS)
18042 +#define AT91_RTT       (0xfffffd20 - AT91_BASE_SYS)
18043 +#define AT91_PIT       (0xfffffd30 - AT91_BASE_SYS)
18044 +#define AT91_WDT       (0xfffffd40 - AT91_BASE_SYS)
18045 +#define AT91_GPBR      (0xfffffd50 - AT91_BASE_SYS)
18046 +
18047 +
18048 +/*
18049 + * Internal Memory.
18050 + */
18051 +#define AT91SAM9261_SRAM_BASE  0x00300000      /* Internal SRAM base address */
18052 +#define AT91SAM9261_SRAM_SIZE  0x00028000      /* Internal SRAM size (160Kb) */
18053 +
18054 +#define AT91SAM9261_ROM_BASE   0x00400000      /* Internal ROM base address */
18055 +#define AT91SAM9261_ROM_SIZE   SZ_32K          /* Internal ROM size (32Kb) */
18056 +
18057 +#define AT91SAM9261_UHP_BASE   0x00500000      /* USB Host controller */
18058 +#define AT91SAM9261_LCDC_BASE  0x00600000      /* LDC controller */
18059 +
18060 +
18061 +#if 0
18062 +/*
18063 + * PIO pin definitions (peripheral A/B multiplexing).
18064 + */
18065 +#define AT91_PA0_SPI0_MISO     (1 <<  0)       /* A: SPI0 Master In Slave */
18066 +#define AT91_PA0_MCDA0         (1 <<  0)       /* B: Multimedia Card A Data 0 */
18067 +#define AT91_PA1_SPI0_MOSI     (1 <<  1)       /* A: SPI0 Master Out Slave */
18068 +#define AT91_PA1_MCCDA         (1 <<  1)       /* B: Multimedia Card A Command */
18069 +#define AT91_PA2_SPI0_SPCK     (1 <<  2)       /* A: SPI0 Serial Clock */
18070 +#define AT91_PA2_MCCK          (1 <<  2)       /* B: Multimedia Card Clock */
18071 +#define AT91_PA3_SPI0_NPCS0    (1 <<  3)       /* A: SPI0 Peripheral Chip Select 0 */
18072 +#define AT91_PA4_SPI0_NPCS1    (1 <<  4)       /* A: SPI0 Peripheral Chip Select 1 */
18073 +#define AT91_PA4_MCDA1         (1 <<  4)       /* B: Multimedia Card A Data 1 */
18074 +#define AT91_PA5_SPI0_NPCS2    (1 <<  5)       /* A: SPI0 Peripheral Chip Select 2 */
18075 +#define AT91_PA5_MCDA2         (1 <<  5)       /* B: Multimedia Card A Data 2 */
18076 +#define AT91_PA6_SPI0_NPCS3    (1 <<  6)       /* A: SPI0 Peripheral Chip Select 3 */
18077 +#define AT91_PA6_MCDA3         (1 <<  6)       /* B: Multimedia Card A Data 3 */
18078 +#define AT91_PA7_TWD           (1 <<  7)       /* A: TWI Two-wire Serial Data */
18079 +#define AT91_PA7_PCK0          (1 <<  7)       /* B: PMC Programmable clock Output 0 */
18080 +#define AT91_PA8_TWCK          (1 <<  8)       /* A: TWI Two-wire Serial Clock */
18081 +#define AT91_PA8_PCK1          (1 <<  8)       /* B: PMC Programmable clock Output 1 */
18082 +#define AT91_PA9_DRXD          (1 <<  9)       /* A: DBGU Debug Receive Data */
18083 +#define AT91_PA9_PCK2          (1 <<  9)       /* B: PMC Programmable clock Output 2 */
18084 +#define AT91_PA10_DTXD         (1 << 10)       /* A: DBGU Debug Transmit Data */
18085 +#define AT91_PA10_PCK3         (1 << 10)       /* B: PMC Programmable clock Output 3 */
18086 +#define AT91_PA11_TSYNC                (1 << 11)       /* A: Trace Synchronization Signal */
18087 +#define AT91_PA11_SCK1         (1 << 11)       /* B: USART1 Serial Clock */
18088 +#define AT91_PA12_TCLK         (1 << 12)       /* A: Trace Clock */
18089 +#define AT91_PA12_RTS1         (1 << 12)       /* B: USART1 Ready To Send */
18090 +#define AT91_PA13_TPS0         (1 << 13)       /* A: Trace ARM Pipeline Status 0 */
18091 +#define AT91_PA13_CTS1         (1 << 13)       /* B: USART1 Clear To Send */
18092 +#define AT91_PA14_TPS1         (1 << 14)       /* A: Trace ARM Pipeline Status 1 */
18093 +#define AT91_PA14_SCK2         (1 << 14)       /* B: USART2 Serial Clock */
18094 +#define AT91_PA15_TPS2         (1 << 15)       /* A: Trace ARM Pipeline Status 2 */
18095 +#define AT91_PA15_RTS2         (1 << 15)       /* B: USART2 Ready To Send */
18096 +#define AT91_PA16_TPK0         (1 << 16)       /* A: Trace Packet Port 0 */
18097 +#define AT91_PA16_CTS2         (1 << 16)       /* B: USART2 Clear To Send */
18098 +#define AT91_PA17_TPK1         (1 << 17)       /* A: Trace Packet Port 1 */
18099 +#define AT91_PA17_TF1          (1 << 17)       /* B: SSC1 Transmit Frame Sync */
18100 +#define AT91_PA18_TPK2         (1 << 18)       /* A: Trace Packet Port 2 */
18101 +#define AT91_PA18_TK1          (1 << 18)       /* B: SSC1 Transmit Clock */
18102 +#define AT91_PA19_TPK3         (1 << 19)       /* A: Trace Packet Port 3 */
18103 +#define AT91_PA19_TD1          (1 << 19)       /* B: SSC1 Transmit Data */
18104 +#define AT91_PA20_TPK4         (1 << 20)       /* A: Trace Packet Port 4 */
18105 +#define AT91_PA20_RD1          (1 << 20)       /* B: SSC1 Receive Data */
18106 +#define AT91_PA21_TPK5         (1 << 21)       /* A: Trace Packet Port 5 */
18107 +#define AT91_PA21_RK1          (1 << 21)       /* B: SSC1 Receive Clock */
18108 +#define AT91_PA22_TPK6         (1 << 22)       /* A: Trace Packet Port 6 */
18109 +#define AT91_PA22_RF1          (1 << 22)       /* B: SSC1 Receive Frame Sync */
18110 +#define AT91_PA23_TPK7         (1 << 23)       /* A: Trace Packet Port 7 */
18111 +#define AT91_PA23_RTS0         (1 << 23)       /* B: USART0 Ready To Send */
18112 +#define AT91_PA24_TPK8         (1 << 24)       /* A: Trace Packet Port 8 */
18113 +#define AT91_PA24_SPI1_NPCS1   (1 << 24)       /* B: SPI1 Peripheral Chip Select 1 */
18114 +#define AT91_PA25_TPK9         (1 << 25)       /* A: Trace Packet Port 9 */
18115 +#define AT91_PA25_SPI1_NPCS2   (1 << 25)       /* B: SPI1 Peripheral Chip Select 2 */
18116 +#define AT91_PA26_TPK10                (1 << 26)       /* A: Trace Packet Port 10 */
18117 +#define AT91_PA26_SPI1_NPCS3   (1 << 26)       /* B: SPI1 Peripheral Chip Select 3 */
18118 +#define AT91_PA27_TPK11                (1 << 27)       /* A: Trace Packet Port 11 */
18119 +#define AT91_PA27_SPI0_NPCS1   (1 << 27)       /* B: SPI0 Peripheral Chip Select 1 */
18120 +#define AT91_PA28_TPK12                (1 << 28)       /* A: Trace Packet Port 12 */
18121 +#define AT91_PA28_SPI0_NPCS2   (1 << 28)       /* B: SPI0 Peripheral Chip Select 2 */
18122 +#define AT91_PA29_TPK13                (1 << 29)       /* A: Trace Packet Port 13 */
18123 +#define AT91_PA29_SPI0_NPCS3   (1 << 29)       /* B: SPI0 Peripheral Chip Select 3 */
18124 +#define AT91_PA30_TPK14                (1 << 30)       /* A: Trace Packet Port 14 */
18125 +#define AT91_PA30_A23          (1 << 30)       /* B: Address Bus bit 23 */
18126 +#define AT91_PA31_TPK15                (1 << 31)       /* A: Trace Packet Port 15 */
18127 +#define AT91_PA31_A24          (1 << 31)       /* B: Address Bus bit 24 */
18128 +
18129 +#define AT91_PB0_LCDVSYNC      (1 <<  0)       /* A: LCD Vertical Synchronization */
18130 +#define AT91_PB1_LCDHSYNC      (1 <<  1)       /* A: LCD Horizontal Synchronization */
18131 +#define AT91_PB2_LCDDOTCK      (1 <<  2)       /* A: LCD Dot Clock */
18132 +#define AT91_PB2_PCK0          (1 <<  2)       /* B: PMC Programmable clock Output 0 */
18133 +#define AT91_PB3_LCDDEN                (1 <<  3)       /* A: LCD Data Enable */
18134 +#define AT91_PB4_LCDCC         (1 <<  4)       /* A: LCD Contrast Control */
18135 +#define AT91_PB4_LCDD2         (1 <<  4)       /* B: LCD Data Bus Bit 2 */
18136 +#define AT91_PB5_LCDD0         (1 <<  5)       /* A: LCD Data Bus Bit 0 */
18137 +#define AT91_PB5_LCDD3         (1 <<  5)       /* B: LCD Data Bus Bit 3 */
18138 +#define AT91_PB6_LCDD1         (1 <<  6)       /* A: LCD Data Bus Bit 1 */
18139 +#define AT91_PB6_LCDD4         (1 <<  6)       /* B: LCD Data Bus Bit 4 */
18140 +#define AT91_PB7_LCDD2         (1 <<  7)       /* A: LCD Data Bus Bit 2 */
18141 +#define AT91_PB7_LCDD5         (1 <<  7)       /* B: LCD Data Bus Bit 5 */
18142 +#define AT91_PB8_LCDD3         (1 <<  8)       /* A: LCD Data Bus Bit 3 */
18143 +#define AT91_PB8_LCDD6         (1 <<  8)       /* B: LCD Data Bus Bit 6 */
18144 +#define AT91_PB9_LCDD4         (1 <<  9)       /* A: LCD Data Bus Bit 4 */
18145 +#define AT91_PB9_LCDD7         (1 <<  9)       /* B: LCD Data Bus Bit 7 */
18146 +#define AT91_PB10_LCDD5                (1 << 10)       /* A: LCD Data Bus Bit 5 */
18147 +#define AT91_PB10_LCDD10       (1 << 10)       /* B: LCD Data Bus Bit 10 */
18148 +#define AT91_PB11_LCDD6                (1 << 11)       /* A: LCD Data Bus Bit 6 */
18149 +#define AT91_PB11_LCDD11       (1 << 11)       /* B: LCD Data Bus Bit 11 */
18150 +#define AT91_PB12_LCDD7                (1 << 12)       /* A: LCD Data Bus Bit 7 */
18151 +#define AT91_PB12_LCDD12       (1 << 12)       /* B: LCD Data Bus Bit 12 */
18152 +#define AT91_PB13_LCDD8                (1 << 13)       /* A: LCD Data Bus Bit 8 */
18153 +#define AT91_PB13_LCDD13       (1 << 13)       /* B: LCD Data Bus Bit 13 */
18154 +#define AT91_PB14_LCDD9                (1 << 14)       /* A: LCD Data Bus Bit 9 */
18155 +#define AT91_PB14_LCDD14       (1 << 14)       /* B: LCD Data Bus Bit 14 */
18156 +#define AT91_PB15_LCDD10       (1 << 15)       /* A: LCD Data Bus Bit 10 */
18157 +#define AT91_PB15_LCDD15       (1 << 15)       /* B: LCD Data Bus Bit 15 */
18158 +#define AT91_PB16_LCDD11       (1 << 16)       /* A: LCD Data Bus Bit 11 */
18159 +#define AT91_PB16_LCDD19       (1 << 16)       /* B: LCD Data Bus Bit 19 */
18160 +#define AT91_PB17_LCDD12       (1 << 17)       /* A: LCD Data Bus Bit 12 */
18161 +#define AT91_PB17_LCDD20       (1 << 17)       /* B: LCD Data Bus Bit 20 */
18162 +#define AT91_PB18_LCDD13       (1 << 18)       /* A: LCD Data Bus Bit 13 */
18163 +#define AT91_PB18_LCDD21       (1 << 18)       /* B: LCD Data Bus Bit 21 */
18164 +#define AT91_PB19_LCDD14       (1 << 19)       /* A: LCD Data Bus Bit 14 */
18165 +#define AT91_PB19_LCDD22       (1 << 19)       /* B: LCD Data Bus Bit 22 */
18166 +#define AT91_PB20_LCDD15       (1 << 20)       /* A: LCD Data Bus Bit 15 */
18167 +#define AT91_PB20_LCDD23       (1 << 20)       /* B: LCD Data Bus Bit 23 */
18168 +#define AT91_PB21_TF0          (1 << 21)       /* A: SSC0 Transmit Frame Sync */
18169 +#define AT91_PB21_LCDD16       (1 << 21)       /* B: LCD Data Bus Bit 16 */
18170 +#define AT91_PB22_TK0          (1 << 22)       /* A: SSC0 Transmit Clock */
18171 +#define AT91_PB22_LCDD17       (1 << 22)       /* B: LCD Data Bus Bit 17 */
18172 +#define AT91_PB23_TD0          (1 << 23)       /* A: SSC0 Transmit Data */
18173 +#define AT91_PB23_LCDD18       (1 << 23)       /* B: LCD Data Bus Bit 18 */
18174 +#define AT91_PB24_RD0          (1 << 24)       /* A: SSC0 Receive Data */
18175 +#define AT91_PB24_LCDD19       (1 << 24)       /* B: LCD Data Bus Bit 19 */
18176 +#define AT91_PB25_RK0          (1 << 25)       /* A: SSC0 Receive Clock */
18177 +#define AT91_PB25_LCDD20       (1 << 25)       /* B: LCD Data Bus Bit 20 */
18178 +#define AT91_PB26_RF0          (1 << 26)       /* A: SSC0 Receive Frame Sync */
18179 +#define AT91_PB26_LCDD21       (1 << 26)       /* B: LCD Data Bus Bit 21 */
18180 +#define AT91_PB27_SPI1_NPCS1   (1 << 27)       /* A: SPI1 Peripheral Chip Select 1 */
18181 +#define AT91_PB27_LCDD22       (1 << 27)       /* B: LCD Data Bus Bit 22 */
18182 +#define AT91_PB28_SPI1_NPCS0   (1 << 28)       /* A: SPI1 Peripheral Chip Select 0 */
18183 +#define AT91_PB28_LCDD23       (1 << 28)       /* B: LCD Data Bus Bit 23 */
18184 +#define AT91_PB29_SPI1_SPCK    (1 << 29)       /* A: SPI1 Serial Clock */
18185 +#define AT91_PB29_IRQ2         (1 << 29)       /* B: Interrupt input 2 */
18186 +#define AT91_PB30_SPI1_MISO    (1 << 30)       /* A: SPI1 Master In Slave */
18187 +#define AT91_PB30_IRQ1         (1 << 30)       /* B: Interrupt input 1 */
18188 +#define AT91_PB31_SPI1_MOSI    (1 << 31)       /* A: SPI1 Master Out Slave */
18189 +#define AT91_PB31_PCK2         (1 << 31)       /* B: PMC Programmable clock Output 2 */
18190 +
18191 +#define AT91_PC0_SMOE          (1 << 0)        /* A: SmartMedia Output Enable */
18192 +#define AT91_PC0_NCS6          (1 << 0)        /* B: Chip Select 6 */
18193 +#define AT91_PC1_SMWE          (1 << 1)        /* A: SmartMedia Write Enable */
18194 +#define AT91_PC1_NCS7          (1 << 1)        /* B: Chip Select 7 */
18195 +#define AT91_PC2_NWAIT         (1 << 2)        /* A: NWAIT */
18196 +#define AT91_PC2_IRQ0          (1 << 2)        /* B: Interrupt input 0 */
18197 +#define AT91_PC3_A25_CFRNW     (1 << 3)        /* A: Address Bus[25] / Compact Flash Read Not Write */
18198 +#define AT91_PC4_NCS4_CFCS0    (1 << 4)        /* A: Chip Select 4 / CompactFlash Chip Select 0 */
18199 +#define AT91_PC5_NCS5_CFCS1    (1 << 5)        /* A: Chip Select 5 / CompactFlash Chip Select 1 */
18200 +#define AT91_PC6_CFCE1         (1 << 6)        /* A: CompactFlash Chip Enable 1 */
18201 +#define AT91_PC7_CFCE2         (1 << 7)        /* A: CompactFlash Chip Enable 2 */
18202 +#define AT91_PC8_TXD0          (1 << 8)        /* A: USART0 Transmit Data */
18203 +#define AT91_PC8_PCK2          (1 << 8)        /* B: PMC Programmable clock Output 2 */
18204 +#define AT91_PC9_RXD0          (1 << 9)        /* A: USART0 Receive Data */
18205 +#define AT91_PC9_PCK3          (1 << 9)        /* B: PMC Programmable clock Output 3 */
18206 +#define AT91_PC10_RTS0         (1 << 10)       /* A: USART0 Ready To Send */
18207 +#define AT91_PC10_SCK0         (1 << 10)       /* B: USART0 Serial Clock */
18208 +#define AT91_PC11_CTS0         (1 << 11)       /* A: USART0 Clear To Send */
18209 +#define AT91_PC11_FIQ          (1 << 11)       /* B: AIC Fast Interrupt Input */
18210 +#define AT91_PC12_TXD1         (1 << 12)       /* A: USART1 Transmit Data */
18211 +#define AT91_PC12_NCS6         (1 << 12)       /* B: Chip Select 6 */
18212 +#define AT91_PC13_RXD1         (1 << 13)       /* A: USART1 Receive Data */
18213 +#define AT91_PC13_NCS7         (1 << 13)       /* B: Chip Select 7 */
18214 +#define AT91_PC14_TXD2         (1 << 14)       /* A: USART2 Transmit Data */
18215 +#define AT91_PC14_SPI1_NPCS2   (1 << 14)       /* B: SPI1 Peripheral Chip Select 2 */
18216 +#define AT91_PC15_RXD2         (1 << 15)       /* A: USART2 Receive Data */
18217 +#define AT91_PC15_SPI1_NPCS3   (1 << 15)       /* B: SPI1 Peripheral Chip Select 3 */
18218 +#define AT91_PC16_D16          (1 << 16)       /* A: Data Bus [16] */
18219 +#define AT91_PC16_TCLK0                (1 << 16)       /* B: Timer Counter 0 external clock input */
18220 +#define AT91_PC17_D17          (1 << 17)       /* A: Data Bus [17] */
18221 +#define AT91_PC17_TCLK1                (1 << 17)       /* B: Timer Counter 1 external clock input */
18222 +#define AT91_PC18_D18          (1 << 18)       /* A: Data Bus [18] */
18223 +#define AT91_PC18_TCLK2                (1 << 18)       /* B: Timer Counter 2 external clock input */
18224 +#define AT91_PC19_D19          (1 << 19)       /* A: Data Bus [19] */
18225 +#define AT91_PC19_TIOA0                (1 << 19)       /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */
18226 +#define AT91_PC20_D20          (1 << 20)       /* A: Data Bus [20] */
18227 +#define AT91_PC20_TIOB0                (1 << 20)       /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */
18228 +#define AT91_PC21_D21          (1 << 21)       /* A: Data Bus [21] */
18229 +#define AT91_PC21_TIOA1                (1 << 21)       /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */
18230 +#define AT91_PC22_D22          (1 << 22)       /* A: Data Bus [22] */
18231 +#define AT91_PC22_TIOB1                (1 << 22)       /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */
18232 +#define AT91_PC23_D23          (1 << 23)       /* A: Data Bus [23] */
18233 +#define AT91_PC23_TIOA2                (1 << 23)       /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */
18234 +#define AT91_PC24_D24          (1 << 24)       /* A: Data Bus [24] */
18235 +#define AT91_PC24_TIOB2                (1 << 24)       /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */
18236 +#define AT91_PC25_D25          (1 << 25)       /* A: Data Bus [25] */
18237 +#define AT91_PC25_TF2          (1 << 25)       /* B: SSC2 Transmit Frame Sync */
18238 +#define AT91_PC26_D26          (1 << 26)       /* A: Data Bus [26] */
18239 +#define AT91_PC26_TK2          (1 << 26)       /* B: SSC2 Transmit Clock */
18240 +#define AT91_PC27_D27          (1 << 27)       /* A: Data Bus [27] */
18241 +#define AT91_PC27_TD2          (1 << 27)       /* B: SSC2 Transmit Data */
18242 +#define AT91_PC28_D28          (1 << 28)       /* A: Data Bus [28] */
18243 +#define AT91_PC28_RD2          (1 << 28)       /* B: SSC2 Receive Data */
18244 +#define AT91_PC29_D29          (1 << 29)       /* A: Data Bus [29] */
18245 +#define AT91_PC29_RK2          (1 << 29)       /* B: SSC2 Receive Clock */
18246 +#define AT91_PC30_D30          (1 << 30)       /* A: Data Bus [30] */
18247 +#define AT91_PC30_RF2          (1 << 30)       /* B: SSC2 Receive Frame Sync */
18248 +#define AT91_PC31_D31          (1 << 31)       /* A: Data Bus [31] */
18249 +#define AT91_PC31_PCK1         (1 << 31)       /* B: PMC Programmable clock Output 1 */
18250 +#endif
18251 +
18252 +#endif
18253 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
18254 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h     Thu Jan  1 02:00:00 1970
18255 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h   Thu Nov 23 17:08:24 2006
18256 @@ -0,0 +1,62 @@
18257 +/*
18258 + * include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
18259 + *
18260 + * Memory Controllers (MATRIX, EBI) - System peripherals registers.
18261 + * Based on AT91SAM9261 datasheet revision D.
18262 + *
18263 + * This program is free software; you can redistribute it and/or modify
18264 + * it under the terms of the GNU General Public License as published by
18265 + * the Free Software Foundation; either version 2 of the License, or
18266 + * (at your option) any later version.
18267 + */
18268 +
18269 +#ifndef AT91SAM9261_MATRIX_H
18270 +#define AT91SAM9261_MATRIX_H
18271 +
18272 +#define AT91_MATRIX_MCFG       (AT91_MATRIX + 0x00)    /* Master Configuration Register */
18273 +#define                AT91_MATRIX_RCB0        (1 << 0)                /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
18274 +#define                AT01_MATRIX_RCB1        (1 << 1)                /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
18275 +
18276 +#define AT91_MATRIX_SCFG0      (AT91_MATRIX + 0x04)    /* Slave Configuration Register 0 */
18277 +#define AT91_MATRIX_SCFG1      (AT91_MATRIX + 0x08)    /* Slave Configuration Register 1 */
18278 +#define AT91_MATRIX_SCFG2      (AT91_MATRIX + 0x0C)    /* Slave Configuration Register 2 */
18279 +#define AT91_MATRIX_SCFG3      (AT91_MATRIX + 0x10)    /* Slave Configuration Register 3 */
18280 +#define AT91_MATRIX_SCFG4      (AT91_MATRIX + 0x14)    /* Slave Configuration Register 4 */
18281 +#define                AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
18282 +#define                AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
18283 +#define                        AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
18284 +#define                        AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
18285 +#define                        AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
18286 +#define                AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
18287 +
18288 +#define AT91_MATRIX_TCR                (AT91_MATRIX + 0x24)    /* TCM Configuration Register */
18289 +#define                AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
18290 +#define                        AT91_MATRIX_ITCM_0              (0 << 0)
18291 +#define                        AT91_MATRIX_ITCM_16             (5 << 0)
18292 +#define                        AT91_MATRIX_ITCM_32             (6 << 0)
18293 +#define                        AT91_MATRIX_ITCM_64             (7 << 0)
18294 +#define                AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
18295 +#define                        AT91_MATRIX_DTCM_0              (0 << 4)
18296 +#define                        AT91_MATRIX_DTCM_16             (5 << 4)
18297 +#define                        AT91_MATRIX_DTCM_32             (6 << 4)
18298 +#define                        AT91_MATRIX_DTCM_64             (7 << 4)
18299 +
18300 +#define AT91_MATRIX_EBICSA     (AT91_MATRIX + 0x30)    /* EBI Chip Select Assignment Register */
18301 +#define                AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
18302 +#define                AT91_MATRIX_CS1A_SMC            (0 << 1)
18303 +#define                AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
18304 +#define                AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
18305 +#define                        AT91_MATRIX_CS3A_SMC            (0 << 3)
18306 +#define                        AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
18307 +#define                AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
18308 +#define                        AT91_MATRIX_CS4A_SMC            (0 << 4)
18309 +#define                        AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
18310 +#define                AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
18311 +#define                        AT91_MATRIX_CS5A_SMC            (0 << 5)
18312 +#define                        AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
18313 +#define                AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
18314 +
18315 +#define AT91_MATRIX_USBPUCR    (AT91_MATRIX + 0x34)    /* USB Pad Pull-Up Control Register */
18316 +#define                AT91_MATRIX_USBPUCR_PUON        (1 << 30)       /* USB Device PAD Pull-up Enable */
18317 +
18318 +#endif
18319 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
18320 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h Thu Jan  1 02:00:00 1970
18321 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h       Mon Nov 13 12:27:30 2006
18322 @@ -0,0 +1,134 @@
18323 +/*
18324 + * include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
18325 + *
18326 + * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
18327 + * Based on AT91SAM9261 datasheet revision D.
18328 + *
18329 + * This program is free software; you can redistribute it and/or modify
18330 + * it under the terms of the GNU General Public License as published by
18331 + * the Free Software Foundation; either version 2 of the License, or
18332 + * (at your option) any later version.
18333 + */
18334 +
18335 +#ifndef AT91SAM926x_MC_H
18336 +#define AT91SAM926x_MC_H
18337 +
18338 +/* SDRAM Controller (SDRAMC) registers */
18339 +#define AT91_SDRAMC_MR         (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
18340 +#define                AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
18341 +#define                        AT91_SDRAMC_MODE_NORMAL         0
18342 +#define                        AT91_SDRAMC_MODE_NOP            1
18343 +#define                        AT91_SDRAMC_MODE_PRECHARGE      2
18344 +#define                        AT91_SDRAMC_MODE_LMR            3
18345 +#define                        AT91_SDRAMC_MODE_REFRESH        4
18346 +#define                        AT91_SDRAMC_MODE_EXT_LMR        5
18347 +#define                        AT91_SDRAMC_MODE_DEEP           6
18348 +
18349 +#define AT91_SDRAMC_TR         (AT91_SDRAMC + 0x04)    /* SDRAM Controller Refresh Timer Register */
18350 +#define                AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Counter */
18351 +
18352 +#define AT91_SDRAMC_CR         (AT91_SDRAMC + 0x08)    /* SDRAM Controller Configuration Register */
18353 +#define                AT91_SDRAMC_NC          (3 << 0)                /* Number of Column Bits */
18354 +#define                        AT91_SDRAMC_NC_8        (0 << 0)
18355 +#define                        AT91_SDRAMC_NC_9        (1 << 0)
18356 +#define                        AT91_SDRAMC_NC_10       (2 << 0)
18357 +#define                        AT91_SDRAMC_NC_11       (3 << 0)
18358 +#define        AT91_SDRAMC_NR          (3 << 2)                /* Number of Row Bits */
18359 +#define                        AT91_SDRAMC_NR_11       (0 << 2)
18360 +#define                        AT91_SDRAMC_NR_12       (1 << 2)
18361 +#define                        AT91_SDRAMC_NR_13       (2 << 2)
18362 +#define        AT91_SDRAMC_NB          (1 << 4)                /* Number of Banks */
18363 +#define                        AT91_SDRAMC_NB_2        (0 << 4)
18364 +#define                AT91_SDRAMC_NB_4        (1 << 4)
18365 +#define        AT91_SDRAMC_CAS         (3 << 5)                /* CAS Latency */
18366 +#define                        AT91_SDRAMC_CAS_1       (1 << 5)
18367 +#define                        AT91_SDRAMC_CAS_2       (2 << 5)
18368 +#define                        AT91_SDRAMC_CAS_3       (3 << 5)
18369 +#define                AT91_SDRAMC_DBW         (1 << 7)                /* Data Bus Width */
18370 +#define                        AT91_SDRAMC_DBW_32      (0 << 7)
18371 +#define                        AT91_SDRAMC_DBW_16      (1 << 7)
18372 +#define                AT91_SDRAMC_TWR         (0xf <<  8)             /* Write Recovery Delay */
18373 +#define                AT91_SDRAMC_TRC         (0xf << 12)             /* Row Cycle Delay */
18374 +#define                AT91_SDRAMC_TRP         (0xf << 16)             /* Row Precharge Delay */
18375 +#define                AT91_SDRAMC_TRCD        (0xf << 20)             /* Row to Column Delay */
18376 +#define                AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
18377 +#define                AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
18378 +
18379 +#define AT91_SDRAMC_LPR                (AT91_SDRAMC + 0x10)    /* SDRAM Controller Low Power Register */
18380 +#define                AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
18381 +#define                        AT91_SDRAMC_LPCB_DISABLE                0
18382 +#define                        AT91_SDRAMC_LPCB_SELF_REFRESH           1
18383 +#define                        AT91_SDRAMC_LPCB_POWER_DOWN             2
18384 +#define                        AT91_SDRAMC_LPCB_DEEP_POWER_DOWN        3
18385 +#define                AT91_SDRAMC_PASR                (7 << 4)        /* Partial Array Self Refresh */
18386 +#define                AT91_SDRAMC_TCSR                (3 << 8)        /* Temperature Compensated Self Refresh */
18387 +#define                AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strenght */
18388 +#define                AT91_SDRAMC_TIMEOUT             (3 << 12)       /* Time to define when Low Power Mode is enabled */
18389 +#define                        AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES        (0 << 12)
18390 +#define                        AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
18391 +#define                        AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      (2 << 12)
18392 +
18393 +#define AT91_SDRAMC_IER                (AT91_SDRAMC + 0x14)    /* SDRAM Controller Interrupt Enable Register */
18394 +#define AT91_SDRAMC_IDR                (AT91_SDRAMC + 0x18)    /* SDRAM Controller Interrupt Disable Register */
18395 +#define AT91_SDRAMC_IMR                (AT91_SDRAMC + 0x1C)    /* SDRAM Controller Interrupt Mask Register */
18396 +#define AT91_SDRAMC_ISR                (AT91_SDRAMC + 0x20)    /* SDRAM Controller Interrupt Status Register */
18397 +#define                AT91_SDRAMC_RES         (1 << 0)                /* Refresh Error Status */
18398 +
18399 +#define AT91_SDRAMC_MDR                (AT91_SDRAMC + 0x24)    /* SDRAM Memory Device Register */
18400 +#define                AT91_SDRAMC_MD          (3 << 0)                /* Memory Device Type */
18401 +#define                        AT91_SDRAMC_MD_SDRAM            0
18402 +#define                        AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
18403 +
18404 +
18405 +/* Static Memory Controller (SMC) registers */
18406 +#define AT91_SMC_SETUP(n)      (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
18407 +#define                AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
18408 +#define                        AT91_SMC_NWESETUP_(x)   ((x) << 0)
18409 +#define                AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
18410 +#define                        AT91_SMC_NCS_WRSETUP_(x)        ((x) << 8)
18411 +#define                AT91_SMC_NRDSETUP       (0x3f << 16)                    /* NRD Setup Length */
18412 +#define                        AT91_SMC_NRDSETUP_(x)   ((x) << 16)
18413 +#define                AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
18414 +#define                        AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
18415 +
18416 +#define AT91_SMC_PULSE(n)      (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
18417 +#define                AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
18418 +#define                        AT91_SMC_NWEPULSE_(x)   ((x) << 0)
18419 +#define                AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
18420 +#define                        AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
18421 +#define                AT91_SMC_NRDPULSE       (0x7f << 16)                    /* NRD Pulse Length */
18422 +#define                        AT91_SMC_NRDPULSE_(x)   ((x) << 16)
18423 +#define                AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
18424 +#define                        AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
18425 +
18426 +#define AT91_SMC_CYCLE(n)      (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
18427 +#define                AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
18428 +#define                        AT91_SMC_NWECYCLE_(x)   ((x) << 0)
18429 +#define                AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
18430 +#define                        AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
18431 +
18432 +#define AT91_SMC_MODE(n)       (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
18433 +#define                AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
18434 +#define                AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
18435 +#define                AT91_SMC_EXNWMODE       (3 <<  5)                       /* NWAIT Mode */
18436 +#define                        AT91_SMC_EXNWMODE_DISABLE       (0 << 5)
18437 +#define                        AT91_SMC_EXNWMODE_FROZEN        (2 << 5)
18438 +#define                        AT91_SMC_EXNWMODE_READY         (3 << 5)
18439 +#define                AT91_SMC_BAT            (1 <<  8)                       /* Byte Access Type */
18440 +#define                        AT91_SMC_BAT_SELECT             (0 << 8)
18441 +#define                        AT91_SMC_BAT_WRITE              (1 << 8)
18442 +#define                AT91_SMC_DBW            (3 << 12)                       /* Data Bus Width */
18443 +#define                        AT91_SMC_DBW_8                  (0 << 12)
18444 +#define                        AT91_SMC_DBW_16                 (1 << 12)
18445 +#define                        AT91_SMC_DBW_32                 (2 << 12)
18446 +#define                AT91_SMC_TDF            (0xf << 16)                     /* Data Float Time. */
18447 +#define                        AT91_SMC_TDF_(x)                ((x) << 16)
18448 +#define                AT91_SMC_TDFMODE        (1 << 20)                       /* TDF Optimization - Enabled */
18449 +#define                AT91_SMC_PMEN           (1 << 24)                       /* Page Mode Enabled */
18450 +#define                AT91_SMC_PS             (3 << 28)                       /* Page Size */
18451 +#define                        AT91_SMC_PS_4                   (0 << 28)
18452 +#define                        AT91_SMC_PS_8                   (1 << 28)
18453 +#define                        AT91_SMC_PS_16                  (2 << 28)
18454 +#define                        AT91_SMC_PS_32                  (3 << 28)
18455 +
18456 +#endif
18457 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/board.h linux-2.6.19/include/asm-arm/arch-at91rm9200/board.h
18458 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/board.h  Mon Dec  4 16:41:04 2006
18459 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/board.h        Sat Nov 25 11:06:32 2006
18460 @@ -48,25 +48,26 @@
18461         u8      det_pin;                /* Card detect */
18462         u8      vcc_pin;                /* power switching */
18463         u8      rst_pin;                /* card reset */
18464 +       u8      chipselect;             /* EBI Chip Select number */
18465  };
18466  extern void __init at91_add_device_cf(struct at91_cf_data *data);
18467
18468   /* MMC / SD */
18469  struct at91_mmc_data {
18470         u8              det_pin;        /* card detect IRQ */
18471 -       unsigned        is_b:1;         /* uses B side (vs A) */
18472 +       unsigned        slot_b:1;       /* uses Slot B */
18473         unsigned        wire4:1;        /* (SD) supports DAT0..DAT3 */
18474         u8              wp_pin;         /* (SD) writeprotect detect */
18475         u8              vcc_pin;        /* power switching (high == on) */
18476  };
18477  extern void __init at91_add_device_mmc(struct at91_mmc_data *data);
18478
18479 - /* Ethernet */
18480 -struct at91_eth_data {
18481 +/* Ethernet (EMAC & MACB) */
18482 +struct eth_platform_data {
18483         u8              phy_irq_pin;    /* PHY IRQ */
18484         u8              is_rmii;        /* using RMII interface? */
18485  };
18486 -extern void __init at91_add_device_eth(struct at91_eth_data *data);
18487 +extern void __init at91_add_device_eth(struct eth_platform_data *data);
18488
18489   /* USB Host */
18490  struct at91_usbh_data {
18491 @@ -81,7 +82,8 @@
18492         u8              rdy_pin;        /* ready/busy */
18493         u8              ale;            /* address line number connected to ALE */
18494         u8              cle;            /* address line number connected to CLE */
18495 -        struct mtd_partition* (*partition_info)(int, int*);
18496 +       u8              bus_width_16;   /* buswidth is 16 bit */
18497 +       struct mtd_partition* (*partition_info)(int, int*);
18498  };
18499  extern void __init at91_add_device_nand(struct at91_nand_data *data);
18500
18501 @@ -112,4 +114,13 @@
18502  extern u8 at91_leds_timer;
18503  extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
18504
18505 +struct at91_gpio_led {
18506 +       u8              index;          /* index of LED */
18507 +       char*           name;           /* name of LED */
18508 +       u8              gpio;           /* AT91_PIN_xx */
18509 +       u8              flags;          /* 1=active-high */
18510 +       char*           trigger;        /* default trigger */
18511 +};
18512 +extern void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr);
18513 +
18514  #endif
18515 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/cpu.h linux-2.6.19/include/asm-arm/arch-at91rm9200/cpu.h
18516 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/cpu.h    Thu Jan  1 02:00:00 1970
18517 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/cpu.h  Wed Nov 15 11:59:16 2006
18518 @@ -0,0 +1,49 @@
18519 +/*
18520 + * include/asm-arm/arch-at91rm9200/cpu.h
18521 + *
18522 + *  Copyright (C) 2006 SAN People
18523 + *
18524 + * This program is free software; you can redistribute it and/or modify
18525 + * it under the terms of the GNU General Public License as published by
18526 + * the Free Software Foundation; either version 2 of the License, or
18527 + * (at your option) any later version.
18528 + *
18529 + */
18530 +
18531 +#ifndef __ASM_ARCH_CPU_H
18532 +#define __ASM_ARCH_CPU_H
18533 +
18534 +#include <asm/hardware.h>
18535 +#include <asm/arch/at91_dbgu.h>
18536 +
18537 +
18538 +#define ARCH_ID_AT91RM9200     0x09290780
18539 +#define ARCH_ID_AT91SAM9260    0x019803a0
18540 +#define ARCH_ID_AT91SAM9261    0x019703a0
18541 +
18542 +
18543 +static inline unsigned long at91_cpu_identify(void)
18544 +{
18545 +       return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
18546 +}
18547 +
18548 +
18549 +#ifdef CONFIG_ARCH_AT91RM9200
18550 +#define cpu_is_at91rm9200()    (at91_cpu_identify() == ARCH_ID_AT91RM9200)
18551 +#else
18552 +#define cpu_is_at91rm9200()    (0)
18553 +#endif
18554 +
18555 +#ifdef CONFIG_ARCH_AT91SAM9260
18556 +#define cpu_is_at91sam9260()   (at91_cpu_identify() == ARCH_ID_AT91SAM9260)
18557 +#else
18558 +#define cpu_is_at91sam9260()   (0)
18559 +#endif
18560 +
18561 +#ifdef CONFIG_ARCH_AT91SAM9261
18562 +#define cpu_is_at91sam9261()   (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
18563 +#else
18564 +#define cpu_is_at91sam9261()   (0)
18565 +#endif
18566 +
18567 +#endif
18568 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/debug-macro.S linux-2.6.19/include/asm-arm/arch-at91rm9200/debug-macro.S
18569 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/debug-macro.S    Tue May 30 11:42:13 2006
18570 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/debug-macro.S  Tue Oct 24 16:04:30 2006
18571 @@ -12,6 +12,7 @@
18572  */
18573
18574  #include <asm/hardware.h>
18575 +#include <asm/arch/at91_dbgu.h>
18576
18577         .macro  addruart,rx
18578         mrc     p15, 0, \rx, c1, c0
18579 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/entry-macro.S linux-2.6.19/include/asm-arm/arch-at91rm9200/entry-macro.S
18580 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/entry-macro.S    Tue May 30 11:42:13 2006
18581 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/entry-macro.S  Tue Oct 24 16:15:21 2006
18582 @@ -11,6 +11,7 @@
18583   */
18584
18585  #include <asm/hardware.h>
18586 +#include <asm/arch/at91_aic.h>
18587
18588         .macro  disable_fiq
18589         .endm
18590 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/hardware.h linux-2.6.19/include/asm-arm/arch-at91rm9200/hardware.h
18591 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/hardware.h       Mon Dec  4 16:41:04 2006
18592 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/hardware.h     Wed Nov 15 09:21:41 2006
18593 @@ -16,8 +16,16 @@
18594
18595  #include <asm/sizes.h>
18596
18597 +#if defined(CONFIG_ARCH_AT91RM9200)
18598  #include <asm/arch/at91rm9200.h>
18599 -#include <asm/arch/at91rm9200_sys.h>
18600 +#elif defined(CONFIG_ARCH_AT91SAM9260)
18601 +#include <asm/arch/at91sam9260.h>
18602 +#elif defined(CONFIG_ARCH_AT91SAM9261)
18603 +#include <asm/arch/at91sam9261.h>
18604 +#else
18605 +#error "Unsupported AT91 processor"
18606 +#endif
18607 +
18608
18609  /*
18610   * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF
18611 @@ -34,29 +42,27 @@
18612   * Virtual to Physical Address mapping for IO devices.
18613   */
18614  #define AT91_VA_BASE_SYS       AT91_IO_P2V(AT91_BASE_SYS)
18615 -#define AT91_VA_BASE_SPI       AT91_IO_P2V(AT91RM9200_BASE_SPI)
18616  #define AT91_VA_BASE_EMAC      AT91_IO_P2V(AT91RM9200_BASE_EMAC)
18617 -#define AT91_VA_BASE_TWI       AT91_IO_P2V(AT91RM9200_BASE_TWI)
18618 -#define AT91_VA_BASE_MCI       AT91_IO_P2V(AT91RM9200_BASE_MCI)
18619 -#define AT91_VA_BASE_UDP       AT91_IO_P2V(AT91RM9200_BASE_UDP)
18620
18621   /* Internal SRAM is mapped below the IO devices */
18622 -#define AT91_SRAM_VIRT_BASE    (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE)
18623 +#define AT91_SRAM_MAX          SZ_1M
18624 +#define AT91_VIRT_BASE         (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
18625
18626  /* Serial ports */
18627 -#define ATMEL_MAX_UART         5               /* 4 USART3's and one DBGU port */
18628 +#define ATMEL_MAX_UART         7               /* 6 USART3's and one DBGU port (SAM9260) */
18629
18630 -/* FLASH */
18631 -#define AT91_FLASH_BASE                0x10000000      /* NCS0: Flash physical base address */
18632 +/* External Memory Map */
18633 +#define AT91_CHIPSELECT_0      0x10000000
18634 +#define AT91_CHIPSELECT_1      0x20000000
18635 +#define AT91_CHIPSELECT_2      0x30000000
18636 +#define AT91_CHIPSELECT_3      0x40000000
18637 +#define AT91_CHIPSELECT_4      0x50000000
18638 +#define AT91_CHIPSELECT_5      0x60000000
18639 +#define AT91_CHIPSELECT_6      0x70000000
18640 +#define AT91_CHIPSELECT_7      0x80000000
18641
18642  /* SDRAM */
18643 -#define AT91_SDRAM_BASE                0x20000000      /* NCS1: SDRAM physical base address */
18644 -
18645 -/* SmartMedia */
18646 -#define AT91_SMARTMEDIA_BASE   0x40000000      /* NCS3: Smartmedia physical base address */
18647 -
18648 -/* Compact Flash */
18649 -#define AT91_CF_BASE           0x50000000      /* NCS4-NCS6: Compact Flash physical base address */
18650 +#define AT91_SDRAM_BASE                AT91_CHIPSELECT_1
18651
18652  /* Clocks */
18653  #define AT91_SLOW_CLOCK                32768           /* slow clock */
18654 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/ics1523.h linux-2.6.19/include/asm-arm/arch-at91rm9200/ics1523.h
18655 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/ics1523.h        Thu Jan  1 02:00:00 1970
18656 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/ics1523.h      Tue Oct 17 08:29:21 2006
18657 @@ -0,0 +1,162 @@
18658 +//*----------------------------------------------------------------------------
18659 +//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
18660 +//*----------------------------------------------------------------------------
18661 +//* The software is delivered "AS IS" without warranty or condition of any
18662 +//* kind, either express, implied or statutory. This includes without
18663 +//* limitation any warranty or condition with respect to merchantability or
18664 +//* fitness for any particular purpose, or against the infringements of
18665 +//* intellectual property rights of others.
18666 +//*----------------------------------------------------------------------------
18667 +//* File Name           : ics1523.h
18668 +//* Object              : Clock Generator Prototyping File.
18669 +//*
18670 +//* 1.0 08/28/02 ED     : Creation
18671 +//* 1.2 13/01/03 FB            : Update on lib V3
18672 +//*----------------------------------------------------------------------------
18673 +
18674 +#ifndef ics1523_h
18675 +#define ics1523_h
18676 +
18677 +/* Standard configurations definitions */
18678 +#define                Clock_Conf              0x0
18679 +
18680 +/*-------------------------------------------*/
18681 +/* ICS1523 TWI Serial Clock Definition       */
18682 +/*-------------------------------------------*/
18683 +
18684 +#define                ICS_MIN_CLOCK           100             /* Min Frequency Access Clock KHz */
18685 +#define                ICS_MAX_CLOCK           400             /* Max Frequency Access Clock KHz */
18686 +#define                ICS_TRANSFER_RATE       ICS_MAX_CLOCK   /* Transfer speed to apply */
18687 +
18688 +#define                ICS_WRITE_CLK_PNB       30              /* TWCK Clock Periods required to write */
18689 +#define                ICS_READ_CLK_PNB        40              /* TWCK Clock Periods required to read */
18690 +
18691 +/*-------------------------------------------*/
18692 +/* ICS1523 Write Operation Definition        */
18693 +/*-------------------------------------------*/
18694 +
18695 +#define                ICS1523_ACCESS_OK       0               /* OK */
18696 +#define                ICS1523_ACCESS_ERROR    -1              /* NOK */
18697 +
18698 +/*-------------------------------------------*/
18699 +/* ICS1523 Device Addresses Definition       */
18700 +/*-------------------------------------------*/
18701 +
18702 +#define                ICS_ADD                 0x26            /* Device Address */
18703 +
18704 +/*--------------------------------------------------*/
18705 +/* ICS1523 Registers Internal Addresses Definition  */
18706 +/*--------------------------------------------------*/
18707 +
18708 +#define                ICS_ICR                 0x0             /* Input Control Register */
18709 +#define                ICS_LCR                 0x1             /* Loop Control Register */
18710 +#define                ICS_FD0                 0x2             /* PLL FeedBack Divider LSBs */
18711 +#define                ICS_FD1                 0x3             /* PLL FeedBack Divider MSBs */
18712 +#define                ICS_DPAO                0x4             /* Dynamic Phase Aligner Offset */
18713 +#define                ICS_DPAC                0x5             /* Dynamic Phase Aligner Resolution */
18714 +#define                ICS_OE                  0x6             /* Output Enables Register */
18715 +#define                ICS_OD                  0x7             /* Osc Divider Register */
18716 +#define                ICS_SWRST               0x8             /* DPA & PLL Reset Register */
18717 +#define                ICS_VID                 0x10            /* Chip Version Register */
18718 +#define                ICS_RID                 0x11            /* Chip Revision Register */
18719 +#define                ICS_SR                  0x12            /* Status Register */
18720 +
18721 +/*------------------------------------------------------*/
18722 +/* ICS1523 Input Control Register Bits Definition       */
18723 +/*------------------------------------------------------*/
18724 +
18725 +#define                ICS_PDEN                0x1             /* Phase Detector Enable */
18726 +#define                ICS_PDPOL               0x2             /* Phase Detector Enable Polarity */
18727 +#define                ICS_REFPOL              0x4             /* External Reference Polarity */
18728 +#define                ICS_FBKPOL              0x8             /* External Feedback Polarity */
18729 +#define                ICS_FBKSEL              0x10            /* External Feedback Select */
18730 +#define                ICS_FUNCSEL             0x20            /* Function Out Select */
18731 +#define                ICS_ENPLS               0x40            /* Enable PLL Lock/Ref Status Output */
18732 +#define                ICS_ENDLS               0x80            /* Enable DPA Lock/Ref Status Output */
18733 +
18734 +/*-----------------------------------------------------*/
18735 +/* ICS1523 Loop Control Register Bits Definition       */
18736 +/*-----------------------------------------------------*/
18737 +
18738 +#define                ICS_PFD                 0x7             /* Phase Detector Gain */
18739 +#define                ICS_PSD                 0x30            /* Post-Scaler Divider */
18740 +
18741 +/*----------------------------------------------------*/
18742 +/* ICS1523 PLL FeedBack Divider LSBs Definition       */
18743 +/*----------------------------------------------------*/
18744 +
18745 +#define                ICS_FBDL                0xFF            /* PLL FeedBack Divider LSBs */
18746 +
18747 +/*----------------------------------------------------*/
18748 +/* ICS1523 PLL FeedBack Divider MSBs Definition       */
18749 +/*----------------------------------------------------*/
18750 +
18751 +#define                ICS_FBDM                0xF             /* PLL FeedBack Divider MSBs */
18752 +
18753 +/*------------------------------------------------------------*/
18754 +/* ICS1523 Dynamic Phase Aligner Offset Bits Definition       */
18755 +/*------------------------------------------------------------*/
18756 +
18757 +#define                ICS_DPAOS               0x2F            /* Dynamic Phase Aligner Offset */
18758 +#define                ICS_FILSEL              0x80            /* Loop Filter Select */
18759 +
18760 +/*----------------------------------------------------------------*/
18761 +/* ICS1523 Dynamic Phase Aligner Resolution Bits Definition       */
18762 +/*----------------------------------------------------------------*/
18763 +
18764 +#define                ICS_DPARES              0x3             /* Dynamic Phase Aligner Resolution */
18765 +#define                ICS_MMREV               0xFC            /* Metal Mask Revision Number */
18766 +
18767 +/*-------------------------------------------------------*/
18768 +/* ICS1523 Output Enables Register Bits Definition       */
18769 +/*-------------------------------------------------------*/
18770 +
18771 +#define                ICS_OEPCK               0x1             /* Output Enable for PECL PCLK Outputs */
18772 +#define                ICS_OETCK               0x2             /* Output Enable for STTL CLK Output */
18773 +#define                ICS_OEP2                0x4             /* Output Enable for PECL CLK/2 Outputs */
18774 +#define                ICS_OET2                0x8             /* Output Enable for STTL CLK/2 Output */
18775 +#define                ICS_OEF                 0x10            /* Output Enable for STTL FUNC Output */
18776 +#define                ICS_CLK2INV             0x20            /* CLK/2 Invert */
18777 +#define                ICS_OSCL                0xC0            /* SSTL Clock Scaler */
18778 +
18779 +/*----------------------------------------------------*/
18780 +/* ICS1523 Osc Divider Register Bits Definition       */
18781 +/*----------------------------------------------------*/
18782 +
18783 +#define                ICS_OSCDIV              0x7F            /* Oscillator Divider Modulus */
18784 +#define                ICS_INSEL               0x80            /* Input Select */
18785 +
18786 +/*---------------------------------------------------*/
18787 +/* ICS1523 DPA & PLL Reset Register Definition       */
18788 +/*---------------------------------------------------*/
18789 +
18790 +#define                ICS_DPAR                0x0A            /* DPA Reset Command */
18791 +#define                ICS_PLLR                0x50            /* PLL Reset Command */
18792 +
18793 +/*------------------------------------------------*/
18794 +/* ICS1523 Chip Version Register Definition       */
18795 +/*------------------------------------------------*/
18796 +
18797 +#define                ICS_CHIPV               0xFF            /* Chip Version */
18798 +
18799 +/*-------------------------------------------------*/
18800 +/* ICS1523 Chip Revision Register Definition       */
18801 +/*-------------------------------------------------*/
18802 +
18803 +#define                ICS_CHIPR               0xFF            /* Chip Revision */
18804 +
18805 +/*------------------------------------------*/
18806 +/* ICS1523 Status Register Definition       */
18807 +/*------------------------------------------*/
18808 +
18809 +#define                ICS_DPALOCK             0x1             /* DPA Lock Status */
18810 +#define                ICS_PLLLOCK             0x2             /* PLL Lock Status */
18811 +
18812 +/* Time constants definition */
18813 +#define                TIMEOUT_OF_300us        3       // (10*100)us
18814 +#define                TIMEOUT_OF_1000us       10      // (10*100)us
18815 +
18816 +/* Function Prototyping ics1523.c */
18817 +int AT91F_ICS1523_clockinit(void);
18818 +
18819 +#endif /* ics1523_h */
18820 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/irqs.h linux-2.6.19/include/asm-arm/arch-at91rm9200/irqs.h
18821 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/irqs.h   Mon Dec  4 16:41:04 2006
18822 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/irqs.h Tue Oct 24 16:15:59 2006
18823 @@ -21,6 +21,8 @@
18824  #ifndef __ASM_ARCH_IRQS_H
18825  #define __ASM_ARCH_IRQS_H
18826
18827 +#include <asm/arch/at91_aic.h>
18828 +
18829  #define NR_AIC_IRQS 32
18830
18831
18832 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/spi.h linux-2.6.19/include/asm-arm/arch-at91rm9200/spi.h
18833 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/spi.h    Thu Jan  1 02:00:00 1970
18834 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/spi.h  Tue Oct 24 14:26:47 2006
18835 @@ -0,0 +1,54 @@
18836 +/*
18837 + * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200
18838 + *
18839 + * (c) SAN People (Pty) Ltd
18840 + *
18841 + * This program is free software; you can redistribute it and/or
18842 + * modify it under the terms of the GNU General Public License
18843 + * as published by the Free Software Foundation; either version
18844 + * 2 of the License, or (at your option) any later version.
18845 + */
18846 +
18847 +#ifndef AT91_LEGACY_SPI_H
18848 +#define AT91_LEGACY_SPI_H
18849 +
18850 +#define SPI_MAJOR              153     /* registered device number */
18851 +
18852 +#define DEFAULT_SPI_CLK                6000000
18853 +
18854 +
18855 +/* Maximum number of buffers in a single SPI transfer.
18856 + *  DataFlash uses maximum of 2
18857 + *  spidev interface supports up to 8.
18858 + */
18859 +#define MAX_SPI_TRANSFERS      8
18860 +#define NR_SPI_DEVICES         4       /* number of devices on SPI bus */
18861 +
18862 +/*
18863 + * Describes the buffers for a SPI transfer.
18864 + * A transmit & receive buffer must be specified for each transfer
18865 + */
18866 +struct spi_transfer_list {
18867 +       void* tx[MAX_SPI_TRANSFERS];    /* transmit */
18868 +       int txlen[MAX_SPI_TRANSFERS];
18869 +       void* rx[MAX_SPI_TRANSFERS];    /* receive */
18870 +       int rxlen[MAX_SPI_TRANSFERS];
18871 +       int nr_transfers;               /* number of transfers */
18872 +       int curr;                       /* current transfer */
18873 +};
18874 +
18875 +struct spi_local {
18876 +       unsigned int pcs;               /* Peripheral Chip Select value */
18877 +
18878 +       struct spi_transfer_list *xfers;        /* current transfer list */
18879 +       dma_addr_t tx, rx;              /* DMA address for current transfer */
18880 +       dma_addr_t txnext, rxnext;      /* DMA address for next transfer */
18881 +};
18882 +
18883 +
18884 +/* Exported functions */
18885 +extern void spi_access_bus(short device);
18886 +extern void spi_release_bus(short device);
18887 +extern int spi_transfer(struct spi_transfer_list* list);
18888 +
18889 +#endif
18890 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/system.h linux-2.6.19/include/asm-arm/arch-at91rm9200/system.h
18891 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/system.h Mon Dec  4 16:34:19 2006
18892 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/system.h       Mon Dec  4 16:00:33 2006
18893 @@ -22,6 +22,8 @@
18894  #define __ASM_ARCH_SYSTEM_H
18895
18896  #include <asm/hardware.h>
18897 +#include <asm/arch/at91_st.h>
18898 +#include <asm/arch/at91_dbgu.h>
18899
18900  static inline void arch_idle(void)
18901  {
18902 @@ -39,21 +41,13 @@
18903         cpu_do_idle();
18904  }
18905
18906 -static inline void arch_reset(char mode)
18907 -{
18908 -       /*
18909 -        * Perform a hardware reset with the use of the Watchdog timer.
18910 -        */
18911 -       at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
18912 -       at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
18913 -}
18914 -
18915 -#define ARCH_ID_AT91RM9200     0x09200080
18916 -#define ARCH_ID_AT91SAM9261    0x019000a0
18917 +void (*at91_arch_reset)(void);
18918
18919 -static inline unsigned long arch_identify(void)
18920 +static inline void arch_reset(char mode)
18921  {
18922 -       return at91_sys_read(AT91_DBGU_CIDR) & (AT91_CIDR_EPROC | AT91_CIDR_ARCH);
18923 +       /* call the CPU-specific reset function */
18924 +       if (at91_arch_reset)
18925 +               (at91_arch_reset)();
18926  }
18927
18928  #endif
18929 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/timex.h linux-2.6.19/include/asm-arm/arch-at91rm9200/timex.h
18930 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/timex.h  Mon Dec  4 16:34:19 2006
18931 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/timex.h        Wed Nov 15 08:55:07 2006
18932 @@ -23,6 +23,15 @@
18933
18934  #include <asm/hardware.h>
18935
18936 +#if defined(CONFIG_ARCH_AT91RM9200)
18937 +
18938  #define CLOCK_TICK_RATE                (AT91_SLOW_CLOCK)
18939
18940 +#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261)
18941 +
18942 +#define AT91SAM9_MASTER_CLOCK  99300000
18943 +#define CLOCK_TICK_RATE                (AT91SAM9_MASTER_CLOCK/16)
18944 +
18945 +#endif
18946 +
18947  #endif
18948 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/uncompress.h linux-2.6.19/include/asm-arm/arch-at91rm9200/uncompress.h
18949 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/uncompress.h     Mon Dec  4 16:34:19 2006
18950 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/uncompress.h   Tue Oct 24 16:11:39 2006
18951 @@ -22,11 +22,11 @@
18952  #define __ASM_ARCH_UNCOMPRESS_H
18953
18954  #include <asm/hardware.h>
18955 +#include <asm/arch/at91_dbgu.h>
18956
18957  /*
18958   * The following code assumes the serial port has already been
18959 - * initialized by the bootloader.  We search for the first enabled
18960 - * port in the most probable order.  If you didn't setup a port in
18961 + * initialized by the bootloader.  If you didn't setup a port in
18962   * your bootloader then nothing will appear (which might be desired).
18963   *
18964   * This does not append a newline
18965 diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/vmalloc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/vmalloc.h
18966 --- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/vmalloc.h        Mon Dec  4 16:34:19 2006
18967 +++ linux-2.6.19/include/asm-arm/arch-at91rm9200/vmalloc.h      Wed Nov  1 15:26:48 2006
18968 @@ -21,6 +21,6 @@
18969  #ifndef __ASM_ARCH_VMALLOC_H
18970  #define __ASM_ARCH_VMALLOC_H
18971
18972 -#define VMALLOC_END            (AT91_SRAM_VIRT_BASE & PGDIR_MASK)
18973 +#define VMALLOC_END            (AT91_VIRT_BASE & PGDIR_MASK)
18974
18975  #endif
18976 diff -urN -x CVS linux-2.6.19-final/include/asm-avr32/arch-at32ap/at91_pdc.h linux-2.6.19/include/asm-avr32/arch-at32ap/at91_pdc.h
18977 --- linux-2.6.19-final/include/asm-avr32/arch-at32ap/at91_pdc.h Thu Jan  1 02:00:00 1970
18978 +++ linux-2.6.19/include/asm-avr32/arch-at32ap/at91_pdc.h       Tue Oct 24 15:32:59 2006
18979 @@ -0,0 +1,36 @@
18980 +/*
18981 + * include/asm-arm/arch-at91rm9200/at91_pdc.h
18982 + *
18983 + * Copyright (C) 2005 Ivan Kokshaysky
18984 + * Copyright (C) SAN People
18985 + *
18986 + * Peripheral Data Controller (PDC) registers.
18987 + * Based on AT91RM9200 datasheet revision E.
18988 + *
18989 + * This program is free software; you can redistribute it and/or modify
18990 + * it under the terms of the GNU General Public License as published by
18991 + * the Free Software Foundation; either version 2 of the License, or
18992 + * (at your option) any later version.
18993 + */
18994 +
18995 +#ifndef AT91_PDC_H
18996 +#define AT91_PDC_H
18997 +
18998 +#define AT91_PDC_RPR           0x100   /* Receive Pointer Register */
18999 +#define AT91_PDC_RCR           0x104   /* Receive Counter Register */
19000 +#define AT91_PDC_TPR           0x108   /* Transmit Pointer Register */
19001 +#define AT91_PDC_TCR           0x10c   /* Transmit Counter Register */
19002 +#define AT91_PDC_RNPR          0x110   /* Receive Next Pointer Register */
19003 +#define AT91_PDC_RNCR          0x114   /* Receive Next Counter Register */
19004 +#define AT91_PDC_TNPR          0x118   /* Transmit Next Pointer Register */
19005 +#define AT91_PDC_TNCR          0x11c   /* Transmit Next Counter Register */
19006 +
19007 +#define AT91_PDC_PTCR          0x120   /* Transfer Control Register */
19008 +#define                AT91_PDC_RXTEN          (1 << 0)        /* Receiver Transfer Enable */
19009 +#define                AT91_PDC_RXTDIS         (1 << 1)        /* Receiver Transfer Disable */
19010 +#define                AT91_PDC_TXTEN          (1 << 8)        /* Transmitter Transfer Enable */
19011 +#define                AT91_PDC_TXTDIS         (1 << 9)        /* Transmitter Transfer Disable */
19012 +
19013 +#define AT91_PDC_PTSR          0x124   /* Transfer Status Register */
19014 +
19015 +#endif
19016 diff -urN -x CVS linux-2.6.19-final/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h linux-2.6.19/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h
19017 --- linux-2.6.19-final/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h   Mon Dec  4 16:41:06 2006
19018 +++ linux-2.6.19/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h Thu Jan  1 02:00:00 1970
19019 @@ -1,36 +0,0 @@
19020 -/*
19021 - * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
19022 - *
19023 - * Copyright (C) 2005 Ivan Kokshaysky
19024 - * Copyright (C) SAN People
19025 - *
19026 - * Peripheral Data Controller (PDC) registers.
19027 - * Based on AT91RM9200 datasheet revision E.
19028 - *
19029 - * This program is free software; you can redistribute it and/or modify
19030 - * it under the terms of the GNU General Public License as published by
19031 - * the Free Software Foundation; either version 2 of the License, or
19032 - * (at your option) any later version.
19033 - */
19034 -
19035 -#ifndef AT91RM9200_PDC_H
19036 -#define AT91RM9200_PDC_H
19037 -
19038 -#define AT91_PDC_RPR           0x100   /* Receive Pointer Register */
19039 -#define AT91_PDC_RCR           0x104   /* Receive Counter Register */
19040 -#define AT91_PDC_TPR           0x108   /* Transmit Pointer Register */
19041 -#define AT91_PDC_TCR           0x10c   /* Transmit Counter Register */
19042 -#define AT91_PDC_RNPR          0x110   /* Receive Next Pointer Register */
19043 -#define AT91_PDC_RNCR          0x114   /* Receive Next Counter Register */
19044 -#define AT91_PDC_TNPR          0x118   /* Transmit Next Pointer Register */
19045 -#define AT91_PDC_TNCR          0x11c   /* Transmit Next Counter Register */
19046 -
19047 -#define AT91_PDC_PTCR          0x120   /* Transfer Control Register */
19048 -#define                AT91_PDC_RXTEN          (1 << 0)        /* Receiver Transfer Enable */
19049 -#define                AT91_PDC_RXTDIS         (1 << 1)        /* Receiver Transfer Disable */
19050 -#define                AT91_PDC_TXTEN          (1 << 8)        /* Transmitter Transfer Enable */
19051 -#define                AT91_PDC_TXTDIS         (1 << 9)        /* Transmitter Transfer Disable */
19052 -
19053 -#define AT91_PDC_PTSR          0x124   /* Transfer Status Register */
19054 -
19055 -#endif
19056 diff -urN -x CVS linux-2.6.19-final/include/linux/i2c-id.h linux-2.6.19/include/linux/i2c-id.h
19057 --- linux-2.6.19-final/include/linux/i2c-id.h   Mon Dec  4 16:41:13 2006
19058 +++ linux-2.6.19/include/linux/i2c-id.h Thu Oct 12 17:07:39 2006
19059 @@ -202,6 +202,7 @@
19060
19061  /* --- PCA 9564 based algorithms */
19062  #define I2C_HW_A_ISA           0x1a0000 /* generic ISA Bus interface card */
19063 +#define I2C_HW_A_PLAT          0x1a0001 /* generic platform_bus interface */
19064
19065  /* --- ACPI Embedded controller algorithms                              */
19066  #define I2C_HW_ACPI_EC          0x1f0000