target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
   7  * Copyright (C) 2006 FON Technology, SL.
   8  * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
   9  * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  10  */
  11
  12 /*
  13  * Platform devices for Atheros SoCs
  14  */
  15
  16 #include <linux/autoconf.h>
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/types.h>
  20 #include <linux/string.h>
  21 #include <linux/mtd/physmap.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/kernel.h>
  24 #include <linux/reboot.h>
  25 #include <asm/bootinfo.h>
  26 #include <asm/reboot.h>
  27 #include <asm/time.h>
  28 #include <asm/irq.h>
  29 #include <asm/io.h>
  30 #include "ar531x.h"
  31
  32 #define NO_PHY 0x1f
  33
  34 static int is_5312 = 0;
  35 static struct platform_device *ar5312_devs[5];
  36
  37 static struct resource ar5312_eth0_res[] = {
  38         {
  39                 .name = "eth0_membase",
  40                 .flags = IORESOURCE_MEM,
  41                 .start = KSEG1ADDR(AR531X_ENET0),
  42                 .end = KSEG1ADDR(AR531X_ENET0 + 0x2000),
  43         },
  44         {
  45                 .name = "eth0_irq",
  46                 .flags = IORESOURCE_IRQ,
  47                 .start = AR5312_IRQ_ENET0_INTRS,
  48                 .end = AR5312_IRQ_ENET0_INTRS,
  49         },
  50 };
  51 static struct ar531x_eth ar5312_eth0_data = {
  52         .phy = NO_PHY,
  53         .mac = 0,
  54         .reset_base = AR531X_RESET,
  55         .reset_mac = AR531X_RESET_ENET0,
  56         .reset_phy = AR531X_RESET_EPHY0,
  57         .phy_base = KSEG1ADDR(AR531X_ENET0),
  58 };
  59
  60 static struct resource ar5312_eth1_res[] = {
  61         {
  62                 .name = "eth1_membase",
  63                 .flags = IORESOURCE_MEM,
  64                 .start = KSEG1ADDR(AR531X_ENET1),
  65                 .end = KSEG1ADDR(AR531X_ENET1 + 0x2000),
  66         },
  67         {
  68                 .name = "eth1_irq",
  69                 .flags = IORESOURCE_IRQ,
  70                 .start = AR5312_IRQ_ENET1_INTRS,
  71                 .end = AR5312_IRQ_ENET1_INTRS,
  72         },
  73 };
  74 static struct ar531x_eth ar5312_eth1_data = {
  75         .phy = NO_PHY,
  76         .mac = 1,
  77         .reset_base = AR531X_RESET,
  78         .reset_mac = AR531X_RESET_ENET1,
  79         .reset_phy = AR531X_RESET_EPHY1,
  80         .phy_base = KSEG1ADDR(AR531X_ENET1),
  81 };
  82
  83 static struct platform_device ar5312_eth[] = {
  84         {
  85                 .id = 0,
  86                 .name = "ar531x-eth",
  87                 .dev.platform_data = &ar5312_eth0_data,
  88                 .resource = ar5312_eth0_res,
  89                 .num_resources = ARRAY_SIZE(ar5312_eth0_res)
  90         },
  91         {
  92                 .id = 1,
  93                 .name = "ar531x-eth",
  94                 .dev.platform_data = &ar5312_eth1_data,
  95                 .resource = ar5312_eth1_res,
  96                 .num_resources = ARRAY_SIZE(ar5312_eth1_res)
  97         },
  98 };
  99
 100
 101 /*
 102  * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
 103  * of ENET1. Atheros calls it 'twisted' for a reason :)
 104  */
 105 static struct resource ar231x_eth0_res[] = {
 106         {
 107                 .name = "eth0_membase",
 108                 .flags = IORESOURCE_MEM,
 109                 .start = KSEG1ADDR(AR531X_ENET1),
 110                 .end = KSEG1ADDR(AR531X_ENET1 + 0x2000),
 111         },
 112         {
 113                 .name = "eth0_irq",
 114                 .flags = IORESOURCE_IRQ,
 115                 .start = AR5312_IRQ_ENET1_INTRS,
 116                 .end = AR5312_IRQ_ENET1_INTRS,
 117         },
 118 };
 119 static struct ar531x_eth ar231x_eth0_data = {
 120         .phy = 1,
 121         .mac = 1,
 122         .reset_base = AR531X_RESET,
 123         .reset_mac = AR531X_RESET_ENET1,
 124         .reset_phy = AR531X_RESET_EPHY1,
 125         .phy_base = KSEG1ADDR(AR531X_ENET0),
 126 };
 127 static struct platform_device ar231x_eth0 = {
 128         .id = 0,
 129         .name = "ar531x-eth",
 130         .dev.platform_data = &ar231x_eth0_data,
 131         .resource = ar231x_eth0_res,
 132         .num_resources = ARRAY_SIZE(ar231x_eth0_res)
 133 };
 134
 135
 136 static struct platform_device ar5312_wmac[] = {
 137         {
 138                 .id = 0,
 139                 .name = "ar531x-wmac",
 140         },
 141         {
 142                 .id = 1,
 143                 .name = "ar531x-wmac",
 144         },
 145 };
 146
 147 static struct physmap_flash_data ar5312_flash_data = {
 148         .width    = 2,
 149 };
 150
 151 static struct resource ar5312_flash_resource = {
 152         .start  = AR531X_FLASH,
 153         .end    = AR531X_FLASH + 0x400000 - 1,
 154         .flags  = IORESOURCE_MEM,
 155 };
 156
 157 static struct platform_device ar5312_physmap_flash = {
 158         .name      = "physmap-flash",
 159         .id      = 0,
 160         .dev            = {
 161                 .platform_data  = &ar5312_flash_data,
 162         },
 163         .num_resources  = 1,
 164         .resource   = &ar5312_flash_resource,
 165 };
 166
 167
 168 /*
 169  * NB: This mapping size is larger than the actual flash size,
 170  * but this shouldn't be a problem here, because the flash
 171  * will simply be mapped multiple times.
 172  */
 173 static char __init *ar5312_flash_limit(void)
 174 {
 175         u32 ctl;
 176         /*
 177          * Configure flash bank 0.
 178          * Assume 8M window size. Flash will be aliased if it's smaller
 179          */
 180         ctl = FLASHCTL_E |
 181                 FLASHCTL_AC_8M |
 182                 FLASHCTL_RBLE |
 183                 (0x01 << FLASHCTL_IDCY_S) |
 184                 (0x07 << FLASHCTL_WST1_S) |
 185                 (0x07 << FLASHCTL_WST2_S) |
 186                 (sysRegRead(AR531X_FLASHCTL0) & FLASHCTL_MW);
 187
 188         sysRegWrite(AR531X_FLASHCTL0, ctl);
 189
 190         /* Disable other flash banks */
 191         sysRegWrite(AR531X_FLASHCTL1,
 192                 sysRegRead(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
 193
 194         sysRegWrite(AR531X_FLASHCTL2,
 195                 sysRegRead(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
 196
 197         return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
 198 }
 199
 200 static struct ar531x_config __init *init_wmac(int unit)
 201 {
 202         struct ar531x_config *config;
 203
 204         config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
 205         config->board = board_config;
 206         config->radio = radio_config;
 207         config->unit = unit;
 208         config->tag = (u_int16_t) ((sysRegRead(AR531X_REV) >> AR531X_REV_WMAC_MIN_S) & AR531X_REV_CHIP);
 209
 210         return config;
 211 }
 212
 213 int __init ar5312_init_devices(void)
 214 {
 215         struct ar531x_boarddata *bcfg;
 216         char *radio, *c;
 217         int dev = 0;
 218
 219         if (!is_5312)
 220                 return 0;
 221
 222         /* Locate board/radio config data */
 223         ar531x_find_config(ar5312_flash_limit());
 224         bcfg = (struct ar531x_boarddata *) board_config;
 225
 226
 227         /*
 228          * Chip IDs and hardware detection for some Atheros
 229          * models are really broken!
 230          *
 231          * Atheros uses a disabled WMAC0 and Silicon ID of AR5312
 232          * as indication for AR2312, which is otherwise
 233          * indistinguishable from the real AR5312.
 234          */
 235         if (radio_config) {
 236                 radio = radio_config + AR531X_RADIO_MASK_OFF;
 237                 if ((*((u32 *) radio) & AR531X_RADIO0_MASK) == 0)
 238                         bcfg->config |= BD_ISCASPER;
 239         } else
 240                 radio = NULL;
 241
 242         /* AR2313 has CPU minor rev. 10 */
 243         if ((current_cpu_data.processor_id & 0xff) == 0x0a)
 244                 mips_machtype = MACH_ATHEROS_AR2313;
 245
 246         /* AR2312 shares the same Silicon ID as AR5312 */
 247         else if (bcfg->config & BD_ISCASPER)
 248                 mips_machtype = MACH_ATHEROS_AR2312;
 249
 250         /* Everything else is probably AR5312 or compatible */
 251         else
 252                 mips_machtype = MACH_ATHEROS_AR5312;
 253
 254         ar5312_eth0_data.board_config = board_config;
 255         ar5312_eth1_data.board_config = board_config;
 256         ar5312_devs[dev++] = &ar5312_physmap_flash;
 257
 258         if (!memcmp(bcfg->enet0Mac, "\xff\xff\xff\xff\xff\xff", 6))
 259                 memcpy(bcfg->enet0Mac, bcfg->enet1Mac, 6);
 260
 261         if (memcmp(bcfg->enet0Mac, bcfg->enet1Mac, 6) == 0) {
 262                 /* ENET0 and ENET1 have the same mac.
 263                  * Increment the one from ENET1 */
 264                 c = bcfg->enet1Mac + 5;
 265                 while ((c >= (char *) bcfg->enet1Mac) && !(++(*c)))
 266                         c--;
 267         }
 268
 269         switch(mips_machtype) {
 270                 case MACH_ATHEROS_AR5312:
 271                         ar5312_eth0_data.macaddr = bcfg->enet0Mac;
 272                         ar5312_eth1_data.macaddr = bcfg->enet1Mac;
 273                         ar5312_devs[dev++] = &ar5312_eth[0];
 274                         ar5312_devs[dev++] = &ar5312_eth[1];
 275                         break;
 276                 case MACH_ATHEROS_AR2312:
 277                 case MACH_ATHEROS_AR2313:
 278                         ar231x_eth0_data.macaddr = bcfg->enet0Mac;
 279                         ar5312_devs[dev++] = &ar231x_eth0;
 280                         ar5312_flash_data.width = 1;
 281                         break;
 282         }
 283
 284         if (radio) {
 285                 if (*((u32 *) radio) & AR531X_RADIO0_MASK) {
 286                         ar5312_wmac[0].dev.platform_data = init_wmac(0);
 287                         ar5312_devs[dev++] = &ar5312_wmac[0];
 288                 }
 289                 if (*((u32 *) radio) & AR531X_RADIO1_MASK) {
 290                         ar5312_wmac[1].dev.platform_data = init_wmac(1);
 291                         ar5312_devs[dev++] = &ar5312_wmac[1];
 292                 }
 293         }
 294
 295         return platform_add_devices(ar5312_devs, dev);
 296 }
 297
 298
 299 /*
 300  * Called when an interrupt is received, this function
 301  * determines exactly which interrupt it was, and it
 302  * invokes the appropriate handler.
 303  *
 304  * Implicitly, we also define interrupt priority by
 305  * choosing which to dispatch first.
 306  */
 307 asmlinkage void ar5312_irq_dispatch(void)
 308 {
 309         int pending = read_c0_status() & read_c0_cause();
 310
 311         if (pending & CAUSEF_IP2)
 312                 do_IRQ(AR5312_IRQ_WLAN0_INTRS);
 313         else if (pending & CAUSEF_IP3)
 314                 do_IRQ(AR5312_IRQ_ENET0_INTRS);
 315         else if (pending & CAUSEF_IP4)
 316                 do_IRQ(AR5312_IRQ_ENET1_INTRS);
 317         else if (pending & CAUSEF_IP5)
 318                 do_IRQ(AR5312_IRQ_WLAN1_INTRS);
 319         else if (pending & CAUSEF_IP6) {
 320                 unsigned int ar531x_misc_intrs = sysRegRead(AR531X_ISR) & sysRegRead(AR531X_IMR);
 321
 322                 if (ar531x_misc_intrs & AR531X_ISR_TIMER) {
 323                         do_IRQ(AR531X_MISC_IRQ_TIMER);
 324                         (void)sysRegRead(AR531X_TIMER);
 325                 } else if (ar531x_misc_intrs & AR531X_ISR_AHBPROC)
 326                         do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
 327                 else if ((ar531x_misc_intrs & AR531X_ISR_UART0))
 328                         do_IRQ(AR531X_MISC_IRQ_UART0);
 329                 else if (ar531x_misc_intrs & AR531X_ISR_WD)
 330                         do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
 331                 else
 332                         do_IRQ(AR531X_MISC_IRQ_NONE);
 333         } else if (pending & CAUSEF_IP7) {
 334                 do_IRQ(AR531X_IRQ_CPU_CLOCK);
 335         }
 336         else
 337                 do_IRQ(AR531X_IRQ_NONE);
 338 }
 339
 340 static void ar5312_halt(void)
 341 {
 342          while (1);
 343 }
 344
 345 static void ar5312_power_off(void)
 346 {
 347          ar5312_halt();
 348 }
 349
 350
 351 static void ar5312_restart(char *command)
 352 {
 353         /* reset the system */
 354         for(;;) sysRegWrite(AR531X_RESET, AR531X_RESET_SYSTEM);
 355 }
 356
 357
 358 /*
 359  * This table is indexed by bits 5..4 of the CLOCKCTL1 register
 360  * to determine the predevisor value.
 361  */
 362 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
 363         1,
 364         2,
 365         4,
 366         5
 367 };
 368
 369
 370 static unsigned int __init ar5312_cpu_frequency(void)
 371 {
 372         unsigned int result;
 373         unsigned int predivide_mask, predivide_shift;
 374         unsigned int multiplier_mask, multiplier_shift;
 375         unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
 376         unsigned int doubler_mask;
 377         unsigned int wisoc_revision;
 378
 379         /* Trust the bootrom's idea of cpu frequency. */
 380         if ((result = sysRegRead(AR5312_SCRATCH)))
 381                 return result;
 382
 383         wisoc_revision = (sysRegRead(AR531X_REV) & AR531X_REV_MAJ) >> AR531X_REV_MAJ_S;
 384         if (wisoc_revision == AR531X_REV_MAJ_AR2313) {
 385                 predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
 386                 predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
 387                 multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
 388                 multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
 389                 doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
 390         } else { /* AR5312 and AR2312 */
 391                 predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
 392                 predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
 393                 multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
 394                 multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
 395                 doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
 396         }
 397
 398         /*
 399          * Clocking is derived from a fixed 40MHz input clock.
 400          *
 401          *  cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
 402          *  sysFreq = cpuFreq / 4          (used for APB clock, serial,
 403          *                                                         flash, Timer, Watchdog Timer)
 404          *
 405          *  cntFreq = cpuFreq / 2          (use for CPU count/compare)
 406          *
 407          * So, for example, with a PLL multiplier of 5, we have
 408          *
 409          *  cpuFreq = 200MHz
 410          *  sysFreq = 50MHz
 411          *  cntFreq = 100MHz
 412          *
 413          * We compute the CPU frequency, based on PLL settings.
 414          */
 415
 416         clockCtl1 = sysRegRead(AR5312_CLOCKCTL1);
 417         preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
 418         preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
 419         multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
 420
 421         if (clockCtl1 & doubler_mask) {
 422                 multiplier = multiplier << 1;
 423         }
 424         return (40000000 / preDivisor) * multiplier;
 425 }
 426
 427 static inline int ar5312_sys_frequency(void)
 428 {
 429         return ar5312_cpu_frequency() / 4;
 430 }
 431
 432 static void __init ar5312_time_init(void)
 433 {
 434         mips_hpt_frequency = ar5312_cpu_frequency() / 2;
 435 }
 436
 437
 438 /* Enable the specified AR531X_MISC_IRQ interrupt */
 439 static void
 440 ar5312_misc_intr_enable(unsigned int irq)
 441 {
 442         unsigned int imr;
 443
 444         imr = sysRegRead(AR531X_IMR);
 445         imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
 446         sysRegWrite(AR531X_IMR, imr);
 447         sysRegRead(AR531X_IMR); /* flush write buffer */
 448 }
 449
 450 /* Disable the specified AR531X_MISC_IRQ interrupt */
 451 static void
 452 ar5312_misc_intr_disable(unsigned int irq)
 453 {
 454         unsigned int imr;
 455
 456         imr = sysRegRead(AR531X_IMR);
 457         imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
 458         sysRegWrite(AR531X_IMR, imr);
 459         sysRegRead(AR531X_IMR); /* flush write buffer */
 460 }
 461
 462 /* Turn on the specified AR531X_MISC_IRQ interrupt */
 463 static unsigned int
 464 ar5312_misc_intr_startup(unsigned int irq)
 465 {
 466         ar5312_misc_intr_enable(irq);
 467         return 0;
 468 }
 469
 470 /* Turn off the specified AR531X_MISC_IRQ interrupt */
 471 static void
 472 ar5312_misc_intr_shutdown(unsigned int irq)
 473 {
 474         ar5312_misc_intr_disable(irq);
 475 }
 476
 477 static void
 478 ar5312_misc_intr_ack(unsigned int irq)
 479 {
 480         ar5312_misc_intr_disable(irq);
 481 }
 482
 483 static void
 484 ar5312_misc_intr_end(unsigned int irq)
 485 {
 486         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 487                 ar5312_misc_intr_enable(irq);
 488 }
 489
 490 static struct irq_chip ar5312_misc_intr_controller = {
 491         .typename       = "AR5312 misc",
 492         .startup        = ar5312_misc_intr_startup,
 493         .shutdown       = ar5312_misc_intr_shutdown,
 494         .enable         = ar5312_misc_intr_enable,
 495         .disable        = ar5312_misc_intr_disable,
 496         .ack            = ar5312_misc_intr_ack,
 497         .end            = ar5312_misc_intr_end,
 498 };
 499
 500 static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
 501 {
 502         u32 proc1 = sysRegRead(AR531X_PROC1);
 503         u32 procAddr = sysRegRead(AR531X_PROCADDR); /* clears error state */
 504         u32 dma1 = sysRegRead(AR531X_DMA1);
 505         u32 dmaAddr = sysRegRead(AR531X_DMAADDR);   /* clears error state */
 506
 507         printk("AHB interrupt: PROCADDR=0x%8.8x  PROC1=0x%8.8x  DMAADDR=0x%8.8x  DMA1=0x%8.8x\n",
 508                         procAddr, proc1, dmaAddr, dma1);
 509
 510         machine_restart("AHB error"); /* Catastrophic failure */
 511         return IRQ_HANDLED;
 512 }
 513
 514
 515 static struct irqaction ar5312_ahb_proc_interrupt  = {
 516         .handler        = ar5312_ahb_proc_handler,
 517         .flags          = SA_INTERRUPT,
 518         .name           = "ar5312_ahb_proc_interrupt",
 519 };
 520
 521
 522 static struct irqaction cascade  = {
 523         .handler        = no_action,
 524         .flags          = SA_INTERRUPT,
 525         .name           = "cascade",
 526 };
 527
 528 void __init ar5312_misc_intr_init(int irq_base)
 529 {
 530         int i;
 531
 532         for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
 533                 irq_desc[i].status = IRQ_DISABLED;
 534                 irq_desc[i].action = NULL;
 535                 irq_desc[i].depth = 1;
 536                 irq_desc[i].chip = &ar5312_misc_intr_controller;
 537         }
 538         setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
 539         setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
 540 }
 541
 542 void __init ar5312_prom_init(void)
 543 {
 544         u32 memsize, memcfg, bank0AC, bank1AC;
 545
 546         is_5312 = 1;
 547
 548         /* Detect memory size */
 549         memcfg = sysRegRead(AR531X_MEM_CFG1);
 550         bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
 551         bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
 552         memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
 553                 + (bank1AC ? (1 << (bank1AC+1)) : 0);
 554         memsize <<= 20;
 555         add_memory_region(0, memsize, BOOT_MEM_RAM);
 556
 557         /* Initialize it to AR5312 for now. Real detection will be done
 558          * in ar5312_init_devices() */
 559         mips_machtype = MACH_ATHEROS_AR5312;
 560 }
 561
 562 void __init ar5312_plat_setup(void)
 563 {
 564         /* Clear any lingering AHB errors */
 565         sysRegRead(AR531X_PROCADDR);
 566         sysRegRead(AR531X_DMAADDR);
 567         sysRegWrite(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
 568
 569         board_time_init = ar5312_time_init;
 570
 571         _machine_restart = ar5312_restart;
 572         _machine_halt = ar5312_halt;
 573         pm_power_off = ar5312_power_off;
 574
 575         serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
 576 }
 577
 578 arch_initcall(ar5312_init_devices);