target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
   7  * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
   8  * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
   9  */
  10
  11 #ifndef AR5312_H
  12 #define AR5312_H
  13
  14 #include <asm/addrspace.h>
  15
  16 /* Address Map */
  17 #define AR531X_WLAN0            0x18000000
  18 #define AR531X_WLAN1            0x18500000
  19 #define AR531X_ENET0            0x18100000
  20 #define AR531X_ENET1            0x18200000
  21 #define AR531X_SDRAMCTL         0x18300000
  22 #define AR531X_FLASHCTL         0x18400000
  23 #define AR531X_APBBASE          0x1c000000
  24 #define AR531X_FLASH            0x1e000000
  25 #define AR531X_UART0            0xbc000003      /* UART MMR */
  26
  27 /*
  28  * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
  29  * should be considered available.  The AR5312 supports 2 enet MACS,
  30  * even though many reference boards only actually use 1 of them
  31  * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
  32  * The AR2312 supports 1 enet MAC.
  33  */
  34 #define AR531X_NUM_ENET_MAC             2
  35
  36 /*
  37  * Need these defines to determine true number of ethernet MACs
  38  */
  39 #define AR5212_AR5312_REV2      0x0052          /* AR5312 WMAC (AP31) */
  40 #define AR5212_AR5312_REV7      0x0057          /* AR5312 WMAC (AP30-040) */
  41 #define AR5212_AR2313_REV8      0x0058          /* AR2313 WMAC (AP43-030) */
  42 #define AR531X_RADIO_MASK_OFF  0xc8
  43 #define AR531X_RADIO0_MASK     0x0003
  44 #define AR531X_RADIO1_MASK     0x000c
  45 #define AR531X_RADIO1_S        2
  46
  47 /*
  48  * AR531X_NUM_WMAC defines the number of Wireless MACs that\
  49  * should be considered available.
  50  */
  51 #define AR531X_NUM_WMAC                 2
  52
  53 /* Reset/Timer Block Address Map */
  54 #define AR531X_RESETTMR         (AR531X_APBBASE  + 0x3000)
  55 #define AR531X_TIMER            (AR531X_RESETTMR + 0x0000) /* countdown timer */
  56 #define AR531X_WD_CTRL          (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
  57 #define AR531X_WD_TIMER         (AR531X_RESETTMR + 0x000c) /* watchdog timer */
  58 #define AR531X_ISR              (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
  59 #define AR531X_IMR              (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
  60 #define AR531X_RESET            (AR531X_RESETTMR + 0x0020)
  61 #define AR5312_CLOCKCTL1        (AR531X_RESETTMR + 0x0064)
  62 #define AR5312_SCRATCH          (AR531X_RESETTMR + 0x006c)
  63 #define AR531X_PROCADDR         (AR531X_RESETTMR + 0x0070)
  64 #define AR531X_PROC1            (AR531X_RESETTMR + 0x0074)
  65 #define AR531X_DMAADDR          (AR531X_RESETTMR + 0x0078)
  66 #define AR531X_DMA1             (AR531X_RESETTMR + 0x007c)
  67 #define AR531X_ENABLE           (AR531X_RESETTMR + 0x0080) /* interface enb */
  68 #define AR531X_REV              (AR531X_RESETTMR + 0x0090) /* revision */
  69
  70 /* AR531X_WD_CTRL register bit field definitions */
  71 #define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
  72 #define AR531X_WD_CTRL_NMI               0x0001
  73 #define AR531X_WD_CTRL_RESET             0x0002
  74
  75 /* AR531X_ISR register bit field definitions */
  76 #define AR531X_ISR_NONE         0x0000
  77 #define AR531X_ISR_TIMER        0x0001
  78 #define AR531X_ISR_AHBPROC      0x0002
  79 #define AR531X_ISR_AHBDMA       0x0004
  80 #define AR531X_ISR_GPIO         0x0008
  81 #define AR531X_ISR_UART0        0x0010
  82 #define AR531X_ISR_UART0DMA     0x0020
  83 #define AR531X_ISR_WD           0x0040
  84 #define AR531X_ISR_LOCAL        0x0080
  85
  86 /* AR531X_RESET register bit field definitions */
  87 #define AR531X_RESET_SYSTEM     0x00000001  /* cold reset full system */
  88 #define AR531X_RESET_PROC       0x00000002  /* cold reset MIPS core */
  89 #define AR531X_RESET_WLAN0      0x00000004  /* cold reset WLAN MAC and BB */
  90 #define AR531X_RESET_EPHY0      0x00000008  /* cold reset ENET0 phy */
  91 #define AR531X_RESET_EPHY1      0x00000010  /* cold reset ENET1 phy */
  92 #define AR531X_RESET_ENET0      0x00000020  /* cold reset ENET0 mac */
  93 #define AR531X_RESET_ENET1      0x00000040  /* cold reset ENET1 mac */
  94 #define AR531X_RESET_UART0      0x00000100  /* cold reset UART0 (high speed) */
  95 #define AR531X_RESET_WLAN1      0x00000200  /* cold reset WLAN MAC/BB */
  96 #define AR531X_RESET_APB        0x00000400  /* cold reset APB (ar5312) */
  97 #define AR531X_RESET_WARM_PROC  0x00001000  /* warm reset MIPS core */
  98 #define AR531X_RESET_WARM_WLAN0_MAC 0x00002000  /* warm reset WLAN0 MAC */
  99 #define AR531X_RESET_WARM_WLAN0_BB  0x00004000  /* warm reset WLAN0 BaseBand */
 100 #define AR531X_RESET_NMI        0x00010000  /* send an NMI to the processor */
 101 #define AR531X_RESET_WARM_WLAN1_MAC 0x00020000  /* warm reset WLAN1 mac */
 102 #define AR531X_RESET_WARM_WLAN1_BB  0x00040000  /* warm reset WLAN1 baseband */
 103 #define AR531X_RESET_LOCAL_BUS  0x00080000  /* reset local bus */
 104 #define AR531X_RESET_WDOG       0x00100000  /* last reset was a watchdog */
 105
 106 #define AR531X_RESET_WMAC0_BITS \
 107         AR531X_RESET_WLAN0 |\
 108         AR531X_RESET_WARM_WLAN0_MAC |\
 109         AR531X_RESET_WARM_WLAN0_BB
 110
 111 #define AR531X_RESERT_WMAC1_BITS \
 112         AR531X_RESET_WLAN1 |\
 113         AR531X_RESET_WARM_WLAN1_MAC |\
 114         AR531X_RESET_WARM_WLAN1_BB
 115
 116 /* AR5312_CLOCKCTL1 register bit field definitions */
 117 #define AR5312_CLOCKCTL1_PREDIVIDE_MASK    0x00000030
 118 #define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT            4
 119 #define AR5312_CLOCKCTL1_MULTIPLIER_MASK   0x00001f00
 120 #define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT           8
 121 #define AR5312_CLOCKCTL1_DOUBLER_MASK      0x00010000
 122
 123 /* Valid for AR5312 and AR2312 */
 124 #define AR5312_CLOCKCTL1_PREDIVIDE_MASK    0x00000030
 125 #define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT            4
 126 #define AR5312_CLOCKCTL1_MULTIPLIER_MASK   0x00001f00
 127 #define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT           8
 128 #define AR5312_CLOCKCTL1_DOUBLER_MASK      0x00010000
 129
 130 /* Valid for AR2313 */
 131 #define AR2313_CLOCKCTL1_PREDIVIDE_MASK    0x00003000
 132 #define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT           12
 133 #define AR2313_CLOCKCTL1_MULTIPLIER_MASK   0x001f0000
 134 #define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT          16
 135 #define AR2313_CLOCKCTL1_DOUBLER_MASK      0x00000000
 136
 137
 138 /* AR531X_ENABLE register bit field definitions */
 139 #define AR531X_ENABLE_WLAN0              0x0001
 140 #define AR531X_ENABLE_ENET0              0x0002
 141 #define AR531X_ENABLE_ENET1              0x0004
 142 #define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008   /* UART, and WLAN1 PIOs */
 143 #define AR531X_ENABLE_WLAN1_DMA          0x0010   /* WLAN1 DMAs */
 144 #define AR531X_ENABLE_WLAN1 \
 145             (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA)
 146
 147 /* AR531X_REV register bit field definitions */
 148 #define AR531X_REV_WMAC_MAJ    0xf000
 149 #define AR531X_REV_WMAC_MAJ_S  12
 150 #define AR531X_REV_WMAC_MIN    0x0f00
 151 #define AR531X_REV_WMAC_MIN_S  8
 152 #define AR531X_REV_MAJ         0x00f0
 153 #define AR531X_REV_MAJ_S       4
 154 #define AR531X_REV_MIN         0x000f
 155 #define AR531X_REV_MIN_S       0
 156 #define AR531X_REV_CHIP        (REV_MAJ|REV_MIN)
 157
 158 /* Major revision numbers, bits 7..4 of Revision ID register */
 159 #define AR531X_REV_MAJ_AR5312          0x4
 160 #define AR531X_REV_MAJ_AR2313          0x5
 161
 162 /* Minor revision numbers, bits 3..0 of Revision ID register */
 163 #define AR5312_REV_MIN_DUAL     0x0     /* Dual WLAN version */
 164 #define AR5312_REV_MIN_SINGLE   0x1     /* Single WLAN version */
 165
 166 /* AR531X_FLASHCTL register bit field definitions */
 167 #define FLASHCTL_IDCY   0x0000000f      /* Idle cycle turn around time */
 168 #define FLASHCTL_IDCY_S 0
 169 #define FLASHCTL_WST1   0x000003e0      /* Wait state 1 */
 170 #define FLASHCTL_WST1_S 5
 171 #define FLASHCTL_RBLE   0x00000400      /* Read byte lane enable */
 172 #define FLASHCTL_WST2   0x0000f800      /* Wait state 2 */
 173 #define FLASHCTL_WST2_S 11
 174 #define FLASHCTL_AC     0x00070000      /* Flash address check (added) */
 175 #define FLASHCTL_AC_S   16
 176 #define FLASHCTL_AC_128K 0x00000000
 177 #define FLASHCTL_AC_256K 0x00010000
 178 #define FLASHCTL_AC_512K 0x00020000
 179 #define FLASHCTL_AC_1M   0x00030000
 180 #define FLASHCTL_AC_2M   0x00040000
 181 #define FLASHCTL_AC_4M   0x00050000
 182 #define FLASHCTL_AC_8M   0x00060000
 183 #define FLASHCTL_AC_RES  0x00070000     /* 16MB is not supported */
 184 #define FLASHCTL_E      0x00080000      /* Flash bank enable (added) */
 185 #define FLASHCTL_BUSERR 0x01000000      /* Bus transfer error status flag */
 186 #define FLASHCTL_WPERR  0x02000000      /* Write protect error status flag */
 187 #define FLASHCTL_WP     0x04000000      /* Write protect */
 188 #define FLASHCTL_BM     0x08000000      /* Burst mode */
 189 #define FLASHCTL_MW     0x30000000      /* Memory width */
 190 #define FLASHCTL_MWx8   0x00000000      /* Memory width x8 */
 191 #define FLASHCTL_MWx16  0x10000000      /* Memory width x16 */
 192 #define FLASHCTL_MWx32  0x20000000      /* Memory width x32 (not supported) */
 193 #define FLASHCTL_ATNR   0x00000000      /* Access type == no retry */
 194 #define FLASHCTL_ATR    0x80000000      /* Access type == retry every */
 195 #define FLASHCTL_ATR4   0xc0000000      /* Access type == retry every 4 */
 196
 197 /* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices.  */
 198 #define AR531X_FLASHCTL0        (AR531X_FLASHCTL + 0x00)
 199 #define AR531X_FLASHCTL1        (AR531X_FLASHCTL + 0x04)
 200 #define AR531X_FLASHCTL2        (AR531X_FLASHCTL + 0x08)
 201
 202 /* ARM SDRAM Controller -- just enough to determine memory size */
 203 #define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
 204 #define MEM_CFG1_AC0    0x00000700      /* bank 0: SDRAM addr check (added) */
 205 #define MEM_CFG1_AC0_S  8
 206 #define MEM_CFG1_AC1    0x00007000      /* bank 1: SDRAM addr check (added) */
 207 #define MEM_CFG1_AC1_S  12
 208
 209 /* GPIO Address Map */
 210 #define AR531X_GPIO         (AR531X_APBBASE  + 0x2000)
 211 #define AR531X_GPIO_DO      (AR531X_GPIO + 0x00)        /* output register */
 212 #define AR531X_GPIO_DI      (AR531X_GPIO + 0x04)        /* intput register */
 213 #define AR531X_GPIO_CR      (AR531X_GPIO + 0x08)        /* control register */
 214
 215 /* GPIO Control Register bit field definitions */
 216 #define AR531X_GPIO_CR_M(x)    (1 << (x))                      /* mask for i/o */
 217 #define AR531X_GPIO_CR_O(x)    (0 << (x))                      /* mask for output */
 218 #define AR531X_GPIO_CR_I(x)    (1 << (x))                      /* mask for input */
 219 #define AR531X_GPIO_CR_INT(x)  (1 << ((x)+8))                  /* mask for interrupt */
 220 #define AR531X_GPIO_CR_UART(x) (1 << ((x)+16))                 /* uart multiplex */
 221
 222 #endif
 223