target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
   7  * Copyright (C) 2006 FON Technology, SL.
   8  * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
   9  * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  10  */
  11
  12 /*
  13  * Platform devices for Atheros SoCs
  14  */
  15
  16 #include <linux/autoconf.h>
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/types.h>
  20 #include <linux/string.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/kernel.h>
  23 #include <linux/reboot.h>
  24 #include <asm/bootinfo.h>
  25 #include <asm/reboot.h>
  26 #include <asm/time.h>
  27 #include <asm/irq.h>
  28 #include <asm/io.h>
  29 #include "ar531x.h"
  30
  31 #define AR531X_IRQ_MISC_INTRS   MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
  32 #define AR531X_IRQ_WLAN0_INTRS  MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
  33 #define AR531X_IRQ_ENET0_INTRS  MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
  34 #define AR531X_IRQ_LCBUS_PCI    MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
  35 #define AR531X_IRQ_WLAN0_POLL   MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
  36
  37 static struct resource ar5315_eth_res[] = {
  38         {
  39                 .name = "eth_membase",
  40                 .flags = IORESOURCE_MEM,
  41                 .start = AR5315_ENET0,
  42                 .end = AR5315_ENET0 + 0x2000,
  43         },
  44         {
  45                 .name = "eth_irq",
  46                 .flags = IORESOURCE_IRQ,
  47                 .start = AR531X_IRQ_ENET0_INTRS,
  48                 .end = AR531X_IRQ_ENET0_INTRS,
  49         },
  50 };
  51
  52 static struct ar531x_eth ar5315_eth_data = {
  53         .phy = 1,
  54         .mac = 0,
  55         .reset_base = AR5315_RESET,
  56         .reset_mac = AR5315_RESET_ENET0,
  57         .reset_phy = AR5315_RESET_EPHY0,
  58 };
  59
  60 static struct platform_device ar5315_eth = {
  61         .id = 0,
  62         .name = "ar531x-eth",
  63         .dev.platform_data = &ar5315_eth_data,
  64         .resource = ar5315_eth_res,
  65         .num_resources = ARRAY_SIZE(ar5315_eth_res)
  66 };
  67
  68 static struct platform_device ar5315_wmac = {
  69         .id = 0,
  70         .name = "ar531x-wmac",
  71         /* FIXME: add resources */
  72 };
  73
  74 static struct resource ar5315_spiflash_res[] = {
  75         {
  76                 .name = "flash_base",
  77                 .flags = IORESOURCE_MEM,
  78                 .start = KSEG1ADDR(AR5315_SPI_READ),
  79                 .end = KSEG1ADDR(AR5315_SPI_READ) + 0x800000,
  80         },
  81         {
  82                 .name = "flash_regs",
  83                 .flags = IORESOURCE_MEM,
  84                 .start = 0x11300000,
  85                 .end = 0x11300012,
  86         },
  87 };
  88
  89 static struct platform_device ar5315_spiflash = {
  90         .id = 0,
  91         .name = "spiflash",
  92         .resource = ar5315_spiflash_res,
  93         .num_resources = ARRAY_SIZE(ar5315_spiflash_res)
  94 };
  95
  96 static __initdata struct platform_device *ar5315_devs[4];
  97
  98
  99
 100 static void *flash_regs;
 101
 102 static inline __u32 spiflash_regread32(int reg)
 103 {
 104         volatile __u32 *data = (__u32 *)(flash_regs + reg);
 105
 106         return (*data);
 107 }
 108
 109 static inline void spiflash_regwrite32(int reg, __u32 data)
 110 {
 111         volatile __u32 *addr = (__u32 *)(flash_regs + reg);
 112
 113         *addr = data;
 114 }
 115
 116 #define SPI_FLASH_CTL      0x00
 117 #define SPI_FLASH_OPCODE   0x04
 118 #define SPI_FLASH_DATA     0x08
 119
 120 static __u8 spiflash_probe(void)
 121 {
 122          __u32 reg;
 123
 124         do {
 125                 reg = spiflash_regread32(SPI_FLASH_CTL);
 126         } while (reg & SPI_CTL_BUSY);
 127
 128         spiflash_regwrite32(SPI_FLASH_OPCODE, 0xab);
 129
 130         reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | 4 |
 131                 (1 << 4) | SPI_CTL_START;
 132
 133         spiflash_regwrite32(SPI_FLASH_CTL, reg);
 134
 135         do {
 136                 reg = spiflash_regread32(SPI_FLASH_CTL);
 137         } while (reg & SPI_CTL_BUSY);
 138
 139         reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
 140         reg &= 0xff;
 141
 142         return (u8) reg;
 143 }
 144
 145
 146 #define STM_8MBIT_SIGNATURE     0x13
 147 #define STM_16MBIT_SIGNATURE    0x14
 148 #define STM_32MBIT_SIGNATURE    0x15
 149 #define STM_64MBIT_SIGNATURE    0x16
 150
 151
 152 static char __init *ar5315_flash_limit(void)
 153 {
 154         u8 sig;
 155         u32 flash_size = 0;
 156
 157         /* probe the flash chip size */
 158         flash_regs = ioremap_nocache(ar5315_spiflash_res[1].start, ar5315_spiflash_res[1].end - ar5315_spiflash_res[1].start);
 159         sig = spiflash_probe();
 160         iounmap(flash_regs);
 161
 162         switch(sig) {
 163                 case STM_8MBIT_SIGNATURE:
 164                         flash_size = 0x00100000;
 165                         break;
 166                 case STM_16MBIT_SIGNATURE:
 167                         flash_size = 0x00200000;
 168                         break;
 169                 case STM_32MBIT_SIGNATURE:
 170                         flash_size = 0x00400000;
 171                         break;
 172                 case STM_64MBIT_SIGNATURE:
 173                         flash_size = 0x00800000;
 174                         break;
 175         }
 176
 177         ar5315_spiflash_res[0].end = ar5315_spiflash_res[0].start + flash_size;
 178         return (char *) ar5315_spiflash_res[0].end;
 179 }
 180
 181 int __init ar5315_init_devices(void)
 182 {
 183         struct ar531x_config *config;
 184         int dev = 0;
 185
 186         if (mips_machtype != MACH_ATHEROS_AR5315)
 187                 return 0;
 188
 189         ar531x_find_config(ar5315_flash_limit());
 190
 191         config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
 192         config->board = board_config;
 193         config->radio = radio_config;
 194         config->unit = 0;
 195         config->tag = (u_int16_t) (sysRegRead(AR5315_SREV) & REV_CHIP);
 196
 197         ar5315_eth_data.board_config = board_config;
 198         ar5315_wmac.dev.platform_data = config;
 199
 200         ar5315_devs[dev++] = &ar5315_eth;
 201         ar5315_devs[dev++] = &ar5315_wmac;
 202         ar5315_devs[dev++] = &ar5315_spiflash;
 203
 204         return platform_add_devices(ar5315_devs, dev);
 205 }
 206
 207
 208 /*
 209  * Called when an interrupt is received, this function
 210  * determines exactly which interrupt it was, and it
 211  * invokes the appropriate handler.
 212  *
 213  * Implicitly, we also define interrupt priority by
 214  * choosing which to dispatch first.
 215  */
 216 asmlinkage void ar5315_irq_dispatch(void)
 217 {
 218         int pending = read_c0_status() & read_c0_cause();
 219
 220         if (pending & CAUSEF_IP3)
 221                 do_IRQ(AR531X_IRQ_WLAN0_INTRS);
 222         else if (pending & CAUSEF_IP4)
 223                 do_IRQ(AR531X_IRQ_ENET0_INTRS);
 224         else if (pending & CAUSEF_IP2) {
 225                 unsigned int ar531x_misc_intrs = sysRegRead(AR5315_ISR) & sysRegRead(AR5315_IMR);
 226
 227             if (ar531x_misc_intrs & AR5315_ISR_TIMER)
 228                         do_IRQ(AR531X_MISC_IRQ_TIMER);
 229                 else if (ar531x_misc_intrs & AR5315_ISR_AHB)
 230                         do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
 231                 else if (ar531x_misc_intrs & AR5315_ISR_GPIO) {
 232                         sysRegWrite(AR5315_ISR, sysRegRead(AR5315_IMR) | ~AR5315_ISR_GPIO);
 233                 } else if (ar531x_misc_intrs & AR5315_ISR_UART0)
 234                         do_IRQ(AR531X_MISC_IRQ_UART0);
 235                 else if (ar531x_misc_intrs & AR5315_ISR_WD)
 236                         do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
 237                 else
 238                         do_IRQ(AR531X_MISC_IRQ_NONE);
 239         } else if (pending & CAUSEF_IP7)
 240                 do_IRQ(AR531X_IRQ_CPU_CLOCK);
 241         else
 242                 do_IRQ(AR531X_IRQ_NONE);
 243 }
 244
 245 static void ar5315_halt(void)
 246 {
 247          while (1);
 248 }
 249
 250 static void ar5315_power_off(void)
 251 {
 252          ar5315_halt();
 253 }
 254
 255
 256 static void ar5315_restart(char *command)
 257 {
 258         unsigned int reg;
 259         for(;;) {
 260
 261                 /* reset the system */
 262                 sysRegWrite(AR5315_COLD_RESET,AR5317_RESET_SYSTEM);
 263
 264                 /*
 265                  * Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
 266                  */
 267
 268                 reg = sysRegRead(AR5315_GPIO_DO);
 269                 reg &= ~(1 << AR5315_RESET_GPIO);
 270                 sysRegWrite(AR5315_GPIO_DO, reg);
 271                 (void)sysRegRead(AR5315_GPIO_DO); /* flush write to hardware */
 272         }
 273 }
 274
 275
 276 /*
 277  * This table is indexed by bits 5..4 of the CLOCKCTL1 register
 278  * to determine the predevisor value.
 279  */
 280 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
 281     1,
 282     2,
 283     4,
 284     5
 285 };
 286
 287 static int __initdata PLLC_DIVIDE_TABLE[5] = {
 288     2,
 289     3,
 290     4,
 291     6,
 292     3
 293 };
 294
 295 static unsigned int __init
 296 ar5315_sys_clk(unsigned int clockCtl)
 297 {
 298     unsigned int pllcCtrl,cpuDiv;
 299     unsigned int pllcOut,refdiv,fdiv,divby2;
 300         unsigned int clkDiv;
 301
 302     pllcCtrl = sysRegRead(AR5315_PLLC_CTL);
 303     refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
 304     refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
 305     fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
 306     divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
 307     divby2 += 1;
 308     pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
 309
 310
 311     /* clkm input selected */
 312         switch(clockCtl & CPUCLK_CLK_SEL_M) {
 313                 case 0:
 314                 case 1:
 315                         clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
 316                         break;
 317                 case 2:
 318                         clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
 319                         break;
 320                 default:
 321                         pllcOut = 40000000;
 322                         clkDiv = 1;
 323                         break;
 324         }
 325         cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
 326         cpuDiv = cpuDiv * 2 ?: 1;
 327         return (pllcOut/(clkDiv * cpuDiv));
 328 }
 329
 330 static inline unsigned int ar5315_cpu_frequency(void)
 331 {
 332     return ar5315_sys_clk(sysRegRead(AR5315_CPUCLK));
 333 }
 334
 335 static inline unsigned int ar5315_apb_frequency(void)
 336 {
 337     return ar5315_sys_clk(sysRegRead(AR5315_AMBACLK));
 338 }
 339
 340 static void __init ar5315_time_init(void)
 341 {
 342         mips_hpt_frequency = ar5315_cpu_frequency() / 2;
 343 }
 344
 345
 346
 347 /* Enable the specified AR531X_MISC_IRQ interrupt */
 348 static void
 349 ar5315_misc_intr_enable(unsigned int irq)
 350 {
 351         unsigned int imr;
 352
 353         imr = sysRegRead(AR5315_IMR);
 354         switch(irq)
 355         {
 356            case AR531X_MISC_IRQ_TIMER:
 357              imr |= AR5315_ISR_TIMER;
 358              break;
 359
 360            case AR531X_MISC_IRQ_AHB_PROC:
 361              imr |= AR5315_ISR_AHB;
 362              break;
 363
 364            case AR531X_MISC_IRQ_AHB_DMA:
 365              imr |= 0/* ?? */;
 366              break;
 367
 368            case AR531X_MISC_IRQ_GPIO:
 369              imr |= AR5315_ISR_GPIO;
 370              break;
 371
 372            case AR531X_MISC_IRQ_UART0:
 373              imr |= AR5315_ISR_UART0;
 374              break;
 375
 376
 377            case AR531X_MISC_IRQ_WATCHDOG:
 378              imr |= AR5315_ISR_WD;
 379              break;
 380
 381            case AR531X_MISC_IRQ_LOCAL:
 382              imr |= 0/* ?? */;
 383              break;
 384
 385         }
 386         sysRegWrite(AR5315_IMR, imr);
 387         imr=sysRegRead(AR5315_IMR); /* flush write buffer */
 388         //printk("enable Interrupt irq 0x%x imr 0x%x \n",irq,imr);
 389
 390 }
 391
 392 /* Disable the specified AR531X_MISC_IRQ interrupt */
 393 static void
 394 ar5315_misc_intr_disable(unsigned int irq)
 395 {
 396         unsigned int imr;
 397
 398         imr = sysRegRead(AR5315_IMR);
 399         switch(irq)
 400         {
 401            case AR531X_MISC_IRQ_TIMER:
 402              imr &= (~AR5315_ISR_TIMER);
 403              break;
 404
 405            case AR531X_MISC_IRQ_AHB_PROC:
 406              imr &= (~AR5315_ISR_AHB);
 407              break;
 408
 409            case AR531X_MISC_IRQ_AHB_DMA:
 410              imr &= 0/* ?? */;
 411              break;
 412
 413            case AR531X_MISC_IRQ_GPIO:
 414              imr &= ~AR5315_ISR_GPIO;
 415              break;
 416
 417            case AR531X_MISC_IRQ_UART0:
 418              imr &= (~AR5315_ISR_UART0);
 419              break;
 420
 421            case AR531X_MISC_IRQ_WATCHDOG:
 422              imr &= (~AR5315_ISR_WD);
 423              break;
 424
 425            case AR531X_MISC_IRQ_LOCAL:
 426              imr &= ~0/* ?? */;
 427              break;
 428
 429         }
 430         sysRegWrite(AR5315_IMR, imr);
 431         sysRegRead(AR5315_IMR); /* flush write buffer */
 432 }
 433
 434 /* Turn on the specified AR531X_MISC_IRQ interrupt */
 435 static unsigned int
 436 ar5315_misc_intr_startup(unsigned int irq)
 437 {
 438         ar5315_misc_intr_enable(irq);
 439         return 0;
 440 }
 441
 442 /* Turn off the specified AR531X_MISC_IRQ interrupt */
 443 static void
 444 ar5315_misc_intr_shutdown(unsigned int irq)
 445 {
 446         ar5315_misc_intr_disable(irq);
 447 }
 448
 449 static void
 450 ar5315_misc_intr_ack(unsigned int irq)
 451 {
 452         ar5315_misc_intr_disable(irq);
 453 }
 454
 455 static void
 456 ar5315_misc_intr_end(unsigned int irq)
 457 {
 458         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 459                 ar5315_misc_intr_enable(irq);
 460 }
 461
 462 static struct irq_chip ar5315_misc_intr_controller = {
 463         .typename       = "AR5315 misc",
 464         .startup        = ar5315_misc_intr_startup,
 465         .shutdown       = ar5315_misc_intr_shutdown,
 466         .enable         = ar5315_misc_intr_enable,
 467         .disable        = ar5315_misc_intr_disable,
 468         .ack            = ar5315_misc_intr_ack,
 469         .end            = ar5315_misc_intr_end,
 470 };
 471
 472 static irqreturn_t ar5315_ahb_proc_handler(int cpl, void *dev_id)
 473 {
 474     sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
 475     sysRegRead(AR5315_AHB_ERR1);
 476
 477     printk("AHB fatal error\n");
 478     machine_restart("AHB error"); /* Catastrophic failure */
 479
 480     return IRQ_HANDLED;
 481 }
 482
 483 static struct irqaction ar5315_ahb_proc_interrupt  = {
 484         .handler        = ar5315_ahb_proc_handler,
 485         .flags          = SA_INTERRUPT,
 486         .name           = "ar5315_ahb_proc_interrupt",
 487 };
 488
 489
 490 static struct irqaction cascade  = {
 491         .handler        = no_action,
 492         .flags          = SA_INTERRUPT,
 493         .name           = "cascade",
 494 };
 495
 496 void ar5315_misc_intr_init(int irq_base)
 497 {
 498         int i;
 499
 500         for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
 501                 irq_desc[i].status = IRQ_DISABLED;
 502                 irq_desc[i].action = NULL;
 503                 irq_desc[i].depth = 1;
 504                 irq_desc[i].chip = &ar5315_misc_intr_controller;
 505         }
 506         setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5315_ahb_proc_interrupt);
 507         setup_irq(AR531X_IRQ_MISC_INTRS, &cascade);
 508 }
 509
 510 void __init ar5315_plat_setup(void)
 511 {
 512         unsigned int config = read_c0_config();
 513
 514         /* Clear any lingering AHB errors */
 515         write_c0_config(config & ~0x3);
 516         sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
 517         sysRegRead(AR5315_AHB_ERR1);
 518         sysRegWrite(AR5315_WDC, WDC_IGNORE_EXPIRATION);
 519
 520         board_time_init = ar5315_time_init;
 521
 522         _machine_restart = ar5315_restart;
 523         _machine_halt = ar5315_halt;
 524         pm_power_off = ar5315_power_off;
 525
 526         serial_setup(KSEG1ADDR(AR5315_UART0), ar5315_apb_frequency());
 527 }
 528
 529 arch_initcall(ar5315_init_devices);