target/linux/atheros-2.6/files/arch/mips/atheros/ar531x.h

   1 #ifndef __AR531X_H
   2 #define __AR531X_H
   3
   4 #include <ar531x_platform.h>
   5 #include "ar5312.h"
   6 #include "ar5315.h"
   7
   8 #define MIPS_CPU_IRQ_BASE               0x00
   9 #define AR531X_HIGH_PRIO                0x10
  10 #define AR531X_MISC_IRQ_BASE            0x20
  11 #define AR531X_GPIO_IRQ_BASE            0x30
  12
  13 /* Software's idea of interrupts handled by "CPU Interrupt Controller" */
  14 #define AR531X_IRQ_NONE         MIPS_CPU_IRQ_BASE+0
  15 #define AR531X_IRQ_CPU_CLOCK    MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
  16
  17 /* Miscellaneous interrupts, which share IP6 */
  18 #define AR531X_MISC_IRQ_NONE            AR531X_MISC_IRQ_BASE+0
  19 #define AR531X_MISC_IRQ_TIMER           AR531X_MISC_IRQ_BASE+1
  20 #define AR531X_MISC_IRQ_AHB_PROC        AR531X_MISC_IRQ_BASE+2
  21 #define AR531X_MISC_IRQ_AHB_DMA         AR531X_MISC_IRQ_BASE+3
  22 #define AR531X_MISC_IRQ_GPIO            AR531X_MISC_IRQ_BASE+4
  23 #define AR531X_MISC_IRQ_UART0           AR531X_MISC_IRQ_BASE+5
  24 #define AR531X_MISC_IRQ_UART0_DMA       AR531X_MISC_IRQ_BASE+6
  25 #define AR531X_MISC_IRQ_WATCHDOG        AR531X_MISC_IRQ_BASE+7
  26 #define AR531X_MISC_IRQ_LOCAL           AR531X_MISC_IRQ_BASE+8
  27 #define AR531X_MISC_IRQ_COUNT           9
  28
  29 /* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
  30 #define AR531X_GPIO_IRQ_NONE            AR531X_MISC_IRQ_BASE+0
  31 #define AR531X_GPIO_IRQ(n)              AR531X_MISC_IRQ_BASE+(n)+1
  32 #define AR531X_GPIO_IRQ_COUNT           22
  33
  34 #define sysRegRead(phys)        \
  35         (*(volatile u32 *)KSEG1ADDR(phys))
  36
  37 #define sysRegWrite(phys, val)  \
  38         ((*(volatile u32 *)KSEG1ADDR(phys)) = (val))
  39
  40 /*
  41  * This is board-specific data that is stored in a "fixed" location in flash.
  42  * It is shared across operating systems, so it should not be changed lightly.
  43  * The main reason we need it is in order to extract the ethernet MAC
  44  * address(es).
  45  */
  46 struct ar531x_boarddata {
  47     u32 magic;                       /* board data is valid */
  48 #define AR531X_BD_MAGIC 0x35333131   /* "5311", for all 531x platforms */
  49     u16 cksum;                       /* checksum (starting with BD_REV 2) */
  50     u16 rev;                         /* revision of this struct */
  51 #define BD_REV  4
  52     char   boardName[64];            /* Name of board */
  53     u16 major;                       /* Board major number */
  54     u16 minor;                       /* Board minor number */
  55     u32 config;                      /* Board configuration */
  56 #define BD_ENET0        0x00000001   /* ENET0 is stuffed */
  57 #define BD_ENET1        0x00000002   /* ENET1 is stuffed */
  58 #define BD_UART1        0x00000004   /* UART1 is stuffed */
  59 #define BD_UART0        0x00000008   /* UART0 is stuffed (dma) */
  60 #define BD_RSTFACTORY   0x00000010   /* Reset factory defaults stuffed */
  61 #define BD_SYSLED       0x00000020   /* System LED stuffed */
  62 #define BD_EXTUARTCLK   0x00000040   /* External UART clock */
  63 #define BD_CPUFREQ      0x00000080   /* cpu freq is valid in nvram */
  64 #define BD_SYSFREQ      0x00000100   /* sys freq is set in nvram */
  65 #define BD_WLAN0        0x00000200   /* Enable WLAN0 */
  66 #define BD_MEMCAP       0x00000400   /* CAP SDRAM @ memCap for testing */
  67 #define BD_DISWATCHDOG  0x00000800   /* disable system watchdog */
  68 #define BD_WLAN1        0x00001000   /* Enable WLAN1 (ar5212) */
  69 #define BD_ISCASPER     0x00002000   /* FLAG for AR2312 */
  70 #define BD_WLAN0_2G_EN  0x00004000   /* FLAG for radio0_2G */
  71 #define BD_WLAN0_5G_EN  0x00008000   /* FLAG for radio0_2G */
  72 #define BD_WLAN1_2G_EN  0x00020000   /* FLAG for radio0_2G */
  73 #define BD_WLAN1_5G_EN  0x00040000   /* FLAG for radio0_2G */
  74     u16 resetConfigGpio;             /* Reset factory GPIO pin */
  75     u16 sysLedGpio;                  /* System LED GPIO pin */
  76
  77     u32 cpuFreq;                     /* CPU core frequency in Hz */
  78     u32 sysFreq;                     /* System frequency in Hz */
  79     u32 cntFreq;                     /* Calculated C0_COUNT frequency */
  80
  81     u8  wlan0Mac[6];
  82     u8  enet0Mac[6];
  83     u8  enet1Mac[6];
  84
  85     u16 pciId;                       /* Pseudo PCIID for common code */
  86     u16 memCap;                      /* cap bank1 in MB */
  87
  88     /* version 3 */
  89     u8  wlan1Mac[6];                 /* (ar5212) */
  90 };
  91
  92
  93 extern char *board_config;
  94 extern char *radio_config;
  95 extern void serial_setup(unsigned long mapbase, unsigned int uartclk);
  96 extern int ar531x_find_config(char *flash_limit);
  97
  98 extern void ar5312_misc_intr_init(int irq_base);
  99 extern void ar5312_irq_dispatch(void);
 100 extern void ar5312_plat_setup(void);
 101
 102 extern void ar5315_misc_intr_init(int irq_base);
 103 extern asmlinkage void ar5315_irq_dispatch(void);
 104 extern void ar5315_plat_setup(void);
 105
 106 #endif