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[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-2.6.32 / 110-ar2313_ethernet.patch
1 Index: linux-2.6.32.7/drivers/net/Kconfig
2 ===================================================================
3 --- linux-2.6.32.7.orig/drivers/net/Kconfig 2010-02-03 16:57:31.714431054 +0100
4 +++ linux-2.6.32.7/drivers/net/Kconfig 2010-02-03 17:00:35.870429264 +0100
5 @@ -359,6 +359,12 @@
6 help
7 Select this if your platform comes with an external 93CX6 eeprom.
8
9 +config AR231X_ETHERNET
10 + tristate "AR231x Ethernet support"
11 + depends on ATHEROS_AR231X
12 + help
13 + Support for the AR231x/531x ethernet controller
14 +
15 config MACE
16 tristate "MACE (Power Mac ethernet) support"
17 depends on PPC_PMAC && PPC32
18 Index: linux-2.6.32.7/drivers/net/Makefile
19 ===================================================================
20 --- linux-2.6.32.7.orig/drivers/net/Makefile 2010-02-03 16:57:31.714431054 +0100
21 +++ linux-2.6.32.7/drivers/net/Makefile 2010-02-03 17:00:35.870429264 +0100
22 @@ -216,6 +216,7 @@
23 obj-$(CONFIG_KORINA) += korina.o
24 obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o
25 obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o
26 +obj-$(CONFIG_AR231X_ETHERNET) += ar231x.o
27 obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o
28 obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o
29 obj-$(CONFIG_DECLANCE) += declance.o
30 Index: linux-2.6.32.7/drivers/net/ar231x.c
31 ===================================================================
32 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
33 +++ linux-2.6.32.7/drivers/net/ar231x.c 2010-02-03 17:00:35.874430230 +0100
34 @@ -0,0 +1,1263 @@
35 +/*
36 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
37 + *
38 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
39 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
40 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
41 + *
42 + * Thanks to Atheros for providing hardware and documentation
43 + * enabling me to write this driver.
44 + *
45 + * This program is free software; you can redistribute it and/or modify
46 + * it under the terms of the GNU General Public License as published by
47 + * the Free Software Foundation; either version 2 of the License, or
48 + * (at your option) any later version.
49 + *
50 + * Additional credits:
51 + * This code is taken from John Taylor's Sibyte driver and then
52 + * modified for the AR2313.
53 + */
54 +
55 +#include <linux/module.h>
56 +#include <linux/version.h>
57 +#include <linux/types.h>
58 +#include <linux/errno.h>
59 +#include <linux/ioport.h>
60 +#include <linux/pci.h>
61 +#include <linux/netdevice.h>
62 +#include <linux/etherdevice.h>
63 +#include <linux/skbuff.h>
64 +#include <linux/init.h>
65 +#include <linux/delay.h>
66 +#include <linux/mm.h>
67 +#include <linux/highmem.h>
68 +#include <linux/sockios.h>
69 +#include <linux/pkt_sched.h>
70 +#include <linux/mii.h>
71 +#include <linux/phy.h>
72 +#include <linux/ethtool.h>
73 +#include <linux/ctype.h>
74 +#include <linux/platform_device.h>
75 +
76 +#include <net/sock.h>
77 +#include <net/ip.h>
78 +
79 +#include <asm/system.h>
80 +#include <asm/io.h>
81 +#include <asm/irq.h>
82 +#include <asm/byteorder.h>
83 +#include <asm/uaccess.h>
84 +#include <asm/bootinfo.h>
85 +
86 +#define AR2313_MTU 1692
87 +#define AR2313_PRIOS 1
88 +#define AR2313_QUEUES (2*AR2313_PRIOS)
89 +#define AR2313_DESCR_ENTRIES 64
90 +
91 +
92 +#ifndef min
93 +#define min(a,b) (((a)<(b))?(a):(b))
94 +#endif
95 +
96 +#ifndef SMP_CACHE_BYTES
97 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
98 +#endif
99 +
100 +#define AR2313_MBOX_SET_BIT 0x8
101 +
102 +#include "ar231x.h"
103 +
104 +/*
105 + * New interrupt handler strategy:
106 + *
107 + * An old interrupt handler worked using the traditional method of
108 + * replacing an skbuff with a new one when a packet arrives. However
109 + * the rx rings do not need to contain a static number of buffer
110 + * descriptors, thus it makes sense to move the memory allocation out
111 + * of the main interrupt handler and do it in a bottom half handler
112 + * and only allocate new buffers when the number of buffers in the
113 + * ring is below a certain threshold. In order to avoid starving the
114 + * NIC under heavy load it is however necessary to force allocation
115 + * when hitting a minimum threshold. The strategy for alloction is as
116 + * follows:
117 + *
118 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
119 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
120 + * the buffers in the interrupt handler
121 + * RX_RING_THRES - maximum number of buffers in the rx ring
122 + *
123 + * One advantagous side effect of this allocation approach is that the
124 + * entire rx processing can be done without holding any spin lock
125 + * since the rx rings and registers are totally independent of the tx
126 + * ring and its registers. This of course includes the kmalloc's of
127 + * new skb's. Thus start_xmit can run in parallel with rx processing
128 + * and the memory allocation on SMP systems.
129 + *
130 + * Note that running the skb reallocation in a bottom half opens up
131 + * another can of races which needs to be handled properly. In
132 + * particular it can happen that the interrupt handler tries to run
133 + * the reallocation while the bottom half is either running on another
134 + * CPU or was interrupted on the same CPU. To get around this the
135 + * driver uses bitops to prevent the reallocation routines from being
136 + * reentered.
137 + *
138 + * TX handling can also be done without holding any spin lock, wheee
139 + * this is fun! since tx_csm is only written to by the interrupt
140 + * handler.
141 + */
142 +
143 +/*
144 + * Threshold values for RX buffer allocation - the low water marks for
145 + * when to start refilling the rings are set to 75% of the ring
146 + * sizes. It seems to make sense to refill the rings entirely from the
147 + * intrrupt handler once it gets below the panic threshold, that way
148 + * we don't risk that the refilling is moved to another CPU when the
149 + * one running the interrupt handler just got the slab code hot in its
150 + * cache.
151 + */
152 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
153 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
154 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
155 +#define CRC_LEN 4
156 +#define RX_OFFSET 2
157 +
158 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
159 +#define VLAN_HDR 4
160 +#else
161 +#define VLAN_HDR 0
162 +#endif
163 +
164 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET)
165 +
166 +#ifdef MODULE
167 +MODULE_LICENSE("GPL");
168 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
169 +MODULE_DESCRIPTION("AR231x Ethernet driver");
170 +#endif
171 +
172 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
173 +
174 +// prototypes
175 +static void ar231x_halt(struct net_device *dev);
176 +static void rx_tasklet_func(unsigned long data);
177 +static void rx_tasklet_cleanup(struct net_device *dev);
178 +static void ar231x_multicast_list(struct net_device *dev);
179 +
180 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
181 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value);
182 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
183 +static int ar231x_mdiobus_probe (struct net_device *dev);
184 +static void ar231x_adjust_link(struct net_device *dev);
185 +
186 +#ifndef ERR
187 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
188 +#endif
189 +
190 +static const struct net_device_ops ar231x_ops = {
191 + .ndo_open = ar231x_open,
192 + .ndo_stop = ar231x_close,
193 + .ndo_start_xmit = ar231x_start_xmit,
194 + .ndo_set_multicast_list = ar231x_multicast_list,
195 + .ndo_do_ioctl = ar231x_ioctl,
196 +};
197 +
198 +int __init ar231x_probe(struct platform_device *pdev)
199 +{
200 + struct net_device *dev;
201 + struct ar231x_private *sp;
202 + struct resource *res;
203 + unsigned long ar_eth_base;
204 + char buf[64];
205 +
206 + dev = alloc_etherdev(sizeof(struct ar231x_private));
207 +
208 + if (dev == NULL) {
209 + printk(KERN_ERR
210 + "ar231x: Unable to allocate net_device structure!\n");
211 + return -ENOMEM;
212 + }
213 +
214 + platform_set_drvdata(pdev, dev);
215 +
216 + sp = netdev_priv(dev);
217 + sp->dev = dev;
218 + sp->cfg = pdev->dev.platform_data;
219 +
220 + sprintf(buf, "eth%d_membase", pdev->id);
221 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
222 + if (!res)
223 + return -ENODEV;
224 +
225 + sp->link = 0;
226 + ar_eth_base = res->start;
227 +
228 + sprintf(buf, "eth%d_irq", pdev->id);
229 + dev->irq = platform_get_irq_byname(pdev, buf);
230 +
231 + spin_lock_init(&sp->lock);
232 +
233 + dev->features |= NETIF_F_HIGHDMA;
234 + dev->netdev_ops = &ar231x_ops;
235 +
236 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
237 + tasklet_disable(&sp->rx_tasklet);
238 +
239 + sp->eth_regs =
240 + ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs));
241 + if (!sp->eth_regs) {
242 + printk("Can't remap eth registers\n");
243 + return (-ENXIO);
244 + }
245 +
246 + /*
247 + * When there's only one MAC, PHY regs are typically on ENET0,
248 + * even though the MAC might be on ENET1.
249 + * Needto remap PHY regs separately in this case
250 + */
251 + if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs))
252 + sp->phy_regs = sp->eth_regs;
253 + else {
254 + sp->phy_regs =
255 + ioremap_nocache(virt_to_phys(sp->cfg->phy_base),
256 + sizeof(*sp->phy_regs));
257 + if (!sp->phy_regs) {
258 + printk("Can't remap phy registers\n");
259 + return (-ENXIO);
260 + }
261 + }
262 +
263 + sp->dma_regs =
264 + ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000),
265 + sizeof(*sp->dma_regs));
266 + dev->base_addr = (unsigned int) sp->dma_regs;
267 + if (!sp->dma_regs) {
268 + printk("Can't remap DMA registers\n");
269 + return (-ENXIO);
270 + }
271 +
272 + sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4);
273 + if (!sp->int_regs) {
274 + printk("Can't remap INTERRUPT registers\n");
275 + return (-ENXIO);
276 + }
277 +
278 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
279 + sp->name[sizeof(sp->name) - 1] = '\0';
280 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
281 +
282 + if (ar231x_init(dev)) {
283 + /*
284 + * ar231x_init() calls ar231x_init_cleanup() on error.
285 + */
286 + kfree(dev);
287 + return -ENODEV;
288 + }
289 +
290 + if (register_netdev(dev)) {
291 + printk("%s: register_netdev failed\n", __func__);
292 + return -1;
293 + }
294 +
295 + printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n",
296 + dev->name, sp->name,
297 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
298 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq);
299 +
300 + sp->mii_bus = mdiobus_alloc();
301 + if (sp->mii_bus == NULL)
302 + return -1;
303 +
304 + sp->mii_bus->priv = dev;
305 + sp->mii_bus->read = ar231x_mdiobus_read;
306 + sp->mii_bus->write = ar231x_mdiobus_write;
307 + sp->mii_bus->reset = ar231x_mdiobus_reset;
308 + sp->mii_bus->name = "ar231x_eth_mii";
309 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
310 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
311 + *sp->mii_bus->irq = PHY_POLL;
312 +
313 + mdiobus_register(sp->mii_bus);
314 +
315 + if (ar231x_mdiobus_probe(dev) != 0) {
316 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
317 + rx_tasklet_cleanup(dev);
318 + ar231x_init_cleanup(dev);
319 + unregister_netdev(dev);
320 + kfree(dev);
321 + return -ENODEV;
322 + }
323 +
324 + /* start link poll timer */
325 + ar231x_setup_timer(dev);
326 +
327 + return 0;
328 +}
329 +
330 +
331 +static void ar231x_multicast_list(struct net_device *dev)
332 +{
333 + struct ar231x_private *sp = netdev_priv(dev);
334 + unsigned int filter;
335 +
336 + filter = sp->eth_regs->mac_control;
337 +
338 + if (dev->flags & IFF_PROMISC)
339 + filter |= MAC_CONTROL_PR;
340 + else
341 + filter &= ~MAC_CONTROL_PR;
342 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
343 + filter |= MAC_CONTROL_PM;
344 + else
345 + filter &= ~MAC_CONTROL_PM;
346 +
347 + sp->eth_regs->mac_control = filter;
348 +}
349 +
350 +static void rx_tasklet_cleanup(struct net_device *dev)
351 +{
352 + struct ar231x_private *sp = netdev_priv(dev);
353 +
354 + /*
355 + * Tasklet may be scheduled. Need to get it removed from the list
356 + * since we're about to free the struct.
357 + */
358 +
359 + sp->unloading = 1;
360 + tasklet_enable(&sp->rx_tasklet);
361 + tasklet_kill(&sp->rx_tasklet);
362 +}
363 +
364 +static int __exit ar231x_remove(struct platform_device *pdev)
365 +{
366 + struct net_device *dev = platform_get_drvdata(pdev);
367 + struct ar231x_private *sp = netdev_priv(dev);
368 + rx_tasklet_cleanup(dev);
369 + ar231x_init_cleanup(dev);
370 + unregister_netdev(dev);
371 + mdiobus_unregister(sp->mii_bus);
372 + mdiobus_free(sp->mii_bus);
373 + kfree(dev);
374 + return 0;
375 +}
376 +
377 +
378 +/*
379 + * Restart the AR2313 ethernet controller.
380 + */
381 +static int ar231x_restart(struct net_device *dev)
382 +{
383 + /* disable interrupts */
384 + disable_irq(dev->irq);
385 +
386 + /* stop mac */
387 + ar231x_halt(dev);
388 +
389 + /* initialize */
390 + ar231x_init(dev);
391 +
392 + /* enable interrupts */
393 + enable_irq(dev->irq);
394 +
395 + return 0;
396 +}
397 +
398 +static struct platform_driver ar231x_driver = {
399 + .driver.name = "ar231x-eth",
400 + .probe = ar231x_probe,
401 + .remove = ar231x_remove,
402 +};
403 +
404 +int __init ar231x_module_init(void)
405 +{
406 + return platform_driver_register(&ar231x_driver);
407 +}
408 +
409 +void __exit ar231x_module_cleanup(void)
410 +{
411 + platform_driver_unregister(&ar231x_driver);
412 +}
413 +
414 +module_init(ar231x_module_init);
415 +module_exit(ar231x_module_cleanup);
416 +
417 +
418 +static void ar231x_free_descriptors(struct net_device *dev)
419 +{
420 + struct ar231x_private *sp = netdev_priv(dev);
421 + if (sp->rx_ring != NULL) {
422 + kfree((void *) KSEG0ADDR(sp->rx_ring));
423 + sp->rx_ring = NULL;
424 + sp->tx_ring = NULL;
425 + }
426 +}
427 +
428 +
429 +static int ar231x_allocate_descriptors(struct net_device *dev)
430 +{
431 + struct ar231x_private *sp = netdev_priv(dev);
432 + int size;
433 + int j;
434 + ar231x_descr_t *space;
435 +
436 + if (sp->rx_ring != NULL) {
437 + printk("%s: already done.\n", __FUNCTION__);
438 + return 0;
439 + }
440 +
441 + size =
442 + (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES));
443 + space = kmalloc(size, GFP_KERNEL);
444 + if (space == NULL)
445 + return 1;
446 +
447 + /* invalidate caches */
448 + dma_cache_inv((unsigned int) space, size);
449 +
450 + /* now convert pointer to KSEG1 */
451 + space = (ar231x_descr_t *) KSEG1ADDR(space);
452 +
453 + memset((void *) space, 0, size);
454 +
455 + sp->rx_ring = space;
456 + space += AR2313_DESCR_ENTRIES;
457 +
458 + sp->tx_ring = space;
459 + space += AR2313_DESCR_ENTRIES;
460 +
461 + /* Initialize the transmit Descriptors */
462 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
463 + ar231x_descr_t *td = &sp->tx_ring[j];
464 + td->status = 0;
465 + td->devcs = DMA_TX1_CHAINED;
466 + td->addr = 0;
467 + td->descr =
468 + virt_to_phys(&sp->
469 + tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]);
470 + }
471 +
472 + return 0;
473 +}
474 +
475 +
476 +/*
477 + * Generic cleanup handling data allocated during init. Used when the
478 + * module is unloaded or if an error occurs during initialization
479 + */
480 +static void ar231x_init_cleanup(struct net_device *dev)
481 +{
482 + struct ar231x_private *sp = netdev_priv(dev);
483 + struct sk_buff *skb;
484 + int j;
485 +
486 + ar231x_free_descriptors(dev);
487 +
488 + if (sp->eth_regs)
489 + iounmap((void *) sp->eth_regs);
490 + if (sp->dma_regs)
491 + iounmap((void *) sp->dma_regs);
492 +
493 + if (sp->rx_skb) {
494 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
495 + skb = sp->rx_skb[j];
496 + if (skb) {
497 + sp->rx_skb[j] = NULL;
498 + dev_kfree_skb(skb);
499 + }
500 + }
501 + kfree(sp->rx_skb);
502 + sp->rx_skb = NULL;
503 + }
504 +
505 + if (sp->tx_skb) {
506 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
507 + skb = sp->tx_skb[j];
508 + if (skb) {
509 + sp->tx_skb[j] = NULL;
510 + dev_kfree_skb(skb);
511 + }
512 + }
513 + kfree(sp->tx_skb);
514 + sp->tx_skb = NULL;
515 + }
516 +}
517 +
518 +static int ar231x_setup_timer(struct net_device *dev)
519 +{
520 + struct ar231x_private *sp = netdev_priv(dev);
521 +
522 + init_timer(&sp->link_timer);
523 +
524 + sp->link_timer.function = ar231x_link_timer_fn;
525 + sp->link_timer.data = (int) dev;
526 + sp->link_timer.expires = jiffies + HZ;
527 +
528 + add_timer(&sp->link_timer);
529 + return 0;
530 +
531 +}
532 +
533 +static void ar231x_link_timer_fn(unsigned long data)
534 +{
535 + struct net_device *dev = (struct net_device *) data;
536 + struct ar231x_private *sp = netdev_priv(dev);
537 +
538 + // see if the link status changed
539 + // This was needed to make sure we set the PHY to the
540 + // autonegotiated value of half or full duplex.
541 + ar231x_check_link(dev);
542 +
543 + // Loop faster when we don't have link.
544 + // This was needed to speed up the AP bootstrap time.
545 + if (sp->link == 0) {
546 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
547 + } else {
548 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
549 + }
550 +}
551 +
552 +static void ar231x_check_link(struct net_device *dev)
553 +{
554 + struct ar231x_private *sp = netdev_priv(dev);
555 + u16 phyData;
556 +
557 + phyData = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
558 + if (sp->phyData != phyData) {
559 + if (phyData & BMSR_LSTATUS) {
560 + /* link is present, ready link partner ability to deterine
561 + duplexity */
562 + int duplex = 0;
563 + u16 reg;
564 +
565 + sp->link = 1;
566 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR);
567 + if (reg & BMCR_ANENABLE) {
568 + /* auto neg enabled */
569 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA);
570 + duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0;
571 + } else {
572 + /* no auto neg, just read duplex config */
573 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
574 + }
575 +
576 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
577 + dev->name, (duplex) ? "full" : "half");
578 +
579 + if (duplex) {
580 + /* full duplex */
581 + sp->eth_regs->mac_control =
582 + ((sp->eth_regs->
583 + mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO);
584 + } else {
585 + /* half duplex */
586 + sp->eth_regs->mac_control =
587 + ((sp->eth_regs->
588 + mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F);
589 + }
590 + } else {
591 + /* no link */
592 + sp->link = 0;
593 + }
594 + sp->phyData = phyData;
595 + }
596 +}
597 +
598 +static int ar231x_reset_reg(struct net_device *dev)
599 +{
600 + struct ar231x_private *sp = netdev_priv(dev);
601 + unsigned int ethsal, ethsah;
602 + unsigned int flags;
603 +
604 + *sp->int_regs |= sp->cfg->reset_mac;
605 + mdelay(10);
606 + *sp->int_regs &= ~sp->cfg->reset_mac;
607 + mdelay(10);
608 + *sp->int_regs |= sp->cfg->reset_phy;
609 + mdelay(10);
610 + *sp->int_regs &= ~sp->cfg->reset_phy;
611 + mdelay(10);
612 +
613 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
614 + mdelay(10);
615 + sp->dma_regs->bus_mode =
616 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
617 +
618 + /* enable interrupts */
619 + sp->dma_regs->intr_ena = (DMA_STATUS_AIS |
620 + DMA_STATUS_NIS |
621 + DMA_STATUS_RI |
622 + DMA_STATUS_TI | DMA_STATUS_FBE);
623 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
624 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
625 + sp->dma_regs->control =
626 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
627 +
628 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
629 + sp->eth_regs->vlan_tag = (0x8100);
630 +
631 + /* Enable Ethernet Interface */
632 + flags = (MAC_CONTROL_TE | /* transmit enable */
633 + MAC_CONTROL_PM | /* pass mcast */
634 + MAC_CONTROL_F | /* full duplex */
635 + MAC_CONTROL_HBD); /* heart beat disabled */
636 +
637 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
638 + flags |= MAC_CONTROL_PR;
639 + }
640 + sp->eth_regs->mac_control = flags;
641 +
642 + /* Set all Ethernet station address registers to their initial values */
643 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
644 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
645 +
646 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
647 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
648 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
649 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
650 +
651 + sp->eth_regs->mac_addr[0] = ethsah;
652 + sp->eth_regs->mac_addr[1] = ethsal;
653 +
654 + mdelay(10);
655 +
656 + return (0);
657 +}
658 +
659 +
660 +static int ar231x_init(struct net_device *dev)
661 +{
662 + struct ar231x_private *sp = netdev_priv(dev);
663 + int ecode = 0;
664 +
665 + /*
666 + * Allocate descriptors
667 + */
668 + if (ar231x_allocate_descriptors(dev)) {
669 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
670 + dev->name, __FUNCTION__);
671 + ecode = -EAGAIN;
672 + goto init_error;
673 + }
674 +
675 + /*
676 + * Get the memory for the skb rings.
677 + */
678 + if (sp->rx_skb == NULL) {
679 + sp->rx_skb =
680 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
681 + GFP_KERNEL);
682 + if (!(sp->rx_skb)) {
683 + printk("%s: %s: rx_skb kmalloc failed\n",
684 + dev->name, __FUNCTION__);
685 + ecode = -EAGAIN;
686 + goto init_error;
687 + }
688 + }
689 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
690 +
691 + if (sp->tx_skb == NULL) {
692 + sp->tx_skb =
693 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
694 + GFP_KERNEL);
695 + if (!(sp->tx_skb)) {
696 + printk("%s: %s: tx_skb kmalloc failed\n",
697 + dev->name, __FUNCTION__);
698 + ecode = -EAGAIN;
699 + goto init_error;
700 + }
701 + }
702 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
703 +
704 + /*
705 + * Set tx_csm before we start receiving interrupts, otherwise
706 + * the interrupt handler might think it is supposed to process
707 + * tx ints before we are up and running, which may cause a null
708 + * pointer access in the int handler.
709 + */
710 + sp->rx_skbprd = 0;
711 + sp->cur_rx = 0;
712 + sp->tx_prd = 0;
713 + sp->tx_csm = 0;
714 +
715 + /*
716 + * Zero the stats before starting the interface
717 + */
718 + memset(&dev->stats, 0, sizeof(dev->stats));
719 +
720 + /*
721 + * We load the ring here as there seem to be no way to tell the
722 + * firmware to wipe the ring without re-initializing it.
723 + */
724 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
725 +
726 + /*
727 + * Init hardware
728 + */
729 + ar231x_reset_reg(dev);
730 +
731 + /*
732 + * Get the IRQ
733 + */
734 + ecode =
735 + request_irq(dev->irq, &ar231x_interrupt,
736 + IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
737 + dev->name, dev);
738 + if (ecode) {
739 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
740 + dev->name, __FUNCTION__, dev->irq);
741 + goto init_error;
742 + }
743 +
744 +
745 + tasklet_enable(&sp->rx_tasklet);
746 +
747 + return 0;
748 +
749 + init_error:
750 + ar231x_init_cleanup(dev);
751 + return ecode;
752 +}
753 +
754 +/*
755 + * Load the rx ring.
756 + *
757 + * Loading rings is safe without holding the spin lock since this is
758 + * done only before the device is enabled, thus no interrupts are
759 + * generated and by the interrupt handler/tasklet handler.
760 + */
761 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
762 +{
763 +
764 + struct ar231x_private *sp = netdev_priv(dev);
765 + short i, idx;
766 +
767 + idx = sp->rx_skbprd;
768 +
769 + for (i = 0; i < nr_bufs; i++) {
770 + struct sk_buff *skb;
771 + ar231x_descr_t *rd;
772 +
773 + if (sp->rx_skb[idx])
774 + break;
775 +
776 + skb = netdev_alloc_skb(dev, AR2313_BUFSIZE);
777 + if (!skb) {
778 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
779 + __FUNCTION__);
780 + break;
781 + }
782 +
783 + /*
784 + * Make sure IP header starts on a fresh cache line.
785 + */
786 + skb->dev = dev;
787 + skb_reserve(skb, RX_OFFSET);
788 + sp->rx_skb[idx] = skb;
789 +
790 + rd = (ar231x_descr_t *) & sp->rx_ring[idx];
791 +
792 + /* initialize dma descriptor */
793 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
794 + DMA_RX1_CHAINED);
795 + rd->addr = virt_to_phys(skb->data);
796 + rd->descr =
797 + virt_to_phys(&sp->
798 + rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]);
799 + rd->status = DMA_RX_OWN;
800 +
801 + idx = DSC_NEXT(idx);
802 + }
803 +
804 + if (i)
805 + sp->rx_skbprd = idx;
806 +
807 + return;
808 +}
809 +
810 +#define AR2313_MAX_PKTS_PER_CALL 64
811 +
812 +static int ar231x_rx_int(struct net_device *dev)
813 +{
814 + struct ar231x_private *sp = netdev_priv(dev);
815 + struct sk_buff *skb, *skb_new;
816 + ar231x_descr_t *rxdesc;
817 + unsigned int status;
818 + u32 idx;
819 + int pkts = 0;
820 + int rval;
821 +
822 + idx = sp->cur_rx;
823 +
824 + /* process at most the entire ring and then wait for another interrupt
825 + */
826 + while (1) {
827 +
828 + rxdesc = &sp->rx_ring[idx];
829 + status = rxdesc->status;
830 + if (status & DMA_RX_OWN) {
831 + /* SiByte owns descriptor or descr not yet filled in */
832 + rval = 0;
833 + break;
834 + }
835 +
836 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
837 + rval = 1;
838 + break;
839 + }
840 +
841 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
842 + dev->stats.rx_errors++;
843 + dev->stats.rx_dropped++;
844 +
845 + /* add statistics counters */
846 + if (status & DMA_RX_ERR_CRC)
847 + dev->stats.rx_crc_errors++;
848 + if (status & DMA_RX_ERR_COL)
849 + dev->stats.rx_over_errors++;
850 + if (status & DMA_RX_ERR_LENGTH)
851 + dev->stats.rx_length_errors++;
852 + if (status & DMA_RX_ERR_RUNT)
853 + dev->stats.rx_over_errors++;
854 + if (status & DMA_RX_ERR_DESC)
855 + dev->stats.rx_over_errors++;
856 +
857 + } else {
858 + /* alloc new buffer. */
859 + skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET);
860 + if (skb_new != NULL) {
861 +
862 + skb = sp->rx_skb[idx];
863 + /* set skb */
864 + skb_put(skb,
865 + ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN);
866 +
867 + dev->stats.rx_bytes += skb->len;
868 + skb->protocol = eth_type_trans(skb, dev);
869 + /* pass the packet to upper layers */
870 + netif_rx(skb);
871 +
872 + skb_new->dev = dev;
873 + /* 16 bit align */
874 + skb_reserve(skb_new, RX_OFFSET);
875 + /* reset descriptor's curr_addr */
876 + rxdesc->addr = virt_to_phys(skb_new->data);
877 +
878 + dev->stats.rx_packets++;
879 + sp->rx_skb[idx] = skb_new;
880 + } else {
881 + dev->stats.rx_dropped++;
882 + }
883 + }
884 +
885 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
886 + DMA_RX1_CHAINED);
887 + rxdesc->status = DMA_RX_OWN;
888 +
889 + idx = DSC_NEXT(idx);
890 + }
891 +
892 + sp->cur_rx = idx;
893 +
894 + return rval;
895 +}
896 +
897 +
898 +static void ar231x_tx_int(struct net_device *dev)
899 +{
900 + struct ar231x_private *sp = netdev_priv(dev);
901 + u32 idx;
902 + struct sk_buff *skb;
903 + ar231x_descr_t *txdesc;
904 + unsigned int status = 0;
905 +
906 + idx = sp->tx_csm;
907 +
908 + while (idx != sp->tx_prd) {
909 + txdesc = &sp->tx_ring[idx];
910 +
911 + if ((status = txdesc->status) & DMA_TX_OWN) {
912 + /* ar231x dma still owns descr */
913 + break;
914 + }
915 + /* done with this descriptor */
916 + dma_unmap_single(NULL, txdesc->addr,
917 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
918 + DMA_TO_DEVICE);
919 + txdesc->status = 0;
920 +
921 + if (status & DMA_TX_ERROR) {
922 + dev->stats.tx_errors++;
923 + dev->stats.tx_dropped++;
924 + if (status & DMA_TX_ERR_UNDER)
925 + dev->stats.tx_fifo_errors++;
926 + if (status & DMA_TX_ERR_HB)
927 + dev->stats.tx_heartbeat_errors++;
928 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
929 + dev->stats.tx_carrier_errors++;
930 + if (status & (DMA_TX_ERR_LATE |
931 + DMA_TX_ERR_COL |
932 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
933 + dev->stats.tx_aborted_errors++;
934 + } else {
935 + /* transmit OK */
936 + dev->stats.tx_packets++;
937 + }
938 +
939 + skb = sp->tx_skb[idx];
940 + sp->tx_skb[idx] = NULL;
941 + idx = DSC_NEXT(idx);
942 + dev->stats.tx_bytes += skb->len;
943 + dev_kfree_skb_irq(skb);
944 + }
945 +
946 + sp->tx_csm = idx;
947 +
948 + return;
949 +}
950 +
951 +
952 +static void rx_tasklet_func(unsigned long data)
953 +{
954 + struct net_device *dev = (struct net_device *) data;
955 + struct ar231x_private *sp = netdev_priv(dev);
956 +
957 + if (sp->unloading) {
958 + return;
959 + }
960 +
961 + if (ar231x_rx_int(dev)) {
962 + tasklet_hi_schedule(&sp->rx_tasklet);
963 + } else {
964 + unsigned long flags;
965 + spin_lock_irqsave(&sp->lock, flags);
966 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
967 + spin_unlock_irqrestore(&sp->lock, flags);
968 + }
969 +}
970 +
971 +static void rx_schedule(struct net_device *dev)
972 +{
973 + struct ar231x_private *sp = netdev_priv(dev);
974 +
975 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
976 +
977 + tasklet_hi_schedule(&sp->rx_tasklet);
978 +}
979 +
980 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
981 +{
982 + struct net_device *dev = (struct net_device *) dev_id;
983 + struct ar231x_private *sp = netdev_priv(dev);
984 + unsigned int status, enabled;
985 +
986 + /* clear interrupt */
987 + /*
988 + * Don't clear RI bit if currently disabled.
989 + */
990 + status = sp->dma_regs->status;
991 + enabled = sp->dma_regs->intr_ena;
992 + sp->dma_regs->status = status & enabled;
993 +
994 + if (status & DMA_STATUS_NIS) {
995 + /* normal status */
996 + /*
997 + * Don't schedule rx processing if interrupt
998 + * is already disabled.
999 + */
1000 + if (status & enabled & DMA_STATUS_RI) {
1001 + /* receive interrupt */
1002 + rx_schedule(dev);
1003 + }
1004 + if (status & DMA_STATUS_TI) {
1005 + /* transmit interrupt */
1006 + ar231x_tx_int(dev);
1007 + }
1008 + }
1009 +
1010 + /* abnormal status */
1011 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) {
1012 + ar231x_restart(dev);
1013 + }
1014 + return IRQ_HANDLED;
1015 +}
1016 +
1017 +
1018 +static int ar231x_open(struct net_device *dev)
1019 +{
1020 + struct ar231x_private *sp = netdev_priv(dev);
1021 + unsigned int ethsal, ethsah;
1022 +
1023 + /* reset the hardware, in case the MAC address changed */
1024 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1025 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
1026 +
1027 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1028 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1029 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1030 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
1031 +
1032 + sp->eth_regs->mac_addr[0] = ethsah;
1033 + sp->eth_regs->mac_addr[1] = ethsal;
1034 +
1035 + mdelay(10);
1036 +
1037 + dev->mtu = 1500;
1038 + netif_start_queue(dev);
1039 +
1040 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1041 +
1042 + return 0;
1043 +}
1044 +
1045 +static void ar231x_halt(struct net_device *dev)
1046 +{
1047 + struct ar231x_private *sp = netdev_priv(dev);
1048 + int j;
1049 +
1050 + tasklet_disable(&sp->rx_tasklet);
1051 +
1052 + /* kill the MAC */
1053 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1054 + MAC_CONTROL_TE); /* disable Transmits */
1055 + /* stop dma */
1056 + sp->dma_regs->control = 0;
1057 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1058 +
1059 + /* place phy and MAC in reset */
1060 + *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy);
1061 +
1062 + /* free buffers on tx ring */
1063 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1064 + struct sk_buff *skb;
1065 + ar231x_descr_t *txdesc;
1066 +
1067 + txdesc = &sp->tx_ring[j];
1068 + txdesc->descr = 0;
1069 +
1070 + skb = sp->tx_skb[j];
1071 + if (skb) {
1072 + dev_kfree_skb(skb);
1073 + sp->tx_skb[j] = NULL;
1074 + }
1075 + }
1076 +}
1077 +
1078 +/*
1079 + * close should do nothing. Here's why. It's called when
1080 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1081 + * the irq is gone forever ! When bond0 is made 'up' again,
1082 + * the ar231x_open () does not call request_irq (). Worse,
1083 + * the call to ar231x_halt() generates a WDOG reset due to
1084 + * the write to 'sp->int_regs' and the box reboots.
1085 + * Commenting this out is good since it allows the
1086 + * system to resume when bond0 is made up again.
1087 + */
1088 +static int ar231x_close(struct net_device *dev)
1089 +{
1090 +#if 0
1091 + /*
1092 + * Disable interrupts
1093 + */
1094 + disable_irq(dev->irq);
1095 +
1096 + /*
1097 + * Without (or before) releasing irq and stopping hardware, this
1098 + * is an absolute non-sense, by the way. It will be reset instantly
1099 + * by the first irq.
1100 + */
1101 + netif_stop_queue(dev);
1102 +
1103 + /* stop the MAC and DMA engines */
1104 + ar231x_halt(dev);
1105 +
1106 + /* release the interrupt */
1107 + free_irq(dev->irq, dev);
1108 +
1109 +#endif
1110 + return 0;
1111 +}
1112 +
1113 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1114 +{
1115 + struct ar231x_private *sp = netdev_priv(dev);
1116 + ar231x_descr_t *td;
1117 + u32 idx;
1118 +
1119 + idx = sp->tx_prd;
1120 + td = &sp->tx_ring[idx];
1121 +
1122 + if (td->status & DMA_TX_OWN) {
1123 + /* free skbuf and lie to the caller that we sent it out */
1124 + dev->stats.tx_dropped++;
1125 + dev_kfree_skb(skb);
1126 +
1127 + /* restart transmitter in case locked */
1128 + sp->dma_regs->xmt_poll = 0;
1129 + return 0;
1130 + }
1131 +
1132 + /* Setup the transmit descriptor. */
1133 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1134 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1135 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1136 + td->status = DMA_TX_OWN;
1137 +
1138 + /* kick transmitter last */
1139 + sp->dma_regs->xmt_poll = 0;
1140 +
1141 + sp->tx_skb[idx] = skb;
1142 + idx = DSC_NEXT(idx);
1143 + sp->tx_prd = idx;
1144 +
1145 + return 0;
1146 +}
1147 +
1148 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1149 +{
1150 + struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
1151 + struct ar231x_private *sp = netdev_priv(dev);
1152 + int ret;
1153 +
1154 + switch (cmd) {
1155 +
1156 + case SIOCETHTOOL:
1157 + spin_lock_irq(&sp->lock);
1158 + ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data);
1159 + spin_unlock_irq(&sp->lock);
1160 + return ret;
1161 +
1162 + case SIOCSIFHWADDR:
1163 + if (copy_from_user
1164 + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1165 + return -EFAULT;
1166 + return 0;
1167 +
1168 + case SIOCGIFHWADDR:
1169 + if (copy_to_user
1170 + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1171 + return -EFAULT;
1172 + return 0;
1173 +
1174 + case SIOCGMIIPHY:
1175 + case SIOCGMIIREG:
1176 + case SIOCSMIIREG:
1177 + return phy_mii_ioctl(sp->phy_dev, data, cmd);
1178 +
1179 + default:
1180 + break;
1181 + }
1182 +
1183 + return -EOPNOTSUPP;
1184 +}
1185 +
1186 +static void ar231x_adjust_link(struct net_device *dev)
1187 +{
1188 + struct ar231x_private *sp = netdev_priv(dev);
1189 + unsigned int mc;
1190 +
1191 + if (!sp->phy_dev->link)
1192 + return;
1193 +
1194 + if (sp->phy_dev->duplex != sp->oldduplex) {
1195 + mc = readl(&sp->eth_regs->mac_control);
1196 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1197 + if (sp->phy_dev->duplex)
1198 + mc |= MAC_CONTROL_F;
1199 + else
1200 + mc |= MAC_CONTROL_DRO;
1201 + writel(mc, &sp->eth_regs->mac_control);
1202 + sp->oldduplex = sp->phy_dev->duplex;
1203 + }
1204 +}
1205 +
1206 +#define MII_ADDR(phy, reg) \
1207 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1208 +
1209 +static int
1210 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1211 +{
1212 + struct net_device *const dev = bus->priv;
1213 + struct ar231x_private *sp = netdev_priv(dev);
1214 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1215 +
1216 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1217 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1218 + return (ethernet->mii_data >> MII_DATA_SHIFT);
1219 +}
1220 +
1221 +static int
1222 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
1223 + u16 value)
1224 +{
1225 + struct net_device *const dev = bus->priv;
1226 + struct ar231x_private *sp = netdev_priv(dev);
1227 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1228 +
1229 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1230 + ethernet->mii_data = value << MII_DATA_SHIFT;
1231 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1232 +
1233 + return 0;
1234 +}
1235 +
1236 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1237 +{
1238 + struct net_device *const dev = bus->priv;
1239 +
1240 + ar231x_reset_reg(dev);
1241 +
1242 + return 0;
1243 +}
1244 +
1245 +static int ar231x_mdiobus_probe (struct net_device *dev)
1246 +{
1247 + struct ar231x_private *const sp = netdev_priv(dev);
1248 + struct phy_device *phydev = NULL;
1249 + int phy_addr;
1250 +
1251 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1252 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1253 + if (sp->mii_bus->phy_map[phy_addr]) {
1254 + phydev = sp->mii_bus->phy_map[phy_addr];
1255 + sp->phy = phy_addr;
1256 + break; /* break out with first one found */
1257 + }
1258 +
1259 + if (!phydev) {
1260 + printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1261 + return -1;
1262 + }
1263 +
1264 + /* now we are supposed to have a proper phydev, to attach to... */
1265 + BUG_ON(!phydev);
1266 + BUG_ON(phydev->attached_dev);
1267 +
1268 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0,
1269 + PHY_INTERFACE_MODE_MII);
1270 +
1271 + if (IS_ERR(phydev)) {
1272 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1273 + return PTR_ERR(phydev);
1274 + }
1275 +
1276 + /* mask with MAC supported features */
1277 + phydev->supported &= (SUPPORTED_10baseT_Half
1278 + | SUPPORTED_10baseT_Full
1279 + | SUPPORTED_100baseT_Half
1280 + | SUPPORTED_100baseT_Full
1281 + | SUPPORTED_Autoneg
1282 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1283 + | SUPPORTED_MII
1284 + | SUPPORTED_TP);
1285 +
1286 + phydev->advertising = phydev->supported;
1287 +
1288 + sp->oldduplex = -1;
1289 + sp->phy_dev = phydev;
1290 +
1291 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1292 + "(mii_bus:phy_addr=%s)\n",
1293 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1294 +
1295 + return 0;
1296 +}
1297 +
1298 Index: linux-2.6.32.7/drivers/net/ar231x.h
1299 ===================================================================
1300 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1301 +++ linux-2.6.32.7/drivers/net/ar231x.h 2010-02-03 17:00:35.874430230 +0100
1302 @@ -0,0 +1,302 @@
1303 +/*
1304 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1305 + *
1306 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1307 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1308 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1309 + *
1310 + * Thanks to Atheros for providing hardware and documentation
1311 + * enabling me to write this driver.
1312 + *
1313 + * This program is free software; you can redistribute it and/or modify
1314 + * it under the terms of the GNU General Public License as published by
1315 + * the Free Software Foundation; either version 2 of the License, or
1316 + * (at your option) any later version.
1317 + */
1318 +
1319 +#ifndef _AR2313_H_
1320 +#define _AR2313_H_
1321 +
1322 +#include <linux/autoconf.h>
1323 +#include <linux/bitops.h>
1324 +#include <asm/bootinfo.h>
1325 +#include <ar231x_platform.h>
1326 +
1327 +/*
1328 + * probe link timer - 5 secs
1329 + */
1330 +#define LINK_TIMER (5*HZ)
1331 +
1332 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1333 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1334 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1335 +
1336 +#define AR2313_TX_TIMEOUT (HZ/4)
1337 +
1338 +/*
1339 + * Rings
1340 + */
1341 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1342 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1343 +
1344 +#define AR2313_MBGET 2
1345 +#define AR2313_MBSET 3
1346 +#define AR2313_PCI_RECONFIG 4
1347 +#define AR2313_PCI_DUMP 5
1348 +#define AR2313_TEST_PANIC 6
1349 +#define AR2313_TEST_NULLPTR 7
1350 +#define AR2313_READ_DATA 8
1351 +#define AR2313_WRITE_DATA 9
1352 +#define AR2313_GET_VERSION 10
1353 +#define AR2313_TEST_HANG 11
1354 +#define AR2313_SYNC 12
1355 +
1356 +#define DMA_RX_ERR_CRC BIT(1)
1357 +#define DMA_RX_ERR_DRIB BIT(2)
1358 +#define DMA_RX_ERR_MII BIT(3)
1359 +#define DMA_RX_EV2 BIT(5)
1360 +#define DMA_RX_ERR_COL BIT(6)
1361 +#define DMA_RX_LONG BIT(7)
1362 +#define DMA_RX_LS BIT(8) /* last descriptor */
1363 +#define DMA_RX_FS BIT(9) /* first descriptor */
1364 +#define DMA_RX_MF BIT(10) /* multicast frame */
1365 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1366 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1367 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1368 +#define DMA_RX_ERROR BIT(15) /* error summary */
1369 +#define DMA_RX_LEN_MASK 0x3fff0000
1370 +#define DMA_RX_LEN_SHIFT 16
1371 +#define DMA_RX_FILT BIT(30)
1372 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1373 +
1374 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1375 +#define DMA_RX1_BSIZE_SHIFT 0
1376 +#define DMA_RX1_CHAINED BIT(24)
1377 +#define DMA_RX1_RER BIT(25)
1378 +
1379 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1380 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1381 +#define DMA_TX_COL_MASK 0x78
1382 +#define DMA_TX_COL_SHIFT 3
1383 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1384 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1385 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1386 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1387 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1388 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1389 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1390 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1391 +
1392 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1393 +#define DMA_TX1_BSIZE_SHIFT 0
1394 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1395 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1396 +#define DMA_TX1_FS BIT(29) /* first segment */
1397 +#define DMA_TX1_LS BIT(30) /* last segment */
1398 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1399 +
1400 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1401 +
1402 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1403 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1404 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1405 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1406 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1407 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1408 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1409 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1410 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1411 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1412 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1413 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1414 +#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */
1415 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1416 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1417 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1418 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1419 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1420 +#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */
1421 +
1422 +#define MII_ADDR_BUSY BIT(0)
1423 +#define MII_ADDR_WRITE BIT(1)
1424 +#define MII_ADDR_REG_SHIFT 6
1425 +#define MII_ADDR_PHY_SHIFT 11
1426 +#define MII_DATA_SHIFT 0
1427 +
1428 +#define FLOW_CONTROL_FCE BIT(1)
1429 +
1430 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1431 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1432 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1433 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1434 +
1435 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1436 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1437 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1438 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1439 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1440 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1441 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1442 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1443 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1444 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1445 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1446 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1447 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1448 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1449 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1450 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1451 +
1452 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1453 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1454 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1455 +
1456 +
1457 +typedef struct {
1458 + volatile unsigned int status; // OWN, Device control and status.
1459 + volatile unsigned int devcs; // pkt Control bits + Length
1460 + volatile unsigned int addr; // Current Address.
1461 + volatile unsigned int descr; // Next descriptor in chain.
1462 +} ar231x_descr_t;
1463 +
1464 +
1465 +
1466 +//
1467 +// New Combo structure for Both Eth0 AND eth1
1468 +//
1469 +typedef struct {
1470 + volatile unsigned int mac_control; /* 0x00 */
1471 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1472 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1473 + volatile unsigned int mii_addr; /* 0x14 */
1474 + volatile unsigned int mii_data; /* 0x18 */
1475 + volatile unsigned int flow_control; /* 0x1c */
1476 + volatile unsigned int vlan_tag; /* 0x20 */
1477 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1478 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1479 +
1480 +} ETHERNET_STRUCT;
1481 +
1482 +/********************************************************************
1483 + * Interrupt controller
1484 + ********************************************************************/
1485 +
1486 +typedef struct {
1487 + volatile unsigned int wdog_control; /* 0x08 */
1488 + volatile unsigned int wdog_timer; /* 0x0c */
1489 + volatile unsigned int misc_status; /* 0x10 */
1490 + volatile unsigned int misc_mask; /* 0x14 */
1491 + volatile unsigned int global_status; /* 0x18 */
1492 + volatile unsigned int reserved; /* 0x1c */
1493 + volatile unsigned int reset_control; /* 0x20 */
1494 +} INTERRUPT;
1495 +
1496 +/********************************************************************
1497 + * DMA controller
1498 + ********************************************************************/
1499 +typedef struct {
1500 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1501 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1502 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1503 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1504 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1505 + volatile unsigned int status; /* 0x14 (CSR5) */
1506 + volatile unsigned int control; /* 0x18 (CSR6) */
1507 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1508 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1509 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1510 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1511 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1512 +} DMA;
1513 +
1514 +/*
1515 + * Struct private for the Sibyte.
1516 + *
1517 + * Elements are grouped so variables used by the tx handling goes
1518 + * together, and will go into the same cache lines etc. in order to
1519 + * avoid cache line contention between the rx and tx handling on SMP.
1520 + *
1521 + * Frequently accessed variables are put at the beginning of the
1522 + * struct to help the compiler generate better/shorter code.
1523 + */
1524 +struct ar231x_private {
1525 + struct net_device *dev;
1526 + int version;
1527 + u32 mb[2];
1528 +
1529 + volatile ETHERNET_STRUCT *phy_regs;
1530 + volatile ETHERNET_STRUCT *eth_regs;
1531 + volatile DMA *dma_regs;
1532 + volatile u32 *int_regs;
1533 + struct ar231x_eth *cfg;
1534 +
1535 + spinlock_t lock; /* Serialise access to device */
1536 +
1537 + /*
1538 + * RX and TX descriptors, must be adjacent
1539 + */
1540 + ar231x_descr_t *rx_ring;
1541 + ar231x_descr_t *tx_ring;
1542 +
1543 +
1544 + struct sk_buff **rx_skb;
1545 + struct sk_buff **tx_skb;
1546 +
1547 + /*
1548 + * RX elements
1549 + */
1550 + u32 rx_skbprd;
1551 + u32 cur_rx;
1552 +
1553 + /*
1554 + * TX elements
1555 + */
1556 + u32 tx_prd;
1557 + u32 tx_csm;
1558 +
1559 + /*
1560 + * Misc elements
1561 + */
1562 + char name[48];
1563 + struct {
1564 + u32 address;
1565 + u32 length;
1566 + char *mapping;
1567 + } desc;
1568 +
1569 +
1570 + struct timer_list link_timer;
1571 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1572 + unsigned short mac;
1573 + unsigned short link; /* 0 - link down, 1 - link up */
1574 + u16 phyData;
1575 +
1576 + struct tasklet_struct rx_tasklet;
1577 + int unloading;
1578 +
1579 + struct phy_device *phy_dev;
1580 + struct mii_bus *mii_bus;
1581 + int oldduplex;
1582 +};
1583 +
1584 +
1585 +/*
1586 + * Prototypes
1587 + */
1588 +static int ar231x_init(struct net_device *dev);
1589 +#ifdef TX_TIMEOUT
1590 +static void ar231x_tx_timeout(struct net_device *dev);
1591 +#endif
1592 +static int ar231x_restart(struct net_device *dev);
1593 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1594 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1595 +static int ar231x_open(struct net_device *dev);
1596 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1597 +static int ar231x_close(struct net_device *dev);
1598 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1599 + int cmd);
1600 +static void ar231x_init_cleanup(struct net_device *dev);
1601 +static int ar231x_setup_timer(struct net_device *dev);
1602 +static void ar231x_link_timer_fn(unsigned long data);
1603 +static void ar231x_check_link(struct net_device *dev);
1604 +#endif /* _AR2313_H_ */
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