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[include] cmake.mk: don't assume toolchain binaries in .../bin/ if an external toolch...
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-2.6.37 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -102,6 +102,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select GENERIC_GPIO
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -716,6 +729,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/bcm63xx/Kconfig"
30 source "arch/mips/jazz/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -5,6 +5,7 @@ platforms += ar7
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR5312/AR2312 WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,17 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + select DMA_NONCOHERENT
62 + select CEVT_R4K
63 + select CSRC_R4K
64 + select IRQ_CPU
65 + select SYS_HAS_CPU_MIPS32_R1
66 + select SYS_SUPPORTS_32BIT_KERNEL
67 + select SYS_SUPPORTS_BIG_ENDIAN
68 + select GENERIC_GPIO
69 + default y
70 --- /dev/null
71 +++ b/arch/mips/ar231x/Makefile
72 @@ -0,0 +1,13 @@
73 +#
74 +# This file is subject to the terms and conditions of the GNU General Public
75 +# License. See the file "COPYING" in the main directory of this archive
76 +# for more details.
77 +#
78 +# Copyright (C) 2006 FON Technology, SL.
79 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
80 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
81 +#
82 +
83 +obj-y += board.o prom.o devices.o
84 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
85 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
86 --- /dev/null
87 +++ b/arch/mips/ar231x/board.c
88 @@ -0,0 +1,258 @@
89 +/*
90 + * This file is subject to the terms and conditions of the GNU General Public
91 + * License. See the file "COPYING" in the main directory of this archive
92 + * for more details.
93 + *
94 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
95 + * Copyright (C) 2006 FON Technology, SL.
96 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
97 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
98 + */
99 +
100 +#include <generated/autoconf.h>
101 +#include <linux/init.h>
102 +#include <linux/module.h>
103 +#include <linux/types.h>
104 +#include <linux/string.h>
105 +#include <linux/platform_device.h>
106 +#include <linux/kernel.h>
107 +#include <linux/random.h>
108 +#include <linux/etherdevice.h>
109 +#include <asm/irq_cpu.h>
110 +#include <asm/reboot.h>
111 +#include <asm/io.h>
112 +
113 +#include <ar231x_platform.h>
114 +#include "devices.h"
115 +#include "ar5312.h"
116 +#include "ar2315.h"
117 +
118 +void (*ar231x_irq_dispatch)(void);
119 +
120 +static inline bool
121 +check_radio_magic(u8 *addr)
122 +{
123 + addr += 0x7a; /* offset for flash magic */
124 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) {
125 + return 1;
126 + }
127 + return 0;
128 +}
129 +
130 +static inline bool
131 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
132 +{
133 + /* config magic found */
134 + if (*((u32 *)addr) == AR531X_BD_MAGIC)
135 + return 1;
136 +
137 + if (!broken)
138 + return 0;
139 +
140 + if (check_radio_magic(addr + 0xf8))
141 + ar231x_board.radio = addr + 0xf8;
142 + if ((addr < flash_limit + 0x10000) &&
143 + check_radio_magic(addr + 0x10000))
144 + ar231x_board.radio = addr + 0x10000;
145 +
146 + if (ar231x_board.radio) {
147 + /* broken board data detected, use radio data to find the offset,
148 + * user will fix this */
149 + return 1;
150 + }
151 + return 0;
152 +}
153 +
154 +static u8 *
155 +find_board_config(u8 *flash_limit, bool broken)
156 +{
157 + u8 *addr;
158 + int found = 0;
159 +
160 + for (addr = flash_limit - 0x1000;
161 + addr >= flash_limit - 0x30000;
162 + addr -= 0x1000) {
163 +
164 + if (check_board_data(flash_limit, addr, broken)) {
165 + found = 1;
166 + break;
167 + }
168 + }
169 +
170 + if (!found)
171 + addr = NULL;
172 +
173 + return addr;
174 +}
175 +
176 +static u8 *
177 +find_radio_config(u8 *flash_limit, u8 *board_config)
178 +{
179 + int found;
180 + u8 *radio_config;
181 +
182 + /*
183 + * Now find the start of Radio Configuration data, using heuristics:
184 + * Search forward from Board Configuration data by 0x1000 bytes
185 + * at a time until we find non-0xffffffff.
186 + */
187 + found = 0;
188 + for (radio_config = board_config + 0x1000;
189 + (radio_config < flash_limit);
190 + radio_config += 0x1000) {
191 + if ((*(u32 *)radio_config != 0xffffffff) &&
192 + check_radio_magic(radio_config)) {
193 + found = 1;
194 + break;
195 + }
196 + }
197 +
198 + /* AR2316 relocates radio config to new location */
199 + if (!found) {
200 + for (radio_config = board_config + 0xf8;
201 + (radio_config < flash_limit - 0x1000 + 0xf8);
202 + radio_config += 0x1000) {
203 + if ((*(u32 *)radio_config != 0xffffffff) &&
204 + check_radio_magic(radio_config)) {
205 + found = 1;
206 + break;
207 + }
208 + }
209 + }
210 +
211 + if (!found) {
212 + printk("Could not find Radio Configuration data\n");
213 + radio_config = 0;
214 + }
215 +
216 + return (u8 *) radio_config;
217 +}
218 +
219 +int __init
220 +ar231x_find_config(u8 *flash_limit)
221 +{
222 + struct ar231x_boarddata *config;
223 + unsigned int rcfg_size;
224 + int broken_boarddata = 0;
225 + u8 *bcfg, *rcfg;
226 + u8 *board_data;
227 + u8 *radio_data;
228 + u8 *mac_addr;
229 + u32 offset;
230 +
231 + ar231x_board.config = NULL;
232 + ar231x_board.radio = NULL;
233 + /* Copy the board and radio data to RAM, because accessing the mapped
234 + * memory of the flash directly after booting is not safe */
235 +
236 + /* Try to find valid board and radio data */
237 + bcfg = find_board_config(flash_limit, false);
238 +
239 + /* If that fails, try to at least find valid radio data */
240 + if (!bcfg) {
241 + bcfg = find_board_config(flash_limit, true);
242 + broken_boarddata = 1;
243 + }
244 +
245 + if (!bcfg) {
246 + printk(KERN_WARNING "WARNING: No board configuration data found!\n");
247 + return -ENODEV;
248 + }
249 +
250 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
251 + ar231x_board.config = (struct ar231x_boarddata *) board_data;
252 + memcpy(board_data, bcfg, 0x100);
253 + if (broken_boarddata) {
254 + printk(KERN_WARNING "WARNING: broken board data detected\n");
255 + config = ar231x_board.config;
256 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
257 + printk(KERN_INFO "Fixing up empty mac addresses\n");
258 + config->resetConfigGpio = 0xffff;
259 + config->sysLedGpio = 0xffff;
260 + random_ether_addr(config->wlan0_mac);
261 + config->wlan0_mac[0] &= ~0x06;
262 + random_ether_addr(config->enet0_mac);
263 + random_ether_addr(config->enet1_mac);
264 + }
265 + }
266 +
267 +
268 + /* Radio config starts 0x100 bytes after board config, regardless
269 + * of what the physical layout on the flash chip looks like */
270 +
271 + if (ar231x_board.radio)
272 + rcfg = (u8 *) ar231x_board.radio;
273 + else
274 + rcfg = find_radio_config(flash_limit, bcfg);
275 +
276 + if (!rcfg)
277 + return -ENODEV;
278 +
279 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
280 + ar231x_board.radio = radio_data;
281 + offset = radio_data - board_data;
282 + printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset);
283 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
284 + memcpy(radio_data, rcfg, rcfg_size);
285 +
286 + mac_addr = &radio_data[0x1d * 2];
287 + if (is_broadcast_ether_addr(mac_addr)) {
288 + printk(KERN_INFO "Radio MAC is blank; using board-data\n");
289 + memcpy(mac_addr, ar231x_board.config->wlan0_mac, ETH_ALEN);
290 + }
291 +
292 + return 0;
293 +}
294 +
295 +static void
296 +ar231x_halt(void)
297 +{
298 + local_irq_disable();
299 + while (1);
300 +}
301 +
302 +void __init
303 +plat_mem_setup(void)
304 +{
305 + _machine_halt = ar231x_halt;
306 + pm_power_off = ar231x_halt;
307 +
308 + ar5312_plat_setup();
309 + ar2315_plat_setup();
310 +
311 + /* Disable data watchpoints */
312 + write_c0_watchlo0(0);
313 +}
314 +
315 +
316 +asmlinkage void
317 +plat_irq_dispatch(void)
318 +{
319 + ar231x_irq_dispatch();
320 +}
321 +
322 +void __init
323 +plat_time_init(void)
324 +{
325 + ar5312_time_init();
326 + ar2315_time_init();
327 +}
328 +
329 +unsigned int __cpuinit
330 +get_c0_compare_int(void)
331 +{
332 + return CP0_LEGACY_COMPARE_IRQ;
333 +}
334 +
335 +void __init
336 +arch_init_irq(void)
337 +{
338 + clear_c0_status(ST0_IM);
339 + mips_cpu_irq_init();
340 +
341 + /* Initialize interrupt controllers */
342 + ar5312_irq_init();
343 + ar2315_irq_init();
344 +}
345 +
346 +
347 --- /dev/null
348 +++ b/arch/mips/ar231x/prom.c
349 @@ -0,0 +1,37 @@
350 +/*
351 + * This file is subject to the terms and conditions of the GNU General Public
352 + * License. See the file "COPYING" in the main directory of this archive
353 + * for more details.
354 + *
355 + * Copyright MontaVista Software Inc
356 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
357 + * Copyright (C) 2006 FON Technology, SL.
358 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
359 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
360 + */
361 +
362 +/*
363 + * Prom setup file for ar531x
364 + */
365 +
366 +#include <linux/init.h>
367 +#include <generated/autoconf.h>
368 +#include <linux/kernel.h>
369 +#include <linux/string.h>
370 +#include <linux/mm.h>
371 +#include <linux/bootmem.h>
372 +
373 +#include <asm/bootinfo.h>
374 +#include <asm/addrspace.h>
375 +#include "ar5312.h"
376 +#include "ar2315.h"
377 +
378 +void __init prom_init(void)
379 +{
380 + ar5312_prom_init();
381 + ar2315_prom_init();
382 +}
383 +
384 +void __init prom_free_prom_memory(void)
385 +{
386 +}
387 --- /dev/null
388 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
389 @@ -0,0 +1,83 @@
390 +#ifndef __AR531X_PLATFORM_H
391 +#define __AR531X_PLATFORM_H
392 +
393 +/*
394 + * This is board-specific data that is stored in a "fixed" location in flash.
395 + * It is shared across operating systems, so it should not be changed lightly.
396 + * The main reason we need it is in order to extract the ethernet MAC
397 + * address(es).
398 + */
399 +struct ar231x_boarddata {
400 + u32 magic; /* board data is valid */
401 +#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
402 + u16 cksum; /* checksum (starting with BD_REV 2) */
403 + u16 rev; /* revision of this struct */
404 +#define BD_REV 4
405 + char boardName[64]; /* Name of board */
406 + u16 major; /* Board major number */
407 + u16 minor; /* Board minor number */
408 + u32 flags; /* Board configuration */
409 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
410 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
411 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
412 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
413 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
414 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
415 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
416 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
417 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
418 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
419 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */
420 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
421 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
422 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
423 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
424 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
425 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
426 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
427 + u16 resetConfigGpio; /* Reset factory GPIO pin */
428 + u16 sysLedGpio; /* System LED GPIO pin */
429 +
430 + u32 cpuFreq; /* CPU core frequency in Hz */
431 + u32 sysFreq; /* System frequency in Hz */
432 + u32 cntFreq; /* Calculated C0_COUNT frequency */
433 +
434 + u8 wlan0_mac[6];
435 + u8 enet0_mac[6];
436 + u8 enet1_mac[6];
437 +
438 + u16 pciId; /* Pseudo PCIID for common code */
439 + u16 memCap; /* cap bank1 in MB */
440 +
441 + /* version 3 */
442 + u8 wlan1_mac[6]; /* (ar5212) */
443 +};
444 +
445 +#define BOARD_CONFIG_BUFSZ 0x1000
446 +
447 +/*
448 + * Platform device information for the Wireless MAC
449 + */
450 +struct ar231x_board_config {
451 + u16 devid;
452 +
453 + /* board config data */
454 + struct ar231x_boarddata *config;
455 +
456 + /* radio calibration data */
457 + const char *radio;
458 +};
459 +
460 +/*
461 + * Platform device information for the Ethernet MAC
462 + */
463 +struct ar231x_eth {
464 + u32 reset_base;
465 + u32 reset_mac;
466 + u32 reset_phy;
467 + u32 phy_base;
468 + struct ar231x_board_config *config;
469 + char *macaddr;
470 +};
471 +
472 +#endif /* __AR531X_PLATFORM_H */
473 --- /dev/null
474 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
475 @@ -0,0 +1,84 @@
476 +/*
477 + * Atheros SoC specific CPU feature overrides
478 + *
479 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
480 + *
481 + * This file was derived from: include/asm-mips/cpu-features.h
482 + * Copyright (C) 2003, 2004 Ralf Baechle
483 + * Copyright (C) 2004 Maciej W. Rozycki
484 + *
485 + * This program is free software; you can redistribute it and/or modify it
486 + * under the terms of the GNU General Public License version 2 as published
487 + * by the Free Software Foundation.
488 + *
489 + */
490 +#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
491 +#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
492 +
493 +/*
494 + * The ATHEROS SoCs have MIPS 4Kc/4KEc core.
495 + */
496 +#define cpu_has_tlb 1
497 +#define cpu_has_4kex 1
498 +#define cpu_has_3k_cache 0
499 +#define cpu_has_4k_cache 1
500 +#define cpu_has_tx39_cache 0
501 +#define cpu_has_sb1_cache 0
502 +#define cpu_has_fpu 0
503 +#define cpu_has_32fpr 0
504 +#define cpu_has_counter 1
505 +/* #define cpu_has_watch ? */
506 +/* #define cpu_has_divec ? */
507 +/* #define cpu_has_vce ? */
508 +/* #define cpu_has_cache_cdex_p ? */
509 +/* #define cpu_has_cache_cdex_s ? */
510 +/* #define cpu_has_prefetch ? */
511 +/* #define cpu_has_mcheck ? */
512 +#define cpu_has_ejtag 1
513 +
514 +#if !defined(CONFIG_ATHEROS_AR5312)
515 +# define cpu_has_llsc 1
516 +#else
517 +/*
518 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
519 + * ll/sc instructions.
520 + */
521 +# define cpu_has_llsc 0
522 +#endif
523 +
524 +#define cpu_has_mips16 0
525 +#define cpu_has_mdmx 0
526 +#define cpu_has_mips3d 0
527 +#define cpu_has_smartmips 0
528 +
529 +/* #define cpu_has_vtag_icache ? */
530 +/* #define cpu_has_dc_aliases ? */
531 +/* #define cpu_has_ic_fills_f_dc ? */
532 +/* #define cpu_has_pindexed_dcache ? */
533 +
534 +/* #define cpu_icache_snoops_remote_store ? */
535 +
536 +#define cpu_has_mips32r1 1
537 +
538 +#if !defined(CONFIG_ATHEROS_AR5312)
539 +# define cpu_has_mips32r2 1
540 +#endif
541 +
542 +#define cpu_has_mips64r1 0
543 +#define cpu_has_mips64r2 0
544 +
545 +#define cpu_has_dsp 0
546 +#define cpu_has_mipsmt 0
547 +
548 +/* #define cpu_has_nofpuex ? */
549 +#define cpu_has_64bits 0
550 +#define cpu_has_64bit_zero_reg 0
551 +#define cpu_has_64bit_gp_regs 0
552 +#define cpu_has_64bit_addresses 0
553 +
554 +/* #define cpu_has_inclusive_pcaches ? */
555 +
556 +/* #define cpu_dcache_line_size() ? */
557 +/* #define cpu_icache_line_size() ? */
558 +
559 +#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
560 --- /dev/null
561 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
562 @@ -0,0 +1,76 @@
563 +/*
564 + * This file is subject to the terms and conditions of the GNU General Public
565 + * License. See the file "COPYING" in the main directory of this archive
566 + * for more details.
567 + *
568 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
569 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
570 + *
571 + */
572 +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
573 +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
574 +
575 +#define PCI_DMA_OFFSET 0x20000000
576 +
577 +#include <linux/device.h>
578 +
579 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
580 +{
581 +#ifdef CONFIG_PCI
582 + extern struct bus_type pci_bus_type;
583 +
584 + if (dev && dev->bus == &pci_bus_type)
585 + return PCI_DMA_OFFSET;
586 + else
587 +#endif
588 + return 0;
589 +}
590 +
591 +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
592 +{
593 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
594 +}
595 +
596 +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
597 +{
598 + return page_to_phys(page) + ar231x_dev_offset(dev);
599 +}
600 +
601 +static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
602 + dma_addr_t dma_addr)
603 +{
604 + return dma_addr - ar231x_dev_offset(dev);
605 +}
606 +
607 +static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
608 + size_t size, enum dma_data_direction direction)
609 +{
610 +}
611 +
612 +static inline int plat_dma_supported(struct device *dev, u64 mask)
613 +{
614 + return 1;
615 +}
616 +
617 +static inline void plat_extra_sync_for_device(struct device *dev)
618 +{
619 + return;
620 +}
621 +
622 +static inline int plat_dma_mapping_error(struct device *dev,
623 + dma_addr_t dma_addr)
624 +{
625 + return 0;
626 +}
627 +
628 +static inline int plat_device_is_coherent(struct device *dev)
629 +{
630 +#ifdef CONFIG_DMA_COHERENT
631 + return 1;
632 +#endif
633 +#ifdef CONFIG_DMA_NONCOHERENT
634 + return 0;
635 +#endif
636 +}
637 +
638 +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
639 --- /dev/null
640 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
641 @@ -0,0 +1,84 @@
642 +#ifndef _ATHEROS_GPIO_H_
643 +#define _ATHEROS_GPIO_H_
644 +
645 +#include <ar231x.h>
646 +
647 +struct ar231x_gpiodev {
648 + u32 valid_mask;
649 + u32 (*get_output)(void);
650 + u32 (*set_output)(u32 mask, u32 val);
651 + u32 (*get)(void);
652 + u32 (*set)(u32 mask, u32 val);
653 +};
654 +
655 +extern const struct ar231x_gpiodev *ar231x_gpiodev;
656 +
657 +/*
658 + * Wrappers for the generic GPIO layer
659 + */
660 +
661 +static inline int gpio_direction_input(unsigned gpio) {
662 + u32 mask = 1 << gpio;
663 +
664 + if (!(ar231x_gpiodev->valid_mask & mask))
665 + return -ENXIO;
666 +
667 + ar231x_gpiodev->set_output(mask, 0);
668 + return 0;
669 +}
670 +
671 +static inline void gpio_set_value(unsigned gpio, int value) {
672 + u32 mask = 1 << gpio;
673 +
674 + if (!(ar231x_gpiodev->valid_mask & mask))
675 + return;
676 +
677 + ar231x_gpiodev->set(mask, (!!value) * mask);
678 +}
679 +
680 +static inline int gpio_direction_output(unsigned gpio, int value) {
681 + u32 mask = 1 << gpio;
682 +
683 + if (!(ar231x_gpiodev->valid_mask & mask))
684 + return -ENXIO;
685 +
686 + ar231x_gpiodev->set_output(mask, mask);
687 + ar231x_gpiodev->set(mask, (!!value) * mask);
688 + return 0;
689 +}
690 +
691 +/* Reads the gpio pin. Unchecked function */
692 +static inline int gpio_get_value(unsigned gpio) {
693 + u32 mask = 1 << gpio;
694 +
695 + if (!(ar231x_gpiodev->valid_mask & mask))
696 + return 0;
697 +
698 + return !!(ar231x_gpiodev->get() & mask);
699 +}
700 +
701 +static inline int gpio_request(unsigned gpio, const char *label) {
702 + return 0;
703 +}
704 +
705 +static inline void gpio_free(unsigned gpio) {
706 +}
707 +
708 +/* Returns IRQ to attach for gpio. Unchecked function */
709 +static inline int gpio_to_irq(unsigned gpio) {
710 + return AR531X_GPIO_IRQ(gpio);
711 +}
712 +
713 +/* Returns gpio for IRQ attached. Unchecked function */
714 +static inline int irq_to_gpio(unsigned irq) {
715 + return (irq - (AR531X_GPIO_IRQ(0)));
716 +}
717 +
718 +static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
719 +{
720 + return -ENOSYS;
721 +}
722 +
723 +#include <asm-generic/gpio.h> /* cansleep wrappers */
724 +
725 +#endif
726 --- /dev/null
727 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
728 @@ -0,0 +1,6 @@
729 +#ifndef __AR531X_RESET_H
730 +#define __AR531X_RESET_H
731 +
732 +void ar531x_disable_reset_button(void);
733 +
734 +#endif /* __AR531X_RESET_H */
735 --- /dev/null
736 +++ b/arch/mips/include/asm/mach-ar231x/war.h
737 @@ -0,0 +1,25 @@
738 +/*
739 + * This file is subject to the terms and conditions of the GNU General Public
740 + * License. See the file "COPYING" in the main directory of this archive
741 + * for more details.
742 + *
743 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
744 + */
745 +#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H
746 +#define __ASM_MIPS_MACH_ATHEROS_WAR_H
747 +
748 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
749 +#define R4600_V1_HIT_CACHEOP_WAR 0
750 +#define R4600_V2_HIT_CACHEOP_WAR 0
751 +#define R5432_CP0_INTERRUPT_WAR 0
752 +#define BCM1250_M3_WAR 0
753 +#define SIBYTE_1956_WAR 0
754 +#define MIPS4K_ICACHE_REFILL_WAR 0
755 +#define MIPS_CACHE_SYNC_WAR 0
756 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
757 +#define RM9000_CDEX_SMP_WAR 0
758 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
759 +#define R10000_LLSC_WAR 0
760 +#define MIPS34K_MISSED_ITLB_WAR 0
761 +
762 +#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
763 --- /dev/null
764 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
765 @@ -0,0 +1,580 @@
766 +/*
767 + * Register definitions for AR2315+
768 + *
769 + * This file is subject to the terms and conditions of the GNU General Public
770 + * License. See the file "COPYING" in the main directory of this archive
771 + * for more details.
772 + *
773 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
774 + * Copyright (C) 2006 FON Technology, SL.
775 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
776 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
777 + */
778 +
779 +#ifndef __AR2315_REG_H
780 +#define __AR2315_REG_H
781 +
782 +/*
783 + * IRQs
784 + */
785 +#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
786 +#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
787 +#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
788 +#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
789 +#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
790 +
791 +/*
792 + * Address map
793 + */
794 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
795 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
796 +#define AR2315_PCI 0x10100000 /* PCI MMR */
797 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
798 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
799 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
800 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
801 +#define AR2315_UART0 0x11100003 /* UART MMR */
802 +#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */
803 +#define AR2315_PCIEXT 0x80000000 /* pci external */
804 +
805 +/*
806 + * Reset Register
807 + */
808 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
809 +
810 +#define AR2315_RESET_COLD_AHB 0x00000001
811 +#define AR2315_RESET_COLD_APB 0x00000002
812 +#define AR2315_RESET_COLD_CPU 0x00000004
813 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
814 +#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */
815 +#define AR2317_RESET_SYSTEM 0x00000010
816 +
817 +
818 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
819 +
820 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
821 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */
822 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
823 +#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
824 +#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */
825 +#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
826 +#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
827 +#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */
828 +#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
829 +#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */
830 +#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
831 +#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */
832 +
833 +/*
834 + * AHB master arbitration control
835 + */
836 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
837 +
838 +#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
839 +#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
840 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
841 +#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */
842 +#define AR2315_ARB_PCI 0x00000010 /* PCI */
843 +#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
844 +#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */
845 +
846 +/*
847 + * Config Register
848 + */
849 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
850 +
851 +#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */
852 +#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
853 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
854 +#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
855 +#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */
856 +#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
857 +#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
858 +
859 +#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
860 +#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
861 +#define AR2315_CONFIG_PCIAHB 0x00000800
862 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
863 +#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
864 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
865 +#define AR2315_CONFIG_CPU_PCI 0x00020000
866 +#define AR2315_CONFIG_CPU_MMR 0x00040000
867 +#define AR2315_CONFIG_BIG 0x00000400
868 +
869 +
870 +/*
871 + * NMI control
872 + */
873 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
874 +
875 +#define AR2315_NMI_EN 1
876 +
877 +/*
878 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
879 + */
880 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
881 +
882 +#define AR2315_REV_MAJ 0x00f0
883 +#define AR2315_REV_MAJ_S 4
884 +#define AR2315_REV_MIN 0x000f
885 +#define AR2315_REV_MIN_S 0
886 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
887 +
888 +/*
889 + * Interface Enable
890 + */
891 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
892 +
893 +#define AR2315_IF_MASK 0x00000007
894 +#define AR2315_IF_DISABLED 0
895 +#define AR2315_IF_PCI 1
896 +#define AR2315_IF_TS_LOCAL 2
897 +#define AR2315_IF_ALL 3 /* only for emulation with separate pins */
898 +#define AR2315_IF_LOCAL_HOST 0x00000008
899 +#define AR2315_IF_PCI_HOST 0x00000010
900 +#define AR2315_IF_PCI_INTR 0x00000020
901 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
902 +#define AR2315_IF_PCI_CLK_INPUT 0
903 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
904 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
905 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
906 +#define AR2315_IF_PCI_CLK_SHIFT 16
907 +
908 +/*
909 + * APB Interrupt control
910 + */
911 +
912 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
913 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
914 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
915 +
916 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
917 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
918 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
919 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
920 +#define AR2315_ISR_APB 0x0010 /* APB error */
921 +#define AR2315_ISR_TIMER 0x0020 /* timer */
922 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
923 +#define AR2315_ISR_WD 0x0080 /* watchdog */
924 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
925 +
926 +#define AR2315_GISR_MISC 0x0001
927 +#define AR2315_GISR_WLAN0 0x0002
928 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
929 +#define AR2315_GISR_LOCALPCI 0x0008
930 +#define AR2315_GISR_WMACPOLL 0x0010
931 +#define AR2315_GISR_TIMER 0x0020
932 +#define AR2315_GISR_ETHERNET 0x0040
933 +
934 +/*
935 + * Interrupt routing from IO to the processor IP bits
936 + * Define our inter mask and level
937 + */
938 +#define AR2315_INTR_MISCIO SR_IBIT3
939 +#define AR2315_INTR_WLAN0 SR_IBIT4
940 +#define AR2315_INTR_ENET0 SR_IBIT5
941 +#define AR2315_INTR_LOCALPCI SR_IBIT6
942 +#define AR2315_INTR_WMACPOLL SR_IBIT7
943 +#define AR2315_INTR_COMPARE SR_IBIT8
944 +
945 +/*
946 + * Timers
947 + */
948 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
949 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
950 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
951 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
952 +
953 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
954 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
955 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
956 +
957 +/*
958 + * CPU Performance Counters
959 + */
960 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
961 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
962 +
963 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
964 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
965 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
966 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
967 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
968 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
969 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
970 +
971 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
972 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
973 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
974 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
975 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
976 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
977 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
978 +
979 +/*
980 + * AHB Error Reporting.
981 + */
982 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
983 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
984 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
985 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
986 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
987 +
988 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
989 + /* write 1 to clear all bits in ERR0 */
990 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
991 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
992 +
993 +#define AR2315_PROCERR_HMAST 0x0000000f
994 +#define AR2315_PROCERR_HMAST_DFLT 0
995 +#define AR2315_PROCERR_HMAST_WMAC 1
996 +#define AR2315_PROCERR_HMAST_ENET 2
997 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
998 +#define AR2315_PROCERR_HMAST_LOCAL 4
999 +#define AR2315_PROCERR_HMAST_CPU 5
1000 +#define AR2315_PROCERR_HMAST_PCITGT 6
1001 +
1002 +#define AR2315_PROCERR_HMAST_S 0
1003 +#define AR2315_PROCERR_HWRITE 0x00000010
1004 +#define AR2315_PROCERR_HSIZE 0x00000060
1005 +#define AR2315_PROCERR_HSIZE_S 5
1006 +#define AR2315_PROCERR_HTRANS 0x00000180
1007 +#define AR2315_PROCERR_HTRANS_S 7
1008 +#define AR2315_PROCERR_HBURST 0x00000e00
1009 +#define AR2315_PROCERR_HBURST_S 9
1010 +
1011 +/*
1012 + * Clock Control
1013 + */
1014 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
1015 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
1016 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
1017 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
1018 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
1019 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
1020 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
1021 +
1022 +/* PLLc Control fields */
1023 +#define PLLC_REF_DIV_M 0x00000003
1024 +#define PLLC_REF_DIV_S 0
1025 +#define PLLC_FDBACK_DIV_M 0x0000007C
1026 +#define PLLC_FDBACK_DIV_S 2
1027 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1028 +#define PLLC_ADD_FDBACK_DIV_S 7
1029 +#define PLLC_CLKC_DIV_M 0x0001c000
1030 +#define PLLC_CLKC_DIV_S 14
1031 +#define PLLC_CLKM_DIV_M 0x00700000
1032 +#define PLLC_CLKM_DIV_S 20
1033 +
1034 +/* CPU CLK Control fields */
1035 +#define CPUCLK_CLK_SEL_M 0x00000003
1036 +#define CPUCLK_CLK_SEL_S 0
1037 +#define CPUCLK_CLK_DIV_M 0x0000000c
1038 +#define CPUCLK_CLK_DIV_S 2
1039 +
1040 +/* AMBA CLK Control fields */
1041 +#define AMBACLK_CLK_SEL_M 0x00000003
1042 +#define AMBACLK_CLK_SEL_S 0
1043 +#define AMBACLK_CLK_DIV_M 0x0000000c
1044 +#define AMBACLK_CLK_DIV_S 2
1045 +
1046 +/*
1047 + * GPIO
1048 + */
1049 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1050 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1051 +#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
1052 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1053 +
1054 +#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1055 +#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
1056 +#define AR2315_GPIO_CR_I(x) (0) /* input */
1057 +
1058 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1059 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1060 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1061 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1062 +
1063 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */
1064 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1065 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1066 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1067 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1068 +
1069 +#define AR2315_RESET_GPIO 5
1070 +#define AR2315_NUM_GPIO 22
1071 +
1072 +/*
1073 + * PCI Clock Control
1074 + */
1075 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1076 +
1077 +#define AR2315_PCICLK_INPUT_M 0x3
1078 +#define AR2315_PCICLK_INPUT_S 0
1079 +
1080 +#define AR2315_PCICLK_PLLC_CLKM 0
1081 +#define AR2315_PCICLK_PLLC_CLKM1 1
1082 +#define AR2315_PCICLK_PLLC_CLKC 2
1083 +#define AR2315_PCICLK_REF_CLK 3
1084 +
1085 +#define AR2315_PCICLK_DIV_M 0xc
1086 +#define AR2315_PCICLK_DIV_S 2
1087 +
1088 +#define AR2315_PCICLK_IN_FREQ 0
1089 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1090 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1091 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1092 +
1093 +/*
1094 + * Observation Control Register
1095 + */
1096 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1097 +#define OCR_GPIO0_IRIN 0x0040
1098 +#define OCR_GPIO1_IROUT 0x0080
1099 +#define OCR_GPIO3_RXCLR 0x0200
1100 +
1101 +/*
1102 + * General Clock Control
1103 + */
1104 +
1105 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1106 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1107 +#define MISCCLK_PROCREFCLK 0x00000002
1108 +
1109 +/*
1110 + * SDRAM Controller
1111 + * - No read or write buffers are included.
1112 + */
1113 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1114 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1115 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1116 +
1117 +#define SDRAM_DATA_WIDTH_M 0x00006000
1118 +#define SDRAM_DATA_WIDTH_S 13
1119 +
1120 +#define SDRAM_COL_WIDTH_M 0x00001E00
1121 +#define SDRAM_COL_WIDTH_S 9
1122 +
1123 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1124 +#define SDRAM_ROW_WIDTH_S 5
1125 +
1126 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1127 +#define SDRAM_BANKADDR_BITS_S 3
1128 +
1129 +/*
1130 + * SPI Flash Interface Registers
1131 + */
1132 +
1133 +#define AR2315_SPI_CTL (AR2315_SPI + 0x00)
1134 +#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04)
1135 +#define AR2315_SPI_DATA (AR2315_SPI + 0x08)
1136 +
1137 +#define SPI_CTL_START 0x00000100
1138 +#define SPI_CTL_BUSY 0x00010000
1139 +#define SPI_CTL_TXCNT_MASK 0x0000000f
1140 +#define SPI_CTL_RXCNT_MASK 0x000000f0
1141 +#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
1142 +#define SPI_CTL_SIZE_MASK 0x00060000
1143 +
1144 +#define SPI_CTL_CLK_SEL_MASK 0x03000000
1145 +#define SPI_OPCODE_MASK 0x000000ff
1146 +
1147 +/*
1148 + * PCI Bus Interface Registers
1149 + */
1150 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1151 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1152 +
1153 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1154 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1155 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1156 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1157 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1158 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1159 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1160 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1161 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1162 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1163 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1164 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1165 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */
1166 +
1167 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1168 +
1169 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1170 +
1171 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1172 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1173 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1174 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1175 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1176 +
1177 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1178 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1179 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1180 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1181 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1182 +
1183 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1184 +
1185 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1186 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1187 +
1188 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1189 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1190 +
1191 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1192 +
1193 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1194 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1195 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1196 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1197 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1198 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1199 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1200 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1201 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1202 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1203 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1204 +#define AR2315_PCI_EXT_INT 0x02000000
1205 +#define AR2315_PCI_ABORT_INT 0x04000000
1206 +
1207 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1208 +
1209 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1210 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1211 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1212 +
1213 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1214 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1215 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1216 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1217 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1218 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1219 +
1220 +
1221 +/*
1222 + * Local Bus Interface Registers
1223 + */
1224 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1225 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1226 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1227 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1228 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1229 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1230 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1231 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1232 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1233 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1234 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1235 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1236 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1237 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1238 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1239 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1240 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1241 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1242 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1243 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1244 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1245 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1246 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1247 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1248 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1249 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1250 +
1251 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1252 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1253 +
1254 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1255 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1256 +
1257 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1258 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1259 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1260 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1261 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1262 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1263 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1264 +#define AR2315_LBM_TIMEOUT_SHFT 7
1265 +#define AR2315_LBM_PORTMUX 0x07000000
1266 +
1267 +
1268 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1269 +
1270 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1271 +#define AR2315_LB_TXEN_0 0x01
1272 +#define AR2315_LB_TXEN_1 0x02
1273 +#define AR2315_LB_TXEN_2 0x04
1274 +#define AR2315_LB_TXEN_3 0x08
1275 +
1276 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1277 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1278 +
1279 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1280 +#define AR2315_LB_RXEN 0x01
1281 +
1282 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1283 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1284 +
1285 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1286 +#define AR2315_INT_TX_DESC 0x0001
1287 +#define AR2315_INT_TX_OK 0x0002
1288 +#define AR2315_INT_TX_ERR 0x0004
1289 +#define AR2315_INT_TX_EOF 0x0008
1290 +#define AR2315_INT_RX_DESC 0x0010
1291 +#define AR2315_INT_RX_OK 0x0020
1292 +#define AR2315_INT_RX_ERR 0x0040
1293 +#define AR2315_INT_RX_EOF 0x0080
1294 +#define AR2315_INT_TX_TRUNC 0x0100
1295 +#define AR2315_INT_TX_STARVE 0x0200
1296 +#define AR2315_INT_LB_TIMEOUT 0x0400
1297 +#define AR2315_INT_LB_ERR 0x0800
1298 +#define AR2315_INT_MBOX_WR 0x1000
1299 +#define AR2315_INT_MBOX_RD 0x2000
1300 +
1301 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1302 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1303 +
1304 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1305 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1306 +
1307 +/*
1308 + * IR Interface Registers
1309 + */
1310 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1311 +
1312 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1313 +
1314 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1315 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1316 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1317 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */
1318 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1319 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */
1320 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1321 +
1322 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1323 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1324 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1325 +
1326 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1327 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */
1328 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */
1329 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1330 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */
1331 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */
1332 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */
1333 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */
1334 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */
1335 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */
1336 +
1337 +#define HOST_PCI_DEV_ID 3
1338 +#define HOST_PCI_MBAR0 0x10000000
1339 +#define HOST_PCI_MBAR1 0x20000000
1340 +#define HOST_PCI_MBAR2 0x30000000
1341 +
1342 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1343 +#define PCI_DEVICE_MEM_SPACE 0x800000
1344 +
1345 +#endif /* __AR2315_REG_H */
1346 --- /dev/null
1347 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1348 @@ -0,0 +1,236 @@
1349 +/*
1350 + * This file is subject to the terms and conditions of the GNU General Public
1351 + * License. See the file "COPYING" in the main directory of this archive
1352 + * for more details.
1353 + *
1354 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1355 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1356 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1357 + */
1358 +
1359 +#ifndef AR5312_H
1360 +#define AR5312_H
1361 +
1362 +#include <asm/addrspace.h>
1363 +
1364 +/*
1365 + * IRQs
1366 + */
1367 +
1368 +#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
1369 +#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
1370 +#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
1371 +#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
1372 +#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
1373 +
1374 +
1375 +/* Address Map */
1376 +#define AR531X_WLAN0 0x18000000
1377 +#define AR531X_WLAN1 0x18500000
1378 +#define AR531X_ENET0 0x18100000
1379 +#define AR531X_ENET1 0x18200000
1380 +#define AR531X_SDRAMCTL 0x18300000
1381 +#define AR531X_FLASHCTL 0x18400000
1382 +#define AR531X_APBBASE 0x1c000000
1383 +#define AR531X_FLASH 0x1e000000
1384 +#define AR531X_UART0 0xbc000003 /* UART MMR */
1385 +
1386 +/*
1387 + * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
1388 + * should be considered available. The AR5312 supports 2 enet MACS,
1389 + * even though many reference boards only actually use 1 of them
1390 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1391 + * The AR2312 supports 1 enet MAC.
1392 + */
1393 +#define AR531X_NUM_ENET_MAC 2
1394 +
1395 +/*
1396 + * Need these defines to determine true number of ethernet MACs
1397 + */
1398 +#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1399 +#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1400 +#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1401 +#define AR531X_RADIO_MASK_OFF 0xc8
1402 +#define AR531X_RADIO0_MASK 0x0003
1403 +#define AR531X_RADIO1_MASK 0x000c
1404 +#define AR531X_RADIO1_S 2
1405 +
1406 +/*
1407 + * AR531X_NUM_WMAC defines the number of Wireless MACs that\
1408 + * should be considered available.
1409 + */
1410 +#define AR531X_NUM_WMAC 2
1411 +
1412 +/* Reset/Timer Block Address Map */
1413 +#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
1414 +#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
1415 +#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
1416 +#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
1417 +#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
1418 +#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
1419 +#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
1420 +#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
1421 +#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
1422 +#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
1423 +#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
1424 +#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
1425 +#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
1426 +#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
1427 +#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
1428 +
1429 +/* AR531X_WD_CTRL register bit field definitions */
1430 +#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
1431 +#define AR531X_WD_CTRL_NMI 0x0001
1432 +#define AR531X_WD_CTRL_RESET 0x0002
1433 +
1434 +/* AR531X_ISR register bit field definitions */
1435 +#define AR531X_ISR_NONE 0x0000
1436 +#define AR531X_ISR_TIMER 0x0001
1437 +#define AR531X_ISR_AHBPROC 0x0002
1438 +#define AR531X_ISR_AHBDMA 0x0004
1439 +#define AR531X_ISR_GPIO 0x0008
1440 +#define AR531X_ISR_UART0 0x0010
1441 +#define AR531X_ISR_UART0DMA 0x0020
1442 +#define AR531X_ISR_WD 0x0040
1443 +#define AR531X_ISR_LOCAL 0x0080
1444 +
1445 +/* AR531X_RESET register bit field definitions */
1446 +#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
1447 +#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
1448 +#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1449 +#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1450 +#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1451 +#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1452 +#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1453 +#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1454 +#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1455 +#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1456 +#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1457 +#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1458 +#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1459 +#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
1460 +#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1461 +#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1462 +#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1463 +#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1464 +
1465 +#define AR531X_RESET_WMAC0_BITS \
1466 + AR531X_RESET_WLAN0 |\
1467 + AR531X_RESET_WARM_WLAN0_MAC |\
1468 + AR531X_RESET_WARM_WLAN0_BB
1469 +
1470 +#define AR531X_RESERT_WMAC1_BITS \
1471 + AR531X_RESET_WLAN1 |\
1472 + AR531X_RESET_WARM_WLAN1_MAC |\
1473 + AR531X_RESET_WARM_WLAN1_BB
1474 +
1475 +/* AR5312_CLOCKCTL1 register bit field definitions */
1476 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1477 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1478 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1479 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1480 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1481 +
1482 +/* Valid for AR5312 and AR2312 */
1483 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1484 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1485 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1486 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1487 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1488 +
1489 +/* Valid for AR2313 */
1490 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1491 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1492 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1493 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1494 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1495 +
1496 +
1497 +/* AR531X_ENABLE register bit field definitions */
1498 +#define AR531X_ENABLE_WLAN0 0x0001
1499 +#define AR531X_ENABLE_ENET0 0x0002
1500 +#define AR531X_ENABLE_ENET1 0x0004
1501 +#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1502 +#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1503 +#define AR531X_ENABLE_WLAN1 \
1504 + (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA)
1505 +
1506 +/* AR531X_REV register bit field definitions */
1507 +#define AR531X_REV_WMAC_MAJ 0xf000
1508 +#define AR531X_REV_WMAC_MAJ_S 12
1509 +#define AR531X_REV_WMAC_MIN 0x0f00
1510 +#define AR531X_REV_WMAC_MIN_S 8
1511 +#define AR531X_REV_MAJ 0x00f0
1512 +#define AR531X_REV_MAJ_S 4
1513 +#define AR531X_REV_MIN 0x000f
1514 +#define AR531X_REV_MIN_S 0
1515 +#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
1516 +
1517 +/* Major revision numbers, bits 7..4 of Revision ID register */
1518 +#define AR531X_REV_MAJ_AR5312 0x4
1519 +#define AR531X_REV_MAJ_AR2313 0x5
1520 +
1521 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1522 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1523 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1524 +
1525 +/* AR531X_FLASHCTL register bit field definitions */
1526 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1527 +#define FLASHCTL_IDCY_S 0
1528 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1529 +#define FLASHCTL_WST1_S 5
1530 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1531 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1532 +#define FLASHCTL_WST2_S 11
1533 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1534 +#define FLASHCTL_AC_S 16
1535 +#define FLASHCTL_AC_128K 0x00000000
1536 +#define FLASHCTL_AC_256K 0x00010000
1537 +#define FLASHCTL_AC_512K 0x00020000
1538 +#define FLASHCTL_AC_1M 0x00030000
1539 +#define FLASHCTL_AC_2M 0x00040000
1540 +#define FLASHCTL_AC_4M 0x00050000
1541 +#define FLASHCTL_AC_8M 0x00060000
1542 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1543 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1544 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1545 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1546 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1547 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1548 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1549 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1550 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1551 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1552 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1553 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1554 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1555 +
1556 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1557 +#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
1558 +#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
1559 +#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
1560 +
1561 +/* ARM SDRAM Controller -- just enough to determine memory size */
1562 +#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
1563 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1564 +#define MEM_CFG1_AC0_S 8
1565 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1566 +#define MEM_CFG1_AC1_S 12
1567 +
1568 +/* GPIO Address Map */
1569 +#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
1570 +#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
1571 +#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
1572 +#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
1573 +
1574 +/* GPIO Control Register bit field definitions */
1575 +#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1576 +#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1577 +#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1578 +#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
1579 +#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1580 +#define AR531X_NUM_GPIO 8
1581 +
1582 +
1583 +#endif
1584 +
1585 --- /dev/null
1586 +++ b/arch/mips/ar231x/ar5312.c
1587 @@ -0,0 +1,549 @@
1588 +/*
1589 + * This file is subject to the terms and conditions of the GNU General Public
1590 + * License. See the file "COPYING" in the main directory of this archive
1591 + * for more details.
1592 + *
1593 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1594 + * Copyright (C) 2006 FON Technology, SL.
1595 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1596 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1597 + */
1598 +
1599 +/*
1600 + * Platform devices for Atheros SoCs
1601 + */
1602 +
1603 +#include <generated/autoconf.h>
1604 +#include <linux/init.h>
1605 +#include <linux/module.h>
1606 +#include <linux/types.h>
1607 +#include <linux/string.h>
1608 +#include <linux/mtd/physmap.h>
1609 +#include <linux/platform_device.h>
1610 +#include <linux/kernel.h>
1611 +#include <linux/reboot.h>
1612 +#include <linux/leds.h>
1613 +#include <asm/bootinfo.h>
1614 +#include <asm/reboot.h>
1615 +#include <asm/time.h>
1616 +#include <asm/irq.h>
1617 +#include <asm/io.h>
1618 +#include <gpio.h>
1619 +
1620 +#include <ar231x_platform.h>
1621 +#include <ar5312_regs.h>
1622 +#include <ar231x.h>
1623 +#include "devices.h"
1624 +#include "ar5312.h"
1625 +
1626 +static void
1627 +ar5312_misc_irq_dispatch(void)
1628 +{
1629 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR);
1630 +
1631 + if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
1632 + do_IRQ(AR531X_MISC_IRQ_TIMER);
1633 + (void)ar231x_read_reg(AR531X_TIMER);
1634 + } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC)
1635 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1636 + else if ((ar231x_misc_intrs & AR531X_ISR_UART0))
1637 + do_IRQ(AR531X_MISC_IRQ_UART0);
1638 + else if (ar231x_misc_intrs & AR531X_ISR_WD)
1639 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1640 + else
1641 + do_IRQ(AR531X_MISC_IRQ_NONE);
1642 +}
1643 +
1644 +static asmlinkage void
1645 +ar5312_irq_dispatch(void)
1646 +{
1647 + int pending = read_c0_status() & read_c0_cause();
1648 +
1649 + if (pending & CAUSEF_IP2)
1650 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1651 + else if (pending & CAUSEF_IP3)
1652 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1653 + else if (pending & CAUSEF_IP4)
1654 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1655 + else if (pending & CAUSEF_IP5)
1656 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1657 + else if (pending & CAUSEF_IP6)
1658 + ar5312_misc_irq_dispatch();
1659 + else if (pending & CAUSEF_IP7)
1660 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
1661 +}
1662 +
1663 +
1664 +/* Enable the specified AR531X_MISC_IRQ interrupt */
1665 +static void
1666 +ar5312_misc_intr_enable(unsigned int irq)
1667 +{
1668 + unsigned int imr;
1669 +
1670 + imr = ar231x_read_reg(AR531X_IMR);
1671 + imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
1672 + ar231x_write_reg(AR531X_IMR, imr);
1673 +}
1674 +
1675 +/* Disable the specified AR531X_MISC_IRQ interrupt */
1676 +static void
1677 +ar5312_misc_intr_disable(unsigned int irq)
1678 +{
1679 + unsigned int imr;
1680 +
1681 + imr = ar231x_read_reg(AR531X_IMR);
1682 + imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
1683 + ar231x_write_reg(AR531X_IMR, imr);
1684 + ar231x_read_reg(AR531X_IMR); /* flush write buffer */
1685 +}
1686 +
1687 +static void
1688 +ar5312_misc_intr_end(unsigned int irq)
1689 +{
1690 + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
1691 + ar5312_misc_intr_enable(irq);
1692 +}
1693 +
1694 +static struct irq_chip ar5312_misc_intr_controller = {
1695 + .name = "AR5312-MISC",
1696 + .disable = ar5312_misc_intr_disable,
1697 + .ack = ar5312_misc_intr_disable,
1698 + .mask_ack = ar5312_misc_intr_disable,
1699 + .mask = ar5312_misc_intr_disable,
1700 + .unmask = ar5312_misc_intr_enable,
1701 + .end = ar5312_misc_intr_end,
1702 +};
1703 +
1704 +
1705 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1706 +{
1707 + u32 proc1 = ar231x_read_reg(AR531X_PROC1);
1708 + u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */
1709 + u32 dma1 = ar231x_read_reg(AR531X_DMA1);
1710 + u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */
1711 +
1712 + printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1713 + procAddr, proc1, dmaAddr, dma1);
1714 +
1715 + machine_restart("AHB error"); /* Catastrophic failure */
1716 + return IRQ_HANDLED;
1717 +}
1718 +
1719 +
1720 +static struct irqaction ar5312_ahb_proc_interrupt = {
1721 + .handler = ar5312_ahb_proc_handler,
1722 + .flags = IRQF_DISABLED,
1723 + .name = "ar5312_ahb_proc_interrupt",
1724 +};
1725 +
1726 +
1727 +static struct irqaction cascade = {
1728 + .handler = no_action,
1729 + .flags = IRQF_DISABLED,
1730 + .name = "cascade",
1731 +};
1732 +
1733 +void __init ar5312_irq_init(void)
1734 +{
1735 + int i;
1736 +
1737 + if (!is_5312())
1738 + return;
1739 +
1740 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1741 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
1742 + int irq = AR531X_MISC_IRQ_BASE + i;
1743 + set_irq_chip_and_handler(irq, &ar5312_misc_intr_controller,
1744 + handle_level_irq);
1745 + }
1746 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1747 + setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
1748 +}
1749 +
1750 +const struct ar231x_gpiodev ar5312_gpiodev;
1751 +
1752 +static u32
1753 +ar5312_gpio_get_output(void)
1754 +{
1755 + u32 reg;
1756 + reg = ~(ar231x_read_reg(AR531X_GPIO_CR));
1757 + reg &= ar5312_gpiodev.valid_mask;
1758 + return reg;
1759 +}
1760 +
1761 +static u32
1762 +ar5312_gpio_set_output(u32 mask, u32 val)
1763 +{
1764 + u32 reg;
1765 +
1766 + reg = ar231x_read_reg(AR531X_GPIO_CR);
1767 + reg |= mask;
1768 + reg &= ~val;
1769 + ar231x_write_reg(AR531X_GPIO_CR, reg);
1770 + return reg;
1771 +}
1772 +
1773 +static u32
1774 +ar5312_gpio_get(void)
1775 +{
1776 + u32 reg;
1777 + reg = ar231x_read_reg(AR531X_GPIO_DI);
1778 + reg &= ar5312_gpiodev.valid_mask;
1779 + return reg;
1780 +}
1781 +
1782 +static u32
1783 +ar5312_gpio_set(u32 mask, u32 value)
1784 +{
1785 + u32 reg;
1786 + reg = ar231x_read_reg(AR531X_GPIO_DO);
1787 + reg &= ~mask;
1788 + reg |= value;
1789 + ar231x_write_reg(AR531X_GPIO_DO, reg);
1790 + return reg;
1791 +}
1792 +
1793 +const struct ar231x_gpiodev ar5312_gpiodev = {
1794 + .valid_mask = (1 << 8) - 1,
1795 + .get_output = ar5312_gpio_get_output,
1796 + .set_output = ar5312_gpio_set_output,
1797 + .get = ar5312_gpio_get,
1798 + .set = ar5312_gpio_set,
1799 +};
1800 +
1801 +static struct physmap_flash_data ar5312_flash_data = {
1802 + .width = 2,
1803 +};
1804 +
1805 +static struct resource ar5312_flash_resource = {
1806 + .start = AR531X_FLASH,
1807 + .end = AR531X_FLASH + 0x800000 - 1,
1808 + .flags = IORESOURCE_MEM,
1809 +};
1810 +
1811 +static struct ar231x_eth ar5312_eth0_data = {
1812 + .reset_base = AR531X_RESET,
1813 + .reset_mac = AR531X_RESET_ENET0,
1814 + .reset_phy = AR531X_RESET_EPHY0,
1815 + .phy_base = KSEG1ADDR(AR531X_ENET0),
1816 + .config = &ar231x_board,
1817 +};
1818 +
1819 +static struct ar231x_eth ar5312_eth1_data = {
1820 + .reset_base = AR531X_RESET,
1821 + .reset_mac = AR531X_RESET_ENET1,
1822 + .reset_phy = AR531X_RESET_EPHY1,
1823 + .phy_base = KSEG1ADDR(AR531X_ENET1),
1824 + .config = &ar231x_board,
1825 +};
1826 +
1827 +static struct platform_device ar5312_physmap_flash = {
1828 + .name = "physmap-flash",
1829 + .id = 0,
1830 + .dev.platform_data = &ar5312_flash_data,
1831 + .resource = &ar5312_flash_resource,
1832 + .num_resources = 1,
1833 +};
1834 +
1835 +#ifdef CONFIG_LEDS_GPIO
1836 +static struct gpio_led ar5312_leds[] = {
1837 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1838 +};
1839 +
1840 +static const struct gpio_led_platform_data ar5312_led_data = {
1841 + .num_leds = ARRAY_SIZE(ar5312_leds),
1842 + .leds = (void *) ar5312_leds,
1843 +};
1844 +
1845 +static struct platform_device ar5312_gpio_leds = {
1846 + .name = "leds-gpio",
1847 + .id = -1,
1848 + .dev.platform_data = (void *) &ar5312_led_data,
1849 +};
1850 +#endif
1851 +
1852 +/*
1853 + * NB: This mapping size is larger than the actual flash size,
1854 + * but this shouldn't be a problem here, because the flash
1855 + * will simply be mapped multiple times.
1856 + */
1857 +static char __init *ar5312_flash_limit(void)
1858 +{
1859 + u32 ctl;
1860 + /*
1861 + * Configure flash bank 0.
1862 + * Assume 8M window size. Flash will be aliased if it's smaller
1863 + */
1864 + ctl = FLASHCTL_E |
1865 + FLASHCTL_AC_8M |
1866 + FLASHCTL_RBLE |
1867 + (0x01 << FLASHCTL_IDCY_S) |
1868 + (0x07 << FLASHCTL_WST1_S) |
1869 + (0x07 << FLASHCTL_WST2_S) |
1870 + (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW);
1871 +
1872 + ar231x_write_reg(AR531X_FLASHCTL0, ctl);
1873 +
1874 + /* Disable other flash banks */
1875 + ar231x_write_reg(AR531X_FLASHCTL1,
1876 + ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
1877 +
1878 + ar231x_write_reg(AR531X_FLASHCTL2,
1879 + ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
1880 +
1881 + return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
1882 +}
1883 +
1884 +int __init ar5312_init_devices(void)
1885 +{
1886 + struct ar231x_boarddata *config;
1887 + u32 fctl = 0;
1888 + const u8 *radio;
1889 + u8 *c;
1890 +
1891 + if (!is_5312())
1892 + return 0;
1893 +
1894 + /* Locate board/radio config data */
1895 + ar231x_find_config(ar5312_flash_limit());
1896 + config = ar231x_board.config;
1897 +
1898 +
1899 + /*
1900 + * Chip IDs and hardware detection for some Atheros
1901 + * models are really broken!
1902 + *
1903 + * Atheros uses a disabled WMAC0 and Silicon ID of AR5312
1904 + * as indication for AR2312, which is otherwise
1905 + * indistinguishable from the real AR5312.
1906 + */
1907 + if (ar231x_board.radio) {
1908 + radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF;
1909 + if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0)
1910 + config->flags |= BD_ISCASPER;
1911 + } else
1912 + radio = NULL;
1913 +
1914 + /* AR2313 has CPU minor rev. 10 */
1915 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1916 + ar231x_devtype = DEV_TYPE_AR2313;
1917 +
1918 + /* AR2312 shares the same Silicon ID as AR5312 */
1919 + else if (config->flags & BD_ISCASPER)
1920 + ar231x_devtype = DEV_TYPE_AR2312;
1921 +
1922 + /* Everything else is probably AR5312 or compatible */
1923 + else
1924 + ar231x_devtype = DEV_TYPE_AR5312;
1925 +
1926 + /* fixup flash width */
1927 + fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW;
1928 + switch (fctl) {
1929 + case FLASHCTL_MWx16:
1930 + ar5312_flash_data.width = 2;
1931 + break;
1932 + case FLASHCTL_MWx8:
1933 + default:
1934 + ar5312_flash_data.width = 1;
1935 + break;
1936 + }
1937 +
1938 + platform_device_register(&ar5312_physmap_flash);
1939 +
1940 +#ifdef CONFIG_LEDS_GPIO
1941 + ar5312_leds[0].gpio = config->sysLedGpio;
1942 + platform_device_register(&ar5312_gpio_leds);
1943 +#endif
1944 +
1945 + /* Fix up MAC addresses if necessary */
1946 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1947 + memcpy(config->enet0_mac, config->enet1_mac, 6);
1948 +
1949 + /* If ENET0 and ENET1 have the same mac address,
1950 + * increment the one from ENET1 */
1951 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1952 + c = config->enet1_mac + 5;
1953 + while ((c >= config->enet1_mac) && !(++(*c)))
1954 + c--;
1955 + }
1956 +
1957 + switch(ar231x_devtype) {
1958 + case DEV_TYPE_AR5312:
1959 + ar5312_eth0_data.macaddr = config->enet0_mac;
1960 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
1961 + AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
1962 +
1963 + ar5312_eth1_data.macaddr = config->enet1_mac;
1964 + ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
1965 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1966 +
1967 + if (!ar231x_board.radio)
1968 + return 0;
1969 +
1970 + if ((*((u32 *) radio) & AR531X_RADIO0_MASK) &&
1971 + (config->flags & BD_WLAN0))
1972 + ar231x_add_wmac(0, AR531X_WLAN0,
1973 + AR5312_IRQ_WLAN0_INTRS);
1974 +
1975 + break;
1976 + /*
1977 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1978 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1979 + */
1980 + case DEV_TYPE_AR2312:
1981 + case DEV_TYPE_AR2313:
1982 + ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
1983 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1984 + ar5312_eth1_data.macaddr = config->enet0_mac;
1985 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
1986 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1987 +
1988 + if (!ar231x_board.radio)
1989 + return 0;
1990 + break;
1991 + default:
1992 + break;
1993 + }
1994 +
1995 + if ((*((u32 *) radio) & AR531X_RADIO1_MASK) &&
1996 + (config->flags & BD_WLAN1))
1997 + ar231x_add_wmac(1, AR531X_WLAN1,
1998 + AR5312_IRQ_WLAN1_INTRS);
1999 +
2000 + return 0;
2001 +}
2002 +
2003 +
2004 +static void ar5312_restart(char *command)
2005 +{
2006 + /* reset the system */
2007 + local_irq_disable();
2008 + while(1) {
2009 + ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
2010 + }
2011 +}
2012 +
2013 +
2014 +/*
2015 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2016 + * to determine the predevisor value.
2017 + */
2018 +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
2019 +
2020 +
2021 +static int __init
2022 +ar5312_cpu_frequency(void)
2023 +{
2024 + unsigned int result;
2025 + unsigned int predivide_mask, predivide_shift;
2026 + unsigned int multiplier_mask, multiplier_shift;
2027 + unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
2028 + unsigned int doubler_mask;
2029 + u16 devid;
2030 +
2031 + /* Trust the bootrom's idea of cpu frequency. */
2032 + if ((result = ar231x_read_reg(AR5312_SCRATCH)))
2033 + return result;
2034 +
2035 + devid = ar231x_read_reg(AR531X_REV);
2036 + devid &= AR531X_REV_MAJ;
2037 + devid >>= AR531X_REV_MAJ_S;
2038 + if (devid == AR531X_REV_MAJ_AR2313) {
2039 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2040 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2041 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2042 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2043 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2044 + } else { /* AR5312 and AR2312 */
2045 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2046 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2047 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2048 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2049 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2050 + }
2051 +
2052 + /*
2053 + * Clocking is derived from a fixed 40MHz input clock.
2054 + *
2055 + * cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
2056 + * sysFreq = cpuFreq / 4 (used for APB clock, serial,
2057 + * flash, Timer, Watchdog Timer)
2058 + *
2059 + * cntFreq = cpuFreq / 2 (use for CPU count/compare)
2060 + *
2061 + * So, for example, with a PLL multiplier of 5, we have
2062 + *
2063 + * cpuFreq = 200MHz
2064 + * sysFreq = 50MHz
2065 + * cntFreq = 100MHz
2066 + *
2067 + * We compute the CPU frequency, based on PLL settings.
2068 + */
2069 +
2070 + clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2071 + preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
2072 + preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
2073 + multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
2074 +
2075 + if (clockCtl1 & doubler_mask) {
2076 + multiplier = multiplier << 1;
2077 + }
2078 + return (40000000 / preDivisor) * multiplier;
2079 +}
2080 +
2081 +static inline int
2082 +ar5312_sys_frequency(void)
2083 +{
2084 + return ar5312_cpu_frequency() / 4;
2085 +}
2086 +
2087 +void __init
2088 +ar5312_time_init(void)
2089 +{
2090 + if (!is_5312())
2091 + return;
2092 +
2093 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2094 +}
2095 +
2096 +
2097 +void __init
2098 +ar5312_prom_init(void)
2099 +{
2100 + u32 memsize, memcfg, bank0AC, bank1AC;
2101 + u32 devid;
2102 +
2103 + if (!is_5312())
2104 + return;
2105 +
2106 + /* Detect memory size */
2107 + memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
2108 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2109 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2110 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
2111 + + (bank1AC ? (1 << (bank1AC+1)) : 0);
2112 + memsize <<= 20;
2113 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2114 +
2115 + devid = ar231x_read_reg(AR531X_REV);
2116 + devid >>= AR531X_REV_WMAC_MIN_S;
2117 + devid &= AR531X_REV_CHIP;
2118 + ar231x_board.devid = (u16) devid;
2119 + ar231x_gpiodev = &ar5312_gpiodev;
2120 +}
2121 +
2122 +void __init
2123 +ar5312_plat_setup(void)
2124 +{
2125 + if (!is_5312())
2126 + return;
2127 +
2128 + /* Clear any lingering AHB errors */
2129 + ar231x_read_reg(AR531X_PROCADDR);
2130 + ar231x_read_reg(AR531X_DMAADDR);
2131 + ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
2132 +
2133 + _machine_restart = ar5312_restart;
2134 + ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
2135 +}
2136 +
2137 --- /dev/null
2138 +++ b/arch/mips/ar231x/ar2315.c
2139 @@ -0,0 +1,658 @@
2140 +/*
2141 + * This file is subject to the terms and conditions of the GNU General Public
2142 + * License. See the file "COPYING" in the main directory of this archive
2143 + * for more details.
2144 + *
2145 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2146 + * Copyright (C) 2006 FON Technology, SL.
2147 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2148 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2149 + */
2150 +
2151 +/*
2152 + * Platform devices for Atheros SoCs
2153 + */
2154 +
2155 +#include <generated/autoconf.h>
2156 +#include <linux/init.h>
2157 +#include <linux/module.h>
2158 +#include <linux/types.h>
2159 +#include <linux/string.h>
2160 +#include <linux/platform_device.h>
2161 +#include <linux/kernel.h>
2162 +#include <linux/reboot.h>
2163 +#include <linux/delay.h>
2164 +#include <linux/leds.h>
2165 +#include <asm/bootinfo.h>
2166 +#include <asm/reboot.h>
2167 +#include <asm/time.h>
2168 +#include <asm/irq.h>
2169 +#include <asm/io.h>
2170 +#include <asm/gpio.h>
2171 +
2172 +#include <ar231x_platform.h>
2173 +#include <ar2315_regs.h>
2174 +#include <ar231x.h>
2175 +#include "devices.h"
2176 +#include "ar2315.h"
2177 +
2178 +static u32 gpiointmask = 0, gpiointval = 0;
2179 +
2180 +static inline void ar2315_gpio_irq(void)
2181 +{
2182 + u32 pend;
2183 + int bit = -1;
2184 +
2185 + /* only do one gpio interrupt at a time */
2186 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2187 +
2188 + if (pend) {
2189 + bit = fls(pend) - 1;
2190 + pend &= ~(1 << bit);
2191 + gpiointval ^= (1 << bit);
2192 + }
2193 +
2194 + if (!pend)
2195 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2196 +
2197 + /* Enable interrupt with edge detection */
2198 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit))
2199 + return;
2200 +
2201 + if (bit >= 0)
2202 + do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
2203 +}
2204 +
2205 +
2206 +/*
2207 + * Called when an interrupt is received, this function
2208 + * determines exactly which interrupt it was, and it
2209 + * invokes the appropriate handler.
2210 + *
2211 + * Implicitly, we also define interrupt priority by
2212 + * choosing which to dispatch first.
2213 + */
2214 +static asmlinkage void
2215 +ar2315_irq_dispatch(void)
2216 +{
2217 + int pending = read_c0_status() & read_c0_cause();
2218 +
2219 + if (pending & CAUSEF_IP3)
2220 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2221 + else if (pending & CAUSEF_IP4)
2222 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2223 + else if (pending & CAUSEF_IP2) {
2224 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
2225 +
2226 + if (misc_intr & AR2315_ISR_SPI)
2227 + do_IRQ(AR531X_MISC_IRQ_SPI);
2228 + else if (misc_intr & AR2315_ISR_TIMER)
2229 + do_IRQ(AR531X_MISC_IRQ_TIMER);
2230 + else if (misc_intr & AR2315_ISR_AHB)
2231 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
2232 + else if (misc_intr & AR2315_ISR_GPIO)
2233 + ar2315_gpio_irq();
2234 + else if (misc_intr & AR2315_ISR_UART0)
2235 + do_IRQ(AR531X_MISC_IRQ_UART0);
2236 + else if (misc_intr & AR2315_ISR_WD)
2237 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
2238 + else
2239 + do_IRQ(AR531X_MISC_IRQ_NONE);
2240 + } else if (pending & CAUSEF_IP7)
2241 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
2242 +}
2243 +
2244 +static void ar2315_set_gpiointmask(int gpio, int level)
2245 +{
2246 + u32 reg;
2247 +
2248 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2249 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2250 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2251 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2252 +}
2253 +
2254 +static void ar2315_gpio_intr_enable(unsigned int irq)
2255 +{
2256 + unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2257 +
2258 + /* Enable interrupt with edge detection */
2259 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio))
2260 + return;
2261 +
2262 + gpiointmask |= (1 << gpio);
2263 + ar2315_set_gpiointmask(gpio, 3);
2264 +}
2265 +
2266 +static unsigned int ar2315_gpio_intr_startup(unsigned int irq)
2267 +{
2268 + unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2269 +
2270 + /* reconfigure GPIO line as input */
2271 + ar231x_mask_reg(AR2315_GPIO_CR, AR2315_GPIO_CR_M(gpio), AR2315_GPIO_CR_I(gpio));
2272 + ar2315_gpio_intr_enable(irq);
2273 + return 0;
2274 +}
2275 +
2276 +static void ar2315_gpio_intr_disable(unsigned int irq)
2277 +{
2278 + unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2279 +
2280 + /* Disable interrupt */
2281 + gpiointmask &= ~(1 << gpio);
2282 + ar2315_set_gpiointmask(gpio, 0);
2283 +}
2284 +
2285 +static void
2286 +ar2315_gpio_intr_end(unsigned int irq)
2287 +{
2288 + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
2289 + ar2315_gpio_intr_enable(irq);
2290 +}
2291 +
2292 +static struct irq_chip ar2315_gpio_intr_controller = {
2293 + .name = "AR2315-GPIO",
2294 + .startup = ar2315_gpio_intr_startup,
2295 + .ack = ar2315_gpio_intr_disable,
2296 + .mask_ack = ar2315_gpio_intr_disable,
2297 + .mask = ar2315_gpio_intr_disable,
2298 + .unmask = ar2315_gpio_intr_enable,
2299 + .end = ar2315_gpio_intr_end,
2300 +};
2301 +
2302 +static void
2303 +ar2315_misc_intr_enable(unsigned int irq)
2304 +{
2305 + unsigned int imr;
2306 +
2307 + imr = ar231x_read_reg(AR2315_IMR);
2308 + switch(irq) {
2309 + case AR531X_MISC_IRQ_SPI:
2310 + imr |= AR2315_ISR_SPI;
2311 + break;
2312 + case AR531X_MISC_IRQ_TIMER:
2313 + imr |= AR2315_ISR_TIMER;
2314 + break;
2315 + case AR531X_MISC_IRQ_AHB_PROC:
2316 + imr |= AR2315_ISR_AHB;
2317 + break;
2318 + case AR531X_MISC_IRQ_GPIO:
2319 + imr |= AR2315_ISR_GPIO;
2320 + break;
2321 + case AR531X_MISC_IRQ_UART0:
2322 + imr |= AR2315_ISR_UART0;
2323 + break;
2324 + case AR531X_MISC_IRQ_WATCHDOG:
2325 + imr |= AR2315_ISR_WD;
2326 + break;
2327 + default:
2328 + break;
2329 + }
2330 + ar231x_write_reg(AR2315_IMR, imr);
2331 +}
2332 +
2333 +static void
2334 +ar2315_misc_intr_disable(unsigned int irq)
2335 +{
2336 + unsigned int imr;
2337 +
2338 + imr = ar231x_read_reg(AR2315_IMR);
2339 + switch(irq) {
2340 + case AR531X_MISC_IRQ_SPI:
2341 + imr &= ~AR2315_ISR_SPI;
2342 + break;
2343 + case AR531X_MISC_IRQ_TIMER:
2344 + imr &= ~AR2315_ISR_TIMER;
2345 + break;
2346 + case AR531X_MISC_IRQ_AHB_PROC:
2347 + imr &= ~AR2315_ISR_AHB;
2348 + break;
2349 + case AR531X_MISC_IRQ_GPIO:
2350 + imr &= ~AR2315_ISR_GPIO;
2351 + break;
2352 + case AR531X_MISC_IRQ_UART0:
2353 + imr &= ~AR2315_ISR_UART0;
2354 + break;
2355 + case AR531X_MISC_IRQ_WATCHDOG:
2356 + imr &= ~AR2315_ISR_WD;
2357 + break;
2358 + default:
2359 + break;
2360 + }
2361 + ar231x_write_reg(AR2315_IMR, imr);
2362 +}
2363 +
2364 +static void
2365 +ar2315_misc_intr_end(unsigned int irq)
2366 +{
2367 + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
2368 + ar2315_misc_intr_enable(irq);
2369 +}
2370 +
2371 +
2372 +static struct irq_chip ar2315_misc_intr_controller = {
2373 + .name = "AR2315-MISC",
2374 + .ack = ar2315_misc_intr_disable,
2375 + .mask_ack = ar2315_misc_intr_disable,
2376 + .mask = ar2315_misc_intr_disable,
2377 + .unmask = ar2315_misc_intr_enable,
2378 + .end = ar2315_misc_intr_end,
2379 +};
2380 +
2381 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2382 +{
2383 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2384 + ar231x_read_reg(AR2315_AHB_ERR1);
2385 +
2386 + printk(KERN_ERR "AHB fatal error\n");
2387 + machine_restart("AHB error"); /* Catastrophic failure */
2388 +
2389 + return IRQ_HANDLED;
2390 +}
2391 +
2392 +static struct irqaction ar2315_ahb_proc_interrupt = {
2393 + .handler = ar2315_ahb_proc_handler,
2394 + .flags = IRQF_DISABLED,
2395 + .name = "ar2315_ahb_proc_interrupt",
2396 +};
2397 +
2398 +static struct irqaction cascade = {
2399 + .handler = no_action,
2400 + .flags = IRQF_DISABLED,
2401 + .name = "cascade",
2402 +};
2403 +
2404 +void
2405 +ar2315_irq_init(void)
2406 +{
2407 + int i;
2408 +
2409 + if (!is_2315())
2410 + return;
2411 +
2412 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2413 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2414 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
2415 + int irq = AR531X_MISC_IRQ_BASE + i;
2416 + set_irq_chip_and_handler(irq, &ar2315_misc_intr_controller,
2417 + handle_level_irq);
2418 + }
2419 + for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
2420 + int irq = AR531X_GPIO_IRQ_BASE + i;
2421 + set_irq_chip_and_handler(irq, &ar2315_gpio_intr_controller,
2422 + handle_level_irq);
2423 + }
2424 + setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
2425 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt);
2426 + setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
2427 +}
2428 +
2429 +const struct ar231x_gpiodev ar2315_gpiodev;
2430 +
2431 +static u32
2432 +ar2315_gpio_get_output(void)
2433 +{
2434 + u32 reg;
2435 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2436 + reg &= ar2315_gpiodev.valid_mask;
2437 + return reg;
2438 +}
2439 +
2440 +static u32
2441 +ar2315_gpio_set_output(u32 mask, u32 val)
2442 +{
2443 + u32 reg;
2444 +
2445 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2446 + reg &= ~mask;
2447 + reg |= val;
2448 + ar231x_write_reg(AR2315_GPIO_CR, reg);
2449 + return reg;
2450 +}
2451 +
2452 +static u32
2453 +ar2315_gpio_get(void)
2454 +{
2455 + u32 reg;
2456 + reg = ar231x_read_reg(AR2315_GPIO_DI);
2457 + reg &= ar2315_gpiodev.valid_mask;
2458 + return reg;
2459 +}
2460 +
2461 +static u32
2462 +ar2315_gpio_set(u32 mask, u32 value)
2463 +{
2464 + u32 reg;
2465 + reg = ar231x_read_reg(AR2315_GPIO_DO);
2466 + reg &= ~mask;
2467 + reg |= value;
2468 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2469 + return reg;
2470 +}
2471 +
2472 +const struct ar231x_gpiodev ar2315_gpiodev = {
2473 + .valid_mask = (1 << 22) - 1,
2474 + .get_output = ar2315_gpio_get_output,
2475 + .set_output = ar2315_gpio_set_output,
2476 + .get = ar2315_gpio_get,
2477 + .set = ar2315_gpio_set,
2478 +};
2479 +
2480 +static struct ar231x_eth ar2315_eth_data = {
2481 + .reset_base = AR2315_RESET,
2482 + .reset_mac = AR2315_RESET_ENET0,
2483 + .reset_phy = AR2315_RESET_EPHY0,
2484 + .phy_base = KSEG1ADDR(AR2315_ENET0),
2485 + .config = &ar231x_board,
2486 +};
2487 +
2488 +static struct resource ar2315_spiflash_res[] = {
2489 + {
2490 + .name = "flash_base",
2491 + .flags = IORESOURCE_MEM,
2492 + .start = KSEG1ADDR(AR2315_SPI_READ),
2493 + .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1,
2494 + },
2495 + {
2496 + .name = "flash_regs",
2497 + .flags = IORESOURCE_MEM,
2498 + .start = 0x11300000,
2499 + .end = 0x11300012,
2500 + },
2501 +};
2502 +
2503 +static struct platform_device ar2315_spiflash = {
2504 + .id = 0,
2505 + .name = "spiflash",
2506 + .resource = ar2315_spiflash_res,
2507 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2508 +};
2509 +
2510 +static struct platform_device ar2315_wdt = {
2511 + .id = 0,
2512 + .name = "ar2315_wdt",
2513 +};
2514 +
2515 +#define SPI_FLASH_CTL 0x00
2516 +#define SPI_FLASH_OPCODE 0x04
2517 +#define SPI_FLASH_DATA 0x08
2518 +
2519 +static inline u32
2520 +spiflash_read_reg(int reg)
2521 +{
2522 + return ar231x_read_reg(AR2315_SPI + reg);
2523 +}
2524 +
2525 +static inline void
2526 +spiflash_write_reg(int reg, u32 data)
2527 +{
2528 + ar231x_write_reg(AR2315_SPI + reg, data);
2529 +}
2530 +
2531 +static u32
2532 +spiflash_wait_status(void)
2533 +{
2534 + u32 reg;
2535 +
2536 + do {
2537 + reg = spiflash_read_reg(SPI_FLASH_CTL);
2538 + } while (reg & SPI_CTL_BUSY);
2539 +
2540 + return reg;
2541 +}
2542 +
2543 +static u8
2544 +spiflash_probe(void)
2545 +{
2546 + u32 reg;
2547 +
2548 + reg = spiflash_wait_status();
2549 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
2550 + reg |= (1 << 4) | 4 | SPI_CTL_START;
2551 +
2552 + spiflash_write_reg(SPI_FLASH_OPCODE, 0xab);
2553 + spiflash_write_reg(SPI_FLASH_CTL, reg);
2554 +
2555 + reg = spiflash_wait_status();
2556 + reg = spiflash_read_reg(SPI_FLASH_DATA);
2557 + reg &= 0xff;
2558 +
2559 + return (u8) reg;
2560 +}
2561 +
2562 +
2563 +#define STM_8MBIT_SIGNATURE 0x13
2564 +#define STM_16MBIT_SIGNATURE 0x14
2565 +#define STM_32MBIT_SIGNATURE 0x15
2566 +#define STM_64MBIT_SIGNATURE 0x16
2567 +#define STM_128MBIT_SIGNATURE 0x17
2568 +
2569 +static u8 __init *
2570 +ar2315_flash_limit(void)
2571 +{
2572 + u32 flash_size = 0;
2573 +
2574 + /* probe the flash chip size */
2575 + switch(spiflash_probe()) {
2576 + case STM_8MBIT_SIGNATURE:
2577 + flash_size = 0x00100000;
2578 + break;
2579 + case STM_16MBIT_SIGNATURE:
2580 + flash_size = 0x00200000;
2581 + break;
2582 + case STM_32MBIT_SIGNATURE:
2583 + flash_size = 0x00400000;
2584 + break;
2585 + case STM_64MBIT_SIGNATURE:
2586 + flash_size = 0x00800000;
2587 + break;
2588 + case STM_128MBIT_SIGNATURE:
2589 + flash_size = 0x01000000;
2590 + break;
2591 + }
2592 +
2593 + ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start +
2594 + flash_size - 1;
2595 + return (u8 *) ar2315_spiflash_res[0].end + 1;
2596 +}
2597 +
2598 +#ifdef CONFIG_LEDS_GPIO
2599 +static struct gpio_led ar2315_leds[6];
2600 +static struct gpio_led_platform_data ar2315_led_data = {
2601 + .leds = (void *) ar2315_leds,
2602 +};
2603 +
2604 +static struct platform_device ar2315_gpio_leds = {
2605 + .name = "leds-gpio",
2606 + .id = -1,
2607 + .dev = {
2608 + .platform_data = (void *) &ar2315_led_data,
2609 + }
2610 +};
2611 +
2612 +static void __init
2613 +ar2315_init_gpio(void)
2614 +{
2615 + static char led_names[6][6];
2616 + int i, led = 0;
2617 +
2618 + ar2315_led_data.num_leds = 0;
2619 + for(i = 1; i < 8; i++)
2620 + {
2621 + if((i == AR2315_RESET_GPIO) ||
2622 + (i == ar231x_board.config->resetConfigGpio))
2623 + continue;
2624 +
2625 + if(i == ar231x_board.config->sysLedGpio)
2626 + strcpy(led_names[led], "wlan");
2627 + else
2628 + sprintf(led_names[led], "gpio%d", i);
2629 +
2630 + ar2315_leds[led].name = led_names[led];
2631 + ar2315_leds[led].gpio = i;
2632 + ar2315_leds[led].active_low = 0;
2633 + led++;
2634 + }
2635 + ar2315_led_data.num_leds = led;
2636 + platform_device_register(&ar2315_gpio_leds);
2637 +}
2638 +#else
2639 +static inline void ar2315_init_gpio(void)
2640 +{
2641 +}
2642 +#endif
2643 +
2644 +int __init
2645 +ar2315_init_devices(void)
2646 +{
2647 + if (!is_2315())
2648 + return 0;
2649 +
2650 + /* Find board configuration */
2651 + ar231x_find_config(ar2315_flash_limit());
2652 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2653 +
2654 + ar2315_init_gpio();
2655 + platform_device_register(&ar2315_wdt);
2656 + platform_device_register(&ar2315_spiflash);
2657 + ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS,
2658 + &ar2315_eth_data);
2659 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2660 +
2661 + return 0;
2662 +}
2663 +
2664 +static void
2665 +ar2315_restart(char *command)
2666 +{
2667 + void (*mips_reset_vec)(void) = (void *) 0xbfc00000;
2668 +
2669 + local_irq_disable();
2670 +
2671 + /* try reset the system via reset control */
2672 + ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM);
2673 +
2674 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
2675 + * give it some time to attempt a gpio based hardware reset
2676 + * (atheros reference design workaround) */
2677 + gpio_direction_output(AR2315_RESET_GPIO, 0);
2678 + mdelay(100);
2679 +
2680 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2681 + * workaround. Attempt to jump to the mips reset location -
2682 + * the boot loader itself might be able to recover the system */
2683 + mips_reset_vec();
2684 +}
2685 +
2686 +
2687 +/*
2688 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2689 + * to determine the predevisor value.
2690 + */
2691 +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
2692 +static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 };
2693 +
2694 +static unsigned int __init
2695 +ar2315_sys_clk(unsigned int clockCtl)
2696 +{
2697 + unsigned int pllcCtrl,cpuDiv;
2698 + unsigned int pllcOut,refdiv,fdiv,divby2;
2699 + unsigned int clkDiv;
2700 +
2701 + pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL);
2702 + refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2703 + refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
2704 + fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2705 + divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2706 + divby2 += 1;
2707 + pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
2708 +
2709 +
2710 + /* clkm input selected */
2711 + switch(clockCtl & CPUCLK_CLK_SEL_M) {
2712 + case 0:
2713 + case 1:
2714 + clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
2715 + break;
2716 + case 2:
2717 + clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
2718 + break;
2719 + default:
2720 + pllcOut = 40000000;
2721 + clkDiv = 1;
2722 + break;
2723 + }
2724 + cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2725 + cpuDiv = cpuDiv * 2 ?: 1;
2726 + return (pllcOut/(clkDiv * cpuDiv));
2727 +}
2728 +
2729 +static inline unsigned int
2730 +ar2315_cpu_frequency(void)
2731 +{
2732 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2733 +}
2734 +
2735 +static inline unsigned int
2736 +ar2315_apb_frequency(void)
2737 +{
2738 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2739 +}
2740 +
2741 +void __init
2742 +ar2315_time_init(void)
2743 +{
2744 + if (!is_2315())
2745 + return;
2746 +
2747 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2748 +}
2749 +
2750 +void __init
2751 +ar2315_prom_init(void)
2752 +{
2753 + u32 memsize, memcfg, devid;
2754 +
2755 + if (!is_2315())
2756 + return;
2757 +
2758 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2759 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2760 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2761 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2762 + memsize <<= 3;
2763 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2764 +
2765 + /* Detect the hardware based on the device ID */
2766 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2767 + switch(devid) {
2768 + case 0x90:
2769 + case 0x91:
2770 + ar231x_devtype = DEV_TYPE_AR2317;
2771 + break;
2772 + default:
2773 + ar231x_devtype = DEV_TYPE_AR2315;
2774 + break;
2775 + }
2776 + ar231x_gpiodev = &ar2315_gpiodev;
2777 + ar231x_board.devid = devid;
2778 +}
2779 +
2780 +void __init
2781 +ar2315_plat_setup(void)
2782 +{
2783 + u32 config;
2784 +
2785 + if (!is_2315())
2786 + return;
2787 +
2788 + /* Clear any lingering AHB errors */
2789 + config = read_c0_config();
2790 + write_c0_config(config & ~0x3);
2791 + ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET);
2792 + ar231x_read_reg(AR2315_AHB_ERR1);
2793 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2794 +
2795 + _machine_restart = ar2315_restart;
2796 + ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency());
2797 +}
2798 --- /dev/null
2799 +++ b/arch/mips/ar231x/ar2315.h
2800 @@ -0,0 +1,37 @@
2801 +#ifndef __AR2315_H
2802 +#define __AR2315_H
2803 +
2804 +#ifdef CONFIG_ATHEROS_AR2315
2805 +
2806 +extern void ar2315_irq_init(void);
2807 +extern int ar2315_init_devices(void);
2808 +extern void ar2315_prom_init(void);
2809 +extern void ar2315_plat_setup(void);
2810 +extern void ar2315_time_init(void);
2811 +
2812 +#else
2813 +
2814 +static inline void ar2315_irq_init(void)
2815 +{
2816 +}
2817 +
2818 +static inline int ar2315_init_devices(void)
2819 +{
2820 + return 0;
2821 +}
2822 +
2823 +static inline void ar2315_prom_init(void)
2824 +{
2825 +}
2826 +
2827 +static inline void ar2315_plat_setup(void)
2828 +{
2829 +}
2830 +
2831 +static inline void ar2315_time_init(void)
2832 +{
2833 +}
2834 +
2835 +#endif
2836 +
2837 +#endif
2838 --- /dev/null
2839 +++ b/arch/mips/ar231x/ar5312.h
2840 @@ -0,0 +1,38 @@
2841 +#ifndef __AR5312_H
2842 +#define __AR5312_H
2843 +
2844 +#ifdef CONFIG_ATHEROS_AR5312
2845 +
2846 +extern void ar5312_irq_init(void);
2847 +extern int ar5312_init_devices(void);
2848 +extern void ar5312_prom_init(void);
2849 +extern void ar5312_plat_setup(void);
2850 +extern void ar5312_time_init(void);
2851 +extern void ar5312_time_init(void);
2852 +
2853 +#else
2854 +
2855 +static inline void ar5312_irq_init(void)
2856 +{
2857 +}
2858 +
2859 +static inline int ar5312_init_devices(void)
2860 +{
2861 + return 0;
2862 +}
2863 +
2864 +static inline void ar5312_prom_init(void)
2865 +{
2866 +}
2867 +
2868 +static inline void ar5312_plat_setup(void)
2869 +{
2870 +}
2871 +
2872 +static inline void ar5312_time_init(void)
2873 +{
2874 +}
2875 +
2876 +#endif
2877 +
2878 +#endif
2879 --- /dev/null
2880 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2881 @@ -0,0 +1,54 @@
2882 +#ifndef __AR531X_H
2883 +#define __AR531X_H
2884 +
2885 +#define AR531X_MISC_IRQ_BASE 0x20
2886 +#define AR531X_GPIO_IRQ_BASE 0x30
2887 +
2888 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2889 +#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0
2890 +#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
2891 +
2892 +/* Miscellaneous interrupts, which share IP6 */
2893 +#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0
2894 +#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1
2895 +#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2
2896 +#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3
2897 +#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4
2898 +#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5
2899 +#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6
2900 +#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7
2901 +#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8
2902 +#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9
2903 +#define AR531X_MISC_IRQ_COUNT 10
2904 +
2905 +/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
2906 +#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0
2907 +#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n
2908 +#define AR531X_GPIO_IRQ_COUNT 22
2909 +
2910 +static inline u32
2911 +ar231x_read_reg(u32 reg)
2912 +{
2913 + return __raw_readl((u32 *) KSEG1ADDR(reg));
2914 +}
2915 +
2916 +static inline void
2917 +ar231x_write_reg(u32 reg, u32 val)
2918 +{
2919 + __raw_writel(val, (u32 *) KSEG1ADDR(reg));
2920 +}
2921 +
2922 +static inline u32
2923 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2924 +{
2925 + u32 ret;
2926 +
2927 + ret = ar231x_read_reg(reg);
2928 + ret &= ~mask;
2929 + ret |= val;
2930 + ar231x_write_reg(reg, ret);
2931 +
2932 + return ret;
2933 +}
2934 +
2935 +#endif
2936 --- /dev/null
2937 +++ b/arch/mips/ar231x/devices.h
2938 @@ -0,0 +1,37 @@
2939 +#ifndef __AR231X_DEVICES_H
2940 +#define __AR231X_DEVICES_H
2941 +
2942 +enum {
2943 + /* handled by ar5312.c */
2944 + DEV_TYPE_AR2312,
2945 + DEV_TYPE_AR2313,
2946 + DEV_TYPE_AR5312,
2947 +
2948 + /* handled by ar2315.c */
2949 + DEV_TYPE_AR2315,
2950 + DEV_TYPE_AR2316,
2951 + DEV_TYPE_AR2317,
2952 +
2953 + DEV_TYPE_UNKNOWN
2954 +};
2955 +
2956 +extern int ar231x_devtype;
2957 +extern struct ar231x_board_config ar231x_board;
2958 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2959 +
2960 +extern int ar231x_find_config(u8 *flash_limit);
2961 +extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk);
2962 +extern int ar231x_add_wmac(int nr, u32 base, int irq);
2963 +extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
2964 +
2965 +static inline bool is_2315(void)
2966 +{
2967 + return (current_cpu_data.cputype == CPU_4KEC);
2968 +}
2969 +
2970 +static inline bool is_5312(void)
2971 +{
2972 + return !is_2315();
2973 +}
2974 +
2975 +#endif
2976 --- /dev/null
2977 +++ b/arch/mips/ar231x/devices.c
2978 @@ -0,0 +1,175 @@
2979 +#include <linux/kernel.h>
2980 +#include <linux/init.h>
2981 +#include <linux/serial.h>
2982 +#include <linux/serial_core.h>
2983 +#include <linux/serial_8250.h>
2984 +#include <linux/platform_device.h>
2985 +#include <ar231x_platform.h>
2986 +#include <ar231x.h>
2987 +#include "devices.h"
2988 +#include "ar5312.h"
2989 +#include "ar2315.h"
2990 +
2991 +struct ar231x_board_config ar231x_board;
2992 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2993 +const struct ar231x_gpiodev *ar231x_gpiodev;
2994 +EXPORT_SYMBOL(ar231x_gpiodev);
2995 +
2996 +static struct resource ar231x_eth0_res[] = {
2997 + {
2998 + .name = "eth0_membase",
2999 + .flags = IORESOURCE_MEM,
3000 + },
3001 + {
3002 + .name = "eth0_irq",
3003 + .flags = IORESOURCE_IRQ,
3004 + }
3005 +};
3006 +
3007 +static struct resource ar231x_eth1_res[] = {
3008 + {
3009 + .name = "eth1_membase",
3010 + .flags = IORESOURCE_MEM,
3011 + },
3012 + {
3013 + .name = "eth1_irq",
3014 + .flags = IORESOURCE_IRQ,
3015 + }
3016 +};
3017 +
3018 +static struct platform_device ar231x_eth[] = {
3019 + {
3020 + .id = 0,
3021 + .name = "ar231x-eth",
3022 + .resource = ar231x_eth0_res,
3023 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
3024 + },
3025 + {
3026 + .id = 1,
3027 + .name = "ar231x-eth",
3028 + .resource = ar231x_eth1_res,
3029 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
3030 + }
3031 +};
3032 +
3033 +static struct resource ar231x_wmac0_res[] = {
3034 + {
3035 + .name = "wmac0_membase",
3036 + .flags = IORESOURCE_MEM,
3037 + },
3038 + {
3039 + .name = "wmac0_irq",
3040 + .flags = IORESOURCE_IRQ,
3041 + }
3042 +};
3043 +
3044 +static struct resource ar231x_wmac1_res[] = {
3045 + {
3046 + .name = "wmac1_membase",
3047 + .flags = IORESOURCE_MEM,
3048 + },
3049 + {
3050 + .name = "wmac1_irq",
3051 + .flags = IORESOURCE_IRQ,
3052 + }
3053 +};
3054 +
3055 +
3056 +static struct platform_device ar231x_wmac[] = {
3057 + {
3058 + .id = 0,
3059 + .name = "ar231x-wmac",
3060 + .resource = ar231x_wmac0_res,
3061 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
3062 + .dev.platform_data = &ar231x_board,
3063 + },
3064 + {
3065 + .id = 1,
3066 + .name = "ar231x-wmac",
3067 + .resource = ar231x_wmac1_res,
3068 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
3069 + .dev.platform_data = &ar231x_board,
3070 + },
3071 +};
3072 +
3073 +static const char *devtype_strings[] = {
3074 + [DEV_TYPE_AR5312] = "Atheros AR5312",
3075 + [DEV_TYPE_AR2312] = "Atheros AR2312",
3076 + [DEV_TYPE_AR2313] = "Atheros AR2313",
3077 + [DEV_TYPE_AR2315] = "Atheros AR2315",
3078 + [DEV_TYPE_AR2316] = "Atheros AR2316",
3079 + [DEV_TYPE_AR2317] = "Atheros AR2317",
3080 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
3081 +};
3082 +
3083 +const char *get_system_type(void)
3084 +{
3085 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
3086 + !devtype_strings[ar231x_devtype])
3087 + return devtype_strings[DEV_TYPE_UNKNOWN];
3088 + return devtype_strings[ar231x_devtype];
3089 +}
3090 +
3091 +
3092 +int __init
3093 +ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
3094 +{
3095 + struct resource *res;
3096 +
3097 + ar231x_eth[nr].dev.platform_data = pdata;
3098 + res = &ar231x_eth[nr].resource[0];
3099 + res->start = base;
3100 + res->end = base + 0x2000 - 1;
3101 + res++;
3102 + res->start = irq;
3103 + res->end = irq;
3104 + return platform_device_register(&ar231x_eth[nr]);
3105 +}
3106 +
3107 +void __init
3108 +ar231x_serial_setup(u32 mapbase, unsigned int uartclk)
3109 +{
3110 + struct uart_port s;
3111 +
3112 + memset(&s, 0, sizeof(s));
3113 +
3114 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3115 + s.iotype = UPIO_MEM;
3116 + s.irq = AR531X_MISC_IRQ_UART0;
3117 + s.regshift = 2;
3118 + s.mapbase = mapbase;
3119 + s.uartclk = uartclk;
3120 + s.membase = (void __iomem *)s.mapbase;
3121 +
3122 + early_serial_setup(&s);
3123 +}
3124 +
3125 +int __init
3126 +ar231x_add_wmac(int nr, u32 base, int irq)
3127 +{
3128 + struct resource *res;
3129 +
3130 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3131 + res = &ar231x_wmac[nr].resource[0];
3132 + res->start = base;
3133 + res->end = base + 0x10000 - 1;
3134 + res++;
3135 + res->start = irq;
3136 + res->end = irq;
3137 + return platform_device_register(&ar231x_wmac[nr]);
3138 +}
3139 +
3140 +static int __init ar231x_register_devices(void)
3141 +{
3142 + static struct resource res = {
3143 + .start = 0xFFFFFFFF,
3144 + };
3145 +
3146 + platform_device_register_simple("GPIODEV", 0, &res, 1);
3147 + ar5312_init_devices();
3148 + ar2315_init_devices();
3149 +
3150 + return 0;
3151 +}
3152 +
3153 +device_initcall(ar231x_register_devices);
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