projects / openwrt / svn-archive / archive.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
atheros: fix includes
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.10 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -138,6 +138,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -838,6 +851,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR5312/AR2312 WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,16 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + select DMA_NONCOHERENT
62 + select CEVT_R4K
63 + select CSRC_R4K
64 + select IRQ_CPU
65 + select SYS_HAS_CPU_MIPS32_R1
66 + select SYS_SUPPORTS_32BIT_KERNEL
67 + select SYS_SUPPORTS_BIG_ENDIAN
68 + default y
69 --- /dev/null
70 +++ b/arch/mips/ar231x/Makefile
71 @@ -0,0 +1,13 @@
72 +#
73 +# This file is subject to the terms and conditions of the GNU General Public
74 +# License. See the file "COPYING" in the main directory of this archive
75 +# for more details.
76 +#
77 +# Copyright (C) 2006 FON Technology, SL.
78 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
79 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
80 +#
81 +
82 +obj-y += board.o prom.o devices.o
83 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
84 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
85 --- /dev/null
86 +++ b/arch/mips/ar231x/board.c
87 @@ -0,0 +1,260 @@
88 +/*
89 + * This file is subject to the terms and conditions of the GNU General Public
90 + * License. See the file "COPYING" in the main directory of this archive
91 + * for more details.
92 + *
93 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
94 + * Copyright (C) 2006 FON Technology, SL.
95 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
96 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
97 + */
98 +
99 +#include <generated/autoconf.h>
100 +#include <linux/init.h>
101 +#include <linux/module.h>
102 +#include <linux/types.h>
103 +#include <linux/string.h>
104 +#include <linux/platform_device.h>
105 +#include <linux/kernel.h>
106 +#include <linux/random.h>
107 +#include <linux/etherdevice.h>
108 +#include <linux/irq.h>
109 +#include <linux/io.h>
110 +#include <asm/irq_cpu.h>
111 +#include <asm/reboot.h>
112 +
113 +#include <ar231x_platform.h>
114 +#include "devices.h"
115 +#include "ar5312.h"
116 +#include "ar2315.h"
117 +
118 +void (*ar231x_irq_dispatch)(void);
119 +
120 +static inline bool
121 +check_radio_magic(u8 *addr)
122 +{
123 + addr += 0x7a; /* offset for flash magic */
124 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5))
125 + return 1;
126 +
127 + return 0;
128 +}
129 +
130 +static inline bool
131 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
132 +{
133 + /* config magic found */
134 + if (*((u32 *)addr) == AR531X_BD_MAGIC)
135 + return 1;
136 +
137 + if (!broken)
138 + return 0;
139 +
140 + if (check_radio_magic(addr + 0xf8))
141 + ar231x_board.radio = addr + 0xf8;
142 + if ((addr < flash_limit + 0x10000) &&
143 + check_radio_magic(addr + 0x10000))
144 + ar231x_board.radio = addr + 0x10000;
145 +
146 + if (ar231x_board.radio) {
147 + /* broken board data detected, use radio data to find the offset,
148 + * user will fix this */
149 + return 1;
150 + }
151 + return 0;
152 +}
153 +
154 +static u8 *
155 +find_board_config(u8 *flash_limit, bool broken)
156 +{
157 + u8 *addr;
158 + int found = 0;
159 +
160 + for (addr = flash_limit - 0x1000;
161 + addr >= flash_limit - 0x30000;
162 + addr -= 0x1000) {
163 +
164 + if (check_board_data(flash_limit, addr, broken)) {
165 + found = 1;
166 + break;
167 + }
168 + }
169 +
170 + if (!found)
171 + addr = NULL;
172 +
173 + return addr;
174 +}
175 +
176 +static u8 *
177 +find_radio_config(u8 *flash_limit, u8 *board_config)
178 +{
179 + int found;
180 + u8 *radio_config;
181 +
182 + /*
183 + * Now find the start of Radio Configuration data, using heuristics:
184 + * Search forward from Board Configuration data by 0x1000 bytes
185 + * at a time until we find non-0xffffffff.
186 + */
187 + found = 0;
188 + for (radio_config = board_config + 0x1000;
189 + (radio_config < flash_limit);
190 + radio_config += 0x1000) {
191 + if ((*(u32 *)radio_config != 0xffffffff) &&
192 + check_radio_magic(radio_config)) {
193 + found = 1;
194 + break;
195 + }
196 + }
197 +
198 + /* AR2316 relocates radio config to new location */
199 + if (!found) {
200 + for (radio_config = board_config + 0xf8;
201 + (radio_config < flash_limit - 0x1000 + 0xf8);
202 + radio_config += 0x1000) {
203 + if ((*(u32 *)radio_config != 0xffffffff) &&
204 + check_radio_magic(radio_config)) {
205 + found = 1;
206 + break;
207 + }
208 + }
209 + }
210 +
211 + if (!found) {
212 + pr_warn("WARNING: Could not find Radio Configuration data\n");
213 + radio_config = 0;
214 + }
215 +
216 + return (u8 *) radio_config;
217 +}
218 +
219 +int __init
220 +ar231x_find_config(u8 *flash_limit)
221 +{
222 + struct ar231x_boarddata *config;
223 + unsigned int rcfg_size;
224 + int broken_boarddata = 0;
225 + u8 *bcfg, *rcfg;
226 + u8 *board_data;
227 + u8 *radio_data;
228 + u8 *mac_addr;
229 + u32 offset;
230 +
231 + ar231x_board.config = NULL;
232 + ar231x_board.radio = NULL;
233 + /* Copy the board and radio data to RAM, because accessing the mapped
234 + * memory of the flash directly after booting is not safe */
235 +
236 + /* Try to find valid board and radio data */
237 + bcfg = find_board_config(flash_limit, false);
238 +
239 + /* If that fails, try to at least find valid radio data */
240 + if (!bcfg) {
241 + bcfg = find_board_config(flash_limit, true);
242 + broken_boarddata = 1;
243 + }
244 +
245 + if (!bcfg) {
246 + pr_warn("WARNING: No board configuration data found!\n");
247 + return -ENODEV;
248 + }
249 +
250 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
251 + ar231x_board.config = (struct ar231x_boarddata *) board_data;
252 + memcpy(board_data, bcfg, 0x100);
253 + if (broken_boarddata) {
254 + pr_warn("WARNING: broken board data detected\n");
255 + config = ar231x_board.config;
256 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
257 + pr_info("Fixing up empty mac addresses\n");
258 + config->reset_config_gpio = 0xffff;
259 + config->sys_led_gpio = 0xffff;
260 + random_ether_addr(config->wlan0_mac);
261 + config->wlan0_mac[0] &= ~0x06;
262 + random_ether_addr(config->enet0_mac);
263 + random_ether_addr(config->enet1_mac);
264 + }
265 + }
266 +
267 +
268 + /* Radio config starts 0x100 bytes after board config, regardless
269 + * of what the physical layout on the flash chip looks like */
270 +
271 + if (ar231x_board.radio)
272 + rcfg = (u8 *) ar231x_board.radio;
273 + else
274 + rcfg = find_radio_config(flash_limit, bcfg);
275 +
276 + if (!rcfg)
277 + return -ENODEV;
278 +
279 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
280 + ar231x_board.radio = radio_data;
281 + offset = radio_data - board_data;
282 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
283 + offset);
284 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
285 + memcpy(radio_data, rcfg, rcfg_size);
286 +
287 + mac_addr = &radio_data[0x1d * 2];
288 + if (is_broadcast_ether_addr(mac_addr)) {
289 + pr_info("Radio MAC is blank; using board-data\n");
290 + memcpy(mac_addr, ar231x_board.config->wlan0_mac, ETH_ALEN);
291 + }
292 +
293 + return 0;
294 +}
295 +
296 +static void
297 +ar231x_halt(void)
298 +{
299 + local_irq_disable();
300 + while (1);
301 +}
302 +
303 +void __init
304 +plat_mem_setup(void)
305 +{
306 + _machine_halt = ar231x_halt;
307 + pm_power_off = ar231x_halt;
308 +
309 + ar5312_plat_setup();
310 + ar2315_plat_setup();
311 +
312 + /* Disable data watchpoints */
313 + write_c0_watchlo0(0);
314 +}
315 +
316 +
317 +asmlinkage void
318 +plat_irq_dispatch(void)
319 +{
320 + ar231x_irq_dispatch();
321 +}
322 +
323 +void __init
324 +plat_time_init(void)
325 +{
326 + ar5312_time_init();
327 + ar2315_time_init();
328 +}
329 +
330 +unsigned int __cpuinit
331 +get_c0_compare_int(void)
332 +{
333 + return CP0_LEGACY_COMPARE_IRQ;
334 +}
335 +
336 +void __init
337 +arch_init_irq(void)
338 +{
339 + clear_c0_status(ST0_IM);
340 + mips_cpu_irq_init();
341 +
342 + /* Initialize interrupt controllers */
343 + ar5312_irq_init();
344 + ar2315_irq_init();
345 +}
346 +
347 +
348 --- /dev/null
349 +++ b/arch/mips/ar231x/prom.c
350 @@ -0,0 +1,37 @@
351 +/*
352 + * This file is subject to the terms and conditions of the GNU General Public
353 + * License. See the file "COPYING" in the main directory of this archive
354 + * for more details.
355 + *
356 + * Copyright MontaVista Software Inc
357 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
358 + * Copyright (C) 2006 FON Technology, SL.
359 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
360 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
361 + */
362 +
363 +/*
364 + * Prom setup file for ar531x
365 + */
366 +
367 +#include <linux/init.h>
368 +#include <generated/autoconf.h>
369 +#include <linux/kernel.h>
370 +#include <linux/string.h>
371 +#include <linux/mm.h>
372 +#include <linux/bootmem.h>
373 +
374 +#include <asm/bootinfo.h>
375 +#include <asm/addrspace.h>
376 +#include "ar5312.h"
377 +#include "ar2315.h"
378 +
379 +void __init prom_init(void)
380 +{
381 + ar5312_prom_init();
382 + ar2315_prom_init();
383 +}
384 +
385 +void __init prom_free_prom_memory(void)
386 +{
387 +}
388 --- /dev/null
389 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
390 @@ -0,0 +1,83 @@
391 +#ifndef __AR531X_PLATFORM_H
392 +#define __AR531X_PLATFORM_H
393 +
394 +/*
395 + * This is board-specific data that is stored in a "fixed" location in flash.
396 + * It is shared across operating systems, so it should not be changed lightly.
397 + * The main reason we need it is in order to extract the ethernet MAC
398 + * address(es).
399 + */
400 +struct ar231x_boarddata {
401 + u32 magic; /* board data is valid */
402 +#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
403 + u16 cksum; /* checksum (starting with BD_REV 2) */
404 + u16 rev; /* revision of this struct */
405 +#define BD_REV 4
406 + char board_name[64]; /* Name of board */
407 + u16 major; /* Board major number */
408 + u16 minor; /* Board minor number */
409 + u32 flags; /* Board configuration */
410 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
411 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
412 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
413 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
414 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
415 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
416 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
417 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
418 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
419 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
420 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
421 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
422 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
423 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
424 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
425 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
426 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
427 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
428 + u16 reset_config_gpio; /* Reset factory GPIO pin */
429 + u16 sys_led_gpio; /* System LED GPIO pin */
430 +
431 + u32 cpu_freq; /* CPU core frequency in Hz */
432 + u32 sys_freq; /* System frequency in Hz */
433 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
434 +
435 + u8 wlan0_mac[6];
436 + u8 enet0_mac[6];
437 + u8 enet1_mac[6];
438 +
439 + u16 pci_id; /* Pseudo PCIID for common code */
440 + u16 mem_cap; /* cap bank1 in MB */
441 +
442 + /* version 3 */
443 + u8 wlan1_mac[6]; /* (ar5212) */
444 +};
445 +
446 +#define BOARD_CONFIG_BUFSZ 0x1000
447 +
448 +/*
449 + * Platform device information for the Wireless MAC
450 + */
451 +struct ar231x_board_config {
452 + u16 devid;
453 +
454 + /* board config data */
455 + struct ar231x_boarddata *config;
456 +
457 + /* radio calibration data */
458 + const char *radio;
459 +};
460 +
461 +/*
462 + * Platform device information for the Ethernet MAC
463 + */
464 +struct ar231x_eth {
465 + u32 reset_base;
466 + u32 reset_mac;
467 + u32 reset_phy;
468 + u32 phy_base;
469 + struct ar231x_board_config *config;
470 + char *macaddr;
471 +};
472 +
473 +#endif /* __AR531X_PLATFORM_H */
474 --- /dev/null
475 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
476 @@ -0,0 +1,84 @@
477 +/*
478 + * Atheros SoC specific CPU feature overrides
479 + *
480 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
481 + *
482 + * This file was derived from: include/asm-mips/cpu-features.h
483 + * Copyright (C) 2003, 2004 Ralf Baechle
484 + * Copyright (C) 2004 Maciej W. Rozycki
485 + *
486 + * This program is free software; you can redistribute it and/or modify it
487 + * under the terms of the GNU General Public License version 2 as published
488 + * by the Free Software Foundation.
489 + *
490 + */
491 +#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
492 +#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
493 +
494 +/*
495 + * The ATHEROS SoCs have MIPS 4Kc/4KEc core.
496 + */
497 +#define cpu_has_tlb 1
498 +#define cpu_has_4kex 1
499 +#define cpu_has_3k_cache 0
500 +#define cpu_has_4k_cache 1
501 +#define cpu_has_tx39_cache 0
502 +#define cpu_has_sb1_cache 0
503 +#define cpu_has_fpu 0
504 +#define cpu_has_32fpr 0
505 +#define cpu_has_counter 1
506 +/* #define cpu_has_watch ? */
507 +/* #define cpu_has_divec ? */
508 +/* #define cpu_has_vce ? */
509 +/* #define cpu_has_cache_cdex_p ? */
510 +/* #define cpu_has_cache_cdex_s ? */
511 +/* #define cpu_has_prefetch ? */
512 +/* #define cpu_has_mcheck ? */
513 +#define cpu_has_ejtag 1
514 +
515 +#if !defined(CONFIG_ATHEROS_AR5312)
516 +# define cpu_has_llsc 1
517 +#else
518 +/*
519 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
520 + * ll/sc instructions.
521 + */
522 +# define cpu_has_llsc 0
523 +#endif
524 +
525 +#define cpu_has_mips16 0
526 +#define cpu_has_mdmx 0
527 +#define cpu_has_mips3d 0
528 +#define cpu_has_smartmips 0
529 +
530 +/* #define cpu_has_vtag_icache ? */
531 +/* #define cpu_has_dc_aliases ? */
532 +/* #define cpu_has_ic_fills_f_dc ? */
533 +/* #define cpu_has_pindexed_dcache ? */
534 +
535 +/* #define cpu_icache_snoops_remote_store ? */
536 +
537 +#define cpu_has_mips32r1 1
538 +
539 +#if !defined(CONFIG_ATHEROS_AR5312)
540 +# define cpu_has_mips32r2 1
541 +#endif
542 +
543 +#define cpu_has_mips64r1 0
544 +#define cpu_has_mips64r2 0
545 +
546 +#define cpu_has_dsp 0
547 +#define cpu_has_mipsmt 0
548 +
549 +/* #define cpu_has_nofpuex ? */
550 +#define cpu_has_64bits 0
551 +#define cpu_has_64bit_zero_reg 0
552 +#define cpu_has_64bit_gp_regs 0
553 +#define cpu_has_64bit_addresses 0
554 +
555 +/* #define cpu_has_inclusive_pcaches ? */
556 +
557 +/* #define cpu_dcache_line_size() ? */
558 +/* #define cpu_icache_line_size() ? */
559 +
560 +#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
561 --- /dev/null
562 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
563 @@ -0,0 +1,76 @@
564 +/*
565 + * This file is subject to the terms and conditions of the GNU General Public
566 + * License. See the file "COPYING" in the main directory of this archive
567 + * for more details.
568 + *
569 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
570 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
571 + *
572 + */
573 +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
574 +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
575 +
576 +#define PCI_DMA_OFFSET 0x20000000
577 +
578 +#include <linux/device.h>
579 +
580 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
581 +{
582 +#ifdef CONFIG_PCI
583 + extern struct bus_type pci_bus_type;
584 +
585 + if (dev && dev->bus == &pci_bus_type)
586 + return PCI_DMA_OFFSET;
587 + else
588 +#endif
589 + return 0;
590 +}
591 +
592 +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
593 +{
594 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
595 +}
596 +
597 +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
598 +{
599 + return page_to_phys(page) + ar231x_dev_offset(dev);
600 +}
601 +
602 +static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
603 + dma_addr_t dma_addr)
604 +{
605 + return dma_addr - ar231x_dev_offset(dev);
606 +}
607 +
608 +static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
609 + size_t size, enum dma_data_direction direction)
610 +{
611 +}
612 +
613 +static inline int plat_dma_supported(struct device *dev, u64 mask)
614 +{
615 + return 1;
616 +}
617 +
618 +static inline void plat_extra_sync_for_device(struct device *dev)
619 +{
620 + return;
621 +}
622 +
623 +static inline int plat_dma_mapping_error(struct device *dev,
624 + dma_addr_t dma_addr)
625 +{
626 + return 0;
627 +}
628 +
629 +static inline int plat_device_is_coherent(struct device *dev)
630 +{
631 +#ifdef CONFIG_DMA_COHERENT
632 + return 1;
633 +#endif
634 +#ifdef CONFIG_DMA_NONCOHERENT
635 + return 0;
636 +#endif
637 +}
638 +
639 +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
640 --- /dev/null
641 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
642 @@ -0,0 +1,30 @@
643 +#ifndef _ATHEROS_GPIO_H_
644 +#define _ATHEROS_GPIO_H_
645 +
646 +#include <ar231x.h>
647 +
648 +#define gpio_get_value __gpio_get_value
649 +#define gpio_set_value __gpio_set_value
650 +#define gpio_cansleep __gpio_cansleep
651 +
652 +/*
653 + * Wrappers for the generic GPIO layer
654 + */
655 +
656 +/* not sure if these are used? */
657 +
658 +/* Returns IRQ to attach for gpio. Unchecked function */
659 +static inline int gpio_to_irq(unsigned gpio)
660 +{
661 + return AR531X_GPIO_IRQ(gpio);
662 +}
663 +
664 +/* Returns gpio for IRQ attached. Unchecked function */
665 +static inline int irq_to_gpio(unsigned irq)
666 +{
667 + return irq - AR531X_GPIO_IRQ(0);
668 +}
669 +
670 +#include <asm-generic/gpio.h> /* cansleep wrappers */
671 +
672 +#endif
673 --- /dev/null
674 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
675 @@ -0,0 +1,6 @@
676 +#ifndef __AR531X_RESET_H
677 +#define __AR531X_RESET_H
678 +
679 +void ar531x_disable_reset_button(void);
680 +
681 +#endif /* __AR531X_RESET_H */
682 --- /dev/null
683 +++ b/arch/mips/include/asm/mach-ar231x/war.h
684 @@ -0,0 +1,25 @@
685 +/*
686 + * This file is subject to the terms and conditions of the GNU General Public
687 + * License. See the file "COPYING" in the main directory of this archive
688 + * for more details.
689 + *
690 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
691 + */
692 +#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H
693 +#define __ASM_MIPS_MACH_ATHEROS_WAR_H
694 +
695 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
696 +#define R4600_V1_HIT_CACHEOP_WAR 0
697 +#define R4600_V2_HIT_CACHEOP_WAR 0
698 +#define R5432_CP0_INTERRUPT_WAR 0
699 +#define BCM1250_M3_WAR 0
700 +#define SIBYTE_1956_WAR 0
701 +#define MIPS4K_ICACHE_REFILL_WAR 0
702 +#define MIPS_CACHE_SYNC_WAR 0
703 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
704 +#define RM9000_CDEX_SMP_WAR 0
705 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
706 +#define R10000_LLSC_WAR 0
707 +#define MIPS34K_MISSED_ITLB_WAR 0
708 +
709 +#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
710 --- /dev/null
711 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
712 @@ -0,0 +1,580 @@
713 +/*
714 + * Register definitions for AR2315+
715 + *
716 + * This file is subject to the terms and conditions of the GNU General Public
717 + * License. See the file "COPYING" in the main directory of this archive
718 + * for more details.
719 + *
720 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
721 + * Copyright (C) 2006 FON Technology, SL.
722 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
723 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
724 + */
725 +
726 +#ifndef __AR2315_REG_H
727 +#define __AR2315_REG_H
728 +
729 +/*
730 + * IRQs
731 + */
732 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
733 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
734 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
735 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
736 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
737 +
738 +/*
739 + * Address map
740 + */
741 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
742 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
743 +#define AR2315_PCI 0x10100000 /* PCI MMR */
744 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
745 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
746 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
747 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
748 +#define AR2315_UART0 0x11100003 /* UART MMR */
749 +#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */
750 +#define AR2315_PCIEXT 0x80000000 /* pci external */
751 +
752 +/*
753 + * Reset Register
754 + */
755 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
756 +
757 +#define AR2315_RESET_COLD_AHB 0x00000001
758 +#define AR2315_RESET_COLD_APB 0x00000002
759 +#define AR2315_RESET_COLD_CPU 0x00000004
760 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
761 +#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */
762 +#define AR2317_RESET_SYSTEM 0x00000010
763 +
764 +
765 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
766 +
767 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
768 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */
769 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
770 +#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
771 +#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */
772 +#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
773 +#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
774 +#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */
775 +#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
776 +#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */
777 +#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
778 +#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */
779 +
780 +/*
781 + * AHB master arbitration control
782 + */
783 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
784 +
785 +#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
786 +#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
787 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
788 +#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */
789 +#define AR2315_ARB_PCI 0x00000010 /* PCI */
790 +#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
791 +#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */
792 +
793 +/*
794 + * Config Register
795 + */
796 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
797 +
798 +#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */
799 +#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
800 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
801 +#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
802 +#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */
803 +#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
804 +#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
805 +
806 +#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
807 +#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
808 +#define AR2315_CONFIG_PCIAHB 0x00000800
809 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
810 +#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
811 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
812 +#define AR2315_CONFIG_CPU_PCI 0x00020000
813 +#define AR2315_CONFIG_CPU_MMR 0x00040000
814 +#define AR2315_CONFIG_BIG 0x00000400
815 +
816 +
817 +/*
818 + * NMI control
819 + */
820 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
821 +
822 +#define AR2315_NMI_EN 1
823 +
824 +/*
825 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
826 + */
827 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
828 +
829 +#define AR2315_REV_MAJ 0x00f0
830 +#define AR2315_REV_MAJ_S 4
831 +#define AR2315_REV_MIN 0x000f
832 +#define AR2315_REV_MIN_S 0
833 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
834 +
835 +/*
836 + * Interface Enable
837 + */
838 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
839 +
840 +#define AR2315_IF_MASK 0x00000007
841 +#define AR2315_IF_DISABLED 0
842 +#define AR2315_IF_PCI 1
843 +#define AR2315_IF_TS_LOCAL 2
844 +#define AR2315_IF_ALL 3 /* only for emulation with separate pins */
845 +#define AR2315_IF_LOCAL_HOST 0x00000008
846 +#define AR2315_IF_PCI_HOST 0x00000010
847 +#define AR2315_IF_PCI_INTR 0x00000020
848 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
849 +#define AR2315_IF_PCI_CLK_INPUT 0
850 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
851 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
852 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
853 +#define AR2315_IF_PCI_CLK_SHIFT 16
854 +
855 +/*
856 + * APB Interrupt control
857 + */
858 +
859 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
860 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
861 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
862 +
863 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
864 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
865 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
866 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
867 +#define AR2315_ISR_APB 0x0010 /* APB error */
868 +#define AR2315_ISR_TIMER 0x0020 /* timer */
869 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
870 +#define AR2315_ISR_WD 0x0080 /* watchdog */
871 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
872 +
873 +#define AR2315_GISR_MISC 0x0001
874 +#define AR2315_GISR_WLAN0 0x0002
875 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
876 +#define AR2315_GISR_LOCALPCI 0x0008
877 +#define AR2315_GISR_WMACPOLL 0x0010
878 +#define AR2315_GISR_TIMER 0x0020
879 +#define AR2315_GISR_ETHERNET 0x0040
880 +
881 +/*
882 + * Interrupt routing from IO to the processor IP bits
883 + * Define our inter mask and level
884 + */
885 +#define AR2315_INTR_MISCIO SR_IBIT3
886 +#define AR2315_INTR_WLAN0 SR_IBIT4
887 +#define AR2315_INTR_ENET0 SR_IBIT5
888 +#define AR2315_INTR_LOCALPCI SR_IBIT6
889 +#define AR2315_INTR_WMACPOLL SR_IBIT7
890 +#define AR2315_INTR_COMPARE SR_IBIT8
891 +
892 +/*
893 + * Timers
894 + */
895 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
896 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
897 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
898 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
899 +
900 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
901 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
902 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
903 +
904 +/*
905 + * CPU Performance Counters
906 + */
907 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
908 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
909 +
910 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
911 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
912 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
913 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
914 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
915 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
916 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
917 +
918 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
919 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
920 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
921 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
922 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
923 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
924 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
925 +
926 +/*
927 + * AHB Error Reporting.
928 + */
929 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
930 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
931 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
932 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
933 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
934 +
935 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
936 + /* write 1 to clear all bits in ERR0 */
937 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
938 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
939 +
940 +#define AR2315_PROCERR_HMAST 0x0000000f
941 +#define AR2315_PROCERR_HMAST_DFLT 0
942 +#define AR2315_PROCERR_HMAST_WMAC 1
943 +#define AR2315_PROCERR_HMAST_ENET 2
944 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
945 +#define AR2315_PROCERR_HMAST_LOCAL 4
946 +#define AR2315_PROCERR_HMAST_CPU 5
947 +#define AR2315_PROCERR_HMAST_PCITGT 6
948 +
949 +#define AR2315_PROCERR_HMAST_S 0
950 +#define AR2315_PROCERR_HWRITE 0x00000010
951 +#define AR2315_PROCERR_HSIZE 0x00000060
952 +#define AR2315_PROCERR_HSIZE_S 5
953 +#define AR2315_PROCERR_HTRANS 0x00000180
954 +#define AR2315_PROCERR_HTRANS_S 7
955 +#define AR2315_PROCERR_HBURST 0x00000e00
956 +#define AR2315_PROCERR_HBURST_S 9
957 +
958 +/*
959 + * Clock Control
960 + */
961 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
962 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
963 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
964 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
965 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
966 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
967 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
968 +
969 +/* PLLc Control fields */
970 +#define PLLC_REF_DIV_M 0x00000003
971 +#define PLLC_REF_DIV_S 0
972 +#define PLLC_FDBACK_DIV_M 0x0000007C
973 +#define PLLC_FDBACK_DIV_S 2
974 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
975 +#define PLLC_ADD_FDBACK_DIV_S 7
976 +#define PLLC_CLKC_DIV_M 0x0001c000
977 +#define PLLC_CLKC_DIV_S 14
978 +#define PLLC_CLKM_DIV_M 0x00700000
979 +#define PLLC_CLKM_DIV_S 20
980 +
981 +/* CPU CLK Control fields */
982 +#define CPUCLK_CLK_SEL_M 0x00000003
983 +#define CPUCLK_CLK_SEL_S 0
984 +#define CPUCLK_CLK_DIV_M 0x0000000c
985 +#define CPUCLK_CLK_DIV_S 2
986 +
987 +/* AMBA CLK Control fields */
988 +#define AMBACLK_CLK_SEL_M 0x00000003
989 +#define AMBACLK_CLK_SEL_S 0
990 +#define AMBACLK_CLK_DIV_M 0x0000000c
991 +#define AMBACLK_CLK_DIV_S 2
992 +
993 +/*
994 + * GPIO
995 + */
996 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
997 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
998 +#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
999 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1000 +
1001 +#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1002 +#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
1003 +#define AR2315_GPIO_CR_I(x) (0) /* input */
1004 +
1005 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1006 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1007 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1008 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1009 +
1010 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */
1011 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1012 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1013 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1014 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1015 +
1016 +#define AR2315_RESET_GPIO 5
1017 +#define AR2315_NUM_GPIO 22
1018 +
1019 +/*
1020 + * PCI Clock Control
1021 + */
1022 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1023 +
1024 +#define AR2315_PCICLK_INPUT_M 0x3
1025 +#define AR2315_PCICLK_INPUT_S 0
1026 +
1027 +#define AR2315_PCICLK_PLLC_CLKM 0
1028 +#define AR2315_PCICLK_PLLC_CLKM1 1
1029 +#define AR2315_PCICLK_PLLC_CLKC 2
1030 +#define AR2315_PCICLK_REF_CLK 3
1031 +
1032 +#define AR2315_PCICLK_DIV_M 0xc
1033 +#define AR2315_PCICLK_DIV_S 2
1034 +
1035 +#define AR2315_PCICLK_IN_FREQ 0
1036 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1037 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1038 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1039 +
1040 +/*
1041 + * Observation Control Register
1042 + */
1043 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1044 +#define OCR_GPIO0_IRIN 0x0040
1045 +#define OCR_GPIO1_IROUT 0x0080
1046 +#define OCR_GPIO3_RXCLR 0x0200
1047 +
1048 +/*
1049 + * General Clock Control
1050 + */
1051 +
1052 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1053 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1054 +#define MISCCLK_PROCREFCLK 0x00000002
1055 +
1056 +/*
1057 + * SDRAM Controller
1058 + * - No read or write buffers are included.
1059 + */
1060 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1061 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1062 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1063 +
1064 +#define SDRAM_DATA_WIDTH_M 0x00006000
1065 +#define SDRAM_DATA_WIDTH_S 13
1066 +
1067 +#define SDRAM_COL_WIDTH_M 0x00001E00
1068 +#define SDRAM_COL_WIDTH_S 9
1069 +
1070 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1071 +#define SDRAM_ROW_WIDTH_S 5
1072 +
1073 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1074 +#define SDRAM_BANKADDR_BITS_S 3
1075 +
1076 +/*
1077 + * SPI Flash Interface Registers
1078 + */
1079 +
1080 +#define AR2315_SPI_CTL (AR2315_SPI + 0x00)
1081 +#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04)
1082 +#define AR2315_SPI_DATA (AR2315_SPI + 0x08)
1083 +
1084 +#define SPI_CTL_START 0x00000100
1085 +#define SPI_CTL_BUSY 0x00010000
1086 +#define SPI_CTL_TXCNT_MASK 0x0000000f
1087 +#define SPI_CTL_RXCNT_MASK 0x000000f0
1088 +#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
1089 +#define SPI_CTL_SIZE_MASK 0x00060000
1090 +
1091 +#define SPI_CTL_CLK_SEL_MASK 0x03000000
1092 +#define SPI_OPCODE_MASK 0x000000ff
1093 +
1094 +/*
1095 + * PCI Bus Interface Registers
1096 + */
1097 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1098 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1099 +
1100 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1101 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1102 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1103 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1104 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1105 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1106 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1107 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1108 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1109 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1110 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1111 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1112 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */
1113 +
1114 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1115 +
1116 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1117 +
1118 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1119 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1120 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1121 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1122 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1123 +
1124 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1125 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1126 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1127 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1128 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1129 +
1130 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1131 +
1132 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1133 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1134 +
1135 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1136 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1137 +
1138 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1139 +
1140 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1141 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1142 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1143 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1144 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1145 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1146 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1147 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1148 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1149 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1150 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1151 +#define AR2315_PCI_EXT_INT 0x02000000
1152 +#define AR2315_PCI_ABORT_INT 0x04000000
1153 +
1154 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1155 +
1156 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1157 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1158 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1159 +
1160 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1161 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1162 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1163 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1164 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1165 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1166 +
1167 +
1168 +/*
1169 + * Local Bus Interface Registers
1170 + */
1171 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1172 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1173 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1174 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1175 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1176 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1177 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1178 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1179 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1180 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1181 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1182 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1183 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1184 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1185 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1186 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1187 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1188 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1189 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1190 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1191 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1192 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1193 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1194 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1195 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1196 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1197 +
1198 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1199 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1200 +
1201 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1202 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1203 +
1204 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1205 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1206 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1207 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1208 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1209 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1210 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1211 +#define AR2315_LBM_TIMEOUT_SHFT 7
1212 +#define AR2315_LBM_PORTMUX 0x07000000
1213 +
1214 +
1215 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1216 +
1217 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1218 +#define AR2315_LB_TXEN_0 0x01
1219 +#define AR2315_LB_TXEN_1 0x02
1220 +#define AR2315_LB_TXEN_2 0x04
1221 +#define AR2315_LB_TXEN_3 0x08
1222 +
1223 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1224 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1225 +
1226 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1227 +#define AR2315_LB_RXEN 0x01
1228 +
1229 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1230 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1231 +
1232 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1233 +#define AR2315_INT_TX_DESC 0x0001
1234 +#define AR2315_INT_TX_OK 0x0002
1235 +#define AR2315_INT_TX_ERR 0x0004
1236 +#define AR2315_INT_TX_EOF 0x0008
1237 +#define AR2315_INT_RX_DESC 0x0010
1238 +#define AR2315_INT_RX_OK 0x0020
1239 +#define AR2315_INT_RX_ERR 0x0040
1240 +#define AR2315_INT_RX_EOF 0x0080
1241 +#define AR2315_INT_TX_TRUNC 0x0100
1242 +#define AR2315_INT_TX_STARVE 0x0200
1243 +#define AR2315_INT_LB_TIMEOUT 0x0400
1244 +#define AR2315_INT_LB_ERR 0x0800
1245 +#define AR2315_INT_MBOX_WR 0x1000
1246 +#define AR2315_INT_MBOX_RD 0x2000
1247 +
1248 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1249 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1250 +
1251 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1252 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1253 +
1254 +/*
1255 + * IR Interface Registers
1256 + */
1257 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1258 +
1259 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1260 +
1261 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1262 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1263 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1264 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */
1265 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1266 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */
1267 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1268 +
1269 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1270 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1271 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1272 +
1273 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1274 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */
1275 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */
1276 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1277 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */
1278 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */
1279 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */
1280 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */
1281 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */
1282 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */
1283 +
1284 +#define HOST_PCI_DEV_ID 3
1285 +#define HOST_PCI_MBAR0 0x10000000
1286 +#define HOST_PCI_MBAR1 0x20000000
1287 +#define HOST_PCI_MBAR2 0x30000000
1288 +
1289 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1290 +#define PCI_DEVICE_MEM_SPACE 0x800000
1291 +
1292 +#endif /* __AR2315_REG_H */
1293 --- /dev/null
1294 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1295 @@ -0,0 +1,232 @@
1296 +/*
1297 + * This file is subject to the terms and conditions of the GNU General Public
1298 + * License. See the file "COPYING" in the main directory of this archive
1299 + * for more details.
1300 + *
1301 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1302 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1303 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1304 + */
1305 +
1306 +#ifndef AR5312_H
1307 +#define AR5312_H
1308 +
1309 +#include <asm/addrspace.h>
1310 +
1311 +/*
1312 + * IRQs
1313 + */
1314 +
1315 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1316 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1317 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1318 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1319 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1320 +
1321 +
1322 +/* Address Map */
1323 +#define AR531X_WLAN0 0x18000000
1324 +#define AR531X_WLAN1 0x18500000
1325 +#define AR531X_ENET0 0x18100000
1326 +#define AR531X_ENET1 0x18200000
1327 +#define AR531X_SDRAMCTL 0x18300000
1328 +#define AR531X_FLASHCTL 0x18400000
1329 +#define AR531X_APBBASE 0x1c000000
1330 +#define AR531X_FLASH 0x1e000000
1331 +#define AR531X_UART0 0xbc000003 /* UART MMR */
1332 +
1333 +/*
1334 + * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
1335 + * should be considered available. The AR5312 supports 2 enet MACS,
1336 + * even though many reference boards only actually use 1 of them
1337 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1338 + * The AR2312 supports 1 enet MAC.
1339 + */
1340 +#define AR531X_NUM_ENET_MAC 2
1341 +
1342 +/*
1343 + * Need these defines to determine true number of ethernet MACs
1344 + */
1345 +#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1346 +#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1347 +#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1348 +
1349 +/*
1350 + * AR531X_NUM_WMAC defines the number of Wireless MACs that\
1351 + * should be considered available.
1352 + */
1353 +#define AR531X_NUM_WMAC 2
1354 +
1355 +/* Reset/Timer Block Address Map */
1356 +#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
1357 +#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
1358 +#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
1359 +#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
1360 +#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
1361 +#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
1362 +#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
1363 +#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
1364 +#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
1365 +#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
1366 +#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
1367 +#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
1368 +#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
1369 +#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
1370 +#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
1371 +
1372 +/* AR531X_WD_CTRL register bit field definitions */
1373 +#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
1374 +#define AR531X_WD_CTRL_NMI 0x0001
1375 +#define AR531X_WD_CTRL_RESET 0x0002
1376 +
1377 +/* AR531X_ISR register bit field definitions */
1378 +#define AR531X_ISR_NONE 0x0000
1379 +#define AR531X_ISR_TIMER 0x0001
1380 +#define AR531X_ISR_AHBPROC 0x0002
1381 +#define AR531X_ISR_AHBDMA 0x0004
1382 +#define AR531X_ISR_GPIO 0x0008
1383 +#define AR531X_ISR_UART0 0x0010
1384 +#define AR531X_ISR_UART0DMA 0x0020
1385 +#define AR531X_ISR_WD 0x0040
1386 +#define AR531X_ISR_LOCAL 0x0080
1387 +
1388 +/* AR531X_RESET register bit field definitions */
1389 +#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
1390 +#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
1391 +#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1392 +#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1393 +#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1394 +#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1395 +#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1396 +#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1397 +#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1398 +#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1399 +#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1400 +#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1401 +#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1402 +#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
1403 +#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1404 +#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1405 +#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1406 +#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1407 +
1408 +#define AR531X_RESET_WMAC0_BITS \
1409 + (AR531X_RESET_WLAN0 |\
1410 + AR531X_RESET_WARM_WLAN0_MAC |\
1411 + AR531X_RESET_WARM_WLAN0_BB)
1412 +
1413 +#define AR531X_RESERT_WMAC1_BITS \
1414 + (AR531X_RESET_WLAN1 |\
1415 + AR531X_RESET_WARM_WLAN1_MAC |\
1416 + AR531X_RESET_WARM_WLAN1_BB)
1417 +
1418 +/* AR5312_CLOCKCTL1 register bit field definitions */
1419 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1420 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1421 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1422 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1423 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1424 +
1425 +/* Valid for AR5312 and AR2312 */
1426 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1427 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1428 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1429 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1430 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1431 +
1432 +/* Valid for AR2313 */
1433 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1434 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1435 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1436 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1437 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1438 +
1439 +
1440 +/* AR531X_ENABLE register bit field definitions */
1441 +#define AR531X_ENABLE_WLAN0 0x0001
1442 +#define AR531X_ENABLE_ENET0 0x0002
1443 +#define AR531X_ENABLE_ENET1 0x0004
1444 +#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1445 +#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1446 +#define AR531X_ENABLE_WLAN1 \
1447 + (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA)
1448 +
1449 +/* AR531X_REV register bit field definitions */
1450 +#define AR531X_REV_WMAC_MAJ 0xf000
1451 +#define AR531X_REV_WMAC_MAJ_S 12
1452 +#define AR531X_REV_WMAC_MIN 0x0f00
1453 +#define AR531X_REV_WMAC_MIN_S 8
1454 +#define AR531X_REV_MAJ 0x00f0
1455 +#define AR531X_REV_MAJ_S 4
1456 +#define AR531X_REV_MIN 0x000f
1457 +#define AR531X_REV_MIN_S 0
1458 +#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
1459 +
1460 +/* Major revision numbers, bits 7..4 of Revision ID register */
1461 +#define AR531X_REV_MAJ_AR5312 0x4
1462 +#define AR531X_REV_MAJ_AR2313 0x5
1463 +
1464 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1465 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1466 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1467 +
1468 +/* AR531X_FLASHCTL register bit field definitions */
1469 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1470 +#define FLASHCTL_IDCY_S 0
1471 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1472 +#define FLASHCTL_WST1_S 5
1473 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1474 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1475 +#define FLASHCTL_WST2_S 11
1476 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1477 +#define FLASHCTL_AC_S 16
1478 +#define FLASHCTL_AC_128K 0x00000000
1479 +#define FLASHCTL_AC_256K 0x00010000
1480 +#define FLASHCTL_AC_512K 0x00020000
1481 +#define FLASHCTL_AC_1M 0x00030000
1482 +#define FLASHCTL_AC_2M 0x00040000
1483 +#define FLASHCTL_AC_4M 0x00050000
1484 +#define FLASHCTL_AC_8M 0x00060000
1485 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1486 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1487 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1488 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1489 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1490 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1491 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1492 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1493 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1494 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1495 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1496 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1497 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1498 +
1499 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1500 +#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
1501 +#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
1502 +#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
1503 +
1504 +/* ARM SDRAM Controller -- just enough to determine memory size */
1505 +#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
1506 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1507 +#define MEM_CFG1_AC0_S 8
1508 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1509 +#define MEM_CFG1_AC1_S 12
1510 +
1511 +/* GPIO Address Map */
1512 +#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
1513 +#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
1514 +#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
1515 +#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
1516 +
1517 +/* GPIO Control Register bit field definitions */
1518 +#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1519 +#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1520 +#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1521 +#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
1522 +#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1523 +#define AR531X_NUM_GPIO 8
1524 +
1525 +
1526 +#endif
1527 +
1528 --- /dev/null
1529 +++ b/arch/mips/ar231x/ar5312.c
1530 @@ -0,0 +1,579 @@
1531 +/*
1532 + * This file is subject to the terms and conditions of the GNU General Public
1533 + * License. See the file "COPYING" in the main directory of this archive
1534 + * for more details.
1535 + *
1536 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1537 + * Copyright (C) 2006 FON Technology, SL.
1538 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1539 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1540 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1541 + */
1542 +
1543 +/*
1544 + * Platform devices for Atheros SoCs
1545 + */
1546 +
1547 +#include <generated/autoconf.h>
1548 +#include <linux/init.h>
1549 +#include <linux/module.h>
1550 +#include <linux/types.h>
1551 +#include <linux/string.h>
1552 +#include <linux/mtd/physmap.h>
1553 +#include <linux/platform_device.h>
1554 +#include <linux/kernel.h>
1555 +#include <linux/reboot.h>
1556 +#include <linux/leds.h>
1557 +#include <linux/gpio.h>
1558 +#include <asm/bootinfo.h>
1559 +#include <asm/reboot.h>
1560 +#include <asm/time.h>
1561 +#include <linux/irq.h>
1562 +#include <linux/io.h>
1563 +
1564 +#include <ar231x_platform.h>
1565 +#include <ar5312_regs.h>
1566 +#include <ar231x.h>
1567 +#include "devices.h"
1568 +#include "ar5312.h"
1569 +
1570 +static void
1571 +ar5312_misc_irq_dispatch(void)
1572 +{
1573 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR);
1574 +
1575 + if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
1576 + do_IRQ(AR531X_MISC_IRQ_TIMER);
1577 + (void)ar231x_read_reg(AR531X_TIMER);
1578 + } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC)
1579 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1580 + else if ((ar231x_misc_intrs & AR531X_ISR_UART0))
1581 + do_IRQ(AR531X_MISC_IRQ_UART0);
1582 + else if (ar231x_misc_intrs & AR531X_ISR_WD)
1583 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1584 + else
1585 + do_IRQ(AR531X_MISC_IRQ_NONE);
1586 +}
1587 +
1588 +static asmlinkage void
1589 +ar5312_irq_dispatch(void)
1590 +{
1591 + int pending = read_c0_status() & read_c0_cause();
1592 +
1593 + if (pending & CAUSEF_IP2)
1594 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1595 + else if (pending & CAUSEF_IP3)
1596 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1597 + else if (pending & CAUSEF_IP4)
1598 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1599 + else if (pending & CAUSEF_IP5)
1600 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1601 + else if (pending & CAUSEF_IP6)
1602 + ar5312_misc_irq_dispatch();
1603 + else if (pending & CAUSEF_IP7)
1604 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
1605 +}
1606 +
1607 +
1608 +/* Enable the specified AR531X_MISC_IRQ interrupt */
1609 +static void
1610 +ar5312_misc_intr_enable(struct irq_data *d)
1611 +{
1612 + unsigned int imr;
1613 +
1614 + imr = ar231x_read_reg(AR531X_IMR);
1615 + imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
1616 + ar231x_write_reg(AR531X_IMR, imr);
1617 +}
1618 +
1619 +/* Disable the specified AR531X_MISC_IRQ interrupt */
1620 +static void
1621 +ar5312_misc_intr_disable(struct irq_data *d)
1622 +{
1623 + unsigned int imr;
1624 +
1625 + imr = ar231x_read_reg(AR531X_IMR);
1626 + imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
1627 + ar231x_write_reg(AR531X_IMR, imr);
1628 + ar231x_read_reg(AR531X_IMR); /* flush write buffer */
1629 +}
1630 +
1631 +static struct irq_chip ar5312_misc_intr_controller = {
1632 + .irq_mask = ar5312_misc_intr_disable,
1633 + .irq_unmask = ar5312_misc_intr_enable,
1634 +};
1635 +
1636 +
1637 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1638 +{
1639 + u32 proc1 = ar231x_read_reg(AR531X_PROC1);
1640 + u32 proc_addr = ar231x_read_reg(AR531X_PROCADDR); /* clears error */
1641 + u32 dma1 = ar231x_read_reg(AR531X_DMA1);
1642 + u32 dma_addr = ar231x_read_reg(AR531X_DMAADDR); /* clears error */
1643 +
1644 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x "
1645 + "DMAADDR=0x%8.8x DMA1=0x%8.8x\n", proc_addr, proc1, dma_addr,
1646 + dma1);
1647 +
1648 + machine_restart("AHB error"); /* Catastrophic failure */
1649 + return IRQ_HANDLED;
1650 +}
1651 +
1652 +
1653 +static struct irqaction ar5312_ahb_proc_interrupt = {
1654 + .handler = ar5312_ahb_proc_handler,
1655 + .name = "ar5312_ahb_proc_interrupt",
1656 +};
1657 +
1658 +
1659 +static struct irqaction cascade = {
1660 + .handler = no_action,
1661 + .name = "cascade",
1662 +};
1663 +
1664 +void __init ar5312_irq_init(void)
1665 +{
1666 + int i;
1667 +
1668 + if (!is_5312())
1669 + return;
1670 +
1671 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1672 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
1673 + int irq = AR531X_MISC_IRQ_BASE + i;
1674 + irq_set_chip_and_handler(irq, &ar5312_misc_intr_controller,
1675 + handle_level_irq);
1676 + }
1677 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1678 + setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
1679 +}
1680 +
1681 +static u32
1682 +ar5312_gpio_set_output(u32 mask, u32 val)
1683 +{
1684 + u32 reg;
1685 +
1686 + reg = ar231x_read_reg(AR531X_GPIO_CR);
1687 + reg |= mask;
1688 + reg &= ~val;
1689 + ar231x_write_reg(AR531X_GPIO_CR, reg);
1690 + return reg;
1691 +}
1692 +
1693 +static u32
1694 +ar5312_gpio_get(u32 valid_mask)
1695 +{
1696 + u32 reg;
1697 + reg = ar231x_read_reg(AR531X_GPIO_DI);
1698 + reg &= valid_mask;
1699 + return reg;
1700 +}
1701 +
1702 +static u32
1703 +ar5312_gpio_set(u32 mask, u32 value)
1704 +{
1705 + u32 reg;
1706 + reg = ar231x_read_reg(AR531X_GPIO_DO);
1707 + reg &= ~mask;
1708 + reg |= value;
1709 + ar231x_write_reg(AR531X_GPIO_DO, reg);
1710 + return reg;
1711 +}
1712 +
1713 +/*
1714 + * gpiolib implementations. Original mask based methods preserved
1715 + */
1716 +static int
1717 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1718 +{
1719 + struct ar231x_gpio_chip *gpch =
1720 + container_of(chip, struct ar231x_gpio_chip, chip);
1721 + u32 mask = 1 << gpio;
1722 + u32 rett;
1723 + if (!(gpch->valid_mask & mask))
1724 + return 0;
1725 + rett = ar5312_gpio_get(gpch->valid_mask);
1726 + return !!(rett & mask);
1727 +}
1728 +
1729 +static void
1730 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1731 +{
1732 + struct ar231x_gpio_chip *gpch =
1733 + container_of(chip, struct ar231x_gpio_chip, chip);
1734 + u32 mask = 1 << gpio;
1735 + if (!(gpch->valid_mask & mask))
1736 + return;
1737 + ar5312_gpio_set(mask, (!!value) * mask);
1738 +}
1739 +
1740 +static int
1741 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1742 +{
1743 + struct ar231x_gpio_chip *gpch =
1744 + container_of(chip, struct ar231x_gpio_chip, chip);
1745 + u32 mask = 1 << gpio;
1746 + if (!(gpch->valid_mask & mask))
1747 + return -ENXIO;
1748 + ar5312_gpio_set_output(mask, 0);
1749 + return 0;
1750 +}
1751 +static int
1752 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1753 +{
1754 + struct ar231x_gpio_chip *gpch =
1755 + container_of(chip, struct ar231x_gpio_chip, chip);
1756 + u32 mask = 1 << gpio;
1757 + if (!(gpch->valid_mask & mask))
1758 + return -ENXIO;
1759 + ar5312_gpio_set_output(mask, mask);
1760 + ar5312_gpio_set(mask, (!!value) * mask);
1761 + return 0;
1762 +}
1763 +
1764 +static struct ar231x_gpio_chip ar5312_gpio_chip = {
1765 + .valid_mask = (1 << 22) - 1,
1766 + .chip = {
1767 + .label = "ar5312-gpio",
1768 + .direction_input = ar5312_gpio_direction_input,
1769 + .direction_output = ar5312_gpio_direction_output,
1770 + .set = ar5312_gpio_set_value,
1771 + .get = ar5312_gpio_get_value,
1772 + .base = 0,
1773 + .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
1774 + }
1775 +};
1776 +
1777 +/* end of gpiolib */
1778 +
1779 +static struct physmap_flash_data ar5312_flash_data = {
1780 + .width = 2,
1781 +};
1782 +
1783 +static struct resource ar5312_flash_resource = {
1784 + .start = AR531X_FLASH,
1785 + .end = AR531X_FLASH + 0x800000 - 1,
1786 + .flags = IORESOURCE_MEM,
1787 +};
1788 +
1789 +static struct ar231x_eth ar5312_eth0_data = {
1790 + .reset_base = AR531X_RESET,
1791 + .reset_mac = AR531X_RESET_ENET0,
1792 + .reset_phy = AR531X_RESET_EPHY0,
1793 + .phy_base = KSEG1ADDR(AR531X_ENET0),
1794 + .config = &ar231x_board,
1795 +};
1796 +
1797 +static struct ar231x_eth ar5312_eth1_data = {
1798 + .reset_base = AR531X_RESET,
1799 + .reset_mac = AR531X_RESET_ENET1,
1800 + .reset_phy = AR531X_RESET_EPHY1,
1801 + .phy_base = KSEG1ADDR(AR531X_ENET1),
1802 + .config = &ar231x_board,
1803 +};
1804 +
1805 +static struct platform_device ar5312_physmap_flash = {
1806 + .name = "physmap-flash",
1807 + .id = 0,
1808 + .dev.platform_data = &ar5312_flash_data,
1809 + .resource = &ar5312_flash_resource,
1810 + .num_resources = 1,
1811 +};
1812 +
1813 +#ifdef CONFIG_LEDS_GPIO
1814 +static struct gpio_led ar5312_leds[] = {
1815 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1816 +};
1817 +
1818 +static const struct gpio_led_platform_data ar5312_led_data = {
1819 + .num_leds = ARRAY_SIZE(ar5312_leds),
1820 + .leds = (void *) ar5312_leds,
1821 +};
1822 +
1823 +static struct platform_device ar5312_gpio_leds = {
1824 + .name = "leds-gpio",
1825 + .id = -1,
1826 + .dev.platform_data = (void *) &ar5312_led_data,
1827 +};
1828 +#endif
1829 +
1830 +/*
1831 + * NB: This mapping size is larger than the actual flash size,
1832 + * but this shouldn't be a problem here, because the flash
1833 + * will simply be mapped multiple times.
1834 + */
1835 +static char __init *ar5312_flash_limit(void)
1836 +{
1837 + u32 ctl;
1838 + /*
1839 + * Configure flash bank 0.
1840 + * Assume 8M window size. Flash will be aliased if it's smaller
1841 + */
1842 + ctl = FLASHCTL_E |
1843 + FLASHCTL_AC_8M |
1844 + FLASHCTL_RBLE |
1845 + (0x01 << FLASHCTL_IDCY_S) |
1846 + (0x07 << FLASHCTL_WST1_S) |
1847 + (0x07 << FLASHCTL_WST2_S) |
1848 + (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW);
1849 +
1850 + ar231x_write_reg(AR531X_FLASHCTL0, ctl);
1851 +
1852 + /* Disable other flash banks */
1853 + ar231x_write_reg(AR531X_FLASHCTL1,
1854 + ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
1855 +
1856 + ar231x_write_reg(AR531X_FLASHCTL2,
1857 + ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
1858 +
1859 + return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
1860 +}
1861 +
1862 +int __init ar5312_init_devices(void)
1863 +{
1864 + struct ar231x_boarddata *config;
1865 + u32 fctl = 0;
1866 + u8 *c;
1867 +
1868 + if (!is_5312())
1869 + return 0;
1870 +
1871 + /* Locate board/radio config data */
1872 + ar231x_find_config(ar5312_flash_limit());
1873 + config = ar231x_board.config;
1874 +
1875 + /* AR2313 has CPU minor rev. 10 */
1876 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1877 + ar231x_devtype = DEV_TYPE_AR2313;
1878 +
1879 + /* AR2312 shares the same Silicon ID as AR5312 */
1880 + else if (config->flags & BD_ISCASPER)
1881 + ar231x_devtype = DEV_TYPE_AR2312;
1882 +
1883 + /* Everything else is probably AR5312 or compatible */
1884 + else
1885 + ar231x_devtype = DEV_TYPE_AR5312;
1886 +
1887 + /* fixup flash width */
1888 + fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW;
1889 + switch (fctl) {
1890 + case FLASHCTL_MWx16:
1891 + ar5312_flash_data.width = 2;
1892 + break;
1893 + case FLASHCTL_MWx8:
1894 + default:
1895 + ar5312_flash_data.width = 1;
1896 + break;
1897 + }
1898 +
1899 + platform_device_register(&ar5312_physmap_flash);
1900 +
1901 +#ifdef CONFIG_LEDS_GPIO
1902 + ar5312_leds[0].gpio = config->sys_led_gpio;
1903 + platform_device_register(&ar5312_gpio_leds);
1904 +#endif
1905 +
1906 + /* Fix up MAC addresses if necessary */
1907 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1908 + memcpy(config->enet0_mac, config->enet1_mac, 6);
1909 +
1910 + /* If ENET0 and ENET1 have the same mac address,
1911 + * increment the one from ENET1 */
1912 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1913 + c = config->enet1_mac + 5;
1914 + while ((c >= config->enet1_mac) && !(++(*c)))
1915 + c--;
1916 + }
1917 +
1918 + switch(ar231x_devtype) {
1919 + case DEV_TYPE_AR5312:
1920 + ar5312_eth0_data.macaddr = config->enet0_mac;
1921 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
1922 + AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
1923 +
1924 + ar5312_eth1_data.macaddr = config->enet1_mac;
1925 + ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
1926 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1927 +
1928 + if (!ar231x_board.radio)
1929 + return 0;
1930 +
1931 + if (!(config->flags & BD_WLAN0))
1932 + break;
1933 +
1934 + ar231x_add_wmac(0, AR531X_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1935 + break;
1936 + /*
1937 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1938 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1939 + */
1940 + case DEV_TYPE_AR2312:
1941 + case DEV_TYPE_AR2313:
1942 + ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
1943 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1944 + ar5312_eth1_data.macaddr = config->enet0_mac;
1945 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
1946 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1947 +
1948 + if (!ar231x_board.radio)
1949 + return 0;
1950 + break;
1951 + default:
1952 + break;
1953 + }
1954 +
1955 + if (config->flags & BD_WLAN1)
1956 + ar231x_add_wmac(1, AR531X_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1957 +
1958 + return 0;
1959 +}
1960 +
1961 +
1962 +static void ar5312_restart(char *command)
1963 +{
1964 + /* reset the system */
1965 + local_irq_disable();
1966 + while (1)
1967 + ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
1968 +}
1969 +
1970 +
1971 +/*
1972 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1973 + * to determine the predevisor value.
1974 + */
1975 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1976 +
1977 +
1978 +static int __init
1979 +ar5312_cpu_frequency(void)
1980 +{
1981 + unsigned int scratch;
1982 + unsigned int predivide_mask, predivide_shift;
1983 + unsigned int multiplier_mask, multiplier_shift;
1984 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1985 + unsigned int doubler_mask;
1986 + u16 devid;
1987 +
1988 + /* Trust the bootrom's idea of cpu frequency. */
1989 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1990 + if (scratch)
1991 + return scratch;
1992 +
1993 + devid = ar231x_read_reg(AR531X_REV);
1994 + devid &= AR531X_REV_MAJ;
1995 + devid >>= AR531X_REV_MAJ_S;
1996 + if (devid == AR531X_REV_MAJ_AR2313) {
1997 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1998 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1999 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2000 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2001 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2002 + } else { /* AR5312 and AR2312 */
2003 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2004 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2005 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2006 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2007 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2008 + }
2009 +
2010 + /*
2011 + * Clocking is derived from a fixed 40MHz input clock.
2012 + *
2013 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
2014 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
2015 + * flash, Timer, Watchdog Timer)
2016 + *
2017 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
2018 + *
2019 + * So, for example, with a PLL multiplier of 5, we have
2020 + *
2021 + * cpu_freq = 200MHz
2022 + * sys_freq = 50MHz
2023 + * cnt_freq = 100MHz
2024 + *
2025 + * We compute the CPU frequency, based on PLL settings.
2026 + */
2027 +
2028 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2029 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
2030 + predivisor = clockctl1_predivide_table[predivide_select];
2031 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
2032 +
2033 + if (clock_ctl1 & doubler_mask)
2034 + multiplier = multiplier << 1;
2035 +
2036 + return (40000000 / predivisor) * multiplier;
2037 +}
2038 +
2039 +static inline int
2040 +ar5312_sys_frequency(void)
2041 +{
2042 + return ar5312_cpu_frequency() / 4;
2043 +}
2044 +
2045 +void __init
2046 +ar5312_time_init(void)
2047 +{
2048 + if (!is_5312())
2049 + return;
2050 +
2051 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2052 +}
2053 +
2054 +int __init
2055 +ar5312_gpio_init(void)
2056 +{
2057 + int ret;
2058 + struct ar231x_gpio_chip *gpch;
2059 + gpch = &ar5312_gpio_chip;
2060 + ret = gpiochip_add(&gpch->chip);
2061 + if (ret) {
2062 + pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
2063 + return ret;
2064 + }
2065 + pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
2066 + gpch->chip.ngpio);
2067 + return ret;
2068 +}
2069 +
2070 +void __init
2071 +ar5312_prom_init(void)
2072 +{
2073 + u32 memsize, memcfg, bank0AC, bank1AC;
2074 + u32 devid;
2075 +
2076 + if (!is_5312())
2077 + return;
2078 +
2079 + /* Detect memory size */
2080 + memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
2081 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2082 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2083 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
2084 + + (bank1AC ? (1 << (bank1AC+1)) : 0);
2085 + memsize <<= 20;
2086 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2087 +
2088 + devid = ar231x_read_reg(AR531X_REV);
2089 + devid >>= AR531X_REV_WMAC_MIN_S;
2090 + devid &= AR531X_REV_CHIP;
2091 + ar231x_board.devid = (u16) devid;
2092 + ar5312_gpio_init();
2093 +}
2094 +
2095 +void __init
2096 +ar5312_plat_setup(void)
2097 +{
2098 + if (!is_5312())
2099 + return;
2100 +
2101 + /* Clear any lingering AHB errors */
2102 + ar231x_read_reg(AR531X_PROCADDR);
2103 + ar231x_read_reg(AR531X_DMAADDR);
2104 + ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
2105 +
2106 + _machine_restart = ar5312_restart;
2107 + ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
2108 +}
2109 +
2110 --- /dev/null
2111 +++ b/arch/mips/ar231x/ar2315.c
2112 @@ -0,0 +1,691 @@
2113 +/*
2114 + * This file is subject to the terms and conditions of the GNU General Public
2115 + * License. See the file "COPYING" in the main directory of this archive
2116 + * for more details.
2117 + *
2118 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2119 + * Copyright (C) 2006 FON Technology, SL.
2120 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2121 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2122 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2123 + */
2124 +
2125 +/*
2126 + * Platform devices for Atheros SoCs
2127 + */
2128 +
2129 +#include <generated/autoconf.h>
2130 +#include <linux/init.h>
2131 +#include <linux/module.h>
2132 +#include <linux/types.h>
2133 +#include <linux/string.h>
2134 +#include <linux/platform_device.h>
2135 +#include <linux/kernel.h>
2136 +#include <linux/reboot.h>
2137 +#include <linux/delay.h>
2138 +#include <linux/leds.h>
2139 +#include <linux/gpio.h>
2140 +#include <asm/bootinfo.h>
2141 +#include <asm/reboot.h>
2142 +#include <asm/time.h>
2143 +#include <linux/irq.h>
2144 +#include <linux/io.h>
2145 +
2146 +#include <ar231x_platform.h>
2147 +#include <ar2315_regs.h>
2148 +#include <ar231x.h>
2149 +#include "devices.h"
2150 +#include "ar2315.h"
2151 +
2152 +static u32 gpiointmask, gpiointval;
2153 +
2154 +static inline void ar2315_gpio_irq(void)
2155 +{
2156 + u32 pend;
2157 + int bit = -1;
2158 +
2159 + /* only do one gpio interrupt at a time */
2160 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2161 +
2162 + if (pend) {
2163 + bit = fls(pend) - 1;
2164 + pend &= ~(1 << bit);
2165 + gpiointval ^= (1 << bit);
2166 + }
2167 +
2168 + if (!pend)
2169 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2170 +
2171 + /* Enable interrupt with edge detection */
2172 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit))
2173 + return;
2174 +
2175 + if (bit >= 0)
2176 + do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
2177 +}
2178 +
2179 +
2180 +/*
2181 + * Called when an interrupt is received, this function
2182 + * determines exactly which interrupt it was, and it
2183 + * invokes the appropriate handler.
2184 + *
2185 + * Implicitly, we also define interrupt priority by
2186 + * choosing which to dispatch first.
2187 + */
2188 +static asmlinkage void
2189 +ar2315_irq_dispatch(void)
2190 +{
2191 + int pending = read_c0_status() & read_c0_cause();
2192 +
2193 + if (pending & CAUSEF_IP3)
2194 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2195 + else if (pending & CAUSEF_IP4)
2196 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2197 + else if (pending & CAUSEF_IP2) {
2198 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
2199 +
2200 + if (misc_intr & AR2315_ISR_SPI)
2201 + do_IRQ(AR531X_MISC_IRQ_SPI);
2202 + else if (misc_intr & AR2315_ISR_TIMER)
2203 + do_IRQ(AR531X_MISC_IRQ_TIMER);
2204 + else if (misc_intr & AR2315_ISR_AHB)
2205 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
2206 + else if (misc_intr & AR2315_ISR_GPIO)
2207 + ar2315_gpio_irq();
2208 + else if (misc_intr & AR2315_ISR_UART0)
2209 + do_IRQ(AR531X_MISC_IRQ_UART0);
2210 + else if (misc_intr & AR2315_ISR_WD)
2211 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
2212 + else
2213 + do_IRQ(AR531X_MISC_IRQ_NONE);
2214 + } else if (pending & CAUSEF_IP7)
2215 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
2216 +}
2217 +
2218 +static void ar2315_set_gpiointmask(int gpio, int level)
2219 +{
2220 + u32 reg;
2221 +
2222 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2223 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2224 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2225 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2226 +}
2227 +
2228 +static void ar2315_gpio_intr_enable(struct irq_data *d)
2229 +{
2230 + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
2231 +
2232 + /* Enable interrupt with edge detection */
2233 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio))
2234 + return;
2235 +
2236 + gpiointmask |= (1 << gpio);
2237 + ar2315_set_gpiointmask(gpio, 3);
2238 +}
2239 +
2240 +static void ar2315_gpio_intr_disable(struct irq_data *d)
2241 +{
2242 + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
2243 +
2244 + /* Disable interrupt */
2245 + gpiointmask &= ~(1 << gpio);
2246 + ar2315_set_gpiointmask(gpio, 0);
2247 +}
2248 +
2249 +static struct irq_chip ar2315_gpio_intr_controller = {
2250 + .irq_mask = ar2315_gpio_intr_disable,
2251 + .irq_unmask = ar2315_gpio_intr_enable,
2252 +};
2253 +
2254 +static void
2255 +ar2315_misc_intr_enable(struct irq_data *d)
2256 +{
2257 + unsigned int imr;
2258 +
2259 + imr = ar231x_read_reg(AR2315_IMR);
2260 + switch(d->irq) {
2261 + case AR531X_MISC_IRQ_SPI:
2262 + imr |= AR2315_ISR_SPI;
2263 + break;
2264 + case AR531X_MISC_IRQ_TIMER:
2265 + imr |= AR2315_ISR_TIMER;
2266 + break;
2267 + case AR531X_MISC_IRQ_AHB_PROC:
2268 + imr |= AR2315_ISR_AHB;
2269 + break;
2270 + case AR531X_MISC_IRQ_GPIO:
2271 + imr |= AR2315_ISR_GPIO;
2272 + break;
2273 + case AR531X_MISC_IRQ_UART0:
2274 + imr |= AR2315_ISR_UART0;
2275 + break;
2276 + case AR531X_MISC_IRQ_WATCHDOG:
2277 + imr |= AR2315_ISR_WD;
2278 + break;
2279 + default:
2280 + break;
2281 + }
2282 + ar231x_write_reg(AR2315_IMR, imr);
2283 +}
2284 +
2285 +static void
2286 +ar2315_misc_intr_disable(struct irq_data *d)
2287 +{
2288 + unsigned int imr;
2289 +
2290 + imr = ar231x_read_reg(AR2315_IMR);
2291 + switch(d->irq) {
2292 + case AR531X_MISC_IRQ_SPI:
2293 + imr &= ~AR2315_ISR_SPI;
2294 + break;
2295 + case AR531X_MISC_IRQ_TIMER:
2296 + imr &= ~AR2315_ISR_TIMER;
2297 + break;
2298 + case AR531X_MISC_IRQ_AHB_PROC:
2299 + imr &= ~AR2315_ISR_AHB;
2300 + break;
2301 + case AR531X_MISC_IRQ_GPIO:
2302 + imr &= ~AR2315_ISR_GPIO;
2303 + break;
2304 + case AR531X_MISC_IRQ_UART0:
2305 + imr &= ~AR2315_ISR_UART0;
2306 + break;
2307 + case AR531X_MISC_IRQ_WATCHDOG:
2308 + imr &= ~AR2315_ISR_WD;
2309 + break;
2310 + default:
2311 + break;
2312 + }
2313 + ar231x_write_reg(AR2315_IMR, imr);
2314 +}
2315 +
2316 +static struct irq_chip ar2315_misc_intr_controller = {
2317 + .irq_mask = ar2315_misc_intr_disable,
2318 + .irq_unmask = ar2315_misc_intr_enable,
2319 +};
2320 +
2321 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2322 +{
2323 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2324 + ar231x_read_reg(AR2315_AHB_ERR1);
2325 +
2326 + pr_emerg("AHB fatal error\n");
2327 + machine_restart("AHB error"); /* Catastrophic failure */
2328 +
2329 + return IRQ_HANDLED;
2330 +}
2331 +
2332 +static struct irqaction ar2315_ahb_proc_interrupt = {
2333 + .handler = ar2315_ahb_proc_handler,
2334 + .name = "ar2315_ahb_proc_interrupt",
2335 +};
2336 +
2337 +static struct irqaction cascade = {
2338 + .handler = no_action,
2339 + .name = "cascade",
2340 +};
2341 +
2342 +void
2343 +ar2315_irq_init(void)
2344 +{
2345 + int i;
2346 +
2347 + if (!is_2315())
2348 + return;
2349 +
2350 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2351 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2352 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
2353 + int irq = AR531X_MISC_IRQ_BASE + i;
2354 + irq_set_chip_and_handler(irq, &ar2315_misc_intr_controller,
2355 + handle_level_irq);
2356 + }
2357 + for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
2358 + int irq = AR531X_GPIO_IRQ_BASE + i;
2359 + irq_set_chip_and_handler(irq, &ar2315_gpio_intr_controller,
2360 + handle_level_irq);
2361 + }
2362 + setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
2363 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt);
2364 + setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
2365 +}
2366 +
2367 +static u32
2368 +ar2315_gpio_set_output(u32 mask, u32 val)
2369 +{
2370 + u32 reg;
2371 +
2372 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2373 + reg &= ~mask;
2374 + reg |= val;
2375 + ar231x_write_reg(AR2315_GPIO_CR, reg);
2376 + return reg;
2377 +}
2378 +
2379 +static u32
2380 +ar2315_gpio_get(u32 valid_mask)
2381 +{
2382 + u32 reg;
2383 + reg = ar231x_read_reg(AR2315_GPIO_DI);
2384 + reg &= valid_mask;
2385 + return reg;
2386 +}
2387 +
2388 +static u32
2389 +ar2315_gpio_set(u32 mask, u32 value)
2390 +{
2391 + u32 reg;
2392 + reg = ar231x_read_reg(AR2315_GPIO_DO);
2393 + reg &= ~mask;
2394 + reg |= value;
2395 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2396 + return reg;
2397 +}
2398 +
2399 +/*
2400 + * gpiolib implementation. Original legacy mask based methods
2401 + * preserved for now.
2402 + */
2403 +static int
2404 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2405 +{
2406 + struct ar231x_gpio_chip *gpch =
2407 + container_of(chip, struct ar231x_gpio_chip, chip);
2408 + u32 mask = 1 << gpio;
2409 + u32 rett;
2410 + if (!(gpch->valid_mask & mask))
2411 + return 0;
2412 + rett = ar2315_gpio_get(gpch->valid_mask); /* legacy code */
2413 + return !!(rett & mask);
2414 +}
2415 +
2416 +static void
2417 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2418 +{
2419 + struct ar231x_gpio_chip *gpch =
2420 + container_of(chip, struct ar231x_gpio_chip, chip);
2421 + u32 mask = 1 << gpio;
2422 + if (!(gpch->valid_mask & mask))
2423 + return;
2424 + ar2315_gpio_set(mask, (!!value) * mask); /* legacy */
2425 +}
2426 +
2427 +static int
2428 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2429 +{
2430 + struct ar231x_gpio_chip *gpch =
2431 + container_of(chip, struct ar231x_gpio_chip, chip);
2432 + u32 mask = 1 << gpio;
2433 + if (!(gpch->valid_mask & mask))
2434 + return -ENXIO;
2435 + ar2315_gpio_set_output(mask, 0); /* legacy */
2436 + return 0;
2437 +}
2438 +
2439 +static int
2440 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2441 +{
2442 + struct ar231x_gpio_chip *gpch =
2443 + container_of(chip, struct ar231x_gpio_chip, chip);
2444 + u32 mask = 1 << gpio;
2445 + if (!(gpch->valid_mask & mask))
2446 + return -ENXIO;
2447 + ar2315_gpio_set_output(mask, mask); /* both legacy */
2448 + ar2315_gpio_set(mask, (!!value) * mask);
2449 + return 0;
2450 +}
2451 +
2452 +static struct ar231x_gpio_chip ar2315_gpio_chip = {
2453 + .valid_mask = (1 << 22) - 1,
2454 + .chip = {
2455 + .label = "ar2315-gpio",
2456 + .direction_input = ar2315_gpio_direction_input,
2457 + .direction_output = ar2315_gpio_direction_output,
2458 + .set = ar2315_gpio_set_value,
2459 + .get = ar2315_gpio_get_value,
2460 + .base = 0,
2461 + .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
2462 + }
2463 +};
2464 +
2465 +/* end of gpiolib */
2466 +
2467 +
2468 +static struct ar231x_eth ar2315_eth_data = {
2469 + .reset_base = AR2315_RESET,
2470 + .reset_mac = AR2315_RESET_ENET0,
2471 + .reset_phy = AR2315_RESET_EPHY0,
2472 + .phy_base = KSEG1ADDR(AR2315_ENET0),
2473 + .config = &ar231x_board,
2474 +};
2475 +
2476 +static struct resource ar2315_spiflash_res[] = {
2477 + {
2478 + .name = "flash_base",
2479 + .flags = IORESOURCE_MEM,
2480 + .start = KSEG1ADDR(AR2315_SPI_READ),
2481 + .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1,
2482 + },
2483 + {
2484 + .name = "flash_regs",
2485 + .flags = IORESOURCE_MEM,
2486 + .start = 0x11300000,
2487 + .end = 0x11300012,
2488 + },
2489 +};
2490 +
2491 +static struct platform_device ar2315_spiflash = {
2492 + .id = 0,
2493 + .name = "spiflash",
2494 + .resource = ar2315_spiflash_res,
2495 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2496 +};
2497 +
2498 +static struct platform_device ar2315_wdt = {
2499 + .id = 0,
2500 + .name = "ar2315_wdt",
2501 +};
2502 +
2503 +#define SPI_FLASH_CTL 0x00
2504 +#define SPI_FLASH_OPCODE 0x04
2505 +#define SPI_FLASH_DATA 0x08
2506 +
2507 +static inline u32
2508 +spiflash_read_reg(int reg)
2509 +{
2510 + return ar231x_read_reg(AR2315_SPI + reg);
2511 +}
2512 +
2513 +static inline void
2514 +spiflash_write_reg(int reg, u32 data)
2515 +{
2516 + ar231x_write_reg(AR2315_SPI + reg, data);
2517 +}
2518 +
2519 +static u32
2520 +spiflash_wait_status(void)
2521 +{
2522 + u32 reg;
2523 +
2524 + do {
2525 + reg = spiflash_read_reg(SPI_FLASH_CTL);
2526 + } while (reg & SPI_CTL_BUSY);
2527 +
2528 + return reg;
2529 +}
2530 +
2531 +static u8
2532 +spiflash_probe(void)
2533 +{
2534 + u32 reg;
2535 +
2536 + reg = spiflash_wait_status();
2537 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
2538 + reg |= (1 << 4) | 4 | SPI_CTL_START;
2539 +
2540 + spiflash_write_reg(SPI_FLASH_OPCODE, 0xab);
2541 + spiflash_write_reg(SPI_FLASH_CTL, reg);
2542 +
2543 + reg = spiflash_wait_status();
2544 + reg = spiflash_read_reg(SPI_FLASH_DATA);
2545 + reg &= 0xff;
2546 +
2547 + return (u8) reg;
2548 +}
2549 +
2550 +
2551 +#define STM_8MBIT_SIGNATURE 0x13
2552 +#define STM_16MBIT_SIGNATURE 0x14
2553 +#define STM_32MBIT_SIGNATURE 0x15
2554 +#define STM_64MBIT_SIGNATURE 0x16
2555 +#define STM_128MBIT_SIGNATURE 0x17
2556 +
2557 +static u8 __init *
2558 +ar2315_flash_limit(void)
2559 +{
2560 + u32 flash_size = 0;
2561 +
2562 + /* probe the flash chip size */
2563 + switch(spiflash_probe()) {
2564 + case STM_8MBIT_SIGNATURE:
2565 + flash_size = 0x00100000;
2566 + break;
2567 + case STM_16MBIT_SIGNATURE:
2568 + flash_size = 0x00200000;
2569 + break;
2570 + case STM_32MBIT_SIGNATURE:
2571 + flash_size = 0x00400000;
2572 + break;
2573 + case STM_64MBIT_SIGNATURE:
2574 + flash_size = 0x00800000;
2575 + break;
2576 + case STM_128MBIT_SIGNATURE:
2577 + flash_size = 0x01000000;
2578 + break;
2579 + }
2580 +
2581 + ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start +
2582 + flash_size - 1;
2583 + return (u8 *) ar2315_spiflash_res[0].end + 1;
2584 +}
2585 +
2586 +#ifdef CONFIG_LEDS_GPIO
2587 +static struct gpio_led ar2315_leds[6];
2588 +static struct gpio_led_platform_data ar2315_led_data = {
2589 + .leds = (void *) ar2315_leds,
2590 +};
2591 +
2592 +static struct platform_device ar2315_gpio_leds = {
2593 + .name = "leds-gpio",
2594 + .id = -1,
2595 + .dev = {
2596 + .platform_data = (void *) &ar2315_led_data,
2597 + }
2598 +};
2599 +
2600 +static void __init
2601 +ar2315_init_gpio_leds(void)
2602 +{
2603 + static char led_names[6][6];
2604 + int i, led = 0;
2605 +
2606 + ar2315_led_data.num_leds = 0;
2607 + for (i = 1; i < 8; i++) {
2608 + if((i == AR2315_RESET_GPIO) ||
2609 + (i == ar231x_board.config->reset_config_gpio))
2610 + continue;
2611 +
2612 + if (i == ar231x_board.config->sys_led_gpio)
2613 + strcpy(led_names[led], "wlan");
2614 + else
2615 + sprintf(led_names[led], "gpio%d", i);
2616 +
2617 + ar2315_leds[led].name = led_names[led];
2618 + ar2315_leds[led].gpio = i;
2619 + ar2315_leds[led].active_low = 0;
2620 + led++;
2621 + }
2622 + ar2315_led_data.num_leds = led;
2623 + platform_device_register(&ar2315_gpio_leds);
2624 +}
2625 +#else
2626 +static inline void ar2315_init_gpio_leds(void)
2627 +{
2628 +}
2629 +#endif
2630 +
2631 +int __init
2632 +ar2315_init_devices(void)
2633 +{
2634 + if (!is_2315())
2635 + return 0;
2636 +
2637 + /* Find board configuration */
2638 + ar231x_find_config(ar2315_flash_limit());
2639 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2640 +
2641 + ar2315_init_gpio_leds();
2642 + platform_device_register(&ar2315_wdt);
2643 + platform_device_register(&ar2315_spiflash);
2644 + ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS,
2645 + &ar2315_eth_data);
2646 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2647 +
2648 + return 0;
2649 +}
2650 +
2651 +static void
2652 +ar2315_restart(char *command)
2653 +{
2654 + void (*mips_reset_vec)(void) = (void *) 0xbfc00000;
2655 +
2656 + local_irq_disable();
2657 +
2658 + /* try reset the system via reset control */
2659 + ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM);
2660 +
2661 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
2662 + * give it some time to attempt a gpio based hardware reset
2663 + * (atheros reference design workaround) */
2664 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2665 + mdelay(100);
2666 +
2667 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2668 + * workaround. Attempt to jump to the mips reset location -
2669 + * the boot loader itself might be able to recover the system */
2670 + mips_reset_vec();
2671 +}
2672 +
2673 +
2674 +/*
2675 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2676 + * to determine the predevisor value.
2677 + */
2678 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2679 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2680 +
2681 +static unsigned int __init
2682 +ar2315_sys_clk(unsigned int clock_ctl)
2683 +{
2684 + unsigned int pllc_ctrl, cpu_div;
2685 + unsigned int pllc_out, refdiv, fdiv, divby2;
2686 + unsigned int clk_div;
2687 +
2688 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2689 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2690 + refdiv = clockctl1_predivide_table[refdiv];
2691 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2692 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2693 + divby2 += 1;
2694 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2695 +
2696 + /* clkm input selected */
2697 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2698 + case 0:
2699 + case 1:
2700 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
2701 + break;
2702 + case 2:
2703 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
2704 + break;
2705 + default:
2706 + pllc_out = 40000000;
2707 + clk_div = 1;
2708 + break;
2709 + }
2710 +
2711 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2712 + cpu_div = cpu_div * 2 ?: 1;
2713 +
2714 + return pllc_out / (clk_div * cpu_div);
2715 +}
2716 +
2717 +static inline unsigned int
2718 +ar2315_cpu_frequency(void)
2719 +{
2720 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2721 +}
2722 +
2723 +static inline unsigned int
2724 +ar2315_apb_frequency(void)
2725 +{
2726 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2727 +}
2728 +
2729 +void __init
2730 +ar2315_time_init(void)
2731 +{
2732 + if (!is_2315())
2733 + return;
2734 +
2735 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2736 +}
2737 +
2738 +int __init
2739 +ar2315_gpio_init(void)
2740 +{
2741 + int ret;
2742 + struct ar231x_gpio_chip *gpch;
2743 + gpch = &ar2315_gpio_chip;
2744 + ret = gpiochip_add(&gpch->chip);
2745 + if (ret) {
2746 + pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
2747 + return ret;
2748 + }
2749 + pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
2750 + gpch->chip.ngpio);
2751 + return ret;
2752 +}
2753 +
2754 +
2755 +
2756 +void __init
2757 +ar2315_prom_init(void)
2758 +{
2759 + u32 memsize, memcfg, devid;
2760 +
2761 + if (!is_2315())
2762 + return;
2763 +
2764 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2765 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2766 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2767 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2768 + memsize <<= 3;
2769 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2770 +
2771 + /* Detect the hardware based on the device ID */
2772 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2773 + switch(devid) {
2774 + case 0x90:
2775 + case 0x91:
2776 + ar231x_devtype = DEV_TYPE_AR2317;
2777 + break;
2778 + default:
2779 + ar231x_devtype = DEV_TYPE_AR2315;
2780 + break;
2781 + }
2782 + ar2315_gpio_init();
2783 + ar231x_board.devid = devid;
2784 +}
2785 +
2786 +void __init
2787 +ar2315_plat_setup(void)
2788 +{
2789 + u32 config;
2790 +
2791 + if (!is_2315())
2792 + return;
2793 +
2794 + /* Clear any lingering AHB errors */
2795 + config = read_c0_config();
2796 + write_c0_config(config & ~0x3);
2797 + ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET);
2798 + ar231x_read_reg(AR2315_AHB_ERR1);
2799 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2800 +
2801 + _machine_restart = ar2315_restart;
2802 + ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency());
2803 +}
2804 --- /dev/null
2805 +++ b/arch/mips/ar231x/ar2315.h
2806 @@ -0,0 +1,37 @@
2807 +#ifndef __AR2315_H
2808 +#define __AR2315_H
2809 +
2810 +#ifdef CONFIG_ATHEROS_AR2315
2811 +
2812 +extern void ar2315_irq_init(void);
2813 +extern int ar2315_init_devices(void);
2814 +extern void ar2315_prom_init(void);
2815 +extern void ar2315_plat_setup(void);
2816 +extern void ar2315_time_init(void);
2817 +
2818 +#else
2819 +
2820 +static inline void ar2315_irq_init(void)
2821 +{
2822 +}
2823 +
2824 +static inline int ar2315_init_devices(void)
2825 +{
2826 + return 0;
2827 +}
2828 +
2829 +static inline void ar2315_prom_init(void)
2830 +{
2831 +}
2832 +
2833 +static inline void ar2315_plat_setup(void)
2834 +{
2835 +}
2836 +
2837 +static inline void ar2315_time_init(void)
2838 +{
2839 +}
2840 +
2841 +#endif
2842 +
2843 +#endif
2844 --- /dev/null
2845 +++ b/arch/mips/ar231x/ar5312.h
2846 @@ -0,0 +1,38 @@
2847 +#ifndef __AR5312_H
2848 +#define __AR5312_H
2849 +
2850 +#ifdef CONFIG_ATHEROS_AR5312
2851 +
2852 +extern void ar5312_irq_init(void);
2853 +extern int ar5312_init_devices(void);
2854 +extern void ar5312_prom_init(void);
2855 +extern void ar5312_plat_setup(void);
2856 +extern void ar5312_time_init(void);
2857 +extern void ar5312_time_init(void);
2858 +
2859 +#else
2860 +
2861 +static inline void ar5312_irq_init(void)
2862 +{
2863 +}
2864 +
2865 +static inline int ar5312_init_devices(void)
2866 +{
2867 + return 0;
2868 +}
2869 +
2870 +static inline void ar5312_prom_init(void)
2871 +{
2872 +}
2873 +
2874 +static inline void ar5312_plat_setup(void)
2875 +{
2876 +}
2877 +
2878 +static inline void ar5312_time_init(void)
2879 +{
2880 +}
2881 +
2882 +#endif
2883 +
2884 +#endif
2885 --- /dev/null
2886 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2887 @@ -0,0 +1,57 @@
2888 +#ifndef __AR531X_H
2889 +#define __AR531X_H
2890 +
2891 +#include <linux/types.h>
2892 +#include <linux/io.h>
2893 +
2894 +#define AR531X_MISC_IRQ_BASE 0x20
2895 +#define AR531X_GPIO_IRQ_BASE 0x30
2896 +
2897 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2898 +#define AR531X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
2899 +#define AR531X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2900 +
2901 +/* Miscellaneous interrupts, which share IP6 */
2902 +#define AR531X_MISC_IRQ_NONE (AR531X_MISC_IRQ_BASE+0)
2903 +#define AR531X_MISC_IRQ_TIMER (AR531X_MISC_IRQ_BASE+1)
2904 +#define AR531X_MISC_IRQ_AHB_PROC (AR531X_MISC_IRQ_BASE+2)
2905 +#define AR531X_MISC_IRQ_AHB_DMA (AR531X_MISC_IRQ_BASE+3)
2906 +#define AR531X_MISC_IRQ_GPIO (AR531X_MISC_IRQ_BASE+4)
2907 +#define AR531X_MISC_IRQ_UART0 (AR531X_MISC_IRQ_BASE+5)
2908 +#define AR531X_MISC_IRQ_UART0_DMA (AR531X_MISC_IRQ_BASE+6)
2909 +#define AR531X_MISC_IRQ_WATCHDOG (AR531X_MISC_IRQ_BASE+7)
2910 +#define AR531X_MISC_IRQ_LOCAL (AR531X_MISC_IRQ_BASE+8)
2911 +#define AR531X_MISC_IRQ_SPI (AR531X_MISC_IRQ_BASE+9)
2912 +#define AR531X_MISC_IRQ_COUNT 10
2913 +
2914 +/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
2915 +#define AR531X_GPIO_IRQ_NONE (AR531X_GPIO_IRQ_BASE+0)
2916 +#define AR531X_GPIO_IRQ(n) (AR531X_GPIO_IRQ_BASE+n)
2917 +#define AR531X_GPIO_IRQ_COUNT 22
2918 +
2919 +static inline u32
2920 +ar231x_read_reg(u32 reg)
2921 +{
2922 + return __raw_readl((u32 *) KSEG1ADDR(reg));
2923 +}
2924 +
2925 +static inline void
2926 +ar231x_write_reg(u32 reg, u32 val)
2927 +{
2928 + __raw_writel(val, (u32 *) KSEG1ADDR(reg));
2929 +}
2930 +
2931 +static inline u32
2932 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2933 +{
2934 + u32 ret;
2935 +
2936 + ret = ar231x_read_reg(reg);
2937 + ret &= ~mask;
2938 + ret |= val;
2939 + ar231x_write_reg(reg, ret);
2940 +
2941 + return ret;
2942 +}
2943 +
2944 +#endif
2945 --- /dev/null
2946 +++ b/arch/mips/ar231x/devices.h
2947 @@ -0,0 +1,42 @@
2948 +#ifndef __AR231X_DEVICES_H
2949 +#define __AR231X_DEVICES_H
2950 +#include <linux/gpio.h>
2951 +
2952 +enum {
2953 + /* handled by ar5312.c */
2954 + DEV_TYPE_AR2312,
2955 + DEV_TYPE_AR2313,
2956 + DEV_TYPE_AR5312,
2957 +
2958 + /* handled by ar2315.c */
2959 + DEV_TYPE_AR2315,
2960 + DEV_TYPE_AR2316,
2961 + DEV_TYPE_AR2317,
2962 +
2963 + DEV_TYPE_UNKNOWN
2964 +};
2965 +
2966 +extern int ar231x_devtype;
2967 +extern struct ar231x_board_config ar231x_board;
2968 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2969 +
2970 +extern int ar231x_find_config(u8 *flash_limit);
2971 +extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk);
2972 +extern int ar231x_add_wmac(int nr, u32 base, int irq);
2973 +extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
2974 +
2975 +static inline bool is_2315(void)
2976 +{
2977 + return (current_cpu_data.cputype == CPU_4KEC);
2978 +}
2979 +
2980 +static inline bool is_5312(void)
2981 +{
2982 + return !is_2315();
2983 +}
2984 +
2985 +struct ar231x_gpio_chip {
2986 + u32 valid_mask;
2987 + struct gpio_chip chip;
2988 +};
2989 +#endif
2990 --- /dev/null
2991 +++ b/arch/mips/ar231x/devices.c
2992 @@ -0,0 +1,168 @@
2993 +#include <linux/kernel.h>
2994 +#include <linux/init.h>
2995 +#include <linux/serial.h>
2996 +#include <linux/serial_core.h>
2997 +#include <linux/serial_8250.h>
2998 +#include <linux/platform_device.h>
2999 +#include <ar231x_platform.h>
3000 +#include <ar231x.h>
3001 +#include "devices.h"
3002 +#include "ar5312.h"
3003 +#include "ar2315.h"
3004 +
3005 +struct ar231x_board_config ar231x_board;
3006 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
3007 +
3008 +static struct resource ar231x_eth0_res[] = {
3009 + {
3010 + .name = "eth0_membase",
3011 + .flags = IORESOURCE_MEM,
3012 + },
3013 + {
3014 + .name = "eth0_irq",
3015 + .flags = IORESOURCE_IRQ,
3016 + }
3017 +};
3018 +
3019 +static struct resource ar231x_eth1_res[] = {
3020 + {
3021 + .name = "eth1_membase",
3022 + .flags = IORESOURCE_MEM,
3023 + },
3024 + {
3025 + .name = "eth1_irq",
3026 + .flags = IORESOURCE_IRQ,
3027 + }
3028 +};
3029 +
3030 +static struct platform_device ar231x_eth[] = {
3031 + {
3032 + .id = 0,
3033 + .name = "ar231x-eth",
3034 + .resource = ar231x_eth0_res,
3035 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
3036 + },
3037 + {
3038 + .id = 1,
3039 + .name = "ar231x-eth",
3040 + .resource = ar231x_eth1_res,
3041 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
3042 + }
3043 +};
3044 +
3045 +static struct resource ar231x_wmac0_res[] = {
3046 + {
3047 + .name = "wmac0_membase",
3048 + .flags = IORESOURCE_MEM,
3049 + },
3050 + {
3051 + .name = "wmac0_irq",
3052 + .flags = IORESOURCE_IRQ,
3053 + }
3054 +};
3055 +
3056 +static struct resource ar231x_wmac1_res[] = {
3057 + {
3058 + .name = "wmac1_membase",
3059 + .flags = IORESOURCE_MEM,
3060 + },
3061 + {
3062 + .name = "wmac1_irq",
3063 + .flags = IORESOURCE_IRQ,
3064 + }
3065 +};
3066 +
3067 +
3068 +static struct platform_device ar231x_wmac[] = {
3069 + {
3070 + .id = 0,
3071 + .name = "ar231x-wmac",
3072 + .resource = ar231x_wmac0_res,
3073 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
3074 + .dev.platform_data = &ar231x_board,
3075 + },
3076 + {
3077 + .id = 1,
3078 + .name = "ar231x-wmac",
3079 + .resource = ar231x_wmac1_res,
3080 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
3081 + .dev.platform_data = &ar231x_board,
3082 + },
3083 +};
3084 +
3085 +static const char *devtype_strings[] = {
3086 + [DEV_TYPE_AR5312] = "Atheros AR5312",
3087 + [DEV_TYPE_AR2312] = "Atheros AR2312",
3088 + [DEV_TYPE_AR2313] = "Atheros AR2313",
3089 + [DEV_TYPE_AR2315] = "Atheros AR2315",
3090 + [DEV_TYPE_AR2316] = "Atheros AR2316",
3091 + [DEV_TYPE_AR2317] = "Atheros AR2317",
3092 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
3093 +};
3094 +
3095 +const char *get_system_type(void)
3096 +{
3097 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
3098 + !devtype_strings[ar231x_devtype])
3099 + return devtype_strings[DEV_TYPE_UNKNOWN];
3100 + return devtype_strings[ar231x_devtype];
3101 +}
3102 +
3103 +
3104 +int __init
3105 +ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
3106 +{
3107 + struct resource *res;
3108 +
3109 + ar231x_eth[nr].dev.platform_data = pdata;
3110 + res = &ar231x_eth[nr].resource[0];
3111 + res->start = base;
3112 + res->end = base + 0x2000 - 1;
3113 + res++;
3114 + res->start = irq;
3115 + res->end = irq;
3116 + return platform_device_register(&ar231x_eth[nr]);
3117 +}
3118 +
3119 +void __init
3120 +ar231x_serial_setup(u32 mapbase, unsigned int uartclk)
3121 +{
3122 + struct uart_port s;
3123 +
3124 + memset(&s, 0, sizeof(s));
3125 +
3126 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3127 + s.iotype = UPIO_MEM;
3128 + s.irq = AR531X_MISC_IRQ_UART0;
3129 + s.regshift = 2;
3130 + s.mapbase = mapbase;
3131 + s.uartclk = uartclk;
3132 + s.membase = (void __iomem *)s.mapbase;
3133 +
3134 + early_serial_setup(&s);
3135 +}
3136 +
3137 +int __init
3138 +ar231x_add_wmac(int nr, u32 base, int irq)
3139 +{
3140 + struct resource *res;
3141 +
3142 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3143 + res = &ar231x_wmac[nr].resource[0];
3144 + res->start = base;
3145 + res->end = base + 0x10000 - 1;
3146 + res++;
3147 + res->start = irq;
3148 + res->end = irq;
3149 + return platform_device_register(&ar231x_wmac[nr]);
3150 +}
3151 +
3152 +static int __init ar231x_register_devices(void)
3153 +{
3154 + ar5312_init_devices();
3155 + ar2315_init_devices();
3156 +
3157 + return 0;
3158 +}
3159 +
3160 +device_initcall(ar231x_register_devices);
OpenWrt SVN history