target/linux/atheros/patches-3.10/105-ar2315_pci.patch

   1 --- a/arch/mips/ar231x/Makefile
   2 +++ b/arch/mips/ar231x/Makefile
   3 @@ -14,3 +14,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
   4
   5  obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
   6  obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
   7 +obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
   8 --- /dev/null
   9 +++ b/arch/mips/ar231x/pci.c
  10 @@ -0,0 +1,229 @@
  11 +/*
  12 + * This program is free software; you can redistribute it and/or
  13 + * modify it under the terms of the GNU General Public License
  14 + * as published by the Free Software Foundation; either version 2
  15 + * of the License, or (at your option) any later version.
  16 + *
  17 + * This program is distributed in the hope that it will be useful,
  18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 + * GNU General Public License for more details.
  21 + *
  22 + * You should have received a copy of the GNU General Public License
  23 + * along with this program; if not, write to the Free Software
  24 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  25 + */
  26 +
  27 +#include <linux/types.h>
  28 +#include <linux/pci.h>
  29 +#include <linux/kernel.h>
  30 +#include <linux/init.h>
  31 +#include <linux/mm.h>
  32 +#include <linux/spinlock.h>
  33 +#include <linux/delay.h>
  34 +#include <linux/irq.h>
  35 +#include <linux/io.h>
  36 +#include <asm/paccess.h>
  37 +#include <ar231x_platform.h>
  38 +#include <ar231x.h>
  39 +#include <ar2315_regs.h>
  40 +#include "devices.h"
  41 +
  42 +#define AR531X_MEM_BASE    0x80800000UL
  43 +#define AR531X_MEM_SIZE    0x00ffffffUL
  44 +#define AR531X_IO_SIZE     0x00007fffUL
  45 +
  46 +static unsigned long configspace;
  47 +
  48 +static int config_access(int devfn, int where, int size, u32 *ptr, bool write)
  49 +{
  50 +       unsigned long flags;
  51 +       int func = PCI_FUNC(devfn);
  52 +       int dev = PCI_SLOT(devfn);
  53 +       u32 value = 0;
  54 +       int err = 0;
  55 +       u32 addr;
  56 +
  57 +       if (((dev != 0) && (dev != 3)) || (func > 2))
  58 +               return PCIBIOS_DEVICE_NOT_FOUND;
  59 +
  60 +       /* Select Configuration access */
  61 +       local_irq_save(flags);
  62 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
  63 +       mb();
  64 +
  65 +       addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where;
  66 +       if (size == 1)
  67 +               addr ^= 0x3;
  68 +       else if (size == 2)
  69 +               addr ^= 0x2;
  70 +
  71 +       if (write) {
  72 +               value = *ptr;
  73 +               if (size == 1)
  74 +                       err = put_dbe(value, (u8 *)addr);
  75 +               else if (size == 2)
  76 +                       err = put_dbe(value, (u16 *)addr);
  77 +               else if (size == 4)
  78 +                       err = put_dbe(value, (u32 *)addr);
  79 +       } else {
  80 +               if (size == 1)
  81 +                       err = get_dbe(value, (u8 *)addr);
  82 +               else if (size == 2)
  83 +                       err = get_dbe(value, (u16 *)addr);
  84 +               else if (size == 4)
  85 +                       err = get_dbe(value, (u32 *)addr);
  86 +               if (err)
  87 +                       *ptr = 0xffffffff;
  88 +               else
  89 +                       *ptr = value;
  90 +       }
  91 +
  92 +       /* Select Memory access */
  93 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
  94 +       local_irq_restore(flags);
  95 +
  96 +       return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
  97 +}
  98 +
  99 +static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
 100 +                          int size, u32 *value)
 101 +{
 102 +       return config_access(devfn, where, size, value, 0);
 103 +}
 104 +
 105 +static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
 106 +{
 107 +       return config_access(devfn, where, size, &value, 1);
 108 +}
 109 +
 110 +struct pci_ops ar231x_pci_ops = {
 111 +       .read   = ar231x_pci_read,
 112 +       .write  = ar231x_pci_write,
 113 +};
 114 +
 115 +static struct resource ar231x_mem_resource = {
 116 +       .name   = "AR531x PCI MEM",
 117 +       .start  = AR531X_MEM_BASE,
 118 +       .end    = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000,
 119 +       .flags  = IORESOURCE_MEM,
 120 +};
 121 +
 122 +static struct resource ar231x_io_resource = {
 123 +       .name   = "AR531x PCI I/O",
 124 +       .start  = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE,
 125 +       .end    = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1,
 126 +       .flags  = IORESOURCE_IO,
 127 +};
 128 +
 129 +struct pci_controller ar231x_pci_controller = {
 130 +       .pci_ops                = &ar231x_pci_ops,
 131 +       .mem_resource   = &ar231x_mem_resource,
 132 +       .io_resource    = &ar231x_io_resource,
 133 +       .mem_offset     = 0x00000000UL,
 134 +       .io_offset      = 0x00000000UL,
 135 +};
 136 +
 137 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 138 +{
 139 +       return AR2315_IRQ_LCBUS_PCI;
 140 +}
 141 +
 142 +int pcibios_plat_dev_init(struct pci_dev *dev)
 143 +{
 144 +       pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
 145 +       pci_write_config_word(dev, 0x40, 0);
 146 +
 147 +       /* Clear any pending Abort or external Interrupts
 148 +        * and enable interrupt processing */
 149 +       ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0);
 150 +       ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
 151 +       ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
 152 +       ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE);
 153 +
 154 +       return 0;
 155 +}
 156 +
 157 +static void
 158 +ar2315_pci_fixup(struct pci_dev *dev)
 159 +{
 160 +       unsigned int devfn = dev->devfn;
 161 +
 162 +       if (dev->bus->number != 0)
 163 +               return;
 164 +
 165 +       /* Only fix up the PCI host settings */
 166 +       if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0))
 167 +               return;
 168 +
 169 +       /* Fix up MBARs */
 170 +       pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
 171 +       pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
 172 +       pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
 173 +       pci_write_config_dword(dev, PCI_COMMAND,
 174 +               PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
 175 +               PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
 176 +               PCI_COMMAND_FAST_BACK);
 177 +}
 178 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup);
 179 +
 180 +static int __init
 181 +ar2315_pci_init(void)
 182 +{
 183 +       u32 reg;
 184 +
 185 +       if (ar231x_devtype != DEV_TYPE_AR2315)
 186 +               return -ENODEV;
 187 +
 188 +       configspace = (unsigned long) ioremap_nocache(AR2315_PCIEXT, 1*1024*1024); /* Remap PCI config space */
 189 +       ar231x_pci_controller.io_map_base =
 190 +               (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE);
 191 +       set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */
 192 +
 193 +       reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
 194 +       msleep(10);
 195 +
 196 +       reg &= ~AR2315_RESET_PCIDMA;
 197 +       ar231x_write_reg(AR2315_RESET, reg);
 198 +       msleep(10);
 199 +
 200 +       ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
 201 +               AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
 202 +
 203 +       ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
 204 +               (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
 205 +       ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
 206 +       ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
 207 +               AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
 208 +                (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT));
 209 +
 210 +       /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
 211 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
 212 +               AR2315_PCIRST_LOW);
 213 +       msleep(100);
 214 +
 215 +       /* Bring the PCI out of reset */
 216 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
 217 +               AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
 218 +
 219 +       ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
 220 +                       0x1E | /* 1GB uncached */
 221 +                       (1 << 5) | /* Enable uncached */
 222 +                       (0x2 << 30) /* Base: 0x80000000 */
 223 +       );
 224 +       ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
 225 +
 226 +       msleep(500);
 227 +
 228 +       /* dirty hack - anyone with a datasheet that knows the memory map ? */
 229 +       ioport_resource.start = 0x10000000;
 230 +       ioport_resource.end = 0xffffffff;
 231 +       iomem_resource.start = 0x10000000;
 232 +       iomem_resource.end = 0xffffffff;
 233 +
 234 +       register_pci_controller(&ar231x_pci_controller);
 235 +
 236 +       return 0;
 237 +}
 238 +
 239 +arch_initcall(ar2315_pci_init);
 240 --- a/arch/mips/ar231x/Kconfig
 241 +++ b/arch/mips/ar231x/Kconfig
 242 @@ -14,3 +14,10 @@ config ATHEROS_AR2315
 243         select SYS_SUPPORTS_32BIT_KERNEL
 244         select SYS_SUPPORTS_BIG_ENDIAN
 245         default y
 246 +
 247 +config ATHEROS_AR2315_PCI
 248 +       bool "PCI support"
 249 +       depends on ATHEROS_AR2315
 250 +       select HW_HAS_PCI
 251 +       select PCI
 252 +       default y
 253 --- a/arch/mips/ar231x/ar2315.c
 254 +++ b/arch/mips/ar231x/ar2315.c
 255 @@ -64,6 +64,27 @@ static inline void ar2315_gpio_irq(void)
 256                 do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
 257  }
 258
 259 +#ifdef CONFIG_ATHEROS_AR2315_PCI
 260 +static inline void pci_abort_irq(void)
 261 +{
 262 +       ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT);
 263 +}
 264 +
 265 +static inline void pci_ack_irq(void)
 266 +{
 267 +       ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
 268 +}
 269 +
 270 +void ar2315_pci_irq(int irq)
 271 +{
 272 +       if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
 273 +               pci_abort_irq();
 274 +       else {
 275 +               do_IRQ(irq);
 276 +               pci_ack_irq();
 277 +       }
 278 +}
 279 +#endif /* CONFIG_ATHEROS_AR2315_PCI */
 280
 281  /*
 282   * Called when an interrupt is received, this function
 283 @@ -82,6 +103,10 @@ ar2315_irq_dispatch(void)
 284                 do_IRQ(AR2315_IRQ_WLAN0_INTRS);
 285         else if (pending & CAUSEF_IP4)
 286                 do_IRQ(AR2315_IRQ_ENET0_INTRS);
 287 +#ifdef CONFIG_ATHEROS_AR2315_PCI
 288 +       else if (pending & CAUSEF_IP5)
 289 +               ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI);
 290 +#endif
 291         else if (pending & CAUSEF_IP2) {
 292                 unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
 293