1 From 403eb25e5ae7a2169d8c1eae9df4162815e7c3ba Mon Sep 17 00:00:00 2001
2 From: Stuart Menefy <stuart.menefy at>
3 Date: Wed, 26 Jun 2013 11:48:38 +0000
4 Subject: [PATCH 01/17] clocksource:arm_global_timer: Add ARM global timer
7 This is a simple driver for the global timer module found in the Cortex
8 A9-MP cores from revision r1p0 onwards. This should be able to perform
9 the functions of the system timer and the local timer in an SMP system.
11 The global timer has the following features:
12 The global timer is a 64-bit incrementing counter with an
13 auto-incrementing feature. It continues incrementing after sending
14 interrupts. The global timer is memory mapped in the private memory
16 The global timer is accessible to all Cortex-A9 processors in the
17 cluster. Each Cortex-A9 processor has a private 64-bit comparator that
18 is used to assert a private interrupt when the global timer has reached
19 the comparator value. All the Cortex-A9 processors in a design use the
20 banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
21 Controller as a Private Peripheral Interrupt. The global timer is
24 Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
25 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
26 CC: Arnd Bergmann <arnd@arndb.de>
27 CC: Rob Herring <robherring2@gmail.com>
28 CC: Linus Walleij <linus.walleij@linaro.org>
29 CC: Will Deacon <will.deacon@arm.com>
30 CC: Thomas Gleixner <tglx@linutronix.de>
32 .../devicetree/bindings/arm/global_timer.txt | 21 ++
33 drivers/clocksource/Kconfig | 13 +
34 drivers/clocksource/Makefile | 1 +
35 drivers/clocksource/arm_global_timer.c | 325 ++++++++++++++++++++
36 4 files changed, 360 insertions(+)
37 create mode 100644 Documentation/devicetree/bindings/arm/global_timer.txt
38 create mode 100644 drivers/clocksource/arm_global_timer.c
41 +++ b/Documentation/devicetree/bindings/arm/global_timer.txt
45 + Cortex-A9 are often associated with a per-core Global timer.
47 +** Timer node required properties:
49 +- compatible : Should be "arm,cortex-a9-global-timer"
50 + Driver supports versions r2p0 and above.
52 +- interrupts : One interrupt to each core
54 +- reg : Specify the base address and the size of the GT timer
60 + compatible = "arm,cortex-a9-global-timer";
61 + reg = <0x2c000600 0x20>;
62 + interrupts = <1 13 0xf01>;
64 --- a/drivers/clocksource/Kconfig
65 +++ b/drivers/clocksource/Kconfig
66 @@ -67,6 +67,19 @@ config ARM_ARCH_TIMER
68 select CLKSRC_OF if OF
70 +config ARM_GLOBAL_TIMER
72 + select CLKSRC_OF if OF
74 + This options enables support for the ARM global timer unit
76 +config CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
78 + depends on ARM_GLOBAL_TIMER
81 + Use ARM global timer clock source as sched_clock
83 config CLKSRC_METAG_GENERIC
86 --- a/drivers/clocksource/Makefile
87 +++ b/drivers/clocksource/Makefile
88 @@ -28,4 +28,5 @@ obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exyno
89 obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o
91 obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
92 +obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
93 obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o
95 +++ b/drivers/clocksource/arm_global_timer.c
98 + * drivers/clocksource/arm_global_timer.c
100 + * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
101 + * Author: Stuart Menefy <stuart.menefy@st.com>
102 + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
104 + * This program is free software; you can redistribute it and/or modify
105 + * it under the terms of the GNU General Public License version 2 as
106 + * published by the Free Software Foundation.
109 +#include <linux/init.h>
110 +#include <linux/interrupt.h>
111 +#include <linux/clocksource.h>
112 +#include <linux/clockchips.h>
113 +#include <linux/cpu.h>
114 +#include <linux/clk.h>
115 +#include <linux/err.h>
116 +#include <linux/io.h>
117 +#include <linux/of.h>
118 +#include <linux/of_irq.h>
119 +#include <linux/of_address.h>
121 +#include <asm/sched_clock.h>
122 +#include <asm/cputype.h>
124 +#define GT_COUNTER0 0x00
125 +#define GT_COUNTER1 0x04
127 +#define GT_CONTROL 0x08
128 +#define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */
129 +#define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */
130 +#define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */
131 +#define GT_CONTROL_AUTO_INC BIT(3) /* banked */
133 +#define GT_INT_STATUS 0x0c
134 +#define GT_INT_STATUS_EVENT_FLAG BIT(0)
136 +#define GT_COMP0 0x10
137 +#define GT_COMP1 0x14
138 +#define GT_AUTO_INC 0x18
141 + * We are expecting to be clocked by the ARM peripheral clock.
143 + * Note: it is assumed we are using a prescaler value of zero, so this is
144 + * the units for all operations.
146 +static void __iomem *gt_base;
147 +static unsigned long gt_clk_rate;
149 +static struct clock_event_device __percpu *gt_evt;
152 + * To get the value from the Global Timer Counter register proceed as follows:
153 + * 1. Read the upper 32-bit timer counter register
154 + * 2. Read the lower 32-bit timer counter register
155 + * 3. Read the upper 32-bit timer counter register again. If the value is
156 + * different to the 32-bit upper value read previously, go back to step 2.
157 + * Otherwise the 64-bit timer counter value is correct.
159 +static u64 gt_counter_read(void)
163 + u32 upper, old_upper;
165 + upper = readl_relaxed(gt_base + GT_COUNTER1);
168 + lower = readl_relaxed(gt_base + GT_COUNTER0);
169 + upper = readl_relaxed(gt_base + GT_COUNTER1);
170 + } while (upper != old_upper);
179 + * To ensure that updates to comparator value register do not set the
180 + * Interrupt Status Register proceed as follows:
181 + * 1. Clear the Comp Enable bit in the Timer Control Register.
182 + * 2. Write the lower 32-bit Comparator Value Register.
183 + * 3. Write the upper 32-bit Comparator Value Register.
184 + * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
186 +static void gt_compare_set(unsigned long delta, int periodic)
188 + u64 counter = gt_counter_read();
189 + unsigned long ctrl = readl(gt_base + GT_CONTROL);
192 + ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE);
194 + writel(ctrl, gt_base + GT_CONTROL);
195 + writel(lower_32_bits(counter), gt_base + GT_COMP0);
196 + writel(upper_32_bits(counter), gt_base + GT_COMP1);
199 + writel(delta, gt_base + GT_AUTO_INC);
200 + ctrl |= GT_CONTROL_AUTO_INC;
203 + ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
204 + writel(ctrl, gt_base + GT_CONTROL);
207 +static void gt_clockevent_set_mode(enum clock_event_mode mode,
208 + struct clock_event_device *clk)
210 + unsigned long ctrl;
213 + case CLOCK_EVT_MODE_PERIODIC:
214 + gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1);
216 + case CLOCK_EVT_MODE_ONESHOT:
217 + case CLOCK_EVT_MODE_UNUSED:
218 + case CLOCK_EVT_MODE_SHUTDOWN:
219 + ctrl = readl(gt_base + GT_CONTROL);
220 + ctrl &= ~(GT_CONTROL_COMP_ENABLE |
221 + GT_CONTROL_IRQ_ENABLE | GT_CONTROL_AUTO_INC);
222 + writel(ctrl, gt_base + GT_CONTROL);
229 +static int gt_clockevent_set_next_event(unsigned long evt,
230 + struct clock_event_device *unused)
232 + gt_compare_set(evt, 0);
236 +static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
238 + struct clock_event_device *evt = dev_id;
240 + if (readl_relaxed(gt_base + GT_INT_STATUS) &
241 + GT_INT_STATUS_EVENT_FLAG) {
243 + * ERRATA 740657( Global Timer can send 2 interrupts for
244 + * the same event in single-shot mode)
246 + * Either disable single-shot mode.
248 + * Modify the Interrupt Handler to avoid the
249 + * offending sequence. This is achieved by clearing
250 + * the Global Timer flag _after_ having incremented
251 + * the Comparator register value to a higher value.
253 + if (!(readl_relaxed(gt_base + GT_CONTROL) &
254 + GT_CONTROL_AUTO_INC))
255 + gt_compare_set(ULONG_MAX, 0);
257 + writel_relaxed(GT_INT_STATUS_EVENT_FLAG,
258 + gt_base + GT_INT_STATUS);
260 + evt->event_handler(evt);
261 + return IRQ_HANDLED;
267 +static int __cpuinit gt_clockevents_init(struct clock_event_device *clk)
269 + int cpu = smp_processor_id();
271 + clk->name = "arm_global_timer";
272 + clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
273 + clk->set_mode = gt_clockevent_set_mode;
274 + clk->set_next_event = gt_clockevent_set_next_event;
275 + clk->cpumask = cpumask_of(cpu);
278 + clockevents_config_and_register(clk, gt_clk_rate,
280 + enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
284 +static void gt_clockevents_stop(struct clock_event_device *clk)
286 + gt_clockevent_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
287 + disable_percpu_irq(clk->irq);
290 +static cycle_t gt_clocksource_read(struct clocksource *cs)
292 + return gt_counter_read();
295 +static struct clocksource gt_clocksource = {
296 + .name = "arm_global_timer",
298 + .read = gt_clocksource_read,
299 + .mask = CLOCKSOURCE_MASK(64),
300 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
303 +#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
304 +static u32 notrace gt_sched_clock_read(void)
306 + return gt_counter_read();
310 +static void __init gt_clocksource_init(void)
312 + writel(0, gt_base + GT_CONTROL);
313 + writel(0, gt_base + GT_COUNTER0);
314 + writel(0, gt_base + GT_COUNTER1);
315 + /* enables timer on all the cores */
316 + writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
318 +#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
319 + setup_sched_clock(gt_sched_clock_read, 32, gt_clk_rate);
321 + clocksource_register_hz(>_clocksource, gt_clk_rate);
324 +static int __cpuinit gt_cpu_notify(struct notifier_block *self,
325 + unsigned long action, void *hcpu)
327 + switch (action & ~CPU_TASKS_FROZEN) {
329 + gt_clockevents_init(this_cpu_ptr(gt_evt));
332 + gt_clockevents_stop(this_cpu_ptr(gt_evt));
338 +static struct notifier_block gt_cpu_nb __cpuinitdata = {
339 + .notifier_call = gt_cpu_notify,
342 +static void __init global_timer_of_register(struct device_node *np)
344 + struct clk *gt_clk;
348 + * In r2p0 the comparators for each processor with the global timer
349 + * fire when the timer value is greater than or equal to. In previous
350 + * revisions the comparators fired when the timer value was equal to.
352 + if ((read_cpuid_id() & 0xf0000f) < 0x200000) {
353 + pr_warn("global-timer: non support for this cpu version.\n");
357 + gt_ppi = irq_of_parse_and_map(np, 0);
359 + pr_warn("global-timer: unable to parse irq\n");
363 + gt_base = of_iomap(np, 0);
365 + pr_warn("global-timer: invalid base address\n");
369 + gt_clk = of_clk_get(np, 0);
370 + if (!IS_ERR(gt_clk)) {
371 + err = clk_prepare_enable(gt_clk);
375 + pr_warn("global-timer: clk not found\n");
380 + gt_clk_rate = clk_get_rate(gt_clk);
381 + gt_evt = alloc_percpu(struct clock_event_device);
383 + pr_warn("global-timer: can't allocate memory\n");
388 + err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
391 + pr_warn("global-timer: can't register interrupt %d (%d)\n",
396 + err = register_cpu_notifier(>_cpu_nb);
398 + pr_warn("global-timer: unable to register cpu notifier.\n");
402 + /* Immediately configure the timer on the boot CPU */
403 + gt_clocksource_init();
404 + gt_clockevents_init(this_cpu_ptr(gt_evt));
409 + free_percpu_irq(gt_ppi, gt_evt);
411 + free_percpu(gt_evt);
413 + clk_disable_unprepare(gt_clk);
416 + WARN(err, "ARM Global timer register failed (%d)\n", err);
419 +/* Only tested on r2p2 and r3p0 */
420 +CLOCKSOURCE_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
421 + global_timer_of_register);