target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c

   1 /*
   2  * Low-Level PCI and SB support for BCM47xx (Linux support code)
   3  *
   4  * Copyright 2006, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id: pcibios.c,v 1.1.1.9 2006/02/27 03:42:55 honor Exp $
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/types.h>
  17 #include <linux/kernel.h>
  18 #include <linux/sched.h>
  19 #include <linux/pci.h>
  20 #include <linux/init.h>
  21 #include <linux/delay.h>
  22 #include <asm/io.h>
  23 #include <asm/irq.h>
  24 #include <asm/paccess.h>
  25
  26 #include <typedefs.h>
  27 #include <osl.h>
  28 #include <sbconfig.h>
  29 #include <sbutils.h>
  30 #include <hndpci.h>
  31 #include <pcicfg.h>
  32 #include <bcmdevs.h>
  33 #include <bcmnvram.h>
  34
  35 /* Global SB handle */
  36 extern sb_t *bcm947xx_sbh;
  37 extern spinlock_t bcm947xx_sbh_lock;
  38
  39 /* Convenience */
  40 #define sbh bcm947xx_sbh
  41 #define sbh_lock bcm947xx_sbh_lock
  42
  43 static int
  44 sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
  45 {
  46         unsigned long flags;
  47         int ret;
  48
  49         spin_lock_irqsave(&sbh_lock, flags);
  50         ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
  51                 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
  52         spin_unlock_irqrestore(&sbh_lock, flags);
  53         return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
  54 }
  55
  56 static int
  57 sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
  58 {
  59         unsigned long flags;
  60         int ret;
  61
  62         spin_lock_irqsave(&sbh_lock, flags);
  63         ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
  64                 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
  65         spin_unlock_irqrestore(&sbh_lock, flags);
  66         return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
  67 }
  68
  69 static int
  70 sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
  71 {
  72         unsigned long flags;
  73         int ret;
  74
  75         spin_lock_irqsave(&sbh_lock, flags);
  76         ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
  77                 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
  78         spin_unlock_irqrestore(&sbh_lock, flags);
  79         return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
  80 }
  81
  82 static int
  83 sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
  84 {
  85         unsigned long flags;
  86         int ret;
  87
  88         spin_lock_irqsave(&sbh_lock, flags);
  89         ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
  90                 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
  91         spin_unlock_irqrestore(&sbh_lock, flags);
  92         return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
  93 }
  94
  95 static int
  96 sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
  97 {
  98         unsigned long flags;
  99         int ret;
 100
 101         spin_lock_irqsave(&sbh_lock, flags);
 102         ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
 103                 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
 104         spin_unlock_irqrestore(&sbh_lock, flags);
 105         return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 106 }
 107
 108 static int
 109 sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
 110 {
 111         unsigned long flags;
 112         int ret;
 113
 114         spin_lock_irqsave(&sbh_lock, flags);
 115         ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
 116                 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
 117         spin_unlock_irqrestore(&sbh_lock, flags);
 118         return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 119 }
 120
 121 static struct pci_ops pcibios_ops = {
 122         sbpci_read_config_byte,
 123         sbpci_read_config_word,
 124         sbpci_read_config_dword,
 125         sbpci_write_config_byte,
 126         sbpci_write_config_word,
 127         sbpci_write_config_dword
 128 };
 129
 130
 131 void __init
 132 pcibios_init(void)
 133 {
 134         ulong flags;
 135
 136         if (!(sbh = sb_kattach(SB_OSH)))
 137                 panic("sb_kattach failed");
 138         spin_lock_init(&sbh_lock);
 139
 140         spin_lock_irqsave(&sbh_lock, flags);
 141         sbpci_init(sbh);
 142         spin_unlock_irqrestore(&sbh_lock, flags);
 143
 144         set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
 145         mdelay(300); /* workaround for atheros cards */
 146
 147         /* Scan the SB bus */
 148         pci_scan_bus(0, &pcibios_ops, NULL);
 149
 150 }
 151
 152 char * __init
 153 pcibios_setup(char *str)
 154 {
 155         if (!strncmp(str, "ban=", 4)) {
 156                 sbpci_ban(simple_strtoul(str + 4, NULL, 0));
 157                 return NULL;
 158         }
 159
 160         return (str);
 161 }
 162
 163 static u32 pci_iobase = 0x100;
 164 static u32 pci_membase = SB_PCI_DMA;
 165 static u32 pcmcia_membase = 0x40004000;
 166
 167 void __init
 168 pcibios_fixup_bus(struct pci_bus *b)
 169 {
 170         struct list_head *ln;
 171         struct pci_dev *d;
 172         struct resource *res;
 173         int pos, size;
 174         u32 *base;
 175         u8 irq;
 176
 177         printk("PCI: Fixing up bus %d\n", b->number);
 178
 179         /* Fix up SB */
 180         if (b->number == 0) {
 181                 for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
 182                         d = pci_dev_b(ln);
 183                         /* Fix up interrupt lines */
 184                         pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
 185                         d->irq = irq + 2;
 186                         pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
 187                 }
 188         }
 189
 190         /* Fix up external PCI */
 191         else {
 192                 for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
 193                         d = pci_dev_b(ln);
 194                         /* Fix up resource bases */
 195                         for (pos = 0; pos < 6; pos++) {
 196                                 res = &d->resource[pos];
 197                                 base = (res->flags & IORESOURCE_IO) ? &pci_iobase : ((b->number == 2) ? &pcmcia_membase : &pci_membase);
 198                                 if (res->end) {
 199                                         size = res->end - res->start + 1;
 200                                         if (*base & (size - 1))
 201                                                 *base = (*base + size) & ~(size - 1);
 202                                         res->start = *base;
 203                                         res->end = res->start + size - 1;
 204                                         *base += size;
 205                                         pci_write_config_dword(d,
 206                                                 PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
 207                                 }
 208                                 /* Fix up PCI bridge BAR0 only */
 209                                 if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
 210                                         break;
 211                         }
 212                         /* Fix up interrupt lines */
 213                         if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
 214                                 d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
 215                         pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
 216                 }
 217         }
 218 }
 219
 220 unsigned int
 221 pcibios_assign_all_busses(void)
 222 {
 223         return 1;
 224 }
 225
 226 void
 227 pcibios_align_resource(void *data, struct resource *res,
 228         unsigned long size, unsigned long align)
 229 {
 230 }
 231
 232 int
 233 pcibios_enable_resources(struct pci_dev *dev)
 234 {
 235         u16 cmd, old_cmd;
 236         int idx;
 237         struct resource *r;
 238
 239         /* External PCI only */
 240         if (dev->bus->number == 0)
 241                 return 0;
 242
 243         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 244         old_cmd = cmd;
 245         for (idx = 0; idx < 6; idx++) {
 246                 r = &dev->resource[idx];
 247                 if (r->flags & IORESOURCE_IO)
 248                         cmd |= PCI_COMMAND_IO;
 249                 if (r->flags & IORESOURCE_MEM)
 250                         cmd |= PCI_COMMAND_MEMORY;
 251         }
 252         if (dev->resource[PCI_ROM_RESOURCE].start)
 253                 cmd |= PCI_COMMAND_MEMORY;
 254         if (cmd != old_cmd) {
 255                 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
 256                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 257         }
 258         return 0;
 259 }
 260
 261 int
 262 pcibios_enable_device(struct pci_dev *dev, int mask)
 263 {
 264         ulong flags;
 265         uint coreidx;
 266         void *regs;
 267
 268         /* External PCI device enable */
 269         if (dev->bus->number != 0)
 270                 return pcibios_enable_resources(dev);
 271
 272         /* These cores come out of reset enabled */
 273         if (dev->device == SB_MIPS ||
 274             dev->device == SB_MIPS33 ||
 275             dev->device == SB_EXTIF ||
 276             dev->device == SB_CC)
 277                 return 0;
 278
 279         spin_lock_irqsave(&sbh_lock, flags);
 280         coreidx = sb_coreidx(sbh);
 281         regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
 282         if (!regs)
 283                 return PCIBIOS_DEVICE_NOT_FOUND;
 284
 285         /*
 286          * The USB core requires a special bit to be set during core
 287          * reset to enable host (OHCI) mode. Resetting the SB core in
 288          * pcibios_enable_device() is a hack for compatibility with
 289          * vanilla usb-ohci so that it does not have to know about
 290          * SB. A driver that wants to use the USB core in device mode
 291          * should know about SB and should reset the bit back to 0
 292          * after calling pcibios_enable_device().
 293          */
 294         if (sb_coreid(sbh) == SB_USB) {
 295                 printk(KERN_INFO "SB USB 1.1 init\n");
 296                 sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
 297                 sb_core_reset(sbh, 1 << 29, 0);
 298         }
 299         /*
 300          * USB 2.0 special considerations:
 301          *
 302          * 1. Since the core supports both OHCI and EHCI functions, it must
 303          *    only be reset once.
 304          *
 305          * 2. In addition to the standard SB reset sequence, the Host Control
 306          *    Register must be programmed to bring the USB core and various
 307          *    phy components out of reset.
 308          */
 309         else if (sb_coreid(sbh) == SB_USB20H) {
 310
 311                 uint corerev = sb_corerev(sbh);
 312
 313                 printk(KERN_INFO "SB USB20H init\n");
 314                 printk(KERN_INFO "SB COREREV: %d\n", corerev);
 315
 316                 if (!sb_iscoreup(sbh)) {
 317
 318                         printk(KERN_INFO "SB USB20H resetting\n");
 319
 320                         sb_core_reset(sbh, 0, 0);
 321                         writel(0x7FF, (ulong)regs + 0x200);
 322                         udelay(1);
 323                 }
 324                 /* PRxxxx: War for 5354 failures. */
 325                 if (corerev == 1 || corerev == 2) {
 326                         uint32 tmp;
 327
 328                         /* Change Flush control reg */
 329                         tmp = readl((uintptr)regs + 0x400);
 330                         tmp &= ~8;
 331                         writel(tmp, (uintptr)regs + 0x400);
 332                         tmp = readl((uintptr)regs + 0x400);
 333                         printk(KERN_INFO "USB20H fcr: 0x%x\n", tmp);
 334
 335                         /* Change Shim control reg */
 336                         tmp = readl((uintptr)regs + 0x304);
 337                         tmp &= ~0x100;
 338                         writel(tmp, (uintptr)regs + 0x304);
 339                         tmp = readl((uintptr)regs + 0x304);
 340                         printk(KERN_INFO "USB20H shim cr: 0x%x\n", tmp);
 341                 }
 342
 343         } else
 344                 sb_core_reset(sbh, 0, 0);
 345
 346         sb_setcoreidx(sbh, coreidx);
 347         spin_unlock_irqrestore(&sbh_lock, flags);
 348
 349         return 0;
 350 }
 351
 352 void
 353 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
 354         struct resource *res, int resource)
 355 {
 356         unsigned long where, size;
 357         u32 reg;
 358
 359         /* External PCI only */
 360         if (dev->bus->number == 0)
 361                 return;
 362
 363         where = PCI_BASE_ADDRESS_0 + (resource * 4);
 364         size = res->end - res->start;
 365         pci_read_config_dword(dev, where, &reg);
 366
 367         if (dev->bus->number == 1)
 368                 reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
 369         else
 370                 reg = res->start;
 371
 372         pci_write_config_dword(dev, where, reg);
 373 }
 374
 375 static void __init
 376 quirk_sbpci_bridge(struct pci_dev *dev)
 377 {
 378         if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
 379                 return;
 380
 381         printk("PCI: Fixing up bridge\n");
 382
 383         /* Enable PCI bridge bus mastering and memory space */
 384         pci_set_master(dev);
 385         pcibios_enable_resources(dev);
 386
 387         /* Enable PCI bridge BAR1 prefetch and burst */
 388         pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
 389 }
 390
 391 struct pci_fixup pcibios_fixups[] = {
 392         { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
 393         { 0 }
 394 };
 395
 396 /*
 397  *  If we set up a device for bus mastering, we need to check the latency
 398  *  timer as certain crappy BIOSes forget to set it properly.
 399  */
 400 unsigned int pcibios_max_latency = 255;
 401
 402 void pcibios_set_master(struct pci_dev *dev)
 403 {
 404         u8 lat;
 405         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 406         if (lat < 16)
 407                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 408         else if (lat > pcibios_max_latency)
 409                 lat = pcibios_max_latency;
 410         else
 411                 return;
 412         printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
 413         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 414 }
 415