target/linux/brcm-2.4/files/arch/mips/bcm947xx/time.c

   1 /*
   2  * Copyright 2006, Broadcom Corporation
   3  * All Rights Reserved.
   4  *
   5  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   6  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   7  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
   8  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
   9  *
  10  * $Id: time.c,v 1.1.1.10 2006/02/27 03:42:55 honor Exp $
  11  */
  12 #include <linux/config.h>
  13 #include <linux/init.h>
  14 #include <linux/kernel.h>
  15 #include <linux/sched.h>
  16 #include <linux/serial_reg.h>
  17 #include <linux/interrupt.h>
  18 #include <asm/addrspace.h>
  19 #include <asm/io.h>
  20 #include <asm/time.h>
  21
  22 #include <typedefs.h>
  23 #include <osl.h>
  24 #include <bcmnvram.h>
  25 #include <sbconfig.h>
  26 #include <sbextif.h>
  27 #include <sbutils.h>
  28 #include <hndmips.h>
  29 #include <mipsinc.h>
  30 #include <hndcpu.h>
  31
  32 /* Global SB handle */
  33 extern void *bcm947xx_sbh;
  34 extern spinlock_t bcm947xx_sbh_lock;
  35
  36 /* Convenience */
  37 #define sbh bcm947xx_sbh
  38 #define sbh_lock bcm947xx_sbh_lock
  39
  40 extern int panic_timeout;
  41 static int watchdog = 0;
  42 static u8 *mcr = NULL;
  43
  44 void __init
  45 bcm947xx_time_init(void)
  46 {
  47         unsigned int hz;
  48         extifregs_t *eir;
  49
  50         /*
  51          * Use deterministic values for initial counter interrupt
  52          * so that calibrate delay avoids encountering a counter wrap.
  53          */
  54         write_c0_count(0);
  55         write_c0_compare(0xffff);
  56
  57         if (!(hz = sb_cpu_clock(sbh)))
  58                 hz = 100000000;
  59
  60         printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
  61                (hz + 500000) / 1000000);
  62
  63         /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
  64         mips_hpt_frequency = hz / 2;
  65
  66         /* Set watchdog interval in ms */
  67         watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
  68
  69         /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
  70         if (watchdog > 0) {
  71                 if (watchdog < 3000)
  72                         watchdog = 3000;
  73         }
  74
  75         /* Set panic timeout in seconds */
  76         panic_timeout = watchdog / 1000;
  77 }
  78
  79 static void
  80 bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  81 {
  82         /* Generic MIPS timer code */
  83         timer_interrupt(irq, dev_id, regs);
  84
  85         /* Set the watchdog timer to reset after the specified number of ms */
  86         if (watchdog > 0)
  87                 sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
  88 }
  89
  90 static struct irqaction bcm947xx_timer_irqaction = {
  91         bcm947xx_timer_interrupt,
  92         SA_INTERRUPT,
  93         0,
  94         "timer",
  95         NULL,
  96         NULL
  97 };
  98
  99 void __init
 100 bcm947xx_timer_setup(struct irqaction *irq)
 101 {
 102         /* Enable the timer interrupt */
 103         setup_irq(7, &bcm947xx_timer_irqaction);
 104 }