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add a few missing exports
[openwrt/svn-archive/archive.git] / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -urN linux.old/arch/mips/bcm947xx/bcmsrom.c linux.dev/arch/mips/bcm947xx/bcmsrom.c
2 --- linux.old/arch/mips/bcm947xx/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux.dev/arch/mips/bcm947xx/bcmsrom.c 2006-10-02 21:19:59.000000000 +0200
4 @@ -0,0 +1,1213 @@
5 +/*
6 + * Misc useful routines to access NIC SROM/OTP .
7 + *
8 + * Copyright 2006, Broadcom Corporation
9 + * All Rights Reserved.
10 + *
11 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 + * $Id: bcmsrom.c,v 1.1.1.14 2006/04/15 01:28:25 michael Exp $
16 + */
17 +
18 +#include <typedefs.h>
19 +#include <bcmdefs.h>
20 +#include <osl.h>
21 +#include <bcmutils.h>
22 +#include <bcmsrom.h>
23 +#include <bcmdevs.h>
24 +#include <bcmendian.h>
25 +#include <sbpcmcia.h>
26 +#include <pcicfg.h>
27 +#include <sbutils.h>
28 +#include <bcmnvram.h>
29 +
30 +/* debug/trace */
31 +#if defined(WLTEST)
32 +#define BS_ERROR(args) printf args
33 +#else
34 +#define BS_ERROR(args)
35 +#endif /* BCMDBG_ERR || WLTEST */
36 +
37 +#define VARS_MAX 4096 /* should be reduced */
38 +
39 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
40 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
41 +
42 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count);
43 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count);
44 +static int initvars_flash_sb(void *sbh, char **vars, uint *count);
45 +static int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count);
46 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
47 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
48 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
49 +static int sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords,
50 + bool check_crc);
51 +
52 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
53 +static int initvars_flash(osl_t *osh, char **vp, uint len, char *devpath);
54 +
55 +/*
56 + * Initialize local vars from the right source for this platform.
57 + * Return 0 on success, nonzero on error.
58 + */
59 +int
60 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, uint *count)
61 +{
62 + ASSERT(bustype == BUSTYPE(bustype));
63 + if (vars == NULL || count == NULL)
64 + return (0);
65 +
66 + switch (BUSTYPE(bustype)) {
67 + case SB_BUS:
68 + case JTAG_BUS:
69 + return initvars_flash_sb(sbh, vars, count);
70 +
71 + case PCI_BUS:
72 + ASSERT(curmap); /* can not be NULL */
73 + return initvars_srom_pci(sbh, curmap, vars, count);
74 +
75 + case PCMCIA_BUS:
76 + return initvars_cis_pcmcia(sbh, osh, vars, count);
77 +
78 +
79 + default:
80 + ASSERT(0);
81 + }
82 + return (-1);
83 +}
84 +
85 +/* support only 16-bit word read from srom */
86 +int
87 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
88 +{
89 + void *srom;
90 + uint i, off, nw;
91 +
92 + ASSERT(bustype == BUSTYPE(bustype));
93 +
94 + /* check input - 16-bit access only */
95 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
96 + return 1;
97 +
98 + off = byteoff / 2;
99 + nw = nbytes / 2;
100 +
101 + if (BUSTYPE(bustype) == PCI_BUS) {
102 + if (!curmap)
103 + return 1;
104 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
105 + if (sprom_read_pci(osh, srom, off, buf, nw, FALSE))
106 + return 1;
107 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
108 + for (i = 0; i < nw; i++) {
109 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
110 + return 1;
111 + }
112 + } else {
113 + return 1;
114 + }
115 +
116 + return 0;
117 +}
118 +
119 +/* support only 16-bit word write into srom */
120 +int
121 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
122 +{
123 + uint16 *srom;
124 + uint i, nw, crc_range;
125 + uint16 image[SPROM_SIZE];
126 + uint8 crc;
127 + volatile uint32 val32;
128 +
129 + ASSERT(bustype == BUSTYPE(bustype));
130 +
131 + /* check input - 16-bit access only */
132 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
133 + return 1;
134 +
135 + /* Are we writing the whole thing at once? */
136 + if ((byteoff == 0) &&
137 + ((nbytes == SPROM_SIZE) ||
138 + (nbytes == (SPROM_CRC_RANGE * 2)) ||
139 + (nbytes == (SROM4_WORDS * 2)))) {
140 + crc_range = nbytes;
141 + bcopy((void*)buf, (void*)image, nbytes);
142 + nw = nbytes / 2;
143 + } else {
144 + if ((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS))
145 + crc_range = SPROM_SIZE;
146 + else
147 + crc_range = SPROM_CRC_RANGE * 2; /* Tentative */
148 +
149 + nw = crc_range / 2;
150 + /* read first 64 words from srom */
151 + if (srom_read(bustype, curmap, osh, 0, crc_range, image))
152 + return 1;
153 + if (image[SROM4_SIGN] == SROM4_SIGNATURE) {
154 + crc_range = SROM4_WORDS;
155 + nw = crc_range / 2;
156 + if (srom_read(bustype, curmap, osh, 0, crc_range, image))
157 + return 1;
158 + }
159 + /* make changes */
160 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
161 + }
162 +
163 + /* calculate crc */
164 + htol16_buf(image, crc_range);
165 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
166 + ltoh16_buf(image, crc_range);
167 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
168 +
169 + if (BUSTYPE(bustype) == PCI_BUS) {
170 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
171 + /* enable writes to the SPROM */
172 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
173 + val32 |= SPROM_WRITEEN;
174 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
175 + bcm_mdelay(WRITE_ENABLE_DELAY);
176 + /* write srom */
177 + for (i = 0; i < nw; i++) {
178 + W_REG(osh, &srom[i], image[i]);
179 + bcm_mdelay(WRITE_WORD_DELAY);
180 + }
181 + /* disable writes to the SPROM */
182 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 &
183 + ~SPROM_WRITEEN);
184 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
185 + /* enable writes to the SPROM */
186 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
187 + return 1;
188 + bcm_mdelay(WRITE_ENABLE_DELAY);
189 + /* write srom */
190 + for (i = 0; i < nw; i++) {
191 + sprom_write_pcmcia(osh, (uint16)(i), image[i]);
192 + bcm_mdelay(WRITE_WORD_DELAY);
193 + }
194 + /* disable writes to the SPROM */
195 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
196 + return 1;
197 + } else {
198 + return 1;
199 + }
200 +
201 + bcm_mdelay(WRITE_ENABLE_DELAY);
202 + return 0;
203 +}
204 +
205 +
206 +static int
207 +srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count)
208 +{
209 + char eabuf[32];
210 + char *vp, *base;
211 + uint8 *cis, tup, tlen, sromrev = 1;
212 + int i, j;
213 + uint varsize;
214 + bool ag_init = FALSE;
215 + uint32 w32;
216 +
217 + ASSERT(vars);
218 + ASSERT(count);
219 +
220 + base = vp = MALLOC(osh, VARS_MAX);
221 + ASSERT(vp);
222 + if (!vp)
223 + return -2;
224 +
225 + while (ciscnt--) {
226 + cis = *pcis++;
227 + i = 0;
228 + do {
229 + tup = cis[i++];
230 + tlen = cis[i++];
231 + if ((i + tlen) >= CIS_SIZE)
232 + break;
233 +
234 + switch (tup) {
235 + case CISTPL_MANFID:
236 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
237 + vp++;
238 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
239 + vp++;
240 + break;
241 +
242 + case CISTPL_FUNCE:
243 + switch (cis[i]) {
244 + case LAN_NID:
245 + ASSERT(cis[i + 1] == 6);
246 + bcm_ether_ntoa((struct ether_addr *)&cis[i + 2], eabuf);
247 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
248 + vp++;
249 + break;
250 + case 1: /* SDIO Extended Data */
251 + vp += sprintf(vp, "sdmaxblk=%d",
252 + (cis[i + 13] << 8) | cis[i + 12]);
253 + vp++;
254 + break;
255 + }
256 + break;
257 +
258 + case CISTPL_CFTABLE:
259 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
260 + vp++;
261 + break;
262 +
263 + case CISTPL_BRCM_HNBU:
264 + switch (cis[i]) {
265 + case HNBU_SROMREV:
266 + sromrev = cis[i + 1];
267 + break;
268 +
269 + case HNBU_CHIPID:
270 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) +
271 + cis[i + 1]);
272 + vp++;
273 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) +
274 + cis[i + 3]);
275 + vp++;
276 + if (tlen == 7) {
277 + vp += sprintf(vp, "chiprev=%d",
278 + (cis[i + 6] << 8) + cis[i + 5]);
279 + vp++;
280 + }
281 + break;
282 +
283 + case HNBU_BOARDREV:
284 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
285 + vp++;
286 + break;
287 +
288 + case HNBU_AA:
289 + vp += sprintf(vp, "aa2g=%d", cis[i + 1]);
290 + vp++;
291 + break;
292 +
293 + case HNBU_AG:
294 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
295 + vp++;
296 + ag_init = TRUE;
297 + break;
298 +
299 + case HNBU_CC:
300 + ASSERT(sromrev == 1);
301 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
302 + vp++;
303 + break;
304 +
305 + case HNBU_PAPARMS:
306 + if (tlen == 2) {
307 + ASSERT(sromrev == 1);
308 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
309 + vp++;
310 + } else if (tlen >= 9) {
311 + if (tlen == 10) {
312 + ASSERT(sromrev == 2);
313 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
314 + vp++;
315 + } else
316 + ASSERT(tlen == 9);
317 +
318 + for (j = 0; j < 3; j++) {
319 + vp += sprintf(vp, "pa0b%d=%d", j,
320 + (cis[i + (j * 2) + 2] << 8) +
321 + cis[i + (j * 2) + 1]);
322 + vp++;
323 + }
324 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
325 + vp++;
326 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
327 + vp++;
328 + } else
329 + ASSERT(tlen >= 9);
330 + break;
331 +
332 + case HNBU_OEM:
333 + ASSERT(sromrev == 1);
334 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
335 + cis[i + 1], cis[i + 2],
336 + cis[i + 3], cis[i + 4],
337 + cis[i + 5], cis[i + 6],
338 + cis[i + 7], cis[i + 8]);
339 + vp++;
340 + break;
341 +
342 + case HNBU_BOARDFLAGS:
343 + w32 = (cis[i + 2] << 8) + cis[i + 1];
344 + if (tlen == 5)
345 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
346 + vp += sprintf(vp, "boardflags=0x%x", w32);
347 + vp++;
348 + break;
349 +
350 + case HNBU_LEDS:
351 + if (cis[i + 1] != 0xff) {
352 + vp += sprintf(vp, "ledbh0=%d", cis[i + 1]);
353 + vp++;
354 + }
355 + if (cis[i + 2] != 0xff) {
356 + vp += sprintf(vp, "ledbh1=%d", cis[i + 2]);
357 + vp++;
358 + }
359 + if (cis[i + 3] != 0xff) {
360 + vp += sprintf(vp, "ledbh2=%d", cis[i + 3]);
361 + vp++;
362 + }
363 + if (cis[i + 4] != 0xff) {
364 + vp += sprintf(vp, "ledbh3=%d", cis[i + 4]);
365 + vp++;
366 + }
367 + break;
368 +
369 + case HNBU_CCODE:
370 + {
371 + char str[3];
372 + ASSERT(sromrev > 1);
373 + str[0] = cis[i + 1];
374 + str[1] = cis[i + 2];
375 + str[2] = 0;
376 + vp += sprintf(vp, "ccode=%s", str);
377 + vp++;
378 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
379 + vp++;
380 + break;
381 + }
382 +
383 + case HNBU_CCKPO:
384 + ASSERT(sromrev > 2);
385 + vp += sprintf(vp, "cckpo=0x%x",
386 + (cis[i + 2] << 8) | cis[i + 1]);
387 + vp++;
388 + break;
389 +
390 + case HNBU_OFDMPO:
391 + ASSERT(sromrev > 2);
392 + vp += sprintf(vp, "ofdmpo=0x%x",
393 + (cis[i + 4] << 24) |
394 + (cis[i + 3] << 16) |
395 + (cis[i + 2] << 8) |
396 + cis[i + 1]);
397 + vp++;
398 + break;
399 + }
400 + break;
401 +
402 + }
403 + i += tlen;
404 + } while (tup != 0xff);
405 + }
406 +
407 + /* Set the srom version */
408 + vp += sprintf(vp, "sromrev=%d", sromrev);
409 + vp++;
410 +
411 + /* if there is no antenna gain field, set default */
412 + if (ag_init == FALSE) {
413 + ASSERT(sromrev == 1);
414 + vp += sprintf(vp, "ag0=%d", 0xff);
415 + vp++;
416 + }
417 +
418 + /* final nullbyte terminator */
419 + *vp++ = '\0';
420 + varsize = (uint)(vp - base);
421 +
422 + ASSERT((vp - base) < VARS_MAX);
423 +
424 + if (varsize == VARS_MAX) {
425 + *vars = base;
426 + } else {
427 + vp = MALLOC(osh, varsize);
428 + ASSERT(vp);
429 + if (vp)
430 + bcopy(base, vp, varsize);
431 + MFREE(osh, base, VARS_MAX);
432 + *vars = vp;
433 + if (!vp) {
434 + *count = 0;
435 + return -2;
436 + }
437 + }
438 + *count = varsize;
439 +
440 + return (0);
441 +}
442 +
443 +
444 +/* set PCMCIA sprom command register */
445 +static int
446 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
447 +{
448 + uint8 status = 0;
449 + uint wait_cnt = 1000;
450 +
451 + /* write sprom command register */
452 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
453 +
454 + /* wait status */
455 + while (wait_cnt--) {
456 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
457 + if (status & SROM_DONE)
458 + return 0;
459 + }
460 +
461 + return 1;
462 +}
463 +
464 +/* read a word from the PCMCIA srom */
465 +static int
466 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
467 +{
468 + uint8 addr_l, addr_h, data_l, data_h;
469 +
470 + addr_l = (uint8)((addr * 2) & 0xff);
471 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
472 +
473 + /* set address */
474 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
475 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
476 +
477 + /* do read */
478 + if (sprom_cmd_pcmcia(osh, SROM_READ))
479 + return 1;
480 +
481 + /* read data */
482 + data_h = data_l = 0;
483 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
484 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
485 +
486 + *data = (data_h << 8) | data_l;
487 + return 0;
488 +}
489 +
490 +/* write a word to the PCMCIA srom */
491 +static int
492 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
493 +{
494 + uint8 addr_l, addr_h, data_l, data_h;
495 +
496 + addr_l = (uint8)((addr * 2) & 0xff);
497 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
498 + data_l = (uint8)(data & 0xff);
499 + data_h = (uint8)((data >> 8) & 0xff);
500 +
501 + /* set address */
502 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
503 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
504 +
505 + /* write data */
506 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
507 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
508 +
509 + /* do write */
510 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
511 +}
512 +
513 +/*
514 + * Read in and validate sprom.
515 + * Return 0 on success, nonzero on error.
516 + */
517 +static int
518 +sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
519 +{
520 + int err = 0;
521 + uint i;
522 +
523 + /* read the sprom */
524 + for (i = 0; i < nwords; i++)
525 + buf[i] = R_REG(osh, &sprom[wordoff + i]);
526 +
527 + if (check_crc) {
528 + /* fixup the endianness so crc8 will pass */
529 + htol16_buf(buf, nwords * 2);
530 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
531 + err = 1;
532 + /* now correct the endianness of the byte array */
533 + ltoh16_buf(buf, nwords * 2);
534 + }
535 +
536 + return err;
537 +}
538 +
539 +/*
540 +* Create variable table from memory.
541 +* Return 0 on success, nonzero on error.
542 +*/
543 +static int
544 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
545 +{
546 + int c = (int)(end - start);
547 +
548 + /* do it only when there is more than just the null string */
549 + if (c > 1) {
550 + char *vp = MALLOC(osh, c);
551 + ASSERT(vp);
552 + if (!vp)
553 + return BCME_NOMEM;
554 + bcopy(start, vp, c);
555 + *vars = vp;
556 + *count = c;
557 + }
558 + else {
559 + *vars = NULL;
560 + *count = 0;
561 + }
562 +
563 + return 0;
564 +}
565 +
566 +/*
567 + * Find variables with <devpath> from flash. 'base' points to the beginning
568 + * of the table upon enter and to the end of the table upon exit when success.
569 + * Return 0 on success, nonzero on error.
570 + */
571 +static int
572 +initvars_flash(osl_t *osh, char **base, uint len, char *devpath)
573 +{
574 + char *vp = *base;
575 + char *flash;
576 + int err;
577 + char *s;
578 + uint l, dl, copy_len;
579 +
580 + /* allocate memory and read in flash */
581 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
582 + return BCME_NOMEM;
583 + if ((err = nvram_getall(flash, NVRAM_SPACE)))
584 + goto exit;
585 +
586 + /* grab vars with the <devpath> prefix in name */
587 + dl = strlen(devpath);
588 + for (s = flash; s && *s; s += l + 1) {
589 + l = strlen(s);
590 +
591 + /* skip non-matching variable */
592 + if (strncmp(s, devpath, dl))
593 + continue;
594 +
595 + /* is there enough room to copy? */
596 + copy_len = l - dl + 1;
597 + if (len < copy_len) {
598 + err = BCME_BUFTOOSHORT;
599 + goto exit;
600 + }
601 +
602 + /* no prefix, just the name=value */
603 + strcpy(vp, &s[dl]);
604 + vp += copy_len;
605 + len -= copy_len;
606 + }
607 +
608 + /* add null string as terminator */
609 + if (len < 1) {
610 + err = BCME_BUFTOOSHORT;
611 + goto exit;
612 + }
613 + *vp++ = '\0';
614 +
615 + *base = vp;
616 +
617 +exit: MFREE(osh, flash, NVRAM_SPACE);
618 + return err;
619 +}
620 +
621 +/*
622 + * Initialize nonvolatile variable table from flash.
623 + * Return 0 on success, nonzero on error.
624 + */
625 +static int
626 +initvars_flash_sb(void *sbh, char **vars, uint *count)
627 +{
628 + osl_t *osh = sb_osh(sbh);
629 + char devpath[SB_DEVPATH_BUFSZ];
630 + char *vp, *base;
631 + int err;
632 +
633 + ASSERT(vars);
634 + ASSERT(count);
635 +
636 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
637 + return err;
638 +
639 + base = vp = MALLOC(osh, VARS_MAX);
640 + ASSERT(vp);
641 + if (!vp)
642 + return BCME_NOMEM;
643 +
644 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
645 + goto err;
646 +
647 + err = initvars_table(osh, base, vp, vars, count);
648 +
649 +err: MFREE(osh, base, VARS_MAX);
650 + return err;
651 +}
652 +
653 +#ifdef WLTEST
654 +char mfgsromvars[256];
655 +char *defaultsromvars = "il0macaddr=00:11:22:33:44:51\0"
656 + "et0macaddr=00:11:22:33:44:52\0"
657 + "et1macaddr=00:11:22:33:44:53\0"
658 + "boardtype=0xffff\0"
659 + "boardrev=0x10\0"
660 + "boardflags=8\0"
661 + "sromrev=2\0"
662 + "aa2g=3";
663 +#define MFGSROM_DEFVARSLEN 147 /* default srom len */
664 +#endif /* WL_TEST */
665 +
666 +/*
667 + * Initialize nonvolatile variable table from sprom.
668 + * Return 0 on success, nonzero on error.
669 + */
670 +static int
671 +initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count)
672 +{
673 + uint16 w, *b;
674 + uint8 sromrev = 0;
675 + struct ether_addr ea;
676 + char eabuf[32];
677 + uint32 w32;
678 + int woff, i;
679 + char *vp, *base;
680 + osl_t *osh = sb_osh(sbh);
681 + bool flash = FALSE;
682 + char name[SB_DEVPATH_BUFSZ+16], *value;
683 + char devpath[SB_DEVPATH_BUFSZ];
684 + int err;
685 +
686 + /*
687 + * Apply CRC over SROM content regardless SROM is present or not,
688 + * and use variable <devpath>sromrev's existance in flash to decide
689 + * if we should return an error when CRC fails or read SROM variables
690 + * from flash.
691 + */
692 + b = MALLOC(osh, SROM_MAX);
693 + ASSERT(b);
694 + if (!b)
695 + return -2;
696 +
697 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
698 + 64, TRUE);
699 + if (b[SROM4_SIGN] == SROM4_SIGNATURE) {
700 + /* sromrev >= 4, read more */
701 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, SROM4_WORDS, TRUE);
702 + sromrev = b[SROM4_WORDS - 1] & 0xff;
703 + } else if (err == 0) {
704 + /* srom is good and is rev < 4 */
705 + /* top word of sprom contains version and crc8 */
706 + sromrev = b[63] & 0xff;
707 + /* bcm4401 sroms misprogrammed */
708 + if (sromrev == 0x10)
709 + sromrev = 1;
710 + }
711 +
712 + if (err) {
713 +#ifdef WLTEST
714 + BS_ERROR(("SROM Crc Error, so see if we could use a default\n"));
715 + w32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
716 + if (w32 & SPROM_OTPIN_USE) {
717 + BS_ERROR(("srom crc failed with OTP, use default vars....\n"));
718 + vp = base = mfgsromvars;
719 + if (sb_chip(sbh) == BCM4311_CHIP_ID) {
720 + BS_ERROR(("setting the devid to be 4311\n"));
721 + vp += sprintf(vp, "devid=0x4311");
722 + vp++;
723 + }
724 + bcopy(defaultsromvars, vp, MFGSROM_DEFVARSLEN);
725 + vp += MFGSROM_DEFVARSLEN;
726 + goto varsdone;
727 + } else {
728 + BS_ERROR(("srom crc failed with SPROM....\n"));
729 +#endif /* WLTEST */
730 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
731 + return err;
732 + sprintf(name, "%ssromrev", devpath);
733 + if (!(value = getvar(NULL, name)))
734 + return (-1);
735 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
736 + flash = TRUE;
737 +#ifdef WLTEST
738 + }
739 +#endif /* WLTEST */
740 + }
741 +
742 + /* srom version check */
743 + if (sromrev > 4)
744 + return (-2);
745 +
746 + ASSERT(vars);
747 + ASSERT(count);
748 +
749 + base = vp = MALLOC(osh, VARS_MAX);
750 + ASSERT(vp);
751 + if (!vp)
752 + return -2;
753 +
754 + /* read variables from flash */
755 + if (flash) {
756 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
757 + goto err;
758 + goto varsdone;
759 + }
760 +
761 + vp += sprintf(vp, "sromrev=%d", sromrev);
762 + vp++;
763 +
764 + if (sromrev >= 4) {
765 + uint path, pathbase;
766 + const uint pathbases[MAX_PATH] = {SROM4_PATH0, SROM4_PATH1,
767 + SROM4_PATH2, SROM4_PATH3};
768 +
769 + vp += sprintf(vp, "boardrev=%d", b[SROM4_BREV]);
770 + vp++;
771 +
772 + vp += sprintf(vp, "boardflags=%d", (b[SROM4_BFL1] << 16) | b[SROM4_BFL0]);
773 + vp++;
774 +
775 + vp += sprintf(vp, "boardflags2=%d", (b[SROM4_BFL3] << 16) | b[SROM4_BFL2]);
776 + vp++;
777 +
778 + /* The macaddr */
779 + ea.octet[0] = (b[SROM4_MACHI] >> 8) & 0xff;
780 + ea.octet[1] = b[SROM4_MACHI] & 0xff;
781 + ea.octet[2] = (b[SROM4_MACMID] >> 8) & 0xff;
782 + ea.octet[3] = b[SROM4_MACMID] & 0xff;
783 + ea.octet[4] = (b[SROM4_MACLO] >> 8) & 0xff;
784 + ea.octet[5] = b[SROM4_MACLO] & 0xff;
785 + bcm_ether_ntoa(&ea, eabuf);
786 + vp += sprintf(vp, "macaddr=%s", eabuf);
787 + vp++;
788 +
789 + w = b[SROM4_CCODE];
790 + if (w == 0)
791 + vp += sprintf(vp, "ccode=");
792 + else
793 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
794 + vp++;
795 + vp += sprintf(vp, "regrev=%d", b[SROM4_REGREV]);
796 + vp++;
797 +
798 + w = b[SROM4_LEDBH10];
799 + if ((w != 0) && (w != 0xffff)) {
800 + /* ledbh0 */
801 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
802 + vp++;
803 +
804 + /* ledbh1 */
805 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
806 + vp++;
807 + }
808 + w = b[SROM4_LEDBH32];
809 + if ((w != 0) && (w != 0xffff)) {
810 + /* ledbh2 */
811 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
812 + vp++;
813 +
814 + /* ledbh3 */
815 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
816 + vp++;
817 + }
818 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
819 + if (w != 0xffff) {
820 + w = b[SROM4_LEDDC];
821 + w32 = ((uint32)((unsigned char)(w >> 8) & 0xff) << 24) | /* oncount */
822 + ((uint32)((unsigned char)(w & 0xff)) << 8); /* offcount */
823 + vp += sprintf(vp, "leddc=%d", w32);
824 + vp++;
825 + }
826 +
827 + w = b[SROM4_AA];
828 + vp += sprintf(vp, "aa2g=%d", w & SROM4_AA2G_MASK);
829 + vp++;
830 + vp += sprintf(vp, "aa5g=%d", w >> SROM4_AA5G_SHIFT);
831 + vp++;
832 +
833 + w = b[SROM4_AG10];
834 + vp += sprintf(vp, "ag0=%d", w & 0xff);
835 + vp++;
836 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
837 + vp++;
838 + w = b[SROM4_AG32];
839 + vp += sprintf(vp, "ag2=%d", w & 0xff);
840 + vp++;
841 + vp += sprintf(vp, "ag3=%d", (w >> 8) & 0xff);
842 + vp++;
843 +
844 + /* Fixed power indices when power control is disabled */
845 + for (i = 0; i < 2; i++) {
846 + w = b[SROM4_TXPID2G + i];
847 + vp += sprintf(vp, "txpid2ga%d=%d", 2 * i, w & 0xff);
848 + vp++;
849 + vp += sprintf(vp, "txpid2ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
850 + vp++;
851 + w = b[SROM4_TXPID5G + i];
852 + vp += sprintf(vp, "txpid5ga%d=%d", 2 * i, w & 0xff);
853 + vp++;
854 + vp += sprintf(vp, "txpid5ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
855 + vp++;
856 + w = b[SROM4_TXPID5GL + i];
857 + vp += sprintf(vp, "txpid5gla%d=%d", 2 * i, w & 0xff);
858 + vp++;
859 + vp += sprintf(vp, "txpid5gla%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
860 + vp++;
861 + w = b[SROM4_TXPID5GH + i];
862 + vp += sprintf(vp, "txpid5gha%d=%d", 2 * i, w & 0xff);
863 + vp++;
864 + vp += sprintf(vp, "txpid5gha%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
865 + vp++;
866 + }
867 +
868 + /* Per path variables */
869 + for (path = 0; path < MAX_PATH; path++) {
870 + pathbase = pathbases[path];
871 + w = b[pathbase + SROM4_2G_ITT_MAXP];
872 + vp += sprintf(vp, "itt2ga%d=%d", path, w >> B2G_ITT_SHIFT);
873 + vp++;
874 + vp += sprintf(vp, "maxp2ga%d=%d", path, w & B2G_MAXP_MASK);
875 + vp++;
876 +
877 + for (i = 0; i < 4; i++) {
878 + vp += sprintf(vp, "pa2gw%da%d=%d", i, path,
879 + b[pathbase + SROM4_2G_PA + i]);
880 + vp++;
881 + }
882 +
883 + w = b[pathbase + SROM4_5G_ITT_MAXP];
884 + vp += sprintf(vp, "itt5ga%d=%d", path, w >> B5G_ITT_SHIFT);
885 + vp++;
886 + vp += sprintf(vp, "maxp5ga%d=%d", path, w & B5G_MAXP_MASK);
887 + vp++;
888 +
889 + w = b[pathbase + SROM4_5GLH_MAXP];
890 + vp += sprintf(vp, "maxp5lga%d=%d", path, w >> B5GL_MAXP_SHIFT);
891 + vp++;
892 + vp += sprintf(vp, "maxp5gha%d=%d", path, w & B5GH_MAXP_MASK);
893 + vp++;
894 +
895 + for (i = 0; i < 4; i++) {
896 + vp += sprintf(vp, "pa5gw%da%d=%d", i, path,
897 + b[pathbase + SROM4_5G_PA + i]);
898 + vp++;
899 + vp += sprintf(vp, "pa5glw%da%d=%d", i, path,
900 + b[pathbase + SROM4_5GL_PA + i]);
901 + vp++;
902 + vp += sprintf(vp, "pa5hgw%da%d=%d", i, path,
903 + b[pathbase + SROM4_5GH_PA + i]);
904 + vp++;
905 + }
906 + }
907 +
908 + vp += sprintf(vp, "cck2gpo=%d", b[SROM4_2G_CCKPO]);
909 + vp++;
910 +
911 + w32 = ((uint32)b[SROM4_2G_OFDMPO + 1] << 16) | b[SROM4_2G_OFDMPO];
912 + vp += sprintf(vp, "ofdm2gpo=%d", w32);
913 + vp++;
914 +
915 + w32 = ((uint32)b[SROM4_5G_OFDMPO + 1] << 16) | b[SROM4_5G_OFDMPO];
916 + vp += sprintf(vp, "ofdm5gpo=%d", w32);
917 + vp++;
918 +
919 + w32 = ((uint32)b[SROM4_5GL_OFDMPO + 1] << 16) | b[SROM4_5GL_OFDMPO];
920 + vp += sprintf(vp, "ofdm5glpo=%d", w32);
921 + vp++;
922 +
923 + w32 = ((uint32)b[SROM4_5GH_OFDMPO + 1] << 16) | b[SROM4_5GH_OFDMPO];
924 + vp += sprintf(vp, "ofdm5ghpo=%d", w32);
925 + vp++;
926 +
927 + for (i = 0; i < 8; i++) {
928 + vp += sprintf(vp, "mcs2gpo%d=%d", i, b[SROM4_2G_MCSPO]);
929 + vp++;
930 + vp += sprintf(vp, "mcs5gpo%d=%d", i, b[SROM4_5G_MCSPO]);
931 + vp++;
932 + vp += sprintf(vp, "mcs5glpo%d=%d", i, b[SROM4_5GL_MCSPO]);
933 + vp++;
934 + vp += sprintf(vp, "mcs5ghpo%d=%d", i, b[SROM4_5GH_MCSPO]);
935 + vp++;
936 + }
937 +
938 + vp += sprintf(vp, "ccdpo%d=%d", i, b[SROM4_CCDPO]);
939 + vp++;
940 + vp += sprintf(vp, "stbcpo%d=%d", i, b[SROM4_STBCPO]);
941 + vp++;
942 + vp += sprintf(vp, "bw40po%d=%d", i, b[SROM4_BW40PO]);
943 + vp++;
944 + vp += sprintf(vp, "bwduppo%d=%d", i, b[SROM4_BWDUPPO]);
945 + vp++;
946 +
947 + goto done;
948 + }
949 + if (sromrev >= 3) {
950 + /* New section takes over the 3th hardware function space */
951 +
952 + /* Words 22+23 are 11a (mid) ofdm power offsets */
953 + w32 = ((uint32)b[23] << 16) | b[22];
954 + vp += sprintf(vp, "ofdmapo=%d", w32);
955 + vp++;
956 +
957 + /* Words 24+25 are 11a (low) ofdm power offsets */
958 + w32 = ((uint32)b[25] << 16) | b[24];
959 + vp += sprintf(vp, "ofdmalpo=%d", w32);
960 + vp++;
961 +
962 + /* Words 26+27 are 11a (high) ofdm power offsets */
963 + w32 = ((uint32)b[27] << 16) | b[26];
964 + vp += sprintf(vp, "ofdmahpo=%d", w32);
965 + vp++;
966 +
967 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
968 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xff) << 24) | /* oncount */
969 + ((uint32)((unsigned char)(b[21] & 0xff)) << 8); /* offcount */
970 + vp += sprintf(vp, "leddc=%d", w32);
971 +
972 + vp++;
973 + }
974 +
975 + if (sromrev >= 2) {
976 + /* New section takes over the 4th hardware function space */
977 +
978 + /* Word 29 is max power 11a high/low */
979 + w = b[29];
980 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
981 + vp++;
982 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
983 + vp++;
984 +
985 + /* Words 30-32 set the 11alow pa settings,
986 + * 33-35 are the 11ahigh ones.
987 + */
988 + for (i = 0; i < 3; i++) {
989 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
990 + vp++;
991 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
992 + vp++;
993 + }
994 + w = b[59];
995 + if (w == 0)
996 + vp += sprintf(vp, "ccode=");
997 + else
998 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
999 + vp++;
1000 +
1001 + }
1002 +
1003 + /* parameter section of sprom starts at byte offset 72 */
1004 + woff = 72/2;
1005 +
1006 + /* first 6 bytes are il0macaddr */
1007 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1008 + ea.octet[1] = b[woff] & 0xff;
1009 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1010 + ea.octet[3] = b[woff+1] & 0xff;
1011 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1012 + ea.octet[5] = b[woff+2] & 0xff;
1013 + woff += 3;
1014 + bcm_ether_ntoa(&ea, eabuf);
1015 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
1016 + vp++;
1017 +
1018 + /* next 6 bytes are et0macaddr */
1019 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1020 + ea.octet[1] = b[woff] & 0xff;
1021 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1022 + ea.octet[3] = b[woff+1] & 0xff;
1023 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1024 + ea.octet[5] = b[woff+2] & 0xff;
1025 + woff += 3;
1026 + bcm_ether_ntoa(&ea, eabuf);
1027 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
1028 + vp++;
1029 +
1030 + /* next 6 bytes are et1macaddr */
1031 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1032 + ea.octet[1] = b[woff] & 0xff;
1033 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1034 + ea.octet[3] = b[woff+1] & 0xff;
1035 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1036 + ea.octet[5] = b[woff+2] & 0xff;
1037 + woff += 3;
1038 + bcm_ether_ntoa(&ea, eabuf);
1039 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
1040 + vp++;
1041 +
1042 + /*
1043 + * Enet phy settings one or two singles or a dual
1044 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
1045 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
1046 + * Bit 14 : Mdio for enet0
1047 + * Bit 15 : Mdio for enet1
1048 + */
1049 + w = b[woff];
1050 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
1051 + vp++;
1052 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
1053 + vp++;
1054 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
1055 + vp++;
1056 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
1057 + vp++;
1058 +
1059 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
1060 + w = b[46];
1061 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
1062 + vp++;
1063 +
1064 + if (sromrev > 1)
1065 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
1066 + else
1067 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
1068 + vp++;
1069 +
1070 + vp += sprintf(vp, "aa2g=%d", (w >> 12) & 0x3);
1071 + vp++;
1072 +
1073 + vp += sprintf(vp, "aa5g=%d", (w >> 14) & 0x3);
1074 + vp++;
1075 +
1076 + /* Words 47-49 set the (wl) pa settings */
1077 + woff = 47;
1078 +
1079 + for (i = 0; i < 3; i++) {
1080 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
1081 + vp++;
1082 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
1083 + vp++;
1084 + }
1085 +
1086 + /*
1087 + * Words 50-51 set the customer-configured wl led behavior.
1088 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
1089 + * LED behavior values defined in wlioctl.h .
1090 + */
1091 + w = b[50];
1092 + if ((w != 0) && (w != 0xffff)) {
1093 + /* ledbh0 */
1094 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
1095 + vp++;
1096 +
1097 + /* ledbh1 */
1098 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
1099 + vp++;
1100 + }
1101 + w = b[51];
1102 + if ((w != 0) && (w != 0xffff)) {
1103 + /* ledbh2 */
1104 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
1105 + vp++;
1106 +
1107 + /* ledbh */
1108 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
1109 + vp++;
1110 + }
1111 +
1112 + /* Word 52 is max power 0/1 */
1113 + w = b[52];
1114 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
1115 + vp++;
1116 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
1117 + vp++;
1118 +
1119 + /* Word 56 is idle tssi target 0/1 */
1120 + w = b[56];
1121 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
1122 + vp++;
1123 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
1124 + vp++;
1125 +
1126 + /* Word 57 is boardflags, if not programmed make it zero */
1127 + w32 = (uint32)b[57];
1128 + if (w32 == 0xffff) w32 = 0;
1129 + if (sromrev > 1) {
1130 + /* Word 28 is the high bits of boardflags */
1131 + w32 |= (uint32)b[28] << 16;
1132 + }
1133 + vp += sprintf(vp, "boardflags=%d", w32);
1134 + vp++;
1135 +
1136 + /* Word 58 is antenna gain 0/1 */
1137 + w = b[58];
1138 + vp += sprintf(vp, "ag0=%d", w & 0xff);
1139 + vp++;
1140 +
1141 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
1142 + vp++;
1143 +
1144 + if (sromrev == 1) {
1145 + /* set the oem string */
1146 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
1147 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
1148 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
1149 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
1150 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
1151 + vp++;
1152 + } else if (sromrev == 2) {
1153 + /* Word 60 OFDM tx power offset from CCK level */
1154 + /* OFDM Power Offset - opo */
1155 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
1156 + vp++;
1157 + } else {
1158 + /* Word 60: cck power offsets */
1159 + vp += sprintf(vp, "cckpo=%d", b[60]);
1160 + vp++;
1161 +
1162 + /* Words 61+62: 11g ofdm power offsets */
1163 + w32 = ((uint32)b[62] << 16) | b[61];
1164 + vp += sprintf(vp, "ofdmgpo=%d", w32);
1165 + vp++;
1166 + }
1167 +
1168 + /* final nullbyte terminator */
1169 +done: *vp++ = '\0';
1170 +
1171 + ASSERT((vp - base) <= VARS_MAX);
1172 +
1173 +varsdone:
1174 + err = initvars_table(osh, base, vp, vars, count);
1175 +
1176 +err:
1177 +#ifdef WLTEST
1178 + if (base != mfgsromvars)
1179 +#endif
1180 + MFREE(osh, base, VARS_MAX);
1181 + MFREE(osh, b, SROM_MAX);
1182 + return err;
1183 +}
1184 +
1185 +/*
1186 + * Read the cis and call parsecis to initialize the vars.
1187 + * Return 0 on success, nonzero on error.
1188 + */
1189 +static int
1190 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count)
1191 +{
1192 + uint8 *cis = NULL;
1193 + int rc;
1194 + uint data_sz;
1195 +
1196 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
1197 +
1198 + if ((cis = MALLOC(osh, data_sz)) == NULL)
1199 + return (-2);
1200 +
1201 + if (sb_pcmciarev(sbh) == 1) {
1202 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
1203 + MFREE(osh, cis, data_sz);
1204 + return (-1);
1205 + }
1206 + /* fix up endianess for 16-bit data vs 8-bit parsing */
1207 + ltoh16_buf((uint16 *)cis, data_sz);
1208 + } else
1209 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
1210 +
1211 + rc = srom_parsecis(osh, &cis, 1, vars, count);
1212 +
1213 + MFREE(osh, cis, data_sz);
1214 +
1215 + return (rc);
1216 +}
1217 +
1218 diff -urN linux.old/arch/mips/bcm947xx/bcmutils.c linux.dev/arch/mips/bcm947xx/bcmutils.c
1219 --- linux.old/arch/mips/bcm947xx/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
1220 +++ linux.dev/arch/mips/bcm947xx/bcmutils.c 2006-10-02 21:19:59.000000000 +0200
1221 @@ -0,0 +1,247 @@
1222 +/*
1223 + * Misc useful OS-independent routines.
1224 + *
1225 + * Copyright 2006, Broadcom Corporation
1226 + * All Rights Reserved.
1227 + *
1228 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1229 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1230 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1231 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1232 + * $Id: bcmutils.c,v 1.1.1.12 2006/02/27 03:43:16 honor Exp $
1233 + */
1234 +
1235 +#include <typedefs.h>
1236 +#include <bcmdefs.h>
1237 +#include <stdarg.h>
1238 +#include <bcmutils.h>
1239 +#include <osl.h>
1240 +#include <sbutils.h>
1241 +#include <bcmnvram.h>
1242 +#include <bcmendian.h>
1243 +#include <bcmdevs.h>
1244 +
1245 +unsigned char bcm_ctype[] = {
1246 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
1247 + _BCM_C, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C,
1248 + _BCM_C, /* 8-15 */
1249 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
1250 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
1251 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
1252 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
1253 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
1254 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
1255 + _BCM_P, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X,
1256 + _BCM_U|_BCM_X, _BCM_U, /* 64-71 */
1257 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
1258 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
1259 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
1260 + _BCM_P, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X,
1261 + _BCM_L|_BCM_X, _BCM_L, /* 96-103 */
1262 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
1263 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
1264 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
1265 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 128-143 */
1266 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 144-159 */
1267 + _BCM_S|_BCM_SP, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1268 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 160-175 */
1269 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1270 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 176-191 */
1271 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,
1272 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, /* 192-207 */
1273 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_P, _BCM_U, _BCM_U, _BCM_U,
1274 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_L, /* 208-223 */
1275 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,
1276 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, /* 224-239 */
1277 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_P, _BCM_L, _BCM_L, _BCM_L,
1278 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L /* 240-255 */
1279 +};
1280 +
1281 +
1282 +ulong
1283 +bcm_strtoul(char *cp, char **endp, uint base)
1284 +{
1285 + ulong result, value;
1286 + bool minus;
1287 +
1288 + minus = FALSE;
1289 +
1290 + while (bcm_isspace(*cp))
1291 + cp++;
1292 +
1293 + if (cp[0] == '+')
1294 + cp++;
1295 + else if (cp[0] == '-') {
1296 + minus = TRUE;
1297 + cp++;
1298 + }
1299 +
1300 + if (base == 0) {
1301 + if (cp[0] == '0') {
1302 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
1303 + base = 16;
1304 + cp = &cp[2];
1305 + } else {
1306 + base = 8;
1307 + cp = &cp[1];
1308 + }
1309 + } else
1310 + base = 10;
1311 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
1312 + cp = &cp[2];
1313 + }
1314 +
1315 + result = 0;
1316 +
1317 + while (bcm_isxdigit(*cp) &&
1318 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
1319 + result = result*base + value;
1320 + cp++;
1321 + }
1322 +
1323 + if (minus)
1324 + result = (ulong)(result * -1);
1325 +
1326 + if (endp)
1327 + *endp = (char *)cp;
1328 +
1329 + return (result);
1330 +}
1331 +
1332 +uchar
1333 +bcm_toupper(uchar c)
1334 +{
1335 + if (bcm_islower(c))
1336 + c -= 'a'-'A';
1337 + return (c);
1338 +}
1339 +
1340 +char*
1341 +bcm_ether_ntoa(struct ether_addr *ea, char *buf)
1342 +{
1343 + sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
1344 + ea->octet[0]&0xff, ea->octet[1]&0xff, ea->octet[2]&0xff,
1345 + ea->octet[3]&0xff, ea->octet[4]&0xff, ea->octet[5]&0xff);
1346 + return (buf);
1347 +}
1348 +
1349 +
1350 +/*
1351 + * Search the name=value vars for a specific one and return its value.
1352 + * Returns NULL if not found.
1353 + */
1354 +char*
1355 +getvar(char *vars, char *name)
1356 +{
1357 + char *s;
1358 + int len;
1359 +
1360 + len = strlen(name);
1361 +
1362 + /* first look in vars[] */
1363 + for (s = vars; s && *s;) {
1364 + /* CSTYLED */
1365 + if ((memcmp(s, name, len) == 0) && (s[len] == '='))
1366 + return (&s[len+1]);
1367 +
1368 + while (*s++)
1369 + ;
1370 + }
1371 +
1372 + /* then query nvram */
1373 + return (nvram_get(name));
1374 +}
1375 +
1376 +/*
1377 + * Search the vars for a specific one and return its value as
1378 + * an integer. Returns 0 if not found.
1379 + */
1380 +int
1381 +getintvar(char *vars, char *name)
1382 +{
1383 + char *val;
1384 +
1385 + if ((val = getvar(vars, name)) == NULL)
1386 + return (0);
1387 +
1388 + return (bcm_strtoul(val, NULL, 0));
1389 +}
1390 +
1391 +
1392 +/*******************************************************************************
1393 + * crc8
1394 + *
1395 + * Computes a crc8 over the input data using the polynomial:
1396 + *
1397 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
1398 + *
1399 + * The caller provides the initial value (either CRC8_INIT_VALUE
1400 + * or the previous returned value) to allow for processing of
1401 + * discontiguous blocks of data. When generating the CRC the
1402 + * caller is responsible for complementing the final return value
1403 + * and inserting it into the byte stream. When checking, a final
1404 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
1405 + *
1406 + * Reference: Dallas Semiconductor Application Note 27
1407 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1408 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1409 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1410 + *
1411 + * ****************************************************************************
1412 + */
1413 +
1414 +static uint8 crc8_table[256] = {
1415 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
1416 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
1417 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
1418 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
1419 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
1420 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
1421 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
1422 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
1423 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
1424 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
1425 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
1426 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
1427 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
1428 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
1429 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
1430 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
1431 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
1432 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
1433 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
1434 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
1435 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
1436 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
1437 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
1438 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
1439 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
1440 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
1441 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
1442 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
1443 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
1444 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
1445 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
1446 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
1447 +};
1448 +
1449 +#define CRC_INNER_LOOP(n, c, x) \
1450 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
1451 +
1452 +uint8
1453 +hndcrc8(
1454 + uint8 *pdata, /* pointer to array of data to process */
1455 + uint nbytes, /* number of input data bytes to process */
1456 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
1457 +)
1458 +{
1459 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
1460 + * to avoid the undefined and unnecessary (uint8 >> 8) operation.
1461 + */
1462 + while (nbytes-- > 0)
1463 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
1464 +
1465 + return crc;
1466 +}
1467 +
1468 +
1469 diff -urN linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
1470 --- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
1471 +++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2006-10-02 21:19:59.000000000 +0200
1472 @@ -0,0 +1,234 @@
1473 +/*
1474 + * NVRAM variable manipulation (Linux kernel half)
1475 + *
1476 + * Copyright 2001-2003, Broadcom Corporation
1477 + * All Rights Reserved.
1478 + *
1479 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1480 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1481 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1482 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1483 + *
1484 + * $Id$
1485 + */
1486 +
1487 +#include <linux/config.h>
1488 +#include <linux/init.h>
1489 +#include <linux/module.h>
1490 +#include <linux/kernel.h>
1491 +#include <linux/string.h>
1492 +#include <asm/io.h>
1493 +#include <asm/uaccess.h>
1494 +
1495 +#include <typedefs.h>
1496 +#include <osl.h>
1497 +#include <bcmendian.h>
1498 +#include <bcmutils.h>
1499 +
1500 +#define NVRAM_SIZE (0x1ff0)
1501 +static char _nvdata[NVRAM_SIZE] __initdata;
1502 +static char _valuestr[256] __initdata;
1503 +
1504 +/*
1505 + * TLV types. These codes are used in the "type-length-value"
1506 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
1507 + *
1508 + * The layout of the flash/nvram is as follows:
1509 + *
1510 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
1511 + *
1512 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
1513 + * The "length" field marks the length of the data section, not
1514 + * including the type and length fields.
1515 + *
1516 + * Environment variables are stored as follows:
1517 + *
1518 + * <type_env> <length> <flags> <name> = <value>
1519 + *
1520 + * If bit 0 (low bit) is set, the length is an 8-bit value.
1521 + * If bit 0 (low bit) is clear, the length is a 16-bit value
1522 + *
1523 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
1524 + * indicates the size of the length field.
1525 + *
1526 + * Flags are from the constants below:
1527 + *
1528 + */
1529 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
1530 +#define ENV_LENGTH_8BITS 0x01
1531 +
1532 +#define ENV_TYPE_USER 0x80
1533 +
1534 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
1535 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
1536 +
1537 +/*
1538 + * The actual TLV types we support
1539 + */
1540 +
1541 +#define ENV_TLV_TYPE_END 0x00
1542 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
1543 +
1544 +/*
1545 + * Environment variable flags
1546 + */
1547 +
1548 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
1549 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
1550 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
1551 +
1552 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
1553 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
1554 +
1555 +
1556 +/* *********************************************************************
1557 + * _nvram_read(buffer,offset,length)
1558 + *
1559 + * Read data from the NVRAM device
1560 + *
1561 + * Input parameters:
1562 + * buffer - destination buffer
1563 + * offset - offset of data to read
1564 + * length - number of bytes to read
1565 + *
1566 + * Return value:
1567 + * number of bytes read, or <0 if error occured
1568 + ********************************************************************* */
1569 +static int
1570 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
1571 +{
1572 + int i;
1573 + if (offset > NVRAM_SIZE)
1574 + return -1;
1575 +
1576 + for ( i = 0; i < length; i++) {
1577 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
1578 + }
1579 + return length;
1580 +}
1581 +
1582 +
1583 +static char*
1584 +_strnchr(const char *dest,int c,size_t cnt)
1585 +{
1586 + while (*dest && (cnt > 0)) {
1587 + if (*dest == c) return (char *) dest;
1588 + dest++;
1589 + cnt--;
1590 + }
1591 + return NULL;
1592 +}
1593 +
1594 +
1595 +
1596 +/*
1597 + * Core support API: Externally visible.
1598 + */
1599 +
1600 +/*
1601 + * Get the value of an NVRAM variable
1602 + * @param name name of variable to get
1603 + * @return value of variable or NULL if undefined
1604 + */
1605 +
1606 +char*
1607 +cfe_env_get(unsigned char *nv_buf, char* name)
1608 +{
1609 + int size;
1610 + unsigned char *buffer;
1611 + unsigned char *ptr;
1612 + unsigned char *envval;
1613 + unsigned int reclen;
1614 + unsigned int rectype;
1615 + int offset;
1616 + int flg;
1617 +
1618 + size = NVRAM_SIZE;
1619 + buffer = &_nvdata[0];
1620 +
1621 + ptr = buffer;
1622 + offset = 0;
1623 +
1624 + /* Read the record type and length */
1625 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1626 + goto error;
1627 + }
1628 +
1629 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1630 +
1631 + /* Adjust pointer for TLV type */
1632 + rectype = *(ptr);
1633 + offset++;
1634 + size--;
1635 +
1636 + /*
1637 + * Read the length. It can be either 1 or 2 bytes
1638 + * depending on the code
1639 + */
1640 + if (rectype & ENV_LENGTH_8BITS) {
1641 + /* Read the record type and length - 8 bits */
1642 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1643 + goto error;
1644 + }
1645 + reclen = *(ptr);
1646 + size--;
1647 + offset++;
1648 + }
1649 + else {
1650 + /* Read the record type and length - 16 bits, MSB first */
1651 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1652 + goto error;
1653 + }
1654 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1655 + size -= 2;
1656 + offset += 2;
1657 + }
1658 +
1659 + if (reclen > size)
1660 + break; /* should not happen, bad NVRAM */
1661 +
1662 + switch (rectype) {
1663 + case ENV_TLV_TYPE_ENV:
1664 + /* Read the TLV data */
1665 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1666 + goto error;
1667 + flg = *ptr++;
1668 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1669 + if (envval) {
1670 + *envval++ = '\0';
1671 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1672 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1673 +#if 0
1674 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1675 +#endif
1676 + if(!strcmp(ptr, name)){
1677 + return _valuestr;
1678 + }
1679 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1680 + return _valuestr;
1681 + }
1682 + break;
1683 +
1684 + default:
1685 + /* Unknown TLV type, skip it. */
1686 + break;
1687 + }
1688 +
1689 + /*
1690 + * Advance to next TLV
1691 + */
1692 +
1693 + size -= (int)reclen;
1694 + offset += reclen;
1695 +
1696 + /* Read the next record type */
1697 + ptr = buffer;
1698 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1699 + goto error;
1700 + }
1701 +
1702 +error:
1703 + return NULL;
1704 +
1705 +}
1706 +
1707 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
1708 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
1709 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2006-10-02 21:19:59.000000000 +0200
1710 @@ -0,0 +1,33 @@
1711 +#
1712 +# Makefile for Broadcom BCM947XX boards
1713 +#
1714 +# Copyright 2001-2003, Broadcom Corporation
1715 +# All Rights Reserved.
1716 +#
1717 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1718 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1719 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1720 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1721 +#
1722 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
1723 +#
1724 +
1725 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
1726 +SYSTEM ?= $(TOPDIR)/vmlinux
1727 +
1728 +all: vmlinuz
1729 +
1730 +# Don't build dependencies, this may die if $(CC) isn't gcc
1731 +dep:
1732 +
1733 +# Create a gzipped version named vmlinuz for compatibility
1734 +vmlinuz: piggy
1735 + gzip -c9 $< > $@
1736 +
1737 +piggy: $(SYSTEM)
1738 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
1739 +
1740 +mrproper: clean
1741 +
1742 +clean:
1743 + rm -f vmlinuz piggy
1744 diff -urN linux.old/arch/mips/bcm947xx/export.c linux.dev/arch/mips/bcm947xx/export.c
1745 --- linux.old/arch/mips/bcm947xx/export.c 1970-01-01 01:00:00.000000000 +0100
1746 +++ linux.dev/arch/mips/bcm947xx/export.c 2006-10-02 21:19:59.000000000 +0200
1747 @@ -0,0 +1,71 @@
1748 +#include <linux/module.h>
1749 +
1750 +#define _export(n) \
1751 + void n(void); \
1752 + EXPORT_SYMBOL(n);
1753 +
1754 +_export(bcm947xx_sbh)
1755 +
1756 +_export(sb_attach)
1757 +_export(sb_kattach)
1758 +_export(sb_boardtype)
1759 +_export(sb_boardvendor)
1760 +_export(sb_btcgpiowar)
1761 +_export(sb_bus)
1762 +_export(sb_chip)
1763 +_export(sb_chiprev)
1764 +_export(sb_chipcrev)
1765 +_export(sb_chippkg)
1766 +_export(sb_clkctl_clk)
1767 +_export(sb_clkctl_fast_pwrup_delay)
1768 +_export(sb_clkctl_init)
1769 +_export(sb_clkctl_xtal)
1770 +_export(sb_core_disable)
1771 +_export(sb_core_reset)
1772 +_export(sb_core_tofixup)
1773 +_export(sb_coreflags)
1774 +_export(sb_coreflagshi)
1775 +_export(sb_coreidx)
1776 +_export(sb_coreregs)
1777 +_export(sb_corerev)
1778 +_export(sb_coreunit)
1779 +_export(sb_detach)
1780 +_export(sb_deviceremoved)
1781 +_export(sb_gpiosetcore)
1782 +_export(sb_gpiocontrol)
1783 +_export(sb_gpiointmask)
1784 +_export(sb_gpiointpolarity)
1785 +_export(sb_gpioled)
1786 +_export(sb_gpioin)
1787 +_export(sb_gpioout)
1788 +_export(sb_gpioouten)
1789 +_export(sb_gpiotimerval)
1790 +_export(sb_irq)
1791 +_export(sb_iscoreup)
1792 +_export(sb_pci_setup)
1793 +_export(sb_pcirev)
1794 +_export(sb_pcmcia_init)
1795 +_export(sb_pcmciarev)
1796 +_export(sb_register_intr_callback)
1797 +_export(sb_setcore)
1798 +_export(sb_setcoreidx)
1799 +_export(sb_war16165)
1800 +_export(sb_war32414_forceHT)
1801 +_export(sb_osh)
1802 +
1803 +_export(getvar)
1804 +_export(getintvar)
1805 +_export(bcm_strtoul)
1806 +_export(bcm_ctype)
1807 +_export(bcm_toupper)
1808 +_export(bcm_ether_ntoa)
1809 +
1810 +_export(nvram_get)
1811 +_export(nvram_getall)
1812 +_export(nvram_set)
1813 +_export(nvram_unset)
1814 +_export(nvram_commit)
1815 +
1816 +_export(srom_read)
1817 +_export(srom_write)
1818 +
1819 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
1820 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
1821 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2006-10-02 21:19:59.000000000 +0200
1822 @@ -0,0 +1,51 @@
1823 +/*
1824 + * Generic interrupt handler for Broadcom MIPS boards
1825 + *
1826 + * Copyright 2004, Broadcom Corporation
1827 + * All Rights Reserved.
1828 + *
1829 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1830 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1831 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1832 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1833 + *
1834 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
1835 + */
1836 +
1837 +#include <linux/config.h>
1838 +
1839 +#include <asm/asm.h>
1840 +#include <asm/mipsregs.h>
1841 +#include <asm/regdef.h>
1842 +#include <asm/stackframe.h>
1843 +
1844 +/*
1845 + * MIPS IRQ Source
1846 + * -------- ------
1847 + * 0 Software (ignored)
1848 + * 1 Software (ignored)
1849 + * 2 Combined hardware interrupt (hw0)
1850 + * 3 Hardware
1851 + * 4 Hardware
1852 + * 5 Hardware
1853 + * 6 Hardware
1854 + * 7 R4k timer
1855 + */
1856 +
1857 + .text
1858 + .set noreorder
1859 + .set noat
1860 + .align 5
1861 + NESTED(brcmIRQ, PT_SIZE, sp)
1862 + SAVE_ALL
1863 + CLI
1864 + .set at
1865 + .set noreorder
1866 +
1867 + jal brcm_irq_dispatch
1868 + move a0, sp
1869 +
1870 + j ret_from_irq
1871 + nop
1872 +
1873 + END(brcmIRQ)
1874 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
1875 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
1876 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2006-10-02 21:19:59.000000000 +0200
1877 @@ -0,0 +1,130 @@
1878 +/*
1879 + * Generic interrupt control functions for Broadcom MIPS boards
1880 + *
1881 + * Copyright 2004, Broadcom Corporation
1882 + * All Rights Reserved.
1883 + *
1884 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1885 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1886 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1887 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1888 + *
1889 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
1890 + */
1891 +
1892 +#include <linux/config.h>
1893 +#include <linux/init.h>
1894 +#include <linux/kernel.h>
1895 +#include <linux/types.h>
1896 +#include <linux/interrupt.h>
1897 +#include <linux/irq.h>
1898 +
1899 +#include <asm/irq.h>
1900 +#include <asm/mipsregs.h>
1901 +#include <asm/gdb-stub.h>
1902 +
1903 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1904 +
1905 +extern asmlinkage void brcmIRQ(void);
1906 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
1907 +
1908 +void
1909 +brcm_irq_dispatch(struct pt_regs *regs)
1910 +{
1911 + u32 cause;
1912 +
1913 + cause = read_c0_cause() &
1914 + read_c0_status() &
1915 + CAUSEF_IP;
1916 +
1917 +#ifdef CONFIG_KERNPROF
1918 + change_c0_status(cause | 1, 1);
1919 +#else
1920 + clear_c0_status(cause);
1921 +#endif
1922 +
1923 + if (cause & CAUSEF_IP7)
1924 + do_IRQ(7, regs);
1925 + if (cause & CAUSEF_IP2)
1926 + do_IRQ(2, regs);
1927 + if (cause & CAUSEF_IP3)
1928 + do_IRQ(3, regs);
1929 + if (cause & CAUSEF_IP4)
1930 + do_IRQ(4, regs);
1931 + if (cause & CAUSEF_IP5)
1932 + do_IRQ(5, regs);
1933 + if (cause & CAUSEF_IP6)
1934 + do_IRQ(6, regs);
1935 +}
1936 +
1937 +static void
1938 +enable_brcm_irq(unsigned int irq)
1939 +{
1940 + if (irq < 8)
1941 + set_c0_status(1 << (irq + 8));
1942 + else
1943 + set_c0_status(IE_IRQ0);
1944 +}
1945 +
1946 +static void
1947 +disable_brcm_irq(unsigned int irq)
1948 +{
1949 + if (irq < 8)
1950 + clear_c0_status(1 << (irq + 8));
1951 + else
1952 + clear_c0_status(IE_IRQ0);
1953 +}
1954 +
1955 +static void
1956 +ack_brcm_irq(unsigned int irq)
1957 +{
1958 + /* Already done in brcm_irq_dispatch */
1959 +}
1960 +
1961 +static unsigned int
1962 +startup_brcm_irq(unsigned int irq)
1963 +{
1964 + enable_brcm_irq(irq);
1965 +
1966 + return 0; /* never anything pending */
1967 +}
1968 +
1969 +static void
1970 +end_brcm_irq(unsigned int irq)
1971 +{
1972 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
1973 + enable_brcm_irq(irq);
1974 +}
1975 +
1976 +static struct hw_interrupt_type brcm_irq_type = {
1977 + typename: "MIPS",
1978 + startup: startup_brcm_irq,
1979 + shutdown: disable_brcm_irq,
1980 + enable: enable_brcm_irq,
1981 + disable: disable_brcm_irq,
1982 + ack: ack_brcm_irq,
1983 + end: end_brcm_irq,
1984 + NULL
1985 +};
1986 +
1987 +void __init
1988 +init_IRQ(void)
1989 +{
1990 + int i;
1991 +
1992 + for (i = 0; i < NR_IRQS; i++) {
1993 + irq_desc[i].status = IRQ_DISABLED;
1994 + irq_desc[i].action = 0;
1995 + irq_desc[i].depth = 1;
1996 + irq_desc[i].handler = &brcm_irq_type;
1997 + }
1998 +
1999 + set_except_vector(0, brcmIRQ);
2000 + change_c0_status(ST0_IM, ALLINTS);
2001 +
2002 +#ifdef CONFIG_REMOTE_DEBUG
2003 + printk("Breaking into debugger...\n");
2004 + set_debug_traps();
2005 + breakpoint();
2006 +#endif
2007 +}
2008 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
2009 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
2010 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2006-10-02 21:26:29.000000000 +0200
2011 @@ -0,0 +1,12 @@
2012 +#
2013 +# Makefile for the BCM947xx specific kernel interface routines
2014 +# under Linux.
2015 +#
2016 +EXTRA_CFLAGS += -fno-delayed-branch
2017 +USE_STANDARD_AS_RULE := true
2018 +
2019 +O_TARGET := brcm.o
2020 +
2021 +obj-y := int-handler.o irq.o
2022 +
2023 +include $(TOPDIR)/Rules.make
2024 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
2025 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
2026 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2006-10-02 21:19:59.000000000 +0200
2027 @@ -0,0 +1,159 @@
2028 +/*
2029 + * GPIO char driver
2030 + *
2031 + * Copyright 2005, Broadcom Corporation
2032 + * All Rights Reserved.
2033 + *
2034 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2035 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2036 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2037 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2038 + *
2039 + * $Id$
2040 + */
2041 +
2042 +#include <linux/module.h>
2043 +#include <linux/init.h>
2044 +#include <linux/fs.h>
2045 +#include <linux/miscdevice.h>
2046 +#include <asm/uaccess.h>
2047 +
2048 +#include <typedefs.h>
2049 +#include <osl.h>
2050 +#include <bcmutils.h>
2051 +#include <sbutils.h>
2052 +#include <bcmdevs.h>
2053 +
2054 +static sb_t *gpio_sbh;
2055 +static int gpio_major;
2056 +static devfs_handle_t gpio_dir;
2057 +static struct {
2058 + char *name;
2059 + devfs_handle_t handle;
2060 +} gpio_file[] = {
2061 + { "in", NULL },
2062 + { "out", NULL },
2063 + { "outen", NULL },
2064 + { "control", NULL }
2065 +};
2066 +
2067 +static int
2068 +gpio_open(struct inode *inode, struct file * file)
2069 +{
2070 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
2071 + return -ENODEV;
2072 +
2073 + MOD_INC_USE_COUNT;
2074 + return 0;
2075 +}
2076 +
2077 +static int
2078 +gpio_release(struct inode *inode, struct file * file)
2079 +{
2080 + MOD_DEC_USE_COUNT;
2081 + return 0;
2082 +}
2083 +
2084 +static ssize_t
2085 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
2086 +{
2087 + u32 val;
2088 +
2089 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2090 + case 0:
2091 + val = sb_gpioin(gpio_sbh);
2092 + break;
2093 + case 1:
2094 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2095 + break;
2096 + case 2:
2097 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2098 + break;
2099 + case 3:
2100 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2101 + break;
2102 + default:
2103 + return -ENODEV;
2104 + }
2105 +
2106 + if (put_user(val, (u32 *) buf))
2107 + return -EFAULT;
2108 +
2109 + return sizeof(val);
2110 +}
2111 +
2112 +static ssize_t
2113 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
2114 +{
2115 + u32 val;
2116 +
2117 + if (get_user(val, (u32 *) buf))
2118 + return -EFAULT;
2119 +
2120 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2121 + case 0:
2122 + return -EACCES;
2123 + case 1:
2124 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2125 + break;
2126 + case 2:
2127 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2128 + break;
2129 + case 3:
2130 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2131 + break;
2132 + default:
2133 + return -ENODEV;
2134 + }
2135 +
2136 + return sizeof(val);
2137 +}
2138 +
2139 +static struct file_operations gpio_fops = {
2140 + owner: THIS_MODULE,
2141 + open: gpio_open,
2142 + release: gpio_release,
2143 + read: gpio_read,
2144 + write: gpio_write,
2145 +};
2146 +
2147 +static int __init
2148 +gpio_init(void)
2149 +{
2150 + int i;
2151 +
2152 + if (!(gpio_sbh = sb_kattach()))
2153 + return -ENODEV;
2154 +
2155 + sb_gpiosetcore(gpio_sbh);
2156 +
2157 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
2158 + return gpio_major;
2159 +
2160 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
2161 +
2162 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
2163 + gpio_file[i].handle = devfs_register(gpio_dir,
2164 + gpio_file[i].name,
2165 + DEVFS_FL_DEFAULT, gpio_major, i,
2166 + S_IFCHR | S_IRUGO | S_IWUGO,
2167 + &gpio_fops, NULL);
2168 + }
2169 +
2170 + return 0;
2171 +}
2172 +
2173 +static void __exit
2174 +gpio_exit(void)
2175 +{
2176 + int i;
2177 +
2178 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
2179 + devfs_unregister(gpio_file[i].handle);
2180 + devfs_unregister(gpio_dir);
2181 + devfs_unregister_chrdev(gpio_major, "gpio");
2182 + sb_detach(gpio_sbh);
2183 +}
2184 +
2185 +module_init(gpio_init);
2186 +module_exit(gpio_exit);
2187 diff -urN linux.old/arch/mips/bcm947xx/hndchipc.c linux.dev/arch/mips/bcm947xx/hndchipc.c
2188 --- linux.old/arch/mips/bcm947xx/hndchipc.c 1970-01-01 01:00:00.000000000 +0100
2189 +++ linux.dev/arch/mips/bcm947xx/hndchipc.c 2006-10-02 21:19:59.000000000 +0200
2190 @@ -0,0 +1,158 @@
2191 +/*
2192 + * BCM47XX support code for some chipcommon (old extif) facilities (uart)
2193 + *
2194 + * Copyright 2006, Broadcom Corporation
2195 + * All Rights Reserved.
2196 + *
2197 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2198 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2199 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2200 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2201 + *
2202 + * $Id: hndchipc.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
2203 + */
2204 +
2205 +#include <typedefs.h>
2206 +#include <bcmdefs.h>
2207 +#include <osl.h>
2208 +#include <bcmutils.h>
2209 +#include <sbutils.h>
2210 +#include <bcmdevs.h>
2211 +#include <bcmnvram.h>
2212 +#include <sbconfig.h>
2213 +#include <sbextif.h>
2214 +#include <sbchipc.h>
2215 +#include <hndcpu.h>
2216 +
2217 +/*
2218 + * Returns TRUE if an external UART exists at the given base
2219 + * register.
2220 + */
2221 +static bool
2222 +BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
2223 +{
2224 + uint8 save_mcr, status1;
2225 +
2226 + save_mcr = R_REG(osh, &regs[UART_MCR]);
2227 + W_REG(osh, &regs[UART_MCR], UART_MCR_LOOP | 0x0a);
2228 + status1 = R_REG(osh, &regs[UART_MSR]) & 0xf0;
2229 + W_REG(osh, &regs[UART_MCR], save_mcr);
2230 +
2231 + return (status1 == 0x90);
2232 +}
2233 +
2234 +/*
2235 + * Initializes UART access. The callback function will be called once
2236 + * per found UART.
2237 + */
2238 +void
2239 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base,
2240 + uint reg_shift))
2241 +{
2242 + osl_t *osh;
2243 + void *regs;
2244 + ulong base;
2245 + uint irq;
2246 + int i, n;
2247 +
2248 + osh = sb_osh(sbh);
2249 +
2250 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
2251 + extifregs_t *eir = (extifregs_t *) regs;
2252 + sbconfig_t *sb;
2253 +
2254 + /* Determine external UART register base */
2255 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
2256 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
2257 +
2258 + /* Determine IRQ */
2259 + irq = sb_irq(sbh);
2260 +
2261 + /* Disable GPIO interrupt initially */
2262 + W_REG(osh, &eir->gpiointpolarity, 0);
2263 + W_REG(osh, &eir->gpiointmask, 0);
2264 +
2265 + /* Search for external UARTs */
2266 + n = 2;
2267 + for (i = 0; i < 2; i++) {
2268 + regs = (void *) REG_MAP(base + (i * 8), 8);
2269 + if (serial_exists(osh, regs)) {
2270 + /* Set GPIO 1 to be the external UART IRQ */
2271 + W_REG(osh, &eir->gpiointmask, 2);
2272 + /* XXXDetermine external UART clock */
2273 + if (add)
2274 + add(regs, irq, 13500000, 0);
2275 + }
2276 + }
2277 +
2278 + /* Add internal UART if enabled */
2279 + if (R_REG(osh, &eir->corecontrol) & CC_UE)
2280 + if (add)
2281 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
2282 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
2283 + chipcregs_t *cc = (chipcregs_t *) regs;
2284 + uint32 rev, cap, pll, baud_base, div;
2285 +
2286 + /* Determine core revision and capabilities */
2287 + rev = sb_corerev(sbh);
2288 + cap = R_REG(osh, &cc->capabilities);
2289 + pll = cap & CAP_PLL_MASK;
2290 +
2291 + /* Determine IRQ */
2292 + irq = sb_irq(sbh);
2293 +
2294 + if (pll == PLL_TYPE1) {
2295 + /* PLL clock */
2296 + baud_base = sb_clock_rate(pll,
2297 + R_REG(osh, &cc->clockcontrol_n),
2298 + R_REG(osh, &cc->clockcontrol_m2));
2299 + div = 1;
2300 + } else {
2301 + /* Fixed ALP clock */
2302 + if (rev >= 11 && rev != 15) {
2303 + baud_base = 20000000;
2304 + div = 1;
2305 + /* Set the override bit so we don't divide it */
2306 + W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
2307 + }
2308 + /* Internal backplane clock */
2309 + else if (rev >= 3) {
2310 + baud_base = sb_clock(sbh);
2311 + div = 2; /* Minimum divisor */
2312 + W_REG(osh, &cc->clkdiv,
2313 + ((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
2314 + }
2315 + /* Fixed internal backplane clock */
2316 + else {
2317 + baud_base = 88000000;
2318 + div = 48;
2319 + }
2320 +
2321 + /* Clock source depends on strapping if UartClkOverride is unset */
2322 + if ((rev > 0) &&
2323 + ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
2324 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
2325 + /* Internal divided backplane clock */
2326 + baud_base /= div;
2327 + } else {
2328 + /* Assume external clock of 1.8432 MHz */
2329 + baud_base = 1843200;
2330 + }
2331 + }
2332 + }
2333 +
2334 + /* Add internal UARTs */
2335 + n = cap & CAP_UARTS_MASK;
2336 + for (i = 0; i < n; i++) {
2337 + /* Register offset changed after revision 0 */
2338 + if (rev)
2339 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
2340 + else
2341 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
2342 +
2343 + if (add)
2344 + add(regs, irq, baud_base, 0);
2345 + }
2346 + }
2347 +}
2348 +
2349 diff -urN linux.old/arch/mips/bcm947xx/include/bcm4710.h linux.dev/arch/mips/bcm947xx/include/bcm4710.h
2350 --- linux.old/arch/mips/bcm947xx/include/bcm4710.h 1970-01-01 01:00:00.000000000 +0100
2351 +++ linux.dev/arch/mips/bcm947xx/include/bcm4710.h 2006-10-02 21:19:59.000000000 +0200
2352 @@ -0,0 +1,91 @@
2353 +/*
2354 + * BCM4710 address space map and definitions
2355 + * Think twice before adding to this file, this is not the kitchen sink
2356 + * These definitions are not guaranteed for all 47xx chips, only the 4710
2357 + *
2358 + * Copyright 2004, Broadcom Corporation
2359 + * All Rights Reserved.
2360 + *
2361 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2362 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2363 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2364 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2365 + *
2366 + * $Id: bcm4710.h,v 1.3 2004/09/27 07:23:30 tallest Exp $
2367 + */
2368 +
2369 +#ifndef _bcm4710_h_
2370 +#define _bcm4710_h_
2371 +
2372 +/* Address map */
2373 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2374 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2375 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2376 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2377 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2378 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2379 +
2380 +/* Core register space */
2381 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2382 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2383 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2384 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2385 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2386 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2387 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2388 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2389 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2390 +
2391 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2392 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2393 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2394 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2395 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2396 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2397 +
2398 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2399 +
2400 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2401 +
2402 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2403 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2404 +
2405 +#define SBFLAG_PCI 0
2406 +#define SBFLAG_ENET0 1
2407 +#define SBFLAG_ILINE20 2
2408 +#define SBFLAG_CODEC 3
2409 +#define SBFLAG_USB 4
2410 +#define SBFLAG_EXTIF 5
2411 +#define SBFLAG_ENET1 6
2412 +
2413 +#ifdef CONFIG_HWSIM
2414 +#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
2415 +#else
2416 +#define BCM4710_TRACE(trval)
2417 +#endif
2418 +
2419 +
2420 +/* BCM94702 CPCI -ExtIF used for LocalBus devs */
2421 +
2422 +#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
2423 +#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
2424 +#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
2425 +#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
2426 +#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
2427 +#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
2428 +#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
2429 +#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
2430 +
2431 +#define LED_REG(x) \
2432 + (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
2433 +
2434 +/*
2435 + * Reset function implemented in PLD. Read or write should trigger hard reset
2436 + */
2437 +#define SYS_HARD_RESET() \
2438 + { for (;;) \
2439 + *( (volatile unsigned char *)\
2440 + KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
2441 + }
2442 +
2443 +#endif /* _bcm4710_h_ */
2444 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdefs.h linux.dev/arch/mips/bcm947xx/include/bcmdefs.h
2445 --- linux.old/arch/mips/bcm947xx/include/bcmdefs.h 1970-01-01 01:00:00.000000000 +0100
2446 +++ linux.dev/arch/mips/bcm947xx/include/bcmdefs.h 2006-10-02 21:19:59.000000000 +0200
2447 @@ -0,0 +1,106 @@
2448 +/*
2449 + * Misc system wide definitions
2450 + *
2451 + * Copyright 2006, Broadcom Corporation
2452 + * All Rights Reserved.
2453 + *
2454 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2455 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2456 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2457 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2458 + * $Id: bcmdefs.h,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
2459 + */
2460 +
2461 +#ifndef _bcmdefs_h_
2462 +#define _bcmdefs_h_
2463 +
2464 +/*
2465 + * One doesn't need to include this file explicitly, gets included automatically if
2466 + * typedefs.h is included.
2467 + */
2468 +
2469 +/* Reclaiming text and data :
2470 + * The following macros specify special linker sections that can be reclaimed
2471 + * after a system is considered 'up'.
2472 + */
2473 +#if defined(__GNUC__) && defined(BCMRECLAIM)
2474 +extern bool bcmreclaimed;
2475 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data
2476 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn
2477 +#else /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2478 +#define BCMINITDATA(_data) _data
2479 +#define BCMINITFN(_fn) _fn
2480 +#define bcmreclaimed 0
2481 +#endif /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2482 +
2483 +/* Reclaim uninit functions if BCMNODOWN is defined */
2484 +/* and if they are not already removed by -gc-sections */
2485 +#ifdef BCMNODOWN
2486 +#define BCMUNINITFN(_fn) BCMINITFN(_fn)
2487 +#else
2488 +#define BCMUNINITFN(_fn) _fn
2489 +#endif
2490 +
2491 +#ifdef BCMRECLAIM
2492 +#define CONST
2493 +#else
2494 +#define CONST const
2495 +#endif /* BCMRECLAIM */
2496 +
2497 +/* Compatibility with old-style BCMRECLAIM */
2498 +#define BCMINIT(_id) _id
2499 +
2500 +
2501 +/* Put some library data/code into ROM to reduce RAM requirements */
2502 +#if defined(__GNUC__) && defined(BCMROMOFFLOAD)
2503 +#define BCMROMDATA(_data) __attribute__ ((__section__ (".datarom." #_data))) _data
2504 +#define BCMROMFN(_fn) __attribute__ ((__section__ (".textrom." #_fn))) _fn
2505 +#else
2506 +#define BCMROMDATA(_data) _data
2507 +#define BCMROMFN(_fn) _fn
2508 +#endif
2509 +
2510 +/* Bus types */
2511 +#define SB_BUS 0 /* Silicon Backplane */
2512 +#define PCI_BUS 1 /* PCI target */
2513 +#define PCMCIA_BUS 2 /* PCMCIA target */
2514 +#define SDIO_BUS 3 /* SDIO target */
2515 +#define JTAG_BUS 4 /* JTAG */
2516 +#define NO_BUS 0xFF /* Bus that does not support R/W REG */
2517 +
2518 +/* Allows optimization for single-bus support */
2519 +#ifdef BCMBUSTYPE
2520 +#define BUSTYPE(bus) (BCMBUSTYPE)
2521 +#else
2522 +#define BUSTYPE(bus) (bus)
2523 +#endif
2524 +
2525 +/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
2526 +#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
2527 +#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
2528 +#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
2529 +
2530 +#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
2531 +#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
2532 +#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
2533 +#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
2534 +
2535 +/* packet headroom necessary to accomodate the largest header in the system, (i.e TXOFF).
2536 + * By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
2537 + * There is a compile time check in wlc.c which ensure that this value is at least as big
2538 + * as TXOFF. This value is used in dma_rxfill (hnddma.c).
2539 + */
2540 +#define BCMEXTRAHDROOM 160
2541 +
2542 +/* Headroom required for dongle-to-host communication. Packets allocated
2543 + * locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
2544 + * leave this much room in front for low-level message headers which may
2545 + * be needed to get across the dongle bus to the host. (These messages
2546 + * don't go over the network, so room for the full WL header above would
2547 + * be a waste.)
2548 + */
2549 +#define BCMDONGLEHDRSZ 8
2550 +
2551 +
2552 +
2553 +#endif /* _bcmdefs_h_ */
2554 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs1.h linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h
2555 --- linux.old/arch/mips/bcm947xx/include/bcmdevs1.h 1970-01-01 01:00:00.000000000 +0100
2556 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h 2006-10-02 21:19:59.000000000 +0200
2557 @@ -0,0 +1,391 @@
2558 +/*
2559 + * Broadcom device-specific manifest constants.
2560 + *
2561 + * Copyright 2005, Broadcom Corporation
2562 + * All Rights Reserved.
2563 + *
2564 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2565 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2566 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2567 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2568 + * $Id$
2569 + */
2570 +
2571 +#ifndef _BCMDEVS_H
2572 +#define _BCMDEVS_H
2573 +
2574 +
2575 +/* Known PCI vendor Id's */
2576 +#define VENDOR_EPIGRAM 0xfeda
2577 +#define VENDOR_BROADCOM 0x14e4
2578 +#define VENDOR_3COM 0x10b7
2579 +#define VENDOR_NETGEAR 0x1385
2580 +#define VENDOR_DIAMOND 0x1092
2581 +#define VENDOR_DELL 0x1028
2582 +#define VENDOR_HP 0x0e11
2583 +#define VENDOR_APPLE 0x106b
2584 +
2585 +/* PCI Device Id's */
2586 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2587 +#define BCM4211_DEVICE_ID 0x4211
2588 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2589 +#define BCM4231_DEVICE_ID 0x4231
2590 +
2591 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2592 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2593 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2594 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2595 +
2596 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2597 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2598 +
2599 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2600 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2601 +
2602 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2603 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
2604 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
2605 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
2606 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
2607 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
2608 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
2609 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
2610 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
2611 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
2612 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
2613 +
2614 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
2615 +
2616 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
2617 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
2618 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
2619 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
2620 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
2621 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
2622 +
2623 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
2624 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
2625 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
2626 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
2627 +
2628 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
2629 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
2630 +
2631 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
2632 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
2633 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
2634 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
2635 +
2636 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
2637 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
2638 +#define BCM4306_D11G_ID2 0x4325
2639 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
2640 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
2641 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
2642 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
2643 +
2644 +#define BCM4309_PKG_ID 1 /* 4309 package id */
2645 +
2646 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
2647 +#define BCM4303_PKG_ID 2 /* 4303 package id */
2648 +
2649 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
2650 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
2651 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
2652 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
2653 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
2654 +
2655 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
2656 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
2657 +
2658 +
2659 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
2660 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
2661 +
2662 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
2663 +
2664 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
2665 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
2666 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
2667 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
2668 +
2669 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
2670 +
2671 +/* Address map */
2672 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2673 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2674 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2675 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2676 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2677 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2678 +
2679 +/* Core register space */
2680 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2681 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2682 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2683 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2684 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2685 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2686 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2687 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2688 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2689 +
2690 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2691 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2692 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2693 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2694 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2695 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2696 +
2697 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2698 +
2699 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2700 +
2701 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2702 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2703 +
2704 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
2705 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
2706 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
2707 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
2708 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
2709 +
2710 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
2711 +
2712 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
2713 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
2714 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
2715 +
2716 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
2717 +
2718 +/* PCMCIA vendor Id's */
2719 +
2720 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
2721 +
2722 +/* SDIO vendor Id's */
2723 +#define VENDOR_BROADCOM_SDIO 0x00BF
2724 +
2725 +
2726 +/* boardflags */
2727 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
2728 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
2729 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
2730 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
2731 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
2732 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
2733 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
2734 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
2735 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
2736 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
2737 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
2738 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
2739 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
2740 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
2741 +
2742 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
2743 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
2744 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
2745 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
2746 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
2747 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
2748 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
2749 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
2750 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
2751 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
2752 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
2753 +
2754 +/* Bus types */
2755 +#define SB_BUS 0 /* Silicon Backplane */
2756 +#define PCI_BUS 1 /* PCI target */
2757 +#define PCMCIA_BUS 2 /* PCMCIA target */
2758 +#define SDIO_BUS 3 /* SDIO target */
2759 +#define JTAG_BUS 4 /* JTAG */
2760 +
2761 +/* Allows optimization for single-bus support */
2762 +#ifdef BCMBUSTYPE
2763 +#define BUSTYPE(bus) (BCMBUSTYPE)
2764 +#else
2765 +#define BUSTYPE(bus) (bus)
2766 +#endif
2767 +
2768 +/* power control defines */
2769 +#define PLL_DELAY 150 /* us pll on delay */
2770 +#define FREF_DELAY 200 /* us fref change delay */
2771 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
2772 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
2773 +
2774 +/* Reference Board Types */
2775 +
2776 +#define BU4710_BOARD 0x0400
2777 +#define VSIM4710_BOARD 0x0401
2778 +#define QT4710_BOARD 0x0402
2779 +
2780 +#define BU4610_BOARD 0x0403
2781 +#define VSIM4610_BOARD 0x0404
2782 +
2783 +#define BU4307_BOARD 0x0405
2784 +#define BCM94301CB_BOARD 0x0406
2785 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
2786 +#define BCM94301MP_BOARD 0x0407
2787 +#define BCM94307MP_BOARD 0x0408
2788 +#define BCMAP4307_BOARD 0x0409
2789 +
2790 +#define BU4309_BOARD 0x040a
2791 +#define BCM94309CB_BOARD 0x040b
2792 +#define BCM94309MP_BOARD 0x040c
2793 +#define BCM4309AP_BOARD 0x040d
2794 +
2795 +#define BCM94302MP_BOARD 0x040e
2796 +
2797 +#define VSIM4310_BOARD 0x040f
2798 +#define BU4711_BOARD 0x0410
2799 +#define BCM94310U_BOARD 0x0411
2800 +#define BCM94310AP_BOARD 0x0412
2801 +#define BCM94310MP_BOARD 0x0414
2802 +
2803 +#define BU4306_BOARD 0x0416
2804 +#define BCM94306CB_BOARD 0x0417
2805 +#define BCM94306MP_BOARD 0x0418
2806 +
2807 +#define BCM94710D_BOARD 0x041a
2808 +#define BCM94710R1_BOARD 0x041b
2809 +#define BCM94710R4_BOARD 0x041c
2810 +#define BCM94710AP_BOARD 0x041d
2811 +
2812 +
2813 +#define BU2050_BOARD 0x041f
2814 +
2815 +
2816 +#define BCM94309G_BOARD 0x0421
2817 +
2818 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
2819 +
2820 +#define BU4704_BOARD 0x0423
2821 +#define BU4702_BOARD 0x0424
2822 +
2823 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
2824 +
2825 +#define BU4317_BOARD 0x0426
2826 +
2827 +
2828 +#define BCM94702MN_BOARD 0x0428
2829 +
2830 +/* BCM4702 1U CompactPCI Board */
2831 +#define BCM94702CPCI_BOARD 0x0429
2832 +
2833 +/* BCM4702 with BCM95380 VLAN Router */
2834 +#define BCM95380RR_BOARD 0x042a
2835 +
2836 +/* cb4306 with SiGe PA */
2837 +#define BCM94306CBSG_BOARD 0x042b
2838 +
2839 +/* mp4301 with 2050 radio */
2840 +#define BCM94301MPL_BOARD 0x042c
2841 +
2842 +/* cb4306 with SiGe PA */
2843 +#define PCSG94306_BOARD 0x042d
2844 +
2845 +/* bu4704 with sdram */
2846 +#define BU4704SD_BOARD 0x042e
2847 +
2848 +/* Dual 11a/11g Router */
2849 +#define BCM94704AGR_BOARD 0x042f
2850 +
2851 +/* 11a-only minipci */
2852 +#define BCM94308MP_BOARD 0x0430
2853 +
2854 +
2855 +
2856 +/* BCM94317 boards */
2857 +#define BCM94317CB_BOARD 0x0440
2858 +#define BCM94317MP_BOARD 0x0441
2859 +#define BCM94317PCMCIA_BOARD 0x0442
2860 +#define BCM94317SDIO_BOARD 0x0443
2861 +
2862 +#define BU4712_BOARD 0x0444
2863 +#define BU4712SD_BOARD 0x045d
2864 +#define BU4712L_BOARD 0x045f
2865 +
2866 +/* BCM4712 boards */
2867 +#define BCM94712AP_BOARD 0x0445
2868 +#define BCM94712P_BOARD 0x0446
2869 +
2870 +/* BCM4318 boards */
2871 +#define BU4318_BOARD 0x0447
2872 +#define CB4318_BOARD 0x0448
2873 +#define MPG4318_BOARD 0x0449
2874 +#define MP4318_BOARD 0x044a
2875 +#define SD4318_BOARD 0x044b
2876 +
2877 +/* BCM63XX boards */
2878 +#define BCM96338_BOARD 0x6338
2879 +#define BCM96345_BOARD 0x6345
2880 +#define BCM96348_BOARD 0x6348
2881 +
2882 +/* Another mp4306 with SiGe */
2883 +#define BCM94306P_BOARD 0x044c
2884 +
2885 +/* CF-like 4317 modules */
2886 +#define BCM94317CF_BOARD 0x044d
2887 +
2888 +/* mp4303 */
2889 +#define BCM94303MP_BOARD 0x044e
2890 +
2891 +/* mpsgh4306 */
2892 +#define BCM94306MPSGH_BOARD 0x044f
2893 +
2894 +/* BRCM 4306 w/ Front End Modules */
2895 +#define BCM94306MPM 0x0450
2896 +#define BCM94306MPL 0x0453
2897 +
2898 +/* 4712agr */
2899 +#define BCM94712AGR_BOARD 0x0451
2900 +
2901 +/* The real CF 4317 board */
2902 +#define CFI4317_BOARD 0x0452
2903 +
2904 +/* pcmcia 4303 */
2905 +#define PC4303_BOARD 0x0454
2906 +
2907 +/* 5350K */
2908 +#define BCM95350K_BOARD 0x0455
2909 +
2910 +/* 5350R */
2911 +#define BCM95350R_BOARD 0x0456
2912 +
2913 +/* 4306mplna */
2914 +#define BCM94306MPLNA_BOARD 0x0457
2915 +
2916 +/* 4320 boards */
2917 +#define BU4320_BOARD 0x0458
2918 +#define BU4320S_BOARD 0x0459
2919 +#define BCM94320PH_BOARD 0x045a
2920 +
2921 +/* 4306mph */
2922 +#define BCM94306MPH_BOARD 0x045b
2923 +
2924 +/* 4306pciv */
2925 +#define BCM94306PCIV_BOARD 0x045c
2926 +
2927 +#define BU4712SD_BOARD 0x045d
2928 +
2929 +#define BCM94320PFLSH_BOARD 0x045e
2930 +
2931 +#define BU4712L_BOARD 0x045f
2932 +#define BCM94712LGR_BOARD 0x0460
2933 +#define BCM94320R_BOARD 0x0461
2934 +
2935 +#define BU5352_BOARD 0x0462
2936 +
2937 +#define BCM94318MPGH_BOARD 0x0463
2938 +
2939 +
2940 +#define BCM95352GR_BOARD 0x0467
2941 +
2942 +/* bcm95351agr */
2943 +#define BCM95351AGR_BOARD 0x0470
2944 +
2945 +/* # of GPIO pins */
2946 +#define GPIO_NUMPINS 16
2947 +
2948 +#endif /* _BCMDEVS_H */
2949 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
2950 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
2951 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-10-02 21:19:59.000000000 +0200
2952 @@ -0,0 +1,369 @@
2953 +/*
2954 + * Broadcom device-specific manifest constants.
2955 + *
2956 + * Copyright 2006, Broadcom Corporation
2957 + * All Rights Reserved.
2958 + *
2959 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2960 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2961 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2962 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2963 + * $Id: bcmdevs.h,v 1.1.1.17 2006/04/15 01:29:08 michael Exp $
2964 + */
2965 +
2966 +#ifndef _BCMDEVS_H
2967 +#define _BCMDEVS_H
2968 +
2969 +#include "bcm4710.h"
2970 +
2971 +/* Known PCI vendor Id's */
2972 +#define VENDOR_EPIGRAM 0xfeda
2973 +#define VENDOR_BROADCOM 0x14e4
2974 +#define VENDOR_3COM 0x10b7
2975 +#define VENDOR_NETGEAR 0x1385
2976 +#define VENDOR_DIAMOND 0x1092
2977 +#define VENDOR_DELL 0x1028
2978 +#define VENDOR_HP 0x0e11
2979 +#define VENDOR_APPLE 0x106b
2980 +
2981 +/* PCI Device Id's */
2982 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2983 +#define BCM4211_DEVICE_ID 0x4211
2984 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2985 +#define BCM4231_DEVICE_ID 0x4231
2986 +
2987 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2988 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2989 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2990 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2991 +
2992 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2993 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2994 +
2995 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2996 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2997 +
2998 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2999 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
3000 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
3001 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
3002 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
3003 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
3004 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
3005 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
3006 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
3007 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
3008 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
3009 +#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
3010 +#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
3011 +#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
3012 +
3013 +#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
3014 +#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
3015 +
3016 +#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */
3017 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
3018 +
3019 +#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
3020 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
3021 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
3022 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
3023 +
3024 +#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
3025 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
3026 +#define BCM4306_D11G_ID2 0x4325
3027 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
3028 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
3029 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
3030 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
3031 +
3032 +#define BCM4309_PKG_ID 1 /* 4309 package id */
3033 +
3034 +#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
3035 +#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
3036 +#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
3037 +#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
3038 +
3039 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
3040 +#define BCM4303_PKG_ID 2 /* 4303 package id */
3041 +
3042 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
3043 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
3044 +
3045 +#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
3046 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
3047 +
3048 +#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */
3049 +#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
3050 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
3051 +#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
3052 +
3053 +#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */
3054 +#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
3055 +#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Hgz band id */
3056 +#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
3057 +
3058 +#define BCM4331_CHIP_ID 0x4331 /* 4331 chip common chipid */
3059 +#define BCM4331_D11N2G_ID 0x4330 /* 4331 802.11n 2.4Ghz band id */
3060 +#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
3061 +#define BCM4331_D11N5G_ID 0x4332 /* 4331 802.11n 5Ghz band id */
3062 +
3063 +#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
3064 +#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
3065 +#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
3066 +
3067 +#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
3068 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
3069 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
3070 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
3071 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
3072 +
3073 +#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
3074 +#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
3075 +#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
3076 +
3077 +#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
3078 +
3079 +#define BCM4328_CHIP_ID 0x4328 /* bcm4328 chipcommon chipid */
3080 +
3081 +#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
3082 +#define BCM43XX_JTAGM_ID 0x43f1 /* 43xx jtagm device id */
3083 +#define BCM43XXOLD_JTAGM_ID 0x4331 /* 43xx old jtagm device id */
3084 +
3085 +#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
3086 +#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
3087 +
3088 +#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
3089 +
3090 +#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
3091 +
3092 +/* PCMCIA vendor Id's */
3093 +
3094 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
3095 +
3096 +/* SDIO vendor Id's */
3097 +#define VENDOR_BROADCOM_SDIO 0x00BF
3098 +
3099 +
3100 +/* boardflags */
3101 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
3102 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
3103 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
3104 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
3105 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
3106 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
3107 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
3108 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
3109 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
3110 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
3111 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
3112 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
3113 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
3114 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
3115 +
3116 +/* boardflags2 */
3117 +#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */
3118 +#define BFL2_SSWITCH_AVAIL 0x00000002 /* This board has a superswitch for > 2 antennas */
3119 +#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits TX Power Control to be enabled */
3120 +
3121 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
3122 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
3123 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
3124 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
3125 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
3126 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
3127 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
3128 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
3129 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
3130 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
3131 +
3132 +/* power control defines */
3133 +#define PLL_DELAY 150 /* us pll on delay */
3134 +#define FREF_DELAY 200 /* us fref change delay */
3135 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
3136 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
3137 +
3138 +/* Reference Board Types */
3139 +
3140 +#define BU4710_BOARD 0x0400
3141 +#define VSIM4710_BOARD 0x0401
3142 +#define QT4710_BOARD 0x0402
3143 +
3144 +#define BU4309_BOARD 0x040a
3145 +#define BCM94309CB_BOARD 0x040b
3146 +#define BCM94309MP_BOARD 0x040c
3147 +#define BCM4309AP_BOARD 0x040d
3148 +
3149 +#define BCM94302MP_BOARD 0x040e
3150 +
3151 +#define BU4306_BOARD 0x0416
3152 +#define BCM94306CB_BOARD 0x0417
3153 +#define BCM94306MP_BOARD 0x0418
3154 +
3155 +#define BCM94710D_BOARD 0x041a
3156 +#define BCM94710R1_BOARD 0x041b
3157 +#define BCM94710R4_BOARD 0x041c
3158 +#define BCM94710AP_BOARD 0x041d
3159 +
3160 +#define BU2050_BOARD 0x041f
3161 +
3162 +
3163 +#define BCM94309G_BOARD 0x0421
3164 +
3165 +#define BU4704_BOARD 0x0423
3166 +#define BU4702_BOARD 0x0424
3167 +
3168 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
3169 +
3170 +
3171 +#define BCM94702MN_BOARD 0x0428
3172 +
3173 +/* BCM4702 1U CompactPCI Board */
3174 +#define BCM94702CPCI_BOARD 0x0429
3175 +
3176 +/* BCM4702 with BCM95380 VLAN Router */
3177 +#define BCM95380RR_BOARD 0x042a
3178 +
3179 +/* cb4306 with SiGe PA */
3180 +#define BCM94306CBSG_BOARD 0x042b
3181 +
3182 +/* cb4306 with SiGe PA */
3183 +#define PCSG94306_BOARD 0x042d
3184 +
3185 +/* bu4704 with sdram */
3186 +#define BU4704SD_BOARD 0x042e
3187 +
3188 +/* Dual 11a/11g Router */
3189 +#define BCM94704AGR_BOARD 0x042f
3190 +
3191 +/* 11a-only minipci */
3192 +#define BCM94308MP_BOARD 0x0430
3193 +
3194 +
3195 +
3196 +#define BU4712_BOARD 0x0444
3197 +#define BU4712SD_BOARD 0x045d
3198 +#define BU4712L_BOARD 0x045f
3199 +
3200 +/* BCM4712 boards */
3201 +#define BCM94712AP_BOARD 0x0445
3202 +#define BCM94712P_BOARD 0x0446
3203 +
3204 +/* BCM4318 boards */
3205 +#define BU4318_BOARD 0x0447
3206 +#define CB4318_BOARD 0x0448
3207 +#define MPG4318_BOARD 0x0449
3208 +#define MP4318_BOARD 0x044a
3209 +#define SD4318_BOARD 0x044b
3210 +
3211 +/* BCM63XX boards */
3212 +#define BCM96338_BOARD 0x6338
3213 +#define BCM96348_BOARD 0x6348
3214 +
3215 +/* Another mp4306 with SiGe */
3216 +#define BCM94306P_BOARD 0x044c
3217 +
3218 +/* mp4303 */
3219 +#define BCM94303MP_BOARD 0x044e
3220 +
3221 +/* mpsgh4306 */
3222 +#define BCM94306MPSGH_BOARD 0x044f
3223 +
3224 +/* BRCM 4306 w/ Front End Modules */
3225 +#define BCM94306MPM 0x0450
3226 +#define BCM94306MPL 0x0453
3227 +
3228 +/* 4712agr */
3229 +#define BCM94712AGR_BOARD 0x0451
3230 +
3231 +/* pcmcia 4303 */
3232 +#define PC4303_BOARD 0x0454
3233 +
3234 +/* 5350K */
3235 +#define BCM95350K_BOARD 0x0455
3236 +
3237 +/* 5350R */
3238 +#define BCM95350R_BOARD 0x0456
3239 +
3240 +/* 4306mplna */
3241 +#define BCM94306MPLNA_BOARD 0x0457
3242 +
3243 +/* 4320 boards */
3244 +#define BU4320_BOARD 0x0458
3245 +#define BU4320S_BOARD 0x0459
3246 +#define BCM94320PH_BOARD 0x045a
3247 +
3248 +/* 4306mph */
3249 +#define BCM94306MPH_BOARD 0x045b
3250 +
3251 +/* 4306pciv */
3252 +#define BCM94306PCIV_BOARD 0x045c
3253 +
3254 +#define BU4712SD_BOARD 0x045d
3255 +
3256 +#define BCM94320PFLSH_BOARD 0x045e
3257 +
3258 +#define BU4712L_BOARD 0x045f
3259 +#define BCM94712LGR_BOARD 0x0460
3260 +#define BCM94320R_BOARD 0x0461
3261 +
3262 +#define BU5352_BOARD 0x0462
3263 +
3264 +#define BCM94318MPGH_BOARD 0x0463
3265 +
3266 +#define BU4311_BOARD 0x0464
3267 +#define BCM94311MC_BOARD 0x0465
3268 +#define BCM94311MCAG_BOARD 0x0466
3269 +
3270 +#define BCM95352GR_BOARD 0x0467
3271 +
3272 +/* bcm95351agr */
3273 +#define BCM95351AGR_BOARD 0x0470
3274 +
3275 +/* bcm94704mpcb */
3276 +#define BCM94704MPCB_BOARD 0x0472
3277 +
3278 +/* 4785 boards */
3279 +#define BU4785_BOARD 0x0478
3280 +
3281 +/* 4321 boards */
3282 +#define BU4321_BOARD 0x046b
3283 +#define BU4321E_BOARD 0x047c
3284 +#define MP4321_BOARD 0x046c
3285 +#define CB2_4321_BOARD 0x046d
3286 +#define MC4321_BOARD 0x046e
3287 +
3288 +/* # of GPIO pins */
3289 +#define GPIO_NUMPINS 16
3290 +
3291 +/* radio ID codes */
3292 +#define NORADIO_ID 0xe4f5
3293 +#define NORADIO_IDCODE 0x4e4f5246
3294 +
3295 +#define BCM2050_ID 0x2050
3296 +#define BCM2050_IDCODE 0x02050000
3297 +#define BCM2050A0_IDCODE 0x1205017f
3298 +#define BCM2050A1_IDCODE 0x2205017f
3299 +#define BCM2050R8_IDCODE 0x8205017f
3300 +
3301 +#define BCM2055_ID 0x2055
3302 +#define BCM2055_IDCODE 0x02055000
3303 +#define BCM2055A0_IDCODE 0x1205517f
3304 +
3305 +#define BCM2060_ID 0x2060
3306 +#define BCM2060_IDCODE 0x02060000
3307 +#define BCM2060WW_IDCODE 0x1206017f
3308 +
3309 +#define BCM2062_ID 0x2062
3310 +#define BCM2062_IDCODE 0x02062000
3311 +#define BCM2062A0_IDCODE 0x0206217f
3312 +
3313 +/* parts of an idcode: */
3314 +#define IDCODE_MFG_MASK 0x00000fff
3315 +#define IDCODE_MFG_SHIFT 0
3316 +#define IDCODE_ID_MASK 0x0ffff000
3317 +#define IDCODE_ID_SHIFT 12
3318 +#define IDCODE_REV_MASK 0xf0000000
3319 +#define IDCODE_REV_SHIFT 28
3320 +
3321 +#endif /* _BCMDEVS_H */
3322 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
3323 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
3324 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-10-02 21:19:59.000000000 +0200
3325 @@ -0,0 +1,198 @@
3326 +/*
3327 + * local version of endian.h - byte order defines
3328 + *
3329 + * Copyright 2006, Broadcom Corporation
3330 + * All Rights Reserved.
3331 + *
3332 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3333 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3334 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3335 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3336 + *
3337 + * $Id: bcmendian.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
3338 +*/
3339 +
3340 +#ifndef _BCMENDIAN_H_
3341 +#define _BCMENDIAN_H_
3342 +
3343 +#include <typedefs.h>
3344 +
3345 +/* Byte swap a 16 bit value */
3346 +#define BCMSWAP16(val) \
3347 + ((uint16)(\
3348 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
3349 + (((uint16)(val) & (uint16)0xff00U) >> 8)))
3350 +
3351 +/* Byte swap a 32 bit value */
3352 +#define BCMSWAP32(val) \
3353 + ((uint32)(\
3354 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
3355 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
3356 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
3357 + (((uint32)(val) & (uint32)0xff000000UL) >> 24)))
3358 +
3359 +/* 2 Byte swap a 32 bit value */
3360 +#define BCMSWAP32BY16(val) \
3361 + ((uint32)(\
3362 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
3363 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16)))
3364 +
3365 +
3366 +static INLINE uint16
3367 +bcmswap16(uint16 val)
3368 +{
3369 + return BCMSWAP16(val);
3370 +}
3371 +
3372 +static INLINE uint32
3373 +bcmswap32(uint32 val)
3374 +{
3375 + return BCMSWAP32(val);
3376 +}
3377 +
3378 +static INLINE uint32
3379 +bcmswap32by16(uint32 val)
3380 +{
3381 + return BCMSWAP32BY16(val);
3382 +}
3383 +
3384 +/* buf - start of buffer of shorts to swap */
3385 +/* len - byte length of buffer */
3386 +static INLINE void
3387 +bcmswap16_buf(uint16 *buf, uint len)
3388 +{
3389 + len = len/2;
3390 +
3391 + while (len--) {
3392 + *buf = bcmswap16(*buf);
3393 + buf++;
3394 + }
3395 +}
3396 +
3397 +#ifndef hton16
3398 +#ifndef IL_BIGENDIAN
3399 +#define HTON16(i) BCMSWAP16(i)
3400 +#define hton16(i) bcmswap16(i)
3401 +#define hton32(i) bcmswap32(i)
3402 +#define ntoh16(i) bcmswap16(i)
3403 +#define ntoh32(i) bcmswap32(i)
3404 +#define ltoh16(i) (i)
3405 +#define ltoh32(i) (i)
3406 +#define htol16(i) (i)
3407 +#define htol32(i) (i)
3408 +#else
3409 +#define HTON16(i) (i)
3410 +#define hton16(i) (i)
3411 +#define hton32(i) (i)
3412 +#define ntoh16(i) (i)
3413 +#define ntoh32(i) (i)
3414 +#define ltoh16(i) bcmswap16(i)
3415 +#define ltoh32(i) bcmswap32(i)
3416 +#define htol16(i) bcmswap16(i)
3417 +#define htol32(i) bcmswap32(i)
3418 +#endif /* IL_BIGENDIAN */
3419 +#endif /* hton16 */
3420 +
3421 +#ifndef IL_BIGENDIAN
3422 +#define ltoh16_buf(buf, i)
3423 +#define htol16_buf(buf, i)
3424 +#else
3425 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3426 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3427 +#endif /* IL_BIGENDIAN */
3428 +
3429 +/*
3430 +* store 16-bit value to unaligned little endian byte array.
3431 +*/
3432 +static INLINE void
3433 +htol16_ua_store(uint16 val, uint8 *bytes)
3434 +{
3435 + bytes[0] = val&0xff;
3436 + bytes[1] = val>>8;
3437 +}
3438 +
3439 +/*
3440 +* store 32-bit value to unaligned little endian byte array.
3441 +*/
3442 +static INLINE void
3443 +htol32_ua_store(uint32 val, uint8 *bytes)
3444 +{
3445 + bytes[0] = val&0xff;
3446 + bytes[1] = (val>>8)&0xff;
3447 + bytes[2] = (val>>16)&0xff;
3448 + bytes[3] = val>>24;
3449 +}
3450 +
3451 +/*
3452 +* store 16-bit value to unaligned network(big) endian byte array.
3453 +*/
3454 +static INLINE void
3455 +hton16_ua_store(uint16 val, uint8 *bytes)
3456 +{
3457 + bytes[1] = val&0xff;
3458 + bytes[0] = val>>8;
3459 +}
3460 +
3461 +/*
3462 +* store 32-bit value to unaligned network(big) endian byte array.
3463 +*/
3464 +static INLINE void
3465 +hton32_ua_store(uint32 val, uint8 *bytes)
3466 +{
3467 + bytes[3] = val&0xff;
3468 + bytes[2] = (val>>8)&0xff;
3469 + bytes[1] = (val>>16)&0xff;
3470 + bytes[0] = val>>24;
3471 +}
3472 +
3473 +/*
3474 +* load 16-bit value from unaligned little endian byte array.
3475 +*/
3476 +static INLINE uint16
3477 +ltoh16_ua(void *bytes)
3478 +{
3479 + return (((uint8*)bytes)[1]<<8)+((uint8 *)bytes)[0];
3480 +}
3481 +
3482 +/*
3483 +* load 32-bit value from unaligned little endian byte array.
3484 +*/
3485 +static INLINE uint32
3486 +ltoh32_ua(void *bytes)
3487 +{
3488 + return (((uint8*)bytes)[3]<<24)+(((uint8*)bytes)[2]<<16)+
3489 + (((uint8*)bytes)[1]<<8)+((uint8*)bytes)[0];
3490 +}
3491 +
3492 +/*
3493 +* load 16-bit value from unaligned big(network) endian byte array.
3494 +*/
3495 +static INLINE uint16
3496 +ntoh16_ua(void *bytes)
3497 +{
3498 + return (((uint8*)bytes)[0]<<8)+((uint8*)bytes)[1];
3499 +}
3500 +
3501 +/*
3502 +* load 32-bit value from unaligned big(network) endian byte array.
3503 +*/
3504 +static INLINE uint32
3505 +ntoh32_ua(void *bytes)
3506 +{
3507 + return (((uint8*)bytes)[0]<<24)+(((uint8*)bytes)[1]<<16)+
3508 + (((uint8*)bytes)[2]<<8)+((uint8*)bytes)[3];
3509 +}
3510 +
3511 +#define ltoh_ua(ptr) (\
3512 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3513 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
3514 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
3515 +)
3516 +
3517 +#define ntoh_ua(ptr) (\
3518 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3519 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
3520 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
3521 +)
3522 +
3523 +#endif /* _BCMENDIAN_H_ */
3524 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
3525 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
3526 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2006-10-02 21:19:59.000000000 +0200
3527 @@ -0,0 +1,159 @@
3528 +/*
3529 + * NVRAM variable manipulation
3530 + *
3531 + * Copyright 2006, Broadcom Corporation
3532 + * All Rights Reserved.
3533 + *
3534 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3535 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3536 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3537 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3538 + *
3539 + * $Id: bcmnvram.h,v 1.17 2006/03/02 12:33:44 honor Exp $
3540 + */
3541 +
3542 +#ifndef _bcmnvram_h_
3543 +#define _bcmnvram_h_
3544 +
3545 +#ifndef _LANGUAGE_ASSEMBLY
3546 +
3547 +#include <typedefs.h>
3548 +#include <bcmdefs.h>
3549 +
3550 +struct nvram_header {
3551 + uint32 magic;
3552 + uint32 len;
3553 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
3554 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
3555 + uint32 config_ncdl; /* ncdl values for memc */
3556 +};
3557 +
3558 +struct nvram_tuple {
3559 + char *name;
3560 + char *value;
3561 + struct nvram_tuple *next;
3562 +};
3563 +
3564 +/*
3565 + * Initialize NVRAM access. May be unnecessary or undefined on certain
3566 + * platforms.
3567 + */
3568 +extern int nvram_init(void *sbh);
3569 +
3570 +/*
3571 + * Disable NVRAM access. May be unnecessary or undefined on certain
3572 + * platforms.
3573 + */
3574 +extern void nvram_exit(void *sbh);
3575 +
3576 +/*
3577 + * Get the value of an NVRAM variable. The pointer returned may be
3578 + * invalid after a set.
3579 + * @param name name of variable to get
3580 + * @return value of variable or NULL if undefined
3581 + */
3582 +extern char * nvram_get(const char *name);
3583 +
3584 +/*
3585 + * Read the reset GPIO value from the nvram and set the GPIO
3586 + * as input
3587 + */
3588 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
3589 +extern int BCMINITFN(nvram_gpio_init)(const char *name, void *sbh);
3590 +extern int BCMINITFN(nvram_gpio_set)(const char *name, void *sbh, int type);
3591 +
3592 +/*
3593 + * Get the value of an NVRAM variable.
3594 + * @param name name of variable to get
3595 + * @return value of variable or NUL if undefined
3596 + */
3597 +#define nvram_safe_get(name) (nvram_get(name) ? : "")
3598 +
3599 +#define nvram_safe_unset(name) ({ \
3600 + if(nvram_get(name)) \
3601 + nvram_unset(name); \
3602 +})
3603 +
3604 +#define nvram_safe_set(name, value) ({ \
3605 + if(!nvram_get(name) || strcmp(nvram_get(name), value)) \
3606 + nvram_set(name, value); \
3607 +})
3608 +
3609 +/*
3610 + * Match an NVRAM variable.
3611 + * @param name name of variable to match
3612 + * @param match value to compare against value of variable
3613 + * @return TRUE if variable is defined and its value is string equal
3614 + * to match or FALSE otherwise
3615 + */
3616 +static INLINE int
3617 +nvram_match(char *name, char *match) {
3618 + const char *value = nvram_get(name);
3619 + return (value && !strcmp(value, match));
3620 +}
3621 +
3622 +/*
3623 + * Inversely match an NVRAM variable.
3624 + * @param name name of variable to match
3625 + * @param match value to compare against value of variable
3626 + * @return TRUE if variable is defined and its value is not string
3627 + * equal to invmatch or FALSE otherwise
3628 + */
3629 +static INLINE int
3630 +nvram_invmatch(char *name, char *invmatch) {
3631 + const char *value = nvram_get(name);
3632 + return (value && strcmp(value, invmatch));
3633 +}
3634 +
3635 +/*
3636 + * Set the value of an NVRAM variable. The name and value strings are
3637 + * copied into private storage. Pointers to previously set values
3638 + * may become invalid. The new value may be immediately
3639 + * retrieved but will not be permanently stored until a commit.
3640 + * @param name name of variable to set
3641 + * @param value value of variable
3642 + * @return 0 on success and errno on failure
3643 + */
3644 +extern int nvram_set(const char *name, const char *value);
3645 +
3646 +/*
3647 + * Unset an NVRAM variable. Pointers to previously set values
3648 + * remain valid until a set.
3649 + * @param name name of variable to unset
3650 + * @return 0 on success and errno on failure
3651 + * NOTE: use nvram_commit to commit this change to flash.
3652 + */
3653 +extern int nvram_unset(const char *name);
3654 +
3655 +/*
3656 + * Commit NVRAM variables to permanent storage. All pointers to values
3657 + * may be invalid after a commit.
3658 + * NVRAM values are undefined after a commit.
3659 + * @return 0 on success and errno on failure
3660 + */
3661 +extern int nvram_commit(void);
3662 +
3663 +/*
3664 + * Get all NVRAM variables (format name=value\0 ... \0\0).
3665 + * @param buf buffer to store variables
3666 + * @param count size of buffer in bytes
3667 + * @return 0 on success and errno on failure
3668 + */
3669 +extern int nvram_getall(char *buf, int count);
3670 +
3671 +extern int file2nvram(char *filename, char *varname);
3672 +extern int nvram2file(char *varname, char *filename);
3673 +
3674 +#endif /* _LANGUAGE_ASSEMBLY */
3675 +
3676 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
3677 +#define NVRAM_CLEAR_MAGIC 0x0
3678 +#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
3679 +#define NVRAM_VERSION 1
3680 +#define NVRAM_HEADER_SIZE 20
3681 +#define NVRAM_SPACE 0x8000
3682 +
3683 +#define NVRAM_MAX_VALUE_LEN 255
3684 +#define NVRAM_MAX_PARAM_LEN 64
3685 +
3686 +#endif /* _bcmnvram_h_ */
3687 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
3688 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
3689 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2006-10-02 21:19:59.000000000 +0200
3690 @@ -0,0 +1,108 @@
3691 +/*
3692 + * Misc useful routines to access NIC local SROM/OTP .
3693 + *
3694 + * Copyright 2006, Broadcom Corporation
3695 + * All Rights Reserved.
3696 + *
3697 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3698 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3699 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3700 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3701 + *
3702 + * $Id: bcmsrom.h,v 1.1.1.13 2006/04/15 01:29:08 michael Exp $
3703 + */
3704 +
3705 +#ifndef _bcmsrom_h_
3706 +#define _bcmsrom_h_
3707 +
3708 +/* Maximum srom: 4 Kilobits == 512 bytes */
3709 +#define SROM_MAX 512
3710 +
3711 +/* SROM Rev 4: Reallocate the software part of the srom to accomodate
3712 + * MIMO features. It assumes up to two PCIE functions and 440 bytes
3713 + * of useable srom i.e. the useable storage in chips with OTP that
3714 + * implements hardware redundancy.
3715 + */
3716 +
3717 +#define SROM4_WORDS 220
3718 +
3719 +#define SROM4_SIGN 32
3720 +#define SROM4_SIGNATURE 0x5372
3721 +
3722 +#define SROM4_BREV 33
3723 +
3724 +#define SROM4_BFL0 34
3725 +#define SROM4_BFL1 35
3726 +#define SROM4_BFL2 36
3727 +#define SROM4_BFL3 37
3728 +
3729 +#define SROM4_MACHI 38
3730 +#define SROM4_MACMID 39
3731 +#define SROM4_MACLO 40
3732 +
3733 +#define SROM4_CCODE 41
3734 +#define SROM4_REGREV 42
3735 +
3736 +#define SROM4_LEDBH10 43
3737 +#define SROM4_LEDBH32 44
3738 +
3739 +#define SROM4_LEDDC 45
3740 +
3741 +#define SROM4_AA 46
3742 +#define SROM4_AA2G_MASK 0x00ff
3743 +#define SROM4_AA2G_SHIFT 0
3744 +#define SROM4_AA5G_MASK 0xff00
3745 +#define SROM4_AA5G_SHIFT 8
3746 +
3747 +#define SROM4_AG10 47
3748 +#define SROM4_AG32 48
3749 +
3750 +#define SROM4_TXPID2G 49
3751 +#define SROM4_TXPID5G 51
3752 +#define SROM4_TXPID5GL 53
3753 +#define SROM4_TXPID5GH 55
3754 +
3755 +/* Per-path fields */
3756 +#define MAX_PATH 4
3757 +#define SROM4_PATH0 64
3758 +#define SROM4_PATH1 87
3759 +#define SROM4_PATH2 110
3760 +#define SROM4_PATH3 133
3761 +
3762 +#define SROM4_2G_ITT_MAXP 0
3763 +#define SROM4_2G_PA 1
3764 +#define SROM4_5G_ITT_MAXP 5
3765 +#define SROM4_5GLH_MAXP 6
3766 +#define SROM4_5G_PA 7
3767 +#define SROM4_5GL_PA 11
3768 +#define SROM4_5GH_PA 15
3769 +
3770 +/* Fields in the ITT_MAXP and 5GLH_MAXP words */
3771 +#define B2G_MAXP_MASK 0xff
3772 +#define B2G_ITT_SHIFT 8
3773 +#define B5G_MAXP_MASK 0xff
3774 +#define B5G_ITT_SHIFT 8
3775 +#define B5GH_MAXP_MASK 0xff
3776 +#define B5GL_MAXP_SHIFT 8
3777 +
3778 +/* All the miriad power offsets */
3779 +#define SROM4_2G_CCKPO 156
3780 +#define SROM4_2G_OFDMPO 157
3781 +#define SROM4_5G_OFDMPO 159
3782 +#define SROM4_5GL_OFDMPO 161
3783 +#define SROM4_5GH_OFDMPO 163
3784 +#define SROM4_2G_MCSPO 165
3785 +#define SROM4_5G_MCSPO 173
3786 +#define SROM4_5GL_MCSPO 181
3787 +#define SROM4_5GH_MCSPO 189
3788 +#define SROM4_CCDPO 197
3789 +#define SROM4_STBCPO 198
3790 +#define SROM4_BW40PO 199
3791 +#define SROM4_BWDUPPO 200
3792 +
3793 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, uint *count);
3794 +
3795 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3796 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3797 +
3798 +#endif /* _bcmsrom_h_ */
3799 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
3800 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
3801 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2006-10-02 21:19:59.000000000 +0200
3802 @@ -0,0 +1,433 @@
3803 +/*
3804 + * Misc useful os-independent macros and functions.
3805 + *
3806 + * Copyright 2006, Broadcom Corporation
3807 + * All Rights Reserved.
3808 + *
3809 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3810 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3811 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3812 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3813 + * $Id: bcmutils.h,v 1.1.1.16 2006/04/08 06:13:39 honor Exp $
3814 + */
3815 +
3816 +#ifndef _bcmutils_h_
3817 +#define _bcmutils_h_
3818 +
3819 +/* ** driver-only section ** */
3820 +#ifdef BCMDRIVER
3821 +
3822 +#define _BCM_U 0x01 /* upper */
3823 +#define _BCM_L 0x02 /* lower */
3824 +#define _BCM_D 0x04 /* digit */
3825 +#define _BCM_C 0x08 /* cntrl */
3826 +#define _BCM_P 0x10 /* punct */
3827 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
3828 +#define _BCM_X 0x40 /* hex digit */
3829 +#define _BCM_SP 0x80 /* hard space (0x20) */
3830 +
3831 +#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */
3832 +
3833 +extern unsigned char bcm_ctype[];
3834 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
3835 +
3836 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
3837 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
3838 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
3839 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
3840 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
3841 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
3842 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
3843 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
3844 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
3845 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
3846 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
3847 +
3848 +/*
3849 + * Spin at most 'us' microseconds while 'exp' is true.
3850 + * Caller should explicitly test 'exp' when this completes
3851 + * and take appropriate error action if 'exp' is still true.
3852 + */
3853 +#define SPINWAIT(exp, us) { \
3854 + uint countdown = (us) + 9; \
3855 + while ((exp) && (countdown >= 10)) {\
3856 + OSL_DELAY(10); \
3857 + countdown -= 10; \
3858 + } \
3859 +}
3860 +
3861 +struct ether_addr {
3862 + uint8 octet[6];
3863 +} __attribute__((packed));
3864 +
3865 +/* string */
3866 +extern uchar bcm_toupper(uchar c);
3867 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
3868 +extern char *bcmstrstr(char *haystack, char *needle);
3869 +extern char *bcmstrcat(char *dest, const char *src);
3870 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
3871 +/* ethernet address */
3872 +extern char *bcm_ether_ntoa(struct ether_addr *ea, char *buf);
3873 +/* variable access */
3874 +extern char *getvar(char *vars, char *name);
3875 +extern int getintvar(char *vars, char *name);
3876 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
3877 +#ifdef BCMPERFSTATS
3878 +extern void bcm_perf_enable(void);
3879 +extern void bcmstats(char *fmt);
3880 +extern void bcmlog(char *fmt, uint a1, uint a2);
3881 +extern void bcmdumplog(char *buf, int size);
3882 +extern int bcmdumplogent(char *buf, uint idx);
3883 +#else
3884 +#define bcm_perf_enable()
3885 +#define bcmstats(fmt)
3886 +#define bcmlog(fmt, a1, a2)
3887 +#define bcmdumplog(buf, size) *buf = '\0'
3888 +#define bcmdumplogent(buf, idx) -1
3889 +#endif /* BCMPERFSTATS */
3890 +extern char *bcm_nvram_vars(uint *length);
3891 +extern int bcm_nvram_cache(void *sbh);
3892 +
3893 +/* Support for sharing code across in-driver iovar implementations.
3894 + * The intent is that a driver use this structure to map iovar names
3895 + * to its (private) iovar identifiers, and the lookup function to
3896 + * find the entry. Macros are provided to map ids and get/set actions
3897 + * into a single number space for a switch statement.
3898 + */
3899 +
3900 +/* iovar structure */
3901 +typedef struct bcm_iovar {
3902 + const char *name; /* name for lookup and display */
3903 + uint16 varid; /* id for switch */
3904 + uint16 flags; /* driver-specific flag bits */
3905 + uint16 type; /* base type of argument */
3906 + uint16 minlen; /* min length for buffer vars */
3907 +} bcm_iovar_t;
3908 +
3909 +/* varid definitions are per-driver, may use these get/set bits */
3910 +
3911 +/* IOVar action bits for id mapping */
3912 +#define IOV_GET 0 /* Get an iovar */
3913 +#define IOV_SET 1 /* Set an iovar */
3914 +
3915 +/* Varid to actionid mapping */
3916 +#define IOV_GVAL(id) ((id)*2)
3917 +#define IOV_SVAL(id) (((id)*2)+IOV_SET)
3918 +#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET)
3919 +
3920 +/* flags are per-driver based on driver attributes */
3921 +
3922 +/* Base type definitions */
3923 +#define IOVT_VOID 0 /* no value (implictly set only) */
3924 +#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */
3925 +#define IOVT_INT8 2 /* integer values are range-checked */
3926 +#define IOVT_UINT8 3 /* unsigned int 8 bits */
3927 +#define IOVT_INT16 4 /* int 16 bits */
3928 +#define IOVT_UINT16 5 /* unsigned int 16 bits */
3929 +#define IOVT_INT32 6 /* int 32 bits */
3930 +#define IOVT_UINT32 7 /* unsigned int 32 bits */
3931 +#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */
3932 +
3933 +extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
3934 +extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
3935 +
3936 +#endif /* #ifdef BCMDRIVER */
3937 +
3938 +/* ** driver/apps-shared section ** */
3939 +
3940 +#define BCME_STRLEN 64 /* Max string length for BCM errors */
3941 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
3942 +
3943 +
3944 +/*
3945 + * error codes could be added but the defined ones shouldn't be changed/deleted
3946 + * these error codes are exposed to the user code
3947 + * when ever a new error code is added to this list
3948 + * please update errorstring table with the related error string and
3949 + * update osl files with os specific errorcode map
3950 +*/
3951 +
3952 +#define BCME_OK 0 /* Success */
3953 +#define BCME_ERROR -1 /* Error generic */
3954 +#define BCME_BADARG -2 /* Bad Argument */
3955 +#define BCME_BADOPTION -3 /* Bad option */
3956 +#define BCME_NOTUP -4 /* Not up */
3957 +#define BCME_NOTDOWN -5 /* Not down */
3958 +#define BCME_NOTAP -6 /* Not AP */
3959 +#define BCME_NOTSTA -7 /* Not STA */
3960 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
3961 +#define BCME_RADIOOFF -9 /* Radio Off */
3962 +#define BCME_NOTBANDLOCKED -10 /* Not band locked */
3963 +#define BCME_NOCLK -11 /* No Clock */
3964 +#define BCME_BADRATESET -12 /* BAD Rate valueset */
3965 +#define BCME_BADBAND -13 /* BAD Band */
3966 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
3967 +#define BCME_BUFTOOLONG -15 /* Buffer too long */
3968 +#define BCME_BUSY -16 /* Busy */
3969 +#define BCME_NOTASSOCIATED -17 /* Not Associated */
3970 +#define BCME_BADSSIDLEN -18 /* Bad SSID len */
3971 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
3972 +#define BCME_BADCHAN -20 /* Bad Channel */
3973 +#define BCME_BADADDR -21 /* Bad Address */
3974 +#define BCME_NORESOURCE -22 /* Not Enough Resources */
3975 +#define BCME_UNSUPPORTED -23 /* Unsupported */
3976 +#define BCME_BADLEN -24 /* Bad length */
3977 +#define BCME_NOTREADY -25 /* Not Ready */
3978 +#define BCME_EPERM -26 /* Not Permitted */
3979 +#define BCME_NOMEM -27 /* No Memory */
3980 +#define BCME_ASSOCIATED -28 /* Associated */
3981 +#define BCME_RANGE -29 /* Not In Range */
3982 +#define BCME_NOTFOUND -30 /* Not Found */
3983 +#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
3984 +#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
3985 +#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
3986 +#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
3987 +#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
3988 +#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
3989 +#define BCME_LAST BCME_DONGLE_DOWN
3990 +
3991 +/* These are collection of BCME Error strings */
3992 +#define BCMERRSTRINGTABLE { \
3993 + "OK", \
3994 + "Undefined error", \
3995 + "Bad Argument", \
3996 + "Bad Option", \
3997 + "Not up", \
3998 + "Not down", \
3999 + "Not AP", \
4000 + "Not STA", \
4001 + "Bad Key Index", \
4002 + "Radio Off", \
4003 + "Not band locked", \
4004 + "No clock", \
4005 + "Bad Rate valueset", \
4006 + "Bad Band", \
4007 + "Buffer too short", \
4008 + "Buffer too long", \
4009 + "Busy", \
4010 + "Not Associated", \
4011 + "Bad SSID len", \
4012 + "Out of Range Channel", \
4013 + "Bad Channel", \
4014 + "Bad Address", \
4015 + "Not Enough Resources", \
4016 + "Unsupported", \
4017 + "Bad length", \
4018 + "Not Ready", \
4019 + "Not Permitted", \
4020 + "No Memory", \
4021 + "Associated", \
4022 + "Not In Range", \
4023 + "Not Found", \
4024 + "WME Not Enabled", \
4025 + "TSPEC Not Found", \
4026 + "ACM Not Supported", \
4027 + "Not WME Association", \
4028 + "SDIO Bus Error", \
4029 + "Dongle Not Accessible" \
4030 +}
4031 +
4032 +#ifndef ABS
4033 +#define ABS(a) (((a) < 0)?-(a):(a))
4034 +#endif /* ABS */
4035 +
4036 +#ifndef MIN
4037 +#define MIN(a, b) (((a) < (b))?(a):(b))
4038 +#endif /* MIN */
4039 +
4040 +#ifndef MAX
4041 +#define MAX(a, b) (((a) > (b))?(a):(b))
4042 +#endif /* MAX */
4043 +
4044 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
4045 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
4046 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
4047 +#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
4048 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
4049 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
4050 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
4051 +
4052 +/* bit map related macros */
4053 +#ifndef setbit
4054 +#ifndef NBBY /* the BSD family defines NBBY */
4055 +#define NBBY 8 /* 8 bits per byte */
4056 +#endif /* #ifndef NBBY */
4057 +#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
4058 +#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
4059 +#define isset(a, i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
4060 +#define isclr(a, i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
4061 +#endif /* setbit */
4062 +
4063 +#define NBITS(type) (sizeof(type) * 8)
4064 +#define NBITVAL(nbits) (1 << (nbits))
4065 +#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
4066 +#define NBITMASK(nbits) MAXBITVAL(nbits)
4067 +#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
4068 +
4069 +/* basic mux operation - can be optimized on several architectures */
4070 +#define MUX(pred, true, false) ((pred) ? (true) : (false))
4071 +
4072 +/* modulo inc/dec - assumes x E [0, bound - 1] */
4073 +#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
4074 +#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
4075 +
4076 +/* modulo inc/dec, bound = 2^k */
4077 +#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
4078 +#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
4079 +
4080 +/* modulo add/sub - assumes x, y E [0, bound - 1] */
4081 +#define MODADD(x, y, bound) \
4082 + MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
4083 +#define MODSUB(x, y, bound) \
4084 + MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
4085 +
4086 +/* module add/sub, bound = 2^k */
4087 +#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
4088 +#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
4089 +
4090 +/* crc defines */
4091 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
4092 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
4093 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
4094 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
4095 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
4096 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
4097 +
4098 +/* bcm_format_flags() bit description structure */
4099 +typedef struct bcm_bit_desc {
4100 + uint32 bit;
4101 + char* name;
4102 +} bcm_bit_desc_t;
4103 +
4104 +/* tag_ID/length/value_buffer tuple */
4105 +typedef struct bcm_tlv {
4106 + uint8 id;
4107 + uint8 len;
4108 + uint8 data[1];
4109 +} bcm_tlv_t;
4110 +
4111 +/* Check that bcm_tlv_t fits into the given buflen */
4112 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
4113 +
4114 +/* buffer length for ethernet address from bcm_ether_ntoa() */
4115 +#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
4116 +
4117 +/* unaligned load and store macros */
4118 +#ifdef IL_BIGENDIAN
4119 +static INLINE uint32
4120 +load32_ua(uint8 *a)
4121 +{
4122 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
4123 +}
4124 +
4125 +static INLINE void
4126 +store32_ua(uint8 *a, uint32 v)
4127 +{
4128 + a[0] = (v >> 24) & 0xff;
4129 + a[1] = (v >> 16) & 0xff;
4130 + a[2] = (v >> 8) & 0xff;
4131 + a[3] = v & 0xff;
4132 +}
4133 +
4134 +static INLINE uint16
4135 +load16_ua(uint8 *a)
4136 +{
4137 + return ((a[0] << 8) | a[1]);
4138 +}
4139 +
4140 +static INLINE void
4141 +store16_ua(uint8 *a, uint16 v)
4142 +{
4143 + a[0] = (v >> 8) & 0xff;
4144 + a[1] = v & 0xff;
4145 +}
4146 +
4147 +#else
4148 +
4149 +static INLINE uint32
4150 +load32_ua(uint8 *a)
4151 +{
4152 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
4153 +}
4154 +
4155 +static INLINE void
4156 +store32_ua(uint8 *a, uint32 v)
4157 +{
4158 + a[3] = (v >> 24) & 0xff;
4159 + a[2] = (v >> 16) & 0xff;
4160 + a[1] = (v >> 8) & 0xff;
4161 + a[0] = v & 0xff;
4162 +}
4163 +
4164 +static INLINE uint16
4165 +load16_ua(uint8 *a)
4166 +{
4167 + return ((a[1] << 8) | a[0]);
4168 +}
4169 +
4170 +static INLINE void
4171 +store16_ua(uint8 *a, uint16 v)
4172 +{
4173 + a[1] = (v >> 8) & 0xff;
4174 + a[0] = v & 0xff;
4175 +}
4176 +
4177 +#endif /* IL_BIGENDIAN */
4178 +
4179 +/* externs */
4180 +/* crc */
4181 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
4182 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
4183 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
4184 +/* format/print */
4185 +extern void printfbig(char *buf);
4186 +
4187 +/* IE parsing */
4188 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
4189 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
4190 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
4191 +
4192 +/* bcmerror */
4193 +extern const char *bcmerrorstr(int bcmerror);
4194 +
4195 +/* multi-bool data type: set of bools, mbool is true if any is set */
4196 +typedef uint32 mbool;
4197 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
4198 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
4199 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
4200 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
4201 +
4202 +/* power conversion */
4203 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
4204 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
4205 +
4206 +/* generic datastruct to help dump routines */
4207 +struct fielddesc {
4208 + char *nameandfmt;
4209 + uint32 offset;
4210 + uint32 len;
4211 +};
4212 +
4213 +/* Buffer structure for collecting string-formatted data
4214 +* using bcm_bprintf() API.
4215 +* Use bcm_binit() to initialize before use
4216 +*/
4217 +struct bcmstrbuf
4218 +{
4219 + char *buf; /* pointer to current position in origbuf */
4220 + uint size; /* current (residual) size in bytes */
4221 + char *origbuf; /* unmodified pointer to orignal buffer */
4222 + uint origsize; /* unmodified orignal buffer size in bytes */
4223 +};
4224 +
4225 +extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
4226 +extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
4227 +
4228 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
4229 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str,
4230 + char *buf, uint32 bufsize);
4231 +
4232 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
4233 +extern uint bcm_bitcount(uint8 *bitmap, uint bytelength);
4234 +
4235 +#endif /* _bcmutils_h_ */
4236 diff -urN linux.old/arch/mips/bcm947xx/include/hndcpu.h linux.dev/arch/mips/bcm947xx/include/hndcpu.h
4237 --- linux.old/arch/mips/bcm947xx/include/hndcpu.h 1970-01-01 01:00:00.000000000 +0100
4238 +++ linux.dev/arch/mips/bcm947xx/include/hndcpu.h 2006-10-02 21:19:59.000000000 +0200
4239 @@ -0,0 +1,28 @@
4240 +/*
4241 + * HND SiliconBackplane MIPS/ARM cores software interface.
4242 + *
4243 + * Copyright 2006, Broadcom Corporation
4244 + * All Rights Reserved.
4245 + *
4246 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4247 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4248 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4249 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4250 + *
4251 + * $Id: hndcpu.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4252 + */
4253 +
4254 +#ifndef _hndcpu_h_
4255 +#define _hndcpu_h_
4256 +
4257 +#if defined(mips)
4258 +#include <hndmips.h>
4259 +#elif defined(__ARM_ARCH_4T__)
4260 +#include <hndarm.h>
4261 +#endif
4262 +
4263 +extern uint sb_irq(sb_t *sbh);
4264 +extern uint32 sb_cpu_clock(sb_t *sbh);
4265 +extern void sb_cpu_wait(void);
4266 +
4267 +#endif /* _hndcpu_h_ */
4268 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
4269 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
4270 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2006-10-02 21:19:59.000000000 +0200
4271 @@ -0,0 +1,45 @@
4272 +/*
4273 + * HND SiliconBackplane MIPS core software interface.
4274 + *
4275 + * Copyright 2006, Broadcom Corporation
4276 + * All Rights Reserved.
4277 + *
4278 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4279 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4280 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4281 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4282 + *
4283 + * $Id: hndmips.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
4284 + */
4285 +
4286 +#ifndef _hndmips_h_
4287 +#define _hndmips_h_
4288 +
4289 +extern void sb_mips_init(sb_t *sbh, uint shirq_map_base);
4290 +extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
4291 +extern void enable_pfc(uint32 mode);
4292 +extern uint32 sb_memc_get_ncdl(sb_t *sbh);
4293 +
4294 +#if defined(BCMPERFSTATS)
4295 +/* enable counting - exclusive version. Only one set of counters allowed at a time */
4296 +extern void hndmips_perf_instrcount_enable(void);
4297 +extern void hndmips_perf_icachecount_enable(void);
4298 +extern void hndmips_perf_dcachecount_enable(void);
4299 +/* start and stop counting */
4300 +#define hndmips_perf_start01() \
4301 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000)
4302 +#define hndmips_perf_stop01() \
4303 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000)
4304 +/* retrieve coutners - counters *decrement* */
4305 +#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0))
4306 +#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1))
4307 +#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2))
4308 +/* enable counting - modular version. Each counters can be enabled separately. */
4309 +extern void hndmips_perf_icache_hit_enable(void);
4310 +extern void hndmips_perf_icache_miss_enable(void);
4311 +extern uint32 hndmips_perf_read_instrcount(void);
4312 +extern uint32 hndmips_perf_read_cache_miss(void);
4313 +extern uint32 hndmips_perf_read_cache_hit(void);
4314 +#endif /* defined(BCMINTERNAL) || defined (BCMPERFSTATS) */
4315 +
4316 +#endif /* _hndmips_h_ */
4317 diff -urN linux.old/arch/mips/bcm947xx/include/hndpci.h linux.dev/arch/mips/bcm947xx/include/hndpci.h
4318 --- linux.old/arch/mips/bcm947xx/include/hndpci.h 1970-01-01 01:00:00.000000000 +0100
4319 +++ linux.dev/arch/mips/bcm947xx/include/hndpci.h 2006-10-02 21:19:59.000000000 +0200
4320 @@ -0,0 +1,30 @@
4321 +/*
4322 + * HND SiliconBackplane PCI core software interface.
4323 + *
4324 + * $Id: hndpci.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4325 + * Copyright 2006, Broadcom Corporation
4326 + * All Rights Reserved.
4327 + *
4328 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4329 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4330 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4331 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4332 + */
4333 +
4334 +#ifndef _hndpci_h_
4335 +#define _hndpci_h_
4336 +
4337 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4338 + int len);
4339 +extern int extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4340 + int len);
4341 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4342 + int len);
4343 +extern int extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4344 + int len);
4345 +extern void sbpci_ban(uint16 core);
4346 +extern int sbpci_init(sb_t *sbh);
4347 +extern int sbpci_init_pci(sb_t *sbh);
4348 +extern void sbpci_check(sb_t *sbh);
4349 +
4350 +#endif /* _hndpci_h_ */
4351 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
4352 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
4353 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2006-10-02 21:19:59.000000000 +0200
4354 @@ -0,0 +1,417 @@
4355 +/*
4356 + * Linux-specific abstractions to gain some independence from linux kernel versions.
4357 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
4358 + *
4359 + * Copyright 2006, Broadcom Corporation
4360 + * All Rights Reserved.
4361 + *
4362 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4363 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4364 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4365 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4366 + *
4367 + * $Id: linuxver.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
4368 + */
4369 +
4370 +#ifndef _linuxver_h_
4371 +#define _linuxver_h_
4372 +
4373 +#include <linux/config.h>
4374 +#include <linux/version.h>
4375 +
4376 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0))
4377 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
4378 +#ifdef __UNDEF_NO_VERSION__
4379 +#undef __NO_VERSION__
4380 +#else
4381 +#define __NO_VERSION__
4382 +#endif
4383 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0) */
4384 +
4385 +#if defined(MODULE) && defined(MODVERSIONS)
4386 +#include <linux/modversions.h>
4387 +#endif
4388 +
4389 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 0)
4390 +#include <linux/moduleparam.h>
4391 +#endif
4392 +
4393 +
4394 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)
4395 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
4396 +#define module_param_string(_name_, _string_, _size_, _perm_) \
4397 + MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
4398 +#endif
4399 +
4400 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
4401 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9))
4402 +#include <linux/malloc.h>
4403 +#else
4404 +#include <linux/slab.h>
4405 +#endif
4406 +
4407 +#include <linux/types.h>
4408 +#include <linux/init.h>
4409 +#include <linux/mm.h>
4410 +#include <linux/string.h>
4411 +#include <linux/pci.h>
4412 +#include <linux/interrupt.h>
4413 +#include <linux/netdevice.h>
4414 +#include <asm/io.h>
4415 +
4416 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
4417 +#include <linux/workqueue.h>
4418 +#else
4419 +#include <linux/tqueue.h>
4420 +#ifndef work_struct
4421 +#define work_struct tq_struct
4422 +#endif
4423 +#ifndef INIT_WORK
4424 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
4425 +#endif
4426 +#ifndef schedule_work
4427 +#define schedule_work(_work) schedule_task((_work))
4428 +#endif
4429 +#ifndef flush_scheduled_work
4430 +#define flush_scheduled_work() flush_scheduled_tasks()
4431 +#endif
4432 +#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41) */
4433 +
4434 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4435 +/* Some distributions have their own 2.6.x compatibility layers */
4436 +#ifndef IRQ_NONE
4437 +typedef void irqreturn_t;
4438 +#define IRQ_NONE
4439 +#define IRQ_HANDLED
4440 +#define IRQ_RETVAL(x)
4441 +#endif
4442 +#else
4443 +typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
4444 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0) */
4445 +
4446 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
4447 +
4448 +#include <pcmcia/version.h>
4449 +#include <pcmcia/cs_types.h>
4450 +#include <pcmcia/cs.h>
4451 +#include <pcmcia/cistpl.h>
4452 +#include <pcmcia/cisreg.h>
4453 +#include <pcmcia/ds.h>
4454 +
4455 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 69))
4456 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
4457 + * does this, but it's not in 2.4 so we do our own for now.
4458 + */
4459 +static inline void
4460 +cs_error(client_handle_t handle, int func, int ret)
4461 +{
4462 + error_info_t err = { func, ret };
4463 + CardServices(ReportError, handle, &err);
4464 +}
4465 +#endif
4466 +
4467 +#endif /* CONFIG_PCMCIA */
4468 +
4469 +#ifndef __exit
4470 +#define __exit
4471 +#endif
4472 +#ifndef __devexit
4473 +#define __devexit
4474 +#endif
4475 +#ifndef __devinit
4476 +#define __devinit __init
4477 +#endif
4478 +#ifndef __devinitdata
4479 +#define __devinitdata
4480 +#endif
4481 +#ifndef __devexit_p
4482 +#define __devexit_p(x) x
4483 +#endif
4484 +
4485 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
4486 +
4487 +#define pci_get_drvdata(dev) (dev)->sysdata
4488 +#define pci_set_drvdata(dev, value) (dev)->sysdata = (value)
4489 +
4490 +/*
4491 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
4492 + */
4493 +
4494 +struct pci_device_id {
4495 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
4496 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
4497 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
4498 + unsigned long driver_data; /* Data private to the driver */
4499 +};
4500 +
4501 +struct pci_driver {
4502 + struct list_head node;
4503 + char *name;
4504 + const struct pci_device_id *id_table; /* NULL if wants all devices */
4505 + int (*probe)(struct pci_dev *dev,
4506 + const struct pci_device_id *id); /* New device inserted */
4507 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug
4508 + * capable driver)
4509 + */
4510 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
4511 + void (*resume)(struct pci_dev *dev); /* Device woken up */
4512 +};
4513 +
4514 +#define MODULE_DEVICE_TABLE(type, name)
4515 +#define PCI_ANY_ID (~0)
4516 +
4517 +/* compatpci.c */
4518 +#define pci_module_init pci_register_driver
4519 +extern int pci_register_driver(struct pci_driver *drv);
4520 +extern void pci_unregister_driver(struct pci_driver *drv);
4521 +
4522 +#endif /* PCI registration */
4523 +
4524 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18))
4525 +#ifdef MODULE
4526 +#define module_init(x) int init_module(void) { return x(); }
4527 +#define module_exit(x) void cleanup_module(void) { x(); }
4528 +#else
4529 +#define module_init(x) __initcall(x);
4530 +#define module_exit(x) __exitcall(x);
4531 +#endif
4532 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18) */
4533 +
4534 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48))
4535 +#define list_for_each(pos, head) \
4536 + for (pos = (head)->next; pos != (head); pos = pos->next)
4537 +#endif
4538 +
4539 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13))
4540 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
4541 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44))
4542 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
4543 +#endif
4544 +
4545 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23))
4546 +#define pci_enable_device(dev) do { } while (0)
4547 +#endif
4548 +
4549 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14))
4550 +#define net_device device
4551 +#endif
4552 +
4553 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42))
4554 +
4555 +/*
4556 + * DMA mapping
4557 + *
4558 + * See linux/Documentation/DMA-mapping.txt
4559 + */
4560 +
4561 +#ifndef PCI_DMA_TODEVICE
4562 +#define PCI_DMA_TODEVICE 1
4563 +#define PCI_DMA_FROMDEVICE 2
4564 +#endif
4565 +
4566 +typedef u32 dma_addr_t;
4567 +
4568 +/* Pure 2^n version of get_order */
4569 +static inline int get_order(unsigned long size)
4570 +{
4571 + int order;
4572 +
4573 + size = (size-1) >> (PAGE_SHIFT-1);
4574 + order = -1;
4575 + do {
4576 + size >>= 1;
4577 + order++;
4578 + } while (size);
4579 + return order;
4580 +}
4581 +
4582 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
4583 + dma_addr_t *dma_handle)
4584 +{
4585 + void *ret;
4586 + int gfp = GFP_ATOMIC | GFP_DMA;
4587 +
4588 + ret = (void *)__get_free_pages(gfp, get_order(size));
4589 +
4590 + if (ret != NULL) {
4591 + memset(ret, 0, size);
4592 + *dma_handle = virt_to_bus(ret);
4593 + }
4594 + return ret;
4595 +}
4596 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
4597 + void *vaddr, dma_addr_t dma_handle)
4598 +{
4599 + free_pages((unsigned long)vaddr, get_order(size));
4600 +}
4601 +#ifdef ILSIM
4602 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
4603 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
4604 +#else
4605 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
4606 +#define pci_unmap_single(cookie, address, size, dir)
4607 +#endif
4608 +
4609 +#endif /* DMA mapping */
4610 +
4611 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43))
4612 +
4613 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
4614 +#define netif_down(dev) do { (dev)->start = 0; } while (0)
4615 +
4616 +/* pcmcia-cs provides its own netdevice compatibility layer */
4617 +#ifndef _COMPAT_NETDEVICE_H
4618 +
4619 +/*
4620 + * SoftNet
4621 + *
4622 + * For pre-softnet kernels we need to tell the upper layer not to
4623 + * re-enter start_xmit() while we are in there. However softnet
4624 + * guarantees not to enter while we are in there so there is no need
4625 + * to do the netif_stop_queue() dance unless the transmit queue really
4626 + * gets stuck. This should also improve performance according to tests
4627 + * done by Aman Singla.
4628 + */
4629 +
4630 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
4631 +#define netif_wake_queue(dev) \
4632 + do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0)
4633 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
4634 +
4635 +static inline void netif_start_queue(struct net_device *dev)
4636 +{
4637 + dev->tbusy = 0;
4638 + dev->interrupt = 0;
4639 + dev->start = 1;
4640 +}
4641 +
4642 +#define netif_queue_stopped(dev) (dev)->tbusy
4643 +#define netif_running(dev) (dev)->start
4644 +
4645 +#endif /* _COMPAT_NETDEVICE_H */
4646 +
4647 +#define netif_device_attach(dev) netif_start_queue(dev)
4648 +#define netif_device_detach(dev) netif_stop_queue(dev)
4649 +
4650 +/* 2.4.x renamed bottom halves to tasklets */
4651 +#define tasklet_struct tq_struct
4652 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
4653 +{
4654 + queue_task(tasklet, &tq_immediate);
4655 + mark_bh(IMMEDIATE_BH);
4656 +}
4657 +
4658 +static inline void tasklet_init(struct tasklet_struct *tasklet,
4659 + void (*func)(unsigned long),
4660 + unsigned long data)
4661 +{
4662 + tasklet->next = NULL;
4663 + tasklet->sync = 0;
4664 + tasklet->routine = (void (*)(void *))func;
4665 + tasklet->data = (void *)data;
4666 +}
4667 +#define tasklet_kill(tasklet) { do{} while (0); }
4668 +
4669 +/* 2.4.x introduced del_timer_sync() */
4670 +#define del_timer_sync(timer) del_timer(timer)
4671 +
4672 +#else
4673 +
4674 +#define netif_down(dev)
4675 +
4676 +#endif /* SoftNet */
4677 +
4678 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3))
4679 +
4680 +/*
4681 + * Emit code to initialise a tq_struct's routine and data pointers
4682 + */
4683 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
4684 + do { \
4685 + (_tq)->routine = _routine; \
4686 + (_tq)->data = _data; \
4687 + } while (0)
4688 +
4689 +/*
4690 + * Emit code to initialise all of a tq_struct
4691 + */
4692 +#define INIT_TQUEUE(_tq, _routine, _data) \
4693 + do { \
4694 + INIT_LIST_HEAD(&(_tq)->list); \
4695 + (_tq)->sync = 0; \
4696 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
4697 + } while (0)
4698 +
4699 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3) */
4700 +
4701 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6))
4702 +
4703 +/* Power management related routines */
4704 +
4705 +static inline int
4706 +pci_save_state(struct pci_dev *dev, u32 *buffer)
4707 +{
4708 + int i;
4709 + if (buffer) {
4710 + for (i = 0; i < 16; i++)
4711 + pci_read_config_dword(dev, i * 4, &buffer[i]);
4712 + }
4713 + return 0;
4714 +}
4715 +
4716 +static inline int
4717 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
4718 +{
4719 + int i;
4720 +
4721 + if (buffer) {
4722 + for (i = 0; i < 16; i++)
4723 + pci_write_config_dword(dev, i * 4, buffer[i]);
4724 + }
4725 + /*
4726 + * otherwise, write the context information we know from bootup.
4727 + * This works around a problem where warm-booting from Windows
4728 + * combined with a D3(hot)->D0 transition causes PCI config
4729 + * header data to be forgotten.
4730 + */
4731 + else {
4732 + for (i = 0; i < 6; i ++)
4733 + pci_write_config_dword(dev,
4734 + PCI_BASE_ADDRESS_0 + (i * 4),
4735 + pci_resource_start(dev, i));
4736 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
4737 + }
4738 + return 0;
4739 +}
4740 +
4741 +#endif /* PCI power management */
4742 +
4743 +/* Old cp0 access macros deprecated in 2.4.19 */
4744 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19))
4745 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
4746 +#endif
4747 +
4748 +/* Module refcount handled internally in 2.6.x */
4749 +#ifndef SET_MODULE_OWNER
4750 +#define SET_MODULE_OWNER(dev) do {} while (0)
4751 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
4752 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
4753 +#else
4754 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
4755 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
4756 +#endif
4757 +
4758 +#ifndef SET_NETDEV_DEV
4759 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
4760 +#endif
4761 +
4762 +#ifndef HAVE_FREE_NETDEV
4763 +#define free_netdev(dev) kfree(dev)
4764 +#endif
4765 +
4766 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4767 +/* struct packet_type redefined in 2.6.x */
4768 +#define af_packet_priv data
4769 +#endif
4770 +
4771 +#endif /* _linuxver_h_ */
4772 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
4773 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
4774 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2006-10-02 21:19:59.000000000 +0200
4775 @@ -0,0 +1,541 @@
4776 +/*
4777 + * HND Run Time Environment for standalone MIPS programs.
4778 + *
4779 + * Copyright 2006, Broadcom Corporation
4780 + * All Rights Reserved.
4781 + *
4782 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4783 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4784 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4785 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4786 + *
4787 + * $Id: mipsinc.h,v 1.1.1.5 2006/02/27 03:43:16 honor Exp $
4788 + */
4789 +
4790 +#ifndef _MISPINC_H
4791 +#define _MISPINC_H
4792 +
4793 +
4794 +/* MIPS defines */
4795 +
4796 +#ifdef _LANGUAGE_ASSEMBLY
4797 +
4798 +/*
4799 + * Symbolic register names for 32 bit ABI
4800 + */
4801 +#define zero $0 /* wired zero */
4802 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
4803 +#define v0 $2 /* return value */
4804 +#define v1 $3
4805 +#define a0 $4 /* argument registers */
4806 +#define a1 $5
4807 +#define a2 $6
4808 +#define a3 $7
4809 +#define t0 $8 /* caller saved */
4810 +#define t1 $9
4811 +#define t2 $10
4812 +#define t3 $11
4813 +#define t4 $12
4814 +#define t5 $13
4815 +#define t6 $14
4816 +#define t7 $15
4817 +#define s0 $16 /* callee saved */
4818 +#define s1 $17
4819 +#define s2 $18
4820 +#define s3 $19
4821 +#define s4 $20
4822 +#define s5 $21
4823 +#define s6 $22
4824 +#define s7 $23
4825 +#define t8 $24 /* caller saved */
4826 +#define t9 $25
4827 +#define jp $25 /* PIC jump register */
4828 +#define k0 $26 /* kernel scratch */
4829 +#define k1 $27
4830 +#define gp $28 /* global pointer */
4831 +#define sp $29 /* stack pointer */
4832 +#define fp $30 /* frame pointer */
4833 +#define s8 $30 /* same like fp! */
4834 +#define ra $31 /* return address */
4835 +
4836 +
4837 +/* CP0 Registers */
4838 +
4839 +#define C0_INX $0
4840 +#define C0_RAND $1
4841 +#define C0_TLBLO0 $2
4842 +#define C0_TLBLO C0_TLBLO0
4843 +#define C0_TLBLO1 $3
4844 +#define C0_CTEXT $4
4845 +#define C0_PGMASK $5
4846 +#define C0_WIRED $6
4847 +#define C0_BADVADDR $8
4848 +#define C0_COUNT $9
4849 +#define C0_TLBHI $10
4850 +#define C0_COMPARE $11
4851 +#define C0_SR $12
4852 +#define C0_STATUS C0_SR
4853 +#define C0_CAUSE $13
4854 +#define C0_EPC $14
4855 +#define C0_PRID $15
4856 +#define C0_CONFIG $16
4857 +#define C0_LLADDR $17
4858 +#define C0_WATCHLO $18
4859 +#define C0_WATCHHI $19
4860 +#define C0_XCTEXT $20
4861 +#define C0_DIAGNOSTIC $22
4862 +#define C0_BROADCOM C0_DIAGNOSTIC
4863 +#define C0_PERFORMANCE $25
4864 +#define C0_ECC $26
4865 +#define C0_CACHEERR $27
4866 +#define C0_TAGLO $28
4867 +#define C0_TAGHI $29
4868 +#define C0_ERREPC $30
4869 +#define C0_DESAVE $31
4870 +
4871 +/*
4872 + * LEAF - declare leaf routine
4873 + */
4874 +#define LEAF(symbol) \
4875 + .globl symbol; \
4876 + .align 2; \
4877 + .type symbol, @function; \
4878 + .ent symbol, 0; \
4879 +symbol: .frame sp, 0, ra
4880 +
4881 +/*
4882 + * END - mark end of function
4883 + */
4884 +#define END(function) \
4885 + .end function; \
4886 + .size function, . - function
4887 +
4888 +#define _ULCAST_
4889 +
4890 +#define MFC0_SEL(dst, src, sel) \
4891 + .word\t(0x40000000 | ((dst) << 16) | ((src) << 11) | (sel))
4892 +
4893 +
4894 +#define MTC0_SEL(dst, src, sel) \
4895 + .word\t(0x40800000 | ((dst) << 16) | ((src) << 11) | (sel))
4896 +
4897 +#else
4898 +
4899 +/*
4900 + * The following macros are especially useful for __asm__
4901 + * inline assembler.
4902 + */
4903 +#ifndef __STR
4904 +#define __STR(x) #x
4905 +#endif
4906 +#ifndef STR
4907 +#define STR(x) __STR(x)
4908 +#endif
4909 +
4910 +#define _ULCAST_ (unsigned long)
4911 +
4912 +
4913 +/* CP0 Registers */
4914 +
4915 +#define C0_INX 0 /* CP0: TLB Index */
4916 +#define C0_RAND 1 /* CP0: TLB Random */
4917 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
4918 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
4919 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
4920 +#define C0_CTEXT 4 /* CP0: Context */
4921 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
4922 +#define C0_WIRED 6 /* CP0: TLB Wired */
4923 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
4924 +#define C0_COUNT 9 /* CP0: Count */
4925 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
4926 +#define C0_COMPARE 11 /* CP0: Compare */
4927 +#define C0_SR 12 /* CP0: Processor Status */
4928 +#define C0_STATUS C0_SR /* CP0: Processor Status */
4929 +#define C0_CAUSE 13 /* CP0: Exception Cause */
4930 +#define C0_EPC 14 /* CP0: Exception PC */
4931 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
4932 +#define C0_CONFIG 16 /* CP0: Config */
4933 +#define C0_LLADDR 17 /* CP0: LLAddr */
4934 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
4935 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
4936 +#define C0_XCTEXT 20 /* CP0: XContext */
4937 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
4938 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
4939 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
4940 +#define C0_ECC 26 /* CP0: ECC */
4941 +#define C0_CACHEERR 27 /* CP0: CacheErr */
4942 +#define C0_TAGLO 28 /* CP0: TagLo */
4943 +#define C0_TAGHI 29 /* CP0: TagHi */
4944 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
4945 +#define C0_DESAVE 31 /* CP0: DebugSave */
4946 +
4947 +#endif /* _LANGUAGE_ASSEMBLY */
4948 +
4949 +/*
4950 + * Memory segments (32bit kernel mode addresses)
4951 + */
4952 +#undef KUSEG
4953 +#undef KSEG0
4954 +#undef KSEG1
4955 +#undef KSEG2
4956 +#undef KSEG3
4957 +#define KUSEG 0x00000000
4958 +#define KSEG0 0x80000000
4959 +#define KSEG1 0xa0000000
4960 +#define KSEG2 0xc0000000
4961 +#define KSEG3 0xe0000000
4962 +#define PHYSADDR_MASK 0x1fffffff
4963 +
4964 +/*
4965 + * Map an address to a certain kernel segment
4966 + */
4967 +#undef PHYSADDR
4968 +#undef KSEG0ADDR
4969 +#undef KSEG1ADDR
4970 +#undef KSEG2ADDR
4971 +#undef KSEG3ADDR
4972 +
4973 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
4974 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
4975 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
4976 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
4977 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
4978 +
4979 +
4980 +#ifndef Index_Invalidate_I
4981 +/*
4982 + * Cache Operations
4983 + */
4984 +#define Index_Invalidate_I 0x00
4985 +#define Index_Writeback_Inv_D 0x01
4986 +#define Index_Invalidate_SI 0x02
4987 +#define Index_Writeback_Inv_SD 0x03
4988 +#define Index_Load_Tag_I 0x04
4989 +#define Index_Load_Tag_D 0x05
4990 +#define Index_Load_Tag_SI 0x06
4991 +#define Index_Load_Tag_SD 0x07
4992 +#define Index_Store_Tag_I 0x08
4993 +#define Index_Store_Tag_D 0x09
4994 +#define Index_Store_Tag_SI 0x0A
4995 +#define Index_Store_Tag_SD 0x0B
4996 +#define Create_Dirty_Excl_D 0x0d
4997 +#define Create_Dirty_Excl_SD 0x0f
4998 +#define Hit_Invalidate_I 0x10
4999 +#define Hit_Invalidate_D 0x11
5000 +#define Hit_Invalidate_SI 0x12
5001 +#define Hit_Invalidate_SD 0x13
5002 +#define Fill_I 0x14
5003 +#define Hit_Writeback_Inv_D 0x15
5004 + /* 0x16 is unused */
5005 +#define Hit_Writeback_Inv_SD 0x17
5006 +#define R5K_Page_Invalidate_S 0x17
5007 +#define Hit_Writeback_I 0x18
5008 +#define Hit_Writeback_D 0x19
5009 + /* 0x1a is unused */
5010 +#define Hit_Writeback_SD 0x1b
5011 + /* 0x1c is unused */
5012 + /* 0x1e is unused */
5013 +#define Hit_Set_Virtual_SI 0x1e
5014 +#define Hit_Set_Virtual_SD 0x1f
5015 +#endif /* !Index_Invalidate_I */
5016 +
5017 +
5018 +/*
5019 + * R4x00 interrupt enable / cause bits
5020 + */
5021 +#define IE_SW0 (_ULCAST_(1) << 8)
5022 +#define IE_SW1 (_ULCAST_(1) << 9)
5023 +#define IE_IRQ0 (_ULCAST_(1) << 10)
5024 +#define IE_IRQ1 (_ULCAST_(1) << 11)
5025 +#define IE_IRQ2 (_ULCAST_(1) << 12)
5026 +#define IE_IRQ3 (_ULCAST_(1) << 13)
5027 +#define IE_IRQ4 (_ULCAST_(1) << 14)
5028 +#define IE_IRQ5 (_ULCAST_(1) << 15)
5029 +
5030 +#ifndef ST0_UM
5031 +/*
5032 + * Bitfields in the mips32 cp0 status register
5033 + */
5034 +#define ST0_IE 0x00000001
5035 +#define ST0_EXL 0x00000002
5036 +#define ST0_ERL 0x00000004
5037 +#define ST0_UM 0x00000010
5038 +#define ST0_SWINT0 0x00000100
5039 +#define ST0_SWINT1 0x00000200
5040 +#define ST0_HWINT0 0x00000400
5041 +#define ST0_HWINT1 0x00000800
5042 +#define ST0_HWINT2 0x00001000
5043 +#define ST0_HWINT3 0x00002000
5044 +#define ST0_HWINT4 0x00004000
5045 +#define ST0_HWINT5 0x00008000
5046 +#define ST0_IM 0x0000ff00
5047 +#define ST0_NMI 0x00080000
5048 +#define ST0_SR 0x00100000
5049 +#define ST0_TS 0x00200000
5050 +#define ST0_BEV 0x00400000
5051 +#define ST0_RE 0x02000000
5052 +#define ST0_RP 0x08000000
5053 +#define ST0_CU 0xf0000000
5054 +#define ST0_CU0 0x10000000
5055 +#define ST0_CU1 0x20000000
5056 +#define ST0_CU2 0x40000000
5057 +#define ST0_CU3 0x80000000
5058 +#endif /* !ST0_UM */
5059 +
5060 +
5061 +/*
5062 + * Bitfields in the mips32 cp0 cause register
5063 + */
5064 +#define C_EXC 0x0000007c
5065 +#define C_EXC_SHIFT 2
5066 +#define C_INT 0x0000ff00
5067 +#define C_INT_SHIFT 8
5068 +#define C_SW0 (_ULCAST_(1) << 8)
5069 +#define C_SW1 (_ULCAST_(1) << 9)
5070 +#define C_IRQ0 (_ULCAST_(1) << 10)
5071 +#define C_IRQ1 (_ULCAST_(1) << 11)
5072 +#define C_IRQ2 (_ULCAST_(1) << 12)
5073 +#define C_IRQ3 (_ULCAST_(1) << 13)
5074 +#define C_IRQ4 (_ULCAST_(1) << 14)
5075 +#define C_IRQ5 (_ULCAST_(1) << 15)
5076 +#define C_WP 0x00400000
5077 +#define C_IV 0x00800000
5078 +#define C_CE 0x30000000
5079 +#define C_CE_SHIFT 28
5080 +#define C_BD 0x80000000
5081 +
5082 +/* Values in C_EXC */
5083 +#define EXC_INT 0
5084 +#define EXC_TLBM 1
5085 +#define EXC_TLBL 2
5086 +#define EXC_TLBS 3
5087 +#define EXC_AEL 4
5088 +#define EXC_AES 5
5089 +#define EXC_IBE 6
5090 +#define EXC_DBE 7
5091 +#define EXC_SYS 8
5092 +#define EXC_BPT 9
5093 +#define EXC_RI 10
5094 +#define EXC_CU 11
5095 +#define EXC_OV 12
5096 +#define EXC_TR 13
5097 +#define EXC_WATCH 23
5098 +#define EXC_MCHK 24
5099 +
5100 +
5101 +/*
5102 + * Bits in the cp0 config register.
5103 + */
5104 +#define CONF_CM_CACHABLE_NO_WA 0
5105 +#define CONF_CM_CACHABLE_WA 1
5106 +#define CONF_CM_UNCACHED 2
5107 +#define CONF_CM_CACHABLE_NONCOHERENT 3
5108 +#define CONF_CM_CACHABLE_CE 4
5109 +#define CONF_CM_CACHABLE_COW 5
5110 +#define CONF_CM_CACHABLE_CUW 6
5111 +#define CONF_CM_CACHABLE_ACCELERATED 7
5112 +#define CONF_CM_CMASK 7
5113 +#define CONF_CU (_ULCAST_(1) << 3)
5114 +#define CONF_DB (_ULCAST_(1) << 4)
5115 +#define CONF_IB (_ULCAST_(1) << 5)
5116 +#define CONF_SE (_ULCAST_(1) << 12)
5117 +#ifndef CONF_BE /* duplicate in mipsregs.h */
5118 +#define CONF_BE (_ULCAST_(1) << 15)
5119 +#endif
5120 +#define CONF_SC (_ULCAST_(1) << 17)
5121 +#define CONF_AC (_ULCAST_(1) << 23)
5122 +#define CONF_HALT (_ULCAST_(1) << 25)
5123 +#ifndef CONF_M /* duplicate in mipsregs.h */
5124 +#define CONF_M (_ULCAST_(1) << 31)
5125 +#endif
5126 +
5127 +
5128 +/*
5129 + * Bits in the cp0 config register select 1.
5130 + */
5131 +#define CONF1_FP 0x00000001 /* FPU present */
5132 +#define CONF1_EP 0x00000002 /* EJTAG present */
5133 +#define CONF1_CA 0x00000004 /* mips16 implemented */
5134 +#define CONF1_WR 0x00000008 /* Watch registers present */
5135 +#define CONF1_PC 0x00000010 /* Performance counters present */
5136 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
5137 +#define CONF1_DA_MASK 0x00000380
5138 +#define CONF1_DA_BASE 1
5139 +#define CONF1_DL_SHIFT 10 /* D$ line size */
5140 +#define CONF1_DL_MASK 0x00001c00
5141 +#define CONF1_DL_BASE 2
5142 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
5143 +#define CONF1_DS_MASK 0x0000e000
5144 +#define CONF1_DS_BASE 64
5145 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
5146 +#define CONF1_IA_MASK 0x00070000
5147 +#define CONF1_IA_BASE 1
5148 +#define CONF1_IL_SHIFT 19 /* I$ line size */
5149 +#define CONF1_IL_MASK 0x00380000
5150 +#define CONF1_IL_BASE 2
5151 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
5152 +#define CONF1_IS_MASK 0x01c00000
5153 +#define CONF1_IS_BASE 64
5154 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
5155 +#define CONF1_MS_SHIFT 25
5156 +
5157 +/* PRID register */
5158 +#define PRID_COPT_MASK 0xff000000
5159 +#define PRID_COMP_MASK 0x00ff0000
5160 +#define PRID_IMP_MASK 0x0000ff00
5161 +#define PRID_REV_MASK 0x000000ff
5162 +
5163 +#define PRID_COMP_LEGACY 0x000000
5164 +#define PRID_COMP_MIPS 0x010000
5165 +#define PRID_COMP_BROADCOM 0x020000
5166 +#define PRID_COMP_ALCHEMY 0x030000
5167 +#define PRID_COMP_SIBYTE 0x040000
5168 +#define PRID_IMP_BCM4710 0x4000
5169 +#define PRID_IMP_BCM3302 0x9000
5170 +#define PRID_IMP_BCM3303 0x9100
5171 +
5172 +#define PRID_IMP_UNKNOWN 0xff00
5173 +
5174 +#define BCM330X(id) \
5175 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5176 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) || \
5177 + ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5178 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
5179 +
5180 +/* Bits in C0_BROADCOM */
5181 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
5182 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
5183 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
5184 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
5185 +#define BRCM_CLF_ENABLE 0x00100000 /* Enable cache line first feature */
5186 +
5187 +/* PreFetch Cache aka Read Ahead Cache */
5188 +
5189 +#define PFC_CR0 0xff400000 /* control reg 0 */
5190 +#define PFC_CR1 0xff400004 /* control reg 1 */
5191 +
5192 +/* PFC operations */
5193 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
5194 +#define PFC_D 0x00000002 /* Enable PFC use for data */
5195 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
5196 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
5197 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
5198 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
5199 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
5200 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
5201 +#define PFC_BRR 0x40000000 /* Bus error indication */
5202 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
5203 +
5204 +/* Handy defaults */
5205 +#define PFC_DISABLED 0
5206 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
5207 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
5208 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
5209 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
5210 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
5211 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
5212 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
5213 +
5214 +#ifndef _LANGUAGE_ASSEMBLY
5215 +
5216 +/*
5217 + * Macros to access the system control coprocessor
5218 + */
5219 +
5220 +#define MFC0(source, sel) \
5221 +({ \
5222 + int __res; \
5223 + __asm__ __volatile__(" \
5224 + .set\tnoreorder; \
5225 + .set\tnoat; \
5226 + .word\t"STR(0x40010000 | ((source) << 11) | (sel))"; \
5227 + move\t%0, $1; \
5228 + .set\tat; \
5229 + .set\treorder" \
5230 + :"=r" (__res) \
5231 + : \
5232 + :"$1"); \
5233 + __res; \
5234 +})
5235 +
5236 +#define MTC0(source, sel, value) \
5237 +do { \
5238 + __asm__ __volatile__(" \
5239 + .set\tnoreorder; \
5240 + .set\tnoat; \
5241 + move\t$1, %z0; \
5242 + .word\t"STR(0x40810000 | ((source) << 11) | (sel))"; \
5243 + .set\tat; \
5244 + .set\treorder" \
5245 + : \
5246 + :"jr" (value) \
5247 + :"$1"); \
5248 +} while (0)
5249 +
5250 +#define get_c0_count() \
5251 +({ \
5252 + int __res; \
5253 + __asm__ __volatile__(" \
5254 + .set\tnoreorder; \
5255 + .set\tnoat; \
5256 + mfc0\t%0, $9; \
5257 + .set\tat; \
5258 + .set\treorder" \
5259 + :"=r" (__res)); \
5260 + __res; \
5261 +})
5262 +
5263 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
5264 +{
5265 + uint lsz, sets, ways;
5266 +
5267 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
5268 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
5269 + lsz = CONF1_IL_BASE << lsz;
5270 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
5271 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
5272 + *size = lsz * sets * ways;
5273 + *lsize = lsz;
5274 +}
5275 +
5276 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
5277 +{
5278 + uint lsz, sets, ways;
5279 +
5280 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
5281 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
5282 + lsz = CONF1_DL_BASE << lsz;
5283 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
5284 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
5285 + *size = lsz * sets * ways;
5286 + *lsize = lsz;
5287 +}
5288 +
5289 +#define cache_op(base, op) \
5290 + __asm__ __volatile__(" \
5291 + .set noreorder; \
5292 + .set mips3; \
5293 + cache %1, (%0); \
5294 + .set mips0; \
5295 + .set reorder" \
5296 + : \
5297 + : "r" (base), \
5298 + "i" (op));
5299 +
5300 +#define cache_unroll4(base, delta, op) \
5301 + __asm__ __volatile__(" \
5302 + .set noreorder; \
5303 + .set mips3; \
5304 + cache %1, 0(%0); \
5305 + cache %1, delta(%0); \
5306 + cache %1, (2 * delta)(%0); \
5307 + cache %1, (3 * delta)(%0); \
5308 + .set mips0; \
5309 + .set reorder" \
5310 + : \
5311 + : "r" (base), \
5312 + "i" (op));
5313 +
5314 +#endif /* !_LANGUAGE_ASSEMBLY */
5315 +
5316 +#endif /* _MISPINC_H */
5317 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
5318 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
5319 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2006-10-02 21:19:59.000000000 +0200
5320 @@ -0,0 +1,181 @@
5321 +#ifndef __osl_h
5322 +#define __osl_h
5323 +
5324 +#include <linux/delay.h>
5325 +#include <typedefs.h>
5326 +#include <linuxver.h>
5327 +#include <bcmutils.h>
5328 +#include <pcicfg.h>
5329 +
5330 +#define ASSERT(n)
5331 +
5332 +/* Pkttag flag should be part of public information */
5333 +typedef struct {
5334 + bool pkttag;
5335 + uint pktalloced; /* Number of allocated packet buffers */
5336 + void *tx_fn;
5337 + void *tx_ctx;
5338 +} osl_pubinfo_t;
5339 +
5340 +struct osl_info {
5341 + osl_pubinfo_t pub;
5342 + uint magic;
5343 + void *pdev;
5344 + uint malloced;
5345 + uint failed;
5346 + void *dbgmem_list;
5347 +};
5348 +
5349 +typedef struct osl_info osl_t;
5350 +
5351 +#define PCI_CFG_RETRY 10
5352 +
5353 +/* map/unmap direction */
5354 +#define DMA_TX 1 /* TX direction for DMA */
5355 +#define DMA_RX 2 /* RX direction for DMA */
5356 +
5357 +#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
5358 +#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
5359 +#define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
5360 +
5361 +/* bcopy, bcmp, and bzero */
5362 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
5363 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
5364 +#define bzero(b, len) memset((b), '\0', (len))
5365 +
5366 +/* uncached virtual address */
5367 +#ifdef mips
5368 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
5369 +#include <asm/addrspace.h>
5370 +#else
5371 +#define OSL_UNCACHED(va) (va)
5372 +#endif /* mips */
5373 +
5374 +
5375 +#ifndef IL_BIGENDIAN
5376 +#define R_REG(osh, r) (\
5377 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
5378 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
5379 + readl((volatile uint32*)(r)) \
5380 +)
5381 +#define W_REG(osh, r, v) do { \
5382 + switch (sizeof(*(r))) { \
5383 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
5384 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
5385 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5386 + } \
5387 +} while (0)
5388 +#else /* IL_BIGENDIAN */
5389 +#define R_REG(osh, r) ({ \
5390 + __typeof(*(r)) __osl_v; \
5391 + switch (sizeof(*(r))) { \
5392 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
5393 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
5394 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
5395 + } \
5396 + __osl_v; \
5397 +})
5398 +#define W_REG(osh, r, v) do { \
5399 + switch (sizeof(*(r))) { \
5400 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
5401 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
5402 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5403 + } \
5404 +} while (0)
5405 +#endif /* IL_BIGENDIAN */
5406 +
5407 +/* dereference an address that may cause a bus exception */
5408 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
5409 +#include <asm/paccess.h>
5410 +
5411 +/* map/unmap physical to virtual I/O */
5412 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
5413 +#define REG_UNMAP(va) iounmap((void *)(va))
5414 +
5415 +/* shared (dma-able) memory access macros */
5416 +#define R_SM(r) *(r)
5417 +#define W_SM(r, v) (*(r) = (v))
5418 +#define BZERO_SM(r, len) memset((r), '\0', (len))
5419 +
5420 +#define MALLOC(osh, size) kmalloc((size), GFP_ATOMIC)
5421 +#define MFREE(osh, addr, size) kfree((addr))
5422 +#define MALLOCED(osh) (0)
5423 +
5424 +#define osl_delay OSL_DELAY
5425 +static inline void OSL_DELAY(uint usec)
5426 +{
5427 + uint d;
5428 +
5429 + while (usec > 0) {
5430 + d = MIN(usec, 1000);
5431 + udelay(d);
5432 + usec -= d;
5433 + }
5434 +}
5435 +
5436 +static inline void
5437 +bcm_mdelay(uint ms)
5438 +{
5439 + uint i;
5440 +
5441 + for (i = 0; i < ms; i++) {
5442 + OSL_DELAY(1000);
5443 + }
5444 +}
5445 +
5446 +
5447 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size)
5448 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
5449 +
5450 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
5451 + osl_pci_read_config((osh), (offset), (size))
5452 +
5453 +static inline uint32
5454 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
5455 +{
5456 + uint val;
5457 + uint retry = PCI_CFG_RETRY;
5458 +
5459 + do {
5460 + pci_read_config_dword(osh->pdev, offset, &val);
5461 + if (val != 0xffffffff)
5462 + break;
5463 + } while (retry--);
5464 +
5465 + return (val);
5466 +}
5467 +
5468 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
5469 + osl_pci_write_config((osh), (offset), (size), (val))
5470 +static inline void
5471 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
5472 +{
5473 + uint retry = PCI_CFG_RETRY;
5474 +
5475 + do {
5476 + pci_write_config_dword(osh->pdev, offset, val);
5477 + if (offset != PCI_BAR0_WIN)
5478 + break;
5479 + if (osl_pci_read_config(osh, offset, size) == val)
5480 + break;
5481 + } while (retry--);
5482 +}
5483 +
5484 +
5485 +/* return bus # for the pci device pointed by osh->pdev */
5486 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
5487 +static inline uint
5488 +osl_pci_bus(osl_t *osh)
5489 +{
5490 + return ((struct pci_dev *)osh->pdev)->bus->number;
5491 +}
5492 +
5493 +/* return slot # for the pci device pointed by osh->pdev */
5494 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
5495 +static inline uint
5496 +osl_pci_slot(osl_t *osh)
5497 +{
5498 + return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
5499 +}
5500 +
5501 +#endif
5502 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
5503 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
5504 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2006-10-02 21:19:59.000000000 +0200
5505 @@ -0,0 +1,495 @@
5506 +/*
5507 + * pcicfg.h: PCI configuration constants and structures.
5508 + *
5509 + * Copyright 2006, Broadcom Corporation
5510 + * All Rights Reserved.
5511 + *
5512 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5513 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5514 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5515 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5516 + *
5517 + * $Id: pcicfg.h,v 1.1.1.11 2006/04/08 06:13:40 honor Exp $
5518 + */
5519 +
5520 +#ifndef _h_pcicfg_
5521 +#define _h_pcicfg_
5522 +
5523 +/* The following inside ifndef's so we don't collide with NTDDK.H */
5524 +#ifndef PCI_MAX_BUS
5525 +#define PCI_MAX_BUS 0x100
5526 +#endif
5527 +#ifndef PCI_MAX_DEVICES
5528 +#define PCI_MAX_DEVICES 0x20
5529 +#endif
5530 +#ifndef PCI_MAX_FUNCTION
5531 +#define PCI_MAX_FUNCTION 0x8
5532 +#endif
5533 +
5534 +#ifndef PCI_INVALID_VENDORID
5535 +#define PCI_INVALID_VENDORID 0xffff
5536 +#endif
5537 +#ifndef PCI_INVALID_DEVICEID
5538 +#define PCI_INVALID_DEVICEID 0xffff
5539 +#endif
5540 +
5541 +
5542 +/* Convert between bus-slot-function-register and config addresses */
5543 +
5544 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
5545 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
5546 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
5547 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
5548 +
5549 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
5550 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
5551 +#define PCICFG_FUN_MASK 7 /* Function mask */
5552 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
5553 +
5554 +#define PCI_CONFIG_ADDR(b, s, f, o) \
5555 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
5556 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
5557 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
5558 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
5559 +
5560 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
5561 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
5562 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
5563 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
5564 +
5565 +/* PCIE Config space accessing MACROS */
5566 +
5567 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
5568 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
5569 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
5570 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
5571 +
5572 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
5573 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
5574 +#define PCIECFG_FUN_MASK 7 /* Function mask */
5575 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
5576 +
5577 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
5578 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
5579 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
5580 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
5581 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
5582 +
5583 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
5584 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
5585 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
5586 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
5587 +
5588 +/* The actual config space */
5589 +
5590 +#define PCI_BAR_MAX 6
5591 +
5592 +#define PCI_ROM_BAR 8
5593 +
5594 +#define PCR_RSVDA_MAX 2
5595 +
5596 +/* Bits in PCI bars' flags */
5597 +
5598 +#define PCIBAR_FLAGS 0xf
5599 +#define PCIBAR_IO 0x1
5600 +#define PCIBAR_MEM1M 0x2
5601 +#define PCIBAR_MEM64 0x4
5602 +#define PCIBAR_PREFETCH 0x8
5603 +#define PCIBAR_MEM32_MASK 0xFFFFFF80
5604 +
5605 +/* pci config status reg has a bit to indicate that capability ptr is present */
5606 +
5607 +#define PCI_CAPPTR_PRESENT 0x0010
5608 +
5609 +typedef struct _pci_config_regs {
5610 + unsigned short vendor;
5611 + unsigned short device;
5612 + unsigned short command;
5613 + unsigned short status;
5614 + unsigned char rev_id;
5615 + unsigned char prog_if;
5616 + unsigned char sub_class;
5617 + unsigned char base_class;
5618 + unsigned char cache_line_size;
5619 + unsigned char latency_timer;
5620 + unsigned char header_type;
5621 + unsigned char bist;
5622 + unsigned long base[PCI_BAR_MAX];
5623 + unsigned long cardbus_cis;
5624 + unsigned short subsys_vendor;
5625 + unsigned short subsys_id;
5626 + unsigned long baserom;
5627 + unsigned long rsvd_a[PCR_RSVDA_MAX];
5628 + unsigned char int_line;
5629 + unsigned char int_pin;
5630 + unsigned char min_gnt;
5631 + unsigned char max_lat;
5632 + unsigned char dev_dep[192];
5633 +} pci_config_regs;
5634 +
5635 +#define SZPCR (sizeof (pci_config_regs))
5636 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
5637 +
5638 +/* A structure for the config registers is nice, but in most
5639 + * systems the config space is not memory mapped, so we need
5640 + * filed offsetts. :-(
5641 + */
5642 +#define PCI_CFG_VID 0
5643 +#define PCI_CFG_DID 2
5644 +#define PCI_CFG_CMD 4
5645 +#define PCI_CFG_STAT 6
5646 +#define PCI_CFG_REV 8
5647 +#define PCI_CFG_PROGIF 9
5648 +#define PCI_CFG_SUBCL 0xa
5649 +#define PCI_CFG_BASECL 0xb
5650 +#define PCI_CFG_CLSZ 0xc
5651 +#define PCI_CFG_LATTIM 0xd
5652 +#define PCI_CFG_HDR 0xe
5653 +#define PCI_CFG_BIST 0xf
5654 +#define PCI_CFG_BAR0 0x10
5655 +#define PCI_CFG_BAR1 0x14
5656 +#define PCI_CFG_BAR2 0x18
5657 +#define PCI_CFG_BAR3 0x1c
5658 +#define PCI_CFG_BAR4 0x20
5659 +#define PCI_CFG_BAR5 0x24
5660 +#define PCI_CFG_CIS 0x28
5661 +#define PCI_CFG_SVID 0x2c
5662 +#define PCI_CFG_SSID 0x2e
5663 +#define PCI_CFG_ROMBAR 0x30
5664 +#define PCI_CFG_CAPPTR 0x34
5665 +#define PCI_CFG_INT 0x3c
5666 +#define PCI_CFG_PIN 0x3d
5667 +#define PCI_CFG_MINGNT 0x3e
5668 +#define PCI_CFG_MAXLAT 0x3f
5669 +
5670 +#ifdef __NetBSD__
5671 +#undef PCI_CLASS_DISPLAY
5672 +#undef PCI_CLASS_MEMORY
5673 +#undef PCI_CLASS_BRIDGE
5674 +#undef PCI_CLASS_INPUT
5675 +#undef PCI_CLASS_DOCK
5676 +#endif /* __NetBSD__ */
5677 +
5678 +/* Classes and subclasses */
5679 +
5680 +typedef enum {
5681 + PCI_CLASS_OLD = 0,
5682 + PCI_CLASS_DASDI,
5683 + PCI_CLASS_NET,
5684 + PCI_CLASS_DISPLAY,
5685 + PCI_CLASS_MMEDIA,
5686 + PCI_CLASS_MEMORY,
5687 + PCI_CLASS_BRIDGE,
5688 + PCI_CLASS_COMM,
5689 + PCI_CLASS_BASE,
5690 + PCI_CLASS_INPUT,
5691 + PCI_CLASS_DOCK,
5692 + PCI_CLASS_CPU,
5693 + PCI_CLASS_SERIAL,
5694 + PCI_CLASS_INTELLIGENT = 0xe,
5695 + PCI_CLASS_SATELLITE,
5696 + PCI_CLASS_CRYPT,
5697 + PCI_CLASS_DSP,
5698 + PCI_CLASS_XOR = 0xfe
5699 +} pci_classes;
5700 +
5701 +typedef enum {
5702 + PCI_DASDI_SCSI,
5703 + PCI_DASDI_IDE,
5704 + PCI_DASDI_FLOPPY,
5705 + PCI_DASDI_IPI,
5706 + PCI_DASDI_RAID,
5707 + PCI_DASDI_OTHER = 0x80
5708 +} pci_dasdi_subclasses;
5709 +
5710 +typedef enum {
5711 + PCI_NET_ETHER,
5712 + PCI_NET_TOKEN,
5713 + PCI_NET_FDDI,
5714 + PCI_NET_ATM,
5715 + PCI_NET_OTHER = 0x80
5716 +} pci_net_subclasses;
5717 +
5718 +typedef enum {
5719 + PCI_DISPLAY_VGA,
5720 + PCI_DISPLAY_XGA,
5721 + PCI_DISPLAY_3D,
5722 + PCI_DISPLAY_OTHER = 0x80
5723 +} pci_display_subclasses;
5724 +
5725 +typedef enum {
5726 + PCI_MMEDIA_VIDEO,
5727 + PCI_MMEDIA_AUDIO,
5728 + PCI_MMEDIA_PHONE,
5729 + PCI_MEDIA_OTHER = 0x80
5730 +} pci_mmedia_subclasses;
5731 +
5732 +typedef enum {
5733 + PCI_MEMORY_RAM,
5734 + PCI_MEMORY_FLASH,
5735 + PCI_MEMORY_OTHER = 0x80
5736 +} pci_memory_subclasses;
5737 +
5738 +typedef enum {
5739 + PCI_BRIDGE_HOST,
5740 + PCI_BRIDGE_ISA,
5741 + PCI_BRIDGE_EISA,
5742 + PCI_BRIDGE_MC,
5743 + PCI_BRIDGE_PCI,
5744 + PCI_BRIDGE_PCMCIA,
5745 + PCI_BRIDGE_NUBUS,
5746 + PCI_BRIDGE_CARDBUS,
5747 + PCI_BRIDGE_RACEWAY,
5748 + PCI_BRIDGE_OTHER = 0x80
5749 +} pci_bridge_subclasses;
5750 +
5751 +typedef enum {
5752 + PCI_COMM_UART,
5753 + PCI_COMM_PARALLEL,
5754 + PCI_COMM_MULTIUART,
5755 + PCI_COMM_MODEM,
5756 + PCI_COMM_OTHER = 0x80
5757 +} pci_comm_subclasses;
5758 +
5759 +typedef enum {
5760 + PCI_BASE_PIC,
5761 + PCI_BASE_DMA,
5762 + PCI_BASE_TIMER,
5763 + PCI_BASE_RTC,
5764 + PCI_BASE_PCI_HOTPLUG,
5765 + PCI_BASE_OTHER = 0x80
5766 +} pci_base_subclasses;
5767 +
5768 +typedef enum {
5769 + PCI_INPUT_KBD,
5770 + PCI_INPUT_PEN,
5771 + PCI_INPUT_MOUSE,
5772 + PCI_INPUT_SCANNER,
5773 + PCI_INPUT_GAMEPORT,
5774 + PCI_INPUT_OTHER = 0x80
5775 +} pci_input_subclasses;
5776 +
5777 +typedef enum {
5778 + PCI_DOCK_GENERIC,
5779 + PCI_DOCK_OTHER = 0x80
5780 +} pci_dock_subclasses;
5781 +
5782 +typedef enum {
5783 + PCI_CPU_386,
5784 + PCI_CPU_486,
5785 + PCI_CPU_PENTIUM,
5786 + PCI_CPU_ALPHA = 0x10,
5787 + PCI_CPU_POWERPC = 0x20,
5788 + PCI_CPU_MIPS = 0x30,
5789 + PCI_CPU_COPROC = 0x40,
5790 + PCI_CPU_OTHER = 0x80
5791 +} pci_cpu_subclasses;
5792 +
5793 +typedef enum {
5794 + PCI_SERIAL_IEEE1394,
5795 + PCI_SERIAL_ACCESS,
5796 + PCI_SERIAL_SSA,
5797 + PCI_SERIAL_USB,
5798 + PCI_SERIAL_FIBER,
5799 + PCI_SERIAL_SMBUS,
5800 + PCI_SERIAL_OTHER = 0x80
5801 +} pci_serial_subclasses;
5802 +
5803 +typedef enum {
5804 + PCI_INTELLIGENT_I2O
5805 +} pci_intelligent_subclasses;
5806 +
5807 +typedef enum {
5808 + PCI_SATELLITE_TV,
5809 + PCI_SATELLITE_AUDIO,
5810 + PCI_SATELLITE_VOICE,
5811 + PCI_SATELLITE_DATA,
5812 + PCI_SATELLITE_OTHER = 0x80
5813 +} pci_satellite_subclasses;
5814 +
5815 +typedef enum {
5816 + PCI_CRYPT_NETWORK,
5817 + PCI_CRYPT_ENTERTAINMENT,
5818 + PCI_CRYPT_OTHER = 0x80
5819 +} pci_crypt_subclasses;
5820 +
5821 +typedef enum {
5822 + PCI_DSP_DPIO,
5823 + PCI_DSP_OTHER = 0x80
5824 +} pci_dsp_subclasses;
5825 +
5826 +typedef enum {
5827 + PCI_XOR_QDMA,
5828 + PCI_XOR_OTHER = 0x80
5829 +} pci_xor_subclasses;
5830 +
5831 +/* Header types */
5832 +typedef enum {
5833 + PCI_HEADER_NORMAL,
5834 + PCI_HEADER_BRIDGE,
5835 + PCI_HEADER_CARDBUS
5836 +} pci_header_types;
5837 +
5838 +
5839 +/* Overlay for a PCI-to-PCI bridge */
5840 +
5841 +#define PPB_RSVDA_MAX 2
5842 +#define PPB_RSVDD_MAX 8
5843 +
5844 +typedef struct _ppb_config_regs {
5845 + unsigned short vendor;
5846 + unsigned short device;
5847 + unsigned short command;
5848 + unsigned short status;
5849 + unsigned char rev_id;
5850 + unsigned char prog_if;
5851 + unsigned char sub_class;
5852 + unsigned char base_class;
5853 + unsigned char cache_line_size;
5854 + unsigned char latency_timer;
5855 + unsigned char header_type;
5856 + unsigned char bist;
5857 + unsigned long rsvd_a[PPB_RSVDA_MAX];
5858 + unsigned char prim_bus;
5859 + unsigned char sec_bus;
5860 + unsigned char sub_bus;
5861 + unsigned char sec_lat;
5862 + unsigned char io_base;
5863 + unsigned char io_lim;
5864 + unsigned short sec_status;
5865 + unsigned short mem_base;
5866 + unsigned short mem_lim;
5867 + unsigned short pf_mem_base;
5868 + unsigned short pf_mem_lim;
5869 + unsigned long pf_mem_base_hi;
5870 + unsigned long pf_mem_lim_hi;
5871 + unsigned short io_base_hi;
5872 + unsigned short io_lim_hi;
5873 + unsigned short subsys_vendor;
5874 + unsigned short subsys_id;
5875 + unsigned long rsvd_b;
5876 + unsigned char rsvd_c;
5877 + unsigned char int_pin;
5878 + unsigned short bridge_ctrl;
5879 + unsigned char chip_ctrl;
5880 + unsigned char diag_ctrl;
5881 + unsigned short arb_ctrl;
5882 + unsigned long rsvd_d[PPB_RSVDD_MAX];
5883 + unsigned char dev_dep[192];
5884 +} ppb_config_regs;
5885 +
5886 +
5887 +/* PCI CAPABILITY DEFINES */
5888 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
5889 +#define PCI_CAP_MSICAP_ID 0x05
5890 +#define PCI_CAP_PCIECAP_ID 0x10
5891 +
5892 +/* Data structure to define the Message Signalled Interrupt facility
5893 + * Valid for PCI and PCIE configurations
5894 + */
5895 +typedef struct _pciconfig_cap_msi {
5896 + unsigned char capID;
5897 + unsigned char nextptr;
5898 + unsigned short msgctrl;
5899 + unsigned int msgaddr;
5900 +} pciconfig_cap_msi;
5901 +
5902 +/* Data structure to define the Power managment facility
5903 + * Valid for PCI and PCIE configurations
5904 + */
5905 +typedef struct _pciconfig_cap_pwrmgmt {
5906 + unsigned char capID;
5907 + unsigned char nextptr;
5908 + unsigned short pme_cap;
5909 + unsigned short pme_sts_ctrl;
5910 + unsigned char pme_bridge_ext;
5911 + unsigned char data;
5912 +} pciconfig_cap_pwrmgmt;
5913 +
5914 +/* Data structure to define the PCIE capability */
5915 +typedef struct _pciconfig_cap_pcie {
5916 + unsigned char capID;
5917 + unsigned char nextptr;
5918 + unsigned short pcie_cap;
5919 + unsigned int dev_cap;
5920 + unsigned short dev_ctrl;
5921 + unsigned short dev_status;
5922 + unsigned int link_cap;
5923 + unsigned short link_ctrl;
5924 + unsigned short link_status;
5925 +} pciconfig_cap_pcie;
5926 +
5927 +/* PCIE Enhanced CAPABILITY DEFINES */
5928 +#define PCIE_EXTCFG_OFFSET 0x100
5929 +#define PCIE_ADVERRREP_CAPID 0x0001
5930 +#define PCIE_VC_CAPID 0x0002
5931 +#define PCIE_DEVSNUM_CAPID 0x0003
5932 +#define PCIE_PWRBUDGET_CAPID 0x0004
5933 +
5934 +/* Header to define the PCIE specific capabilities in the extended config space */
5935 +typedef struct _pcie_enhanced_caphdr {
5936 + unsigned short capID;
5937 + unsigned short cap_ver : 4;
5938 + unsigned short next_ptr : 12;
5939 +} pcie_enhanced_caphdr;
5940 +
5941 +
5942 +/* Everything below is BRCM HND proprietary */
5943 +
5944 +
5945 +/* Brcm PCI configuration registers */
5946 +#define cap_list rsvd_a[0]
5947 +#define bar0_window dev_dep[0x80 - 0x40]
5948 +#define bar1_window dev_dep[0x84 - 0x40]
5949 +#define sprom_control dev_dep[0x88 - 0x40]
5950 +
5951 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
5952 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
5953 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
5954 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
5955 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
5956 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
5957 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
5958 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
5959 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address */
5960 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
5961 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
5962 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
5963 +
5964 +#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
5965 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
5966 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
5967 +#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
5968 + * 8KB window, so their address is the "regular"
5969 + * address plus 4K
5970 + */
5971 +#define PCI_BAR0_WINSZ 8192 /* bar0 window size */
5972 +
5973 +/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
5974 +#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
5975 +#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
5976 +#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
5977 +
5978 +/* PCI_INT_STATUS */
5979 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
5980 +
5981 +/* PCI_INT_MASK */
5982 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
5983 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
5984 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
5985 +
5986 +/* PCI_SPROM_CONTROL */
5987 +#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
5988 +#define SPROM_LOCKED 0x08 /* SPROM Locked */
5989 +#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
5990 +#define SPROM_WRITEEN 0x10 /* SPROM write enable */
5991 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
5992 +#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
5993 +
5994 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
5995 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
5996 +
5997 +/* PCI_CFG_CMD_STAT */
5998 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
5999 +
6000 +#endif /* _h_pcicfg_ */
6001 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
6002 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
6003 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2006-10-02 21:19:59.000000000 +0200
6004 @@ -0,0 +1,516 @@
6005 +/*
6006 + * SiliconBackplane Chipcommon core hardware definitions.
6007 + *
6008 + * The chipcommon core provides chip identification, SB control,
6009 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6010 + * gpio interface, extbus, and support for serial and parallel flashes.
6011 + *
6012 + * $Id: sbchipc.h,v 1.1.1.14 2006/04/15 01:29:08 michael Exp $
6013 + * Copyright 2006, Broadcom Corporation
6014 + * All Rights Reserved.
6015 + *
6016 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6017 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6018 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6019 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6020 + *
6021 + */
6022 +
6023 +#ifndef _SBCHIPC_H
6024 +#define _SBCHIPC_H
6025 +
6026 +
6027 +#ifndef _LANGUAGE_ASSEMBLY
6028 +
6029 +/* cpp contortions to concatenate w/arg prescan */
6030 +#ifndef PAD
6031 +#define _PADLINE(line) pad ## line
6032 +#define _XSTR(line) _PADLINE(line)
6033 +#define PAD _XSTR(__LINE__)
6034 +#endif /* PAD */
6035 +
6036 +typedef volatile struct {
6037 + uint32 chipid; /* 0x0 */
6038 + uint32 capabilities;
6039 + uint32 corecontrol; /* corerev >= 1 */
6040 + uint32 bist;
6041 +
6042 + /* OTP */
6043 + uint32 otpstatus; /* 0x10, corerev >= 10 */
6044 + uint32 otpcontrol;
6045 + uint32 otpprog;
6046 + uint32 PAD;
6047 +
6048 + /* Interrupt control */
6049 + uint32 intstatus; /* 0x20 */
6050 + uint32 intmask;
6051 + uint32 chipcontrol; /* 0x28, rev >= 11 */
6052 + uint32 chipstatus; /* 0x2c, rev >= 11 */
6053 +
6054 + /* Jtag Master */
6055 + uint32 jtagcmd; /* 0x30, rev >= 10 */
6056 + uint32 jtagir;
6057 + uint32 jtagdr;
6058 + uint32 jtagctrl;
6059 +
6060 + /* serial flash interface registers */
6061 + uint32 flashcontrol; /* 0x40 */
6062 + uint32 flashaddress;
6063 + uint32 flashdata;
6064 + uint32 PAD[1];
6065 +
6066 + /* Silicon backplane configuration broadcast control */
6067 + uint32 broadcastaddress; /* 0x50 */
6068 + uint32 broadcastdata;
6069 + uint32 PAD[2];
6070 +
6071 + /* gpio - cleared only by power-on-reset */
6072 + uint32 gpioin; /* 0x60 */
6073 + uint32 gpioout;
6074 + uint32 gpioouten;
6075 + uint32 gpiocontrol;
6076 + uint32 gpiointpolarity;
6077 + uint32 gpiointmask;
6078 + uint32 PAD[2];
6079 +
6080 + /* Watchdog timer */
6081 + uint32 watchdog; /* 0x80 */
6082 + uint32 PAD[1];
6083 +
6084 + /* GPIO based LED powersave registers corerev >= 16 */
6085 + uint32 gpiotimerval; /* 0x88 */
6086 + uint32 gpiotimeroutmask;
6087 +
6088 + /* clock control */
6089 + uint32 clockcontrol_n; /* 0x90 */
6090 + uint32 clockcontrol_sb; /* aka m0 */
6091 + uint32 clockcontrol_pci; /* aka m1 */
6092 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
6093 + uint32 clockcontrol_m3; /* cpu */
6094 + uint32 clkdiv; /* corerev >= 3 */
6095 + uint32 PAD[2];
6096 +
6097 + /* pll delay registers (corerev >= 4) */
6098 + uint32 pll_on_delay; /* 0xb0 */
6099 + uint32 fref_sel_delay;
6100 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
6101 + uint32 PAD[1];
6102 +
6103 + /* Instaclock registers (corerev >= 10) */
6104 + uint32 system_clk_ctl; /* 0xc0 */
6105 + uint32 clkstatestretch;
6106 + uint32 PAD[14];
6107 +
6108 + /* ExtBus control registers (corerev >= 3) */
6109 + uint32 pcmcia_config; /* 0x100 */
6110 + uint32 pcmcia_memwait;
6111 + uint32 pcmcia_attrwait;
6112 + uint32 pcmcia_iowait;
6113 + uint32 ide_config;
6114 + uint32 ide_memwait;
6115 + uint32 ide_attrwait;
6116 + uint32 ide_iowait;
6117 + uint32 prog_config;
6118 + uint32 prog_waitcount;
6119 + uint32 flash_config;
6120 + uint32 flash_waitcount;
6121 + uint32 PAD[44];
6122 +
6123 + /* Clock control and hardware workarounds */
6124 + uint32 clk_ctl_st;
6125 + uint32 hw_war;
6126 + uint32 PAD[70];
6127 +
6128 + /* uarts */
6129 + uint8 uart0data; /* 0x300 */
6130 + uint8 uart0imr;
6131 + uint8 uart0fcr;
6132 + uint8 uart0lcr;
6133 + uint8 uart0mcr;
6134 + uint8 uart0lsr;
6135 + uint8 uart0msr;
6136 + uint8 uart0scratch;
6137 + uint8 PAD[248]; /* corerev >= 1 */
6138 +
6139 + uint8 uart1data; /* 0x400 */
6140 + uint8 uart1imr;
6141 + uint8 uart1fcr;
6142 + uint8 uart1lcr;
6143 + uint8 uart1mcr;
6144 + uint8 uart1lsr;
6145 + uint8 uart1msr;
6146 + uint8 uart1scratch;
6147 +} chipcregs_t;
6148 +
6149 +#endif /* _LANGUAGE_ASSEMBLY */
6150 +
6151 +#define CC_CHIPID 0
6152 +#define CC_CAPABILITIES 4
6153 +#define CC_JTAGCMD 0x30
6154 +#define CC_JTAGIR 0x34
6155 +#define CC_JTAGDR 0x38
6156 +#define CC_JTAGCTRL 0x3c
6157 +#define CC_WATCHDOG 0x80
6158 +#define CC_CLKC_N 0x90
6159 +#define CC_CLKC_M0 0x94
6160 +#define CC_CLKC_M1 0x98
6161 +#define CC_CLKC_M2 0x9c
6162 +#define CC_CLKC_M3 0xa0
6163 +#define CC_CLKDIV 0xa4
6164 +#define CC_SYS_CLK_CTL 0xc0
6165 +#define CC_OTP 0x800
6166 +
6167 +/* chipid */
6168 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
6169 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
6170 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
6171 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
6172 +#define CID_PKG_SHIFT 20 /* Package Option shift */
6173 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
6174 +#define CID_CC_SHIFT 24
6175 +
6176 +/* capabilities */
6177 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
6178 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
6179 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
6180 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
6181 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
6182 +#define CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
6183 +#define CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
6184 +#define CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
6185 +#define CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
6186 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
6187 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
6188 +#define CAP_PWR_CTL 0x00040000 /* Power control */
6189 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
6190 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
6191 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
6192 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
6193 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
6194 +#define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
6195 +
6196 +/* PLL type */
6197 +#define PLL_NONE 0x00000000
6198 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
6199 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
6200 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
6201 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
6202 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
6203 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
6204 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
6205 +
6206 +/* corecontrol */
6207 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
6208 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
6209 +
6210 +/* chipcontrol */
6211 +#define CHIPCTRL_4321A0_DEFAULT 0x3a4
6212 +#define CHIPCTRL_4321A1_DEFAULT 0x0a4
6213 +
6214 +/* Fields in the otpstatus register */
6215 +#define OTPS_PROGFAIL 0x80000000
6216 +#define OTPS_PROTECT 0x00000007
6217 +#define OTPS_HW_PROTECT 0x00000001
6218 +#define OTPS_SW_PROTECT 0x00000002
6219 +#define OTPS_CID_PROTECT 0x00000004
6220 +
6221 +/* Fields in the otpcontrol register */
6222 +#define OTPC_RECWAIT 0xff000000
6223 +#define OTPC_PROGWAIT 0x00ffff00
6224 +#define OTPC_PRW_SHIFT 8
6225 +#define OTPC_MAXFAIL 0x00000038
6226 +#define OTPC_VSEL 0x00000006
6227 +#define OTPC_SELVL 0x00000001
6228 +
6229 +/* Fields in otpprog */
6230 +#define OTPP_COL_MASK 0x000000ff
6231 +#define OTPP_ROW_MASK 0x0000ff00
6232 +#define OTPP_ROW_SHIFT 8
6233 +#define OTPP_READERR 0x10000000
6234 +#define OTPP_VALUE 0x20000000
6235 +#define OTPP_VALUE_SHIFT 29
6236 +#define OTPP_READ 0x40000000
6237 +#define OTPP_START 0x80000000
6238 +#define OTPP_BUSY 0x80000000
6239 +
6240 +/* jtagcmd */
6241 +#define JCMD_START 0x80000000
6242 +#define JCMD_BUSY 0x80000000
6243 +#define JCMD_PAUSE 0x40000000
6244 +#define JCMD0_ACC_MASK 0x0000f000
6245 +#define JCMD0_ACC_IRDR 0x00000000
6246 +#define JCMD0_ACC_DR 0x00001000
6247 +#define JCMD0_ACC_IR 0x00002000
6248 +#define JCMD0_ACC_RESET 0x00003000
6249 +#define JCMD0_ACC_IRPDR 0x00004000
6250 +#define JCMD0_ACC_PDR 0x00005000
6251 +#define JCMD0_IRW_MASK 0x00000f00
6252 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
6253 +#define JCMD_ACC_IRDR 0x00000000
6254 +#define JCMD_ACC_DR 0x00010000
6255 +#define JCMD_ACC_IR 0x00020000
6256 +#define JCMD_ACC_RESET 0x00030000
6257 +#define JCMD_ACC_IRPDR 0x00040000
6258 +#define JCMD_ACC_PDR 0x00050000
6259 +#define JCMD_IRW_MASK 0x00001f00
6260 +#define JCMD_IRW_SHIFT 8
6261 +#define JCMD_DRW_MASK 0x0000003f
6262 +
6263 +/* jtagctrl */
6264 +#define JCTRL_FORCE_CLK 4 /* Force clock */
6265 +#define JCTRL_EXT_EN 2 /* Enable external targets */
6266 +#define JCTRL_EN 1 /* Enable Jtag master */
6267 +
6268 +/* Fields in clkdiv */
6269 +#define CLKD_SFLASH 0x0f000000
6270 +#define CLKD_SFLASH_SHIFT 24
6271 +#define CLKD_OTP 0x000f0000
6272 +#define CLKD_OTP_SHIFT 16
6273 +#define CLKD_JTAG 0x00000f00
6274 +#define CLKD_JTAG_SHIFT 8
6275 +#define CLKD_UART 0x000000ff
6276 +
6277 +/* intstatus/intmask */
6278 +#define CI_GPIO 0x00000001 /* gpio intr */
6279 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
6280 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
6281 +
6282 +/* slow_clk_ctl */
6283 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
6284 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
6285 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
6286 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
6287 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
6288 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
6289 + * 0: LPO is enabled
6290 + */
6291 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
6292 + * 0: power logic control
6293 + */
6294 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
6295 + * PLL clock disable requests from core
6296 + */
6297 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
6298 + * disable crystal when appropriate
6299 + */
6300 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
6301 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
6302 +#define SCC_CD_SHIFT 16
6303 +
6304 +/* system_clk_ctl */
6305 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
6306 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
6307 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
6308 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
6309 +#define SYCC_HR 0x00000010 /* Force HT */
6310 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
6311 +#define SYCC_CD_SHIFT 16
6312 +
6313 +/* gpiotimerval */
6314 +#define GPIO_ONTIME_SHIFT 16
6315 +
6316 +/* clockcontrol_n */
6317 +#define CN_N1_MASK 0x3f /* n1 control */
6318 +#define CN_N2_MASK 0x3f00 /* n2 control */
6319 +#define CN_N2_SHIFT 8
6320 +#define CN_PLLC_MASK 0xf0000 /* pll control */
6321 +#define CN_PLLC_SHIFT 16
6322 +
6323 +/* clockcontrol_sb/pci/uart */
6324 +#define CC_M1_MASK 0x3f /* m1 control */
6325 +#define CC_M2_MASK 0x3f00 /* m2 control */
6326 +#define CC_M2_SHIFT 8
6327 +#define CC_M3_MASK 0x3f0000 /* m3 control */
6328 +#define CC_M3_SHIFT 16
6329 +#define CC_MC_MASK 0x1f000000 /* mux control */
6330 +#define CC_MC_SHIFT 24
6331 +
6332 +/* N3M Clock control magic field values */
6333 +#define CC_F6_2 0x02 /* A factor of 2 in */
6334 +#define CC_F6_3 0x03 /* 6-bit fields like */
6335 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
6336 +#define CC_F6_5 0x09
6337 +#define CC_F6_6 0x11
6338 +#define CC_F6_7 0x21
6339 +
6340 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
6341 +
6342 +#define CC_MC_BYPASS 0x08
6343 +#define CC_MC_M1 0x04
6344 +#define CC_MC_M1M2 0x02
6345 +#define CC_MC_M1M2M3 0x01
6346 +#define CC_MC_M1M3 0x11
6347 +
6348 +/* Type 2 Clock control magic field values */
6349 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
6350 +#define CC_T2M2_BIAS 3 /* m2 bias */
6351 +
6352 +#define CC_T2MC_M1BYP 1
6353 +#define CC_T2MC_M2BYP 2
6354 +#define CC_T2MC_M3BYP 4
6355 +
6356 +/* Type 6 Clock control magic field values */
6357 +#define CC_T6_MMASK 1 /* bits of interest in m */
6358 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
6359 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
6360 +#define SB2MIPS_T6(sb) (2 * (sb))
6361 +
6362 +/* Common clock base */
6363 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
6364 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
6365 +
6366 +/* Clock control values for 200Mhz in 5350 */
6367 +#define CLKC_5350_N 0x0311
6368 +#define CLKC_5350_M 0x04020009
6369 +
6370 +/* Flash types in the chipcommon capabilities register */
6371 +#define FLASH_NONE 0x000 /* No flash */
6372 +#define SFLASH_ST 0x100 /* ST serial flash */
6373 +#define SFLASH_AT 0x200 /* Atmel serial flash */
6374 +#define PFLASH 0x700 /* Parallel flash */
6375 +
6376 +/* Bits in the ExtBus config registers */
6377 +#define CC_CFG_EN 0x0001 /* Enable */
6378 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
6379 +#define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
6380 +#define CC_CFG_EM_SYNC 0x0002 /* Synchronous */
6381 +#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
6382 +#define CC_CFG_EM_IDE 0x0006 /* IDE */
6383 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
6384 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
6385 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
6386 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
6387 +
6388 +/* ExtBus address space */
6389 +#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
6390 +#define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
6391 +#define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
6392 +#define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
6393 +#define CC_EB_IDE 0x1a800000 /* IDE memory base */
6394 +#define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
6395 +#define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
6396 +#define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
6397 +#define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
6398 +
6399 +
6400 +/* Start/busy bit in flashcontrol */
6401 +#define SFLASH_OPCODE 0x000000ff
6402 +#define SFLASH_ACTION 0x00000700
6403 +#define SFLASH_START 0x80000000
6404 +#define SFLASH_BUSY SFLASH_START
6405 +
6406 +/* flashcontrol action codes */
6407 +#define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
6408 +#define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
6409 +#define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 address bytes */
6410 +#define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addres & 1 data bytes */
6411 +#define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addres & 4 data bytes */
6412 +#define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addres, 4 don't care & 4 data bytes */
6413 +#define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addres, 1 don't care & 4 data bytes */
6414 +
6415 +/* flashcontrol action+opcodes for ST flashes */
6416 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
6417 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
6418 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
6419 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
6420 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
6421 +#define SFLASH_ST_PP 0x0302 /* Page Program */
6422 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
6423 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
6424 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
6425 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
6426 +
6427 +/* Status register bits for ST flashes */
6428 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
6429 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
6430 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
6431 +#define SFLASH_ST_BP_SHIFT 2
6432 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
6433 +
6434 +/* flashcontrol action+opcodes for Atmel flashes */
6435 +#define SFLASH_AT_READ 0x07e8
6436 +#define SFLASH_AT_PAGE_READ 0x07d2
6437 +#define SFLASH_AT_BUF1_READ
6438 +#define SFLASH_AT_BUF2_READ
6439 +#define SFLASH_AT_STATUS 0x01d7
6440 +#define SFLASH_AT_BUF1_WRITE 0x0384
6441 +#define SFLASH_AT_BUF2_WRITE 0x0387
6442 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
6443 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
6444 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
6445 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
6446 +#define SFLASH_AT_PAGE_ERASE 0x0281
6447 +#define SFLASH_AT_BLOCK_ERASE 0x0250
6448 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
6449 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
6450 +#define SFLASH_AT_BUF1_LOAD 0x0253
6451 +#define SFLASH_AT_BUF2_LOAD 0x0255
6452 +#define SFLASH_AT_BUF1_COMPARE 0x0260
6453 +#define SFLASH_AT_BUF2_COMPARE 0x0261
6454 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
6455 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
6456 +
6457 +/* Status register bits for Atmel flashes */
6458 +#define SFLASH_AT_READY 0x80
6459 +#define SFLASH_AT_MISMATCH 0x40
6460 +#define SFLASH_AT_ID_MASK 0x38
6461 +#define SFLASH_AT_ID_SHIFT 3
6462 +
6463 +/* OTP regions */
6464 +#define OTP_HW_REGION OTPS_HW_PROTECT
6465 +#define OTP_SW_REGION OTPS_SW_PROTECT
6466 +#define OTP_CID_REGION OTPS_CID_PROTECT
6467 +
6468 +/* OTP regions (Byte offsets from otp size) */
6469 +#define OTP_SWLIM_OFF (-8)
6470 +#define OTP_CIDBASE_OFF 0
6471 +#define OTP_CIDLIM_OFF 8
6472 +
6473 +/* Predefined OTP words (Word offset from otp size) */
6474 +#define OTP_BOUNDARY_OFF (-4)
6475 +#define OTP_HWSIGN_OFF (-3)
6476 +#define OTP_SWSIGN_OFF (-2)
6477 +#define OTP_CIDSIGN_OFF (-1)
6478 +
6479 +#define OTP_CID_OFF 0
6480 +#define OTP_PKG_OFF 1
6481 +#define OTP_FID_OFF 2
6482 +#define OTP_RSV_OFF 3
6483 +#define OTP_LIM_OFF 4
6484 +
6485 +#define OTP_SIGNATURE 0x578a
6486 +#define OTP_MAGIC 0x4e56
6487 +
6488 +/*
6489 + * These are the UART port assignments, expressed as offsets from the base
6490 + * register. These assignments should hold for any serial port based on
6491 + * a 8250, 16450, or 16550(A).
6492 + */
6493 +
6494 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
6495 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
6496 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
6497 +#define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
6498 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
6499 +#define UART_IIR 2 /* In: Interrupt Identity Register */
6500 +#define UART_FCR 2 /* Out: FIFO Control Register */
6501 +#define UART_LCR 3 /* Out: Line Control Register */
6502 +#define UART_MCR 4 /* Out: Modem Control Register */
6503 +#define UART_LSR 5 /* In: Line Status Register */
6504 +#define UART_MSR 6 /* In: Modem Status Register */
6505 +#define UART_SCR 7 /* I/O: Scratch Register */
6506 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
6507 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
6508 +#define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
6509 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
6510 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
6511 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
6512 +#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
6513 +
6514 +/* Interrupt Enable Register (IER) bits */
6515 +#define UART_IER_EDSSI 8 /* enable modem status interrupt */
6516 +#define UART_IER_ELSI 4 /* enable receiver line status interrupt */
6517 +#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
6518 +#define UART_IER_ERBFI 1 /* enable data available interrupt */
6519 +
6520 +#endif /* _SBCHIPC_H */
6521 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
6522 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
6523 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2006-10-02 21:19:59.000000000 +0200
6524 @@ -0,0 +1,369 @@
6525 +/*
6526 + * Broadcom SiliconBackplane hardware register definitions.
6527 + *
6528 + * Copyright 2006, Broadcom Corporation
6529 + * All Rights Reserved.
6530 + *
6531 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6532 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6533 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6534 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6535 + *
6536 + * $Id: sbconfig.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
6537 + */
6538 +
6539 +#ifndef _SBCONFIG_H
6540 +#define _SBCONFIG_H
6541 +
6542 +/* cpp contortions to concatenate w/arg prescan */
6543 +#ifndef PAD
6544 +#define _PADLINE(line) pad ## line
6545 +#define _XSTR(line) _PADLINE(line)
6546 +#define PAD _XSTR(__LINE__)
6547 +#endif
6548 +
6549 +/*
6550 + * SiliconBackplane Address Map.
6551 + * All regions may not exist on all chips.
6552 + */
6553 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
6554 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
6555 +#define SB_PCI_MEM_SZ (64 * 1024 * 1024)
6556 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
6557 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6558 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
6559 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
6560 +
6561 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
6562 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
6563 +
6564 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
6565 +#define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
6566 +#define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
6567 +
6568 +#define SB_ROM 0x20000000 /* ARM ROM */
6569 +#define SB_SRAM2 0x80000000 /* ARM SRAM Region 2 */
6570 +#define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
6571 +#define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
6572 +
6573 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
6574 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
6575 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
6576 + * (2 ZettaBytes), low 32 bits
6577 + */
6578 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
6579 + * (2 ZettaBytes), high 32 bits
6580 + */
6581 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
6582 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
6583 +
6584 +
6585 +/* enumeration space related defs */
6586 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
6587 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
6588 +#define SB_MAXFUNCS 4 /* max. # functions per core */
6589 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
6590 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
6591 +
6592 +/* mips address */
6593 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6594 +
6595 +/*
6596 + * Sonics Configuration Space Registers.
6597 + */
6598 +#define SBIPSFLAG 0x08
6599 +#define SBTPSFLAG 0x18
6600 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
6601 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
6602 +#define SBADMATCH3 0x60
6603 +#define SBADMATCH2 0x68
6604 +#define SBADMATCH1 0x70
6605 +#define SBIMSTATE 0x90
6606 +#define SBINTVEC 0x94
6607 +#define SBTMSTATELOW 0x98
6608 +#define SBTMSTATEHIGH 0x9c
6609 +#define SBBWA0 0xa0
6610 +#define SBIMCONFIGLOW 0xa8
6611 +#define SBIMCONFIGHIGH 0xac
6612 +#define SBADMATCH0 0xb0
6613 +#define SBTMCONFIGLOW 0xb8
6614 +#define SBTMCONFIGHIGH 0xbc
6615 +#define SBBCONFIG 0xc0
6616 +#define SBBSTATE 0xc8
6617 +#define SBACTCNFG 0xd8
6618 +#define SBFLAGST 0xe8
6619 +#define SBIDLOW 0xf8
6620 +#define SBIDHIGH 0xfc
6621 +
6622 +/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
6623 + * a few registers *below* that line. I think it would be very confusing to try
6624 + * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
6625 + */
6626 +
6627 +#define SBIMERRLOGA 0xea8
6628 +#define SBIMERRLOG 0xeb0
6629 +#define SBTMPORTCONNID0 0xed8
6630 +#define SBTMPORTLOCK0 0xef8
6631 +
6632 +#ifndef _LANGUAGE_ASSEMBLY
6633 +
6634 +typedef volatile struct _sbconfig {
6635 + uint32 PAD[2];
6636 + uint32 sbipsflag; /* initiator port ocp slave flag */
6637 + uint32 PAD[3];
6638 + uint32 sbtpsflag; /* target port ocp slave flag */
6639 + uint32 PAD[11];
6640 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
6641 + uint32 PAD;
6642 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
6643 + uint32 PAD[3];
6644 + uint32 sbadmatch3; /* address match3 */
6645 + uint32 PAD;
6646 + uint32 sbadmatch2; /* address match2 */
6647 + uint32 PAD;
6648 + uint32 sbadmatch1; /* address match1 */
6649 + uint32 PAD[7];
6650 + uint32 sbimstate; /* initiator agent state */
6651 + uint32 sbintvec; /* interrupt mask */
6652 + uint32 sbtmstatelow; /* target state */
6653 + uint32 sbtmstatehigh; /* target state */
6654 + uint32 sbbwa0; /* bandwidth allocation table0 */
6655 + uint32 PAD;
6656 + uint32 sbimconfiglow; /* initiator configuration */
6657 + uint32 sbimconfighigh; /* initiator configuration */
6658 + uint32 sbadmatch0; /* address match0 */
6659 + uint32 PAD;
6660 + uint32 sbtmconfiglow; /* target configuration */
6661 + uint32 sbtmconfighigh; /* target configuration */
6662 + uint32 sbbconfig; /* broadcast configuration */
6663 + uint32 PAD;
6664 + uint32 sbbstate; /* broadcast state */
6665 + uint32 PAD[3];
6666 + uint32 sbactcnfg; /* activate configuration */
6667 + uint32 PAD[3];
6668 + uint32 sbflagst; /* current sbflags */
6669 + uint32 PAD[3];
6670 + uint32 sbidlow; /* identification */
6671 + uint32 sbidhigh; /* identification */
6672 +} sbconfig_t;
6673 +
6674 +#endif /* _LANGUAGE_ASSEMBLY */
6675 +
6676 +/* sbipsflag */
6677 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
6678 +#define SBIPS_INT1_SHIFT 0
6679 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
6680 +#define SBIPS_INT2_SHIFT 8
6681 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
6682 +#define SBIPS_INT3_SHIFT 16
6683 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
6684 +#define SBIPS_INT4_SHIFT 24
6685 +
6686 +/* sbtpsflag */
6687 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
6688 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
6689 +
6690 +/* sbtmerrlog */
6691 +#define SBTMEL_CM 0x00000007 /* command */
6692 +#define SBTMEL_CI 0x0000ff00 /* connection id */
6693 +#define SBTMEL_EC 0x0f000000 /* error code */
6694 +#define SBTMEL_ME 0x80000000 /* multiple error */
6695 +
6696 +/* sbimstate */
6697 +#define SBIM_PC 0xf /* pipecount */
6698 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
6699 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
6700 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
6701 +#define SBIM_AP_TK 0x20 /* use token only */
6702 +#define SBIM_AP_RSV 0x30 /* reserved */
6703 +#define SBIM_IBE 0x20000 /* inbanderror */
6704 +#define SBIM_TO 0x40000 /* timeout */
6705 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
6706 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
6707 +
6708 +/* sbtmstatelow */
6709 +#define SBTML_RESET 0x1 /* reset */
6710 +#define SBTML_REJ_MASK 0x6 /* reject */
6711 +#define SBTML_REJ_SHIFT 1
6712 +#define SBTML_CLK 0x10000 /* clock enable */
6713 +#define SBTML_FGC 0x20000 /* force gated clocks on */
6714 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
6715 +#define SBTML_PE 0x40000000 /* pme enable */
6716 +#define SBTML_BE 0x80000000 /* bist enable */
6717 +
6718 +/* sbtmstatehigh */
6719 +#define SBTMH_SERR 0x1 /* serror */
6720 +#define SBTMH_INT 0x2 /* interrupt */
6721 +#define SBTMH_BUSY 0x4 /* busy */
6722 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
6723 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
6724 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
6725 +#define SBTMH_GCR 0x20000000 /* gated clock request */
6726 +#define SBTMH_BISTF 0x40000000 /* bist failed */
6727 +#define SBTMH_BISTD 0x80000000 /* bist done */
6728 +
6729 +
6730 +/* sbbwa0 */
6731 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
6732 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
6733 +#define SBBWA_TAB1_SHIFT 16
6734 +
6735 +/* sbimconfiglow */
6736 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
6737 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
6738 +#define SBIMCL_RTO_SHIFT 4
6739 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
6740 +#define SBIMCL_CID_SHIFT 16
6741 +
6742 +/* sbimconfighigh */
6743 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
6744 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
6745 +#define SBIMCH_TEM_SHIFT 4
6746 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
6747 +#define SBIMCH_BEM_SHIFT 6
6748 +
6749 +/* sbadmatch0 */
6750 +#define SBAM_TYPE_MASK 0x3 /* address type */
6751 +#define SBAM_AD64 0x4 /* reserved */
6752 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
6753 +#define SBAM_ADINT0_SHIFT 3
6754 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
6755 +#define SBAM_ADINT1_SHIFT 3
6756 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
6757 +#define SBAM_ADINT2_SHIFT 3
6758 +#define SBAM_ADEN 0x400 /* enable */
6759 +#define SBAM_ADNEG 0x800 /* negative decode */
6760 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
6761 +#define SBAM_BASE0_SHIFT 8
6762 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
6763 +#define SBAM_BASE1_SHIFT 12
6764 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
6765 +#define SBAM_BASE2_SHIFT 16
6766 +
6767 +/* sbtmconfiglow */
6768 +#define SBTMCL_CD_MASK 0xff /* clock divide */
6769 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
6770 +#define SBTMCL_CO_SHIFT 11
6771 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
6772 +#define SBTMCL_IF_SHIFT 18
6773 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
6774 +#define SBTMCL_IM_SHIFT 24
6775 +
6776 +/* sbtmconfighigh */
6777 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
6778 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
6779 +#define SBTMCH_RM_SHIFT 2
6780 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
6781 +#define SBTMCH_SM_SHIFT 4
6782 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
6783 +#define SBTMCH_EM_SHIFT 8
6784 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
6785 +#define SBTMCH_IM_SHIFT 10
6786 +
6787 +/* sbbconfig */
6788 +#define SBBC_LAT_MASK 0x3 /* sb latency */
6789 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
6790 +#define SBBC_MAX0_SHIFT 16
6791 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
6792 +#define SBBC_MAX1_SHIFT 20
6793 +
6794 +/* sbbstate */
6795 +#define SBBS_SRD 0x1 /* st reg disable */
6796 +#define SBBS_HRD 0x2 /* hold reg disable */
6797 +
6798 +/* sbidlow */
6799 +#define SBIDL_CS_MASK 0x3 /* config space */
6800 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
6801 +#define SBIDL_AR_SHIFT 3
6802 +#define SBIDL_SYNCH 0x40 /* sync */
6803 +#define SBIDL_INIT 0x80 /* initiator */
6804 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
6805 +#define SBIDL_MINLAT_SHIFT 8
6806 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
6807 +#define SBIDL_MAXLAT_SHIFT 12
6808 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
6809 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
6810 +#define SBIDL_CW_SHIFT 18
6811 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
6812 +#define SBIDL_TP_SHIFT 20
6813 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
6814 +#define SBIDL_IP_SHIFT 24
6815 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
6816 +#define SBIDL_RV_SHIFT 28
6817 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
6818 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
6819 +
6820 +/* sbidhigh */
6821 +#define SBIDH_RC_MASK 0x000f /* revision code */
6822 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
6823 +#define SBIDH_RCE_SHIFT 8
6824 +#define SBCOREREV(sbidh) \
6825 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
6826 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
6827 +#define SBIDH_CC_SHIFT 4
6828 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
6829 +#define SBIDH_VC_SHIFT 16
6830 +
6831 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
6832 +
6833 +/* vendor codes */
6834 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
6835 +
6836 +/* core codes */
6837 +#define SB_NODEV 0x700 /* Invalid coreid */
6838 +#define SB_CC 0x800 /* chipcommon core */
6839 +#define SB_ILINE20 0x801 /* iline20 core */
6840 +#define SB_SDRAM 0x803 /* sdram core */
6841 +#define SB_PCI 0x804 /* pci core */
6842 +#define SB_MIPS 0x805 /* mips core */
6843 +#define SB_ENET 0x806 /* enet mac core */
6844 +#define SB_CODEC 0x807 /* v90 codec core */
6845 +#define SB_USB 0x808 /* usb 1.1 host/device core */
6846 +#define SB_ADSL 0x809 /* ADSL core */
6847 +#define SB_ILINE100 0x80a /* iline100 core */
6848 +#define SB_IPSEC 0x80b /* ipsec core */
6849 +#define SB_PCMCIA 0x80d /* pcmcia core */
6850 +#define SB_SDIOD SB_PCMCIA /* pcmcia core has sdio device */
6851 +#define SB_SOCRAM 0x80e /* internal memory core */
6852 +#define SB_MEMC 0x80f /* memc sdram core */
6853 +#define SB_EXTIF 0x811 /* external interface core */
6854 +#define SB_D11 0x812 /* 802.11 MAC core */
6855 +#define SB_MIPS33 0x816 /* mips3302 core */
6856 +#define SB_USB11H 0x817 /* usb 1.1 host core */
6857 +#define SB_USB11D 0x818 /* usb 1.1 device core */
6858 +#define SB_USB20H 0x819 /* usb 2.0 host core */
6859 +#define SB_USB20D 0x81a /* usb 2.0 device core */
6860 +#define SB_SDIOH 0x81b /* sdio host core */
6861 +#define SB_ROBO 0x81c /* roboswitch core */
6862 +#define SB_ATA100 0x81d /* parallel ATA core */
6863 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
6864 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
6865 +#define SB_PCIE 0x820 /* pci express core */
6866 +#define SB_MIMO 0x821 /* MIMO phy core */
6867 +#define SB_SRAMC 0x822 /* SRAM controller core */
6868 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
6869 +#define SB_ARM11 0x824 /* ARM 1176 core */
6870 +#define SB_ARM7 0x825 /* ARM 7tdmi core */
6871 +
6872 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
6873 +
6874 +/* Not really related to Silicon Backplane, but a couple of software
6875 + * conventions for the use the flash space:
6876 + */
6877 +
6878 +/* Minumum amount of flash we support */
6879 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
6880 +
6881 +/* A boot/binary may have an embedded block that describes its size */
6882 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
6883 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
6884 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
6885 +#define BISZ_TXTST_IDX 1 /* 1: text start */
6886 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
6887 +#define BISZ_DATAST_IDX 3 /* 3: text start */
6888 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
6889 +#define BISZ_BSSST_IDX 5 /* 5: text start */
6890 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
6891 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
6892 +
6893 +#endif /* _SBCONFIG_H */
6894 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
6895 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
6896 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2006-10-02 21:19:59.000000000 +0200
6897 @@ -0,0 +1,243 @@
6898 +/*
6899 + * Hardware-specific External Interface I/O core definitions
6900 + * for the BCM47xx family of SiliconBackplane-based chips.
6901 + *
6902 + * The External Interface core supports a total of three external chip selects
6903 + * supporting external interfaces. One of the external chip selects is
6904 + * used for Flash, one is used for PCMCIA, and the other may be
6905 + * programmed to support either a synchronous interface or an
6906 + * asynchronous interface. The asynchronous interface can be used to
6907 + * support external devices such as UARTs and the BCM2019 Bluetooth
6908 + * baseband processor.
6909 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
6910 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
6911 + *
6912 + * Copyright 2006, Broadcom Corporation
6913 + * All Rights Reserved.
6914 + *
6915 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6916 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6917 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6918 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6919 + *
6920 + * $Id: sbextif.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
6921 + */
6922 +
6923 +#ifndef _SBEXTIF_H
6924 +#define _SBEXTIF_H
6925 +
6926 +/* external interface address space */
6927 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
6928 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
6929 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
6930 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
6931 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
6932 +
6933 +/* cpp contortions to concatenate w/arg prescan */
6934 +#ifndef PAD
6935 +#define _PADLINE(line) pad ## line
6936 +#define _XSTR(line) _PADLINE(line)
6937 +#define PAD _XSTR(__LINE__)
6938 +#endif /* PAD */
6939 +
6940 +/*
6941 + * The multiple instances of output and output enable registers
6942 + * are present to allow driver software for multiple cores to control
6943 + * gpio outputs without needing to share a single register pair.
6944 + */
6945 +struct gpiouser {
6946 + uint32 out;
6947 + uint32 outen;
6948 +};
6949 +#define NGPIOUSER 5
6950 +
6951 +typedef volatile struct {
6952 + uint32 corecontrol;
6953 + uint32 extstatus;
6954 + uint32 PAD[2];
6955 +
6956 + /* pcmcia control registers */
6957 + uint32 pcmcia_config;
6958 + uint32 pcmcia_memwait;
6959 + uint32 pcmcia_attrwait;
6960 + uint32 pcmcia_iowait;
6961 +
6962 + /* programmable interface control registers */
6963 + uint32 prog_config;
6964 + uint32 prog_waitcount;
6965 +
6966 + /* flash control registers */
6967 + uint32 flash_config;
6968 + uint32 flash_waitcount;
6969 + uint32 PAD[4];
6970 +
6971 + uint32 watchdog;
6972 +
6973 + /* clock control */
6974 + uint32 clockcontrol_n;
6975 + uint32 clockcontrol_sb;
6976 + uint32 clockcontrol_pci;
6977 + uint32 clockcontrol_mii;
6978 + uint32 PAD[3];
6979 +
6980 + /* gpio */
6981 + uint32 gpioin;
6982 + struct gpiouser gpio[NGPIOUSER];
6983 + uint32 PAD;
6984 + uint32 ejtagouten;
6985 + uint32 gpiointpolarity;
6986 + uint32 gpiointmask;
6987 + uint32 PAD[153];
6988 +
6989 + uint8 uartdata;
6990 + uint8 PAD[3];
6991 + uint8 uartimer;
6992 + uint8 PAD[3];
6993 + uint8 uartfcr;
6994 + uint8 PAD[3];
6995 + uint8 uartlcr;
6996 + uint8 PAD[3];
6997 + uint8 uartmcr;
6998 + uint8 PAD[3];
6999 + uint8 uartlsr;
7000 + uint8 PAD[3];
7001 + uint8 uartmsr;
7002 + uint8 PAD[3];
7003 + uint8 uartscratch;
7004 + uint8 PAD[3];
7005 +} extifregs_t;
7006 +
7007 +/* corecontrol */
7008 +#define CC_UE (1 << 0) /* uart enable */
7009 +
7010 +/* extstatus */
7011 +#define ES_EM (1 << 0) /* endian mode (ro) */
7012 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
7013 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
7014 +
7015 +/* gpio bit mask */
7016 +#define GPIO_BIT0 (1 << 0)
7017 +#define GPIO_BIT1 (1 << 1)
7018 +#define GPIO_BIT2 (1 << 2)
7019 +#define GPIO_BIT3 (1 << 3)
7020 +#define GPIO_BIT4 (1 << 4)
7021 +#define GPIO_BIT5 (1 << 5)
7022 +#define GPIO_BIT6 (1 << 6)
7023 +#define GPIO_BIT7 (1 << 7)
7024 +
7025 +
7026 +/* pcmcia/prog/flash_config */
7027 +#define CF_EN (1 << 0) /* enable */
7028 +#define CF_EM_MASK 0xe /* mode */
7029 +#define CF_EM_SHIFT 1
7030 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
7031 +#define CF_EM_SYNC 0x2 /* synchronous mode */
7032 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
7033 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
7034 +#define CF_BS (1 << 5) /* byteswap */
7035 +#define CF_CD_MASK 0xc0 /* clock divider */
7036 +#define CF_CD_SHIFT 6
7037 +#define CF_CD_DIV2 0x0 /* backplane/2 */
7038 +#define CF_CD_DIV3 0x40 /* backplane/3 */
7039 +#define CF_CD_DIV4 0x80 /* backplane/4 */
7040 +#define CF_CE (1 << 8) /* clock enable */
7041 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
7042 +
7043 +/* pcmcia_memwait */
7044 +#define PM_W0_MASK 0x3f /* waitcount0 */
7045 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
7046 +#define PM_W1_SHIFT 8
7047 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
7048 +#define PM_W2_SHIFT 16
7049 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
7050 +#define PM_W3_SHIFT 24
7051 +
7052 +/* pcmcia_attrwait */
7053 +#define PA_W0_MASK 0x3f /* waitcount0 */
7054 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
7055 +#define PA_W1_SHIFT 8
7056 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
7057 +#define PA_W2_SHIFT 16
7058 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
7059 +#define PA_W3_SHIFT 24
7060 +
7061 +/* pcmcia_iowait */
7062 +#define PI_W0_MASK 0x3f /* waitcount0 */
7063 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
7064 +#define PI_W1_SHIFT 8
7065 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
7066 +#define PI_W2_SHIFT 16
7067 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
7068 +#define PI_W3_SHIFT 24
7069 +
7070 +/* prog_waitcount */
7071 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
7072 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
7073 +#define PW_W1_SHIFT 8
7074 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
7075 +#define PW_W2_SHIFT 16
7076 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
7077 +#define PW_W3_SHIFT 24
7078 +
7079 +#define PW_W0 0x0000000c
7080 +#define PW_W1 0x00000a00
7081 +#define PW_W2 0x00020000
7082 +#define PW_W3 0x01000000
7083 +
7084 +/* flash_waitcount */
7085 +#define FW_W0_MASK 0x1f /* waitcount0 */
7086 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
7087 +#define FW_W1_SHIFT 8
7088 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
7089 +#define FW_W2_SHIFT 16
7090 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
7091 +#define FW_W3_SHIFT 24
7092 +
7093 +/* watchdog */
7094 +#define WATCHDOG_CLOCK 48000000 /* Hz */
7095 +
7096 +/* clockcontrol_n */
7097 +#define CN_N1_MASK 0x3f /* n1 control */
7098 +#define CN_N2_MASK 0x3f00 /* n2 control */
7099 +#define CN_N2_SHIFT 8
7100 +
7101 +/* clockcontrol_sb/pci/mii */
7102 +#define CC_M1_MASK 0x3f /* m1 control */
7103 +#define CC_M2_MASK 0x3f00 /* m2 control */
7104 +#define CC_M2_SHIFT 8
7105 +#define CC_M3_MASK 0x3f0000 /* m3 control */
7106 +#define CC_M3_SHIFT 16
7107 +#define CC_MC_MASK 0x1f000000 /* mux control */
7108 +#define CC_MC_SHIFT 24
7109 +
7110 +/* Clock control default values */
7111 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
7112 +#define CC_DEF_100 0x04020011
7113 +#define CC_DEF_33 0x11030011
7114 +#define CC_DEF_25 0x11050011
7115 +
7116 +/* Clock control values for 125Mhz */
7117 +#define CC_125_N 0x0802
7118 +#define CC_125_M 0x04020009
7119 +#define CC_125_M25 0x11090009
7120 +#define CC_125_M33 0x11090005
7121 +
7122 +/* Clock control magic field values */
7123 +#define CC_F6_2 0x02 /* A factor of 2 in */
7124 +#define CC_F6_3 0x03 /* 6-bit fields like */
7125 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
7126 +#define CC_F6_5 0x09
7127 +#define CC_F6_6 0x11
7128 +#define CC_F6_7 0x21
7129 +
7130 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
7131 +
7132 +#define CC_MC_BYPASS 0x08
7133 +#define CC_MC_M1 0x04
7134 +#define CC_MC_M1M2 0x02
7135 +#define CC_MC_M1M2M3 0x01
7136 +#define CC_MC_M1M3 0x11
7137 +
7138 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
7139 +
7140 +#endif /* _SBEXTIF_H */
7141 diff -urN linux.old/arch/mips/bcm947xx/include/sbhndmips.h linux.dev/arch/mips/bcm947xx/include/sbhndmips.h
7142 --- linux.old/arch/mips/bcm947xx/include/sbhndmips.h 1970-01-01 01:00:00.000000000 +0100
7143 +++ linux.dev/arch/mips/bcm947xx/include/sbhndmips.h 2006-10-02 21:19:59.000000000 +0200
7144 @@ -0,0 +1,47 @@
7145 +/*
7146 + * Broadcom SiliconBackplane MIPS definitions
7147 + *
7148 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
7149 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
7150 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
7151 + * interface. The core revision is stored in the SB ID register in SB
7152 + * configuration space.
7153 + *
7154 + * Copyright 2006, Broadcom Corporation
7155 + * All Rights Reserved.
7156 + *
7157 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7158 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7159 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7160 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7161 + *
7162 + * $Id: sbhndmips.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
7163 + */
7164 +
7165 +#ifndef _sbhndmips_h_
7166 +#define _sbhndmips_h_
7167 +
7168 +#include <mipsinc.h>
7169 +
7170 +#ifndef _LANGUAGE_ASSEMBLY
7171 +
7172 +/* cpp contortions to concatenate w/arg prescan */
7173 +#ifndef PAD
7174 +#define _PADLINE(line) pad ## line
7175 +#define _XSTR(line) _PADLINE(line)
7176 +#define PAD _XSTR(__LINE__)
7177 +#endif /* PAD */
7178 +
7179 +typedef volatile struct {
7180 + uint32 corecontrol;
7181 + uint32 PAD[2];
7182 + uint32 biststatus;
7183 + uint32 PAD[4];
7184 + uint32 intstatus;
7185 + uint32 intmask;
7186 + uint32 timer;
7187 +} mipsregs_t;
7188 +
7189 +#endif /* _LANGUAGE_ASSEMBLY */
7190 +
7191 +#endif /* _sbhndmips_h_ */
7192 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
7193 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
7194 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2006-10-02 21:19:59.000000000 +0200
7195 @@ -0,0 +1,147 @@
7196 +/*
7197 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
7198 + *
7199 + * Copyright 2006, Broadcom Corporation
7200 + * All Rights Reserved.
7201 + *
7202 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7203 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7204 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7205 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7206 + *
7207 + * $Id: sbmemc.h,v 1.6 2006/03/02 12:33:44 honor Exp $
7208 + */
7209 +
7210 +#ifndef _SBMEMC_H
7211 +#define _SBMEMC_H
7212 +
7213 +#ifdef _LANGUAGE_ASSEMBLY
7214 +
7215 +#define MEMC_CONTROL 0x00
7216 +#define MEMC_CONFIG 0x04
7217 +#define MEMC_REFRESH 0x08
7218 +#define MEMC_BISTSTAT 0x0c
7219 +#define MEMC_MODEBUF 0x10
7220 +#define MEMC_BKCLS 0x14
7221 +#define MEMC_PRIORINV 0x18
7222 +#define MEMC_DRAMTIM 0x1c
7223 +#define MEMC_INTSTAT 0x20
7224 +#define MEMC_INTMASK 0x24
7225 +#define MEMC_INTINFO 0x28
7226 +#define MEMC_NCDLCTL 0x30
7227 +#define MEMC_RDNCDLCOR 0x34
7228 +#define MEMC_WRNCDLCOR 0x38
7229 +#define MEMC_MISCDLYCTL 0x3c
7230 +#define MEMC_DQSGATENCDL 0x40
7231 +#define MEMC_SPARE 0x44
7232 +#define MEMC_TPADDR 0x48
7233 +#define MEMC_TPDATA 0x4c
7234 +#define MEMC_BARRIER 0x50
7235 +#define MEMC_CORE 0x54
7236 +
7237 +#else /* !_LANGUAGE_ASSEMBLY */
7238 +
7239 +/* Sonics side: MEMC core registers */
7240 +typedef volatile struct sbmemcregs {
7241 + uint32 control;
7242 + uint32 config;
7243 + uint32 refresh;
7244 + uint32 biststat;
7245 + uint32 modebuf;
7246 + uint32 bkcls;
7247 + uint32 priorinv;
7248 + uint32 dramtim;
7249 + uint32 intstat;
7250 + uint32 intmask;
7251 + uint32 intinfo;
7252 + uint32 reserved1;
7253 + uint32 ncdlctl;
7254 + uint32 rdncdlcor;
7255 + uint32 wrncdlcor;
7256 + uint32 miscdlyctl;
7257 + uint32 dqsgatencdl;
7258 + uint32 spare;
7259 + uint32 tpaddr;
7260 + uint32 tpdata;
7261 + uint32 barrier;
7262 + uint32 core;
7263 +} sbmemcregs_t;
7264 +
7265 +#endif /* _LANGUAGE_ASSEMBLY */
7266 +
7267 +/* MEMC Core Init values (OCP ID 0x80f) */
7268 +
7269 +/* For sdr: */
7270 +#define MEMC_SD_CONFIG_INIT 0x00048000
7271 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
7272 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
7273 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
7274 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
7275 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
7276 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
7277 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
7278 +#define MEMC_SD_CONTROL_INIT0 0x00000002
7279 +#define MEMC_SD_CONTROL_INIT1 0x00000008
7280 +#define MEMC_SD_CONTROL_INIT2 0x00000004
7281 +#define MEMC_SD_CONTROL_INIT3 0x00000010
7282 +#define MEMC_SD_CONTROL_INIT4 0x00000001
7283 +#define MEMC_SD_MODEBUF_INIT 0x00000000
7284 +#define MEMC_SD_REFRESH_INIT 0x0000840f
7285 +
7286 +
7287 +/* This is for SDRM8X8X4 */
7288 +#define MEMC_SDR_INIT 0x0008
7289 +#define MEMC_SDR_MODE 0x32
7290 +#define MEMC_SDR_NCDL 0x00020032
7291 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
7292 +
7293 +/* For ddr: */
7294 +#define MEMC_CONFIG_INIT 0x00048000
7295 +#define MEMC_DRAMTIM2_INIT 0x000754d8
7296 +#define MEMC_DRAMTIM25_INIT 0x000754d9
7297 +#define MEMC_RDNCDLCOR_INIT 0x00000000
7298 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
7299 +#define MEMC_WRNCDLCOR_INIT 0x49351200
7300 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
7301 +#define MEMC_DQSGATENCDL_INIT 0x00030000
7302 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
7303 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
7304 +#define MEMC_NCDLCTL_INIT 0x00002001
7305 +#define MEMC_CONTROL_INIT0 0x00000002
7306 +#define MEMC_CONTROL_INIT1 0x00000008
7307 +#define MEMC_MODEBUF_INIT0 0x00004000
7308 +#define MEMC_CONTROL_INIT2 0x00000010
7309 +#define MEMC_MODEBUF_INIT1 0x00000100
7310 +#define MEMC_CONTROL_INIT3 0x00000010
7311 +#define MEMC_CONTROL_INIT4 0x00000008
7312 +#define MEMC_REFRESH_INIT 0x0000840f
7313 +#define MEMC_CONTROL_INIT5 0x00000004
7314 +#define MEMC_MODEBUF_INIT2 0x00000000
7315 +#define MEMC_CONTROL_INIT6 0x00000010
7316 +#define MEMC_CONTROL_INIT7 0x00000001
7317 +
7318 +
7319 +/* This is for DDRM16X16X2 */
7320 +#define MEMC_DDR_INIT 0x0009
7321 +#define MEMC_DDR_MODE 0x62
7322 +#define MEMC_DDR_NCDL 0x0005050a
7323 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
7324 +
7325 +/* mask for sdr/ddr calibration registers */
7326 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
7327 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
7328 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
7329 +
7330 +/* masks for miscdlyctl registers */
7331 +#define MEMC_MISC_SM_MASK 0x30000000
7332 +#define MEMC_MISC_SM_SHIFT 28
7333 +#define MEMC_MISC_SD_MASK 0x0f000000
7334 +#define MEMC_MISC_SD_SHIFT 24
7335 +
7336 +/* hw threshhold for calculating wr/rd for sdr memc */
7337 +#define MEMC_CD_THRESHOLD 128
7338 +
7339 +/* Low bit of init register says if memc is ddr or sdr */
7340 +#define MEMC_CONFIG_DDR 0x00000001
7341 +
7342 +#endif /* _SBMEMC_H */
7343 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcie.h linux.dev/arch/mips/bcm947xx/include/sbpcie.h
7344 --- linux.old/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
7345 +++ linux.dev/arch/mips/bcm947xx/include/sbpcie.h 2006-10-02 21:19:59.000000000 +0200
7346 @@ -0,0 +1,200 @@
7347 +/*
7348 + * BCM43XX SiliconBackplane PCIE core hardware definitions.
7349 + *
7350 + * Copyright 2006, Broadcom Corporation
7351 + * All Rights Reserved.
7352 + *
7353 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7354 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7355 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7356 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7357 + *
7358 + * $Id: sbpcie.h,v 1.1.1.2 2006/02/27 03:43:16 honor Exp $
7359 + */
7360 +
7361 +#ifndef _SBPCIE_H
7362 +#define _SBPCIE_H
7363 +
7364 +/* cpp contortions to concatenate w/arg prescan */
7365 +#ifndef PAD
7366 +#define _PADLINE(line) pad ## line
7367 +#define _XSTR(line) _PADLINE(line)
7368 +#define PAD _XSTR(__LINE__)
7369 +#endif
7370 +
7371 +/* PCIE Enumeration space offsets */
7372 +#define PCIE_CORE_CONFIG_OFFSET 0x0
7373 +#define PCIE_FUNC0_CONFIG_OFFSET 0x400
7374 +#define PCIE_FUNC1_CONFIG_OFFSET 0x500
7375 +#define PCIE_FUNC2_CONFIG_OFFSET 0x600
7376 +#define PCIE_FUNC3_CONFIG_OFFSET 0x700
7377 +#define PCIE_SPROM_SHADOW_OFFSET 0x800
7378 +#define PCIE_SBCONFIG_OFFSET 0xE00
7379 +
7380 +/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
7381 +#define PCIE_DEV_BAR0_SIZE 0x4000
7382 +#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
7383 +#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
7384 +#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
7385 +#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
7386 +
7387 +/* SB side: PCIE core and host control registers */
7388 +typedef struct sbpcieregs {
7389 + uint32 PAD[3];
7390 + uint32 biststatus; /* bist Status: 0x00C */
7391 + uint32 PAD[6];
7392 + uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
7393 + uint32 PAD[54];
7394 + uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
7395 + uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
7396 + uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
7397 + uint32 PAD[4];
7398 +
7399 + /* pcie core supports in direct access to config space */
7400 + uint32 configaddr; /* pcie config space access: Address field: 0x120 */
7401 + uint32 configdata; /* pcie config space access: Data field: 0x124 */
7402 +
7403 + /* mdio access to serdes */
7404 + uint32 mdiocontrol; /* controls the mdio access: 0x128 */
7405 + uint32 mdiodata; /* Data to the mdio access: 0x12c */
7406 +
7407 + /* pcie protocol phy/dllp/tlp register access mechanism */
7408 + uint32 pcieaddr; /* address of the internal registeru: 0x130 */
7409 + uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
7410 +
7411 + uint32 PAD[434];
7412 + uint16 sprom[36]; /* SPROM shadow Area */
7413 +} sbpcieregs_t;
7414 +
7415 +/* SB to PCIE translation masks */
7416 +#define SBTOPCIE0_MASK 0xfc000000
7417 +#define SBTOPCIE1_MASK 0xfc000000
7418 +#define SBTOPCIE2_MASK 0xc0000000
7419 +
7420 +/* Access type bits (0:1) */
7421 +#define SBTOPCIE_MEM 0
7422 +#define SBTOPCIE_IO 1
7423 +#define SBTOPCIE_CFG0 2
7424 +#define SBTOPCIE_CFG1 3
7425 +
7426 +/* Prefetch enable bit 2 */
7427 +#define SBTOPCIE_PF 4
7428 +
7429 +/* Write Burst enable for memory write bit 3 */
7430 +#define SBTOPCIE_WR_BURST 8
7431 +
7432 +/* config access */
7433 +#define CONFIGADDR_FUNC_MASK 0x7000
7434 +#define CONFIGADDR_FUNC_SHF 12
7435 +#define CONFIGADDR_REG_MASK 0x0FFF
7436 +#define CONFIGADDR_REG_SHF 0
7437 +
7438 +/* PCIE protocol regs Indirect Address */
7439 +#define PCIEADDR_PROT_MASK 0x300
7440 +#define PCIEADDR_PROT_SHF 8
7441 +#define PCIEADDR_PL_TLP 0
7442 +#define PCIEADDR_PL_DLLP 1
7443 +#define PCIEADDR_PL_PLP 2
7444 +
7445 +/* PCIE protocol PHY diagnostic registers */
7446 +#define PCIE_PLP_MODEREG 0x200 /* Mode */
7447 +#define PCIE_PLP_STATUSREG 0x204 /* Status */
7448 +#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
7449 +#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
7450 +#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
7451 +#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
7452 +#define PCIE_PLP_ATTNREG 0x218 /* Attention */
7453 +#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
7454 +#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
7455 +#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
7456 +#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
7457 +#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */
7458 +#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
7459 +#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
7460 +#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
7461 +#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
7462 +
7463 +/* PCIE protocol DLLP diagnostic registers */
7464 +#define PCIE_DLLP_LCREG 0x100 /* Link Control */
7465 +#define PCIE_DLLP_LSREG 0x104 /* Link Status */
7466 +#define PCIE_DLLP_LAREG 0x108 /* Link Attention */
7467 +#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
7468 +#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
7469 +#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
7470 +#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
7471 +#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
7472 +#define PCIE_DLLP_LRREG 0x120 /* Link Replay */
7473 +#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
7474 +#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
7475 +#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
7476 +#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
7477 +#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
7478 +#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
7479 +#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
7480 +#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
7481 +#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */
7482 +#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
7483 +#define PCIE_DLLP_TESTREG 0x14C /* Test */
7484 +#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
7485 +
7486 +/* PCIE protocol TLP diagnostic registers */
7487 +#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
7488 +#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
7489 +#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */
7490 +#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */
7491 +#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */
7492 +#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */
7493 +#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */
7494 +#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */
7495 +#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */
7496 +#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */
7497 +#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */
7498 +#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */
7499 +#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */
7500 +#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */
7501 +#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */
7502 +#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */
7503 +#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */
7504 +#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */
7505 +#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
7506 +#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
7507 +#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
7508 +#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */
7509 +#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */
7510 +#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */
7511 +#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */
7512 +#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */
7513 +#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */
7514 +#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */
7515 +#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */
7516 +#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */
7517 +#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */
7518 +
7519 +/* MDIO control */
7520 +#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
7521 +#define MDIOCTL_DIVISOR_VAL 0x2
7522 +#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
7523 +#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
7524 +
7525 +/* MDIO Data */
7526 +#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
7527 +#define MDIODATA_TA 0x00020000 /* Turnaround */
7528 +#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
7529 +#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
7530 +#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
7531 +#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
7532 +#define MDIODATA_WRITE 0x10000000 /* write Transaction */
7533 +#define MDIODATA_READ 0x20000000 /* Read Transaction */
7534 +#define MDIODATA_START 0x40000000 /* start of Transaction */
7535 +
7536 +/* MDIO devices (SERDES modules) */
7537 +#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
7538 +#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
7539 +#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
7540 +
7541 +/* SERDES registers */
7542 +#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
7543 +#define SERDES_RX_CDR 6 /* CDR */
7544 +#define SERDES_RX_CDRBW 7 /* CDR BW */
7545 +
7546 +#endif /* _SBPCIE_H */
7547 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
7548 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
7549 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2006-10-02 21:19:59.000000000 +0200
7550 @@ -0,0 +1,114 @@
7551 +/*
7552 + * HND SiliconBackplane PCI core hardware definitions.
7553 + *
7554 + * Copyright 2006, Broadcom Corporation
7555 + * All Rights Reserved.
7556 + *
7557 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7558 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7559 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7560 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7561 + *
7562 + * $Id: sbpci.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
7563 + */
7564 +
7565 +#ifndef _sbpci_h_
7566 +#define _sbpci_h_
7567 +
7568 +#ifndef _LANGUAGE_ASSEMBLY
7569 +
7570 +/* cpp contortions to concatenate w/arg prescan */
7571 +#ifndef PAD
7572 +#define _PADLINE(line) pad ## line
7573 +#define _XSTR(line) _PADLINE(line)
7574 +#define PAD _XSTR(__LINE__)
7575 +#endif
7576 +
7577 +/* Sonics side: PCI core and host control registers */
7578 +typedef struct sbpciregs {
7579 + uint32 control; /* PCI control */
7580 + uint32 PAD[3];
7581 + uint32 arbcontrol; /* PCI arbiter control */
7582 + uint32 PAD[3];
7583 + uint32 intstatus; /* Interrupt status */
7584 + uint32 intmask; /* Interrupt mask */
7585 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
7586 + uint32 PAD[9];
7587 + uint32 bcastaddr; /* Sonics broadcast address */
7588 + uint32 bcastdata; /* Sonics broadcast data */
7589 + uint32 PAD[2];
7590 + uint32 gpioin; /* ro: gpio input (>=rev2) */
7591 + uint32 gpioout; /* rw: gpio output (>=rev2) */
7592 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
7593 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
7594 + uint32 PAD[36];
7595 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
7596 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
7597 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
7598 + uint32 PAD[189];
7599 + uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
7600 + uint16 sprom[36]; /* SPROM shadow Area */
7601 + uint32 PAD[46];
7602 +} sbpciregs_t;
7603 +
7604 +#endif /* _LANGUAGE_ASSEMBLY */
7605 +
7606 +/* PCI control */
7607 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
7608 +#define PCI_RST 0x02 /* Value driven out to pin */
7609 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
7610 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
7611 +
7612 +/* PCI arbiter control */
7613 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
7614 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
7615 +/* ParkID - for PCI corerev >= 8 */
7616 +#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */
7617 +#define PCI_PARKID_SHIFT 2
7618 +#define PCI_PARKID_EXT0 0 /* External master 0 */
7619 +#define PCI_PARKID_EXT1 1 /* External master 1 */
7620 +#define PCI_PARKID_EXT2 2 /* External master 2 */
7621 +#define PCI_PARKID_INT 3 /* Internal master */
7622 +#define PCI_PARKID_LAST 4 /* Last active master */
7623 +
7624 +/* Interrupt status/mask */
7625 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
7626 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
7627 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
7628 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
7629 +#define PCI_PME 0x10 /* PCI PME# is asserted */
7630 +
7631 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
7632 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
7633 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
7634 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
7635 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
7636 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
7637 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
7638 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
7639 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
7640 +
7641 +/* Sonics broadcast address */
7642 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
7643 +
7644 +/* Sonics to PCI translation types */
7645 +#define SBTOPCI0_MASK 0xfc000000
7646 +#define SBTOPCI1_MASK 0xfc000000
7647 +#define SBTOPCI2_MASK 0xc0000000
7648 +#define SBTOPCI_MEM 0
7649 +#define SBTOPCI_IO 1
7650 +#define SBTOPCI_CFG0 2
7651 +#define SBTOPCI_CFG1 3
7652 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
7653 +#define SBTOPCI_BURST 0x8 /* burst enable */
7654 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
7655 +#define SBTOPCI_RC_READ 0x00 /* memory read */
7656 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
7657 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
7658 +
7659 +/* PCI core index in SROM shadow area */
7660 +#define SRSH_PI_OFFSET 0 /* first word */
7661 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
7662 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
7663 +
7664 +#endif /* _sbpci_h_ */
7665 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcmcia.h linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h
7666 --- linux.old/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
7667 +++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2006-10-02 21:19:59.000000000 +0200
7668 @@ -0,0 +1,147 @@
7669 +/*
7670 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
7671 + *
7672 + * Copyright 2006, Broadcom Corporation
7673 + * All Rights Reserved.
7674 + *
7675 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7676 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7677 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7678 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7679 + *
7680 + * $Id: sbpcmcia.h,v 1.1.1.9 2006/02/27 03:43:16 honor Exp $
7681 + */
7682 +
7683 +#ifndef _SBPCMCIA_H
7684 +#define _SBPCMCIA_H
7685 +
7686 +
7687 +/* All the addresses that are offsets in attribute space are divided
7688 + * by two to account for the fact that odd bytes are invalid in
7689 + * attribute space and our read/write routines make the space appear
7690 + * as if they didn't exist. Still we want to show the original numbers
7691 + * as documented in the hnd_pcmcia core manual.
7692 + */
7693 +
7694 +/* PCMCIA Function Configuration Registers */
7695 +#define PCMCIA_FCR (0x700 / 2)
7696 +
7697 +#define FCR0_OFF 0
7698 +#define FCR1_OFF (0x40 / 2)
7699 +#define FCR2_OFF (0x80 / 2)
7700 +#define FCR3_OFF (0xc0 / 2)
7701 +
7702 +#define PCMCIA_FCR0 (0x700 / 2)
7703 +#define PCMCIA_FCR1 (0x740 / 2)
7704 +#define PCMCIA_FCR2 (0x780 / 2)
7705 +#define PCMCIA_FCR3 (0x7c0 / 2)
7706 +
7707 +/* Standard PCMCIA FCR registers */
7708 +
7709 +#define PCMCIA_COR 0
7710 +
7711 +#define COR_RST 0x80
7712 +#define COR_LEV 0x40
7713 +#define COR_IRQEN 0x04
7714 +#define COR_BLREN 0x01
7715 +#define COR_FUNEN 0x01
7716 +
7717 +
7718 +#define PCICIA_FCSR (2 / 2)
7719 +#define PCICIA_PRR (4 / 2)
7720 +#define PCICIA_SCR (6 / 2)
7721 +#define PCICIA_ESR (8 / 2)
7722 +
7723 +
7724 +#define PCM_MEMOFF 0x0000
7725 +#define F0_MEMOFF 0x1000
7726 +#define F1_MEMOFF 0x2000
7727 +#define F2_MEMOFF 0x3000
7728 +#define F3_MEMOFF 0x4000
7729 +
7730 +/* Memory base in the function fcr's */
7731 +#define MEM_ADDR0 (0x728 / 2)
7732 +#define MEM_ADDR1 (0x72a / 2)
7733 +#define MEM_ADDR2 (0x72c / 2)
7734 +
7735 +/* PCMCIA base plus Srom access in fcr0: */
7736 +#define PCMCIA_ADDR0 (0x072e / 2)
7737 +#define PCMCIA_ADDR1 (0x0730 / 2)
7738 +#define PCMCIA_ADDR2 (0x0732 / 2)
7739 +
7740 +#define MEM_SEG (0x0734 / 2)
7741 +#define SROM_CS (0x0736 / 2)
7742 +#define SROM_DATAL (0x0738 / 2)
7743 +#define SROM_DATAH (0x073a / 2)
7744 +#define SROM_ADDRL (0x073c / 2)
7745 +#define SROM_ADDRH (0x073e / 2)
7746 +
7747 +/* Values for srom_cs: */
7748 +#define SROM_IDLE 0
7749 +#define SROM_WRITE 1
7750 +#define SROM_READ 2
7751 +#define SROM_WEN 4
7752 +#define SROM_WDS 7
7753 +#define SROM_DONE 8
7754 +
7755 +/* CIS stuff */
7756 +
7757 +/* The CIS stops where the FCRs start */
7758 +#define CIS_SIZE PCMCIA_FCR
7759 +
7760 +/* Standard tuples we know about */
7761 +
7762 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
7763 +#define CISTPL_FUNCE 0x22 /* Function extensions */
7764 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
7765 +
7766 +/* Function extensions for LANs */
7767 +
7768 +#define LAN_TECH 1 /* Technology type */
7769 +#define LAN_SPEED 2 /* Raw bit rate */
7770 +#define LAN_MEDIA 3 /* Transmission media */
7771 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
7772 +#define LAN_CONN 5 /* Connector standard */
7773 +
7774 +
7775 +/* CFTable */
7776 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
7777 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
7778 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
7779 +
7780 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
7781 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
7782 + */
7783 +
7784 +#define CISTPL_BRCM_HNBU 0x80
7785 +
7786 +/* Subtypes of BRCM_HNBU: */
7787 +
7788 +#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
7789 +#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */
7790 +#define HNBU_BOARDREV 0x02 /* One byte board revision */
7791 +#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1)
7792 + * or 9 (sromrev > 1) bytes
7793 + */
7794 +#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
7795 +#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
7796 +#define HNBU_AA 0x06 /* Antennas available */
7797 +#define HNBU_AG 0x07 /* Antenna gain */
7798 +#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
7799 +#define HNBU_LEDS 0x09 /* LED set */
7800 +#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
7801 + * in rev 2
7802 + */
7803 +#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
7804 +#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
7805 +#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
7806 +
7807 +
7808 +/* sbtmstatelow */
7809 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
7810 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
7811 +
7812 +/* sbtmstatehigh */
7813 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
7814 +
7815 +#endif /* _SBPCMCIA_H */
7816 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
7817 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
7818 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2006-10-02 21:19:59.000000000 +0200
7819 @@ -0,0 +1,85 @@
7820 +/*
7821 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
7822 + *
7823 + * Copyright 2006, Broadcom Corporation
7824 + * All Rights Reserved.
7825 + *
7826 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7827 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7828 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7829 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7830 + *
7831 + * $Id: sbsdram.h,v 1.1.1.9 2006/03/02 13:03:52 honor Exp $
7832 + */
7833 +
7834 +#ifndef _SBSDRAM_H
7835 +#define _SBSDRAM_H
7836 +
7837 +#ifndef _LANGUAGE_ASSEMBLY
7838 +
7839 +/* Sonics side: SDRAM core registers */
7840 +typedef volatile struct sbsdramregs {
7841 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
7842 + uint32 config; /* Initializes external SDRAM mode register */
7843 + uint32 refresh; /* Controls external SDRAM refresh rate */
7844 + uint32 pad1;
7845 + uint32 pad2;
7846 +} sbsdramregs_t;
7847 +
7848 +/* SDRAM simulation */
7849 +#ifdef RAMSZ
7850 +#define SDRAMSZ RAMSZ
7851 +#else
7852 +#define SDRAMSZ (4 * 1024 * 1024)
7853 +#endif
7854 +
7855 +extern uchar sdrambuf[SDRAMSZ];
7856 +
7857 +#endif /* _LANGUAGE_ASSEMBLY */
7858 +
7859 +/* SDRAM initialization control (initcontrol) register bits */
7860 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
7861 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
7862 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
7863 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
7864 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
7865 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
7866 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
7867 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
7868 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
7869 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
7870 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
7871 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
7872 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
7873 +
7874 +/* SDRAM configuration (config) register bits */
7875 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
7876 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
7877 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
7878 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
7879 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
7880 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
7881 +
7882 +/* SDRAM refresh control (refresh) register bits */
7883 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
7884 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
7885 +
7886 +/* SDRAM Core default Init values (OCP ID 0x803) */
7887 +#define SDRAM_INIT MEM4MX16X2
7888 +#define SDRAM_CONFIG SDRAM_BURSTFULL
7889 +#define SDRAM_REFRESH SDRAM_REF(0x40)
7890 +
7891 +#define MEM1MX16 0x009 /* 2 MB */
7892 +#define MEM1MX16X2 0x409 /* 4 MB */
7893 +#define MEM2MX8X2 0x809 /* 4 MB */
7894 +#define MEM2MX8X4 0xc09 /* 8 MB */
7895 +#define MEM2MX32 0x439 /* 8 MB */
7896 +#define MEM4MX16 0x019 /* 8 MB */
7897 +#define MEM4MX16X2 0x419 /* 16 MB */
7898 +#define MEM8MX8X2 0x819 /* 16 MB */
7899 +#define MEM8MX16 0x829 /* 16 MB */
7900 +#define MEM4MX32 0x429 /* 16 MB */
7901 +#define MEM8MX8X4 0xc19 /* 32 MB */
7902 +#define MEM8MX16X2 0xc29 /* 32 MB */
7903 +
7904 +#endif /* _SBSDRAM_H */
7905 diff -urN linux.old/arch/mips/bcm947xx/include/sbsocram.h linux.dev/arch/mips/bcm947xx/include/sbsocram.h
7906 --- linux.old/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
7907 +++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2006-10-02 21:19:59.000000000 +0200
7908 @@ -0,0 +1,64 @@
7909 +/*
7910 + * BCM47XX Sonics SiliconBackplane embedded ram core
7911 + *
7912 + * Copyright 2006, Broadcom Corporation
7913 + * All Rights Reserved.
7914 + *
7915 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7916 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7917 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7918 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7919 + *
7920 + * $Id: sbsocram.h,v 1.1.1.3 2006/02/27 03:43:16 honor Exp $
7921 + */
7922 +
7923 +#ifndef _SBSOCRAM_H
7924 +#define _SBSOCRAM_H
7925 +
7926 +#define SR_COREINFO 0x00
7927 +#define SR_BWALLOC 0x04
7928 +#define SR_BISTSTAT 0x0c
7929 +#define SR_BANKINDEX 0x10
7930 +#define SR_BANKSTBYCTL 0x14
7931 +
7932 +
7933 +#ifndef _LANGUAGE_ASSEMBLY
7934 +
7935 +/* Memcsocram core registers */
7936 +typedef volatile struct sbsocramregs {
7937 + uint32 coreinfo;
7938 + uint32 bwalloc;
7939 + uint32 PAD;
7940 + uint32 biststat;
7941 + uint32 bankidx;
7942 + uint32 standbyctrl;
7943 +} sbsocramregs_t;
7944 +
7945 +#endif
7946 +
7947 +/* Coreinfo register */
7948 +#define SRCI_PT_MASK 0x30000
7949 +#define SRCI_PT_SHIFT 16
7950 +
7951 +/* In corerev 0, the memory size is 2 to the power of the
7952 + * base plus 16 plus to the contents of the memsize field plus 1.
7953 + */
7954 +#define SRCI_MS0_MASK 0xf
7955 +#define SR_MS0_BASE 16
7956 +
7957 +/*
7958 + * In corerev 1 the bank size is 2 ^ the bank size field plus 14,
7959 + * the memory size is number of banks times bank size.
7960 + * The same applies to rom size.
7961 + */
7962 +#define SRCI_ROMNB_MASK 0xf000
7963 +#define SRCI_ROMNB_SHIFT 12
7964 +#define SRCI_ROMBSZ_MASK 0xf00
7965 +#define SRCI_ROMBSZ_SHIFT 8
7966 +#define SRCI_SRNB_MASK 0xf0
7967 +#define SRCI_SRNB_SHIFT 4
7968 +#define SRCI_SRBSZ_MASK 0xf
7969 +#define SRCI_SRBSZ_SHIFT 0
7970 +
7971 +#define SR_BSZ_BASE 14
7972 +#endif /* _SBSOCRAM_H */
7973 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
7974 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
7975 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2006-10-02 21:19:59.000000000 +0200
7976 @@ -0,0 +1,151 @@
7977 +/*
7978 + * Misc utility routines for accessing chip-specific features
7979 + * of Broadcom HNBU SiliconBackplane-based chips.
7980 + *
7981 + * Copyright 2006, Broadcom Corporation
7982 + * All Rights Reserved.
7983 + *
7984 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7985 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7986 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7987 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7988 + *
7989 + * $Id: sbutils.h,v 1.4 2006/04/08 07:12:42 honor Exp $
7990 + */
7991 +
7992 +#ifndef _sbutils_h_
7993 +#define _sbutils_h_
7994 +
7995 +/*
7996 + * Datastructure to export all chip specific common variables
7997 + * public (read-only) portion of sbutils handle returned by
7998 + * sb_attach()/sb_kattach()
7999 +*/
8000 +
8001 +struct sb_pub {
8002 +
8003 + uint bustype; /* SB_BUS, PCI_BUS */
8004 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE */
8005 + uint buscorerev; /* buscore rev */
8006 + uint buscoreidx; /* buscore index */
8007 + int ccrev; /* chip common core rev */
8008 + uint boardtype; /* board type */
8009 + uint boardvendor; /* board vendor */
8010 + uint chip; /* chip number */
8011 + uint chiprev; /* chip revision */
8012 + uint chippkg; /* chip package option */
8013 + uint sonicsrev; /* sonics backplane rev */
8014 +};
8015 +
8016 +typedef const struct sb_pub sb_t;
8017 +
8018 +/*
8019 + * Many of the routines below take an 'sbh' handle as their first arg.
8020 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
8021 + * At any one time, the sbh is logically focused on one particular sb core
8022 + * (the "current core").
8023 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
8024 + */
8025 +
8026 +#define SB_OSH NULL /* Use for sb_kattach when no osh is available */
8027 +/* exported externs */
8028 +extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
8029 + void *sdh, char **vars, uint *varsz);
8030 +extern sb_t *sb_kattach(void);
8031 +extern void sb_detach(sb_t *sbh);
8032 +extern uint sb_chip(sb_t *sbh);
8033 +extern uint sb_chiprev(sb_t *sbh);
8034 +extern uint sb_chipcrev(sb_t *sbh);
8035 +extern uint sb_chippkg(sb_t *sbh);
8036 +extern uint sb_pcirev(sb_t *sbh);
8037 +extern bool sb_war16165(sb_t *sbh);
8038 +extern uint sb_pcmciarev(sb_t *sbh);
8039 +extern uint sb_boardvendor(sb_t *sbh);
8040 +extern uint sb_boardtype(sb_t *sbh);
8041 +extern uint sb_bus(sb_t *sbh);
8042 +extern uint sb_buscoretype(sb_t *sbh);
8043 +extern uint sb_buscorerev(sb_t *sbh);
8044 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
8045 +extern uint sb_coreid(sb_t *sbh);
8046 +extern uint sb_coreidx(sb_t *sbh);
8047 +extern uint sb_coreunit(sb_t *sbh);
8048 +extern uint sb_corevendor(sb_t *sbh);
8049 +extern uint sb_corerev(sb_t *sbh);
8050 +extern void *sb_osh(sb_t *sbh);
8051 +extern void sb_setosh(sb_t *sbh, osl_t *osh);
8052 +extern void *sb_coreregs(sb_t *sbh);
8053 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
8054 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
8055 +extern bool sb_iscoreup(sb_t *sbh);
8056 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
8057 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
8058 +extern int sb_corebist(sb_t *sbh);
8059 +extern void sb_commit(sb_t *sbh);
8060 +extern uint32 sb_base(uint32 admatch);
8061 +extern uint32 sb_size(uint32 admatch);
8062 +extern void sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits);
8063 +extern void sb_core_tofixup(sb_t *sbh);
8064 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
8065 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
8066 +extern uint32 sb_clock(sb_t *sbh);
8067 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
8068 +extern void sb_pcmcia_init(sb_t *sbh);
8069 +extern void sb_watchdog(sb_t *sbh, uint ticks);
8070 +extern void *sb_gpiosetcore(sb_t *sbh);
8071 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8072 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8073 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8074 +extern uint32 sb_gpioin(sb_t *sbh);
8075 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8076 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8077 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
8078 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
8079 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
8080 +
8081 +extern void sb_clkctl_init(sb_t *sbh);
8082 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
8083 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
8084 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
8085 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
8086 + void *intrsenabled_fn, void *intr_arg);
8087 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
8088 +extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
8089 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
8090 + uint8 *pciheader);
8091 +extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
8092 +extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
8093 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
8094 +extern bool sb_backplane64(sb_t *sbh);
8095 +extern void sb_btcgpiowar(sb_t *sbh);
8096 +
8097 +
8098 +
8099 +
8100 +extern bool sb_deviceremoved(sb_t *sbh);
8101 +extern uint32 sb_socram_size(sb_t *sbh);
8102 +
8103 +/*
8104 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
8105 +* The returned path is NULL terminated and has trailing '/'.
8106 +* Return 0 on success, nonzero otherwise.
8107 +*/
8108 +extern int sb_devpath(sb_t *sbh, char *path, int size);
8109 +
8110 +/* clkctl xtal what flags */
8111 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
8112 +#define PLL 0x2 /* main chip pll */
8113 +
8114 +/* clkctl clk mode */
8115 +#define CLK_FAST 0 /* force fast (pll) clock */
8116 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
8117 +
8118 +
8119 +/* GPIO usage priorities */
8120 +#define GPIO_DRV_PRIORITY 0 /* Driver */
8121 +#define GPIO_APP_PRIORITY 1 /* Application */
8122 +#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
8123 +
8124 +/* device path */
8125 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
8126 +
8127 +#endif /* _sbutils_h_ */
8128 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
8129 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
8130 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2006-10-02 21:19:59.000000000 +0200
8131 @@ -0,0 +1,36 @@
8132 +/*
8133 + * Broadcom SiliconBackplane chipcommon serial flash interface
8134 + *
8135 + * Copyright 2006, Broadcom Corporation
8136 + * All Rights Reserved.
8137 + *
8138 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8139 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8140 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8141 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8142 + *
8143 + * $Id: sflash.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
8144 + */
8145 +
8146 +#ifndef _sflash_h_
8147 +#define _sflash_h_
8148 +
8149 +#include <typedefs.h>
8150 +#include <sbchipc.h>
8151 +
8152 +struct sflash {
8153 + uint blocksize; /* Block size */
8154 + uint numblocks; /* Number of blocks */
8155 + uint32 type; /* Type */
8156 + uint size; /* Total size in bytes */
8157 +};
8158 +
8159 +/* Utility functions */
8160 +extern int sflash_poll(chipcregs_t *cc, uint offset);
8161 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
8162 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8163 +extern int sflash_erase(chipcregs_t *cc, uint offset);
8164 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8165 +extern struct sflash * sflash_init(chipcregs_t *cc);
8166 +
8167 +#endif /* _sflash_h_ */
8168 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
8169 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
8170 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2006-10-02 21:19:59.000000000 +0200
8171 @@ -0,0 +1,33 @@
8172 +/*
8173 + * TRX image file header format.
8174 + *
8175 + * Copyright 2005, Broadcom Corporation
8176 + * All Rights Reserved.
8177 + *
8178 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8179 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8180 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8181 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8182 + *
8183 + * $Id$
8184 + */
8185 +
8186 +#include <typedefs.h>
8187 +
8188 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
8189 +#define TRX_VERSION 1
8190 +#define TRX_MAX_LEN 0x3A0000
8191 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
8192 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
8193 +#define TRX_MAX_OFFSET 3
8194 +
8195 +struct trx_header {
8196 + uint32 magic; /* "HDR0" */
8197 + uint32 len; /* Length of file including header */
8198 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
8199 + uint32 flag_version; /* 0:15 flags, 16:31 version */
8200 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
8201 +};
8202 +
8203 +/* Compatibility */
8204 +typedef struct trx_header TRXHDR, *PTRXHDR;
8205 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
8206 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
8207 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2006-10-02 21:19:59.000000000 +0200
8208 @@ -0,0 +1,361 @@
8209 +/*
8210 + * Copyright 2006, Broadcom Corporation
8211 + * All Rights Reserved.
8212 + *
8213 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8214 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8215 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8216 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8217 + * $Id: typedefs.h,v 1.1.1.12 2006/04/08 06:13:40 honor Exp $
8218 + */
8219 +
8220 +#ifndef _TYPEDEFS_H_
8221 +#define _TYPEDEFS_H_
8222 +
8223 +
8224 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
8225 + * typedef file "site_typedefs.h".
8226 + *
8227 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
8228 + * section of this file makes inferences about the compile environment
8229 + * based on defined symbols and possibly compiler pragmas.
8230 + *
8231 + * Following these two sections is the "Default Typedefs"
8232 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
8233 + * defined. This section has a default set of typedefs and a few
8234 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
8235 + */
8236 +
8237 +#ifdef SITE_TYPEDEFS
8238 +
8239 +/*
8240 + * Site Specific Typedefs
8241 + *
8242 + */
8243 +
8244 +#include "site_typedefs.h"
8245 +
8246 +#else
8247 +
8248 +/*
8249 + * Inferred Typedefs
8250 + *
8251 + */
8252 +
8253 +/* Infer the compile environment based on preprocessor symbols and pramas.
8254 + * Override type definitions as needed, and include configuration dependent
8255 + * header files to define types.
8256 + */
8257 +
8258 +#ifdef __cplusplus
8259 +
8260 +#define TYPEDEF_BOOL
8261 +#ifndef FALSE
8262 +#define FALSE false
8263 +#endif
8264 +#ifndef TRUE
8265 +#define TRUE true
8266 +#endif
8267 +
8268 +#else /* ! __cplusplus */
8269 +
8270 +#if defined(_WIN32)
8271 +
8272 +#define TYPEDEF_BOOL
8273 +typedef unsigned char bool; /* consistent w/BOOL */
8274 +
8275 +#endif /* _WIN32 */
8276 +
8277 +#endif /* ! __cplusplus */
8278 +
8279 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
8280 +#if defined(_WIN64)
8281 +#include <basetsd.h>
8282 +#define TYPEDEF_UINTPTR
8283 +typedef ULONG_PTR uintptr;
8284 +#endif
8285 +
8286 +
8287 +#if defined(_MINOSL_)
8288 +#define _NEED_SIZE_T_
8289 +#endif
8290 +
8291 +#if defined(_NEED_SIZE_T_)
8292 +typedef long unsigned int size_t;
8293 +#endif
8294 +
8295 +#ifdef __DJGPP__
8296 +typedef long unsigned int size_t;
8297 +#endif /* __DJGPP__ */
8298 +
8299 +#ifdef _MSC_VER /* Microsoft C */
8300 +#define TYPEDEF_INT64
8301 +#define TYPEDEF_UINT64
8302 +typedef signed __int64 int64;
8303 +typedef unsigned __int64 uint64;
8304 +#endif
8305 +
8306 +#if defined(MACOSX)
8307 +#define TYPEDEF_BOOL
8308 +#endif
8309 +
8310 +#if defined(__NetBSD__)
8311 +#define TYPEDEF_ULONG
8312 +#endif
8313 +
8314 +
8315 +#if defined(linux)
8316 +#define TYPEDEF_UINT
8317 +#define TYPEDEF_USHORT
8318 +#define TYPEDEF_ULONG
8319 +#endif
8320 +
8321 +#if !defined(linux) && !defined(_WIN32) && !defined(_CFE_) && \
8322 + !defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__)
8323 +#define TYPEDEF_UINT
8324 +#define TYPEDEF_USHORT
8325 +#endif
8326 +
8327 +
8328 +/* Do not support the (u)int64 types with strict ansi for GNU C */
8329 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
8330 +#define TYPEDEF_INT64
8331 +#define TYPEDEF_UINT64
8332 +#endif
8333 +
8334 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
8335 + * for singned or unsigned
8336 + */
8337 +#if defined(__ICL)
8338 +
8339 +#define TYPEDEF_INT64
8340 +
8341 +#if defined(__STDC__)
8342 +#define TYPEDEF_UINT64
8343 +#endif
8344 +
8345 +#endif /* __ICL */
8346 +
8347 +#if !defined(_WIN32) && !defined(_CFE_) && !defined(_MINOSL_) && \
8348 + !defined(__DJGPP__)
8349 +
8350 +/* pick up ushort & uint from standard types.h */
8351 +#if defined(linux) && defined(__KERNEL__)
8352 +
8353 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
8354 +
8355 +#else
8356 +
8357 +#include <sys/types.h>
8358 +
8359 +#endif
8360 +
8361 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ && !__DJGPP__ */
8362 +
8363 +#if defined(MACOSX)
8364 +
8365 +#ifdef __BIG_ENDIAN__
8366 +#define IL_BIGENDIAN
8367 +#else
8368 +#ifdef IL_BIGENDIAN
8369 +#error "IL_BIGENDIAN was defined for a little-endian compile"
8370 +#endif
8371 +#endif /* __BIG_ENDIAN__ */
8372 +
8373 +#if !defined(__cplusplus)
8374 +
8375 +#if defined(__i386__)
8376 +typedef unsigned char bool;
8377 +#else
8378 +typedef unsigned int bool;
8379 +#endif
8380 +#define TYPE_BOOL 1
8381 +enum {
8382 + false = 0,
8383 + true = 1
8384 +};
8385 +
8386 +#if defined(KERNEL)
8387 +#include <IOKit/IOTypes.h>
8388 +#endif /* KERNEL */
8389 +
8390 +#endif /* __cplusplus */
8391 +
8392 +#endif /* MACOSX */
8393 +
8394 +
8395 +/* use the default typedefs in the next section of this file */
8396 +#define USE_TYPEDEF_DEFAULTS
8397 +
8398 +#endif /* SITE_TYPEDEFS */
8399 +
8400 +
8401 +/*
8402 + * Default Typedefs
8403 + *
8404 + */
8405 +
8406 +#ifdef USE_TYPEDEF_DEFAULTS
8407 +#undef USE_TYPEDEF_DEFAULTS
8408 +
8409 +#ifndef TYPEDEF_BOOL
8410 +typedef /* @abstract@ */ unsigned char bool;
8411 +#endif
8412 +
8413 +/* define uchar, ushort, uint, ulong */
8414 +
8415 +#ifndef TYPEDEF_UCHAR
8416 +typedef unsigned char uchar;
8417 +#endif
8418 +
8419 +#ifndef TYPEDEF_USHORT
8420 +typedef unsigned short ushort;
8421 +#endif
8422 +
8423 +#ifndef TYPEDEF_UINT
8424 +typedef unsigned int uint;
8425 +#endif
8426 +
8427 +#ifndef TYPEDEF_ULONG
8428 +typedef unsigned long ulong;
8429 +#endif
8430 +
8431 +/* define [u]int8/16/32/64, uintptr */
8432 +
8433 +#ifndef TYPEDEF_UINT8
8434 +typedef unsigned char uint8;
8435 +#endif
8436 +
8437 +#ifndef TYPEDEF_UINT16
8438 +typedef unsigned short uint16;
8439 +#endif
8440 +
8441 +#ifndef TYPEDEF_UINT32
8442 +typedef unsigned int uint32;
8443 +#endif
8444 +
8445 +#ifndef TYPEDEF_UINT64
8446 +typedef unsigned long long uint64;
8447 +#endif
8448 +
8449 +#ifndef TYPEDEF_UINTPTR
8450 +typedef unsigned int uintptr;
8451 +#endif
8452 +
8453 +#ifndef TYPEDEF_INT8
8454 +typedef signed char int8;
8455 +#endif
8456 +
8457 +#ifndef TYPEDEF_INT16
8458 +typedef signed short int16;
8459 +#endif
8460 +
8461 +#ifndef TYPEDEF_INT32
8462 +typedef signed int int32;
8463 +#endif
8464 +
8465 +#ifndef TYPEDEF_INT64
8466 +typedef signed long long int64;
8467 +#endif
8468 +
8469 +/* define float32/64, float_t */
8470 +
8471 +#ifndef TYPEDEF_FLOAT32
8472 +typedef float float32;
8473 +#endif
8474 +
8475 +#ifndef TYPEDEF_FLOAT64
8476 +typedef double float64;
8477 +#endif
8478 +
8479 +/*
8480 + * abstracted floating point type allows for compile time selection of
8481 + * single or double precision arithmetic. Compiling with -DFLOAT32
8482 + * selects single precision; the default is double precision.
8483 + */
8484 +
8485 +#ifndef TYPEDEF_FLOAT_T
8486 +
8487 +#if defined(FLOAT32)
8488 +typedef float32 float_t;
8489 +#else /* default to double precision floating point */
8490 +typedef float64 float_t;
8491 +#endif
8492 +
8493 +#endif /* TYPEDEF_FLOAT_T */
8494 +
8495 +/* define macro values */
8496 +
8497 +#ifndef FALSE
8498 +#define FALSE 0
8499 +#endif
8500 +
8501 +#ifndef TRUE
8502 +#define TRUE 1 /* TRUE */
8503 +#endif
8504 +
8505 +#ifndef NULL
8506 +#define NULL 0
8507 +#endif
8508 +
8509 +#ifndef OFF
8510 +#define OFF 0
8511 +#endif
8512 +
8513 +#ifndef ON
8514 +#define ON 1 /* ON = 1 */
8515 +#endif
8516 +
8517 +#define AUTO (-1) /* Auto = -1 */
8518 +
8519 +/* define PTRSZ, INLINE */
8520 +
8521 +#ifndef PTRSZ
8522 +#define PTRSZ sizeof(char*)
8523 +#endif
8524 +
8525 +#ifndef INLINE
8526 +
8527 +#ifdef _MSC_VER
8528 +
8529 +#define INLINE __inline
8530 +
8531 +#elif __GNUC__
8532 +
8533 +#define INLINE __inline__
8534 +
8535 +#else
8536 +
8537 +#define INLINE
8538 +
8539 +#endif /* _MSC_VER */
8540 +
8541 +#endif /* INLINE */
8542 +
8543 +#undef TYPEDEF_BOOL
8544 +#undef TYPEDEF_UCHAR
8545 +#undef TYPEDEF_USHORT
8546 +#undef TYPEDEF_UINT
8547 +#undef TYPEDEF_ULONG
8548 +#undef TYPEDEF_UINT8
8549 +#undef TYPEDEF_UINT16
8550 +#undef TYPEDEF_UINT32
8551 +#undef TYPEDEF_UINT64
8552 +#undef TYPEDEF_UINTPTR
8553 +#undef TYPEDEF_INT8
8554 +#undef TYPEDEF_INT16
8555 +#undef TYPEDEF_INT32
8556 +#undef TYPEDEF_INT64
8557 +#undef TYPEDEF_FLOAT32
8558 +#undef TYPEDEF_FLOAT64
8559 +#undef TYPEDEF_FLOAT_T
8560 +
8561 +#endif /* USE_TYPEDEF_DEFAULTS */
8562 +
8563 +/*
8564 + * Including the bcmdefs.h here, to make sure everyone including typedefs.h
8565 + * gets this automatically
8566 +*/
8567 +#include "bcmdefs.h"
8568 +
8569 +#endif /* _TYPEDEFS_H_ */
8570 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
8571 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
8572 +++ linux.dev/arch/mips/bcm947xx/Makefile 2006-10-02 21:26:08.000000000 +0200
8573 @@ -0,0 +1,17 @@
8574 +#
8575 +# Makefile for the BCM947xx specific kernel interface routines
8576 +# under Linux.
8577 +#
8578 +
8579 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER -fno-delayed-branch
8580 +
8581 +O_TARGET := bcm947xx.o
8582 +
8583 +export-objs := export.o
8584 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
8585 +obj-y += nvram.o nvram_linux.o sflash.o cfe_env.o
8586 +obj-y += sbutils.o bcmutils.o bcmsrom.o hndchipc.o
8587 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
8588 +obj-y += export.o
8589 +
8590 +include $(TOPDIR)/Rules.make
8591 diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
8592 --- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
8593 +++ linux.dev/arch/mips/bcm947xx/nvram.c 2006-10-02 21:19:59.000000000 +0200
8594 @@ -0,0 +1,315 @@
8595 +/*
8596 + * NVRAM variable manipulation (common)
8597 + *
8598 + * Copyright 2004, Broadcom Corporation
8599 + * All Rights Reserved.
8600 + *
8601 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8602 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8603 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8604 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8605 + *
8606 + */
8607 +
8608 +#include <typedefs.h>
8609 +#include <osl.h>
8610 +#include <bcmendian.h>
8611 +#include <bcmnvram.h>
8612 +#include <bcmutils.h>
8613 +#include <sbsdram.h>
8614 +
8615 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
8616 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
8617 +extern int BCMINIT(_nvram_read)(void *buf);
8618 +
8619 +char * BCMINIT(_nvram_get)(const char *name);
8620 +int BCMINIT(_nvram_set)(const char *name, const char *value);
8621 +int BCMINIT(_nvram_unset)(const char *name);
8622 +int BCMINIT(_nvram_getall)(char *buf, int count);
8623 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
8624 +int BCMINIT(_nvram_init)(void);
8625 +void BCMINIT(_nvram_exit)(void);
8626 +
8627 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
8628 +static struct nvram_tuple * nvram_dead;
8629 +
8630 +/* Free all tuples. Should be locked. */
8631 +static void
8632 +BCMINITFN(nvram_free)(void)
8633 +{
8634 + uint i;
8635 + struct nvram_tuple *t, *next;
8636 +
8637 + /* Free hash table */
8638 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8639 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
8640 + next = t->next;
8641 + BCMINIT(_nvram_free)(t);
8642 + }
8643 + BCMINIT(nvram_hash)[i] = NULL;
8644 + }
8645 +
8646 + /* Free dead table */
8647 + for (t = nvram_dead; t; t = next) {
8648 + next = t->next;
8649 + BCMINIT(_nvram_free)(t);
8650 + }
8651 + nvram_dead = NULL;
8652 +
8653 + /* Indicate to per-port code that all tuples have been freed */
8654 + BCMINIT(_nvram_free)(NULL);
8655 +}
8656 +
8657 +/* String hash */
8658 +static INLINE uint
8659 +hash(const char *s)
8660 +{
8661 + uint hash = 0;
8662 +
8663 + while (*s)
8664 + hash = 31 * hash + *s++;
8665 +
8666 + return hash;
8667 +}
8668 +
8669 +/* (Re)initialize the hash table. Should be locked. */
8670 +static int
8671 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
8672 +{
8673 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
8674 +
8675 + /* (Re)initialize hash table */
8676 + BCMINIT(nvram_free)();
8677 +
8678 + /* Parse and set "name=value\0 ... \0\0" */
8679 + name = (char *) &header[1];
8680 + end = (char *) header + NVRAM_SPACE - 2;
8681 + end[0] = end[1] = '\0';
8682 + for (; *name; name = value + strlen(value) + 1) {
8683 + if (!(eq = strchr(name, '=')))
8684 + break;
8685 + *eq = '\0';
8686 + value = eq + 1;
8687 + BCMINIT(_nvram_set)(name, value);
8688 + *eq = '=';
8689 + }
8690 +
8691 + /* Set special SDRAM parameters */
8692 + if (!BCMINIT(_nvram_get)("sdram_init")) {
8693 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
8694 + BCMINIT(_nvram_set)("sdram_init", buf);
8695 + }
8696 + if (!BCMINIT(_nvram_get)("sdram_config")) {
8697 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
8698 + BCMINIT(_nvram_set)("sdram_config", buf);
8699 + }
8700 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
8701 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
8702 + BCMINIT(_nvram_set)("sdram_refresh", buf);
8703 + }
8704 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
8705 + sprintf(buf, "0x%08X", header->config_ncdl);
8706 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
8707 + }
8708 +
8709 + return 0;
8710 +}
8711 +
8712 +/* Get the value of an NVRAM variable. Should be locked. */
8713 +char *
8714 +BCMINITFN(_nvram_get)(const char *name)
8715 +{
8716 + uint i;
8717 + struct nvram_tuple *t;
8718 + char *value;
8719 +
8720 + if (!name)
8721 + return NULL;
8722 +
8723 + /* Hash the name */
8724 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8725 +
8726 + /* Find the associated tuple in the hash table */
8727 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
8728 +
8729 + value = t ? t->value : NULL;
8730 +
8731 + return value;
8732 +}
8733 +
8734 +/* Get the value of an NVRAM variable. Should be locked. */
8735 +int
8736 +BCMINITFN(_nvram_set)(const char *name, const char *value)
8737 +{
8738 + uint i;
8739 + struct nvram_tuple *t, *u, **prev;
8740 +
8741 + /* Hash the name */
8742 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8743 +
8744 + /* Find the associated tuple in the hash table */
8745 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8746 +
8747 + /* (Re)allocate tuple */
8748 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
8749 + return -12; /* -ENOMEM */
8750 +
8751 + /* Value reallocated */
8752 + if (t && t == u)
8753 + return 0;
8754 +
8755 + /* Move old tuple to the dead table */
8756 + if (t) {
8757 + *prev = t->next;
8758 + t->next = nvram_dead;
8759 + nvram_dead = t;
8760 + }
8761 +
8762 + /* Add new tuple to the hash table */
8763 + u->next = BCMINIT(nvram_hash)[i];
8764 + BCMINIT(nvram_hash)[i] = u;
8765 +
8766 + return 0;
8767 +}
8768 +
8769 +/* Unset the value of an NVRAM variable. Should be locked. */
8770 +int
8771 +BCMINITFN(_nvram_unset)(const char *name)
8772 +{
8773 + uint i;
8774 + struct nvram_tuple *t, **prev;
8775 +
8776 + if (!name)
8777 + return 0;
8778 +
8779 + /* Hash the name */
8780 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8781 +
8782 + /* Find the associated tuple in the hash table */
8783 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8784 +
8785 + /* Move it to the dead table */
8786 + if (t) {
8787 + *prev = t->next;
8788 + t->next = nvram_dead;
8789 + nvram_dead = t;
8790 + }
8791 +
8792 + return 0;
8793 +}
8794 +
8795 +/* Get all NVRAM variables. Should be locked. */
8796 +int
8797 +BCMINITFN(_nvram_getall)(char *buf, int count)
8798 +{
8799 + uint i;
8800 + struct nvram_tuple *t;
8801 + int len = 0;
8802 +
8803 + bzero(buf, count);
8804 +
8805 + /* Write name=value\0 ... \0\0 */
8806 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8807 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8808 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
8809 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
8810 + else
8811 + break;
8812 + }
8813 + }
8814 +
8815 + return 0;
8816 +}
8817 +
8818 +/* Regenerate NVRAM. Should be locked. */
8819 +int
8820 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
8821 +{
8822 + char *init, *config, *refresh, *ncdl;
8823 + char *ptr, *end;
8824 + int i;
8825 + struct nvram_tuple *t;
8826 + struct nvram_header tmp;
8827 + uint8 crc;
8828 +
8829 + /* Regenerate header */
8830 + header->magic = NVRAM_MAGIC;
8831 + header->crc_ver_init = (NVRAM_VERSION << 8);
8832 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
8833 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
8834 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
8835 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
8836 + header->crc_ver_init |= SDRAM_INIT << 16;
8837 + header->config_refresh = SDRAM_CONFIG;
8838 + header->config_refresh |= SDRAM_REFRESH << 16;
8839 + header->config_ncdl = 0;
8840 + } else {
8841 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
8842 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
8843 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
8844 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
8845 + }
8846 +
8847 + /* Clear data area */
8848 + ptr = (char *) header + sizeof(struct nvram_header);
8849 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
8850 +
8851 + /* Leave space for a double NUL at the end */
8852 + end = (char *) header + NVRAM_SPACE - 2;
8853 +
8854 + /* Write out all tuples */
8855 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8856 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8857 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
8858 + break;
8859 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
8860 + }
8861 + }
8862 +
8863 + /* End with a double NUL */
8864 + ptr += 2;
8865 +
8866 + /* Set new length */
8867 + header->len = ROUNDUP(ptr - (char *) header, 4);
8868 +
8869 + /* Little-endian CRC8 over the last 11 bytes of the header */
8870 + tmp.crc_ver_init = htol32(header->crc_ver_init);
8871 + tmp.config_refresh = htol32(header->config_refresh);
8872 + tmp.config_ncdl = htol32(header->config_ncdl);
8873 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
8874 +
8875 + /* Continue CRC8 over data bytes */
8876 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
8877 +
8878 + /* Set new CRC8 */
8879 + header->crc_ver_init |= crc;
8880 +
8881 + /* Reinitialize hash table */
8882 + return BCMINIT(nvram_rehash)(header);
8883 +}
8884 +
8885 +/* Initialize hash table. Should be locked. */
8886 +int
8887 +BCMINITFN(_nvram_init)(void)
8888 +{
8889 + struct nvram_header *header;
8890 + int ret;
8891 +
8892 + if (!(header = (struct nvram_header *) kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
8893 + return -12; /* -ENOMEM */
8894 + }
8895 +
8896 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
8897 + header->magic == NVRAM_MAGIC)
8898 + BCMINIT(nvram_rehash)(header);
8899 +
8900 + kfree(header);
8901 + return ret;
8902 +}
8903 +
8904 +/* Free hash table. Should be locked. */
8905 +void
8906 +BCMINITFN(_nvram_exit)(void)
8907 +{
8908 + BCMINIT(nvram_free)();
8909 +}
8910 diff -urN linux.old/arch/mips/bcm947xx/nvram_linux.c linux.dev/arch/mips/bcm947xx/nvram_linux.c
8911 --- linux.old/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
8912 +++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2006-10-02 21:19:59.000000000 +0200
8913 @@ -0,0 +1,723 @@
8914 +/*
8915 + * NVRAM variable manipulation (Linux kernel half)
8916 + *
8917 + * Copyright 2006, Broadcom Corporation
8918 + * All Rights Reserved.
8919 + *
8920 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8921 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8922 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8923 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8924 + *
8925 + * $Id: nvram_linux.c,v 1.19 2006/04/08 07:12:42 honor Exp $
8926 + */
8927 +
8928 +#include <linux/config.h>
8929 +#include <linux/init.h>
8930 +#include <linux/module.h>
8931 +#include <linux/kernel.h>
8932 +#include <linux/string.h>
8933 +#include <linux/interrupt.h>
8934 +#include <linux/spinlock.h>
8935 +#include <linux/slab.h>
8936 +#include <linux/bootmem.h>
8937 +#include <linux/wrapper.h>
8938 +#include <linux/fs.h>
8939 +#include <linux/miscdevice.h>
8940 +#include <linux/mtd/mtd.h>
8941 +#include <asm/addrspace.h>
8942 +#include <asm/io.h>
8943 +#include <asm/uaccess.h>
8944 +
8945 +#include <typedefs.h>
8946 +#include <osl.h>
8947 +#include <bcmendian.h>
8948 +#include <bcmnvram.h>
8949 +#include <bcmutils.h>
8950 +#include <sbconfig.h>
8951 +#include <sbchipc.h>
8952 +#include <sbutils.h>
8953 +#include <hndmips.h>
8954 +#include <sflash.h>
8955 +
8956 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
8957 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
8958 +
8959 +#ifdef MODULE
8960 +
8961 +#define early_nvram_get(name) nvram_get(name)
8962 +
8963 +#else /* !MODULE */
8964 +
8965 +/* Global SB handle */
8966 +extern void *bcm947xx_sbh;
8967 +extern spinlock_t bcm947xx_sbh_lock;
8968 +
8969 +static int cfe_env;
8970 +extern char *cfe_env_get(char *nv_buf, const char *name);
8971 +
8972 +/* Convenience */
8973 +#define sbh bcm947xx_sbh
8974 +#define sbh_lock bcm947xx_sbh_lock
8975 +#define KB * 1024
8976 +#define MB * 1024 * 1024
8977 +
8978 +/* Probe for NVRAM header */
8979 +static void __init
8980 +early_nvram_init(void)
8981 +{
8982 + struct nvram_header *header;
8983 + chipcregs_t *cc;
8984 + struct sflash *info = NULL;
8985 + int i;
8986 + uint32 base, off, lim;
8987 + u32 *src, *dst;
8988 +
8989 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
8990 + base = KSEG1ADDR(SB_FLASH2);
8991 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
8992 + case PFLASH:
8993 + lim = SB_FLASH2_SZ;
8994 + break;
8995 +
8996 + case SFLASH_ST:
8997 + case SFLASH_AT:
8998 + if ((info = sflash_init(cc)) == NULL)
8999 + return;
9000 + lim = info->size;
9001 + break;
9002 +
9003 + case FLASH_NONE:
9004 + default:
9005 + return;
9006 + }
9007 + } else {
9008 + /* extif assumed, Stop at 4 MB */
9009 + base = KSEG1ADDR(SB_FLASH1);
9010 + lim = SB_FLASH1_SZ;
9011 + }
9012 +
9013 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
9014 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
9015 + dst = (u32 *) nvram_buf;
9016 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
9017 + printk("early_nvram_init: WGT634U NVRAM found.\n");
9018 +
9019 + for (i = 0; i < 0x1ff0; i++) {
9020 + if (*src == 0xFFFFFFFF)
9021 + break;
9022 + *dst++ = *src++;
9023 + }
9024 + cfe_env = 1;
9025 + return;
9026 + }
9027 +
9028 + off = FLASH_MIN;
9029 + while (off <= lim) {
9030 + /* Windowed flash access */
9031 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
9032 + if (header->magic == NVRAM_MAGIC)
9033 + goto found;
9034 + off <<= 1;
9035 + }
9036 +
9037 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
9038 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
9039 + if (header->magic == NVRAM_MAGIC)
9040 + goto found;
9041 +
9042 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
9043 + if (header->magic == NVRAM_MAGIC)
9044 + goto found;
9045 +
9046 + printk("early_nvram_init: NVRAM not found\n");
9047 + return;
9048 +
9049 +found:
9050 + src = (u32 *) header;
9051 + dst = (u32 *) nvram_buf;
9052 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
9053 + *dst++ = *src++;
9054 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
9055 + *dst++ = ltoh32(*src++);
9056 +}
9057 +
9058 +/* Early (before mm or mtd) read-only access to NVRAM */
9059 +static char * __init
9060 +early_nvram_get(const char *name)
9061 +{
9062 + char *var, *value, *end, *eq;
9063 +
9064 + if (!name)
9065 + return NULL;
9066 +
9067 + /* Too early? */
9068 + if (sbh == NULL)
9069 + return NULL;
9070 +
9071 + if (!nvram_buf[0])
9072 + early_nvram_init();
9073 +
9074 + if (cfe_env)
9075 + return cfe_env_get(nvram_buf, name);
9076 +
9077 + /* Look for name=value and return value */
9078 + var = &nvram_buf[sizeof(struct nvram_header)];
9079 + end = nvram_buf + sizeof(nvram_buf) - 2;
9080 + end[0] = end[1] = '\0';
9081 + for (; *var; var = value + strlen(value) + 1) {
9082 + if (!(eq = strchr(var, '=')))
9083 + break;
9084 + value = eq + 1;
9085 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
9086 + return value;
9087 + }
9088 +
9089 + return NULL;
9090 +}
9091 +
9092 +static int __init
9093 +early_nvram_getall(char *buf, int count)
9094 +{
9095 + char *var, *end;
9096 + int len = 0;
9097 +
9098 + /* Too early? */
9099 + if (sbh == NULL)
9100 + return -1;
9101 +
9102 + if (!nvram_buf[0])
9103 + early_nvram_init();
9104 +
9105 + bzero(buf, count);
9106 +
9107 + /* Write name=value\0 ... \0\0 */
9108 + var = &nvram_buf[sizeof(struct nvram_header)];
9109 + end = nvram_buf + sizeof(nvram_buf) - 2;
9110 + end[0] = end[1] = '\0';
9111 + for (; *var; var += strlen(var) + 1) {
9112 + if ((count - len) <= (strlen(var) + 1))
9113 + break;
9114 + len += sprintf(buf + len, "%s", var) + 1;
9115 + }
9116 +
9117 + return 0;
9118 +}
9119 +#endif /* !MODULE */
9120 +
9121 +extern char * _nvram_get(const char *name);
9122 +extern int _nvram_set(const char *name, const char *value);
9123 +extern int _nvram_unset(const char *name);
9124 +extern int _nvram_getall(char *buf, int count);
9125 +extern int _nvram_commit(struct nvram_header *header);
9126 +extern int _nvram_init(void *sbh);
9127 +extern void _nvram_exit(void);
9128 +
9129 +/* Globals */
9130 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
9131 +static struct semaphore nvram_sem;
9132 +static unsigned long nvram_offset = 0;
9133 +static int nvram_major = -1;
9134 +static devfs_handle_t nvram_handle = NULL;
9135 +static struct mtd_info *nvram_mtd = NULL;
9136 +
9137 +int
9138 +_nvram_read(char *buf)
9139 +{
9140 + struct nvram_header *header = (struct nvram_header *) buf;
9141 + size_t len;
9142 +
9143 + if (!nvram_mtd ||
9144 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
9145 + len != NVRAM_SPACE ||
9146 + header->magic != NVRAM_MAGIC) {
9147 + /* Maybe we can recover some data from early initialization */
9148 + memcpy(buf, nvram_buf, NVRAM_SPACE);
9149 + }
9150 +
9151 + return 0;
9152 +}
9153 +
9154 +struct nvram_tuple *
9155 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
9156 +{
9157 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
9158 + return NULL;
9159 +
9160 + if (!t) {
9161 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
9162 + return NULL;
9163 +
9164 + /* Copy name */
9165 + t->name = (char *) &t[1];
9166 + strcpy(t->name, name);
9167 +
9168 + t->value = NULL;
9169 + }
9170 +
9171 + /* Copy value */
9172 + if (!t->value || strcmp(t->value, value)) {
9173 + t->value = &nvram_buf[nvram_offset];
9174 + strcpy(t->value, value);
9175 + nvram_offset += strlen(value) + 1;
9176 + }
9177 +
9178 + return t;
9179 +}
9180 +
9181 +void
9182 +_nvram_free(struct nvram_tuple *t)
9183 +{
9184 + if (!t)
9185 + nvram_offset = 0;
9186 + else
9187 + kfree(t);
9188 +}
9189 +
9190 +int
9191 +nvram_set(const char *name, const char *value)
9192 +{
9193 + unsigned long flags;
9194 + int ret;
9195 + struct nvram_header *header;
9196 +
9197 + spin_lock_irqsave(&nvram_lock, flags);
9198 + if ((ret = _nvram_set(name, value))) {
9199 + /* Consolidate space and try again */
9200 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
9201 + if (_nvram_commit(header) == 0)
9202 + ret = _nvram_set(name, value);
9203 + kfree(header);
9204 + }
9205 + }
9206 + spin_unlock_irqrestore(&nvram_lock, flags);
9207 +
9208 + return ret;
9209 +}
9210 +
9211 +char *
9212 +real_nvram_get(const char *name)
9213 +{
9214 + unsigned long flags;
9215 + char *value;
9216 +
9217 + spin_lock_irqsave(&nvram_lock, flags);
9218 + value = _nvram_get(name);
9219 + spin_unlock_irqrestore(&nvram_lock, flags);
9220 +
9221 + return value;
9222 +}
9223 +
9224 +char *
9225 +nvram_get(const char *name)
9226 +{
9227 + if (nvram_major >= 0)
9228 + return real_nvram_get(name);
9229 + else
9230 + return early_nvram_get(name);
9231 +}
9232 +
9233 +int
9234 +nvram_unset(const char *name)
9235 +{
9236 + unsigned long flags;
9237 + int ret;
9238 +
9239 + spin_lock_irqsave(&nvram_lock, flags);
9240 + ret = _nvram_unset(name);
9241 + spin_unlock_irqrestore(&nvram_lock, flags);
9242 +
9243 + return ret;
9244 +}
9245 +
9246 +static void
9247 +erase_callback(struct erase_info *done)
9248 +{
9249 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
9250 + wake_up(wait_q);
9251 +}
9252 +
9253 +int
9254 +nvram_commit(void)
9255 +{
9256 + char *buf;
9257 + size_t erasesize, len, magic_len;
9258 + unsigned int i;
9259 + int ret;
9260 + struct nvram_header *header;
9261 + unsigned long flags;
9262 + u_int32_t offset;
9263 + DECLARE_WAITQUEUE(wait, current);
9264 + wait_queue_head_t wait_q;
9265 + struct erase_info erase;
9266 + u_int32_t magic_offset = 0; /* Offset for writing MAGIC # */
9267 +
9268 + if (!nvram_mtd) {
9269 + printk("nvram_commit: NVRAM not found\n");
9270 + return -ENODEV;
9271 + }
9272 +
9273 + if (in_interrupt()) {
9274 + printk("nvram_commit: not committing in interrupt\n");
9275 + return -EINVAL;
9276 + }
9277 +
9278 + /* Backup sector blocks to be erased */
9279 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
9280 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
9281 + printk("nvram_commit: out of memory\n");
9282 + return -ENOMEM;
9283 + }
9284 +
9285 + down(&nvram_sem);
9286 +
9287 + if ((i = erasesize - NVRAM_SPACE) > 0) {
9288 + offset = nvram_mtd->size - erasesize;
9289 + len = 0;
9290 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
9291 + if (ret || len != i) {
9292 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
9293 + ret = -EIO;
9294 + goto done;
9295 + }
9296 + header = (struct nvram_header *)(buf + i);
9297 + magic_offset = i + ((void *)&header->magic - (void *)header);
9298 + } else {
9299 + offset = nvram_mtd->size - NVRAM_SPACE;
9300 + magic_offset = ((void *)&header->magic - (void *)header);
9301 + header = (struct nvram_header *)buf;
9302 + }
9303 +
9304 + /* clear the existing magic # to mark the NVRAM as unusable
9305 + we can pull MAGIC bits low without erase */
9306 + header->magic = NVRAM_CLEAR_MAGIC; /* All zeros magic */
9307 +
9308 + /* Unlock sector blocks (for Intel 28F320C3B flash) , 20060309 */
9309 + if(nvram_mtd->unlock)
9310 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9311 +
9312 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9313 + &magic_len, (char *)&header->magic);
9314 + if (ret || magic_len != sizeof(header->magic)) {
9315 + printk("nvram_commit: clear MAGIC error\n");
9316 + ret = -EIO;
9317 + goto done;
9318 + }
9319 +
9320 + header->magic = NVRAM_MAGIC; /* reset MAGIC before we regenerate the NVRAM,
9321 + otherwise we'll have an incorrect CRC */
9322 + /* Regenerate NVRAM */
9323 + spin_lock_irqsave(&nvram_lock, flags);
9324 + ret = _nvram_commit(header);
9325 + spin_unlock_irqrestore(&nvram_lock, flags);
9326 + if (ret)
9327 + goto done;
9328 +
9329 + /* Erase sector blocks */
9330 + init_waitqueue_head(&wait_q);
9331 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
9332 + erase.mtd = nvram_mtd;
9333 + erase.addr = offset;
9334 + erase.len = nvram_mtd->erasesize;
9335 + erase.callback = erase_callback;
9336 + erase.priv = (u_long) &wait_q;
9337 +
9338 + set_current_state(TASK_INTERRUPTIBLE);
9339 + add_wait_queue(&wait_q, &wait);
9340 +
9341 + /* Unlock sector blocks */
9342 + if (nvram_mtd->unlock)
9343 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9344 +
9345 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
9346 + set_current_state(TASK_RUNNING);
9347 + remove_wait_queue(&wait_q, &wait);
9348 + printk("nvram_commit: erase error\n");
9349 + goto done;
9350 + }
9351 +
9352 + /* Wait for erase to finish */
9353 + schedule();
9354 + remove_wait_queue(&wait_q, &wait);
9355 + }
9356 +
9357 + /* Write partition up to end of data area */
9358 + header->magic = NVRAM_INVALID_MAGIC; /* All ones magic */
9359 + offset = nvram_mtd->size - erasesize;
9360 + i = erasesize - NVRAM_SPACE + header->len;
9361 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
9362 + if (ret || len != i) {
9363 + printk("nvram_commit: write error\n");
9364 + ret = -EIO;
9365 + goto done;
9366 + }
9367 +
9368 + /* Now mark the NVRAM in flash as "valid" by setting the correct
9369 + MAGIC # */
9370 + header->magic = NVRAM_MAGIC;
9371 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9372 + &magic_len, (char *)&header->magic);
9373 + if (ret || magic_len != sizeof(header->magic)) {
9374 + printk("nvram_commit: write MAGIC error\n");
9375 + ret = -EIO;
9376 + goto done;
9377 + }
9378 +
9379 + /*
9380 + * Reading a few bytes back here will put the device
9381 + * back to the correct mode on certain flashes */
9382 + offset = nvram_mtd->size - erasesize;
9383 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
9384 +
9385 + done:
9386 + up(&nvram_sem);
9387 + kfree(buf);
9388 +
9389 + return ret;
9390 +}
9391 +
9392 +int
9393 +nvram_getall(char *buf, int count)
9394 +{
9395 + unsigned long flags;
9396 + int ret;
9397 +
9398 + spin_lock_irqsave(&nvram_lock, flags);
9399 + if (nvram_major >= 0)
9400 + ret = _nvram_getall(buf, count);
9401 + else
9402 + ret = early_nvram_getall(buf, count);
9403 + spin_unlock_irqrestore(&nvram_lock, flags);
9404 +
9405 + return ret;
9406 +}
9407 +
9408 +
9409 +
9410 +
9411 +
9412 +
9413 +
9414 +/* User mode interface below */
9415 +
9416 +static ssize_t
9417 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
9418 +{
9419 + char tmp[100], *name = tmp, *value;
9420 + ssize_t ret;
9421 + unsigned long off;
9422 +
9423 + if (count > sizeof(tmp)) {
9424 + if (!(name = kmalloc(count, GFP_KERNEL)))
9425 + return -ENOMEM;
9426 + }
9427 +
9428 + if (copy_from_user(name, buf, count)) {
9429 + ret = -EFAULT;
9430 + goto done;
9431 + }
9432 +
9433 + if (*name == '\0') {
9434 + /* Get all variables */
9435 + ret = nvram_getall(name, count);
9436 + if (ret == 0) {
9437 + if (copy_to_user(buf, name, count)) {
9438 + ret = -EFAULT;
9439 + goto done;
9440 + }
9441 + ret = count;
9442 + }
9443 + } else {
9444 + if (!(value = nvram_get(name))) {
9445 + ret = 0;
9446 + goto done;
9447 + }
9448 +
9449 + /* Provide the offset into mmap() space */
9450 + off = (unsigned long) value - (unsigned long) nvram_buf;
9451 +
9452 + if (put_user(off, (unsigned long *) buf)) {
9453 + ret = -EFAULT;
9454 + goto done;
9455 + }
9456 +
9457 + ret = sizeof(unsigned long);
9458 + }
9459 +
9460 + flush_cache_all();
9461 +
9462 +done:
9463 + if (name != tmp)
9464 + kfree(name);
9465 +
9466 + return ret;
9467 +}
9468 +
9469 +static ssize_t
9470 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
9471 +{
9472 + char tmp[100], *name = tmp, *value;
9473 + ssize_t ret;
9474 +
9475 + if (count > sizeof(tmp)) {
9476 + if (!(name = kmalloc(count, GFP_KERNEL)))
9477 + return -ENOMEM;
9478 + }
9479 +
9480 + if (copy_from_user(name, buf, count)) {
9481 + ret = -EFAULT;
9482 + goto done;
9483 + }
9484 +
9485 + value = name;
9486 + name = strsep(&value, "=");
9487 + if (value)
9488 + ret = nvram_set(name, value) ? : count;
9489 + else
9490 + ret = nvram_unset(name) ? : count;
9491 +
9492 + done:
9493 + if (name != tmp)
9494 + kfree(name);
9495 +
9496 + return ret;
9497 +}
9498 +
9499 +static int
9500 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
9501 +{
9502 + if (cmd != NVRAM_MAGIC)
9503 + return -EINVAL;
9504 +
9505 + return nvram_commit();
9506 +}
9507 +
9508 +static int
9509 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
9510 +{
9511 + unsigned long offset = virt_to_phys(nvram_buf);
9512 +
9513 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
9514 + vma->vm_page_prot))
9515 + return -EAGAIN;
9516 +
9517 + return 0;
9518 +}
9519 +
9520 +static int
9521 +dev_nvram_open(struct inode *inode, struct file * file)
9522 +{
9523 + MOD_INC_USE_COUNT;
9524 + return 0;
9525 +}
9526 +
9527 +static int
9528 +dev_nvram_release(struct inode *inode, struct file * file)
9529 +{
9530 + MOD_DEC_USE_COUNT;
9531 + return 0;
9532 +}
9533 +
9534 +static struct file_operations dev_nvram_fops = {
9535 + owner: THIS_MODULE,
9536 + open: dev_nvram_open,
9537 + release: dev_nvram_release,
9538 + read: dev_nvram_read,
9539 + write: dev_nvram_write,
9540 + ioctl: dev_nvram_ioctl,
9541 + mmap: dev_nvram_mmap,
9542 +};
9543 +
9544 +static void
9545 +dev_nvram_exit(void)
9546 +{
9547 + int order = 0;
9548 + struct page *page, *end;
9549 +
9550 + if (nvram_handle)
9551 + devfs_unregister(nvram_handle);
9552 +
9553 + if (nvram_major >= 0)
9554 + devfs_unregister_chrdev(nvram_major, "nvram");
9555 +
9556 + if (nvram_mtd)
9557 + put_mtd_device(nvram_mtd);
9558 +
9559 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9560 + order++;
9561 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9562 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9563 + mem_map_unreserve(page);
9564 +
9565 + _nvram_exit();
9566 +}
9567 +
9568 +static int __init
9569 +dev_nvram_init(void)
9570 +{
9571 + int order = 0, ret = 0;
9572 + struct page *page, *end;
9573 + unsigned int i;
9574 +
9575 + /* Allocate and reserve memory to mmap() */
9576 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9577 + order++;
9578 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9579 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9580 + mem_map_reserve(page);
9581 +
9582 +#ifdef CONFIG_MTD
9583 + /* Find associated MTD device */
9584 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
9585 + nvram_mtd = get_mtd_device(NULL, i);
9586 + if (nvram_mtd) {
9587 + if (!strcmp(nvram_mtd->name, "nvram") &&
9588 + nvram_mtd->size >= NVRAM_SPACE)
9589 + break;
9590 + put_mtd_device(nvram_mtd);
9591 + }
9592 + }
9593 + if (i >= MAX_MTD_DEVICES)
9594 + nvram_mtd = NULL;
9595 +#endif
9596 +
9597 + /* Initialize hash table lock */
9598 + spin_lock_init(&nvram_lock);
9599 +
9600 + /* Initialize commit semaphore */
9601 + init_MUTEX(&nvram_sem);
9602 +
9603 + /* Register char device */
9604 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
9605 + ret = nvram_major;
9606 + goto err;
9607 + }
9608 +
9609 + /* Initialize hash table */
9610 + _nvram_init(sbh);
9611 +
9612 + /* Create /dev/nvram handle */
9613 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
9614 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
9615 +
9616 + /* Set the SDRAM NCDL value into NVRAM if not already done */
9617 + if (getintvar(NULL, "sdram_ncdl") == 0) {
9618 + unsigned int ncdl;
9619 + char buf[] = "0x00000000";
9620 +
9621 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
9622 + sprintf(buf, "0x%08x", ncdl);
9623 + nvram_set("sdram_ncdl", buf);
9624 + nvram_commit();
9625 + }
9626 + }
9627 +
9628 + return 0;
9629 +
9630 + err:
9631 + dev_nvram_exit();
9632 + return ret;
9633 +}
9634 +
9635 +module_init(dev_nvram_init);
9636 +module_exit(dev_nvram_exit);
9637 diff -urN linux.old/arch/mips/bcm947xx/pcibios.c linux.dev/arch/mips/bcm947xx/pcibios.c
9638 --- linux.old/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
9639 +++ linux.dev/arch/mips/bcm947xx/pcibios.c 2006-10-02 21:22:56.000000000 +0200
9640 @@ -0,0 +1,380 @@
9641 +/*
9642 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
9643 + *
9644 + * Copyright 2006, Broadcom Corporation
9645 + * All Rights Reserved.
9646 + *
9647 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9648 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9649 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9650 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9651 + *
9652 + * $Id: pcibios.c,v 1.1.1.9 2006/02/27 03:42:55 honor Exp $
9653 + */
9654 +
9655 +#include <linux/config.h>
9656 +#include <linux/types.h>
9657 +#include <linux/kernel.h>
9658 +#include <linux/sched.h>
9659 +#include <linux/pci.h>
9660 +#include <linux/init.h>
9661 +#include <linux/delay.h>
9662 +#include <asm/io.h>
9663 +#include <asm/irq.h>
9664 +#include <asm/paccess.h>
9665 +
9666 +#include <typedefs.h>
9667 +#include <osl.h>
9668 +#include <bcmutils.h>
9669 +#include <sbconfig.h>
9670 +#include <sbutils.h>
9671 +#include <hndpci.h>
9672 +#include <pcicfg.h>
9673 +#include <bcmdevs.h>
9674 +#include <bcmnvram.h>
9675 +
9676 +/* Global SB handle */
9677 +extern sb_t *bcm947xx_sbh;
9678 +extern spinlock_t bcm947xx_sbh_lock;
9679 +
9680 +/* Convenience */
9681 +#define sbh bcm947xx_sbh
9682 +#define sbh_lock bcm947xx_sbh_lock
9683 +
9684 +static int
9685 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
9686 +{
9687 + unsigned long flags;
9688 + int ret;
9689 +
9690 + spin_lock_irqsave(&sbh_lock, flags);
9691 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9692 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9693 + spin_unlock_irqrestore(&sbh_lock, flags);
9694 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9695 +}
9696 +
9697 +static int
9698 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
9699 +{
9700 + unsigned long flags;
9701 + int ret;
9702 +
9703 + spin_lock_irqsave(&sbh_lock, flags);
9704 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9705 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9706 + spin_unlock_irqrestore(&sbh_lock, flags);
9707 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9708 +}
9709 +
9710 +static int
9711 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
9712 +{
9713 + unsigned long flags;
9714 + int ret;
9715 +
9716 + spin_lock_irqsave(&sbh_lock, flags);
9717 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9718 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9719 + spin_unlock_irqrestore(&sbh_lock, flags);
9720 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9721 +}
9722 +
9723 +static int
9724 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
9725 +{
9726 + unsigned long flags;
9727 + int ret;
9728 +
9729 + spin_lock_irqsave(&sbh_lock, flags);
9730 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9731 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9732 + spin_unlock_irqrestore(&sbh_lock, flags);
9733 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9734 +}
9735 +
9736 +static int
9737 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
9738 +{
9739 + unsigned long flags;
9740 + int ret;
9741 +
9742 + spin_lock_irqsave(&sbh_lock, flags);
9743 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9744 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9745 + spin_unlock_irqrestore(&sbh_lock, flags);
9746 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9747 +}
9748 +
9749 +static int
9750 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
9751 +{
9752 + unsigned long flags;
9753 + int ret;
9754 +
9755 + spin_lock_irqsave(&sbh_lock, flags);
9756 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9757 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9758 + spin_unlock_irqrestore(&sbh_lock, flags);
9759 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9760 +}
9761 +
9762 +static struct pci_ops pcibios_ops = {
9763 + sbpci_read_config_byte,
9764 + sbpci_read_config_word,
9765 + sbpci_read_config_dword,
9766 + sbpci_write_config_byte,
9767 + sbpci_write_config_word,
9768 + sbpci_write_config_dword
9769 +};
9770 +
9771 +
9772 +void __init
9773 +pcibios_init(void)
9774 +{
9775 + ulong flags;
9776 +
9777 + if (!(sbh = sb_kattach()))
9778 + panic("sb_kattach failed");
9779 + spin_lock_init(&sbh_lock);
9780 +
9781 + spin_lock_irqsave(&sbh_lock, flags);
9782 + sbpci_init(sbh);
9783 + spin_unlock_irqrestore(&sbh_lock, flags);
9784 +
9785 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
9786 +
9787 + /* Scan the SB bus */
9788 + pci_scan_bus(0, &pcibios_ops, NULL);
9789 +
9790 +}
9791 +
9792 +char * __init
9793 +pcibios_setup(char *str)
9794 +{
9795 + if (!strncmp(str, "ban=", 4)) {
9796 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
9797 + return NULL;
9798 + }
9799 +
9800 + return (str);
9801 +}
9802 +
9803 +static u32 pci_iobase = 0x100;
9804 +static u32 pci_membase = SB_PCI_DMA;
9805 +
9806 +void __init
9807 +pcibios_fixup_bus(struct pci_bus *b)
9808 +{
9809 + struct list_head *ln;
9810 + struct pci_dev *d;
9811 + struct resource *res;
9812 + int pos, size;
9813 + u32 *base;
9814 + u8 irq;
9815 +
9816 + printk("PCI: Fixing up bus %d\n", b->number);
9817 +
9818 + /* Fix up SB */
9819 + if (b->number == 0) {
9820 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9821 + d = pci_dev_b(ln);
9822 + /* Fix up interrupt lines */
9823 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
9824 + d->irq = irq + 2;
9825 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9826 + }
9827 + }
9828 +
9829 + /* Fix up external PCI */
9830 + else {
9831 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9832 + d = pci_dev_b(ln);
9833 + /* Fix up resource bases */
9834 + for (pos = 0; pos < 6; pos++) {
9835 + res = &d->resource[pos];
9836 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
9837 + if (res->end) {
9838 + size = res->end - res->start + 1;
9839 + if (*base & (size - 1))
9840 + *base = (*base + size) & ~(size - 1);
9841 + res->start = *base;
9842 + res->end = res->start + size - 1;
9843 + *base += size;
9844 + pci_write_config_dword(d,
9845 + PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
9846 + }
9847 + /* Fix up PCI bridge BAR0 only */
9848 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
9849 + break;
9850 + }
9851 + /* Fix up interrupt lines */
9852 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
9853 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
9854 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9855 + }
9856 + }
9857 +}
9858 +
9859 +unsigned int
9860 +pcibios_assign_all_busses(void)
9861 +{
9862 + return 1;
9863 +}
9864 +
9865 +void
9866 +pcibios_align_resource(void *data, struct resource *res,
9867 + unsigned long size, unsigned long align)
9868 +{
9869 +}
9870 +
9871 +int
9872 +pcibios_enable_resources(struct pci_dev *dev)
9873 +{
9874 + u16 cmd, old_cmd;
9875 + int idx;
9876 + struct resource *r;
9877 +
9878 + /* External PCI only */
9879 + if (dev->bus->number == 0)
9880 + return 0;
9881 +
9882 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
9883 + old_cmd = cmd;
9884 + for (idx = 0; idx < 6; idx++) {
9885 + r = &dev->resource[idx];
9886 + if (r->flags & IORESOURCE_IO)
9887 + cmd |= PCI_COMMAND_IO;
9888 + if (r->flags & IORESOURCE_MEM)
9889 + cmd |= PCI_COMMAND_MEMORY;
9890 + }
9891 + if (dev->resource[PCI_ROM_RESOURCE].start)
9892 + cmd |= PCI_COMMAND_MEMORY;
9893 + if (cmd != old_cmd) {
9894 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
9895 + pci_write_config_word(dev, PCI_COMMAND, cmd);
9896 + }
9897 + return 0;
9898 +}
9899 +
9900 +int
9901 +pcibios_enable_device(struct pci_dev *dev, int mask)
9902 +{
9903 + ulong flags;
9904 + uint coreidx;
9905 + void *regs;
9906 +
9907 + /* External PCI device enable */
9908 + if (dev->bus->number != 0)
9909 + return pcibios_enable_resources(dev);
9910 +
9911 + /* These cores come out of reset enabled */
9912 + if (dev->device == SB_MIPS ||
9913 + dev->device == SB_MIPS33 ||
9914 + dev->device == SB_EXTIF ||
9915 + dev->device == SB_CC)
9916 + return 0;
9917 +
9918 + spin_lock_irqsave(&sbh_lock, flags);
9919 + coreidx = sb_coreidx(sbh);
9920 + regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
9921 + if (!regs)
9922 + return PCIBIOS_DEVICE_NOT_FOUND;
9923 +
9924 + /*
9925 + * The USB core requires a special bit to be set during core
9926 + * reset to enable host (OHCI) mode. Resetting the SB core in
9927 + * pcibios_enable_device() is a hack for compatibility with
9928 + * vanilla usb-ohci so that it does not have to know about
9929 + * SB. A driver that wants to use the USB core in device mode
9930 + * should know about SB and should reset the bit back to 0
9931 + * after calling pcibios_enable_device().
9932 + */
9933 + if (sb_coreid(sbh) == SB_USB) {
9934 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
9935 + sb_core_reset(sbh, 1 << 29, 0);
9936 + }
9937 + /*
9938 + * USB 2.0 special considerations:
9939 + *
9940 + * 1. Since the core supports both OHCI and EHCI functions, it must
9941 + * only be reset once.
9942 + *
9943 + * 2. In addition to the standard SB reset sequence, the Host Control
9944 + * Register must be programmed to bring the USB core and various
9945 + * phy components out of reset.
9946 + */
9947 + else if (sb_coreid(sbh) == SB_USB20H) {
9948 + if (!sb_iscoreup(sbh)) {
9949 + sb_core_reset(sbh, 0, 0);
9950 + writel(0x7FF, (ulong)regs + 0x200);
9951 + udelay(1);
9952 + }
9953 + } else
9954 + sb_core_reset(sbh, 0, 0);
9955 +
9956 + sb_setcoreidx(sbh, coreidx);
9957 + spin_unlock_irqrestore(&sbh_lock, flags);
9958 +
9959 + return 0;
9960 +}
9961 +
9962 +void
9963 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
9964 + struct resource *res, int resource)
9965 +{
9966 + unsigned long where, size;
9967 + u32 reg;
9968 +
9969 + /* External PCI only */
9970 + if (dev->bus->number == 0)
9971 + return;
9972 +
9973 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
9974 + size = res->end - res->start;
9975 + pci_read_config_dword(dev, where, &reg);
9976 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
9977 + pci_write_config_dword(dev, where, reg);
9978 +}
9979 +
9980 +static void __init
9981 +quirk_sbpci_bridge(struct pci_dev *dev)
9982 +{
9983 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
9984 + return;
9985 +
9986 + printk("PCI: Fixing up bridge\n");
9987 +
9988 + /* Enable PCI bridge bus mastering and memory space */
9989 + pci_set_master(dev);
9990 + pcibios_enable_resources(dev);
9991 +
9992 + /* Enable PCI bridge BAR1 prefetch and burst */
9993 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
9994 +}
9995 +
9996 +struct pci_fixup pcibios_fixups[] = {
9997 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
9998 + { 0 }
9999 +};
10000 +
10001 +/*
10002 + * If we set up a device for bus mastering, we need to check the latency
10003 + * timer as certain crappy BIOSes forget to set it properly.
10004 + */
10005 +unsigned int pcibios_max_latency = 255;
10006 +
10007 +void pcibios_set_master(struct pci_dev *dev)
10008 +{
10009 + u8 lat;
10010 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
10011 + if (lat < 16)
10012 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
10013 + else if (lat > pcibios_max_latency)
10014 + lat = pcibios_max_latency;
10015 + else
10016 + return;
10017 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
10018 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
10019 +}
10020 +
10021 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
10022 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
10023 +++ linux.dev/arch/mips/bcm947xx/prom.c 2006-10-02 21:19:59.000000000 +0200
10024 @@ -0,0 +1,41 @@
10025 +/*
10026 + * Early initialization code for BCM94710 boards
10027 + *
10028 + * Copyright 2004, Broadcom Corporation
10029 + * All Rights Reserved.
10030 + *
10031 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10032 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10033 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10034 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10035 + *
10036 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
10037 + */
10038 +
10039 +#include <linux/config.h>
10040 +#include <linux/init.h>
10041 +#include <linux/kernel.h>
10042 +#include <linux/types.h>
10043 +#include <asm/bootinfo.h>
10044 +
10045 +void __init
10046 +prom_init(int argc, const char **argv)
10047 +{
10048 + unsigned long mem;
10049 +
10050 + mips_machgroup = MACH_GROUP_BRCM;
10051 + mips_machtype = MACH_BCM947XX;
10052 +
10053 + /* Figure out memory size by finding aliases */
10054 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
10055 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
10056 + *(unsigned long *)(prom_init))
10057 + break;
10058 + }
10059 + add_memory_region(0, mem, BOOT_MEM_RAM);
10060 +}
10061 +
10062 +void __init
10063 +prom_free_prom_memory(void)
10064 +{
10065 +}
10066 diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
10067 --- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
10068 +++ linux.dev/arch/mips/bcm947xx/sbmips.c 2006-10-02 21:19:59.000000000 +0200
10069 @@ -0,0 +1,1132 @@
10070 +/*
10071 + * BCM47XX Sonics SiliconBackplane MIPS core routines
10072 + *
10073 + * Copyright 2006, Broadcom Corporation
10074 + * All Rights Reserved.
10075 + *
10076 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10077 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10078 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10079 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10080 + *
10081 + * $Id: hndmips.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
10082 + */
10083 +
10084 +#include <typedefs.h>
10085 +#include <bcmdefs.h>
10086 +#include <osl.h>
10087 +#include <bcmutils.h>
10088 +#include <sbutils.h>
10089 +#include <bcmdevs.h>
10090 +#include <bcmnvram.h>
10091 +#include <sbconfig.h>
10092 +#include <sbextif.h>
10093 +#include <sbchipc.h>
10094 +#include <sbmemc.h>
10095 +#include <mipsinc.h>
10096 +#include <sbhndmips.h>
10097 +#include <hndcpu.h>
10098 +
10099 +/* sbipsflag register format, indexed by irq. */
10100 +static const uint32 sbips_int_mask[] = {
10101 + 0, /* placeholder */
10102 + SBIPS_INT1_MASK,
10103 + SBIPS_INT2_MASK,
10104 + SBIPS_INT3_MASK,
10105 + SBIPS_INT4_MASK
10106 +};
10107 +
10108 +static const uint32 sbips_int_shift[] = {
10109 + 0, /* placeholder */
10110 + SBIPS_INT1_SHIFT,
10111 + SBIPS_INT2_SHIFT,
10112 + SBIPS_INT3_SHIFT,
10113 + SBIPS_INT4_SHIFT
10114 +};
10115 +
10116 +/*
10117 + * Map SB cores sharing the MIPS hardware IRQ0 to virtual dedicated OS IRQs.
10118 + * Per-port BSP code is required to provide necessary translations between
10119 + * the shared MIPS IRQ and the virtual OS IRQs based on SB core flag.
10120 + *
10121 + * See sb_irq() for the mapping.
10122 + */
10123 +static uint shirq_map_base = 0;
10124 +
10125 +/* Returns the SB interrupt flag of the current core. */
10126 +static uint32
10127 +sb_getflag(sb_t *sbh)
10128 +{
10129 + osl_t *osh;
10130 + void *regs;
10131 + sbconfig_t *sb;
10132 +
10133 + osh = sb_osh(sbh);
10134 + regs = sb_coreregs(sbh);
10135 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10136 +
10137 + return (R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK);
10138 +}
10139 +
10140 +/*
10141 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
10142 + * 0 is returned.
10143 + */
10144 +uint
10145 +sb_irq(sb_t *sbh)
10146 +{
10147 + osl_t *osh;
10148 + uint idx;
10149 + void *regs;
10150 + sbconfig_t *sb;
10151 + uint32 flag, sbipsflag;
10152 + uint irq = 0;
10153 +
10154 + osh = sb_osh(sbh);
10155 + flag = sb_getflag(sbh);
10156 +
10157 + idx = sb_coreidx(sbh);
10158 +
10159 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
10160 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
10161 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10162 +
10163 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
10164 + sbipsflag = R_REG(osh, &sb->sbipsflag);
10165 + for (irq = 1; irq <= 4; irq++) {
10166 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
10167 + break;
10168 + }
10169 + if (irq == 5)
10170 + irq = 0;
10171 + }
10172 +
10173 + sb_setcoreidx(sbh, idx);
10174 +
10175 + return irq;
10176 +}
10177 +
10178 +/* Clears the specified MIPS IRQ. */
10179 +static void
10180 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
10181 +{
10182 + osl_t *osh;
10183 + void *regs;
10184 + sbconfig_t *sb;
10185 +
10186 + osh = sb_osh(sbh);
10187 +
10188 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10189 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10190 + ASSERT(regs);
10191 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10192 +
10193 + if (irq == 0)
10194 + W_REG(osh, &sb->sbintvec, 0);
10195 + else
10196 + OR_REG(osh, &sb->sbipsflag, sbips_int_mask[irq]);
10197 +}
10198 +
10199 +/*
10200 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
10201 + * IRQ 0 may be assigned more than once.
10202 + *
10203 + * The old assignment to the specified core is removed first.
10204 + */
10205 +static void
10206 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
10207 +{
10208 + osl_t *osh;
10209 + void *regs;
10210 + sbconfig_t *sb;
10211 + uint32 flag;
10212 + uint oldirq;
10213 +
10214 + osh = sb_osh(sbh);
10215 +
10216 + regs = sb_setcore(sbh, coreid, coreunit);
10217 + ASSERT(regs);
10218 + flag = sb_getflag(sbh);
10219 + oldirq = sb_irq(sbh);
10220 + if (oldirq)
10221 + sb_clearirq(sbh, oldirq);
10222 +
10223 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10224 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10225 + ASSERT(regs);
10226 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10227 +
10228 + if (!oldirq)
10229 + AND_REG(osh, &sb->sbintvec, ~(1 << flag));
10230 +
10231 + if (irq == 0)
10232 + OR_REG(osh, &sb->sbintvec, 1 << flag);
10233 + else {
10234 + flag <<= sbips_int_shift[irq];
10235 + ASSERT(!(flag & ~sbips_int_mask[irq]));
10236 + flag |= R_REG(osh, &sb->sbipsflag) & ~sbips_int_mask[irq];
10237 + W_REG(osh, &sb->sbipsflag, flag);
10238 + }
10239 +}
10240 +
10241 +/*
10242 + * Initializes clocks and interrupts. SB and NVRAM access must be
10243 + * initialized prior to calling.
10244 + *
10245 + * 'shirqmap' enables virtual dedicated OS IRQ mapping if non-zero.
10246 + */
10247 +void
10248 +BCMINITFN(sb_mips_init)(sb_t *sbh, uint shirqmap)
10249 +{
10250 + osl_t *osh;
10251 + ulong hz, ns, tmp;
10252 + extifregs_t *eir;
10253 + chipcregs_t *cc;
10254 + char *value;
10255 + uint irq;
10256 +
10257 + osh = sb_osh(sbh);
10258 +
10259 + /* Figure out current SB clock speed */
10260 + if ((hz = sb_clock(sbh)) == 0)
10261 + hz = 100000000;
10262 + ns = 1000000000 / hz;
10263 +
10264 + /* Setup external interface timing */
10265 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
10266 + /* Initialize extif so we can get to the LEDs and external UART */
10267 + W_REG(osh, &eir->prog_config, CF_EN);
10268 +
10269 + /* Set timing for the flash */
10270 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10271 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
10272 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10273 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10274 +
10275 + /* Set programmable interface timing for external uart */
10276 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10277 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
10278 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
10279 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10280 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10281 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
10282 + /* Set timing for the flash */
10283 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10284 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
10285 + tmp |= CEIL(120, ns); /* W0 = 120nS */
10286 + if ((sb_corerev(sbh) < 9) ||
10287 + (BCMINIT(sb_chip)(sbh) == 0x5365))
10288 + W_REG(osh, &cc->flash_waitcount, tmp);
10289 +
10290 + if ((sb_corerev(sbh) < 9) ||
10291 + ((sb_chip(sbh) == BCM5350_CHIP_ID) && sb_chiprev(sbh) == 0) ||
10292 + (BCMINIT(sb_chip)(sbh) == 0x5365)) {
10293 + W_REG(osh, &cc->pcmcia_memwait, tmp);
10294 + }
10295 +
10296 + /* Save shared IRQ mapping base */
10297 + shirq_map_base = shirqmap;
10298 + }
10299 +
10300 + /* Chip specific initialization */
10301 + switch (sb_chip(sbh)) {
10302 + case BCM4710_CHIP_ID:
10303 + /* Clear interrupt map */
10304 + for (irq = 0; irq <= 4; irq++)
10305 + sb_clearirq(sbh, irq);
10306 + sb_setirq(sbh, 0, SB_CODEC, 0);
10307 + sb_setirq(sbh, 0, SB_EXTIF, 0);
10308 + sb_setirq(sbh, 2, SB_ENET, 1);
10309 + sb_setirq(sbh, 3, SB_ILINE20, 0);
10310 + sb_setirq(sbh, 4, SB_PCI, 0);
10311 + ASSERT(eir);
10312 + value = nvram_get("et0phyaddr");
10313 + if (value && !strcmp(value, "31")) {
10314 + /* Enable internal UART */
10315 + W_REG(osh, &eir->corecontrol, CC_UE);
10316 + /* Give USB its own interrupt */
10317 + sb_setirq(sbh, 1, SB_USB, 0);
10318 + } else {
10319 + /* Disable internal UART */
10320 + W_REG(osh, &eir->corecontrol, 0);
10321 + /* Give Ethernet its own interrupt */
10322 + sb_setirq(sbh, 1, SB_ENET, 0);
10323 + sb_setirq(sbh, 0, SB_USB, 0);
10324 + }
10325 + break;
10326 + case BCM5350_CHIP_ID:
10327 + /* Clear interrupt map */
10328 + for (irq = 0; irq <= 4; irq++)
10329 + sb_clearirq(sbh, irq);
10330 + sb_setirq(sbh, 0, SB_CC, 0);
10331 + sb_setirq(sbh, 0, SB_MIPS33, 0);
10332 + sb_setirq(sbh, 1, SB_D11, 0);
10333 + sb_setirq(sbh, 2, SB_ENET, 0);
10334 + sb_setirq(sbh, 3, SB_PCI, 0);
10335 + sb_setirq(sbh, 4, SB_USB, 0);
10336 + break;
10337 + case BCM4785_CHIP_ID:
10338 + /* Reassign PCI to irq 4 */
10339 + sb_setirq(sbh, 4, SB_PCI, 0);
10340 + break;
10341 + }
10342 +}
10343 +
10344 +uint32
10345 +BCMINITFN(sb_cpu_clock)(sb_t *sbh)
10346 +{
10347 + extifregs_t *eir;
10348 + chipcregs_t *cc;
10349 + uint32 n, m;
10350 + uint idx;
10351 + uint32 pll_type, rate = 0;
10352 +
10353 + /* get index of the current core */
10354 + idx = sb_coreidx(sbh);
10355 + pll_type = PLL_TYPE1;
10356 +
10357 + /* switch to extif or chipc core */
10358 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10359 + n = R_REG(osh, &eir->clockcontrol_n);
10360 + m = R_REG(osh, &eir->clockcontrol_sb);
10361 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10362 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10363 + n = R_REG(osh, &cc->clockcontrol_n);
10364 + if ((pll_type == PLL_TYPE2) ||
10365 + (pll_type == PLL_TYPE4) ||
10366 + (pll_type == PLL_TYPE6) ||
10367 + (pll_type == PLL_TYPE7))
10368 + m = R_REG(osh, &cc->clockcontrol_m3);
10369 + else if (pll_type == PLL_TYPE5) {
10370 + rate = 200000000;
10371 + goto out;
10372 + }
10373 + else if (pll_type == PLL_TYPE3) {
10374 + if (sb_chip(sbh) == BCM5365_CHIP_ID) {
10375 + rate = 200000000;
10376 + goto out;
10377 + }
10378 + /* 5350 uses m2 to control mips */
10379 + else
10380 + m = R_REG(osh, &cc->clockcontrol_m2);
10381 + } else
10382 + m = R_REG(osh, &cc->clockcontrol_sb);
10383 + } else
10384 + goto out;
10385 +
10386 +
10387 + /* calculate rate */
10388 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
10389 + rate = 100000000;
10390 + else
10391 + rate = sb_clock_rate(pll_type, n, m);
10392 +
10393 + if (pll_type == PLL_TYPE6)
10394 + rate = SB2MIPS_T6(rate);
10395 +
10396 +out:
10397 + /* switch back to previous core */
10398 + sb_setcoreidx(sbh, idx);
10399 +
10400 + return rate;
10401 +}
10402 +
10403 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
10404 +
10405 +static void
10406 +BCMINITFN(handler)(void)
10407 +{
10408 + __asm__(
10409 + ".set\tmips32\n\t"
10410 + "ssnop\n\t"
10411 + "ssnop\n\t"
10412 + /* Disable interrupts */
10413 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
10414 + "mfc0 $15, $12\n\t"
10415 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
10416 + "li $14, -31746\n\t"
10417 + "and $15, $15, $14\n\t"
10418 + "mtc0 $15, $12\n\t"
10419 + "eret\n\t"
10420 + "nop\n\t"
10421 + "nop\n\t"
10422 + ".set\tmips0");
10423 +}
10424 +
10425 +/* The following MUST come right after handler() */
10426 +static void
10427 +BCMINITFN(afterhandler)(void)
10428 +{
10429 +}
10430 +
10431 +/*
10432 + * Set the MIPS, backplane and PCI clocks as closely as possible.
10433 + *
10434 + * MIPS clocks synchronization function has been moved from PLL in chipcommon
10435 + * core rev. 15 to a DLL inside the MIPS core in 4785.
10436 + */
10437 +bool
10438 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
10439 +{
10440 + extifregs_t *eir = NULL;
10441 + chipcregs_t *cc = NULL;
10442 + mipsregs_t *mipsr = NULL;
10443 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
10444 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
10445 + uint32 pll_type, sync_mode;
10446 + uint ic_size, ic_lsize;
10447 + uint idx, i;
10448 +
10449 + /* PLL configuration: type 1 */
10450 + typedef struct {
10451 + uint32 mipsclock;
10452 + uint16 n;
10453 + uint32 sb;
10454 + uint32 pci33;
10455 + uint32 pci25;
10456 + } n3m_table_t;
10457 + static n3m_table_t BCMINITDATA(type1_table)[] = {
10458 + /* 96.000 32.000 24.000 */
10459 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 },
10460 + /* 100.000 33.333 25.000 */
10461 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 },
10462 + /* 104.000 31.200 24.960 */
10463 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 },
10464 + /* 108.000 32.400 24.923 */
10465 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 },
10466 + /* 112.000 32.000 24.889 */
10467 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 },
10468 + /* 115.200 32.000 24.000 */
10469 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 },
10470 + /* 120.000 30.000 24.000 */
10471 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 },
10472 + /* 124.800 31.200 24.960 */
10473 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 },
10474 + /* 128.000 32.000 24.000 */
10475 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 },
10476 + /* 132.000 33.000 24.750 */
10477 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 },
10478 + /* 136.000 32.640 24.727 */
10479 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 },
10480 + /* 140.000 30.000 24.706 */
10481 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 },
10482 + /* 144.000 30.857 24.686 */
10483 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 },
10484 + /* 150.857 33.000 24.000 */
10485 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 },
10486 + /* 152.000 32.571 24.000 */
10487 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 },
10488 + /* 156.000 31.200 24.960 */
10489 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 },
10490 + /* 160.000 32.000 24.000 */
10491 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 },
10492 + /* 163.200 32.640 24.727 */
10493 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 },
10494 + /* 168.000 32.000 24.889 */
10495 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 },
10496 + /* 176.000 33.000 24.000 */
10497 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 },
10498 + };
10499 +
10500 + /* PLL configuration: type 3 */
10501 + typedef struct {
10502 + uint32 mipsclock;
10503 + uint16 n;
10504 + uint32 m2; /* that is the clockcontrol_m2 */
10505 + } type3_table_t;
10506 + static type3_table_t type3_table[] = {
10507 + /* for 5350, mips clock is always double sb clock */
10508 + { 150000000, 0x311, 0x4020005 },
10509 + { 200000000, 0x311, 0x4020003 },
10510 + };
10511 +
10512 + /* PLL configuration: type 2, 4, 7 */
10513 + typedef struct {
10514 + uint32 mipsclock;
10515 + uint32 sbclock;
10516 + uint16 n;
10517 + uint32 sb;
10518 + uint32 pci33;
10519 + uint32 m2;
10520 + uint32 m3;
10521 + uint32 ratio_cfg;
10522 + uint32 ratio_parm;
10523 + uint32 d11_r1;
10524 + uint32 d11_r2;
10525 + } n4m_table_t;
10526 + static n4m_table_t BCMINITDATA(type2_table)[] = {
10527 + { 120000000, 60000000, 0x0303, 0x01000200, 0x01000600, 0x01000200, 0x05000200, 11,
10528 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10529 + { 150000000, 75000000, 0x0303, 0x01000100, 0x01000600, 0x01000100, 0x05000100, 11,
10530 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10531 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8,
10532 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10533 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11,
10534 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10535 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11,
10536 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10537 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10538 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10539 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10540 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10541 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10542 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10543 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8,
10544 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10545 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10546 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10547 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11,
10548 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10549 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11,
10550 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10551 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10552 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10553 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10554 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10555 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10556 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10557 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10558 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10559 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10560 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10561 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01010100, 0x05000100, 8,
10562 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10563 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01010100, 0x05000100, 11,
10564 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10565 + { 330000000, 132000000, 0x0903, 0x01000200, 0x00020200, 0x01010100, 0x05000100, 0,
10566 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10567 + { 330000000, 146666666, 0x0903, 0x01010000, 0x00020200, 0x01010100, 0x05000100, 0,
10568 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10569 + { 330000000, 165000000, 0x0903, 0x01000100, 0x00020200, 0x01010100, 0x05000100, 0,
10570 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10571 + { 360000000, 120000000, 0x0a03, 0x01000300, 0x00010201, 0x01010200, 0x05000100, 0,
10572 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10573 + { 360000000, 144000000, 0x0a03, 0x01000200, 0x00010201, 0x01010200, 0x05000100, 0,
10574 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10575 + { 360000000, 160000000, 0x0a03, 0x01010000, 0x00010201, 0x01010200, 0x05000100, 0,
10576 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10577 + { 360000000, 180000000, 0x0a03, 0x01000100, 0x00010201, 0x01010200, 0x05000100, 0,
10578 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10579 + { 390000000, 130000000, 0x0b03, 0x01010100, 0x00020101, 0x01020100, 0x05000100, 0,
10580 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10581 + { 390000000, 156000000, 0x0b03, 0x01000200, 0x00020101, 0x01020100, 0x05000100, 0,
10582 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10583 + { 390000000, 173000000, 0x0b03, 0x01010000, 0x00020101, 0x01020100, 0x05000100, 0,
10584 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10585 + { 390000000, 195000000, 0x0b03, 0x01000100, 0x00020101, 0x01020100, 0x05000100, 0,
10586 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10587 + };
10588 + static n4m_table_t BCMINITDATA(type4_table)[] = {
10589 + { 120000000, 60000000, 0x0009, 0x11020009, 0x01030203, 0x11020009, 0x04000009, 11,
10590 + 0x0aaa0555 },
10591 + { 150000000, 75000000, 0x0009, 0x11050002, 0x01030203, 0x11050002, 0x04000005, 11,
10592 + 0x0aaa0555 },
10593 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10594 + 0x0aaa0555 },
10595 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11,
10596 + 0x0aaa0555 },
10597 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10598 + 0x0aaa0555 },
10599 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10600 + 0x0aaa0555 },
10601 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11,
10602 + 0x0aaa0555 },
10603 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10604 + 0x0aaa0555 },
10605 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10606 + 0x0aaa0555 },
10607 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11,
10608 + 0x0aaa0555 },
10609 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8,
10610 + 0x012a00a9 },
10611 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10612 + 0x0aaa0555 },
10613 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13,
10614 + 0x254a14a9 },
10615 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11,
10616 + 0x0aaa0555 },
10617 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9,
10618 + 0x02520129 },
10619 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10620 + 0x0aaa0555 },
10621 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10622 + 0x0aaa0555 },
10623 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13,
10624 + 0x254a14a9 },
10625 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10626 + 0x254a14a9 },
10627 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10628 + 0x254a14a9 },
10629 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9,
10630 + 0x02520129 },
10631 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11,
10632 + 0x0aaa0555 }
10633 + };
10634 + static n4m_table_t BCMINITDATA(type7_table)[] = {
10635 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10636 + 0x0aaa0555 },
10637 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10638 + 0x0aaa0555 },
10639 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10640 + 0x0aaa0555 },
10641 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11,
10642 + 0x0aaa0555 },
10643 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10644 + 0x0aaa0555 },
10645 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10646 + 0x0aaa0555 },
10647 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10648 + 0x0aaa0555 },
10649 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11,
10650 + 0x0aaa0555 },
10651 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10652 + 0x0aaa0555 },
10653 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10654 + 0x0aaa0555 },
10655 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10656 + 0x0aaa0555 },
10657 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10658 + 0x0aaa0555 },
10659 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11,
10660 + 0x0aaa0555 },
10661 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11,
10662 + 0x0aaa0555 }
10663 + };
10664 +
10665 + ulong start, end, dst;
10666 + bool ret = FALSE;
10667 +
10668 + volatile uint32 *dll_ctrl = (volatile uint32 *)0xff400008;
10669 + volatile uint32 *dll_r1 = (volatile uint32 *)0xff400010;
10670 + volatile uint32 *dll_r2 = (volatile uint32 *)0xff400018;
10671 +
10672 + /* get index of the current core */
10673 + idx = sb_coreidx(sbh);
10674 + clockcontrol_m2 = NULL;
10675 +
10676 + /* switch to extif or chipc core */
10677 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10678 + pll_type = PLL_TYPE1;
10679 + clockcontrol_n = &eir->clockcontrol_n;
10680 + clockcontrol_sb = &eir->clockcontrol_sb;
10681 + clockcontrol_pci = &eir->clockcontrol_pci;
10682 + clockcontrol_m2 = &cc->clockcontrol_m2;
10683 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10684 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10685 + if (pll_type == PLL_TYPE6) {
10686 + clockcontrol_n = NULL;
10687 + clockcontrol_sb = NULL;
10688 + clockcontrol_pci = NULL;
10689 + } else {
10690 + clockcontrol_n = &cc->clockcontrol_n;
10691 + clockcontrol_sb = &cc->clockcontrol_sb;
10692 + clockcontrol_pci = &cc->clockcontrol_pci;
10693 + clockcontrol_m2 = &cc->clockcontrol_m2;
10694 + }
10695 + } else
10696 + goto done;
10697 +
10698 + if (pll_type == PLL_TYPE6) {
10699 + /* Silence compilers */
10700 + orig_n = orig_sb = orig_pci = 0;
10701 + } else {
10702 + /* Store the current clock register values */
10703 + orig_n = R_REG(osh, clockcontrol_n);
10704 + orig_sb = R_REG(osh, clockcontrol_sb);
10705 + orig_pci = R_REG(osh, clockcontrol_pci);
10706 + }
10707 +
10708 + if (pll_type == PLL_TYPE1) {
10709 + /* Keep the current PCI clock if not specified */
10710 + if (pciclock == 0) {
10711 + pciclock = sb_clock_rate(pll_type, R_REG(osh, clockcontrol_n),
10712 + R_REG(osh, clockcontrol_pci));
10713 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
10714 + }
10715 +
10716 + /* Search for the closest MIPS clock less than or equal to a preferred value */
10717 + for (i = 0; i < ARRAYSIZE(type1_table); i++) {
10718 + ASSERT(type1_table[i].mipsclock ==
10719 + sb_clock_rate(pll_type, type1_table[i].n,
10720 + type1_table[i].sb));
10721 + if (type1_table[i].mipsclock > mipsclock)
10722 + break;
10723 + }
10724 + if (i == 0) {
10725 + ret = FALSE;
10726 + goto done;
10727 + } else {
10728 + ret = TRUE;
10729 + i--;
10730 + }
10731 + ASSERT(type1_table[i].mipsclock <= mipsclock);
10732 +
10733 + /* No PLL change */
10734 + if ((orig_n == type1_table[i].n) &&
10735 + (orig_sb == type1_table[i].sb) &&
10736 + (orig_pci == type1_table[i].pci33))
10737 + goto done;
10738 +
10739 + /* Set the PLL controls */
10740 + W_REG(osh, clockcontrol_n, type1_table[i].n);
10741 + W_REG(osh, clockcontrol_sb, type1_table[i].sb);
10742 + if (pciclock == 25000000)
10743 + W_REG(osh, clockcontrol_pci, type1_table[i].pci25);
10744 + else
10745 + W_REG(osh, clockcontrol_pci, type1_table[i].pci33);
10746 +
10747 + /* Reset */
10748 + sb_watchdog(sbh, 1);
10749 + while (1);
10750 + } else if (pll_type == PLL_TYPE3) {
10751 + /* 5350 */
10752 + if (sb_chip(sbh) != BCM5365_CHIP_ID) {
10753 + /*
10754 + * Search for the closest MIPS clock less than or equal to
10755 + * a preferred value.
10756 + */
10757 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
10758 + if (type3_table[i].mipsclock > mipsclock)
10759 + break;
10760 + }
10761 + if (i == 0) {
10762 + ret = FALSE;
10763 + goto done;
10764 + } else {
10765 + ret = TRUE;
10766 + i--;
10767 + }
10768 + ASSERT(type3_table[i].mipsclock <= mipsclock);
10769 +
10770 + /* No PLL change */
10771 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10772 + if ((orig_n == type3_table[i].n) &&
10773 + (orig_m2 == type3_table[i].m2)) {
10774 + goto done;
10775 + }
10776 +
10777 + /* Set the PLL controls */
10778 + W_REG(osh, clockcontrol_n, type3_table[i].n);
10779 + W_REG(osh, clockcontrol_m2, type3_table[i].m2);
10780 +
10781 + /* Reset */
10782 + sb_watchdog(sbh, 1);
10783 + while (1);
10784 + }
10785 + } else if ((pll_type == PLL_TYPE2) ||
10786 + (pll_type == PLL_TYPE4) ||
10787 + (pll_type == PLL_TYPE6) ||
10788 + (pll_type == PLL_TYPE7)) {
10789 + n4m_table_t *table = NULL, *te;
10790 + uint tabsz = 0;
10791 +
10792 + ASSERT(cc);
10793 +
10794 + orig_mips = R_REG(osh, &cc->clockcontrol_m3);
10795 +
10796 + switch (pll_type) {
10797 + case PLL_TYPE6: {
10798 + uint32 new_mips = 0;
10799 +
10800 + ret = TRUE;
10801 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
10802 + new_mips = CC_T6_MMASK;
10803 +
10804 + if (orig_mips == new_mips)
10805 + goto done;
10806 +
10807 + W_REG(osh, &cc->clockcontrol_m3, new_mips);
10808 + goto end_fill;
10809 + }
10810 + case PLL_TYPE2:
10811 + table = type2_table;
10812 + tabsz = ARRAYSIZE(type2_table);
10813 + break;
10814 + case PLL_TYPE4:
10815 + table = type4_table;
10816 + tabsz = ARRAYSIZE(type4_table);
10817 + break;
10818 + case PLL_TYPE7:
10819 + table = type7_table;
10820 + tabsz = ARRAYSIZE(type7_table);
10821 + break;
10822 + default:
10823 + ASSERT("No table for plltype" == NULL);
10824 + break;
10825 + }
10826 +
10827 + /* Store the current clock register values */
10828 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10829 + orig_ratio_parm = 0;
10830 + orig_ratio_cfg = 0;
10831 +
10832 + /* Look up current ratio */
10833 + for (i = 0; i < tabsz; i++) {
10834 + if ((orig_n == table[i].n) &&
10835 + (orig_sb == table[i].sb) &&
10836 + (orig_pci == table[i].pci33) &&
10837 + (orig_m2 == table[i].m2) &&
10838 + (orig_mips == table[i].m3)) {
10839 + orig_ratio_parm = table[i].ratio_parm;
10840 + orig_ratio_cfg = table[i].ratio_cfg;
10841 + break;
10842 + }
10843 + }
10844 +
10845 + /* Search for the closest MIPS clock greater or equal to a preferred value */
10846 + for (i = 0; i < tabsz; i++) {
10847 + ASSERT(table[i].mipsclock ==
10848 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
10849 + if ((mipsclock <= table[i].mipsclock) &&
10850 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
10851 + break;
10852 + }
10853 + if (i == tabsz) {
10854 + ret = FALSE;
10855 + goto done;
10856 + } else {
10857 + te = &table[i];
10858 + ret = TRUE;
10859 + }
10860 +
10861 + /* No PLL change */
10862 + if ((orig_n == te->n) &&
10863 + (orig_sb == te->sb) &&
10864 + (orig_pci == te->pci33) &&
10865 + (orig_m2 == te->m2) &&
10866 + (orig_mips == te->m3))
10867 + goto done;
10868 +
10869 + /* Set the PLL controls */
10870 + W_REG(osh, clockcontrol_n, te->n);
10871 + W_REG(osh, clockcontrol_sb, te->sb);
10872 + W_REG(osh, clockcontrol_pci, te->pci33);
10873 + W_REG(osh, &cc->clockcontrol_m2, te->m2);
10874 + W_REG(osh, &cc->clockcontrol_m3, te->m3);
10875 +
10876 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
10877 + if ((pll_type == PLL_TYPE7) && (te->sb != te->m2) &&
10878 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
10879 + W_REG(osh, &cc->chipcontrol,
10880 + R_REG(osh, &cc->chipcontrol) | 0x100);
10881 +
10882 + /* No ratio change */
10883 + if (sb_chip(sbh) != BCM4785_CHIP_ID) {
10884 + if (orig_ratio_parm == te->ratio_parm)
10885 + goto end_fill;
10886 + }
10887 +
10888 + /* Preload the code into the cache */
10889 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
10890 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10891 + start = ((ulong) &&start_fill_4785) & ~(ic_lsize - 1);
10892 + end = ((ulong) &&end_fill_4785 + (ic_lsize - 1)) & ~(ic_lsize - 1);
10893 + }
10894 + else {
10895 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
10896 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
10897 + }
10898 + while (start < end) {
10899 + cache_op(start, Fill_I);
10900 + start += ic_lsize;
10901 + }
10902 +
10903 + /* Copy the handler */
10904 + start = (ulong) &handler;
10905 + end = (ulong) &afterhandler;
10906 + dst = KSEG1ADDR(0x180);
10907 + for (i = 0; i < (end - start); i += 4)
10908 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
10909 +
10910 + /* Preload the handler into the cache one line at a time */
10911 + for (i = 0; i < (end - start); i += ic_lsize)
10912 + cache_op(dst + i, Fill_I);
10913 +
10914 + /* Clear BEV bit */
10915 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
10916 +
10917 + /* Enable interrupts */
10918 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
10919 +
10920 + /* 4785 clock freq change procedures */
10921 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10922 + start_fill_4785:
10923 + /* Switch to async */
10924 + MTC0(C0_BROADCOM, 4, (1 << 22));
10925 +
10926 + /* Set clock ratio in MIPS */
10927 + *dll_r1 = (*dll_r1 & 0xfffffff0) | (te->d11_r1 - 1);
10928 + *dll_r2 = te->d11_r2;
10929 +
10930 + /* Enable new settings in MIPS */
10931 + *dll_r1 = *dll_r1 | 0xc0000000;
10932 +
10933 + /* Set active cfg */
10934 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) | (1 << 3) | 1);
10935 +
10936 + /* Fake soft reset (clock cfg registers not reset) */
10937 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
10938 +
10939 + /* Clear active cfg */
10940 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) & ~(1 << 3));
10941 +
10942 + /* set watchdog timer */
10943 + W_REG(osh, &cc->watchdog, 20);
10944 + (void) R_REG(osh, &cc->chipid);
10945 +
10946 + /* wait for timer interrupt */
10947 + __asm__ __volatile__(
10948 + ".set\tmips3\n\t"
10949 + "sync\n\t"
10950 + "wait\n\t"
10951 + ".set\tmips0");
10952 + end_fill_4785:
10953 + while (1);
10954 + }
10955 + /* Generic clock freq change procedures */
10956 + else {
10957 + /* Enable MIPS timer interrupt */
10958 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
10959 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
10960 + ASSERT(mipsr);
10961 + W_REG(osh, &mipsr->intmask, 1);
10962 +
10963 + start_fill:
10964 + /* step 1, set clock ratios */
10965 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
10966 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
10967 +
10968 + /* step 2: program timer intr */
10969 + W_REG(osh, &mipsr->timer, 100);
10970 + (void) R_REG(osh, &mipsr->timer);
10971 +
10972 + /* step 3, switch to async */
10973 + sync_mode = MFC0(C0_BROADCOM, 4);
10974 + MTC0(C0_BROADCOM, 4, 1 << 22);
10975 +
10976 + /* step 4, set cfg active */
10977 + MTC0(C0_BROADCOM, 2, (1 << 3) | 1);
10978 +
10979 + /* steps 5 & 6 */
10980 + __asm__ __volatile__(
10981 + ".set\tmips3\n\t"
10982 + "wait\n\t"
10983 + ".set\tmips0");
10984 +
10985 + /* step 7, clear cfg active */
10986 + MTC0(C0_BROADCOM, 2, 0);
10987 +
10988 + /* Additional Step: set back to orig sync mode */
10989 + MTC0(C0_BROADCOM, 4, sync_mode);
10990 +
10991 + /* step 8, fake soft reset */
10992 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
10993 +
10994 + end_fill:
10995 + /* set watchdog timer */
10996 + W_REG(osh, &cc->watchdog, 20);
10997 + (void) R_REG(osh, &cc->chipid);
10998 +
10999 + /* wait for timer interrupt */
11000 + __asm__ __volatile__(
11001 + ".set\tmips3\n\t"
11002 + "sync\n\t"
11003 + "wait\n\t"
11004 + ".set\tmips0");
11005 + while (1);
11006 + }
11007 + }
11008 +
11009 +done:
11010 + /* Enable 4785 DLL */
11011 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
11012 + uint32 tmp;
11013 +
11014 + /* set mask to 1e, enable DLL (bit 0) */
11015 + *dll_ctrl |= 0x0041e021;
11016 +
11017 + /* enable aggressive hardware mode */
11018 + *dll_ctrl |= 0x00000080;
11019 +
11020 + /* wait for lock flag to clear */
11021 + while ((*dll_ctrl & 0x2) == 0);
11022 +
11023 + /* clear sticky flags (clear on write 1) */
11024 + tmp = *dll_ctrl;
11025 + *dll_ctrl = tmp;
11026 +
11027 + /* set mask to 5b'10001 */
11028 + *dll_ctrl = (*dll_ctrl & 0xfffc1fff) | 0x00022000;
11029 +
11030 + /* enable sync mode */
11031 + MTC0(C0_BROADCOM, 4, MFC0(C0_BROADCOM, 4) & 0xfe3fffff);
11032 + (void)MFC0(C0_BROADCOM, 4);
11033 + }
11034 +
11035 + /* switch back to previous core */
11036 + sb_setcoreidx(sbh, idx);
11037 +
11038 + return ret;
11039 +}
11040 +
11041 +void
11042 +BCMINITFN(enable_pfc)(uint32 mode)
11043 +{
11044 + ulong start, end;
11045 + uint ic_size, ic_lsize;
11046 +
11047 + /* If auto then choose the correct mode for this
11048 + * platform, currently we only ever select one mode
11049 + */
11050 + if (mode == PFC_AUTO)
11051 + mode = PFC_INST;
11052 +
11053 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
11054 +
11055 + /* enable prefetch cache if available */
11056 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
11057 + start = ((ulong) &&setpfc_start) & ~(ic_lsize - 1);
11058 + end = ((ulong) &&setpfc_end + (ic_lsize - 1)) & ~(ic_lsize - 1);
11059 +
11060 + /* Preload setpfc code into the cache one line at a time */
11061 + while (start < end) {
11062 + cache_op(start, Fill_I);
11063 + start += ic_lsize;
11064 + }
11065 +
11066 + /* Now set the pfc */
11067 + setpfc_start:
11068 + /* write range */
11069 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
11070 +
11071 + /* enable */
11072 + *(volatile uint32 *)PFC_CR0 = mode;
11073 + setpfc_end:
11074 + /* Compiler foder */
11075 + ic_size = 0;
11076 + }
11077 +}
11078 +
11079 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
11080 +uint32
11081 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
11082 +{
11083 + osl_t *osh;
11084 + sbmemcregs_t *memc;
11085 + uint32 ret = 0;
11086 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
11087 + uint idx, rev;
11088 +
11089 + osh = sb_osh(sbh);
11090 +
11091 + idx = sb_coreidx(sbh);
11092 +
11093 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
11094 + if (memc == 0)
11095 + goto out;
11096 +
11097 + rev = sb_corerev(sbh);
11098 +
11099 + config = R_REG(osh, &memc->config);
11100 + wr = R_REG(osh, &memc->wrncdlcor);
11101 + rd = R_REG(osh, &memc->rdncdlcor);
11102 + misc = R_REG(osh, &memc->miscdlyctl);
11103 + dqsg = R_REG(osh, &memc->dqsgatencdl);
11104 +
11105 + rd &= MEMC_RDNCDLCOR_RD_MASK;
11106 + wr &= MEMC_WRNCDLCOR_WR_MASK;
11107 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
11108 +
11109 + if (config & MEMC_CONFIG_DDR) {
11110 + ret = (wr << 16) | (rd << 8) | dqsg;
11111 + } else {
11112 + if (rev > 0)
11113 + cd = rd;
11114 + else
11115 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
11116 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
11117 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
11118 + ret = (sm << 16) | (sd << 8) | cd;
11119 + }
11120 +
11121 +out:
11122 + /* switch back to previous core */
11123 + sb_setcoreidx(sbh, idx);
11124 +
11125 + return ret;
11126 +}
11127 +
11128 +#if defined(BCMPERFSTATS)
11129 +/*
11130 + * CP0 Register 25 supports 4 semi-independent 32bit performance counters.
11131 + * $25 select 0, 1, 2, and 3 are the counters. The counters *decrement* (who thought this one up?)
11132 + * $25 select 4 and 5 each contain 2-16bit control fields, one for each of the 4 counters
11133 + * $25 select 6 is the global perf control register.
11134 + */
11135 +/* enable and start instruction counting */
11136 +
11137 +void
11138 +hndmips_perf_instrcount_enable()
11139 +{
11140 + MTC0(C0_PERFORMANCE, 6, 0x80000200); /* global enable perf counters */
11141 + MTC0(C0_PERFORMANCE, 4,
11142 + 0x8044 | MFC0(C0_PERFORMANCE, 4)); /* enable instruction counting for counter 0 */
11143 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter zero */
11144 +}
11145 +
11146 +/* enable and start I$ hit and I$ miss counting */
11147 +void
11148 +hndmips_perf_icachecount_enable(void)
11149 +{
11150 + MTC0(C0_PERFORMANCE, 6, 0x80000218); /* enable I$ counting */
11151 + MTC0(C0_PERFORMANCE, 4, 0x80148018); /* count I$ hits in cntr 0 and misses in cntr 1 */
11152 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # I$ hits */
11153 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # I$ misses */
11154 +}
11155 +
11156 +/* enable and start D$ hit and I$ miss counting */
11157 +void
11158 +hndmips_perf_dcachecount_enable(void)
11159 +{
11160 + MTC0(C0_PERFORMANCE, 6, 0x80000211); /* enable D$ counting */
11161 + MTC0(C0_PERFORMANCE, 4, 0x80248028); /* count D$ hits in cntr 0 and misses in cntr 1 */
11162 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # D$ hits */
11163 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # D$ misses */
11164 +}
11165 +
11166 +void
11167 +hndmips_perf_icache_miss_enable()
11168 +{
11169 + MTC0(C0_PERFORMANCE, 4,
11170 + 0x80140000 | MFC0(C0_PERFORMANCE, 4)); /* enable cache misses counting for counter 1 */
11171 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter one */
11172 +}
11173 +
11174 +
11175 +void
11176 +hndmips_perf_icache_hit_enable()
11177 +{
11178 + MTC0(C0_PERFORMANCE, 5, 0x8018 | MFC0(C0_PERFORMANCE, 5));
11179 + /* enable cache hits counting for counter 2 */
11180 + MTC0(C0_PERFORMANCE, 2, 0); /* zero counter 2 */
11181 +}
11182 +
11183 +uint32
11184 +hndmips_perf_read_instrcount()
11185 +{
11186 + return -(long)(MFC0(C0_PERFORMANCE, 0));
11187 +}
11188 +
11189 +uint32
11190 +hndmips_perf_read_cache_miss()
11191 +{
11192 + return -(long)(MFC0(C0_PERFORMANCE, 1));
11193 +}
11194 +
11195 +uint32
11196 +hndmips_perf_read_cache_hit()
11197 +{
11198 + return -(long)(MFC0(C0_PERFORMANCE, 2));
11199 +}
11200 +
11201 +#endif /* BCMINTERNAL | BCMPERFSTATS */
11202 diff -urN linux.old/arch/mips/bcm947xx/sbpci.c linux.dev/arch/mips/bcm947xx/sbpci.c
11203 --- linux.old/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
11204 +++ linux.dev/arch/mips/bcm947xx/sbpci.c 2006-10-02 21:19:59.000000000 +0200
11205 @@ -0,0 +1,768 @@
11206 +/*
11207 + * Low-Level PCI and SB support for BCM47xx
11208 + *
11209 + * Copyright 2006, Broadcom Corporation
11210 + * All Rights Reserved.
11211 + *
11212 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11213 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11214 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11215 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11216 + *
11217 + * $Id: hndpci.c,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
11218 + */
11219 +
11220 +#include <typedefs.h>
11221 +#include <osl.h>
11222 +#include <pcicfg.h>
11223 +#include <bcmdevs.h>
11224 +#include <sbconfig.h>
11225 +#include <bcmutils.h>
11226 +#include <sbutils.h>
11227 +#include <sbpci.h>
11228 +#include <bcmendian.h>
11229 +#include <bcmnvram.h>
11230 +#include <hndcpu.h>
11231 +#include <hndmips.h>
11232 +#include <hndpci.h>
11233 +
11234 +/* debug/trace */
11235 +#ifdef BCMDBG_PCI
11236 +#define PCI_MSG(args) printf args
11237 +#else
11238 +#define PCI_MSG(args)
11239 +#endif /* BCMDBG_PCI */
11240 +
11241 +/* Can free sbpci_init() memory after boot */
11242 +#ifndef linux
11243 +#define __init
11244 +#endif /* linux */
11245 +
11246 +/* Emulated configuration space */
11247 +typedef struct {
11248 + int n;
11249 + uint size0;
11250 + uint size1;
11251 + uint size2;
11252 + uint size3;
11253 +} sb_bar_cfg_t;
11254 +static pci_config_regs sb_config_regs[SB_MAXCORES];
11255 +static sb_bar_cfg_t sb_bar_cfg[SB_MAXCORES];
11256 +
11257 +/* Links to emulated and real PCI configuration spaces */
11258 +#define MAXFUNCS 2
11259 +typedef struct {
11260 + pci_config_regs *emu; /* emulated PCI config */
11261 + pci_config_regs *pci; /* real PCI config */
11262 + sb_bar_cfg_t *bar; /* region sizes */
11263 +} sb_pci_cfg_t;
11264 +static sb_pci_cfg_t sb_pci_cfg[SB_MAXCORES][MAXFUNCS];
11265 +
11266 +/* Special emulated config space for non-existing device */
11267 +static pci_config_regs sb_pci_null = { 0xffff, 0xffff };
11268 +
11269 +/* Banned cores */
11270 +static uint16 pci_ban[SB_MAXCORES] = { 0 };
11271 +static uint pci_banned = 0;
11272 +
11273 +/* CardBus mode */
11274 +static bool cardbus = FALSE;
11275 +
11276 +/* Disable PCI host core */
11277 +static bool pci_disabled = FALSE;
11278 +
11279 +/* Host bridge slot #, default to 0 */
11280 +static uint8 pci_hbslot = 0;
11281 +
11282 +/* Internal macros */
11283 +#define PCI_SLOTAD_MAP 16 /* SLOT<n> mapps to AD<n+16> */
11284 +#define PCI_HBSBCFG_REV 8 /* MIN. core rev. required to
11285 + * access host bridge PCI cfg space
11286 + * from SB
11287 + */
11288 +
11289 +/*
11290 + * Functions for accessing external PCI configuration space
11291 + */
11292 +
11293 +/* Assume one-hot slot wiring */
11294 +#define PCI_SLOT_MAX 16 /* Max. PCI Slots */
11295 +
11296 +static uint32
11297 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
11298 +{
11299 + uint coreidx;
11300 + sbpciregs_t *regs;
11301 + uint32 addr = 0;
11302 + osl_t *osh;
11303 +
11304 + /* CardBusMode supports only one device */
11305 + if (cardbus && dev > 1)
11306 + return 0;
11307 +
11308 + osh = sb_osh(sbh);
11309 +
11310 + coreidx = sb_coreidx(sbh);
11311 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
11312 +
11313 + /* Type 0 transaction */
11314 + if (bus == 1) {
11315 + /* Skip unwired slots */
11316 + if (dev < PCI_SLOT_MAX) {
11317 + uint32 win;
11318 +
11319 + /* Slide the PCI window to the appropriate slot */
11320 + win = (SBTOPCI_CFG0 | ((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK));
11321 + W_REG(osh, &regs->sbtopci1, win);
11322 + addr = SB_PCI_CFG |
11323 + ((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) |
11324 + (func << PCICFG_FUN_SHIFT) |
11325 + (off & ~3);
11326 + }
11327 + } else {
11328 + /* Type 1 transaction */
11329 + W_REG(osh, &regs->sbtopci1, SBTOPCI_CFG1);
11330 + addr = SB_PCI_CFG |
11331 + (bus << PCICFG_BUS_SHIFT) |
11332 + (dev << PCICFG_SLOT_SHIFT) |
11333 + (func << PCICFG_FUN_SHIFT) |
11334 + (off & ~3);
11335 + }
11336 +
11337 + sb_setcoreidx(sbh, coreidx);
11338 +
11339 + return addr;
11340 +}
11341 +
11342 +/*
11343 + * Read host bridge PCI config registers from Silicon Backplane (>=rev8).
11344 + *
11345 + * It returns TRUE to indicate that access to the host bridge's pci config
11346 + * from SB is ok, and values in 'addr' and 'val' are valid.
11347 + *
11348 + * It can only read registers at multiple of 4-bytes. Callers must pick up
11349 + * needed bytes from 'val' based on 'off' value. Value in 'addr' reflects
11350 + * the register address where value in 'val' is read.
11351 + */
11352 +static bool
11353 +sb_pcihb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off,
11354 + uint32 **addr, uint32 *val)
11355 +{
11356 + sbpciregs_t *regs;
11357 + osl_t *osh;
11358 + uint coreidx;
11359 + bool ret = FALSE;
11360 +
11361 + /* sanity check */
11362 + ASSERT(bus == 1);
11363 + ASSERT(dev == pci_hbslot);
11364 + ASSERT(func == 0);
11365 +
11366 + osh = sb_osh(sbh);
11367 +
11368 + /* read pci config when core rev >= 8 */
11369 + coreidx = sb_coreidx(sbh);
11370 + regs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
11371 + if (regs && sb_corerev(sbh) >= PCI_HBSBCFG_REV) {
11372 + *addr = (uint32 *)&regs->pcicfg[func][off >> 2];
11373 + *val = R_REG(osh, *addr);
11374 + ret = TRUE;
11375 + }
11376 + sb_setcoreidx(sbh, coreidx);
11377 +
11378 + return ret;
11379 +}
11380 +
11381 +int
11382 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11383 +{
11384 + uint32 addr = 0, *reg = NULL, val;
11385 + int ret = 0;
11386 +
11387 + /*
11388 + * Set value to -1 when:
11389 + * flag 'pci_disabled' is true;
11390 + * value of 'addr' is zero;
11391 + * REG_MAP() fails;
11392 + * BUSPROBE() fails;
11393 + */
11394 + if (pci_disabled)
11395 + val = 0xffffffff;
11396 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11397 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11398 + ;
11399 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11400 + ((reg = (uint32 *)REG_MAP(addr, len)) == 0) ||
11401 + (BUSPROBE(val, reg) != 0))
11402 + val = 0xffffffff;
11403 +
11404 + PCI_MSG(("%s: 0x%x <= 0x%p(0x%x), len %d, off 0x%x, buf 0x%p\n",
11405 + __FUNCTION__, val, reg, addr, len, off, buf));
11406 +
11407 + val >>= 8 * (off & 3);
11408 + if (len == 4)
11409 + *((uint32 *) buf) = val;
11410 + else if (len == 2)
11411 + *((uint16 *) buf) = (uint16) val;
11412 + else if (len == 1)
11413 + *((uint8 *) buf) = (uint8) val;
11414 + else
11415 + ret = -1;
11416 +
11417 + if (reg && addr)
11418 + REG_UNMAP(reg);
11419 +
11420 + return ret;
11421 +}
11422 +
11423 +int
11424 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11425 +{
11426 + osl_t *osh;
11427 + uint32 addr = 0, *reg = NULL, val;
11428 + int ret = 0;
11429 +
11430 + osh = sb_osh(sbh);
11431 +
11432 + /*
11433 + * Ignore write attempt when:
11434 + * flag 'pci_disabled' is true;
11435 + * value of 'addr' is zero;
11436 + * REG_MAP() fails;
11437 + * BUSPROBE() fails;
11438 + */
11439 + if (pci_disabled)
11440 + return 0;
11441 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11442 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11443 + ;
11444 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11445 + ((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
11446 + (BUSPROBE(val, reg) != 0))
11447 + goto done;
11448 +
11449 + if (len == 4)
11450 + val = *((uint32 *) buf);
11451 + else if (len == 2) {
11452 + val &= ~(0xffff << (8 * (off & 3)));
11453 + val |= *((uint16 *) buf) << (8 * (off & 3));
11454 + } else if (len == 1) {
11455 + val &= ~(0xff << (8 * (off & 3)));
11456 + val |= *((uint8 *) buf) << (8 * (off & 3));
11457 + } else {
11458 + ret = -1;
11459 + goto done;
11460 + }
11461 +
11462 + PCI_MSG(("%s: 0x%x => 0x%p\n", __FUNCTION__, val, reg));
11463 +
11464 + W_REG(osh, reg, val);
11465 +
11466 +done:
11467 + if (reg && addr)
11468 + REG_UNMAP(reg);
11469 +
11470 + return ret;
11471 +}
11472 +
11473 +/*
11474 + * Must access emulated PCI configuration at these locations even when
11475 + * the real PCI config space exists and is accessible.
11476 + *
11477 + * PCI_CFG_VID (0x00)
11478 + * PCI_CFG_DID (0x02)
11479 + * PCI_CFG_PROGIF (0x09)
11480 + * PCI_CFG_SUBCL (0x0a)
11481 + * PCI_CFG_BASECL (0x0b)
11482 + * PCI_CFG_HDR (0x0e)
11483 + * PCI_CFG_INT (0x3c)
11484 + * PCI_CFG_PIN (0x3d)
11485 + */
11486 +#define FORCE_EMUCFG(off, len) \
11487 + ((off == PCI_CFG_VID) || (off == PCI_CFG_DID) || \
11488 + (off == PCI_CFG_PROGIF) || \
11489 + (off == PCI_CFG_SUBCL) || (off == PCI_CFG_BASECL) || \
11490 + (off == PCI_CFG_HDR) || \
11491 + (off == PCI_CFG_INT) || (off == PCI_CFG_PIN))
11492 +
11493 +/* Sync the emulation registers and the real PCI config registers. */
11494 +static void
11495 +sb_pcid_read_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11496 + uint off, uint len)
11497 +{
11498 + osl_t *osh;
11499 + uint oldidx;
11500 +
11501 + ASSERT(cfg);
11502 + ASSERT(cfg->emu);
11503 + ASSERT(cfg->pci);
11504 +
11505 + /* decide if real PCI config register access is necessary */
11506 + if (FORCE_EMUCFG(off, len))
11507 + return;
11508 +
11509 + osh = sb_osh(sbh);
11510 +
11511 + /* access to the real pci config space only when the core is up */
11512 + oldidx = sb_coreidx(sbh);
11513 + sb_setcoreidx(sbh, coreidx);
11514 + if (sb_iscoreup(sbh)) {
11515 + if (len == 4)
11516 + *(uint32 *)((ulong)cfg->emu + off) =
11517 + htol32(R_REG(osh, (uint32 *)((ulong)cfg->pci + off)));
11518 + else if (len == 2)
11519 + *(uint16 *)((ulong)cfg->emu + off) =
11520 + htol16(R_REG(osh, (uint16 *)((ulong)cfg->pci + off)));
11521 + else if (len == 1)
11522 + *(uint8 *)((ulong)cfg->emu + off) =
11523 + R_REG(osh, (uint8 *)((ulong)cfg->pci + off));
11524 + }
11525 + sb_setcoreidx(sbh, oldidx);
11526 +}
11527 +
11528 +static void
11529 +sb_pcid_write_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11530 + uint off, uint len)
11531 +{
11532 + osl_t *osh;
11533 + uint oldidx;
11534 +
11535 + ASSERT(cfg);
11536 + ASSERT(cfg->emu);
11537 + ASSERT(cfg->pci);
11538 +
11539 + osh = sb_osh(sbh);
11540 +
11541 + /* decide if real PCI config register access is necessary */
11542 + if (FORCE_EMUCFG(off, len))
11543 + return;
11544 +
11545 + /* access to the real pci config space only when the core is up */
11546 + oldidx = sb_coreidx(sbh);
11547 + sb_setcoreidx(sbh, coreidx);
11548 + if (sb_iscoreup(sbh)) {
11549 + if (len == 4)
11550 + W_REG(osh, (uint32 *)((ulong)cfg->pci + off),
11551 + ltoh32(*(uint32 *)((ulong)cfg->emu + off)));
11552 + else if (len == 2)
11553 + W_REG(osh, (uint16 *)((ulong)cfg->pci + off),
11554 + ltoh16(*(uint16 *)((ulong)cfg->emu + off)));
11555 + else if (len == 1)
11556 + W_REG(osh, (uint8 *)((ulong)cfg->pci + off),
11557 + *(uint8 *)((ulong)cfg->emu + off));
11558 + }
11559 + sb_setcoreidx(sbh, oldidx);
11560 +}
11561 +
11562 +/*
11563 + * Functions for accessing translated SB configuration space
11564 + */
11565 +static int
11566 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11567 +{
11568 + pci_config_regs *cfg;
11569 +
11570 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11571 + return -1;
11572 + cfg = sb_pci_cfg[dev][func].emu;
11573 +
11574 + ASSERT(ISALIGNED(off, len));
11575 + ASSERT(ISALIGNED((uintptr)buf, len));
11576 +
11577 + /* use special config space if the device does not exist */
11578 + if (!cfg)
11579 + cfg = &sb_pci_null;
11580 + /* sync emulation with real PCI config if necessary */
11581 + else if (sb_pci_cfg[dev][func].pci)
11582 + sb_pcid_read_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11583 +
11584 + if (len == 4)
11585 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
11586 + else if (len == 2)
11587 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
11588 + else if (len == 1)
11589 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
11590 + else
11591 + return -1;
11592 +
11593 + return 0;
11594 +}
11595 +
11596 +static int
11597 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11598 +{
11599 + uint coreidx;
11600 + void *regs;
11601 + pci_config_regs *cfg;
11602 + osl_t *osh;
11603 + sb_bar_cfg_t *bar;
11604 +
11605 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11606 + return -1;
11607 + cfg = sb_pci_cfg[dev][func].emu;
11608 + if (!cfg)
11609 + return -1;
11610 +
11611 + ASSERT(ISALIGNED(off, len));
11612 + ASSERT(ISALIGNED((uintptr)buf, len));
11613 +
11614 + osh = sb_osh(sbh);
11615 +
11616 + /* Emulate BAR sizing */
11617 + if (off >= OFFSETOF(pci_config_regs, base[0]) &&
11618 + off <= OFFSETOF(pci_config_regs, base[3]) &&
11619 + len == 4 && *((uint32 *) buf) == ~0) {
11620 + coreidx = sb_coreidx(sbh);
11621 + if ((regs = sb_setcoreidx(sbh, dev))) {
11622 + bar = sb_pci_cfg[dev][func].bar;
11623 + /* Highest numbered address match register */
11624 + if (off == OFFSETOF(pci_config_regs, base[0]))
11625 + cfg->base[0] = ~(bar->size0 - 1);
11626 + else if (off == OFFSETOF(pci_config_regs, base[1]) && bar->n >= 1)
11627 + cfg->base[1] = ~(bar->size1 - 1);
11628 + else if (off == OFFSETOF(pci_config_regs, base[2]) && bar->n >= 2)
11629 + cfg->base[2] = ~(bar->size2 - 1);
11630 + else if (off == OFFSETOF(pci_config_regs, base[3]) && bar->n >= 3)
11631 + cfg->base[3] = ~(bar->size3 - 1);
11632 + }
11633 + sb_setcoreidx(sbh, coreidx);
11634 + }
11635 + else if (len == 4)
11636 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
11637 + else if (len == 2)
11638 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
11639 + else if (len == 1)
11640 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
11641 + else
11642 + return -1;
11643 +
11644 + /* sync emulation with real PCI config if necessary */
11645 + if (sb_pci_cfg[dev][func].pci)
11646 + sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11647 +
11648 + return 0;
11649 +}
11650 +
11651 +int
11652 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11653 +{
11654 + if (bus == 0)
11655 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
11656 + else
11657 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
11658 +}
11659 +
11660 +int
11661 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11662 +{
11663 + if (bus == 0)
11664 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
11665 + else
11666 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
11667 +}
11668 +
11669 +void
11670 +sbpci_ban(uint16 core)
11671 +{
11672 + if (pci_banned < ARRAYSIZE(pci_ban))
11673 + pci_ban[pci_banned++] = core;
11674 +}
11675 +
11676 +/*
11677 + * Initiliaze PCI core. Return 0 after a successful initialization.
11678 + * Otherwise return -1 to indicate there is no PCI core and return 1
11679 + * to indicate PCI core is disabled.
11680 + */
11681 +int __init
11682 +sbpci_init_pci(sb_t *sbh)
11683 +{
11684 + uint chip, chiprev, chippkg, host;
11685 + uint32 boardflags;
11686 + sbpciregs_t *pci;
11687 + sbconfig_t *sb;
11688 + uint32 val;
11689 + int ret = 0;
11690 + char *hbslot;
11691 + osl_t *osh;
11692 +
11693 + chip = sb_chip(sbh);
11694 + chiprev = sb_chiprev(sbh);
11695 + chippkg = sb_chippkg(sbh);
11696 +
11697 + osh = sb_osh(sbh);
11698 +
11699 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
11700 + printk("PCI: no core\n");
11701 + pci_disabled = TRUE;
11702 + return -1;
11703 + }
11704 +
11705 + if ((chip == 0x4310) && (chiprev == 0))
11706 + pci_disabled = TRUE;
11707 +
11708 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
11709 +
11710 + boardflags = (uint32) getintvar(NULL, "boardflags");
11711 +
11712 + /*
11713 + * The 200-pin BCM4712 package does not bond out PCI. Even when
11714 + * PCI is bonded out, some boards may leave the pins
11715 + * floating.
11716 + */
11717 + if (((chip == BCM4712_CHIP_ID) &&
11718 + ((chippkg == BCM4712SMALL_PKG_ID) ||
11719 + (chippkg == BCM4712MID_PKG_ID))) ||
11720 + (boardflags & BFL_NOPCI))
11721 + pci_disabled = TRUE;
11722 +
11723 + /* Enable the core */
11724 + sb_core_reset(sbh, 0, 0);
11725 +
11726 + /*
11727 + * If the PCI core should not be touched (disabled, not bonded
11728 + * out, or pins floating), do not even attempt to access core
11729 + * registers. Otherwise, try to determine if it is in host
11730 + * mode.
11731 + */
11732 + if (pci_disabled)
11733 + host = 0;
11734 + else
11735 + host = !BUSPROBE(val, &pci->control);
11736 +
11737 + if (!host) {
11738 + ret = 1;
11739 +
11740 + /* Disable PCI interrupts in client mode */
11741 + W_REG(osh, &sb->sbintvec, 0);
11742 +
11743 + /* Disable the PCI bridge in client mode */
11744 + sbpci_ban(SB_PCI);
11745 + sb_core_disable(sbh, 0);
11746 +
11747 + printk("PCI: Disabled\n");
11748 + } else {
11749 + printk("PCI: Initializing host\n");
11750 +
11751 + /* Disable PCI SBReqeustTimeout for BCM4785 */
11752 + if (chip == BCM4785_CHIP_ID) {
11753 + AND_REG(osh, &sb->sbimconfiglow, ~0x00000070);
11754 + sb_commit(sbh);
11755 + }
11756 +
11757 + /* Reset the external PCI bus and enable the clock */
11758 + W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */
11759 + W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */
11760 + OSL_DELAY(150); /* delay > 100 us */
11761 + W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */
11762 + /* Use internal arbiter and park REQ/GRNT at external master 0 */
11763 + W_REG(osh, &pci->arbcontrol, PCI_INT_ARB);
11764 + OSL_DELAY(1); /* delay 1 us */
11765 + if (sb_corerev(sbh) >= 8) {
11766 + val = getintvar(NULL, "parkid");
11767 + ASSERT(val <= PCI_PARKID_LAST);
11768 + OR_REG(osh, &pci->arbcontrol, val << PCI_PARKID_SHIFT);
11769 + OSL_DELAY(1);
11770 + }
11771 +
11772 + /* Enable CardBusMode */
11773 + cardbus = getintvar(NULL, "cardbus") == 1;
11774 + if (cardbus) {
11775 + printk("PCI: Enabling CardBus\n");
11776 + /* GPIO 1 resets the CardBus device on bcm94710ap */
11777 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
11778 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
11779 + W_REG(osh, &pci->sprom[0], R_REG(osh, &pci->sprom[0]) | 0x400);
11780 + }
11781 +
11782 + /* 64 MB I/O access window */
11783 + W_REG(osh, &pci->sbtopci0, SBTOPCI_IO);
11784 + /* 64 MB configuration access window */
11785 + W_REG(osh, &pci->sbtopci1, SBTOPCI_CFG0);
11786 + /* 1 GB memory access window */
11787 + W_REG(osh, &pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
11788 +
11789 + /* Host bridge slot # nvram overwrite */
11790 + if ((hbslot = nvram_get("pcihbslot"))) {
11791 + pci_hbslot = bcm_strtoul(hbslot, NULL, 0);
11792 + ASSERT(pci_hbslot < PCI_MAX_DEVICES);
11793 + }
11794 +
11795 + /* Enable PCI bridge BAR0 prefetch and burst */
11796 + val = 6;
11797 + sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val, sizeof(val));
11798 +
11799 + /* Enable PCI interrupts */
11800 + W_REG(osh, &pci->intmask, PCI_INTA);
11801 + }
11802 +
11803 + return ret;
11804 +}
11805 +
11806 +/*
11807 + * Get the PCI region address and size information.
11808 + */
11809 +static void __init
11810 +sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar)
11811 +{
11812 + osl_t *osh;
11813 + uint16 coreid;
11814 + void *regs;
11815 + sbconfig_t *sb;
11816 + uint32 base;
11817 +
11818 + osh = sb_osh(sbh);
11819 + coreid = sb_coreid(sbh);
11820 + regs = sb_coreregs(sbh);
11821 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11822 +
11823 + switch (coreid) {
11824 + case SB_USB20H:
11825 + base = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11826 +
11827 + cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */
11828 + cfg->base[1] = 0;
11829 + cfg->base[2] = 0;
11830 + cfg->base[3] = 0;
11831 + cfg->base[4] = 0;
11832 + cfg->base[5] = 0;
11833 + bar->n = 1;
11834 + bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */
11835 + bar->size1 = 0;
11836 + bar->size2 = 0;
11837 + bar->size3 = 0;
11838 + break;
11839 + default:
11840 + cfg->base[0] = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11841 + cfg->base[1] = htol32(sb_base(R_REG(osh, &sb->sbadmatch1)));
11842 + cfg->base[2] = htol32(sb_base(R_REG(osh, &sb->sbadmatch2)));
11843 + cfg->base[3] = htol32(sb_base(R_REG(osh, &sb->sbadmatch3)));
11844 + cfg->base[4] = 0;
11845 + cfg->base[5] = 0;
11846 + bar->n = (R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
11847 + bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0));
11848 + bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1));
11849 + bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2));
11850 + bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3));
11851 + break;
11852 + }
11853 +}
11854 +
11855 +/*
11856 + * Construct PCI config spaces for SB cores so that they
11857 + * can be accessed as if they were PCI devices.
11858 + */
11859 +static void __init
11860 +sbpci_init_cores(sb_t *sbh)
11861 +{
11862 + uint chiprev, coreidx, i;
11863 + sbconfig_t *sb;
11864 + pci_config_regs *cfg, *pci;
11865 + sb_bar_cfg_t *bar;
11866 + void *regs;
11867 + osl_t *osh;
11868 + uint16 vendor, device;
11869 + uint16 coreid;
11870 + uint8 class, subclass, progif;
11871 + uint dev;
11872 + uint8 header;
11873 + uint func;
11874 +
11875 + chiprev = sb_chiprev(sbh);
11876 + coreidx = sb_coreidx(sbh);
11877 +
11878 + osh = sb_osh(sbh);
11879 +
11880 + /* Scan the SB bus */
11881 + bzero(sb_config_regs, sizeof(sb_config_regs));
11882 + bzero(sb_bar_cfg, sizeof(sb_bar_cfg));
11883 + bzero(sb_pci_cfg, sizeof(sb_pci_cfg));
11884 + memset(&sb_pci_null, -1, sizeof(sb_pci_null));
11885 + cfg = sb_config_regs;
11886 + bar = sb_bar_cfg;
11887 + for (dev = 0; dev < SB_MAXCORES; dev ++) {
11888 + /* Check if the core exists */
11889 + if (!(regs = sb_setcoreidx(sbh, dev)))
11890 + continue;
11891 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11892 +
11893 + /* Check if this core is banned */
11894 + coreid = sb_coreid(sbh);
11895 + for (i = 0; i < pci_banned; i++)
11896 + if (coreid == pci_ban[i])
11897 + break;
11898 + if (i < pci_banned)
11899 + continue;
11900 +
11901 + for (func = 0; func < MAXFUNCS; ++func) {
11902 + /* Make sure we won't go beyond the limit */
11903 + if (cfg >= &sb_config_regs[SB_MAXCORES]) {
11904 + printk("PCI: too many emulated devices\n");
11905 + goto done;
11906 + }
11907 +
11908 + /* Convert core id to pci id */
11909 + if (sb_corepciid(sbh, func, &vendor, &device, &class, &subclass,
11910 + &progif, &header))
11911 + continue;
11912 +
11913 + /*
11914 + * Differentiate real PCI config from emulated.
11915 + * non zero 'pci' indicate there is a real PCI config space
11916 + * for this device.
11917 + */
11918 + switch (device) {
11919 + case BCM47XX_GIGETH_ID:
11920 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11921 + break;
11922 + case BCM47XX_SATAXOR_ID:
11923 + pci = (pci_config_regs *)((uint32)regs + 0x400);
11924 + break;
11925 + case BCM47XX_ATA100_ID:
11926 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11927 + break;
11928 + default:
11929 + pci = NULL;
11930 + break;
11931 + }
11932 + /* Supported translations */
11933 + cfg->vendor = htol16(vendor);
11934 + cfg->device = htol16(device);
11935 + cfg->rev_id = chiprev;
11936 + cfg->prog_if = progif;
11937 + cfg->sub_class = subclass;
11938 + cfg->base_class = class;
11939 + cfg->header_type = header;
11940 + sbpci_init_regions(sbh, func, cfg, bar);
11941 + /* Save core interrupt flag */
11942 + cfg->int_pin = R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
11943 + /* Save core interrupt assignment */
11944 + cfg->int_line = sb_irq(sbh);
11945 + /* Indicate there is no SROM */
11946 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
11947 +
11948 + /* Point to the PCI config spaces */
11949 + sb_pci_cfg[dev][func].emu = cfg;
11950 + sb_pci_cfg[dev][func].pci = pci;
11951 + sb_pci_cfg[dev][func].bar = bar;
11952 + cfg ++;
11953 + bar ++;
11954 + }
11955 + }
11956 +
11957 +done:
11958 + sb_setcoreidx(sbh, coreidx);
11959 +}
11960 +
11961 +/*
11962 + * Initialize PCI core and construct PCI config spaces for SB cores.
11963 + * Must propagate sbpci_init_pci() return value to the caller to let
11964 + * them know the PCI core initialization status.
11965 + */
11966 +int __init
11967 +sbpci_init(sb_t *sbh)
11968 +{
11969 + int status = sbpci_init_pci(sbh);
11970 + sbpci_init_cores(sbh);
11971 + return status;
11972 +}
11973 +
11974 diff -urN linux.old/arch/mips/bcm947xx/sbutils.c linux.dev/arch/mips/bcm947xx/sbutils.c
11975 --- linux.old/arch/mips/bcm947xx/sbutils.c 1970-01-01 01:00:00.000000000 +0100
11976 +++ linux.dev/arch/mips/bcm947xx/sbutils.c 2006-10-02 21:19:59.000000000 +0200
11977 @@ -0,0 +1,3103 @@
11978 +/*
11979 + * Misc utility routines for accessing chip-specific features
11980 + * of the SiliconBackplane-based Broadcom chips.
11981 + *
11982 + * Copyright 2006, Broadcom Corporation
11983 + * All Rights Reserved.
11984 + *
11985 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11986 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11987 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11988 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11989 + * $Id: sbutils.c,v 1.10 2006/04/08 07:12:42 honor Exp $
11990 + */
11991 +
11992 +#include <typedefs.h>
11993 +#include <bcmdefs.h>
11994 +#include <osl.h>
11995 +#include <bcmutils.h>
11996 +#include <sbutils.h>
11997 +#include <bcmdevs.h>
11998 +#include <sbconfig.h>
11999 +#include <sbchipc.h>
12000 +#include <sbpci.h>
12001 +#include <sbpcie.h>
12002 +#include <pcicfg.h>
12003 +#include <sbpcmcia.h>
12004 +#include <sbextif.h>
12005 +#include <sbsocram.h>
12006 +#include <bcmsrom.h>
12007 +#ifdef __mips__
12008 +#include <mipsinc.h>
12009 +#endif /* __mips__ */
12010 +
12011 +/* debug/trace */
12012 +#define SB_ERROR(args)
12013 +
12014 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
12015 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
12016 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
12017 +
12018 +/* misc sb info needed by some of the routines */
12019 +typedef struct sb_info {
12020 +
12021 + struct sb_pub sb; /* back plane public state (must be first field) */
12022 +
12023 + void *osh; /* osl os handle */
12024 + void *sdh; /* bcmsdh handle */
12025 +
12026 + void *curmap; /* current regs va */
12027 + void *regs[SB_MAXCORES]; /* other regs va */
12028 +
12029 + uint curidx; /* current core index */
12030 + uint dev_coreid; /* the core provides driver functions */
12031 +
12032 + bool memseg; /* flag to toggle MEM_SEG register */
12033 +
12034 + uint gpioidx; /* gpio control core index */
12035 + uint gpioid; /* gpio control coretype */
12036 +
12037 + uint numcores; /* # discovered cores */
12038 + uint coreid[SB_MAXCORES]; /* id of each core */
12039 +
12040 + void *intr_arg; /* interrupt callback function arg */
12041 + sb_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
12042 + sb_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
12043 + sb_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
12044 +
12045 +} sb_info_t;
12046 +
12047 +/* local prototypes */
12048 +static sb_info_t * sb_doattach(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12049 + uint bustype, void *sdh, char **vars, uint *varsz);
12050 +static void sb_scan(sb_info_t *si);
12051 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
12052 +static uint _sb_coreidx(sb_info_t *si);
12053 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
12054 +static uint sb_pcidev2chip(uint pcidev);
12055 +static uint sb_chip2numcores(uint chip);
12056 +static bool sb_ispcie(sb_info_t *si);
12057 +static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
12058 +static int sb_pci_fixcfg(sb_info_t *si);
12059 +
12060 +/* routines to access mdio slave device registers */
12061 +static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
12062 +static void sb_war30841(sb_info_t *si);
12063 +
12064 +/* delay needed between the mdio control/ mdiodata register data access */
12065 +#define PR28829_DELAY() OSL_DELAY(10)
12066 +
12067 +/* size that can take bitfielddump */
12068 +#define BITFIELD_DUMP_SIZE 32
12069 +
12070 +/* global variable to indicate reservation/release of gpio's */
12071 +static uint32 sb_gpioreservation = 0;
12072 +
12073 +#define SB_INFO(sbh) (sb_info_t*)sbh
12074 +#define SET_SBREG(si, r, mask, val) \
12075 + W_SBREG((si), (r), ((R_SBREG((si), (r)) & ~(mask)) | (val)))
12076 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && \
12077 + ISALIGNED((x), SB_CORE_SIZE))
12078 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
12079 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
12080 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
12081 +#define BADIDX (SB_MAXCORES+1)
12082 +#define NOREV -1 /* Invalid rev */
12083 +
12084 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
12085 +#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
12086 +
12087 +/* sonicsrev */
12088 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
12089 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
12090 +
12091 +#define R_SBREG(si, sbr) sb_read_sbreg((si), (sbr))
12092 +#define W_SBREG(si, sbr, v) sb_write_sbreg((si), (sbr), (v))
12093 +#define AND_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) & (v)))
12094 +#define OR_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) | (v)))
12095 +
12096 +/*
12097 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
12098 + * after core switching to avoid invalid register accesss inside ISR.
12099 + */
12100 +#define INTR_OFF(si, intr_val) \
12101 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12102 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
12103 +#define INTR_RESTORE(si, intr_val) \
12104 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12105 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
12106 +
12107 +/* dynamic clock control defines */
12108 +#define LPOMINFREQ 25000 /* low power oscillator min */
12109 +#define LPOMAXFREQ 43000 /* low power oscillator max */
12110 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
12111 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
12112 +#define PCIMINFREQ 25000000 /* 25 MHz */
12113 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
12114 +
12115 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
12116 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
12117 +
12118 +/* different register spaces to access thr'u pcie indirect access */
12119 +#define PCIE_CONFIGREGS 1 /* Access to config space */
12120 +#define PCIE_PCIEREGS 2 /* Access to pcie registers */
12121 +
12122 +/* force HT war check */
12123 +#define FORCEHT_WAR32414(si) \
12124 + ((PCIE(si)) && (((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev == 1)) || \
12125 + ((si->sb.chip == BCM4321_CHIP_ID) && (si->sb.chiprev <= 3))))
12126 +
12127 +/* GPIO Based LED powersave defines */
12128 +#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
12129 +#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
12130 +
12131 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
12132 +
12133 +static uint32
12134 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
12135 +{
12136 + uint8 tmp;
12137 + uint32 val, intr_val = 0;
12138 +
12139 +
12140 + /*
12141 + * compact flash only has 11 bits address, while we needs 12 bits address.
12142 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12143 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12144 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12145 + */
12146 + if (si->memseg) {
12147 + INTR_OFF(si, intr_val);
12148 + tmp = 1;
12149 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12150 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12151 + }
12152 +
12153 + val = R_REG(si->osh, sbr);
12154 +
12155 + if (si->memseg) {
12156 + tmp = 0;
12157 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12158 + INTR_RESTORE(si, intr_val);
12159 + }
12160 +
12161 + return (val);
12162 +}
12163 +
12164 +static void
12165 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
12166 +{
12167 + uint8 tmp;
12168 + volatile uint32 dummy;
12169 + uint32 intr_val = 0;
12170 +
12171 +
12172 + /*
12173 + * compact flash only has 11 bits address, while we needs 12 bits address.
12174 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12175 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12176 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12177 + */
12178 + if (si->memseg) {
12179 + INTR_OFF(si, intr_val);
12180 + tmp = 1;
12181 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12182 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12183 + }
12184 +
12185 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12186 +#ifdef IL_BIGENDIAN
12187 + dummy = R_REG(si->osh, sbr);
12188 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12189 + dummy = R_REG(si->osh, sbr);
12190 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12191 +#else
12192 + dummy = R_REG(si->osh, sbr);
12193 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12194 + dummy = R_REG(si->osh, sbr);
12195 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12196 +#endif /* IL_BIGENDIAN */
12197 + } else
12198 + W_REG(si->osh, sbr, v);
12199 +
12200 + if (si->memseg) {
12201 + tmp = 0;
12202 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12203 + INTR_RESTORE(si, intr_val);
12204 + }
12205 +}
12206 +
12207 +/*
12208 + * Allocate a sb handle.
12209 + * devid - pci device id (used to determine chip#)
12210 + * osh - opaque OS handle
12211 + * regs - virtual address of initial core registers
12212 + * bustype - pci/pcmcia/sb/sdio/etc
12213 + * vars - pointer to a pointer area for "environment" variables
12214 + * varsz - pointer to int to return the size of the vars
12215 + */
12216 +sb_t *
12217 +BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
12218 + uint bustype, void *sdh, char **vars, uint *varsz)
12219 +{
12220 + sb_info_t *si;
12221 +
12222 + /* alloc sb_info_t */
12223 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
12224 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
12225 + return (NULL);
12226 + }
12227 +
12228 + if (sb_doattach(si, devid, osh, regs, bustype, sdh, vars, (uint*)varsz) == NULL) {
12229 + MFREE(osh, si, sizeof(sb_info_t));
12230 + return (NULL);
12231 + }
12232 +
12233 + return (sb_t *)si;
12234 +}
12235 +
12236 +/* Using sb_kattach depends on SB_BUS support, either implicit */
12237 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
12238 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12239 +
12240 +/* global kernel resource */
12241 +static sb_info_t ksi;
12242 +static bool ksi_attached = FALSE;
12243 +
12244 +/* generic kernel variant of sb_attach() */
12245 +sb_t *
12246 +BCMINITFN(sb_kattach)(void)
12247 +{
12248 + osl_t *osh = NULL;
12249 + uint32 *regs;
12250 +
12251 + if (!ksi_attached) {
12252 + uint32 cid;
12253 +
12254 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
12255 + cid = R_REG(osh, (uint32 *)regs);
12256 + if (((cid & CID_ID_MASK) == BCM4712_CHIP_ID) &&
12257 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
12258 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
12259 + uint32 *scc, val;
12260 +
12261 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
12262 + val = R_REG(osh, scc);
12263 + SB_ERROR((" initial scc = 0x%x\n", val));
12264 + val |= SCC_SS_XTAL;
12265 + W_REG(osh, scc, val);
12266 + }
12267 +
12268 + if (sb_doattach(&ksi, BCM4710_DEVICE_ID, osh, (void*)regs,
12269 + SB_BUS, NULL, NULL, NULL) == NULL) {
12270 + return NULL;
12271 + }
12272 + else
12273 + ksi_attached = TRUE;
12274 + }
12275 +
12276 + return (sb_t *)&ksi;
12277 +}
12278 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12279 +
12280 +void
12281 +BCMINITFN(sb_war32414_forceHT)(sb_t *sbh, bool forceHT)
12282 +{
12283 + sb_info_t *si;
12284 +
12285 + si = SB_INFO(sbh);
12286 +
12287 +
12288 + if (FORCEHT_WAR32414(si)) {
12289 + uint32 val = 0;
12290 + if (forceHT)
12291 + val = SYCC_HR;
12292 + sb_corereg((void*)si, SB_CC_IDX, OFFSETOF(chipcregs_t, system_clk_ctl),
12293 + SYCC_HR, val);
12294 + }
12295 +}
12296 +
12297 +static sb_info_t *
12298 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12299 + uint bustype, void *sdh, char **vars, uint *varsz)
12300 +{
12301 + uint origidx;
12302 + chipcregs_t *cc;
12303 + sbconfig_t *sb;
12304 + uint32 w;
12305 +
12306 + ASSERT(GOODREGS(regs));
12307 +
12308 + bzero((uchar*)si, sizeof(sb_info_t));
12309 +
12310 + si->sb.buscoreidx = si->gpioidx = BADIDX;
12311 +
12312 + si->curmap = regs;
12313 + si->sdh = sdh;
12314 + si->osh = osh;
12315 +
12316 + /* check to see if we are a sb core mimic'ing a pci core */
12317 + if (bustype == PCI_BUS) {
12318 + if (OSL_PCI_READ_CONFIG(si->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff) {
12319 + SB_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SB "
12320 + "devid:0x%x\n", __FUNCTION__, devid));
12321 + bustype = SB_BUS;
12322 + }
12323 + }
12324 +
12325 + si->sb.bustype = bustype;
12326 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
12327 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
12328 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
12329 + return NULL;
12330 + }
12331 +
12332 + /* need to set memseg flag for CF card first before any sb registers access */
12333 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
12334 + si->memseg = TRUE;
12335 +
12336 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
12337 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
12338 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
12339 +
12340 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12341 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12342 + if (!GOODCOREADDR(w))
12343 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32), SB_ENUM_BASE);
12344 + }
12345 +
12346 + /* initialize current core index value */
12347 + si->curidx = _sb_coreidx(si);
12348 +
12349 + if (si->curidx == BADIDX) {
12350 + SB_ERROR(("sb_doattach: bad core index\n"));
12351 + return NULL;
12352 + }
12353 +
12354 + /* get sonics backplane revision */
12355 + sb = REGS2SB(si->curmap);
12356 + si->sb.sonicsrev = (R_SBREG(si, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
12357 +
12358 + /* keep and reuse the initial register mapping */
12359 + origidx = si->curidx;
12360 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12361 + si->regs[origidx] = regs;
12362 +
12363 + /* is core-0 a chipcommon core? */
12364 + si->numcores = 1;
12365 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
12366 + if (sb_coreid(&si->sb) != SB_CC)
12367 + cc = NULL;
12368 +
12369 + /* determine chip id and rev */
12370 + if (cc) {
12371 + /* chip common core found! */
12372 + si->sb.chip = R_REG(si->osh, &cc->chipid) & CID_ID_MASK;
12373 + si->sb.chiprev = (R_REG(si->osh, &cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
12374 + si->sb.chippkg = (R_REG(si->osh, &cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
12375 + } else {
12376 + /* no chip common core -- must convert device id to chip id */
12377 + if ((si->sb.chip = sb_pcidev2chip(devid)) == 0) {
12378 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
12379 + sb_setcoreidx(&si->sb, origidx);
12380 + return NULL;
12381 + }
12382 + }
12383 +
12384 + /* get chipcommon rev */
12385 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
12386 +
12387 + /* determine numcores */
12388 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
12389 + si->numcores = (R_REG(si->osh, &cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
12390 + else
12391 + si->numcores = sb_chip2numcores(si->sb.chip);
12392 +
12393 + /* return to original core */
12394 + sb_setcoreidx(&si->sb, origidx);
12395 +
12396 + /* sanity checks */
12397 + ASSERT(si->sb.chip);
12398 +
12399 + /* scan for cores */
12400 + sb_scan(si);
12401 +
12402 + /* fixup necessary chip/core configurations */
12403 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12404 + if (sb_pci_fixcfg(si)) {
12405 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
12406 + return NULL;
12407 + }
12408 + }
12409 +
12410 + /* srom_var_init() depends on sb_scan() info */
12411 + if (srom_var_init(si, si->sb.bustype, si->curmap, si->osh, vars, varsz)) {
12412 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
12413 + return (NULL);
12414 + }
12415 +
12416 + if (cc == NULL) {
12417 + /*
12418 + * The chip revision number is hardwired into all
12419 + * of the pci function config rev fields and is
12420 + * independent from the individual core revision numbers.
12421 + * For example, the "A0" silicon of each chip is chip rev 0.
12422 + * For PCMCIA we get it from the CIS instead.
12423 + */
12424 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12425 + ASSERT(vars);
12426 + si->sb.chiprev = getintvar(*vars, "chiprev");
12427 + } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12428 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_REV, sizeof(uint32));
12429 + si->sb.chiprev = w & 0xff;
12430 + } else
12431 + si->sb.chiprev = 0;
12432 + }
12433 +
12434 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12435 + w = getintvar(*vars, "regwindowsz");
12436 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
12437 + }
12438 +
12439 + /* gpio control core is required */
12440 + if (!GOODIDX(si->gpioidx)) {
12441 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
12442 + return NULL;
12443 + }
12444 +
12445 + /* get boardtype and boardrev */
12446 + switch (BUSTYPE(si->sb.bustype)) {
12447 + case PCI_BUS:
12448 + /* do a pci config read to get subsystem id and subvendor id */
12449 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_SVID, sizeof(uint32));
12450 + si->sb.boardvendor = w & 0xffff;
12451 + si->sb.boardtype = (w >> 16) & 0xffff;
12452 + break;
12453 +
12454 + case PCMCIA_BUS:
12455 + case SDIO_BUS:
12456 + si->sb.boardvendor = getintvar(*vars, "manfid");
12457 + si->sb.boardtype = getintvar(*vars, "prodid");
12458 + break;
12459 +
12460 + case SB_BUS:
12461 + case JTAG_BUS:
12462 + si->sb.boardvendor = VENDOR_BROADCOM;
12463 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
12464 + si->sb.boardtype = 0xffff;
12465 + break;
12466 + }
12467 +
12468 + if (si->sb.boardtype == 0) {
12469 + SB_ERROR(("sb_doattach: unknown board type\n"));
12470 + ASSERT(si->sb.boardtype);
12471 + }
12472 +
12473 + /* setup the GPIO based LED powersave register */
12474 + if (si->sb.ccrev >= 16) {
12475 + if ((vars == NULL) || ((w = getintvar(*vars, "leddc")) == 0))
12476 + w = DEFAULT_GPIOTIMERVAL;
12477 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
12478 + }
12479 + if (FORCEHT_WAR32414(si)) {
12480 + /* set proper clk setup delays before forcing HT */
12481 + sb_clkctl_init((void *)si);
12482 + sb_war32414_forceHT((void *)si, 1);
12483 + }
12484 +
12485 +
12486 + return (si);
12487 +}
12488 +
12489 +
12490 +uint
12491 +sb_coreid(sb_t *sbh)
12492 +{
12493 + sb_info_t *si;
12494 + sbconfig_t *sb;
12495 +
12496 + si = SB_INFO(sbh);
12497 + sb = REGS2SB(si->curmap);
12498 +
12499 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
12500 +}
12501 +
12502 +uint
12503 +sb_coreidx(sb_t *sbh)
12504 +{
12505 + sb_info_t *si;
12506 +
12507 + si = SB_INFO(sbh);
12508 + return (si->curidx);
12509 +}
12510 +
12511 +/* return current index of core */
12512 +static uint
12513 +_sb_coreidx(sb_info_t *si)
12514 +{
12515 + sbconfig_t *sb;
12516 + uint32 sbaddr = 0;
12517 +
12518 + ASSERT(si);
12519 +
12520 + switch (BUSTYPE(si->sb.bustype)) {
12521 + case SB_BUS:
12522 + sb = REGS2SB(si->curmap);
12523 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
12524 + break;
12525 +
12526 + case PCI_BUS:
12527 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12528 + break;
12529 +
12530 + case PCMCIA_BUS: {
12531 + uint8 tmp = 0;
12532 +
12533 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
12534 + sbaddr = (uint)tmp << 12;
12535 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
12536 + sbaddr |= (uint)tmp << 16;
12537 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
12538 + sbaddr |= (uint)tmp << 24;
12539 + break;
12540 + }
12541 +
12542 +#ifdef BCMJTAG
12543 + case JTAG_BUS:
12544 + sbaddr = (uint32)si->curmap;
12545 + break;
12546 +#endif /* BCMJTAG */
12547 +
12548 + default:
12549 + ASSERT(0);
12550 + }
12551 +
12552 + if (!GOODCOREADDR(sbaddr))
12553 + return BADIDX;
12554 +
12555 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
12556 +}
12557 +
12558 +uint
12559 +sb_corevendor(sb_t *sbh)
12560 +{
12561 + sb_info_t *si;
12562 + sbconfig_t *sb;
12563 +
12564 + si = SB_INFO(sbh);
12565 + sb = REGS2SB(si->curmap);
12566 +
12567 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
12568 +}
12569 +
12570 +uint
12571 +sb_corerev(sb_t *sbh)
12572 +{
12573 + sb_info_t *si;
12574 + sbconfig_t *sb;
12575 + uint sbidh;
12576 +
12577 + si = SB_INFO(sbh);
12578 + sb = REGS2SB(si->curmap);
12579 + sbidh = R_SBREG(si, &sb->sbidhigh);
12580 +
12581 + return (SBCOREREV(sbidh));
12582 +}
12583 +
12584 +void *
12585 +sb_osh(sb_t *sbh)
12586 +{
12587 + sb_info_t *si;
12588 +
12589 + si = SB_INFO(sbh);
12590 + return si->osh;
12591 +}
12592 +
12593 +void
12594 +sb_setosh(sb_t *sbh, osl_t *osh)
12595 +{
12596 + sb_info_t *si;
12597 +
12598 + si = SB_INFO(sbh);
12599 + if (si->osh != NULL) {
12600 + SB_ERROR(("osh is already set....\n"));
12601 + ASSERT(!si->osh);
12602 + }
12603 + si->osh = osh;
12604 +}
12605 +
12606 +/* set/clear sbtmstatelow core-specific flags */
12607 +uint32
12608 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
12609 +{
12610 + sb_info_t *si;
12611 + sbconfig_t *sb;
12612 + uint32 w;
12613 +
12614 + si = SB_INFO(sbh);
12615 + sb = REGS2SB(si->curmap);
12616 +
12617 + ASSERT((val & ~mask) == 0);
12618 +
12619 + /* mask and set */
12620 + if (mask || val) {
12621 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
12622 + W_SBREG(si, &sb->sbtmstatelow, w);
12623 + }
12624 +
12625 + /* return the new value */
12626 + return (R_SBREG(si, &sb->sbtmstatelow));
12627 +}
12628 +
12629 +/* set/clear sbtmstatehigh core-specific flags */
12630 +uint32
12631 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
12632 +{
12633 + sb_info_t *si;
12634 + sbconfig_t *sb;
12635 + uint32 w;
12636 +
12637 + si = SB_INFO(sbh);
12638 + sb = REGS2SB(si->curmap);
12639 +
12640 + ASSERT((val & ~mask) == 0);
12641 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
12642 +
12643 + /* mask and set */
12644 + if (mask || val) {
12645 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
12646 + W_SBREG(si, &sb->sbtmstatehigh, w);
12647 + }
12648 +
12649 + /* return the new value */
12650 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
12651 +}
12652 +
12653 +/* Run bist on current core. Caller needs to take care of core-specific bist hazards */
12654 +int
12655 +sb_corebist(sb_t *sbh)
12656 +{
12657 + uint32 sblo;
12658 + sb_info_t *si;
12659 + sbconfig_t *sb;
12660 + int result = 0;
12661 +
12662 + si = SB_INFO(sbh);
12663 + sb = REGS2SB(si->curmap);
12664 +
12665 + sblo = R_SBREG(si, &sb->sbtmstatelow);
12666 + W_SBREG(si, &sb->sbtmstatelow, (sblo | SBTML_FGC | SBTML_BE));
12667 +
12668 + SPINWAIT(((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTD) == 0), 100000);
12669 +
12670 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTF)
12671 + result = BCME_ERROR;
12672 +
12673 + W_SBREG(si, &sb->sbtmstatelow, sblo);
12674 +
12675 + return result;
12676 +}
12677 +
12678 +bool
12679 +sb_iscoreup(sb_t *sbh)
12680 +{
12681 + sb_info_t *si;
12682 + sbconfig_t *sb;
12683 +
12684 + si = SB_INFO(sbh);
12685 + sb = REGS2SB(si->curmap);
12686 +
12687 + return ((R_SBREG(si, &sb->sbtmstatelow) &
12688 + (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
12689 +}
12690 +
12691 +/*
12692 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
12693 + * switch back to the original core, and return the new value.
12694 + *
12695 + * When using the silicon backplane, no fidleing with interrupts or core switches are needed.
12696 + *
12697 + * Also, when using pci/pcie, we can optimize away the core switching for pci registers
12698 + * and (on newer pci cores) chipcommon registers.
12699 + */
12700 +static uint
12701 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
12702 +{
12703 + uint origidx = 0;
12704 + uint32 *r = NULL;
12705 + uint w;
12706 + uint intr_val = 0;
12707 + bool fast = FALSE;
12708 +
12709 + ASSERT(GOODIDX(coreidx));
12710 + ASSERT(regoff < SB_CORE_SIZE);
12711 + ASSERT((val & ~mask) == 0);
12712 +
12713 +#ifdef notyet
12714 + if (si->sb.bustype == SB_BUS) {
12715 + /* If internal bus, we can always get at everything */
12716 + fast = TRUE;
12717 + r = (uint32 *)((uchar *)si->regs[coreidx] + regoff);
12718 + } else if (si->sb.bustype == PCI_BUS) {
12719 + /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
12720 +
12721 + if ((si->coreid[coreidx] == SB_CC) &&
12722 + ((si->sb.buscoretype == SB_PCIE) ||
12723 + (si->sb.buscorerev >= 13))) {
12724 + /* Chipc registers are mapped at 12KB */
12725 +
12726 + fast = TRUE;
12727 + r = (uint32 *)((char *)si->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
12728 + } else if (si->sb.buscoreidx == coreidx) {
12729 + /* pci registers are at either in the last 2KB of an 8KB window
12730 + * or, in pcie and pci rev 13 at 8KB
12731 + */
12732 + fast = TRUE;
12733 + if ((si->sb.buscoretype == SB_PCIE) ||
12734 + (si->sb.buscorerev >= 13))
12735 + r = (uint32 *)((char *)si->curmap +
12736 + PCI_16KB0_PCIREGS_OFFSET + regoff);
12737 + else
12738 + r = (uint32 *)((char *)si->curmap +
12739 + ((regoff >= SBCONFIGOFF) ?
12740 + PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
12741 + regoff);
12742 + }
12743 + }
12744 +#endif /* notyet */
12745 +
12746 + if (!fast) {
12747 + INTR_OFF(si, intr_val);
12748 +
12749 + /* save current core index */
12750 + origidx = sb_coreidx(&si->sb);
12751 +
12752 + /* switch core */
12753 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
12754 + }
12755 + ASSERT(r);
12756 +
12757 + /* mask and set */
12758 + if (mask || val) {
12759 + if (regoff >= SBCONFIGOFF) {
12760 + w = (R_SBREG(si, r) & ~mask) | val;
12761 + W_SBREG(si, r, w);
12762 + } else {
12763 + w = (R_REG(si->osh, r) & ~mask) | val;
12764 + W_REG(si->osh, r, w);
12765 + }
12766 + }
12767 +
12768 + /* readback */
12769 + if (regoff >= SBCONFIGOFF)
12770 + w = R_SBREG(si, r);
12771 + else
12772 + w = R_REG(si->osh, r);
12773 +
12774 + if (!fast) {
12775 + /* restore core index */
12776 + if (origidx != coreidx)
12777 + sb_setcoreidx(&si->sb, origidx);
12778 +
12779 + INTR_RESTORE(si, intr_val);
12780 + }
12781 +
12782 + return (w);
12783 +}
12784 +
12785 +#define DWORD_ALIGN(x) (x & ~(0x03))
12786 +#define BYTE_POS(x) (x & 0x3)
12787 +#define WORD_POS(x) (x & 0x1)
12788 +
12789 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
12790 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
12791 +
12792 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
12793 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
12794 +
12795 +#define read_pci_cfg_byte(a) \
12796 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
12797 +
12798 +#define read_pci_cfg_word(a) \
12799 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
12800 +
12801 +
12802 +/* return TRUE if requested capability exists in the PCI config space */
12803 +static bool
12804 +sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
12805 +{
12806 + uint8 cap_id;
12807 + uint8 cap_ptr;
12808 + uint32 bufsize;
12809 + uint8 byte_val;
12810 +
12811 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
12812 + return FALSE;
12813 +
12814 + /* check for Header type 0 */
12815 + byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
12816 + if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
12817 + return FALSE;
12818 +
12819 + /* check if the capability pointer field exists */
12820 + byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
12821 + if (!(byte_val & PCI_CAPPTR_PRESENT))
12822 + return FALSE;
12823 +
12824 + cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
12825 + /* check if the capability pointer is 0x00 */
12826 + if (cap_ptr == 0x00)
12827 + return FALSE;
12828 +
12829 +
12830 + /* loop thr'u the capability list and see if the pcie capabilty exists */
12831 +
12832 + cap_id = read_pci_cfg_byte(cap_ptr);
12833 +
12834 + while (cap_id != req_cap_id) {
12835 + cap_ptr = read_pci_cfg_byte((cap_ptr+1));
12836 + if (cap_ptr == 0x00) break;
12837 + cap_id = read_pci_cfg_byte(cap_ptr);
12838 + }
12839 + if (cap_id != req_cap_id) {
12840 + return FALSE;
12841 + }
12842 + /* found the caller requested capability */
12843 + if ((buf != NULL) && (buflen != NULL)) {
12844 + bufsize = *buflen;
12845 + if (!bufsize) goto end;
12846 + *buflen = 0;
12847 + /* copy the cpability data excluding cap ID and next ptr */
12848 + cap_ptr += 2;
12849 + if ((bufsize + cap_ptr) > SZPCR)
12850 + bufsize = SZPCR - cap_ptr;
12851 + *buflen = bufsize;
12852 + while (bufsize--) {
12853 + *buf = read_pci_cfg_byte(cap_ptr);
12854 + cap_ptr++;
12855 + buf++;
12856 + }
12857 + }
12858 +end:
12859 + return TRUE;
12860 +}
12861 +
12862 +/* return TRUE if PCIE capability exists the pci config space */
12863 +static inline bool
12864 +sb_ispcie(sb_info_t *si)
12865 +{
12866 + return (sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
12867 +}
12868 +
12869 +/* scan the sb enumerated space to identify all cores */
12870 +static void
12871 +BCMINITFN(sb_scan)(sb_info_t *si)
12872 +{
12873 + uint origidx;
12874 + uint i;
12875 + bool pci;
12876 + bool pcie;
12877 + uint pciidx;
12878 + uint pcieidx;
12879 + uint pcirev;
12880 + uint pcierev;
12881 +
12882 +
12883 + /* numcores should already be set */
12884 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
12885 +
12886 + /* save current core index */
12887 + origidx = sb_coreidx(&si->sb);
12888 +
12889 + si->sb.buscorerev = NOREV;
12890 + si->sb.buscoreidx = BADIDX;
12891 +
12892 + si->gpioidx = BADIDX;
12893 +
12894 + pci = pcie = FALSE;
12895 + pcirev = pcierev = NOREV;
12896 + pciidx = pcieidx = BADIDX;
12897 +
12898 + for (i = 0; i < si->numcores; i++) {
12899 + sb_setcoreidx(&si->sb, i);
12900 + si->coreid[i] = sb_coreid(&si->sb);
12901 +
12902 + if (si->coreid[i] == SB_PCI) {
12903 + pciidx = i;
12904 + pcirev = sb_corerev(&si->sb);
12905 + pci = TRUE;
12906 + } else if (si->coreid[i] == SB_PCIE) {
12907 + pcieidx = i;
12908 + pcierev = sb_corerev(&si->sb);
12909 + pcie = TRUE;
12910 + } else if (si->coreid[i] == SB_PCMCIA) {
12911 + si->sb.buscorerev = sb_corerev(&si->sb);
12912 + si->sb.buscoretype = si->coreid[i];
12913 + si->sb.buscoreidx = i;
12914 + }
12915 + }
12916 + if (pci && pcie) {
12917 + if (sb_ispcie(si))
12918 + pci = FALSE;
12919 + else
12920 + pcie = FALSE;
12921 + }
12922 + if (pci) {
12923 + si->sb.buscoretype = SB_PCI;
12924 + si->sb.buscorerev = pcirev;
12925 + si->sb.buscoreidx = pciidx;
12926 + } else if (pcie) {
12927 + si->sb.buscoretype = SB_PCIE;
12928 + si->sb.buscorerev = pcierev;
12929 + si->sb.buscoreidx = pcieidx;
12930 + }
12931 +
12932 + /*
12933 + * Find the gpio "controlling core" type and index.
12934 + * Precedence:
12935 + * - if there's a chip common core - use that
12936 + * - else if there's a pci core (rev >= 2) - use that
12937 + * - else there had better be an extif core (4710 only)
12938 + */
12939 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
12940 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
12941 + si->gpioid = SB_CC;
12942 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
12943 + si->gpioidx = si->sb.buscoreidx;
12944 + si->gpioid = SB_PCI;
12945 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
12946 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
12947 + si->gpioid = SB_EXTIF;
12948 + } else
12949 + ASSERT(si->gpioidx != BADIDX);
12950 +
12951 + /* return to original core index */
12952 + sb_setcoreidx(&si->sb, origidx);
12953 +}
12954 +
12955 +/* may be called with core in reset */
12956 +void
12957 +sb_detach(sb_t *sbh)
12958 +{
12959 + sb_info_t *si;
12960 + uint idx;
12961 +
12962 + si = SB_INFO(sbh);
12963 +
12964 + if (si == NULL)
12965 + return;
12966 +
12967 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12968 + for (idx = 0; idx < SB_MAXCORES; idx++)
12969 + if (si->regs[idx]) {
12970 + REG_UNMAP(si->regs[idx]);
12971 + si->regs[idx] = NULL;
12972 + }
12973 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12974 + if (si != &ksi)
12975 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12976 + MFREE(si->osh, si, sizeof(sb_info_t));
12977 +
12978 +}
12979 +
12980 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
12981 +static uint
12982 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
12983 +{
12984 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
12985 + return (BCM4710_CHIP_ID);
12986 + if ((pcidev >= BCM4402_ENET_ID) && (pcidev <= BCM4402_V90_ID))
12987 + return (BCM4402_CHIP_ID);
12988 + if (pcidev == BCM4401_ENET_ID)
12989 + return (BCM4402_CHIP_ID);
12990 +
12991 + return (0);
12992 +}
12993 +
12994 +/* convert chip number to number of i/o cores */
12995 +static uint
12996 +BCMINITFN(sb_chip2numcores)(uint chip)
12997 +{
12998 + if (chip == BCM4710_CHIP_ID)
12999 + return (9);
13000 + if (chip == BCM4402_CHIP_ID)
13001 + return (3);
13002 + if (chip == BCM4306_CHIP_ID) /* < 4306c0 */
13003 + return (6);
13004 + if (chip == BCM4704_CHIP_ID)
13005 + return (9);
13006 + if (chip == BCM5365_CHIP_ID)
13007 + return (7);
13008 +
13009 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
13010 + ASSERT(0);
13011 + return (1);
13012 +}
13013 +
13014 +/* return index of coreid or BADIDX if not found */
13015 +static uint
13016 +sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit)
13017 +{
13018 + uint found;
13019 + uint i;
13020 +
13021 + found = 0;
13022 +
13023 + for (i = 0; i < si->numcores; i++)
13024 + if (si->coreid[i] == coreid) {
13025 + if (found == coreunit)
13026 + return (i);
13027 + found++;
13028 + }
13029 +
13030 + return (BADIDX);
13031 +}
13032 +
13033 +/*
13034 + * this function changes logical "focus" to the indiciated core,
13035 + * must be called with interrupt off.
13036 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13037 + */
13038 +void*
13039 +sb_setcoreidx(sb_t *sbh, uint coreidx)
13040 +{
13041 + sb_info_t *si;
13042 + uint32 sbaddr;
13043 + uint8 tmp;
13044 +
13045 + si = SB_INFO(sbh);
13046 +
13047 + if (coreidx >= si->numcores)
13048 + return (NULL);
13049 +
13050 + /*
13051 + * If the user has provided an interrupt mask enabled function,
13052 + * then assert interrupts are disabled before switching the core.
13053 + */
13054 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
13055 +
13056 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
13057 +
13058 + switch (BUSTYPE(si->sb.bustype)) {
13059 + case SB_BUS:
13060 + /* map new one */
13061 + if (!si->regs[coreidx]) {
13062 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
13063 + ASSERT(GOODREGS(si->regs[coreidx]));
13064 + }
13065 + si->curmap = si->regs[coreidx];
13066 + break;
13067 +
13068 + case PCI_BUS:
13069 + /* point bar0 window */
13070 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
13071 + break;
13072 +
13073 + case PCMCIA_BUS:
13074 + tmp = (sbaddr >> 12) & 0x0f;
13075 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
13076 + tmp = (sbaddr >> 16) & 0xff;
13077 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
13078 + tmp = (sbaddr >> 24) & 0xff;
13079 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
13080 + break;
13081 +#ifdef BCMJTAG
13082 + case JTAG_BUS:
13083 + /* map new one */
13084 + if (!si->regs[coreidx]) {
13085 + si->regs[coreidx] = (void *)sbaddr;
13086 + ASSERT(GOODREGS(si->regs[coreidx]));
13087 + }
13088 + si->curmap = si->regs[coreidx];
13089 + break;
13090 +#endif /* BCMJTAG */
13091 + }
13092 +
13093 + si->curidx = coreidx;
13094 +
13095 + return (si->curmap);
13096 +}
13097 +
13098 +/*
13099 + * this function changes logical "focus" to the indiciated core,
13100 + * must be called with interrupt off.
13101 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13102 + */
13103 +void*
13104 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
13105 +{
13106 + sb_info_t *si;
13107 + uint idx;
13108 +
13109 + si = SB_INFO(sbh);
13110 + idx = sb_findcoreidx(si, coreid, coreunit);
13111 + if (!GOODIDX(idx))
13112 + return (NULL);
13113 +
13114 + return (sb_setcoreidx(sbh, idx));
13115 +}
13116 +
13117 +/* return chip number */
13118 +uint
13119 +sb_chip(sb_t *sbh)
13120 +{
13121 + sb_info_t *si;
13122 +
13123 + si = SB_INFO(sbh);
13124 + return (si->sb.chip);
13125 +}
13126 +
13127 +/* return chip revision number */
13128 +uint
13129 +sb_chiprev(sb_t *sbh)
13130 +{
13131 + sb_info_t *si;
13132 +
13133 + si = SB_INFO(sbh);
13134 + return (si->sb.chiprev);
13135 +}
13136 +
13137 +/* return chip common revision number */
13138 +uint
13139 +sb_chipcrev(sb_t *sbh)
13140 +{
13141 + sb_info_t *si;
13142 +
13143 + si = SB_INFO(sbh);
13144 + return (si->sb.ccrev);
13145 +}
13146 +
13147 +/* return chip package option */
13148 +uint
13149 +sb_chippkg(sb_t *sbh)
13150 +{
13151 + sb_info_t *si;
13152 +
13153 + si = SB_INFO(sbh);
13154 + return (si->sb.chippkg);
13155 +}
13156 +
13157 +/* return PCI core rev. */
13158 +uint
13159 +sb_pcirev(sb_t *sbh)
13160 +{
13161 + sb_info_t *si;
13162 +
13163 + si = SB_INFO(sbh);
13164 + return (si->sb.buscorerev);
13165 +}
13166 +
13167 +bool
13168 +BCMINITFN(sb_war16165)(sb_t *sbh)
13169 +{
13170 + sb_info_t *si;
13171 +
13172 + si = SB_INFO(sbh);
13173 +
13174 + return (PCI(si) && (si->sb.buscorerev <= 10));
13175 +}
13176 +
13177 +static void
13178 +BCMINITFN(sb_war30841)(sb_info_t *si)
13179 +{
13180 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
13181 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
13182 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
13183 +}
13184 +
13185 +/* return PCMCIA core rev. */
13186 +uint
13187 +BCMINITFN(sb_pcmciarev)(sb_t *sbh)
13188 +{
13189 + sb_info_t *si;
13190 +
13191 + si = SB_INFO(sbh);
13192 + return (si->sb.buscorerev);
13193 +}
13194 +
13195 +/* return board vendor id */
13196 +uint
13197 +sb_boardvendor(sb_t *sbh)
13198 +{
13199 + sb_info_t *si;
13200 +
13201 + si = SB_INFO(sbh);
13202 + return (si->sb.boardvendor);
13203 +}
13204 +
13205 +/* return boardtype */
13206 +uint
13207 +sb_boardtype(sb_t *sbh)
13208 +{
13209 + sb_info_t *si;
13210 + char *var;
13211 +
13212 + si = SB_INFO(sbh);
13213 +
13214 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
13215 + /* boardtype format is a hex string */
13216 + si->sb.boardtype = getintvar(NULL, "boardtype");
13217 +
13218 + /* backward compatibility for older boardtype string format */
13219 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
13220 + if (!strcmp(var, "bcm94710dev"))
13221 + si->sb.boardtype = BCM94710D_BOARD;
13222 + else if (!strcmp(var, "bcm94710ap"))
13223 + si->sb.boardtype = BCM94710AP_BOARD;
13224 + else if (!strcmp(var, "bu4710"))
13225 + si->sb.boardtype = BU4710_BOARD;
13226 + else if (!strcmp(var, "bcm94702mn"))
13227 + si->sb.boardtype = BCM94702MN_BOARD;
13228 + else if (!strcmp(var, "bcm94710r1"))
13229 + si->sb.boardtype = BCM94710R1_BOARD;
13230 + else if (!strcmp(var, "bcm94710r4"))
13231 + si->sb.boardtype = BCM94710R4_BOARD;
13232 + else if (!strcmp(var, "bcm94702cpci"))
13233 + si->sb.boardtype = BCM94702CPCI_BOARD;
13234 + else if (!strcmp(var, "bcm95380_rr"))
13235 + si->sb.boardtype = BCM95380RR_BOARD;
13236 + }
13237 + }
13238 +
13239 + return (si->sb.boardtype);
13240 +}
13241 +
13242 +/* return bus type of sbh device */
13243 +uint
13244 +sb_bus(sb_t *sbh)
13245 +{
13246 + sb_info_t *si;
13247 +
13248 + si = SB_INFO(sbh);
13249 + return (si->sb.bustype);
13250 +}
13251 +
13252 +/* return bus core type */
13253 +uint
13254 +sb_buscoretype(sb_t *sbh)
13255 +{
13256 + sb_info_t *si;
13257 +
13258 + si = SB_INFO(sbh);
13259 +
13260 + return (si->sb.buscoretype);
13261 +}
13262 +
13263 +/* return bus core revision */
13264 +uint
13265 +sb_buscorerev(sb_t *sbh)
13266 +{
13267 + sb_info_t *si;
13268 + si = SB_INFO(sbh);
13269 +
13270 + return (si->sb.buscorerev);
13271 +}
13272 +
13273 +/* return list of found cores */
13274 +uint
13275 +sb_corelist(sb_t *sbh, uint coreid[])
13276 +{
13277 + sb_info_t *si;
13278 +
13279 + si = SB_INFO(sbh);
13280 +
13281 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof(uint)));
13282 + return (si->numcores);
13283 +}
13284 +
13285 +/* return current register mapping */
13286 +void *
13287 +sb_coreregs(sb_t *sbh)
13288 +{
13289 + sb_info_t *si;
13290 +
13291 + si = SB_INFO(sbh);
13292 + ASSERT(GOODREGS(si->curmap));
13293 +
13294 + return (si->curmap);
13295 +}
13296 +
13297 +
13298 +/* do buffered registers update */
13299 +void
13300 +sb_commit(sb_t *sbh)
13301 +{
13302 + sb_info_t *si;
13303 + uint origidx;
13304 + uint intr_val = 0;
13305 +
13306 + si = SB_INFO(sbh);
13307 +
13308 + origidx = si->curidx;
13309 + ASSERT(GOODIDX(origidx));
13310 +
13311 + INTR_OFF(si, intr_val);
13312 +
13313 + /* switch over to chipcommon core if there is one, else use pci */
13314 + if (si->sb.ccrev != NOREV) {
13315 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
13316 +
13317 + /* do the buffer registers update */
13318 + W_REG(si->osh, &ccregs->broadcastaddress, SB_COMMIT);
13319 + W_REG(si->osh, &ccregs->broadcastdata, 0x0);
13320 + } else if (PCI(si)) {
13321 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
13322 +
13323 + /* do the buffer registers update */
13324 + W_REG(si->osh, &pciregs->bcastaddr, SB_COMMIT);
13325 + W_REG(si->osh, &pciregs->bcastdata, 0x0);
13326 + } else
13327 + ASSERT(0);
13328 +
13329 + /* restore core index */
13330 + sb_setcoreidx(sbh, origidx);
13331 + INTR_RESTORE(si, intr_val);
13332 +}
13333 +
13334 +/* reset and re-enable a core
13335 + * inputs:
13336 + * bits - core specific bits that are set during and after reset sequence
13337 + * resetbits - core specific bits that are set only during reset sequence
13338 + */
13339 +void
13340 +sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits)
13341 +{
13342 + sb_info_t *si;
13343 + sbconfig_t *sb;
13344 + volatile uint32 dummy;
13345 +
13346 + si = SB_INFO(sbh);
13347 + ASSERT(GOODREGS(si->curmap));
13348 + sb = REGS2SB(si->curmap);
13349 +
13350 + /*
13351 + * Must do the disable sequence first to work for arbitrary current core state.
13352 + */
13353 + sb_core_disable(sbh, (bits | resetbits));
13354 +
13355 + /*
13356 + * Now do the initialization sequence.
13357 + */
13358 +
13359 + /* set reset while enabling the clock and forcing them on throughout the core */
13360 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits | resetbits));
13361 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13362 + OSL_DELAY(1);
13363 +
13364 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
13365 + W_SBREG(si, &sb->sbtmstatehigh, 0);
13366 + }
13367 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
13368 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
13369 + }
13370 +
13371 + /* clear reset and allow it to propagate throughout the core */
13372 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
13373 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13374 + OSL_DELAY(1);
13375 +
13376 + /* leave clock enabled */
13377 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
13378 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13379 + OSL_DELAY(1);
13380 +}
13381 +
13382 +void
13383 +sb_core_tofixup(sb_t *sbh)
13384 +{
13385 + sb_info_t *si;
13386 + sbconfig_t *sb;
13387 +
13388 + si = SB_INFO(sbh);
13389 +
13390 + if ((BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) ||
13391 + (PCI(si) && (si->sb.buscorerev >= 5)))
13392 + return;
13393 +
13394 + ASSERT(GOODREGS(si->curmap));
13395 + sb = REGS2SB(si->curmap);
13396 +
13397 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
13398 + SET_SBREG(si, &sb->sbimconfiglow,
13399 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13400 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
13401 + } else {
13402 + if (sb_coreid(sbh) == SB_PCI) {
13403 + SET_SBREG(si, &sb->sbimconfiglow,
13404 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13405 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13406 + } else {
13407 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
13408 + }
13409 + }
13410 +
13411 + sb_commit(sbh);
13412 +}
13413 +
13414 +/*
13415 + * Set the initiator timeout for the "master core".
13416 + * The master core is defined to be the core in control
13417 + * of the chip and so it issues accesses to non-memory
13418 + * locations (Because of dma *any* core can access memeory).
13419 + *
13420 + * The routine uses the bus to decide who is the master:
13421 + * SB_BUS => mips
13422 + * JTAG_BUS => chipc
13423 + * PCI_BUS => pci or pcie
13424 + * PCMCIA_BUS => pcmcia
13425 + * SDIO_BUS => pcmcia
13426 + *
13427 + * This routine exists so callers can disable initiator
13428 + * timeouts so accesses to very slow devices like otp
13429 + * won't cause an abort. The routine allows arbitrary
13430 + * settings of the service and request timeouts, though.
13431 + *
13432 + * Returns the timeout state before changing it or -1
13433 + * on error.
13434 + */
13435 +
13436 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
13437 +
13438 +uint32
13439 +sb_set_initiator_to(sb_t *sbh, uint32 to)
13440 +{
13441 + sb_info_t *si;
13442 + uint origidx, idx;
13443 + uint intr_val = 0;
13444 + uint32 tmp, ret = 0xffffffff;
13445 + sbconfig_t *sb;
13446 +
13447 + si = SB_INFO(sbh);
13448 +
13449 + if ((to & ~TO_MASK) != 0)
13450 + return ret;
13451 +
13452 + /* Figure out the master core */
13453 + idx = BADIDX;
13454 + switch (BUSTYPE(si->sb.bustype)) {
13455 + case PCI_BUS:
13456 + idx = si->sb.buscoreidx;
13457 + break;
13458 + case JTAG_BUS:
13459 + idx = SB_CC_IDX;
13460 + break;
13461 + case PCMCIA_BUS:
13462 + case SDIO_BUS:
13463 + idx = sb_findcoreidx(si, SB_PCMCIA, 0);
13464 + break;
13465 + case SB_BUS:
13466 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
13467 + idx = sb_findcoreidx(si, SB_MIPS, 0);
13468 + break;
13469 + default:
13470 + ASSERT(0);
13471 + }
13472 + if (idx == BADIDX)
13473 + return ret;
13474 +
13475 + INTR_OFF(si, intr_val);
13476 + origidx = sb_coreidx(sbh);
13477 +
13478 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
13479 +
13480 + tmp = R_SBREG(si, &sb->sbimconfiglow);
13481 + ret = tmp & TO_MASK;
13482 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
13483 +
13484 + sb_commit(sbh);
13485 + sb_setcoreidx(sbh, origidx);
13486 + INTR_RESTORE(si, intr_val);
13487 + return ret;
13488 +}
13489 +
13490 +void
13491 +sb_core_disable(sb_t *sbh, uint32 bits)
13492 +{
13493 + sb_info_t *si;
13494 + volatile uint32 dummy;
13495 + uint32 rej;
13496 + sbconfig_t *sb;
13497 +
13498 + si = SB_INFO(sbh);
13499 +
13500 + ASSERT(GOODREGS(si->curmap));
13501 + sb = REGS2SB(si->curmap);
13502 +
13503 + /* if core is already in reset, just return */
13504 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
13505 + return;
13506 +
13507 + /* reject value changed between sonics 2.2 and 2.3 */
13508 + if (si->sb.sonicsrev == SONICS_2_2)
13509 + rej = (1 << SBTML_REJ_SHIFT);
13510 + else
13511 + rej = (2 << SBTML_REJ_SHIFT);
13512 +
13513 + /* if clocks are not enabled, put into reset and return */
13514 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
13515 + goto disable;
13516 +
13517 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
13518 + OR_SBREG(si, &sb->sbtmstatelow, rej);
13519 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13520 + OSL_DELAY(1);
13521 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
13522 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY)
13523 + SB_ERROR(("%s: target state still busy\n", __FUNCTION__));
13524 +
13525 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
13526 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
13527 + dummy = R_SBREG(si, &sb->sbimstate);
13528 + OSL_DELAY(1);
13529 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
13530 + }
13531 +
13532 + /* set reset and reject while enabling the clocks */
13533 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
13534 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13535 + OSL_DELAY(10);
13536 +
13537 + /* don't forget to clear the initiator reject bit */
13538 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
13539 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
13540 +
13541 +disable:
13542 + /* leave reset and reject asserted */
13543 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
13544 + OSL_DELAY(1);
13545 +}
13546 +
13547 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
13548 +void
13549 +sb_watchdog(sb_t *sbh, uint ticks)
13550 +{
13551 + sb_info_t *si = SB_INFO(sbh);
13552 +
13553 + /* make sure we come up in fast clock mode */
13554 + sb_clkctl_clk(sbh, CLK_FAST);
13555 +
13556 + /* instant NMI */
13557 + switch (si->gpioid) {
13558 + case SB_CC:
13559 +#ifdef __mips__
13560 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1)
13561 + MTC0(C0_BROADCOM, 4, (1 << 22));
13562 +#endif /* __mips__ */
13563 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
13564 +#ifdef __mips__
13565 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1) {
13566 + __asm__ __volatile__ (
13567 + ".set\tmips3\n\t"
13568 + "sync\n\t"
13569 + "wait\n\t"
13570 + ".set\tmips0"
13571 + );
13572 + while (1);
13573 + }
13574 +#endif /* __mips__ */
13575 + break;
13576 + case SB_EXTIF:
13577 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
13578 + break;
13579 + }
13580 +}
13581 +
13582 +/* initialize the pcmcia core */
13583 +void
13584 +sb_pcmcia_init(sb_t *sbh)
13585 +{
13586 + sb_info_t *si;
13587 + uint8 cor = 0;
13588 +
13589 + si = SB_INFO(sbh);
13590 +
13591 + /* enable d11 mac interrupts */
13592 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13593 + cor |= COR_IRQEN | COR_FUNEN;
13594 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13595 +
13596 +}
13597 +
13598 +
13599 +/*
13600 + * Configure the pci core for pci client (NIC) action
13601 + * coremask is the bitvec of cores by index to be enabled.
13602 + */
13603 +void
13604 +BCMINITFN(sb_pci_setup)(sb_t *sbh, uint coremask)
13605 +{
13606 + sb_info_t *si;
13607 + sbconfig_t *sb;
13608 + sbpciregs_t *pciregs;
13609 + uint32 sbflag;
13610 + uint32 w;
13611 + uint idx;
13612 + int reg_val;
13613 +
13614 + si = SB_INFO(sbh);
13615 +
13616 + /* if not pci bus, we're done */
13617 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
13618 + return;
13619 +
13620 + ASSERT(PCI(si) || PCIE(si));
13621 + ASSERT(si->sb.buscoreidx != BADIDX);
13622 +
13623 + /* get current core index */
13624 + idx = si->curidx;
13625 +
13626 + /* we interrupt on this backplane flag number */
13627 + ASSERT(GOODREGS(si->curmap));
13628 + sb = REGS2SB(si->curmap);
13629 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
13630 +
13631 + /* switch over to pci core */
13632 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
13633 + sb = REGS2SB(pciregs);
13634 +
13635 + /*
13636 + * Enable sb->pci interrupts. Assume
13637 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
13638 + */
13639 + if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
13640 + /* pci config write to set this core bit in PCIIntMask */
13641 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
13642 + w |= (coremask << PCI_SBIM_SHIFT);
13643 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
13644 + } else {
13645 + /* set sbintvec bit for our flag number */
13646 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
13647 + }
13648 +
13649 + if (PCI(si)) {
13650 + OR_REG(si->osh, &pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
13651 + if (si->sb.buscorerev >= 11)
13652 + OR_REG(si->osh, &pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
13653 + if (si->sb.buscorerev < 5) {
13654 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13655 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13656 + sb_commit(sbh);
13657 + }
13658 + }
13659 +
13660 +#ifdef PCIE_SUPPOER
13661 + /* PCIE workarounds */
13662 + if (PCIE(si)) {
13663 + if ((si->sb.buscorerev == 0) || (si->sb.buscorerev == 1)) {
13664 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13665 + PCIE_TLP_WORKAROUNDSREG);
13666 + reg_val |= 0x8;
13667 + sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS,
13668 + PCIE_TLP_WORKAROUNDSREG, reg_val);
13669 + }
13670 +
13671 + if (si->sb.buscorerev == 1) {
13672 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13673 + PCIE_DLLP_LCREG);
13674 + reg_val |= (0x40);
13675 + sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
13676 + }
13677 +
13678 + if (si->sb.buscorerev == 0)
13679 + sb_war30841(si);
13680 + }
13681 +#endif
13682 +
13683 + /* switch back to previous core */
13684 + sb_setcoreidx(sbh, idx);
13685 +}
13686 +
13687 +uint32
13688 +sb_base(uint32 admatch)
13689 +{
13690 + uint32 base;
13691 + uint type;
13692 +
13693 + type = admatch & SBAM_TYPE_MASK;
13694 + ASSERT(type < 3);
13695 +
13696 + base = 0;
13697 +
13698 + if (type == 0) {
13699 + base = admatch & SBAM_BASE0_MASK;
13700 + } else if (type == 1) {
13701 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13702 + base = admatch & SBAM_BASE1_MASK;
13703 + } else if (type == 2) {
13704 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13705 + base = admatch & SBAM_BASE2_MASK;
13706 + }
13707 +
13708 + return (base);
13709 +}
13710 +
13711 +uint32
13712 +sb_size(uint32 admatch)
13713 +{
13714 + uint32 size;
13715 + uint type;
13716 +
13717 + type = admatch & SBAM_TYPE_MASK;
13718 + ASSERT(type < 3);
13719 +
13720 + size = 0;
13721 +
13722 + if (type == 0) {
13723 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
13724 + } else if (type == 1) {
13725 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13726 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
13727 + } else if (type == 2) {
13728 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13729 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
13730 + }
13731 +
13732 + return (size);
13733 +}
13734 +
13735 +/* return the core-type instantiation # of the current core */
13736 +uint
13737 +sb_coreunit(sb_t *sbh)
13738 +{
13739 + sb_info_t *si;
13740 + uint idx;
13741 + uint coreid;
13742 + uint coreunit;
13743 + uint i;
13744 +
13745 + si = SB_INFO(sbh);
13746 + coreunit = 0;
13747 +
13748 + idx = si->curidx;
13749 +
13750 + ASSERT(GOODREGS(si->curmap));
13751 + coreid = sb_coreid(sbh);
13752 +
13753 + /* count the cores of our type */
13754 + for (i = 0; i < idx; i++)
13755 + if (si->coreid[i] == coreid)
13756 + coreunit++;
13757 +
13758 + return (coreunit);
13759 +}
13760 +
13761 +static INLINE uint32
13762 +factor6(uint32 x)
13763 +{
13764 + switch (x) {
13765 + case CC_F6_2: return 2;
13766 + case CC_F6_3: return 3;
13767 + case CC_F6_4: return 4;
13768 + case CC_F6_5: return 5;
13769 + case CC_F6_6: return 6;
13770 + case CC_F6_7: return 7;
13771 + default: return 0;
13772 + }
13773 +}
13774 +
13775 +/* calculate the speed the SB would run at given a set of clockcontrol values */
13776 +uint32
13777 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
13778 +{
13779 + uint32 n1, n2, clock, m1, m2, m3, mc;
13780 +
13781 + n1 = n & CN_N1_MASK;
13782 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
13783 +
13784 + if (pll_type == PLL_TYPE6) {
13785 + if (m & CC_T6_MMASK)
13786 + return CC_T6_M1;
13787 + else
13788 + return CC_T6_M0;
13789 + } else if ((pll_type == PLL_TYPE1) ||
13790 + (pll_type == PLL_TYPE3) ||
13791 + (pll_type == PLL_TYPE4) ||
13792 + (pll_type == PLL_TYPE7)) {
13793 + n1 = factor6(n1);
13794 + n2 += CC_F5_BIAS;
13795 + } else if (pll_type == PLL_TYPE2) {
13796 + n1 += CC_T2_BIAS;
13797 + n2 += CC_T2_BIAS;
13798 + ASSERT((n1 >= 2) && (n1 <= 7));
13799 + ASSERT((n2 >= 5) && (n2 <= 23));
13800 + } else if (pll_type == PLL_TYPE5) {
13801 + return (100000000);
13802 + } else
13803 + ASSERT(0);
13804 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
13805 + if ((pll_type == PLL_TYPE3) ||
13806 + (pll_type == PLL_TYPE7)) {
13807 + clock = CC_CLOCK_BASE2 * n1 * n2;
13808 + } else
13809 + clock = CC_CLOCK_BASE1 * n1 * n2;
13810 +
13811 + if (clock == 0)
13812 + return 0;
13813 +
13814 + m1 = m & CC_M1_MASK;
13815 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
13816 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
13817 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
13818 +
13819 + if ((pll_type == PLL_TYPE1) ||
13820 + (pll_type == PLL_TYPE3) ||
13821 + (pll_type == PLL_TYPE4) ||
13822 + (pll_type == PLL_TYPE7)) {
13823 + m1 = factor6(m1);
13824 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
13825 + m2 += CC_F5_BIAS;
13826 + else
13827 + m2 = factor6(m2);
13828 + m3 = factor6(m3);
13829 +
13830 + switch (mc) {
13831 + case CC_MC_BYPASS: return (clock);
13832 + case CC_MC_M1: return (clock / m1);
13833 + case CC_MC_M1M2: return (clock / (m1 * m2));
13834 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
13835 + case CC_MC_M1M3: return (clock / (m1 * m3));
13836 + default: return (0);
13837 + }
13838 + } else {
13839 + ASSERT(pll_type == PLL_TYPE2);
13840 +
13841 + m1 += CC_T2_BIAS;
13842 + m2 += CC_T2M2_BIAS;
13843 + m3 += CC_T2_BIAS;
13844 + ASSERT((m1 >= 2) && (m1 <= 7));
13845 + ASSERT((m2 >= 3) && (m2 <= 10));
13846 + ASSERT((m3 >= 2) && (m3 <= 7));
13847 +
13848 + if ((mc & CC_T2MC_M1BYP) == 0)
13849 + clock /= m1;
13850 + if ((mc & CC_T2MC_M2BYP) == 0)
13851 + clock /= m2;
13852 + if ((mc & CC_T2MC_M3BYP) == 0)
13853 + clock /= m3;
13854 +
13855 + return (clock);
13856 + }
13857 +}
13858 +
13859 +/* returns the current speed the SB is running at */
13860 +uint32
13861 +sb_clock(sb_t *sbh)
13862 +{
13863 + sb_info_t *si;
13864 + extifregs_t *eir;
13865 + chipcregs_t *cc;
13866 + uint32 n, m;
13867 + uint idx;
13868 + uint32 pll_type, rate;
13869 + uint intr_val = 0;
13870 +
13871 + si = SB_INFO(sbh);
13872 + idx = si->curidx;
13873 + pll_type = PLL_TYPE1;
13874 +
13875 + INTR_OFF(si, intr_val);
13876 +
13877 + /* switch to extif or chipc core */
13878 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
13879 + n = R_REG(si->osh, &eir->clockcontrol_n);
13880 + m = R_REG(si->osh, &eir->clockcontrol_sb);
13881 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
13882 + pll_type = R_REG(si->osh, &cc->capabilities) & CAP_PLL_MASK;
13883 + if (pll_type == PLL_NONE) {
13884 + INTR_RESTORE(si, intr_val);
13885 + return 80000000;
13886 + }
13887 + n = R_REG(si->osh, &cc->clockcontrol_n);
13888 + if (pll_type == PLL_TYPE6)
13889 + m = R_REG(si->osh, &cc->clockcontrol_m3);
13890 + else if ((pll_type == PLL_TYPE3) && !(BCMINIT(sb_chip)(sbh) == 0x5365))
13891 + m = R_REG(si->osh, &cc->clockcontrol_m2);
13892 + else
13893 + m = R_REG(si->osh, &cc->clockcontrol_sb);
13894 + } else {
13895 + INTR_RESTORE(si, intr_val);
13896 + return 0;
13897 + }
13898 +
13899 + /* calculate rate */
13900 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
13901 + rate = 100000000;
13902 + else {
13903 + rate = sb_clock_rate(pll_type, n, m);
13904 +
13905 + if (pll_type == PLL_TYPE3)
13906 + rate = rate / 2;
13907 + }
13908 +
13909 + /* switch back to previous core */
13910 + sb_setcoreidx(sbh, idx);
13911 +
13912 + INTR_RESTORE(si, intr_val);
13913 +
13914 + return rate;
13915 +}
13916 +
13917 +/* change logical "focus" to the gpio core for optimized access */
13918 +void*
13919 +sb_gpiosetcore(sb_t *sbh)
13920 +{
13921 + sb_info_t *si;
13922 +
13923 + si = SB_INFO(sbh);
13924 +
13925 + return (sb_setcoreidx(sbh, si->gpioidx));
13926 +}
13927 +
13928 +/* mask&set gpiocontrol bits */
13929 +uint32
13930 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13931 +{
13932 + sb_info_t *si;
13933 + uint regoff;
13934 +
13935 + si = SB_INFO(sbh);
13936 + regoff = 0;
13937 +
13938 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13939 +
13940 + /* gpios could be shared on router platforms */
13941 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13942 + mask = priority ? (sb_gpioreservation & mask) :
13943 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13944 + val &= mask;
13945 + }
13946 +
13947 + switch (si->gpioid) {
13948 + case SB_CC:
13949 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
13950 + break;
13951 +
13952 + case SB_PCI:
13953 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
13954 + break;
13955 +
13956 + case SB_EXTIF:
13957 + return (0);
13958 + }
13959 +
13960 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13961 +}
13962 +
13963 +/* mask&set gpio output enable bits */
13964 +uint32
13965 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13966 +{
13967 + sb_info_t *si;
13968 + uint regoff;
13969 +
13970 + si = SB_INFO(sbh);
13971 + regoff = 0;
13972 +
13973 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13974 +
13975 + /* gpios could be shared on router platforms */
13976 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13977 + mask = priority ? (sb_gpioreservation & mask) :
13978 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13979 + val &= mask;
13980 + }
13981 +
13982 + switch (si->gpioid) {
13983 + case SB_CC:
13984 + regoff = OFFSETOF(chipcregs_t, gpioouten);
13985 + break;
13986 +
13987 + case SB_PCI:
13988 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
13989 + break;
13990 +
13991 + case SB_EXTIF:
13992 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
13993 + break;
13994 + }
13995 +
13996 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13997 +}
13998 +
13999 +/* mask&set gpio output bits */
14000 +uint32
14001 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14002 +{
14003 + sb_info_t *si;
14004 + uint regoff;
14005 +
14006 + si = SB_INFO(sbh);
14007 + regoff = 0;
14008 +
14009 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14010 +
14011 + /* gpios could be shared on router platforms */
14012 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14013 + mask = priority ? (sb_gpioreservation & mask) :
14014 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14015 + val &= mask;
14016 + }
14017 +
14018 + switch (si->gpioid) {
14019 + case SB_CC:
14020 + regoff = OFFSETOF(chipcregs_t, gpioout);
14021 + break;
14022 +
14023 + case SB_PCI:
14024 + regoff = OFFSETOF(sbpciregs_t, gpioout);
14025 + break;
14026 +
14027 + case SB_EXTIF:
14028 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
14029 + break;
14030 + }
14031 +
14032 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14033 +}
14034 +
14035 +/* reserve one gpio */
14036 +uint32
14037 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14038 +{
14039 + sb_info_t *si;
14040 +
14041 + si = SB_INFO(sbh);
14042 +
14043 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14044 +
14045 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14046 + * reserve/release GPIO
14047 + */
14048 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14049 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14050 + return -1;
14051 + }
14052 + /* make sure only one bit is set */
14053 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14054 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14055 + return -1;
14056 + }
14057 +
14058 + /* already reserved */
14059 + if (sb_gpioreservation & gpio_bitmask)
14060 + return -1;
14061 + /* set reservation */
14062 + sb_gpioreservation |= gpio_bitmask;
14063 +
14064 + return sb_gpioreservation;
14065 +}
14066 +
14067 +/* release one gpio */
14068 +/*
14069 + * releasing the gpio doesn't change the current value on the GPIO last write value
14070 + * persists till some one overwrites it
14071 +*/
14072 +
14073 +uint32
14074 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14075 +{
14076 + sb_info_t *si;
14077 +
14078 + si = SB_INFO(sbh);
14079 +
14080 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14081 +
14082 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14083 + * reserve/release GPIO
14084 + */
14085 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14086 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14087 + return -1;
14088 + }
14089 + /* make sure only one bit is set */
14090 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14091 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14092 + return -1;
14093 + }
14094 +
14095 + /* already released */
14096 + if (!(sb_gpioreservation & gpio_bitmask))
14097 + return -1;
14098 +
14099 + /* clear reservation */
14100 + sb_gpioreservation &= ~gpio_bitmask;
14101 +
14102 + return sb_gpioreservation;
14103 +}
14104 +
14105 +/* return the current gpioin register value */
14106 +uint32
14107 +sb_gpioin(sb_t *sbh)
14108 +{
14109 + sb_info_t *si;
14110 + uint regoff;
14111 +
14112 + si = SB_INFO(sbh);
14113 + regoff = 0;
14114 +
14115 + switch (si->gpioid) {
14116 + case SB_CC:
14117 + regoff = OFFSETOF(chipcregs_t, gpioin);
14118 + break;
14119 +
14120 + case SB_PCI:
14121 + regoff = OFFSETOF(sbpciregs_t, gpioin);
14122 + break;
14123 +
14124 + case SB_EXTIF:
14125 + regoff = OFFSETOF(extifregs_t, gpioin);
14126 + break;
14127 + }
14128 +
14129 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
14130 +}
14131 +
14132 +/* mask&set gpio interrupt polarity bits */
14133 +uint32
14134 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14135 +{
14136 + sb_info_t *si;
14137 + uint regoff;
14138 +
14139 + si = SB_INFO(sbh);
14140 + regoff = 0;
14141 +
14142 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14143 +
14144 + /* gpios could be shared on router platforms */
14145 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14146 + mask = priority ? (sb_gpioreservation & mask) :
14147 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14148 + val &= mask;
14149 + }
14150 +
14151 + switch (si->gpioid) {
14152 + case SB_CC:
14153 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
14154 + break;
14155 +
14156 + case SB_PCI:
14157 + /* pci gpio implementation does not support interrupt polarity */
14158 + ASSERT(0);
14159 + break;
14160 +
14161 + case SB_EXTIF:
14162 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
14163 + break;
14164 + }
14165 +
14166 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14167 +}
14168 +
14169 +/* mask&set gpio interrupt mask bits */
14170 +uint32
14171 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14172 +{
14173 + sb_info_t *si;
14174 + uint regoff;
14175 +
14176 + si = SB_INFO(sbh);
14177 + regoff = 0;
14178 +
14179 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14180 +
14181 + /* gpios could be shared on router platforms */
14182 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14183 + mask = priority ? (sb_gpioreservation & mask) :
14184 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14185 + val &= mask;
14186 + }
14187 +
14188 + switch (si->gpioid) {
14189 + case SB_CC:
14190 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
14191 + break;
14192 +
14193 + case SB_PCI:
14194 + /* pci gpio implementation does not support interrupt mask */
14195 + ASSERT(0);
14196 + break;
14197 +
14198 + case SB_EXTIF:
14199 + regoff = OFFSETOF(extifregs_t, gpiointmask);
14200 + break;
14201 + }
14202 +
14203 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14204 +}
14205 +
14206 +/* assign the gpio to an led */
14207 +uint32
14208 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
14209 +{
14210 + sb_info_t *si;
14211 +
14212 + si = SB_INFO(sbh);
14213 + if (si->sb.ccrev < 16)
14214 + return -1;
14215 +
14216 + /* gpio led powersave reg */
14217 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
14218 +}
14219 +
14220 +/* mask & set gpio timer val */
14221 +uint32
14222 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
14223 +{
14224 + sb_info_t *si;
14225 + si = SB_INFO(sbh);
14226 +
14227 + if (si->sb.ccrev < 16)
14228 + return -1;
14229 +
14230 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
14231 +}
14232 +
14233 +
14234 +/* return the slow clock source - LPO, XTAL, or PCI */
14235 +static uint
14236 +sb_slowclk_src(sb_info_t *si)
14237 +{
14238 + chipcregs_t *cc;
14239 +
14240 +
14241 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14242 +
14243 + if (si->sb.ccrev < 6) {
14244 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS) &&
14245 + (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32)) &
14246 + PCI_CFG_GPIO_SCS))
14247 + return (SCC_SS_PCI);
14248 + else
14249 + return (SCC_SS_XTAL);
14250 + } else if (si->sb.ccrev < 10) {
14251 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14252 + return (R_REG(si->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);
14253 + } else /* Insta-clock */
14254 + return (SCC_SS_XTAL);
14255 +}
14256 +
14257 +/* return the ILP (slowclock) min or max frequency */
14258 +static uint
14259 +sb_slowclk_freq(sb_info_t *si, bool max)
14260 +{
14261 + chipcregs_t *cc;
14262 + uint32 slowclk;
14263 + uint div;
14264 +
14265 +
14266 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14267 +
14268 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14269 +
14270 + /* shouldn't be here unless we've established the chip has dynamic clk control */
14271 + ASSERT(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL);
14272 +
14273 + slowclk = sb_slowclk_src(si);
14274 + if (si->sb.ccrev < 6) {
14275 + if (slowclk == SCC_SS_PCI)
14276 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
14277 + else
14278 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
14279 + } else if (si->sb.ccrev < 10) {
14280 + div = 4 * (((R_REG(si->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
14281 + if (slowclk == SCC_SS_LPO)
14282 + return (max? LPOMAXFREQ : LPOMINFREQ);
14283 + else if (slowclk == SCC_SS_XTAL)
14284 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
14285 + else if (slowclk == SCC_SS_PCI)
14286 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
14287 + else
14288 + ASSERT(0);
14289 + } else {
14290 + /* Chipc rev 10 is InstaClock */
14291 + div = R_REG(si->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
14292 + div = 4 * (div + 1);
14293 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
14294 + }
14295 + return (0);
14296 +}
14297 +
14298 +static void
14299 +BCMINITFN(sb_clkctl_setdelay)(sb_info_t *si, void *chipcregs)
14300 +{
14301 + chipcregs_t * cc;
14302 + uint slowmaxfreq, pll_delay, slowclk;
14303 + uint pll_on_delay, fref_sel_delay;
14304 +
14305 + pll_delay = PLL_DELAY;
14306 +
14307 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
14308 + * since the xtal will also be powered down by dynamic clk control logic.
14309 + */
14310 +
14311 + slowclk = sb_slowclk_src(si);
14312 + if (slowclk != SCC_SS_XTAL)
14313 + pll_delay += XTAL_ON_DELAY;
14314 +
14315 + /* Starting with 4318 it is ILP that is used for the delays */
14316 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
14317 +
14318 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
14319 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
14320 +
14321 + cc = (chipcregs_t *)chipcregs;
14322 + W_REG(si->osh, &cc->pll_on_delay, pll_on_delay);
14323 + W_REG(si->osh, &cc->fref_sel_delay, fref_sel_delay);
14324 +}
14325 +
14326 +/* initialize power control delay registers */
14327 +void
14328 +BCMINITFN(sb_clkctl_init)(sb_t *sbh)
14329 +{
14330 + sb_info_t *si;
14331 + uint origidx;
14332 + chipcregs_t *cc;
14333 +
14334 + si = SB_INFO(sbh);
14335 +
14336 + origidx = si->curidx;
14337 +
14338 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14339 + return;
14340 +
14341 + if ((si->sb.chip == BCM4321_CHIP_ID) && (si->sb.chiprev < 2))
14342 + W_REG(si->osh, &cc->chipcontrol,
14343 + (si->sb.chiprev == 0) ? CHIPCTRL_4321A0_DEFAULT : CHIPCTRL_4321A1_DEFAULT);
14344 +
14345 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14346 + goto done;
14347 +
14348 + /* set all Instaclk chip ILP to 1 MHz */
14349 + else if (si->sb.ccrev >= 10)
14350 + SET_REG(si->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
14351 + (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
14352 +
14353 + sb_clkctl_setdelay(si, (void *)cc);
14354 +
14355 +done:
14356 + sb_setcoreidx(sbh, origidx);
14357 +}
14358 +
14359 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
14360 +uint16
14361 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
14362 +{
14363 + sb_info_t *si;
14364 + uint origidx;
14365 + chipcregs_t *cc;
14366 + uint slowminfreq;
14367 + uint16 fpdelay;
14368 + uint intr_val = 0;
14369 +
14370 + si = SB_INFO(sbh);
14371 + fpdelay = 0;
14372 + origidx = si->curidx;
14373 +
14374 + INTR_OFF(si, intr_val);
14375 +
14376 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14377 + goto done;
14378 +
14379 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14380 + goto done;
14381 +
14382 + slowminfreq = sb_slowclk_freq(si, FALSE);
14383 + fpdelay = (((R_REG(si->osh, &cc->pll_on_delay) + 2) * 1000000) +
14384 + (slowminfreq - 1)) / slowminfreq;
14385 +
14386 +done:
14387 + sb_setcoreidx(sbh, origidx);
14388 + INTR_RESTORE(si, intr_val);
14389 + return (fpdelay);
14390 +}
14391 +
14392 +/* turn primary xtal and/or pll off/on */
14393 +int
14394 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
14395 +{
14396 + sb_info_t *si;
14397 + uint32 in, out, outen;
14398 +
14399 + si = SB_INFO(sbh);
14400 +
14401 + switch (BUSTYPE(si->sb.bustype)) {
14402 +
14403 +
14404 + case PCMCIA_BUS:
14405 + return (0);
14406 +
14407 +
14408 + case PCI_BUS:
14409 +
14410 + /* pcie core doesn't have any mapping to control the xtal pu */
14411 + if (PCIE(si))
14412 + return -1;
14413 +
14414 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof(uint32));
14415 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32));
14416 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32));
14417 +
14418 + /*
14419 + * Avoid glitching the clock if GPRS is already using it.
14420 + * We can't actually read the state of the PLLPD so we infer it
14421 + * by the value of XTAL_PU which *is* readable via gpioin.
14422 + */
14423 + if (on && (in & PCI_CFG_GPIO_XTAL))
14424 + return (0);
14425 +
14426 + if (what & XTAL)
14427 + outen |= PCI_CFG_GPIO_XTAL;
14428 + if (what & PLL)
14429 + outen |= PCI_CFG_GPIO_PLL;
14430 +
14431 + if (on) {
14432 + /* turn primary xtal on */
14433 + if (what & XTAL) {
14434 + out |= PCI_CFG_GPIO_XTAL;
14435 + if (what & PLL)
14436 + out |= PCI_CFG_GPIO_PLL;
14437 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14438 + sizeof(uint32), out);
14439 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN,
14440 + sizeof(uint32), outen);
14441 + OSL_DELAY(XTAL_ON_DELAY);
14442 + }
14443 +
14444 + /* turn pll on */
14445 + if (what & PLL) {
14446 + out &= ~PCI_CFG_GPIO_PLL;
14447 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14448 + sizeof(uint32), out);
14449 + OSL_DELAY(2000);
14450 + }
14451 + } else {
14452 + if (what & XTAL)
14453 + out &= ~PCI_CFG_GPIO_XTAL;
14454 + if (what & PLL)
14455 + out |= PCI_CFG_GPIO_PLL;
14456 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32), out);
14457 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32),
14458 + outen);
14459 + }
14460 +
14461 + default:
14462 + return (-1);
14463 + }
14464 +
14465 + return (0);
14466 +}
14467 +
14468 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
14469 +/* returns true if we are forcing fast clock */
14470 +bool
14471 +sb_clkctl_clk(sb_t *sbh, uint mode)
14472 +{
14473 + sb_info_t *si;
14474 + uint origidx;
14475 + chipcregs_t *cc;
14476 + uint32 scc;
14477 + uint intr_val = 0;
14478 +
14479 + si = SB_INFO(sbh);
14480 +
14481 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
14482 + if (si->sb.ccrev < 6)
14483 + return (FALSE);
14484 +
14485 +
14486 + /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */
14487 + ASSERT(si->sb.ccrev != 10);
14488 +
14489 + INTR_OFF(si, intr_val);
14490 +
14491 + origidx = si->curidx;
14492 +
14493 + if (sb_setcore(sbh, SB_MIPS33, 0) && (sb_corerev(&si->sb) <= 7) &&
14494 + (BUSTYPE(si->sb.bustype) == SB_BUS) && (si->sb.ccrev >= 10))
14495 + goto done;
14496 +
14497 + /* PR32414WAR "Force HT clock on" all the time, no dynamic clk ctl */
14498 + if ((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev <= 1))
14499 + goto done;
14500 +
14501 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
14502 + ASSERT(cc != NULL);
14503 +
14504 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14505 + goto done;
14506 +
14507 + switch (mode) {
14508 + case CLK_FAST: /* force fast (pll) clock */
14509 + if (si->sb.ccrev < 10) {
14510 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
14511 + sb_clkctl_xtal(&si->sb, XTAL, ON);
14512 +
14513 + SET_REG(si->osh, &cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
14514 + } else
14515 + OR_REG(si->osh, &cc->system_clk_ctl, SYCC_HR);
14516 + /* wait for the PLL */
14517 + OSL_DELAY(PLL_DELAY);
14518 + break;
14519 +
14520 + case CLK_DYNAMIC: /* enable dynamic clock control */
14521 +
14522 + if (si->sb.ccrev < 10) {
14523 + scc = R_REG(si->osh, &cc->slow_clk_ctl);
14524 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
14525 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
14526 + scc |= SCC_XC;
14527 + W_REG(si->osh, &cc->slow_clk_ctl, scc);
14528 +
14529 + /* for dynamic control, we have to release our xtal_pu "force on" */
14530 + if (scc & SCC_XC)
14531 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
14532 + } else {
14533 + /* Instaclock */
14534 + AND_REG(si->osh, &cc->system_clk_ctl, ~SYCC_HR);
14535 + }
14536 + break;
14537 +
14538 + default:
14539 + ASSERT(0);
14540 + }
14541 +
14542 +done:
14543 + sb_setcoreidx(sbh, origidx);
14544 + INTR_RESTORE(si, intr_val);
14545 + return (mode == CLK_FAST);
14546 +}
14547 +
14548 +/* register driver interrupt disabling and restoring callback functions */
14549 +void
14550 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
14551 + void *intrsenabled_fn, void *intr_arg)
14552 +{
14553 + sb_info_t *si;
14554 +
14555 + si = SB_INFO(sbh);
14556 + si->intr_arg = intr_arg;
14557 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
14558 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
14559 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
14560 + /* save current core id. when this function called, the current core
14561 + * must be the core which provides driver functions(il, et, wl, etc.)
14562 + */
14563 + si->dev_coreid = si->coreid[si->curidx];
14564 +}
14565 +
14566 +
14567 +int
14568 +sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
14569 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
14570 + uint8 *pciheader)
14571 +{
14572 + uint16 vendor = 0xffff, device = 0xffff;
14573 + uint core, unit;
14574 + uint chip, chippkg;
14575 + uint nfunc;
14576 + char varname[SB_DEVPATH_BUFSZ + 8];
14577 + uint8 class, subclass, progif;
14578 + char devpath[SB_DEVPATH_BUFSZ];
14579 + uint8 header;
14580 +
14581 + core = sb_coreid(sbh);
14582 + unit = sb_coreunit(sbh);
14583 +
14584 + chip = sb_chip(sbh);
14585 + chippkg = sb_chippkg(sbh);
14586 +
14587 + progif = 0;
14588 + header = PCI_HEADER_NORMAL;
14589 +
14590 + /* Verify whether the function exists for the core */
14591 + nfunc = (core == SB_USB20H) ? 2 : 1;
14592 + if (func >= nfunc)
14593 + return BCME_ERROR;
14594 +
14595 + /* Known vendor translations */
14596 + switch (sb_corevendor(sbh)) {
14597 + case SB_VEND_BCM:
14598 + vendor = VENDOR_BROADCOM;
14599 + break;
14600 + default:
14601 + return BCME_ERROR;
14602 + }
14603 +
14604 + /* Determine class based on known core codes */
14605 + switch (core) {
14606 + case SB_ILINE20:
14607 + class = PCI_CLASS_NET;
14608 + subclass = PCI_NET_ETHER;
14609 + device = BCM47XX_ILINE_ID;
14610 + break;
14611 + case SB_ENET:
14612 + class = PCI_CLASS_NET;
14613 + subclass = PCI_NET_ETHER;
14614 + device = BCM47XX_ENET_ID;
14615 + break;
14616 + case SB_GIGETH:
14617 + class = PCI_CLASS_NET;
14618 + subclass = PCI_NET_ETHER;
14619 + device = BCM47XX_GIGETH_ID;
14620 + break;
14621 + case SB_SDRAM:
14622 + case SB_MEMC:
14623 + class = PCI_CLASS_MEMORY;
14624 + subclass = PCI_MEMORY_RAM;
14625 + device = (uint16)core;
14626 + break;
14627 + case SB_PCI:
14628 + case SB_PCIE:
14629 + class = PCI_CLASS_BRIDGE;
14630 + subclass = PCI_BRIDGE_PCI;
14631 + device = (uint16)core;
14632 + header = PCI_HEADER_BRIDGE;
14633 + break;
14634 + case SB_MIPS:
14635 + case SB_MIPS33:
14636 + class = PCI_CLASS_CPU;
14637 + subclass = PCI_CPU_MIPS;
14638 + device = (uint16)core;
14639 + break;
14640 + case SB_CODEC:
14641 + class = PCI_CLASS_COMM;
14642 + subclass = PCI_COMM_MODEM;
14643 + device = BCM47XX_V90_ID;
14644 + break;
14645 + case SB_USB:
14646 + class = PCI_CLASS_SERIAL;
14647 + subclass = PCI_SERIAL_USB;
14648 + progif = 0x10; /* OHCI */
14649 + device = BCM47XX_USB_ID;
14650 + break;
14651 + case SB_USB11H:
14652 + class = PCI_CLASS_SERIAL;
14653 + subclass = PCI_SERIAL_USB;
14654 + progif = 0x10; /* OHCI */
14655 + device = BCM47XX_USBH_ID;
14656 + break;
14657 + case SB_USB20H:
14658 + class = PCI_CLASS_SERIAL;
14659 + subclass = PCI_SERIAL_USB;
14660 + progif = func == 0 ? 0x10 : 0x20; /* OHCI/EHCI */
14661 + device = BCM47XX_USB20H_ID;
14662 + header = 0x80; /* multifunction */
14663 + break;
14664 + case SB_USB11D:
14665 + class = PCI_CLASS_SERIAL;
14666 + subclass = PCI_SERIAL_USB;
14667 + device = BCM47XX_USBD_ID;
14668 + break;
14669 + case SB_USB20D:
14670 + class = PCI_CLASS_SERIAL;
14671 + subclass = PCI_SERIAL_USB;
14672 + device = BCM47XX_USB20D_ID;
14673 + break;
14674 + case SB_IPSEC:
14675 + class = PCI_CLASS_CRYPT;
14676 + subclass = PCI_CRYPT_NETWORK;
14677 + device = BCM47XX_IPSEC_ID;
14678 + break;
14679 + case SB_ROBO:
14680 + class = PCI_CLASS_NET;
14681 + subclass = PCI_NET_OTHER;
14682 + device = BCM47XX_ROBO_ID;
14683 + break;
14684 + case SB_EXTIF:
14685 + case SB_CC:
14686 + class = PCI_CLASS_MEMORY;
14687 + subclass = PCI_MEMORY_FLASH;
14688 + device = (uint16)core;
14689 + break;
14690 + case SB_D11:
14691 + class = PCI_CLASS_NET;
14692 + subclass = PCI_NET_OTHER;
14693 + /* Let nvram variable override core ID */
14694 + sb_devpath(sbh, devpath, sizeof(devpath));
14695 + sprintf(varname, "%sdevid", devpath);
14696 + if ((device = (uint16)getintvar(NULL, varname)))
14697 + break;
14698 + /*
14699 + * no longer support wl%did, but keep the code
14700 + * here for backward compatibility.
14701 + */
14702 + sprintf(varname, "wl%did", unit);
14703 + if ((device = (uint16)getintvar(NULL, varname)))
14704 + break;
14705 + /* Chip specific conversion */
14706 + if (chip == BCM4712_CHIP_ID) {
14707 + if (chippkg == BCM4712SMALL_PKG_ID)
14708 + device = BCM4306_D11G_ID;
14709 + else
14710 + device = BCM4306_D11DUAL_ID;
14711 + break;
14712 + }
14713 + /* ignore it */
14714 + device = 0xffff;
14715 + break;
14716 + case SB_SATAXOR:
14717 + class = PCI_CLASS_XOR;
14718 + subclass = PCI_XOR_QDMA;
14719 + device = BCM47XX_SATAXOR_ID;
14720 + break;
14721 + case SB_ATA100:
14722 + class = PCI_CLASS_DASDI;
14723 + subclass = PCI_DASDI_IDE;
14724 + device = BCM47XX_ATA100_ID;
14725 + break;
14726 +
14727 + default:
14728 + class = subclass = progif = 0xff;
14729 + device = (uint16)core;
14730 + break;
14731 + }
14732 +
14733 + *pcivendor = vendor;
14734 + *pcidevice = device;
14735 + *pciclass = class;
14736 + *pcisubclass = subclass;
14737 + *pciprogif = progif;
14738 + *pciheader = header;
14739 +
14740 + return 0;
14741 +}
14742 +
14743 +
14744 +
14745 +/* use the mdio interface to write to mdio slaves */
14746 +static int
14747 +sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint regaddr, uint val)
14748 +{
14749 + uint mdiodata;
14750 + uint i = 0;
14751 + sbpcieregs_t *pcieregs;
14752 +
14753 + pcieregs = (sbpcieregs_t*) sb_setcoreidx(&si->sb, si->sb.buscoreidx);
14754 + ASSERT(pcieregs);
14755 +
14756 + /* enable mdio access to SERDES */
14757 + W_REG(si->osh, (&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
14758 +
14759 + mdiodata = MDIODATA_START | MDIODATA_WRITE |
14760 + (physmedia << MDIODATA_DEVADDR_SHF) |
14761 + (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val;
14762 +
14763 + W_REG(si->osh, (&pcieregs->mdiodata), mdiodata);
14764 +
14765 + PR28829_DELAY();
14766 +
14767 + /* retry till the transaction is complete */
14768 + while (i < 10) {
14769 + if (R_REG(si->osh, &(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
14770 + /* Disable mdio access to SERDES */
14771 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14772 + return 0;
14773 + }
14774 + OSL_DELAY(1000);
14775 + i++;
14776 + }
14777 +
14778 + SB_ERROR(("sb_pcie_mdiowrite: timed out\n"));
14779 + /* Disable mdio access to SERDES */
14780 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14781 + ASSERT(0);
14782 + return 1;
14783 +
14784 +}
14785 +
14786 +/* indirect way to read pcie config regs */
14787 +uint
14788 +sb_pcie_readreg(void *sb, void* arg1, uint offset)
14789 +{
14790 + sb_info_t *si;
14791 + sb_t *sbh;
14792 + uint retval = 0xFFFFFFFF;
14793 + sbpcieregs_t *pcieregs;
14794 + uint addrtype;
14795 +
14796 + sbh = (sb_t *)sb;
14797 + si = SB_INFO(sbh);
14798 + ASSERT(PCIE(si));
14799 +
14800 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14801 + ASSERT(pcieregs);
14802 +
14803 + addrtype = (uint)((uintptr)arg1);
14804 + switch (addrtype) {
14805 + case PCIE_CONFIGREGS:
14806 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14807 + retval = R_REG(si->osh, &(pcieregs->configdata));
14808 + break;
14809 + case PCIE_PCIEREGS:
14810 + W_REG(si->osh, &(pcieregs->pcieaddr), offset);
14811 + retval = R_REG(si->osh, &(pcieregs->pciedata));
14812 + break;
14813 + default:
14814 + ASSERT(0);
14815 + break;
14816 + }
14817 + return retval;
14818 +}
14819 +
14820 +/* indirect way to write pcie config/mdio/pciecore regs */
14821 +uint
14822 +sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
14823 +{
14824 + sb_info_t *si;
14825 + sbpcieregs_t *pcieregs;
14826 + uint addrtype;
14827 +
14828 + si = SB_INFO(sbh);
14829 + ASSERT(PCIE(si));
14830 +
14831 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14832 + ASSERT(pcieregs);
14833 +
14834 + addrtype = (uint)((uintptr)arg1);
14835 +
14836 + switch (addrtype) {
14837 + case PCIE_CONFIGREGS:
14838 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14839 + W_REG(si->osh, (&pcieregs->configdata), val);
14840 + break;
14841 + case PCIE_PCIEREGS:
14842 + W_REG(si->osh, (&pcieregs->pcieaddr), offset);
14843 + W_REG(si->osh, (&pcieregs->pciedata), val);
14844 + break;
14845 + default:
14846 + ASSERT(0);
14847 + break;
14848 + }
14849 + return 0;
14850 +}
14851 +
14852 +/* Build device path. Support SB, PCI, and JTAG for now. */
14853 +int
14854 +sb_devpath(sb_t *sbh, char *path, int size)
14855 +{
14856 + ASSERT(path);
14857 + ASSERT(size >= SB_DEVPATH_BUFSZ);
14858 +
14859 + switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
14860 + case SB_BUS:
14861 + case JTAG_BUS:
14862 + sprintf(path, "sb/%u/", sb_coreidx(sbh));
14863 + break;
14864 + case PCI_BUS:
14865 + ASSERT((SB_INFO(sbh))->osh);
14866 + sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
14867 + OSL_PCI_SLOT((SB_INFO(sbh))->osh));
14868 + break;
14869 + case PCMCIA_BUS:
14870 + SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n"));
14871 + SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n"));
14872 + sprintf(path, "pc/%u/%u/", 1, 1);
14873 + break;
14874 + case SDIO_BUS:
14875 + SB_ERROR(("sb_devpath: device 0 assumed\n"));
14876 + sprintf(path, "sd/%u/", sb_coreidx(sbh));
14877 + break;
14878 + default:
14879 + ASSERT(0);
14880 + break;
14881 + }
14882 +
14883 + return 0;
14884 +}
14885 +
14886 +/*
14887 + * Fixup SROMless PCI device's configuration.
14888 + * The current core may be changed upon return.
14889 + */
14890 +static int
14891 +sb_pci_fixcfg(sb_info_t *si)
14892 +{
14893 + uint origidx, pciidx;
14894 + sbpciregs_t *pciregs;
14895 + sbpcieregs_t *pcieregs;
14896 + uint16 val16, *reg16;
14897 + char name[SB_DEVPATH_BUFSZ+16], *value;
14898 + char devpath[SB_DEVPATH_BUFSZ];
14899 +
14900 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
14901 +
14902 + /* Fixup PI in SROM shadow area to enable the correct PCI core access */
14903 + /* save the current index */
14904 + origidx = sb_coreidx(&si->sb);
14905 +
14906 + /* check 'pi' is correct and fix it if not */
14907 + if (si->sb.buscoretype == SB_PCIE) {
14908 + pcieregs = (sbpcieregs_t *)sb_setcore(&si->sb, SB_PCIE, 0);
14909 + ASSERT(pcieregs);
14910 + reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
14911 + } else if (si->sb.buscoretype == SB_PCI) {
14912 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
14913 + ASSERT(pciregs);
14914 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
14915 + } else {
14916 + ASSERT(0);
14917 + return -1;
14918 + }
14919 + pciidx = sb_coreidx(&si->sb);
14920 + val16 = R_REG(si->osh, reg16);
14921 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
14922 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
14923 + W_REG(si->osh, reg16, val16);
14924 + }
14925 +
14926 + /* restore the original index */
14927 + sb_setcoreidx(&si->sb, origidx);
14928 +
14929 + /*
14930 + * Fixup bar0window in PCI config space to make the core indicated
14931 + * by the nvram variable the current core.
14932 + * !Do it last, it may change the current core!
14933 + */
14934 + if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
14935 + return -1;
14936 + sprintf(name, "%sb0w", devpath);
14937 + if ((value = getvar(NULL, name))) {
14938 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
14939 + bcm_strtoul(value, NULL, 16));
14940 + /* update curidx since the current core is changed */
14941 + si->curidx = _sb_coreidx(si);
14942 + if (si->curidx == BADIDX) {
14943 + SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
14944 + return -1;
14945 + }
14946 + }
14947 +
14948 + return 0;
14949 +}
14950 +
14951 +static uint
14952 +sb_chipc_capability(sb_t *sbh)
14953 +{
14954 + sb_info_t *si;
14955 +
14956 + si = SB_INFO(sbh);
14957 +
14958 + /* Make sure that there is ChipCommon core present */
14959 + if (si->coreid[SB_CC_IDX] == SB_CC)
14960 + return (sb_corereg(si, SB_CC_IDX, OFFSETOF(chipcregs_t, capabilities),
14961 + 0, 0));
14962 + return 0;
14963 +}
14964 +
14965 +/* Return ADDR64 capability of the backplane */
14966 +bool
14967 +sb_backplane64(sb_t *sbh)
14968 +{
14969 + return ((sb_chipc_capability(sbh) & CAP_BKPLN64) != 0);
14970 +}
14971 +
14972 +void
14973 +sb_btcgpiowar(sb_t *sbh)
14974 +{
14975 + sb_info_t *si;
14976 + uint origidx;
14977 + uint intr_val = 0;
14978 + chipcregs_t *cc;
14979 + si = SB_INFO(sbh);
14980 +
14981 + /* Make sure that there is ChipCommon core present &&
14982 + * UART_TX is strapped to 1
14983 + */
14984 + if (!(sb_chipc_capability(sbh) & CAP_UARTGPIO))
14985 + return;
14986 +
14987 + /* sb_corereg cannot be used as we have to guarantee 8-bit read/writes */
14988 + INTR_OFF(si, intr_val);
14989 +
14990 + origidx = sb_coreidx(sbh);
14991 +
14992 + cc = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
14993 + if (cc == NULL)
14994 + goto end;
14995 +
14996 + W_REG(si->osh, &cc->uart0mcr, R_REG(si->osh, &cc->uart0mcr) | 0x04);
14997 +
14998 +end:
14999 + /* restore the original index */
15000 + sb_setcoreidx(sbh, origidx);
15001 +
15002 + INTR_RESTORE(si, intr_val);
15003 +}
15004 +
15005 +/* check if the device is removed */
15006 +bool
15007 +sb_deviceremoved(sb_t *sbh)
15008 +{
15009 + uint32 w;
15010 + sb_info_t *si;
15011 +
15012 + si = SB_INFO(sbh);
15013 +
15014 + switch (BUSTYPE(si->sb.bustype)) {
15015 + case PCI_BUS:
15016 + ASSERT(si->osh);
15017 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_VID, sizeof(uint32));
15018 + if ((w & 0xFFFF) != VENDOR_BROADCOM)
15019 + return TRUE;
15020 + else
15021 + return FALSE;
15022 + default:
15023 + return FALSE;
15024 + }
15025 + return FALSE;
15026 +}
15027 +
15028 +/* Return the RAM size of the SOCRAM core */
15029 +uint32
15030 +sb_socram_size(sb_t *sbh)
15031 +{
15032 + sb_info_t *si;
15033 + uint origidx;
15034 + uint intr_val = 0;
15035 +
15036 + sbsocramregs_t *regs;
15037 + bool wasup;
15038 + uint corerev;
15039 + uint32 coreinfo;
15040 + uint memsize = 0;
15041 +
15042 + si = SB_INFO(sbh);
15043 + ASSERT(si);
15044 +
15045 + /* Block ints and save current core */
15046 + INTR_OFF(si, intr_val);
15047 + origidx = sb_coreidx(sbh);
15048 +
15049 + /* Switch to SOCRAM core */
15050 + if (!(regs = sb_setcore(sbh, SB_SOCRAM, 0)))
15051 + goto done;
15052 +
15053 + /* Get info for determining size */
15054 + if (!(wasup = sb_iscoreup(sbh)))
15055 + sb_core_reset(sbh, 0, 0);
15056 + corerev = sb_corerev(sbh);
15057 + coreinfo = R_REG(si->osh, &regs->coreinfo);
15058 +
15059 + /* Calculate size from coreinfo based on rev */
15060 + switch (corerev) {
15061 + case 0:
15062 + memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK));
15063 + break;
15064 + default: /* rev >= 1 */
15065 + memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK));
15066 + memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
15067 + break;
15068 + }
15069 +
15070 + /* Return to previous state and core */
15071 + if (!wasup)
15072 + sb_core_disable(sbh, 0);
15073 + sb_setcoreidx(sbh, origidx);
15074 +
15075 +done:
15076 + INTR_RESTORE(si, intr_val);
15077 + return memsize;
15078 +}
15079 +
15080 +
15081 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
15082 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
15083 +++ linux.dev/arch/mips/bcm947xx/setup.c 2006-10-02 21:19:59.000000000 +0200
15084 @@ -0,0 +1,241 @@
15085 +/*
15086 + * Generic setup routines for Broadcom MIPS boards
15087 + *
15088 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
15089 + *
15090 + * This program is free software; you can redistribute it and/or modify it
15091 + * under the terms of the GNU General Public License as published by the
15092 + * Free Software Foundation; either version 2 of the License, or (at your
15093 + * option) any later version.
15094 + *
15095 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15096 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15097 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15098 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15099 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15100 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15101 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
15102 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15103 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
15104 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15105 + *
15106 + * You should have received a copy of the GNU General Public License along
15107 + * with this program; if not, write to the Free Software Foundation, Inc.,
15108 + * 675 Mass Ave, Cambridge, MA 02139, USA.
15109 + *
15110 + *
15111 + * Copyright 2005, Broadcom Corporation
15112 + * All Rights Reserved.
15113 + *
15114 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15115 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15116 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15117 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15118 + *
15119 + */
15120 +
15121 +#include <linux/config.h>
15122 +#include <linux/init.h>
15123 +#include <linux/kernel.h>
15124 +#include <linux/module.h>
15125 +#include <linux/serialP.h>
15126 +#include <linux/ide.h>
15127 +#include <asm/bootinfo.h>
15128 +#include <asm/cpu.h>
15129 +#include <asm/time.h>
15130 +#include <asm/reboot.h>
15131 +
15132 +#include <typedefs.h>
15133 +#include <osl.h>
15134 +#include <sbutils.h>
15135 +#include <bcmutils.h>
15136 +#include <bcmnvram.h>
15137 +#include <sbhndmips.h>
15138 +#include <hndmips.h>
15139 +#include <trxhdr.h>
15140 +
15141 +/* Virtual IRQ base, after last hw IRQ */
15142 +#define SBMIPS_VIRTIRQ_BASE 6
15143 +
15144 +/* # IRQs, hw and sw IRQs */
15145 +#define SBMIPS_NUMIRQS 8
15146 +
15147 +/* Global SB handle */
15148 +sb_t *bcm947xx_sbh = NULL;
15149 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
15150 +
15151 +/* Convenience */
15152 +#define sbh bcm947xx_sbh
15153 +#define sbh_lock bcm947xx_sbh_lock
15154 +
15155 +extern void bcm947xx_time_init(void);
15156 +extern void bcm947xx_timer_setup(struct irqaction *irq);
15157 +
15158 +#ifdef CONFIG_REMOTE_DEBUG
15159 +extern void set_debug_traps(void);
15160 +extern void rs_kgdb_hook(struct serial_state *);
15161 +extern void breakpoint(void);
15162 +#endif
15163 +
15164 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15165 +extern struct ide_ops std_ide_ops;
15166 +#endif
15167 +
15168 +/* Kernel command line */
15169 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
15170 +extern void sb_serial_init(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
15171 +
15172 +void
15173 +bcm947xx_machine_restart(char *command)
15174 +{
15175 + printk("Please stand by while rebooting the system...\n");
15176 +
15177 + /* Set the watchdog timer to reset immediately */
15178 + __cli();
15179 + sb_watchdog(sbh, 1);
15180 + while (1);
15181 +}
15182 +
15183 +void
15184 +bcm947xx_machine_halt(void)
15185 +{
15186 + printk("System halted\n");
15187 +
15188 + /* Disable interrupts and watchdog and spin forever */
15189 + __cli();
15190 + sb_watchdog(sbh, 0);
15191 + while (1);
15192 +}
15193 +
15194 +#ifdef CONFIG_SERIAL
15195 +
15196 +static int ser_line = 0;
15197 +
15198 +typedef struct {
15199 + void *regs;
15200 + uint irq;
15201 + uint baud_base;
15202 + uint reg_shift;
15203 +} serial_port;
15204 +
15205 +static serial_port ports[4];
15206 +static int num_ports = 0;
15207 +
15208 +static void
15209 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
15210 +{
15211 + ports[num_ports].regs = regs;
15212 + ports[num_ports].irq = irq;
15213 + ports[num_ports].baud_base = baud_base;
15214 + ports[num_ports].reg_shift = reg_shift;
15215 + num_ports++;
15216 +}
15217 +
15218 +static void
15219 +do_serial_add(serial_port *port)
15220 +{
15221 + void *regs;
15222 + uint irq;
15223 + uint baud_base;
15224 + uint reg_shift;
15225 + struct serial_struct s;
15226 +
15227 + regs = port->regs;
15228 + irq = port->irq;
15229 + baud_base = port->baud_base;
15230 + reg_shift = port->reg_shift;
15231 +
15232 + memset(&s, 0, sizeof(s));
15233 +
15234 + s.line = ser_line++;
15235 + s.iomem_base = regs;
15236 + s.irq = irq + 2;
15237 + s.baud_base = baud_base / 16;
15238 + s.flags = ASYNC_BOOT_AUTOCONF;
15239 + s.io_type = SERIAL_IO_MEM;
15240 + s.iomem_reg_shift = reg_shift;
15241 +
15242 + if (early_serial_setup(&s) != 0) {
15243 + printk(KERN_ERR "Serial setup failed!\n");
15244 + }
15245 +}
15246 +
15247 +#endif /* CONFIG_SERIAL */
15248 +
15249 +void __init
15250 +brcm_setup(void)
15251 +{
15252 + char *s;
15253 + int i;
15254 + char *value;
15255 +
15256 + /* Get global SB handle */
15257 + sbh = sb_kattach();
15258 +
15259 + /* Initialize clocks and interrupts */
15260 + sb_mips_init(sbh, SBMIPS_VIRTIRQ_BASE);
15261 +
15262 + if (BCM330X(current_cpu_data.processor_id) &&
15263 + (read_c0_diag() & BRCM_PFC_AVAIL)) {
15264 + /*
15265 + * Now that the sbh is inited set the proper PFC value
15266 + */
15267 + printk("Setting the PFC to its default value\n");
15268 + enable_pfc(PFC_AUTO);
15269 + }
15270 +
15271 +
15272 +#ifdef CONFIG_SERIAL
15273 + sb_serial_init(sbh, serial_add);
15274 +
15275 + /* reverse serial ports if nvram variable starts with console=ttyS1 */
15276 + /* Initialize UARTs */
15277 + s = nvram_get("kernel_args");
15278 + if (!s) s = "";
15279 + if (!strncmp(s, "console=ttyS1", 13)) {
15280 + for (i = num_ports; i; i--)
15281 + do_serial_add(&ports[i - 1]);
15282 + } else {
15283 + for (i = 0; i < num_ports; i++)
15284 + do_serial_add(&ports[i]);
15285 + }
15286 +#endif
15287 +
15288 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15289 + ide_ops = &std_ide_ops;
15290 +#endif
15291 +
15292 + /* Override default command line arguments */
15293 + value = nvram_get("kernel_cmdline");
15294 + if (value && strlen(value) && strncmp(value, "empty", 5))
15295 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
15296 +
15297 +
15298 + /* Generic setup */
15299 + _machine_restart = bcm947xx_machine_restart;
15300 + _machine_halt = bcm947xx_machine_halt;
15301 + _machine_power_off = bcm947xx_machine_halt;
15302 +
15303 + board_time_init = bcm947xx_time_init;
15304 + board_timer_setup = bcm947xx_timer_setup;
15305 +}
15306 +
15307 +const char *
15308 +get_system_type(void)
15309 +{
15310 + static char s[32];
15311 +
15312 + if (bcm947xx_sbh) {
15313 + sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
15314 + sb_chiprev(bcm947xx_sbh));
15315 + return s;
15316 + }
15317 + else
15318 + return "Broadcom BCM947XX";
15319 +}
15320 +
15321 +void __init
15322 +bus_error_init(void)
15323 +{
15324 +}
15325 +
15326 diff -urN linux.old/arch/mips/bcm947xx/sflash.c linux.dev/arch/mips/bcm947xx/sflash.c
15327 --- linux.old/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
15328 +++ linux.dev/arch/mips/bcm947xx/sflash.c 2006-10-02 21:19:59.000000000 +0200
15329 @@ -0,0 +1,422 @@
15330 +/*
15331 + * Broadcom SiliconBackplane chipcommon serial flash interface
15332 + *
15333 + * Copyright 2006, Broadcom Corporation
15334 + * All Rights Reserved.
15335 + *
15336 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15337 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15338 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15339 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15340 + *
15341 + * $Id: sflash.c,v 1.1.1.13 2006/02/27 03:43:16 honor Exp $
15342 + */
15343 +
15344 +#include <osl.h>
15345 +#include <typedefs.h>
15346 +#include <sbconfig.h>
15347 +#include <sbchipc.h>
15348 +#include <mipsinc.h>
15349 +#include <bcmutils.h>
15350 +#include <bcmdevs.h>
15351 +#include <sflash.h>
15352 +
15353 +/* Private global state */
15354 +static struct sflash sflash;
15355 +
15356 +/* Issue a serial flash command */
15357 +static INLINE void
15358 +sflash_cmd(chipcregs_t *cc, uint opcode)
15359 +{
15360 + W_REG(NULL, &cc->flashcontrol, SFLASH_START | opcode);
15361 + while (R_REG(NULL, &cc->flashcontrol) & SFLASH_BUSY);
15362 +}
15363 +
15364 +/* Initialize serial flash access */
15365 +struct sflash *
15366 +sflash_init(chipcregs_t *cc)
15367 +{
15368 + uint32 id, id2;
15369 +
15370 + bzero(&sflash, sizeof(sflash));
15371 +
15372 + sflash.type = R_REG(NULL, &cc->capabilities) & CAP_FLASH_MASK;
15373 +
15374 + switch (sflash.type) {
15375 + case SFLASH_ST:
15376 + /* Probe for ST chips */
15377 + sflash_cmd(cc, SFLASH_ST_DP);
15378 + sflash_cmd(cc, SFLASH_ST_RES);
15379 + id = R_REG(NULL, &cc->flashdata);
15380 + switch (id) {
15381 + case 0x11:
15382 + /* ST M25P20 2 Mbit Serial Flash */
15383 + sflash.blocksize = 64 * 1024;
15384 + sflash.numblocks = 4;
15385 + break;
15386 + case 0x12:
15387 + /* ST M25P40 4 Mbit Serial Flash */
15388 + sflash.blocksize = 64 * 1024;
15389 + sflash.numblocks = 8;
15390 + break;
15391 + case 0x13:
15392 + /* ST M25P80 8 Mbit Serial Flash */
15393 + sflash.blocksize = 64 * 1024;
15394 + sflash.numblocks = 16;
15395 + break;
15396 + case 0x14:
15397 + /* ST M25P16 16 Mbit Serial Flash */
15398 + sflash.blocksize = 64 * 1024;
15399 + sflash.numblocks = 32;
15400 + break;
15401 + case 0x15:
15402 + /* ST M25P32 32 Mbit Serial Flash */
15403 + sflash.blocksize = 64 * 1024;
15404 + sflash.numblocks = 64;
15405 + break;
15406 + case 0x16:
15407 + /* ST M25P64 64 Mbit Serial Flash */
15408 + sflash.blocksize = 64 * 1024;
15409 + sflash.numblocks = 128;
15410 + break;
15411 + case 0xbf:
15412 + W_REG(NULL, &cc->flashaddress, 1);
15413 + sflash_cmd(cc, SFLASH_ST_RES);
15414 + id2 = R_REG(NULL, &cc->flashdata);
15415 + if (id2 == 0x44) {
15416 + /* SST M25VF80 4 Mbit Serial Flash */
15417 + sflash.blocksize = 64 * 1024;
15418 + sflash.numblocks = 8;
15419 + }
15420 + break;
15421 + }
15422 + break;
15423 +
15424 + case SFLASH_AT:
15425 + /* Probe for Atmel chips */
15426 + sflash_cmd(cc, SFLASH_AT_STATUS);
15427 + id = R_REG(NULL, &cc->flashdata) & 0x3c;
15428 + switch (id) {
15429 + case 0xc:
15430 + /* Atmel AT45DB011 1Mbit Serial Flash */
15431 + sflash.blocksize = 256;
15432 + sflash.numblocks = 512;
15433 + break;
15434 + case 0x14:
15435 + /* Atmel AT45DB021 2Mbit Serial Flash */
15436 + sflash.blocksize = 256;
15437 + sflash.numblocks = 1024;
15438 + break;
15439 + case 0x1c:
15440 + /* Atmel AT45DB041 4Mbit Serial Flash */
15441 + sflash.blocksize = 256;
15442 + sflash.numblocks = 2048;
15443 + break;
15444 + case 0x24:
15445 + /* Atmel AT45DB081 8Mbit Serial Flash */
15446 + sflash.blocksize = 256;
15447 + sflash.numblocks = 4096;
15448 + break;
15449 + case 0x2c:
15450 + /* Atmel AT45DB161 16Mbit Serial Flash */
15451 + sflash.blocksize = 512;
15452 + sflash.numblocks = 4096;
15453 + break;
15454 + case 0x34:
15455 + /* Atmel AT45DB321 32Mbit Serial Flash */
15456 + sflash.blocksize = 512;
15457 + sflash.numblocks = 8192;
15458 + break;
15459 + case 0x3c:
15460 + /* Atmel AT45DB642 64Mbit Serial Flash */
15461 + sflash.blocksize = 1024;
15462 + sflash.numblocks = 8192;
15463 + break;
15464 + }
15465 + break;
15466 + }
15467 +
15468 + sflash.size = sflash.blocksize * sflash.numblocks;
15469 + return sflash.size ? &sflash : NULL;
15470 +}
15471 +
15472 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
15473 +int
15474 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
15475 +{
15476 + int cnt;
15477 + uint32 *from, *to;
15478 +
15479 + if (!len)
15480 + return 0;
15481 +
15482 + if ((offset + len) > sflash.size)
15483 + return -22;
15484 +
15485 + if ((len >= 4) && (offset & 3))
15486 + cnt = 4 - (offset & 3);
15487 + else if ((len >= 4) && ((uint32)buf & 3))
15488 + cnt = 4 - ((uint32)buf & 3);
15489 + else
15490 + cnt = len;
15491 +
15492 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
15493 + to = (uint32 *)buf;
15494 +
15495 + if (cnt < 4) {
15496 + bcopy(from, to, cnt);
15497 + return cnt;
15498 + }
15499 +
15500 + while (cnt >= 4) {
15501 + *to++ = *from++;
15502 + cnt -= 4;
15503 + }
15504 +
15505 + return (len - cnt);
15506 +}
15507 +
15508 +/* Poll for command completion. Returns zero when complete. */
15509 +int
15510 +sflash_poll(chipcregs_t *cc, uint offset)
15511 +{
15512 + if (offset >= sflash.size)
15513 + return -22;
15514 +
15515 + switch (sflash.type) {
15516 + case SFLASH_ST:
15517 + /* Check for ST Write In Progress bit */
15518 + sflash_cmd(cc, SFLASH_ST_RDSR);
15519 + return R_REG(NULL, &cc->flashdata) & SFLASH_ST_WIP;
15520 + case SFLASH_AT:
15521 + /* Check for Atmel Ready bit */
15522 + sflash_cmd(cc, SFLASH_AT_STATUS);
15523 + return !(R_REG(NULL, &cc->flashdata) & SFLASH_AT_READY);
15524 + }
15525 +
15526 + return 0;
15527 +}
15528 +
15529 +/* Write len bytes starting at offset into buf. Returns number of bytes
15530 + * written. Caller should poll for completion.
15531 + */
15532 +int
15533 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15534 +{
15535 + struct sflash *sfl;
15536 + int ret = 0;
15537 + bool is4712b0;
15538 + uint32 page, byte, mask;
15539 +
15540 + if (!len)
15541 + return 0;
15542 +
15543 + if ((offset + len) > sflash.size)
15544 + return -22;
15545 +
15546 + sfl = &sflash;
15547 + switch (sfl->type) {
15548 + case SFLASH_ST:
15549 + mask = R_REG(NULL, &cc->chipid);
15550 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_CHIP_ID) &&
15551 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
15552 + /* Enable writes */
15553 + sflash_cmd(cc, SFLASH_ST_WREN);
15554 + if (is4712b0) {
15555 + mask = 1 << 14;
15556 + W_REG(NULL, &cc->flashaddress, offset);
15557 + W_REG(NULL, &cc->flashdata, *buf++);
15558 + /* Set chip select */
15559 + OR_REG(NULL, &cc->gpioout, mask);
15560 + /* Issue a page program with the first byte */
15561 + sflash_cmd(cc, SFLASH_ST_PP);
15562 + ret = 1;
15563 + offset++;
15564 + len--;
15565 + while (len > 0) {
15566 + if ((offset & 255) == 0) {
15567 + /* Page boundary, drop cs and return */
15568 + AND_REG(NULL, &cc->gpioout, ~mask);
15569 + if (!sflash_poll(cc, offset)) {
15570 + /* Flash rejected command */
15571 + return -11;
15572 + }
15573 + return ret;
15574 + } else {
15575 + /* Write single byte */
15576 + sflash_cmd(cc, *buf++);
15577 + }
15578 + ret++;
15579 + offset++;
15580 + len--;
15581 + }
15582 + /* All done, drop cs if needed */
15583 + if ((offset & 255) != 1) {
15584 + /* Drop cs */
15585 + AND_REG(NULL, &cc->gpioout, ~mask);
15586 + if (!sflash_poll(cc, offset)) {
15587 + /* Flash rejected command */
15588 + return -12;
15589 + }
15590 + }
15591 + } else {
15592 + ret = 1;
15593 + W_REG(NULL, &cc->flashaddress, offset);
15594 + W_REG(NULL, &cc->flashdata, *buf);
15595 + /* Page program */
15596 + sflash_cmd(cc, SFLASH_ST_PP);
15597 + }
15598 + break;
15599 + case SFLASH_AT:
15600 + mask = sfl->blocksize - 1;
15601 + page = (offset & ~mask) << 1;
15602 + byte = offset & mask;
15603 + /* Read main memory page into buffer 1 */
15604 + if (byte || (len < sfl->blocksize)) {
15605 + W_REG(NULL, &cc->flashaddress, page);
15606 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
15607 + /* 250 us for AT45DB321B */
15608 + SPINWAIT(sflash_poll(cc, offset), 1000);
15609 + ASSERT(!sflash_poll(cc, offset));
15610 + }
15611 + /* Write into buffer 1 */
15612 + for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
15613 + W_REG(NULL, &cc->flashaddress, byte++);
15614 + W_REG(NULL, &cc->flashdata, *buf++);
15615 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
15616 + }
15617 + /* Write buffer 1 into main memory page */
15618 + W_REG(NULL, &cc->flashaddress, page);
15619 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
15620 + break;
15621 + }
15622 +
15623 + return ret;
15624 +}
15625 +
15626 +/* Erase a region. Returns number of bytes scheduled for erasure.
15627 + * Caller should poll for completion.
15628 + */
15629 +int
15630 +sflash_erase(chipcregs_t *cc, uint offset)
15631 +{
15632 + struct sflash *sfl;
15633 +
15634 + if (offset >= sflash.size)
15635 + return -22;
15636 +
15637 + sfl = &sflash;
15638 + switch (sfl->type) {
15639 + case SFLASH_ST:
15640 + sflash_cmd(cc, SFLASH_ST_WREN);
15641 + W_REG(NULL, &cc->flashaddress, offset);
15642 + sflash_cmd(cc, SFLASH_ST_SE);
15643 + return sfl->blocksize;
15644 + case SFLASH_AT:
15645 + W_REG(NULL, &cc->flashaddress, offset << 1);
15646 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
15647 + return sfl->blocksize;
15648 + }
15649 +
15650 + return 0;
15651 +}
15652 +
15653 +/*
15654 + * writes the appropriate range of flash, a NULL buf simply erases
15655 + * the region of flash
15656 + */
15657 +int
15658 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15659 +{
15660 + struct sflash *sfl;
15661 + uchar *block = NULL, *cur_ptr, *blk_ptr;
15662 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
15663 + uint blk_offset, blk_len, copied;
15664 + int bytes, ret = 0;
15665 +
15666 + /* Check address range */
15667 + if (len <= 0)
15668 + return 0;
15669 +
15670 + sfl = &sflash;
15671 + if ((offset + len) > sfl->size)
15672 + return -1;
15673 +
15674 + blocksize = sfl->blocksize;
15675 + mask = blocksize - 1;
15676 +
15677 + /* Allocate a block of mem */
15678 + if (!(block = MALLOC(NULL, blocksize)))
15679 + return -1;
15680 +
15681 + while (len) {
15682 + /* Align offset */
15683 + cur_offset = offset & ~mask;
15684 + cur_length = blocksize;
15685 + cur_ptr = block;
15686 +
15687 + remainder = blocksize - (offset & mask);
15688 + if (len < remainder)
15689 + cur_retlen = len;
15690 + else
15691 + cur_retlen = remainder;
15692 +
15693 + /* buf == NULL means erase only */
15694 + if (buf) {
15695 + /* Copy existing data into holding block if necessary */
15696 + if ((offset & mask) || (len < blocksize)) {
15697 + blk_offset = cur_offset;
15698 + blk_len = cur_length;
15699 + blk_ptr = cur_ptr;
15700 +
15701 + /* Copy entire block */
15702 + while (blk_len) {
15703 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
15704 + blk_offset += copied;
15705 + blk_len -= copied;
15706 + blk_ptr += copied;
15707 + }
15708 + }
15709 +
15710 + /* Copy input data into holding block */
15711 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
15712 + }
15713 +
15714 + /* Erase block */
15715 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
15716 + goto done;
15717 + while (sflash_poll(cc, (uint) cur_offset));
15718 +
15719 + /* buf == NULL means erase only */
15720 + if (!buf) {
15721 + offset += cur_retlen;
15722 + len -= cur_retlen;
15723 + continue;
15724 + }
15725 +
15726 + /* Write holding block */
15727 + while (cur_length > 0) {
15728 + if ((bytes = sflash_write(cc,
15729 + (uint) cur_offset,
15730 + (uint) cur_length,
15731 + (uchar *) cur_ptr)) < 0) {
15732 + ret = bytes;
15733 + goto done;
15734 + }
15735 + while (sflash_poll(cc, (uint) cur_offset));
15736 + cur_offset += bytes;
15737 + cur_length -= bytes;
15738 + cur_ptr += bytes;
15739 + }
15740 +
15741 + offset += cur_retlen;
15742 + len -= cur_retlen;
15743 + buf += cur_retlen;
15744 + }
15745 +
15746 + ret = len;
15747 +done:
15748 + if (block)
15749 + MFREE(NULL, block, blocksize);
15750 + return ret;
15751 +}
15752 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
15753 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
15754 +++ linux.dev/arch/mips/bcm947xx/time.c 2006-10-02 21:19:59.000000000 +0200
15755 @@ -0,0 +1,104 @@
15756 +/*
15757 + * Copyright 2006, Broadcom Corporation
15758 + * All Rights Reserved.
15759 + *
15760 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15761 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15762 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15763 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15764 + *
15765 + * $Id: time.c,v 1.1.1.10 2006/02/27 03:42:55 honor Exp $
15766 + */
15767 +#include <linux/config.h>
15768 +#include <linux/init.h>
15769 +#include <linux/kernel.h>
15770 +#include <linux/sched.h>
15771 +#include <linux/serial_reg.h>
15772 +#include <linux/interrupt.h>
15773 +#include <asm/addrspace.h>
15774 +#include <asm/io.h>
15775 +#include <asm/time.h>
15776 +
15777 +#include <typedefs.h>
15778 +#include <osl.h>
15779 +#include <bcmnvram.h>
15780 +#include <sbconfig.h>
15781 +#include <sbextif.h>
15782 +#include <sbutils.h>
15783 +#include <hndmips.h>
15784 +#include <mipsinc.h>
15785 +#include <hndcpu.h>
15786 +
15787 +/* Global SB handle */
15788 +extern void *bcm947xx_sbh;
15789 +extern spinlock_t bcm947xx_sbh_lock;
15790 +
15791 +/* Convenience */
15792 +#define sbh bcm947xx_sbh
15793 +#define sbh_lock bcm947xx_sbh_lock
15794 +
15795 +extern int panic_timeout;
15796 +static int watchdog = 0;
15797 +static u8 *mcr = NULL;
15798 +
15799 +void __init
15800 +bcm947xx_time_init(void)
15801 +{
15802 + unsigned int hz;
15803 + extifregs_t *eir;
15804 +
15805 + /*
15806 + * Use deterministic values for initial counter interrupt
15807 + * so that calibrate delay avoids encountering a counter wrap.
15808 + */
15809 + write_c0_count(0);
15810 + write_c0_compare(0xffff);
15811 +
15812 + if (!(hz = sb_cpu_clock(sbh)))
15813 + hz = 100000000;
15814 +
15815 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
15816 + (hz + 500000) / 1000000);
15817 +
15818 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
15819 + mips_hpt_frequency = hz / 2;
15820 +
15821 + /* Set watchdog interval in ms */
15822 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
15823 +
15824 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
15825 + if (watchdog > 0) {
15826 + if (watchdog < 3000)
15827 + watchdog = 3000;
15828 + }
15829 +
15830 + /* Set panic timeout in seconds */
15831 + panic_timeout = watchdog / 1000;
15832 +}
15833 +
15834 +static void
15835 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
15836 +{
15837 + /* Generic MIPS timer code */
15838 + timer_interrupt(irq, dev_id, regs);
15839 +
15840 + /* Set the watchdog timer to reset after the specified number of ms */
15841 + if (watchdog > 0)
15842 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
15843 +}
15844 +
15845 +static struct irqaction bcm947xx_timer_irqaction = {
15846 + bcm947xx_timer_interrupt,
15847 + SA_INTERRUPT,
15848 + 0,
15849 + "timer",
15850 + NULL,
15851 + NULL
15852 +};
15853 +
15854 +void __init
15855 +bcm947xx_timer_setup(struct irqaction *irq)
15856 +{
15857 + /* Enable the timer interrupt */
15858 + setup_irq(7, &bcm947xx_timer_irqaction);
15859 +}
15860 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
15861 --- linux.old/arch/mips/config-shared.in 2006-10-02 21:23:10.000000000 +0200
15862 +++ linux.dev/arch/mips/config-shared.in 2006-10-02 21:19:59.000000000 +0200
15863 @@ -208,6 +208,14 @@
15864 fi
15865 define_bool CONFIG_MIPS_RTC y
15866 fi
15867 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
15868 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
15869 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15870 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
15871 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
15872 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
15873 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
15874 +fi
15875 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
15876 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
15877 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
15878 @@ -229,6 +237,11 @@
15879 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
15880
15881 #
15882 +# Provide an option for a default kernel command line
15883 +#
15884 +string 'Default kernel command string' CONFIG_CMDLINE ""
15885 +
15886 +#
15887 # Select some configuration options automatically based on user selections.
15888 #
15889 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
15890 @@ -554,6 +567,12 @@
15891 define_bool CONFIG_SWAP_IO_SPACE_L y
15892 define_bool CONFIG_BOOT_ELF32 y
15893 fi
15894 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15895 + define_bool CONFIG_PCI y
15896 + define_bool CONFIG_NONCOHERENT_IO y
15897 + define_bool CONFIG_NEW_TIME_C y
15898 + define_bool CONFIG_NEW_IRQ y
15899 +fi
15900 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
15901 define_bool CONFIG_ARC32 y
15902 define_bool CONFIG_ARC_MEMORY y
15903 @@ -1042,7 +1061,11 @@
15904
15905 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
15906 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
15907 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
15908 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15909 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
15910 +else
15911 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
15912 +fi
15913 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
15914 if [ "$CONFIG_KGDB" = "y" ]; then
15915 define_bool CONFIG_DEBUG_INFO y
15916 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
15917 --- linux.old/arch/mips/kernel/cpu-probe.c 2006-10-02 21:23:10.000000000 +0200
15918 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2006-10-02 21:19:59.000000000 +0200
15919 @@ -162,7 +162,7 @@
15920
15921 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
15922 {
15923 - switch (c->processor_id & 0xff00) {
15924 + switch (c->processor_id & PRID_IMP_MASK) {
15925 case PRID_IMP_R2000:
15926 c->cputype = CPU_R2000;
15927 c->isa_level = MIPS_CPU_ISA_I;
15928 @@ -172,7 +172,7 @@
15929 c->tlbsize = 64;
15930 break;
15931 case PRID_IMP_R3000:
15932 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
15933 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
15934 if (cpu_has_confreg())
15935 c->cputype = CPU_R3081E;
15936 else
15937 @@ -187,12 +187,12 @@
15938 break;
15939 case PRID_IMP_R4000:
15940 if (read_c0_config() & CONF_SC) {
15941 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15942 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15943 c->cputype = CPU_R4400PC;
15944 else
15945 c->cputype = CPU_R4000PC;
15946 } else {
15947 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15948 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15949 c->cputype = CPU_R4400SC;
15950 else
15951 c->cputype = CPU_R4000SC;
15952 @@ -438,7 +438,7 @@
15953 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
15954 {
15955 decode_config1(c);
15956 - switch (c->processor_id & 0xff00) {
15957 + switch (c->processor_id & PRID_IMP_MASK) {
15958 case PRID_IMP_4KC:
15959 c->cputype = CPU_4KC;
15960 c->isa_level = MIPS_CPU_ISA_M32;
15961 @@ -479,10 +479,10 @@
15962 {
15963 decode_config1(c);
15964 c->options |= MIPS_CPU_PREFETCH;
15965 - switch (c->processor_id & 0xff00) {
15966 + switch (c->processor_id & PRID_IMP_MASK) {
15967 case PRID_IMP_AU1_REV1:
15968 case PRID_IMP_AU1_REV2:
15969 - switch ((c->processor_id >> 24) & 0xff) {
15970 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
15971 case 0:
15972 c->cputype = CPU_AU1000;
15973 break;
15974 @@ -510,10 +510,34 @@
15975 }
15976 }
15977
15978 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
15979 +{
15980 + decode_config1(c);
15981 + c->options |= MIPS_CPU_PREFETCH;
15982 + switch (c->processor_id & PRID_IMP_MASK) {
15983 + case PRID_IMP_BCM4710:
15984 + c->cputype = CPU_BCM4710;
15985 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
15986 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
15987 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
15988 + break;
15989 + case PRID_IMP_4KC:
15990 + case PRID_IMP_BCM3302:
15991 + c->cputype = CPU_BCM3302;
15992 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
15993 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
15994 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
15995 + break;
15996 + default:
15997 + c->cputype = CPU_UNKNOWN;
15998 + break;
15999 + }
16000 +}
16001 +
16002 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
16003 {
16004 decode_config1(c);
16005 - switch (c->processor_id & 0xff00) {
16006 + switch (c->processor_id & PRID_IMP_MASK) {
16007 case PRID_IMP_SB1:
16008 c->cputype = CPU_SB1;
16009 c->isa_level = MIPS_CPU_ISA_M64;
16010 @@ -535,7 +559,7 @@
16011 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
16012 {
16013 decode_config1(c);
16014 - switch (c->processor_id & 0xff00) {
16015 + switch (c->processor_id & PRID_IMP_MASK) {
16016 case PRID_IMP_SR71000:
16017 c->cputype = CPU_SR71000;
16018 c->isa_level = MIPS_CPU_ISA_M64;
16019 @@ -560,7 +584,7 @@
16020 c->cputype = CPU_UNKNOWN;
16021
16022 c->processor_id = read_c0_prid();
16023 - switch (c->processor_id & 0xff0000) {
16024 + switch (c->processor_id & PRID_COMP_MASK) {
16025
16026 case PRID_COMP_LEGACY:
16027 cpu_probe_legacy(c);
16028 @@ -571,6 +595,9 @@
16029 case PRID_COMP_ALCHEMY:
16030 cpu_probe_alchemy(c);
16031 break;
16032 + case PRID_COMP_BROADCOM:
16033 + cpu_probe_broadcom(c);
16034 + break;
16035 case PRID_COMP_SIBYTE:
16036 cpu_probe_sibyte(c);
16037 break;
16038 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
16039 --- linux.old/arch/mips/kernel/head.S 2006-10-02 21:23:10.000000000 +0200
16040 +++ linux.dev/arch/mips/kernel/head.S 2006-10-02 21:19:59.000000000 +0200
16041 @@ -28,12 +28,20 @@
16042 #include <asm/mipsregs.h>
16043 #include <asm/stackframe.h>
16044
16045 +#ifdef CONFIG_BCM4710
16046 +#undef eret
16047 +#define eret nop; nop; eret
16048 +#endif
16049 +
16050 .text
16051 + j kernel_entry
16052 + nop
16053 +
16054 /*
16055 * Reserved space for exception handlers.
16056 * Necessary for machines which link their kernels at KSEG0.
16057 */
16058 - .fill 0x400
16059 + .fill 0x3f4
16060
16061 /* The following two symbols are used for kernel profiling. */
16062 EXPORT(stext)
16063 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
16064 --- linux.old/arch/mips/kernel/proc.c 2006-10-02 21:23:10.000000000 +0200
16065 +++ linux.dev/arch/mips/kernel/proc.c 2006-10-02 21:19:59.000000000 +0200
16066 @@ -78,9 +78,10 @@
16067 [CPU_AU1550] "Au1550",
16068 [CPU_24K] "MIPS 24K",
16069 [CPU_AU1200] "Au1200",
16070 + [CPU_BCM4710] "BCM4710",
16071 + [CPU_BCM3302] "BCM3302",
16072 };
16073
16074 -
16075 static int show_cpuinfo(struct seq_file *m, void *v)
16076 {
16077 unsigned int version = current_cpu_data.processor_id;
16078 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
16079 --- linux.old/arch/mips/kernel/setup.c 2006-10-02 21:23:10.000000000 +0200
16080 +++ linux.dev/arch/mips/kernel/setup.c 2006-10-02 21:19:59.000000000 +0200
16081 @@ -493,6 +493,7 @@
16082 void swarm_setup(void);
16083 void hp_setup(void);
16084 void au1x00_setup(void);
16085 + void brcm_setup(void);
16086 void frame_info_init(void);
16087
16088 frame_info_init();
16089 @@ -691,6 +692,11 @@
16090 pmc_yosemite_setup();
16091 break;
16092 #endif
16093 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
16094 + case MACH_GROUP_BRCM:
16095 + brcm_setup();
16096 + break;
16097 +#endif
16098 default:
16099 panic("Unsupported architecture");
16100 }
16101 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
16102 --- linux.old/arch/mips/kernel/traps.c 2006-10-02 21:23:10.000000000 +0200
16103 +++ linux.dev/arch/mips/kernel/traps.c 2006-10-02 21:19:59.000000000 +0200
16104 @@ -920,6 +920,7 @@
16105 void __init trap_init(void)
16106 {
16107 extern char except_vec1_generic;
16108 + extern char except_vec2_generic;
16109 extern char except_vec3_generic, except_vec3_r4000;
16110 extern char except_vec_ejtag_debug;
16111 extern char except_vec4;
16112 @@ -927,6 +928,7 @@
16113
16114 /* Copy the generic exception handler code to it's final destination. */
16115 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
16116 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
16117
16118 /*
16119 * Setup default vectors
16120 @@ -985,6 +987,12 @@
16121 set_except_vector(13, handle_tr);
16122 set_except_vector(22, handle_mdmx);
16123
16124 + if (current_cpu_data.cputype == CPU_SB1) {
16125 + /* Enable timer interrupt and scd mapped interrupt */
16126 + clear_c0_status(0xf000);
16127 + set_c0_status(0xc00);
16128 + }
16129 +
16130 if (cpu_has_fpu && !cpu_has_nofpuex)
16131 set_except_vector(15, handle_fpe);
16132
16133 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
16134 --- linux.old/arch/mips/Makefile 2006-10-02 21:23:10.000000000 +0200
16135 +++ linux.dev/arch/mips/Makefile 2006-10-02 21:19:59.000000000 +0200
16136 @@ -726,6 +726,19 @@
16137 endif
16138
16139 #
16140 +# Broadcom BCM947XX variants
16141 +#
16142 +ifdef CONFIG_BCM947XX
16143 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
16144 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
16145 +LOADADDR := 0x80001000
16146 +
16147 +zImage: vmlinux
16148 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
16149 +export LOADADDR
16150 +endif
16151 +
16152 +#
16153 # Choosing incompatible machines durings configuration will result in
16154 # error messages during linking. Select a default linkscript if
16155 # none has been choosen above.
16156 @@ -778,6 +791,7 @@
16157 $(MAKE) -C arch/$(ARCH)/tools clean
16158 $(MAKE) -C arch/mips/baget clean
16159 $(MAKE) -C arch/mips/lasat clean
16160 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
16161
16162 archmrproper:
16163 @$(MAKEBOOT) mrproper
16164 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
16165 --- linux.old/arch/mips/mm/c-r4k.c 2006-10-02 21:23:10.000000000 +0200
16166 +++ linux.dev/arch/mips/mm/c-r4k.c 2006-10-02 21:19:59.000000000 +0200
16167 @@ -1166,3 +1166,47 @@
16168 build_clear_page();
16169 build_copy_page();
16170 }
16171 +
16172 +#ifdef CONFIG_BCM4704
16173 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
16174 +{
16175 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
16176 + int i;
16177 + for (i = 0; i < nbytes; i += ic_lsize)
16178 + fill_icache_line((addr + i));
16179 +}
16180 +
16181 +/*
16182 + * This must be run from the cache on 4704A0
16183 + * so there are no mips core BIU ops in progress
16184 + * when the PFC is enabled.
16185 + */
16186 +#define PFC_CR0 0xff400000 /* control reg 0 */
16187 +#define PFC_CR1 0xff400004 /* control reg 1 */
16188 +static void __init enable_pfc(u32 mode)
16189 +{
16190 + /* write range */
16191 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
16192 +
16193 + /* enable */
16194 + *(volatile u32 *)PFC_CR0 = mode;
16195 +}
16196 +#endif
16197 +
16198 +
16199 +void check_enable_mips_pfc(int val)
16200 +{
16201 +
16202 +#ifdef CONFIG_BCM4704
16203 + struct cpuinfo_mips *c = &current_cpu_data;
16204 +
16205 + /* enable prefetch cache */
16206 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
16207 + && (read_c0_diag() & (1 << 29))) {
16208 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
16209 + enable_pfc(val);
16210 + }
16211 +#endif
16212 +}
16213 +
16214 +
16215 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
16216 --- linux.old/arch/mips/pci/Makefile 2006-10-02 21:23:10.000000000 +0200
16217 +++ linux.dev/arch/mips/pci/Makefile 2006-10-02 21:19:59.000000000 +0200
16218 @@ -13,7 +13,9 @@
16219 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
16220 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
16221 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
16222 +ifndef CONFIG_BCM947XX
16223 obj-y += pci.o
16224 +endif
16225 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
16226
16227 include $(TOPDIR)/Rules.make
16228 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
16229 --- linux.old/drivers/char/serial.c 2006-10-02 21:23:10.000000000 +0200
16230 +++ linux.dev/drivers/char/serial.c 2006-10-02 21:19:59.000000000 +0200
16231 @@ -444,6 +444,10 @@
16232 return inb(info->port+1);
16233 #endif
16234 case SERIAL_IO_MEM:
16235 +#ifdef CONFIG_BCM4310
16236 + readb((unsigned long) info->iomem_base +
16237 + (UART_SCR<<info->iomem_reg_shift));
16238 +#endif
16239 return readb((unsigned long) info->iomem_base +
16240 (offset<<info->iomem_reg_shift));
16241 default:
16242 @@ -464,6 +468,9 @@
16243 case SERIAL_IO_MEM:
16244 writeb(value, (unsigned long) info->iomem_base +
16245 (offset<<info->iomem_reg_shift));
16246 +#ifdef CONFIG_BCM4704
16247 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
16248 +#endif
16249 break;
16250 default:
16251 outb(value, info->port+offset);
16252 @@ -1728,7 +1735,7 @@
16253 /* Special case since 134 is really 134.5 */
16254 quot = (2*baud_base / 269);
16255 else if (baud)
16256 - quot = baud_base / baud;
16257 + quot = (baud_base + (baud / 2)) / baud;
16258 }
16259 /* If the quotient is zero refuse the change */
16260 if (!quot && old_termios) {
16261 @@ -1745,12 +1752,12 @@
16262 /* Special case since 134 is really 134.5 */
16263 quot = (2*baud_base / 269);
16264 else if (baud)
16265 - quot = baud_base / baud;
16266 + quot = (baud_base + (baud / 2)) / baud;
16267 }
16268 }
16269 /* As a last resort, if the quotient is zero, default to 9600 bps */
16270 if (!quot)
16271 - quot = baud_base / 9600;
16272 + quot = (baud_base + 4800) / 9600;
16273 /*
16274 * Work around a bug in the Oxford Semiconductor 952 rev B
16275 * chip which causes it to seriously miscalculate baud rates
16276 @@ -5994,6 +6001,13 @@
16277 * Divisor, bytesize and parity
16278 */
16279 state = rs_table + co->index;
16280 + /*
16281 + * Safe guard: state structure must have been initialized
16282 + */
16283 + if (state->iomem_base == NULL) {
16284 + printk("!unable to setup serial console!\n");
16285 + return -1;
16286 + }
16287 if (doflow)
16288 state->flags |= ASYNC_CONS_FLOW;
16289 info = &async_sercons;
16290 @@ -6007,7 +6021,7 @@
16291 info->io_type = state->io_type;
16292 info->iomem_base = state->iomem_base;
16293 info->iomem_reg_shift = state->iomem_reg_shift;
16294 - quot = state->baud_base / baud;
16295 + quot = (state->baud_base + (baud / 2)) / baud;
16296 cval = cflag & (CSIZE | CSTOPB);
16297 #if defined(__powerpc__) || defined(__alpha__)
16298 cval >>= 8;
16299 diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
16300 --- linux.old/drivers/net/Makefile 2006-10-02 21:23:10.000000000 +0200
16301 +++ linux.dev/drivers/net/Makefile 2006-10-02 21:19:59.000000000 +0200
16302 @@ -3,6 +3,8 @@
16303 # Makefile for the Linux network (ethercard) device drivers.
16304 #
16305
16306 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
16307 +
16308 obj-y :=
16309 obj-m :=
16310 obj-n :=
16311 diff -urN linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.in
16312 --- linux.old/drivers/parport/Config.in 2006-10-02 21:23:10.000000000 +0200
16313 +++ linux.dev/drivers/parport/Config.in 2006-10-02 21:19:59.000000000 +0200
16314 @@ -11,6 +11,7 @@
16315 tristate 'Parallel port support' CONFIG_PARPORT
16316 if [ "$CONFIG_PARPORT" != "n" ]; then
16317 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
16318 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
16319 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
16320 if [ "$CONFIG_SERIAL" = "m" ]; then
16321 define_tristate CONFIG_PARPORT_PC_CML1 m
16322 diff -urN linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
16323 --- linux.old/drivers/parport/Makefile 2006-10-02 21:23:10.000000000 +0200
16324 +++ linux.dev/drivers/parport/Makefile 2006-10-02 21:19:59.000000000 +0200
16325 @@ -22,6 +22,7 @@
16326
16327 obj-$(CONFIG_PARPORT) += parport.o
16328 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
16329 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
16330 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
16331 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
16332 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
16333 diff -urN linux.old/drivers/parport/parport_splink.c linux.dev/drivers/parport/parport_splink.c
16334 --- linux.old/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
16335 +++ linux.dev/drivers/parport/parport_splink.c 2006-10-02 21:19:59.000000000 +0200
16336 @@ -0,0 +1,345 @@
16337 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
16338 + *
16339 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
16340 + * Based on parport_pc source
16341 + */
16342 +
16343 +#include <linux/config.h>
16344 +#include <linux/module.h>
16345 +#include <linux/init.h>
16346 +#include <linux/ioport.h>
16347 +#include <linux/kernel.h>
16348 +#include <linux/slab.h>
16349 +#include <linux/parport.h>
16350 +#include <linux/parport_pc.h>
16351 +
16352 +#define SPLINK_ADDRESS 0xBF800010
16353 +
16354 +#undef DEBUG
16355 +
16356 +#ifdef DEBUG
16357 +#define DPRINTK printk
16358 +#else
16359 +#define DPRINTK(stuff...)
16360 +#endif
16361 +
16362 +
16363 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
16364 + * it doesn't do any extra masking. */
16365 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
16366 + unsigned char mask,
16367 + unsigned char val)
16368 +{
16369 + struct parport_pc_private *priv = p->physport->private_data;
16370 + unsigned char *io = (unsigned char *) p->base;
16371 + unsigned char ctr = priv->ctr;
16372 +#ifdef DEBUG_PARPORT
16373 + printk (KERN_DEBUG
16374 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
16375 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
16376 +#endif
16377 + ctr = (ctr & ~mask) ^ val;
16378 + ctr &= priv->ctr_writable; /* only write writable bits. */
16379 + *(io+2) = ctr;
16380 + priv->ctr = ctr; /* Update soft copy */
16381 + return ctr;
16382 +}
16383 +
16384 +
16385 +
16386 +static void parport_splink_data_forward (struct parport *p)
16387 +{
16388 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
16389 + __parport_splink_frob_control (p, 0x20, 0);
16390 +}
16391 +
16392 +static void parport_splink_data_reverse (struct parport *p)
16393 +{
16394 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
16395 + __parport_splink_frob_control (p, 0x20, 0x20);
16396 +}
16397 +
16398 +/*
16399 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
16400 +{
16401 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
16402 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
16403 +}
16404 +*/
16405 +
16406 +static void parport_splink_enable_irq(struct parport *p)
16407 +{
16408 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
16409 + __parport_splink_frob_control (p, 0x10, 0x10);
16410 +}
16411 +
16412 +static void parport_splink_disable_irq(struct parport *p)
16413 +{
16414 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
16415 + __parport_splink_frob_control (p, 0x10, 0);
16416 +}
16417 +
16418 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
16419 +{
16420 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
16421 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
16422 + if (dev->irq_func &&
16423 + dev->port->irq != PARPORT_IRQ_NONE)
16424 + /* Set ackIntEn */
16425 + s->u.pc.ctr |= 0x10;
16426 +}
16427 +
16428 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
16429 +{
16430 + const struct parport_pc_private *priv = p->physport->private_data;
16431 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
16432 + s->u.pc.ctr = priv->ctr;
16433 +}
16434 +
16435 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
16436 +{
16437 + struct parport_pc_private *priv = p->physport->private_data;
16438 + unsigned char *io = (unsigned char *) p->base;
16439 + unsigned char ctr = s->u.pc.ctr;
16440 +
16441 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
16442 + *(io+2) = ctr;
16443 + priv->ctr = ctr;
16444 +}
16445 +
16446 +static void parport_splink_setup_interrupt(void) {
16447 + return;
16448 +}
16449 +
16450 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
16451 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
16452 + unsigned char *io = (unsigned char *) p->base;
16453 + *io = d;
16454 +}
16455 +
16456 +static unsigned char parport_splink_read_data(struct parport *p) {
16457 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
16458 + unsigned char *io = (unsigned char *) p->base;
16459 + return *io;
16460 +}
16461 +
16462 +static void parport_splink_write_control(struct parport *p, unsigned char d)
16463 +{
16464 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16465 + PARPORT_CONTROL_AUTOFD |
16466 + PARPORT_CONTROL_INIT |
16467 + PARPORT_CONTROL_SELECT);
16468 +
16469 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
16470 + /* Take this out when drivers have adapted to the newer interface. */
16471 + if (d & 0x20) {
16472 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
16473 + p->name, p->cad->name);
16474 + parport_splink_data_reverse (p);
16475 + }
16476 +
16477 + __parport_splink_frob_control (p, wm, d & wm);
16478 +}
16479 +
16480 +static unsigned char parport_splink_read_control(struct parport *p)
16481 +{
16482 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16483 + PARPORT_CONTROL_AUTOFD |
16484 + PARPORT_CONTROL_INIT |
16485 + PARPORT_CONTROL_SELECT);
16486 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
16487 + const struct parport_pc_private *priv = p->physport->private_data;
16488 + return priv->ctr & wm; /* Use soft copy */
16489 +}
16490 +
16491 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
16492 + unsigned char val)
16493 +{
16494 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16495 + PARPORT_CONTROL_AUTOFD |
16496 + PARPORT_CONTROL_INIT |
16497 + PARPORT_CONTROL_SELECT);
16498 +
16499 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
16500 + /* Take this out when drivers have adapted to the newer interface. */
16501 + if (mask & 0x20) {
16502 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
16503 + p->name, p->cad->name,
16504 + (val & 0x20) ? "reverse" : "forward");
16505 + if (val & 0x20)
16506 + parport_splink_data_reverse (p);
16507 + else
16508 + parport_splink_data_forward (p);
16509 + }
16510 +
16511 + /* Restrict mask and val to control lines. */
16512 + mask &= wm;
16513 + val &= wm;
16514 +
16515 + return __parport_splink_frob_control (p, mask, val);
16516 +}
16517 +
16518 +static unsigned char parport_splink_read_status(struct parport *p)
16519 +{
16520 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
16521 + unsigned char *io = (unsigned char *) p->base;
16522 + return *(io+1);
16523 +}
16524 +
16525 +static void parport_splink_inc_use_count(void)
16526 +{
16527 +#ifdef MODULE
16528 + MOD_INC_USE_COUNT;
16529 +#endif
16530 +}
16531 +
16532 +static void parport_splink_dec_use_count(void)
16533 +{
16534 +#ifdef MODULE
16535 + MOD_DEC_USE_COUNT;
16536 +#endif
16537 +}
16538 +
16539 +static struct parport_operations parport_splink_ops =
16540 +{
16541 + parport_splink_write_data,
16542 + parport_splink_read_data,
16543 +
16544 + parport_splink_write_control,
16545 + parport_splink_read_control,
16546 + parport_splink_frob_control,
16547 +
16548 + parport_splink_read_status,
16549 +
16550 + parport_splink_enable_irq,
16551 + parport_splink_disable_irq,
16552 +
16553 + parport_splink_data_forward,
16554 + parport_splink_data_reverse,
16555 +
16556 + parport_splink_init_state,
16557 + parport_splink_save_state,
16558 + parport_splink_restore_state,
16559 +
16560 + parport_splink_inc_use_count,
16561 + parport_splink_dec_use_count,
16562 +
16563 + parport_ieee1284_epp_write_data,
16564 + parport_ieee1284_epp_read_data,
16565 + parport_ieee1284_epp_write_addr,
16566 + parport_ieee1284_epp_read_addr,
16567 +
16568 + parport_ieee1284_ecp_write_data,
16569 + parport_ieee1284_ecp_read_data,
16570 + parport_ieee1284_ecp_write_addr,
16571 +
16572 + parport_ieee1284_write_compat,
16573 + parport_ieee1284_read_nibble,
16574 + parport_ieee1284_read_byte,
16575 +};
16576 +
16577 +/* --- Initialisation code -------------------------------- */
16578 +
16579 +static struct parport *parport_splink_probe_port (unsigned long int base)
16580 +{
16581 + struct parport_pc_private *priv;
16582 + struct parport_operations *ops;
16583 + struct parport *p;
16584 +
16585 + if (check_mem_region(base, 3)) {
16586 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
16587 + return NULL;
16588 + }
16589 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
16590 + if (!priv) {
16591 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
16592 + return NULL;
16593 + }
16594 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
16595 + if (!ops) {
16596 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
16597 + base);
16598 + kfree (priv);
16599 + return NULL;
16600 + }
16601 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
16602 + priv->ctr = 0xc;
16603 + priv->ctr_writable = 0xff;
16604 +
16605 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
16606 + PARPORT_DMA_NONE, ops))) {
16607 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
16608 + base);
16609 + kfree (priv);
16610 + kfree (ops);
16611 + return NULL;
16612 + }
16613 +
16614 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
16615 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
16616 + p->private_data = priv;
16617 +
16618 + parport_proc_register(p);
16619 + request_mem_region (p->base, 3, p->name);
16620 +
16621 + /* Done probing. Now put the port into a sensible start-up state. */
16622 + parport_splink_write_data(p, 0);
16623 + parport_splink_data_forward (p);
16624 +
16625 + /* Now that we've told the sharing engine about the port, and
16626 + found out its characteristics, let the high-level drivers
16627 + know about it. */
16628 + parport_announce_port (p);
16629 +
16630 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
16631 + base);
16632 + return p;
16633 +}
16634 +
16635 +static void parport_splink_unregister_port(struct parport *p) {
16636 + struct parport_pc_private *priv = p->private_data;
16637 + struct parport_operations *ops = p->ops;
16638 +
16639 + if (p->irq != PARPORT_IRQ_NONE)
16640 + free_irq(p->irq, p);
16641 + release_mem_region(p->base, 3);
16642 + parport_proc_unregister(p);
16643 + kfree (priv);
16644 + parport_unregister_port(p);
16645 + kfree (ops);
16646 +}
16647 +
16648 +
16649 +int parport_splink_init(void)
16650 +{
16651 + int ret;
16652 +
16653 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
16654 + parport_splink_setup_interrupt();
16655 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
16656 +
16657 + return ret;
16658 +}
16659 +
16660 +void parport_splink_cleanup(void) {
16661 + struct parport *p = parport_enumerate(), *tmp;
16662 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
16663 + if (p->size) {
16664 + if (p->modes & PARPORT_MODE_PCSPP) {
16665 + while(p) {
16666 + tmp = p->next;
16667 + parport_splink_unregister_port(p);
16668 + p = tmp;
16669 + }
16670 + }
16671 + }
16672 +}
16673 +
16674 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
16675 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
16676 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
16677 +MODULE_LICENSE("GPL");
16678 +
16679 +module_init(parport_splink_init)
16680 +module_exit(parport_splink_cleanup)
16681 +
16682 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
16683 --- linux.old/include/asm-mips/bootinfo.h 2006-10-02 21:23:10.000000000 +0200
16684 +++ linux.dev/include/asm-mips/bootinfo.h 2006-10-02 21:19:59.000000000 +0200
16685 @@ -37,6 +37,7 @@
16686 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
16687 #define MACH_GROUP_LASAT 21
16688 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
16689 +#define MACH_GROUP_BRCM 23 /* Broadcom */
16690
16691 /*
16692 * Valid machtype values for group unknown (low order halfword of mips_machtype)
16693 @@ -197,6 +198,15 @@
16694 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
16695
16696 /*
16697 + * Valid machtypes for group Broadcom
16698 + */
16699 +#define MACH_BCM93725 0
16700 +#define MACH_BCM93725_VJ 1
16701 +#define MACH_BCM93730 2
16702 +#define MACH_BCM947XX 3
16703 +#define MACH_BCM933XX 4
16704 +
16705 +/*
16706 * Valid machtype for group TITAN
16707 */
16708 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
16709 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
16710 --- linux.old/include/asm-mips/cpu.h 2006-10-02 21:23:10.000000000 +0200
16711 +++ linux.dev/include/asm-mips/cpu.h 2006-10-02 21:19:59.000000000 +0200
16712 @@ -22,6 +22,11 @@
16713 spec.
16714 */
16715
16716 +#define PRID_COPT_MASK 0xff000000
16717 +#define PRID_COMP_MASK 0x00ff0000
16718 +#define PRID_IMP_MASK 0x0000ff00
16719 +#define PRID_REV_MASK 0x000000ff
16720 +
16721 #define PRID_COMP_LEGACY 0x000000
16722 #define PRID_COMP_MIPS 0x010000
16723 #define PRID_COMP_BROADCOM 0x020000
16724 @@ -58,6 +63,7 @@
16725 #define PRID_IMP_RM7000 0x2700
16726 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
16727 #define PRID_IMP_RM9000 0x3400
16728 +#define PRID_IMP_BCM4710 0x4000
16729 #define PRID_IMP_R5432 0x5400
16730 #define PRID_IMP_R5500 0x5500
16731 #define PRID_IMP_4KC 0x8000
16732 @@ -66,10 +72,16 @@
16733 #define PRID_IMP_4KEC 0x8400
16734 #define PRID_IMP_4KSC 0x8600
16735 #define PRID_IMP_25KF 0x8800
16736 +#define PRID_IMP_BCM3302 0x9000
16737 +#define PRID_IMP_BCM3303 0x9100
16738 #define PRID_IMP_24K 0x9300
16739
16740 #define PRID_IMP_UNKNOWN 0xff00
16741
16742 +#define BCM330X(id) \
16743 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
16744 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
16745 +
16746 /*
16747 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
16748 */
16749 @@ -174,7 +186,9 @@
16750 #define CPU_AU1550 57
16751 #define CPU_24K 58
16752 #define CPU_AU1200 59
16753 -#define CPU_LAST 59
16754 +#define CPU_BCM4710 60
16755 +#define CPU_BCM3302 61
16756 +#define CPU_LAST 61
16757
16758 /*
16759 * ISA Level encodings
16760 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
16761 --- linux.old/include/asm-mips/r4kcache.h 2006-10-02 21:23:10.000000000 +0200
16762 +++ linux.dev/include/asm-mips/r4kcache.h 2006-10-02 21:19:59.000000000 +0200
16763 @@ -658,4 +658,17 @@
16764 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
16765 }
16766
16767 +extern inline void fill_icache_line(unsigned long addr)
16768 +{
16769 + __asm__ __volatile__(
16770 + ".set noreorder\n\t"
16771 + ".set mips3\n\t"
16772 + "cache %1, (%0)\n\t"
16773 + ".set mips0\n\t"
16774 + ".set reorder"
16775 + :
16776 + : "r" (addr),
16777 + "i" (Fill));
16778 +}
16779 +
16780 #endif /* __ASM_R4KCACHE_H */
16781 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
16782 --- linux.old/include/asm-mips/serial.h 2006-10-02 21:23:10.000000000 +0200
16783 +++ linux.dev/include/asm-mips/serial.h 2006-10-02 21:19:59.000000000 +0200
16784 @@ -223,6 +223,13 @@
16785 #define TXX927_SERIAL_PORT_DEFNS
16786 #endif
16787
16788 +#ifdef CONFIG_BCM947XX
16789 +/* reserve 4 ports to be configured at runtime */
16790 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
16791 +#else
16792 +#define BCM947XX_SERIAL_PORT_DEFNS
16793 +#endif
16794 +
16795 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
16796 #define STD_SERIAL_PORT_DEFNS \
16797 /* UART CLK PORT IRQ FLAGS */ \
16798 @@ -470,6 +477,7 @@
16799 #define SERIAL_PORT_DFNS \
16800 ATLAS_SERIAL_PORT_DEFNS \
16801 AU1000_SERIAL_PORT_DEFNS \
16802 + BCM947XX_SERIAL_PORT_DEFNS \
16803 COBALT_SERIAL_PORT_DEFNS \
16804 DDB5477_SERIAL_PORT_DEFNS \
16805 EV96100_SERIAL_PORT_DEFNS \
16806 diff -urN linux.old/init/do_mounts.c linux.dev/init/do_mounts.c
16807 --- linux.old/init/do_mounts.c 2006-10-02 21:23:10.000000000 +0200
16808 +++ linux.dev/init/do_mounts.c 2006-10-02 21:19:59.000000000 +0200
16809 @@ -254,7 +254,13 @@
16810 { "ftlb", 0x2c08 },
16811 { "ftlc", 0x2c10 },
16812 { "ftld", 0x2c18 },
16813 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
16814 { "mtdblock", 0x1f00 },
16815 + { "mtdblock0",0x1f00 },
16816 + { "mtdblock1",0x1f01 },
16817 + { "mtdblock2",0x1f02 },
16818 + { "mtdblock3",0x1f03 },
16819 +#endif
16820 { "nb", 0x2b00 },
16821 { NULL, 0 }
16822 };
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