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kernel: update 3.18 to 3.18.21
[openwrt/svn-archive/archive.git] / target / linux / brcm2708 / patches-3.18 / 0089-Add-2709-platform-for-Raspberry-Pi-2.patch
1 From 08891f5b4dedf2c490371cef6af91f3b7475282d Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Tue, 7 May 2013 14:32:27 +0100
4 Subject: [PATCH 089/114] Add 2709 platform for Raspberry Pi 2
5
6 ---
7 arch/arm/Kconfig | 21 +
8 arch/arm/Makefile | 1 +
9 arch/arm/boot/dts/Makefile | 11 +-
10 arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 101 ++
11 arch/arm/boot/dts/bcm2709.dtsi | 159 +++
12 arch/arm/configs/bcm2709_defconfig | 1149 ++++++++++++++++++++
13 arch/arm/configs/bcm2709_sdcard_defconfig | 129 +++
14 arch/arm/configs/bcm2709_small_defconfig | 61 ++
15 arch/arm/configs/bcm2835_sdcard_defconfig | 176 +++
16 arch/arm/configs/bcmrpi_sdcard_defconfig | 176 +++
17 arch/arm/configs/bcmrpi_small_defconfig | 103 ++
18 arch/arm/kernel/head.S | 8 +
19 arch/arm/mach-bcm2709/Kconfig | 49 +
20 arch/arm/mach-bcm2709/Makefile | 7 +
21 arch/arm/mach-bcm2709/Makefile.boot | 3 +
22 arch/arm/mach-bcm2709/armctrl.c | 357 +++++++
23 arch/arm/mach-bcm2709/armctrl.h | 27 +
24 arch/arm/mach-bcm2709/bcm2708_gpio.c | 426 ++++++++
25 arch/arm/mach-bcm2709/bcm2709.c | 1237 ++++++++++++++++++++++
26 arch/arm/mach-bcm2709/bcm2709.h | 49 +
27 arch/arm/mach-bcm2709/clock.c | 61 ++
28 arch/arm/mach-bcm2709/clock.h | 24 +
29 arch/arm/mach-bcm2709/delay.S | 21 +
30 arch/arm/mach-bcm2709/dma.c | 409 +++++++
31 arch/arm/mach-bcm2709/dmaer.c | 886 ++++++++++++++++
32 arch/arm/mach-bcm2709/include/mach/arm_control.h | 493 +++++++++
33 arch/arm/mach-bcm2709/include/mach/arm_power.h | 62 ++
34 arch/arm/mach-bcm2709/include/mach/barriers.h | 3 +
35 arch/arm/mach-bcm2709/include/mach/clkdev.h | 7 +
36 arch/arm/mach-bcm2709/include/mach/debug-macro.S | 22 +
37 arch/arm/mach-bcm2709/include/mach/dma.h | 94 ++
38 arch/arm/mach-bcm2709/include/mach/entry-macro.S | 123 +++
39 arch/arm/mach-bcm2709/include/mach/frc.h | 38 +
40 arch/arm/mach-bcm2709/include/mach/gpio.h | 17 +
41 arch/arm/mach-bcm2709/include/mach/hardware.h | 28 +
42 arch/arm/mach-bcm2709/include/mach/io.h | 27 +
43 arch/arm/mach-bcm2709/include/mach/irqs.h | 225 ++++
44 arch/arm/mach-bcm2709/include/mach/memory.h | 57 +
45 arch/arm/mach-bcm2709/include/mach/platform.h | 225 ++++
46 arch/arm/mach-bcm2709/include/mach/power.h | 26 +
47 arch/arm/mach-bcm2709/include/mach/system.h | 38 +
48 arch/arm/mach-bcm2709/include/mach/timex.h | 23 +
49 arch/arm/mach-bcm2709/include/mach/uncompress.h | 84 ++
50 arch/arm/mach-bcm2709/include/mach/vc_mem.h | 35 +
51 arch/arm/mach-bcm2709/include/mach/vc_support.h | 69 ++
52 arch/arm/mach-bcm2709/include/mach/vcio.h | 165 +++
53 arch/arm/mach-bcm2709/include/mach/vmalloc.h | 20 +
54 arch/arm/mach-bcm2709/power.c | 195 ++++
55 arch/arm/mach-bcm2709/vc_mem.c | 431 ++++++++
56 arch/arm/mach-bcm2709/vc_support.c | 318 ++++++
57 arch/arm/mach-bcm2709/vcio.c | 474 +++++++++
58 arch/arm/mm/proc-v7.S | 1 +
59 arch/arm/tools/mach-types | 1 +
60 drivers/char/hw_random/Kconfig | 2 +-
61 drivers/clocksource/arm_arch_timer.c | 36 +
62 drivers/dma/Kconfig | 2 +-
63 drivers/i2c/busses/Kconfig | 4 +-
64 drivers/media/platform/bcm2835/Kconfig | 2 +-
65 drivers/misc/vc04_services/Kconfig | 2 +-
66 drivers/misc/vc04_services/Makefile | 3 -
67 drivers/mmc/host/Kconfig | 2 +-
68 drivers/spi/Kconfig | 4 +-
69 drivers/watchdog/Kconfig | 2 +-
70 sound/arm/Kconfig | 2 +-
71 sound/soc/bcm/Kconfig | 2 +-
72 65 files changed, 8999 insertions(+), 16 deletions(-)
73 create mode 100644 arch/arm/boot/dts/bcm2709-rpi-2-b.dts
74 create mode 100644 arch/arm/boot/dts/bcm2709.dtsi
75 create mode 100644 arch/arm/configs/bcm2709_defconfig
76 create mode 100644 arch/arm/configs/bcm2709_sdcard_defconfig
77 create mode 100644 arch/arm/configs/bcm2709_small_defconfig
78 create mode 100644 arch/arm/configs/bcm2835_sdcard_defconfig
79 create mode 100644 arch/arm/configs/bcmrpi_sdcard_defconfig
80 create mode 100644 arch/arm/configs/bcmrpi_small_defconfig
81 create mode 100644 arch/arm/mach-bcm2709/Kconfig
82 create mode 100644 arch/arm/mach-bcm2709/Makefile
83 create mode 100644 arch/arm/mach-bcm2709/Makefile.boot
84 create mode 100644 arch/arm/mach-bcm2709/armctrl.c
85 create mode 100644 arch/arm/mach-bcm2709/armctrl.h
86 create mode 100644 arch/arm/mach-bcm2709/bcm2708_gpio.c
87 create mode 100644 arch/arm/mach-bcm2709/bcm2709.c
88 create mode 100644 arch/arm/mach-bcm2709/bcm2709.h
89 create mode 100644 arch/arm/mach-bcm2709/clock.c
90 create mode 100644 arch/arm/mach-bcm2709/clock.h
91 create mode 100644 arch/arm/mach-bcm2709/delay.S
92 create mode 100644 arch/arm/mach-bcm2709/dma.c
93 create mode 100755 arch/arm/mach-bcm2709/dmaer.c
94 create mode 100644 arch/arm/mach-bcm2709/include/mach/arm_control.h
95 create mode 100644 arch/arm/mach-bcm2709/include/mach/arm_power.h
96 create mode 100644 arch/arm/mach-bcm2709/include/mach/barriers.h
97 create mode 100644 arch/arm/mach-bcm2709/include/mach/clkdev.h
98 create mode 100644 arch/arm/mach-bcm2709/include/mach/debug-macro.S
99 create mode 100644 arch/arm/mach-bcm2709/include/mach/dma.h
100 create mode 100644 arch/arm/mach-bcm2709/include/mach/entry-macro.S
101 create mode 100644 arch/arm/mach-bcm2709/include/mach/frc.h
102 create mode 100644 arch/arm/mach-bcm2709/include/mach/gpio.h
103 create mode 100644 arch/arm/mach-bcm2709/include/mach/hardware.h
104 create mode 100644 arch/arm/mach-bcm2709/include/mach/io.h
105 create mode 100644 arch/arm/mach-bcm2709/include/mach/irqs.h
106 create mode 100644 arch/arm/mach-bcm2709/include/mach/memory.h
107 create mode 100644 arch/arm/mach-bcm2709/include/mach/platform.h
108 create mode 100644 arch/arm/mach-bcm2709/include/mach/power.h
109 create mode 100644 arch/arm/mach-bcm2709/include/mach/system.h
110 create mode 100644 arch/arm/mach-bcm2709/include/mach/timex.h
111 create mode 100644 arch/arm/mach-bcm2709/include/mach/uncompress.h
112 create mode 100644 arch/arm/mach-bcm2709/include/mach/vc_mem.h
113 create mode 100755 arch/arm/mach-bcm2709/include/mach/vc_support.h
114 create mode 100644 arch/arm/mach-bcm2709/include/mach/vcio.h
115 create mode 100644 arch/arm/mach-bcm2709/include/mach/vmalloc.h
116 create mode 100644 arch/arm/mach-bcm2709/power.c
117 create mode 100644 arch/arm/mach-bcm2709/vc_mem.c
118 create mode 100755 arch/arm/mach-bcm2709/vc_support.c
119 create mode 100644 arch/arm/mach-bcm2709/vcio.c
120
121 --- a/arch/arm/Kconfig
122 +++ b/arch/arm/Kconfig
123 @@ -803,6 +803,26 @@ config ARCH_OMAP1
124 help
125 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
126
127 +config ARCH_BCM2709
128 + bool "Broadcom BCM2709 family"
129 + select ARCH_HAS_BARRIERS if SMP
130 + select CPU_V7
131 + select HAVE_SMP
132 + select ARM_AMBA
133 + select MIGHT_HAVE_CACHE_L2X0
134 + select HAVE_SCHED_CLOCK
135 + select NEED_MACH_MEMORY_H
136 + select NEED_MACH_IO_H
137 + select COMMON_CLK
138 + select ARCH_HAS_CPUFREQ
139 + select GENERIC_CLOCKEVENTS
140 + select MACH_BCM2709
141 + select VC4
142 + select FIQ
143 +# select ZONE_DMA
144 + help
145 + This enables support for Broadcom BCM2709 boards.
146 +
147 endchoice
148
149 menu "Multiple platform selection"
150 @@ -990,6 +1010,7 @@ source "arch/arm/mach-vt8500/Kconfig"
151
152 source "arch/arm/mach-w90x900/Kconfig"
153 source "arch/arm/mach-bcm2708/Kconfig"
154 +source "arch/arm/mach-bcm2709/Kconfig"
155
156 source "arch/arm/mach-zynq/Kconfig"
157
158 --- a/arch/arm/Makefile
159 +++ b/arch/arm/Makefile
160 @@ -152,6 +152,7 @@ machine-$(CONFIG_ARCH_AT91) += at91
161 machine-$(CONFIG_ARCH_AXXIA) += axxia
162 machine-$(CONFIG_ARCH_BCM) += bcm
163 machine-$(CONFIG_ARCH_BCM2708) += bcm2708
164 +machine-$(CONFIG_ARCH_BCM2709) += bcm2709
165 machine-$(CONFIG_ARCH_BERLIN) += berlin
166 machine-$(CONFIG_ARCH_CLPS711X) += clps711x
167 machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
168 --- a/arch/arm/boot/dts/Makefile
169 +++ b/arch/arm/boot/dts/Makefile
170 @@ -53,6 +53,14 @@ dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4e
171
172 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
173 dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
174 +
175 +# Raspberry Pi
176 +ifeq ($(CONFIG_BCM2708_DT),y)
177 + RPI_DT_OVERLAYS=y
178 +endif
179 +ifeq ($(CONFIG_BCM2709_DT),y)
180 + RPI_DT_OVERLAYS=y
181 +endif
182 dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b.dtb
183 dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b-plus.dtb
184 dtb-$(CONFIG_BCM2708_DT) += hifiberry-dac-overlay.dtb
185 @@ -68,6 +76,7 @@ dtb-$(CONFIG_BCM2708_DT) += ds1307-rtc-o
186 dtb-$(CONFIG_BCM2708_DT) += w1-gpio-overlay.dtb
187 dtb-$(CONFIG_BCM2708_DT) += w1-gpio-pullup-overlay.dtb
188 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
189 +
190 dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
191 dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
192 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
193 @@ -537,7 +546,7 @@ targets += $(dtb-y)
194 endif
195
196 # Enable fixups to support overlays on BCM2708 platforms
197 -ifeq ($(CONFIG_BCM2708_DT),y)
198 +ifeq ($(RPI_DT_OVERLAYS),y)
199 DTC_FLAGS ?= -@
200 endif
201
202 --- /dev/null
203 +++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts
204 @@ -0,0 +1,101 @@
205 +/dts-v1/;
206 +
207 +/include/ "bcm2709.dtsi"
208 +
209 +/ {
210 + compatible = "brcm,bcm2709";
211 + model = "Raspberry Pi 2 Model B";
212 +
213 + aliases {
214 + soc = &soc;
215 + spi0 = &spi0;
216 + i2c0 = &i2c0;
217 + i2c1 = &i2c1;
218 + i2s = &i2s;
219 + gpio = &gpio;
220 + intc = &intc;
221 + leds = &leds;
222 + sound = &sound;
223 + };
224 +
225 + sound: sound {
226 + };
227 +};
228 +
229 +&gpio {
230 + spi0_pins: spi0_pins {
231 + brcm,pins = <7 8 9 10 11>;
232 + brcm,function = <4>; /* alt0 */
233 + };
234 +
235 + i2c0_pins: i2c0 {
236 + brcm,pins = <0 1>;
237 + brcm,function = <4>;
238 + };
239 +
240 + i2c1_pins: i2c1 {
241 + brcm,pins = <2 3>;
242 + brcm,function = <4>;
243 + };
244 +
245 + i2s_pins: i2s {
246 + brcm,pins = <18 19 20 21>;
247 + brcm,function = <4>; /* alt0 */
248 + };
249 +};
250 +
251 +&spi0 {
252 + pinctrl-names = "default";
253 + pinctrl-0 = <&spi0_pins>;
254 +
255 + spidev@0{
256 + compatible = "spidev";
257 + reg = <0>; /* CE0 */
258 + #address-cells = <1>;
259 + #size-cells = <0>;
260 + spi-max-frequency = <500000>;
261 + };
262 +
263 + spidev@1{
264 + compatible = "spidev";
265 + reg = <1>; /* CE1 */
266 + #address-cells = <1>;
267 + #size-cells = <0>;
268 + spi-max-frequency = <500000>;
269 + };
270 +};
271 +
272 +&i2c0 {
273 + pinctrl-names = "default";
274 + pinctrl-0 = <&i2c0_pins>;
275 + clock-frequency = <100000>;
276 +};
277 +
278 +&i2c1 {
279 + pinctrl-names = "default";
280 + pinctrl-0 = <&i2c1_pins>;
281 + clock-frequency = <100000>;
282 +};
283 +
284 +&i2s {
285 + #sound-dai-cells = <0>;
286 + pinctrl-names = "default";
287 + pinctrl-0 = <&i2s_pins>;
288 +};
289 +
290 +&act_led {
291 + gpios = <&gpio 47 0>;
292 +};
293 +
294 +/ {
295 + __overrides__ {
296 + i2s = <&i2s>,"status";
297 + spi = <&spi0>,"status";
298 + i2c0 = <&i2c0>,"status";
299 + i2c1 = <&i2c1>,"status";
300 +
301 + act_led_gpio = <&act_led>,"gpios:4";
302 + act_led_activelow = <&act_led>,"gpios:8";
303 + act_led_trigger = <&act_led>,"linux,default-trigger";
304 + };
305 +};
306 --- /dev/null
307 +++ b/arch/arm/boot/dts/bcm2709.dtsi
308 @@ -0,0 +1,159 @@
309 +/include/ "skeleton.dtsi"
310 +
311 +/ {
312 + compatible = "brcm,bcm2709";
313 + model = "BCM2709";
314 +
315 + interrupt-parent = <&intc>;
316 +
317 + chosen {
318 + /* No padding required - the boot loader can do that. */
319 + bootargs = "";
320 + };
321 +
322 + soc: soc {
323 + compatible = "simple-bus";
324 + #address-cells = <1>;
325 + #size-cells = <1>;
326 + ranges = <0x7e000000 0x3f000000 0x01000000>;
327 +
328 + intc: interrupt-controller {
329 + compatible = "brcm,bcm2708-armctrl-ic";
330 + reg = <0x7e00b200 0x200>;
331 + interrupt-controller;
332 + #interrupt-cells = <2>;
333 + };
334 +
335 + gpio: gpio {
336 + compatible = "brcm,bcm2835-gpio";
337 + reg = <0x7e200000 0xb4>;
338 + interrupts = <2 17>, <2 18>;
339 +
340 + gpio-controller;
341 + #gpio-cells = <2>;
342 +
343 + interrupt-controller;
344 + #interrupt-cells = <2>;
345 + };
346 +
347 + i2s: i2s@7e203000 {
348 + compatible = "brcm,bcm2708-i2s";
349 + reg = <0x7e203000 0x20>,
350 + <0x7e101098 0x02>;
351 +
352 + //dmas = <&dma 2>,
353 + // <&dma 3>;
354 + dma-names = "tx", "rx";
355 + status = "disabled";
356 + };
357 +
358 + spi0: spi@7e204000 {
359 + compatible = "brcm,bcm2708-spi";
360 + reg = <0x7e204000 0x1000>;
361 + interrupts = <2 22>;
362 + clocks = <&clk_spi>;
363 + #address-cells = <1>;
364 + #size-cells = <0>;
365 + status = "disabled";
366 + };
367 +
368 + i2c0: i2c@7e205000 {
369 + compatible = "brcm,bcm2708-i2c";
370 + reg = <0x7e205000 0x1000>;
371 + interrupts = <2 21>;
372 + clocks = <&clk_i2c>;
373 + #address-cells = <1>;
374 + #size-cells = <0>;
375 + status = "disabled";
376 + };
377 +
378 + i2c1: i2c@7e804000 {
379 + compatible = "brcm,bcm2708-i2c";
380 + reg = <0x7e804000 0x1000>;
381 + interrupts = <2 21>;
382 + clocks = <&clk_i2c>;
383 + #address-cells = <1>;
384 + #size-cells = <0>;
385 + status = "disabled";
386 + };
387 +
388 + leds: leds {
389 + compatible = "gpio-leds";
390 +
391 + act_led: act {
392 + label = "ACT";
393 + linux,default-trigger = "mmc0";
394 + };
395 + };
396 + };
397 +
398 + clocks {
399 + compatible = "simple-bus";
400 + #address-cells = <1>;
401 + #size-cells = <0>;
402 +
403 + clk_i2c: i2c {
404 + compatible = "fixed-clock";
405 + reg = <1>;
406 + #clock-cells = <0>;
407 + clock-frequency = <250000000>;
408 + };
409 +
410 + clk_spi: clock@2 {
411 + compatible = "fixed-clock";
412 + reg = <2>;
413 + #clock-cells = <0>;
414 + clock-output-names = "spi";
415 + clock-frequency = <250000000>;
416 + };
417 + };
418 +
419 + timer {
420 + compatible = "arm,armv7-timer";
421 + clock-frequency = <19200000>;
422 + interrupts = <3 0>, // PHYS_SECURE_PPI
423 + <3 1>, // PHYS_NONSECURE_PPI
424 + <3 3>, // VIRT_PPI
425 + <3 2>; // HYP_PPI
426 + };
427 +
428 + cpus: cpus {
429 + #address-cells = <1>;
430 + #size-cells = <0>;
431 +
432 + v7_cpu0: cpu@0 {
433 + device_type = "cpu";
434 + compatible = "arm,cortex-a7";
435 + reg = <0xf00>;
436 + clock-frequency = <800000000>;
437 + };
438 +
439 + v7_cpu1: cpu@1 {
440 + device_type = "cpu";
441 + compatible = "arm,cortex-a7";
442 + reg = <0xf01>;
443 + clock-frequency = <800000000>;
444 + };
445 +
446 + v7_cpu2: cpu@2 {
447 + device_type = "cpu";
448 + compatible = "arm,cortex-a7";
449 + reg = <0xf02>;
450 + clock-frequency = <800000000>;
451 + };
452 +
453 + v7_cpu3: cpu@3 {
454 + device_type = "cpu";
455 + compatible = "arm,cortex-a7";
456 + reg = <0xf03>;
457 + clock-frequency = <800000000>;
458 + };
459 + };
460 +
461 + __overrides__ {
462 + arm_freq = <&v7_cpu0>, "clock-frequency:0",
463 + <&v7_cpu1>, "clock-frequency:0",
464 + <&v7_cpu2>, "clock-frequency:0",
465 + <&v7_cpu3>, "clock-frequency:0";
466 + };
467 +};
468 --- /dev/null
469 +++ b/arch/arm/configs/bcm2709_defconfig
470 @@ -0,0 +1,1149 @@
471 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set
472 +CONFIG_PHYS_OFFSET=0
473 +CONFIG_LOCALVERSION="-v7"
474 +# CONFIG_LOCALVERSION_AUTO is not set
475 +CONFIG_SYSVIPC=y
476 +CONFIG_POSIX_MQUEUE=y
477 +CONFIG_FHANDLE=y
478 +CONFIG_AUDIT=y
479 +CONFIG_NO_HZ=y
480 +CONFIG_HIGH_RES_TIMERS=y
481 +CONFIG_BSD_PROCESS_ACCT=y
482 +CONFIG_BSD_PROCESS_ACCT_V3=y
483 +CONFIG_TASKSTATS=y
484 +CONFIG_TASK_DELAY_ACCT=y
485 +CONFIG_TASK_XACCT=y
486 +CONFIG_TASK_IO_ACCOUNTING=y
487 +CONFIG_IKCONFIG=y
488 +CONFIG_IKCONFIG_PROC=y
489 +CONFIG_CGROUP_FREEZER=y
490 +CONFIG_CGROUP_DEVICE=y
491 +CONFIG_CGROUP_CPUACCT=y
492 +CONFIG_RESOURCE_COUNTERS=y
493 +CONFIG_MEMCG=y
494 +CONFIG_BLK_CGROUP=y
495 +CONFIG_NAMESPACES=y
496 +CONFIG_SCHED_AUTOGROUP=y
497 +CONFIG_BLK_DEV_INITRD=y
498 +CONFIG_EMBEDDED=y
499 +# CONFIG_COMPAT_BRK is not set
500 +CONFIG_PROFILING=y
501 +CONFIG_OPROFILE=m
502 +CONFIG_KPROBES=y
503 +CONFIG_JUMP_LABEL=y
504 +CONFIG_MODULES=y
505 +CONFIG_MODULE_UNLOAD=y
506 +CONFIG_MODVERSIONS=y
507 +CONFIG_MODULE_SRCVERSION_ALL=y
508 +CONFIG_BLK_DEV_THROTTLING=y
509 +CONFIG_PARTITION_ADVANCED=y
510 +CONFIG_MAC_PARTITION=y
511 +CONFIG_CFQ_GROUP_IOSCHED=y
512 +CONFIG_ARCH_BCM2709=y
513 +CONFIG_BCM2709_DT=y
514 +# CONFIG_CACHE_L2X0 is not set
515 +CONFIG_SMP=y
516 +CONFIG_HAVE_ARM_ARCH_TIMER=y
517 +CONFIG_VMSPLIT_2G=y
518 +CONFIG_PREEMPT=y
519 +CONFIG_AEABI=y
520 +CONFIG_CLEANCACHE=y
521 +CONFIG_FRONTSWAP=y
522 +CONFIG_CMA=y
523 +CONFIG_UACCESS_WITH_MEMCPY=y
524 +CONFIG_SECCOMP=y
525 +CONFIG_ZBOOT_ROM_TEXT=0x0
526 +CONFIG_ZBOOT_ROM_BSS=0x0
527 +CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
528 +CONFIG_KEXEC=y
529 +CONFIG_CPU_FREQ=y
530 +CONFIG_CPU_FREQ_STAT=m
531 +CONFIG_CPU_FREQ_STAT_DETAILS=y
532 +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
533 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
534 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
535 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
536 +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
537 +CONFIG_CPU_IDLE=y
538 +CONFIG_VFP=y
539 +CONFIG_NEON=y
540 +CONFIG_KERNEL_MODE_NEON=y
541 +CONFIG_BINFMT_MISC=m
542 +CONFIG_NET=y
543 +CONFIG_PACKET=y
544 +CONFIG_UNIX=y
545 +CONFIG_XFRM_USER=y
546 +CONFIG_NET_KEY=m
547 +CONFIG_INET=y
548 +CONFIG_IP_MULTICAST=y
549 +CONFIG_IP_ADVANCED_ROUTER=y
550 +CONFIG_IP_MULTIPLE_TABLES=y
551 +CONFIG_IP_ROUTE_MULTIPATH=y
552 +CONFIG_IP_ROUTE_VERBOSE=y
553 +CONFIG_IP_PNP=y
554 +CONFIG_IP_PNP_DHCP=y
555 +CONFIG_IP_PNP_RARP=y
556 +CONFIG_NET_IPIP=m
557 +CONFIG_NET_IPGRE_DEMUX=m
558 +CONFIG_NET_IPGRE=m
559 +CONFIG_IP_MROUTE=y
560 +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
561 +CONFIG_IP_PIMSM_V1=y
562 +CONFIG_IP_PIMSM_V2=y
563 +CONFIG_SYN_COOKIES=y
564 +CONFIG_INET_AH=m
565 +CONFIG_INET_ESP=m
566 +CONFIG_INET_IPCOMP=m
567 +CONFIG_INET_XFRM_MODE_TRANSPORT=m
568 +CONFIG_INET_XFRM_MODE_TUNNEL=m
569 +CONFIG_INET_XFRM_MODE_BEET=m
570 +CONFIG_INET_LRO=m
571 +CONFIG_INET_DIAG=m
572 +CONFIG_INET6_AH=m
573 +CONFIG_INET6_ESP=m
574 +CONFIG_INET6_IPCOMP=m
575 +CONFIG_IPV6_TUNNEL=m
576 +CONFIG_IPV6_MULTIPLE_TABLES=y
577 +CONFIG_IPV6_MROUTE=y
578 +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
579 +CONFIG_IPV6_PIMSM_V2=y
580 +CONFIG_NETFILTER=y
581 +CONFIG_NF_CONNTRACK=m
582 +CONFIG_NF_CONNTRACK_ZONES=y
583 +CONFIG_NF_CONNTRACK_EVENTS=y
584 +CONFIG_NF_CONNTRACK_TIMESTAMP=y
585 +CONFIG_NF_CT_PROTO_DCCP=m
586 +CONFIG_NF_CT_PROTO_UDPLITE=m
587 +CONFIG_NF_CONNTRACK_AMANDA=m
588 +CONFIG_NF_CONNTRACK_FTP=m
589 +CONFIG_NF_CONNTRACK_H323=m
590 +CONFIG_NF_CONNTRACK_IRC=m
591 +CONFIG_NF_CONNTRACK_NETBIOS_NS=m
592 +CONFIG_NF_CONNTRACK_SNMP=m
593 +CONFIG_NF_CONNTRACK_PPTP=m
594 +CONFIG_NF_CONNTRACK_SANE=m
595 +CONFIG_NF_CONNTRACK_SIP=m
596 +CONFIG_NF_CONNTRACK_TFTP=m
597 +CONFIG_NF_CT_NETLINK=m
598 +CONFIG_NETFILTER_XT_SET=m
599 +CONFIG_NETFILTER_XT_TARGET_AUDIT=m
600 +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
601 +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
602 +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
603 +CONFIG_NETFILTER_XT_TARGET_DSCP=m
604 +CONFIG_NETFILTER_XT_TARGET_HMARK=m
605 +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
606 +CONFIG_NETFILTER_XT_TARGET_LED=m
607 +CONFIG_NETFILTER_XT_TARGET_LOG=m
608 +CONFIG_NETFILTER_XT_TARGET_MARK=m
609 +CONFIG_NETFILTER_XT_TARGET_NFLOG=m
610 +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
611 +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
612 +CONFIG_NETFILTER_XT_TARGET_TEE=m
613 +CONFIG_NETFILTER_XT_TARGET_TPROXY=m
614 +CONFIG_NETFILTER_XT_TARGET_TRACE=m
615 +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
616 +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
617 +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
618 +CONFIG_NETFILTER_XT_MATCH_BPF=m
619 +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
620 +CONFIG_NETFILTER_XT_MATCH_COMMENT=m
621 +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
622 +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
623 +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
624 +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
625 +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
626 +CONFIG_NETFILTER_XT_MATCH_CPU=m
627 +CONFIG_NETFILTER_XT_MATCH_DCCP=m
628 +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
629 +CONFIG_NETFILTER_XT_MATCH_DSCP=m
630 +CONFIG_NETFILTER_XT_MATCH_ESP=m
631 +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
632 +CONFIG_NETFILTER_XT_MATCH_HELPER=m
633 +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
634 +CONFIG_NETFILTER_XT_MATCH_IPVS=m
635 +CONFIG_NETFILTER_XT_MATCH_LENGTH=m
636 +CONFIG_NETFILTER_XT_MATCH_LIMIT=m
637 +CONFIG_NETFILTER_XT_MATCH_MAC=m
638 +CONFIG_NETFILTER_XT_MATCH_MARK=m
639 +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
640 +CONFIG_NETFILTER_XT_MATCH_NFACCT=m
641 +CONFIG_NETFILTER_XT_MATCH_OSF=m
642 +CONFIG_NETFILTER_XT_MATCH_OWNER=m
643 +CONFIG_NETFILTER_XT_MATCH_POLICY=m
644 +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
645 +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
646 +CONFIG_NETFILTER_XT_MATCH_QUOTA=m
647 +CONFIG_NETFILTER_XT_MATCH_RATEEST=m
648 +CONFIG_NETFILTER_XT_MATCH_REALM=m
649 +CONFIG_NETFILTER_XT_MATCH_RECENT=m
650 +CONFIG_NETFILTER_XT_MATCH_SOCKET=m
651 +CONFIG_NETFILTER_XT_MATCH_STATE=m
652 +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
653 +CONFIG_NETFILTER_XT_MATCH_STRING=m
654 +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
655 +CONFIG_NETFILTER_XT_MATCH_TIME=m
656 +CONFIG_NETFILTER_XT_MATCH_U32=m
657 +CONFIG_IP_SET=m
658 +CONFIG_IP_SET_BITMAP_IP=m
659 +CONFIG_IP_SET_BITMAP_IPMAC=m
660 +CONFIG_IP_SET_BITMAP_PORT=m
661 +CONFIG_IP_SET_HASH_IP=m
662 +CONFIG_IP_SET_HASH_IPPORT=m
663 +CONFIG_IP_SET_HASH_IPPORTIP=m
664 +CONFIG_IP_SET_HASH_IPPORTNET=m
665 +CONFIG_IP_SET_HASH_NET=m
666 +CONFIG_IP_SET_HASH_NETPORT=m
667 +CONFIG_IP_SET_HASH_NETIFACE=m
668 +CONFIG_IP_SET_LIST_SET=m
669 +CONFIG_IP_VS=m
670 +CONFIG_IP_VS_PROTO_TCP=y
671 +CONFIG_IP_VS_PROTO_UDP=y
672 +CONFIG_IP_VS_PROTO_ESP=y
673 +CONFIG_IP_VS_PROTO_AH=y
674 +CONFIG_IP_VS_PROTO_SCTP=y
675 +CONFIG_IP_VS_RR=m
676 +CONFIG_IP_VS_WRR=m
677 +CONFIG_IP_VS_LC=m
678 +CONFIG_IP_VS_WLC=m
679 +CONFIG_IP_VS_LBLC=m
680 +CONFIG_IP_VS_LBLCR=m
681 +CONFIG_IP_VS_DH=m
682 +CONFIG_IP_VS_SH=m
683 +CONFIG_IP_VS_SED=m
684 +CONFIG_IP_VS_NQ=m
685 +CONFIG_IP_VS_FTP=m
686 +CONFIG_IP_VS_PE_SIP=m
687 +CONFIG_NF_CONNTRACK_IPV4=m
688 +CONFIG_IP_NF_IPTABLES=m
689 +CONFIG_IP_NF_MATCH_AH=m
690 +CONFIG_IP_NF_MATCH_ECN=m
691 +CONFIG_IP_NF_MATCH_TTL=m
692 +CONFIG_IP_NF_FILTER=m
693 +CONFIG_IP_NF_TARGET_REJECT=m
694 +CONFIG_IP_NF_NAT=m
695 +CONFIG_IP_NF_TARGET_MASQUERADE=m
696 +CONFIG_IP_NF_TARGET_NETMAP=m
697 +CONFIG_IP_NF_TARGET_REDIRECT=m
698 +CONFIG_IP_NF_MANGLE=m
699 +CONFIG_IP_NF_TARGET_ECN=m
700 +CONFIG_IP_NF_TARGET_TTL=m
701 +CONFIG_IP_NF_RAW=m
702 +CONFIG_IP_NF_ARPTABLES=m
703 +CONFIG_IP_NF_ARPFILTER=m
704 +CONFIG_IP_NF_ARP_MANGLE=m
705 +CONFIG_NF_CONNTRACK_IPV6=m
706 +CONFIG_IP6_NF_IPTABLES=m
707 +CONFIG_IP6_NF_MATCH_AH=m
708 +CONFIG_IP6_NF_MATCH_EUI64=m
709 +CONFIG_IP6_NF_MATCH_FRAG=m
710 +CONFIG_IP6_NF_MATCH_OPTS=m
711 +CONFIG_IP6_NF_MATCH_HL=m
712 +CONFIG_IP6_NF_MATCH_IPV6HEADER=m
713 +CONFIG_IP6_NF_MATCH_MH=m
714 +CONFIG_IP6_NF_MATCH_RT=m
715 +CONFIG_IP6_NF_TARGET_HL=m
716 +CONFIG_IP6_NF_FILTER=m
717 +CONFIG_IP6_NF_TARGET_REJECT=m
718 +CONFIG_IP6_NF_MANGLE=m
719 +CONFIG_IP6_NF_RAW=m
720 +CONFIG_IP6_NF_NAT=m
721 +CONFIG_IP6_NF_TARGET_MASQUERADE=m
722 +CONFIG_IP6_NF_TARGET_NPT=m
723 +CONFIG_BRIDGE_NF_EBTABLES=m
724 +CONFIG_BRIDGE_EBT_BROUTE=m
725 +CONFIG_BRIDGE_EBT_T_FILTER=m
726 +CONFIG_BRIDGE_EBT_T_NAT=m
727 +CONFIG_BRIDGE_EBT_802_3=m
728 +CONFIG_BRIDGE_EBT_AMONG=m
729 +CONFIG_BRIDGE_EBT_ARP=m
730 +CONFIG_BRIDGE_EBT_IP=m
731 +CONFIG_BRIDGE_EBT_IP6=m
732 +CONFIG_BRIDGE_EBT_LIMIT=m
733 +CONFIG_BRIDGE_EBT_MARK=m
734 +CONFIG_BRIDGE_EBT_PKTTYPE=m
735 +CONFIG_BRIDGE_EBT_STP=m
736 +CONFIG_BRIDGE_EBT_VLAN=m
737 +CONFIG_BRIDGE_EBT_ARPREPLY=m
738 +CONFIG_BRIDGE_EBT_DNAT=m
739 +CONFIG_BRIDGE_EBT_MARK_T=m
740 +CONFIG_BRIDGE_EBT_REDIRECT=m
741 +CONFIG_BRIDGE_EBT_SNAT=m
742 +CONFIG_BRIDGE_EBT_LOG=m
743 +CONFIG_BRIDGE_EBT_NFLOG=m
744 +CONFIG_SCTP_COOKIE_HMAC_SHA1=y
745 +CONFIG_ATM=m
746 +CONFIG_L2TP=m
747 +CONFIG_L2TP_V3=y
748 +CONFIG_L2TP_IP=m
749 +CONFIG_L2TP_ETH=m
750 +CONFIG_BRIDGE=m
751 +CONFIG_VLAN_8021Q=m
752 +CONFIG_VLAN_8021Q_GVRP=y
753 +CONFIG_ATALK=m
754 +CONFIG_NET_SCHED=y
755 +CONFIG_NET_SCH_CBQ=m
756 +CONFIG_NET_SCH_HTB=m
757 +CONFIG_NET_SCH_HFSC=m
758 +CONFIG_NET_SCH_PRIO=m
759 +CONFIG_NET_SCH_MULTIQ=m
760 +CONFIG_NET_SCH_RED=m
761 +CONFIG_NET_SCH_SFB=m
762 +CONFIG_NET_SCH_SFQ=m
763 +CONFIG_NET_SCH_TEQL=m
764 +CONFIG_NET_SCH_TBF=m
765 +CONFIG_NET_SCH_GRED=m
766 +CONFIG_NET_SCH_DSMARK=m
767 +CONFIG_NET_SCH_NETEM=m
768 +CONFIG_NET_SCH_DRR=m
769 +CONFIG_NET_SCH_MQPRIO=m
770 +CONFIG_NET_SCH_CHOKE=m
771 +CONFIG_NET_SCH_QFQ=m
772 +CONFIG_NET_SCH_CODEL=m
773 +CONFIG_NET_SCH_FQ_CODEL=m
774 +CONFIG_NET_SCH_INGRESS=m
775 +CONFIG_NET_SCH_PLUG=m
776 +CONFIG_NET_CLS_BASIC=m
777 +CONFIG_NET_CLS_TCINDEX=m
778 +CONFIG_NET_CLS_ROUTE4=m
779 +CONFIG_NET_CLS_FW=m
780 +CONFIG_NET_CLS_U32=m
781 +CONFIG_CLS_U32_MARK=y
782 +CONFIG_NET_CLS_RSVP=m
783 +CONFIG_NET_CLS_RSVP6=m
784 +CONFIG_NET_CLS_FLOW=m
785 +CONFIG_NET_CLS_CGROUP=m
786 +CONFIG_NET_EMATCH=y
787 +CONFIG_NET_EMATCH_CMP=m
788 +CONFIG_NET_EMATCH_NBYTE=m
789 +CONFIG_NET_EMATCH_U32=m
790 +CONFIG_NET_EMATCH_META=m
791 +CONFIG_NET_EMATCH_TEXT=m
792 +CONFIG_NET_EMATCH_IPSET=m
793 +CONFIG_NET_CLS_ACT=y
794 +CONFIG_NET_ACT_POLICE=m
795 +CONFIG_NET_ACT_GACT=m
796 +CONFIG_GACT_PROB=y
797 +CONFIG_NET_ACT_MIRRED=m
798 +CONFIG_NET_ACT_IPT=m
799 +CONFIG_NET_ACT_NAT=m
800 +CONFIG_NET_ACT_PEDIT=m
801 +CONFIG_NET_ACT_SIMP=m
802 +CONFIG_NET_ACT_SKBEDIT=m
803 +CONFIG_NET_ACT_CSUM=m
804 +CONFIG_BATMAN_ADV=m
805 +CONFIG_OPENVSWITCH=m
806 +CONFIG_NET_PKTGEN=m
807 +CONFIG_HAMRADIO=y
808 +CONFIG_AX25=m
809 +CONFIG_NETROM=m
810 +CONFIG_ROSE=m
811 +CONFIG_MKISS=m
812 +CONFIG_6PACK=m
813 +CONFIG_BPQETHER=m
814 +CONFIG_BAYCOM_SER_FDX=m
815 +CONFIG_BAYCOM_SER_HDX=m
816 +CONFIG_YAM=m
817 +CONFIG_IRDA=m
818 +CONFIG_IRLAN=m
819 +CONFIG_IRNET=m
820 +CONFIG_IRCOMM=m
821 +CONFIG_IRDA_ULTRA=y
822 +CONFIG_IRDA_CACHE_LAST_LSAP=y
823 +CONFIG_IRDA_FAST_RR=y
824 +CONFIG_IRTTY_SIR=m
825 +CONFIG_KINGSUN_DONGLE=m
826 +CONFIG_KSDAZZLE_DONGLE=m
827 +CONFIG_KS959_DONGLE=m
828 +CONFIG_USB_IRDA=m
829 +CONFIG_SIGMATEL_FIR=m
830 +CONFIG_MCS_FIR=m
831 +CONFIG_BT=m
832 +CONFIG_BT_RFCOMM=m
833 +CONFIG_BT_RFCOMM_TTY=y
834 +CONFIG_BT_BNEP=m
835 +CONFIG_BT_BNEP_MC_FILTER=y
836 +CONFIG_BT_BNEP_PROTO_FILTER=y
837 +CONFIG_BT_HIDP=m
838 +CONFIG_BT_HCIBTUSB=m
839 +CONFIG_BT_HCIBCM203X=m
840 +CONFIG_BT_HCIBPA10X=m
841 +CONFIG_BT_HCIBFUSB=m
842 +CONFIG_BT_HCIVHCI=m
843 +CONFIG_BT_MRVL=m
844 +CONFIG_BT_MRVL_SDIO=m
845 +CONFIG_BT_ATH3K=m
846 +CONFIG_BT_WILINK=m
847 +CONFIG_CFG80211_WEXT=y
848 +CONFIG_MAC80211=m
849 +CONFIG_MAC80211_MESH=y
850 +CONFIG_WIMAX=m
851 +CONFIG_RFKILL=m
852 +CONFIG_RFKILL_INPUT=y
853 +CONFIG_NET_9P=m
854 +CONFIG_NFC=m
855 +CONFIG_NFC_PN533=m
856 +CONFIG_DEVTMPFS=y
857 +CONFIG_DEVTMPFS_MOUNT=y
858 +CONFIG_DMA_CMA=y
859 +CONFIG_CMA_SIZE_MBYTES=5
860 +CONFIG_BLK_DEV_LOOP=y
861 +CONFIG_BLK_DEV_CRYPTOLOOP=m
862 +CONFIG_BLK_DEV_DRBD=m
863 +CONFIG_BLK_DEV_NBD=m
864 +CONFIG_BLK_DEV_RAM=y
865 +CONFIG_CDROM_PKTCDVD=m
866 +CONFIG_EEPROM_AT24=m
867 +CONFIG_SCSI=y
868 +# CONFIG_SCSI_PROC_FS is not set
869 +CONFIG_BLK_DEV_SD=y
870 +CONFIG_CHR_DEV_ST=m
871 +CONFIG_CHR_DEV_OSST=m
872 +CONFIG_BLK_DEV_SR=m
873 +CONFIG_CHR_DEV_SG=m
874 +CONFIG_SCSI_ISCSI_ATTRS=y
875 +CONFIG_ISCSI_TCP=m
876 +CONFIG_ISCSI_BOOT_SYSFS=m
877 +CONFIG_MD=y
878 +CONFIG_MD_LINEAR=m
879 +CONFIG_MD_RAID0=m
880 +CONFIG_BLK_DEV_DM=m
881 +CONFIG_DM_CRYPT=m
882 +CONFIG_DM_SNAPSHOT=m
883 +CONFIG_DM_MIRROR=m
884 +CONFIG_DM_LOG_USERSPACE=m
885 +CONFIG_DM_RAID=m
886 +CONFIG_DM_ZERO=m
887 +CONFIG_DM_DELAY=m
888 +CONFIG_NETDEVICES=y
889 +CONFIG_BONDING=m
890 +CONFIG_DUMMY=m
891 +CONFIG_IFB=m
892 +CONFIG_MACVLAN=m
893 +CONFIG_NETCONSOLE=m
894 +CONFIG_TUN=m
895 +CONFIG_VETH=m
896 +CONFIG_MDIO_BITBANG=m
897 +CONFIG_PPP=m
898 +CONFIG_PPP_BSDCOMP=m
899 +CONFIG_PPP_DEFLATE=m
900 +CONFIG_PPP_FILTER=y
901 +CONFIG_PPP_MPPE=m
902 +CONFIG_PPP_MULTILINK=y
903 +CONFIG_PPPOATM=m
904 +CONFIG_PPPOE=m
905 +CONFIG_PPPOL2TP=m
906 +CONFIG_PPP_ASYNC=m
907 +CONFIG_PPP_SYNC_TTY=m
908 +CONFIG_SLIP=m
909 +CONFIG_SLIP_COMPRESSED=y
910 +CONFIG_SLIP_SMART=y
911 +CONFIG_USB_CATC=m
912 +CONFIG_USB_KAWETH=m
913 +CONFIG_USB_PEGASUS=m
914 +CONFIG_USB_RTL8150=m
915 +CONFIG_USB_RTL8152=m
916 +CONFIG_USB_USBNET=y
917 +CONFIG_USB_NET_AX8817X=m
918 +CONFIG_USB_NET_AX88179_178A=m
919 +CONFIG_USB_NET_CDCETHER=m
920 +CONFIG_USB_NET_CDC_EEM=m
921 +CONFIG_USB_NET_CDC_NCM=m
922 +CONFIG_USB_NET_HUAWEI_CDC_NCM=m
923 +CONFIG_USB_NET_CDC_MBIM=m
924 +CONFIG_USB_NET_DM9601=m
925 +CONFIG_USB_NET_SR9700=m
926 +CONFIG_USB_NET_SR9800=m
927 +CONFIG_USB_NET_SMSC75XX=m
928 +CONFIG_USB_NET_SMSC95XX=y
929 +CONFIG_USB_NET_GL620A=m
930 +CONFIG_USB_NET_NET1080=m
931 +CONFIG_USB_NET_PLUSB=m
932 +CONFIG_USB_NET_MCS7830=m
933 +CONFIG_USB_NET_CDC_SUBSET=m
934 +CONFIG_USB_ALI_M5632=y
935 +CONFIG_USB_AN2720=y
936 +CONFIG_USB_EPSON2888=y
937 +CONFIG_USB_KC2190=y
938 +CONFIG_USB_NET_ZAURUS=m
939 +CONFIG_USB_NET_CX82310_ETH=m
940 +CONFIG_USB_NET_KALMIA=m
941 +CONFIG_USB_NET_QMI_WWAN=m
942 +CONFIG_USB_HSO=m
943 +CONFIG_USB_NET_INT51X1=m
944 +CONFIG_USB_IPHETH=m
945 +CONFIG_USB_SIERRA_NET=m
946 +CONFIG_USB_VL600=m
947 +CONFIG_LIBERTAS_THINFIRM=m
948 +CONFIG_LIBERTAS_THINFIRM_USB=m
949 +CONFIG_AT76C50X_USB=m
950 +CONFIG_USB_ZD1201=m
951 +CONFIG_USB_NET_RNDIS_WLAN=m
952 +CONFIG_RTL8187=m
953 +CONFIG_MAC80211_HWSIM=m
954 +CONFIG_ATH_CARDS=m
955 +CONFIG_ATH9K=m
956 +CONFIG_ATH9K_HTC=m
957 +CONFIG_CARL9170=m
958 +CONFIG_ATH6KL=m
959 +CONFIG_ATH6KL_USB=m
960 +CONFIG_AR5523=m
961 +CONFIG_B43=m
962 +# CONFIG_B43_PHY_N is not set
963 +CONFIG_B43LEGACY=m
964 +CONFIG_BRCMFMAC=m
965 +CONFIG_BRCMFMAC_USB=y
966 +CONFIG_HOSTAP=m
967 +CONFIG_LIBERTAS=m
968 +CONFIG_LIBERTAS_USB=m
969 +CONFIG_LIBERTAS_SDIO=m
970 +CONFIG_P54_COMMON=m
971 +CONFIG_P54_USB=m
972 +CONFIG_RT2X00=m
973 +CONFIG_RT2500USB=m
974 +CONFIG_RT73USB=m
975 +CONFIG_RT2800USB=m
976 +CONFIG_RT2800USB_RT3573=y
977 +CONFIG_RT2800USB_RT53XX=y
978 +CONFIG_RT2800USB_RT55XX=y
979 +CONFIG_RT2800USB_UNKNOWN=y
980 +CONFIG_RTL8192CU=m
981 +CONFIG_ZD1211RW=m
982 +CONFIG_MWIFIEX=m
983 +CONFIG_MWIFIEX_SDIO=m
984 +CONFIG_WIMAX_I2400M_USB=m
985 +CONFIG_INPUT_POLLDEV=m
986 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
987 +CONFIG_INPUT_JOYDEV=m
988 +CONFIG_INPUT_EVDEV=m
989 +# CONFIG_INPUT_KEYBOARD is not set
990 +# CONFIG_INPUT_MOUSE is not set
991 +CONFIG_INPUT_JOYSTICK=y
992 +CONFIG_JOYSTICK_IFORCE=m
993 +CONFIG_JOYSTICK_IFORCE_USB=y
994 +CONFIG_JOYSTICK_XPAD=m
995 +CONFIG_JOYSTICK_XPAD_FF=y
996 +CONFIG_INPUT_TOUCHSCREEN=y
997 +CONFIG_TOUCHSCREEN_ADS7846=m
998 +CONFIG_INPUT_MISC=y
999 +CONFIG_INPUT_AD714X=m
1000 +CONFIG_INPUT_ATI_REMOTE2=m
1001 +CONFIG_INPUT_KEYSPAN_REMOTE=m
1002 +CONFIG_INPUT_POWERMATE=m
1003 +CONFIG_INPUT_YEALINK=m
1004 +CONFIG_INPUT_CM109=m
1005 +CONFIG_INPUT_UINPUT=m
1006 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
1007 +CONFIG_INPUT_ADXL34X=m
1008 +CONFIG_INPUT_CMA3000=m
1009 +CONFIG_SERIO=m
1010 +CONFIG_SERIO_RAW=m
1011 +CONFIG_GAMEPORT=m
1012 +CONFIG_GAMEPORT_NS558=m
1013 +CONFIG_GAMEPORT_L4=m
1014 +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
1015 +# CONFIG_LEGACY_PTYS is not set
1016 +# CONFIG_DEVKMEM is not set
1017 +CONFIG_SERIAL_AMBA_PL011=y
1018 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1019 +CONFIG_TTY_PRINTK=y
1020 +CONFIG_HW_RANDOM=y
1021 +CONFIG_HW_RANDOM_BCM2708=m
1022 +CONFIG_RAW_DRIVER=y
1023 +CONFIG_BRCM_CHAR_DRIVERS=y
1024 +CONFIG_BCM_VC_CMA=y
1025 +CONFIG_BCM_VC_SM=y
1026 +CONFIG_I2C=y
1027 +CONFIG_I2C_CHARDEV=m
1028 +CONFIG_I2C_MUX=m
1029 +CONFIG_I2C_BCM2708=m
1030 +CONFIG_SPI=y
1031 +CONFIG_SPI_BCM2708=m
1032 +CONFIG_SPI_SPIDEV=y
1033 +CONFIG_PPS=m
1034 +CONFIG_PPS_CLIENT_LDISC=m
1035 +CONFIG_PPS_CLIENT_GPIO=m
1036 +CONFIG_GPIO_SYSFS=y
1037 +CONFIG_GPIO_ARIZONA=m
1038 +CONFIG_W1=m
1039 +CONFIG_W1_MASTER_DS2490=m
1040 +CONFIG_W1_MASTER_DS2482=m
1041 +CONFIG_W1_MASTER_DS1WM=m
1042 +CONFIG_W1_MASTER_GPIO=m
1043 +CONFIG_W1_SLAVE_THERM=m
1044 +CONFIG_W1_SLAVE_SMEM=m
1045 +CONFIG_W1_SLAVE_DS2408=m
1046 +CONFIG_W1_SLAVE_DS2413=m
1047 +CONFIG_W1_SLAVE_DS2406=m
1048 +CONFIG_W1_SLAVE_DS2423=m
1049 +CONFIG_W1_SLAVE_DS2431=m
1050 +CONFIG_W1_SLAVE_DS2433=m
1051 +CONFIG_W1_SLAVE_DS2760=m
1052 +CONFIG_W1_SLAVE_DS2780=m
1053 +CONFIG_W1_SLAVE_DS2781=m
1054 +CONFIG_W1_SLAVE_DS28E04=m
1055 +CONFIG_W1_SLAVE_BQ27000=m
1056 +CONFIG_BATTERY_DS2760=m
1057 +# CONFIG_HWMON is not set
1058 +CONFIG_THERMAL=y
1059 +CONFIG_THERMAL_BCM2835=y
1060 +CONFIG_WATCHDOG=y
1061 +CONFIG_BCM2708_WDT=m
1062 +CONFIG_UCB1400_CORE=m
1063 +CONFIG_MFD_ARIZONA_I2C=m
1064 +CONFIG_MFD_ARIZONA_SPI=m
1065 +CONFIG_MFD_WM5102=y
1066 +CONFIG_MEDIA_SUPPORT=m
1067 +CONFIG_MEDIA_CAMERA_SUPPORT=y
1068 +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
1069 +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
1070 +CONFIG_MEDIA_RADIO_SUPPORT=y
1071 +CONFIG_MEDIA_RC_SUPPORT=y
1072 +CONFIG_MEDIA_CONTROLLER=y
1073 +CONFIG_LIRC=m
1074 +CONFIG_RC_DEVICES=y
1075 +CONFIG_RC_ATI_REMOTE=m
1076 +CONFIG_IR_IMON=m
1077 +CONFIG_IR_MCEUSB=m
1078 +CONFIG_IR_REDRAT3=m
1079 +CONFIG_IR_STREAMZAP=m
1080 +CONFIG_IR_IGUANA=m
1081 +CONFIG_IR_TTUSBIR=m
1082 +CONFIG_RC_LOOPBACK=m
1083 +CONFIG_IR_GPIO_CIR=m
1084 +CONFIG_MEDIA_USB_SUPPORT=y
1085 +CONFIG_USB_VIDEO_CLASS=m
1086 +CONFIG_USB_M5602=m
1087 +CONFIG_USB_STV06XX=m
1088 +CONFIG_USB_GL860=m
1089 +CONFIG_USB_GSPCA_BENQ=m
1090 +CONFIG_USB_GSPCA_CONEX=m
1091 +CONFIG_USB_GSPCA_CPIA1=m
1092 +CONFIG_USB_GSPCA_DTCS033=m
1093 +CONFIG_USB_GSPCA_ETOMS=m
1094 +CONFIG_USB_GSPCA_FINEPIX=m
1095 +CONFIG_USB_GSPCA_JEILINJ=m
1096 +CONFIG_USB_GSPCA_JL2005BCD=m
1097 +CONFIG_USB_GSPCA_KINECT=m
1098 +CONFIG_USB_GSPCA_KONICA=m
1099 +CONFIG_USB_GSPCA_MARS=m
1100 +CONFIG_USB_GSPCA_MR97310A=m
1101 +CONFIG_USB_GSPCA_NW80X=m
1102 +CONFIG_USB_GSPCA_OV519=m
1103 +CONFIG_USB_GSPCA_OV534=m
1104 +CONFIG_USB_GSPCA_OV534_9=m
1105 +CONFIG_USB_GSPCA_PAC207=m
1106 +CONFIG_USB_GSPCA_PAC7302=m
1107 +CONFIG_USB_GSPCA_PAC7311=m
1108 +CONFIG_USB_GSPCA_SE401=m
1109 +CONFIG_USB_GSPCA_SN9C2028=m
1110 +CONFIG_USB_GSPCA_SN9C20X=m
1111 +CONFIG_USB_GSPCA_SONIXB=m
1112 +CONFIG_USB_GSPCA_SONIXJ=m
1113 +CONFIG_USB_GSPCA_SPCA500=m
1114 +CONFIG_USB_GSPCA_SPCA501=m
1115 +CONFIG_USB_GSPCA_SPCA505=m
1116 +CONFIG_USB_GSPCA_SPCA506=m
1117 +CONFIG_USB_GSPCA_SPCA508=m
1118 +CONFIG_USB_GSPCA_SPCA561=m
1119 +CONFIG_USB_GSPCA_SPCA1528=m
1120 +CONFIG_USB_GSPCA_SQ905=m
1121 +CONFIG_USB_GSPCA_SQ905C=m
1122 +CONFIG_USB_GSPCA_SQ930X=m
1123 +CONFIG_USB_GSPCA_STK014=m
1124 +CONFIG_USB_GSPCA_STK1135=m
1125 +CONFIG_USB_GSPCA_STV0680=m
1126 +CONFIG_USB_GSPCA_SUNPLUS=m
1127 +CONFIG_USB_GSPCA_T613=m
1128 +CONFIG_USB_GSPCA_TOPRO=m
1129 +CONFIG_USB_GSPCA_TV8532=m
1130 +CONFIG_USB_GSPCA_VC032X=m
1131 +CONFIG_USB_GSPCA_VICAM=m
1132 +CONFIG_USB_GSPCA_XIRLINK_CIT=m
1133 +CONFIG_USB_GSPCA_ZC3XX=m
1134 +CONFIG_USB_PWC=m
1135 +CONFIG_VIDEO_CPIA2=m
1136 +CONFIG_USB_ZR364XX=m
1137 +CONFIG_USB_STKWEBCAM=m
1138 +CONFIG_USB_S2255=m
1139 +CONFIG_VIDEO_USBTV=m
1140 +CONFIG_VIDEO_PVRUSB2=m
1141 +CONFIG_VIDEO_HDPVR=m
1142 +CONFIG_VIDEO_TLG2300=m
1143 +CONFIG_VIDEO_USBVISION=m
1144 +CONFIG_VIDEO_STK1160_COMMON=m
1145 +CONFIG_VIDEO_STK1160_AC97=y
1146 +CONFIG_VIDEO_GO7007=m
1147 +CONFIG_VIDEO_GO7007_USB=m
1148 +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
1149 +CONFIG_VIDEO_AU0828=m
1150 +CONFIG_VIDEO_AU0828_RC=y
1151 +CONFIG_VIDEO_CX231XX=m
1152 +CONFIG_VIDEO_CX231XX_ALSA=m
1153 +CONFIG_VIDEO_CX231XX_DVB=m
1154 +CONFIG_VIDEO_TM6000=m
1155 +CONFIG_VIDEO_TM6000_ALSA=m
1156 +CONFIG_VIDEO_TM6000_DVB=m
1157 +CONFIG_DVB_USB=m
1158 +CONFIG_DVB_USB_A800=m
1159 +CONFIG_DVB_USB_DIBUSB_MB=m
1160 +CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
1161 +CONFIG_DVB_USB_DIBUSB_MC=m
1162 +CONFIG_DVB_USB_DIB0700=m
1163 +CONFIG_DVB_USB_UMT_010=m
1164 +CONFIG_DVB_USB_CXUSB=m
1165 +CONFIG_DVB_USB_M920X=m
1166 +CONFIG_DVB_USB_DIGITV=m
1167 +CONFIG_DVB_USB_VP7045=m
1168 +CONFIG_DVB_USB_VP702X=m
1169 +CONFIG_DVB_USB_GP8PSK=m
1170 +CONFIG_DVB_USB_NOVA_T_USB2=m
1171 +CONFIG_DVB_USB_TTUSB2=m
1172 +CONFIG_DVB_USB_DTT200U=m
1173 +CONFIG_DVB_USB_OPERA1=m
1174 +CONFIG_DVB_USB_AF9005=m
1175 +CONFIG_DVB_USB_AF9005_REMOTE=m
1176 +CONFIG_DVB_USB_PCTV452E=m
1177 +CONFIG_DVB_USB_DW2102=m
1178 +CONFIG_DVB_USB_CINERGY_T2=m
1179 +CONFIG_DVB_USB_DTV5100=m
1180 +CONFIG_DVB_USB_FRIIO=m
1181 +CONFIG_DVB_USB_AZ6027=m
1182 +CONFIG_DVB_USB_TECHNISAT_USB2=m
1183 +CONFIG_DVB_USB_V2=m
1184 +CONFIG_DVB_USB_AF9015=m
1185 +CONFIG_DVB_USB_AF9035=m
1186 +CONFIG_DVB_USB_ANYSEE=m
1187 +CONFIG_DVB_USB_AU6610=m
1188 +CONFIG_DVB_USB_AZ6007=m
1189 +CONFIG_DVB_USB_CE6230=m
1190 +CONFIG_DVB_USB_EC168=m
1191 +CONFIG_DVB_USB_GL861=m
1192 +CONFIG_DVB_USB_LME2510=m
1193 +CONFIG_DVB_USB_MXL111SF=m
1194 +CONFIG_DVB_USB_RTL28XXU=m
1195 +CONFIG_SMS_USB_DRV=m
1196 +CONFIG_DVB_B2C2_FLEXCOP_USB=m
1197 +CONFIG_DVB_AS102=m
1198 +CONFIG_VIDEO_EM28XX=m
1199 +CONFIG_VIDEO_EM28XX_ALSA=m
1200 +CONFIG_VIDEO_EM28XX_DVB=m
1201 +CONFIG_V4L_PLATFORM_DRIVERS=y
1202 +CONFIG_VIDEO_BCM2835=y
1203 +CONFIG_VIDEO_BCM2835_MMAL=m
1204 +CONFIG_RADIO_SI470X=y
1205 +CONFIG_USB_SI470X=m
1206 +CONFIG_I2C_SI470X=m
1207 +CONFIG_RADIO_SI4713=m
1208 +CONFIG_I2C_SI4713=m
1209 +CONFIG_USB_MR800=m
1210 +CONFIG_USB_DSBR=m
1211 +CONFIG_RADIO_SHARK=m
1212 +CONFIG_RADIO_SHARK2=m
1213 +CONFIG_USB_KEENE=m
1214 +CONFIG_USB_MA901=m
1215 +CONFIG_RADIO_TEA5764=m
1216 +CONFIG_RADIO_SAA7706H=m
1217 +CONFIG_RADIO_TEF6862=m
1218 +CONFIG_RADIO_WL1273=m
1219 +CONFIG_RADIO_WL128X=m
1220 +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
1221 +CONFIG_VIDEO_UDA1342=m
1222 +CONFIG_VIDEO_SONY_BTF_MPX=m
1223 +CONFIG_VIDEO_TVP5150=m
1224 +CONFIG_VIDEO_TW2804=m
1225 +CONFIG_VIDEO_TW9903=m
1226 +CONFIG_VIDEO_TW9906=m
1227 +CONFIG_VIDEO_OV7640=m
1228 +CONFIG_VIDEO_MT9V011=m
1229 +CONFIG_FB=y
1230 +CONFIG_FB_BCM2708=y
1231 +# CONFIG_BACKLIGHT_GENERIC is not set
1232 +CONFIG_FRAMEBUFFER_CONSOLE=y
1233 +CONFIG_LOGO=y
1234 +# CONFIG_LOGO_LINUX_MONO is not set
1235 +# CONFIG_LOGO_LINUX_VGA16 is not set
1236 +CONFIG_SOUND=y
1237 +CONFIG_SND=m
1238 +CONFIG_SND_SEQUENCER=m
1239 +CONFIG_SND_SEQ_DUMMY=m
1240 +CONFIG_SND_MIXER_OSS=m
1241 +CONFIG_SND_PCM_OSS=m
1242 +CONFIG_SND_SEQUENCER_OSS=y
1243 +CONFIG_SND_HRTIMER=m
1244 +CONFIG_SND_DUMMY=m
1245 +CONFIG_SND_ALOOP=m
1246 +CONFIG_SND_VIRMIDI=m
1247 +CONFIG_SND_MTPAV=m
1248 +CONFIG_SND_SERIAL_U16550=m
1249 +CONFIG_SND_MPU401=m
1250 +CONFIG_SND_BCM2835=m
1251 +CONFIG_SND_USB_AUDIO=m
1252 +CONFIG_SND_USB_UA101=m
1253 +CONFIG_SND_USB_CAIAQ=m
1254 +CONFIG_SND_USB_CAIAQ_INPUT=y
1255 +CONFIG_SND_USB_6FIRE=m
1256 +CONFIG_SND_SOC=m
1257 +CONFIG_SND_BCM2708_SOC_I2S=m
1258 +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
1259 +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
1260 +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
1261 +CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
1262 +CONFIG_SND_BCM2708_SOC_RPI_DAC=m
1263 +CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
1264 +CONFIG_SND_SIMPLE_CARD=m
1265 +CONFIG_SOUND_PRIME=m
1266 +CONFIG_HIDRAW=y
1267 +CONFIG_HID_A4TECH=m
1268 +CONFIG_HID_ACRUX=m
1269 +CONFIG_HID_APPLE=m
1270 +CONFIG_HID_BELKIN=m
1271 +CONFIG_HID_CHERRY=m
1272 +CONFIG_HID_CHICONY=m
1273 +CONFIG_HID_CYPRESS=m
1274 +CONFIG_HID_DRAGONRISE=m
1275 +CONFIG_HID_EMS_FF=m
1276 +CONFIG_HID_ELECOM=m
1277 +CONFIG_HID_ELO=m
1278 +CONFIG_HID_EZKEY=m
1279 +CONFIG_HID_HOLTEK=m
1280 +CONFIG_HID_KEYTOUCH=m
1281 +CONFIG_HID_KYE=m
1282 +CONFIG_HID_UCLOGIC=m
1283 +CONFIG_HID_WALTOP=m
1284 +CONFIG_HID_GYRATION=m
1285 +CONFIG_HID_TWINHAN=m
1286 +CONFIG_HID_KENSINGTON=m
1287 +CONFIG_HID_LCPOWER=m
1288 +CONFIG_HID_LOGITECH=m
1289 +CONFIG_HID_MAGICMOUSE=m
1290 +CONFIG_HID_MICROSOFT=m
1291 +CONFIG_HID_MONTEREY=m
1292 +CONFIG_HID_MULTITOUCH=m
1293 +CONFIG_HID_NTRIG=m
1294 +CONFIG_HID_ORTEK=m
1295 +CONFIG_HID_PANTHERLORD=m
1296 +CONFIG_HID_PETALYNX=m
1297 +CONFIG_HID_PICOLCD=m
1298 +CONFIG_HID_ROCCAT=m
1299 +CONFIG_HID_SAMSUNG=m
1300 +CONFIG_HID_SONY=m
1301 +CONFIG_HID_SPEEDLINK=m
1302 +CONFIG_HID_SUNPLUS=m
1303 +CONFIG_HID_GREENASIA=m
1304 +CONFIG_HID_SMARTJOYPLUS=m
1305 +CONFIG_HID_TOPSEED=m
1306 +CONFIG_HID_THINGM=m
1307 +CONFIG_HID_THRUSTMASTER=m
1308 +CONFIG_HID_WACOM=m
1309 +CONFIG_HID_WIIMOTE=m
1310 +CONFIG_HID_XINMO=m
1311 +CONFIG_HID_ZEROPLUS=m
1312 +CONFIG_HID_ZYDACRON=m
1313 +CONFIG_HID_PID=y
1314 +CONFIG_USB_HIDDEV=y
1315 +CONFIG_USB=y
1316 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1317 +CONFIG_USB_MON=m
1318 +CONFIG_USB_DWCOTG=y
1319 +CONFIG_USB_PRINTER=m
1320 +CONFIG_USB_STORAGE=y
1321 +CONFIG_USB_STORAGE_REALTEK=m
1322 +CONFIG_USB_STORAGE_DATAFAB=m
1323 +CONFIG_USB_STORAGE_FREECOM=m
1324 +CONFIG_USB_STORAGE_ISD200=m
1325 +CONFIG_USB_STORAGE_USBAT=m
1326 +CONFIG_USB_STORAGE_SDDR09=m
1327 +CONFIG_USB_STORAGE_SDDR55=m
1328 +CONFIG_USB_STORAGE_JUMPSHOT=m
1329 +CONFIG_USB_STORAGE_ALAUDA=m
1330 +CONFIG_USB_STORAGE_ONETOUCH=m
1331 +CONFIG_USB_STORAGE_KARMA=m
1332 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
1333 +CONFIG_USB_STORAGE_ENE_UB6250=m
1334 +CONFIG_USB_UAS=m
1335 +CONFIG_USB_MDC800=m
1336 +CONFIG_USB_MICROTEK=m
1337 +CONFIG_USB_SERIAL=m
1338 +CONFIG_USB_SERIAL_GENERIC=y
1339 +CONFIG_USB_SERIAL_AIRCABLE=m
1340 +CONFIG_USB_SERIAL_ARK3116=m
1341 +CONFIG_USB_SERIAL_BELKIN=m
1342 +CONFIG_USB_SERIAL_CH341=m
1343 +CONFIG_USB_SERIAL_WHITEHEAT=m
1344 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1345 +CONFIG_USB_SERIAL_CP210X=m
1346 +CONFIG_USB_SERIAL_CYPRESS_M8=m
1347 +CONFIG_USB_SERIAL_EMPEG=m
1348 +CONFIG_USB_SERIAL_FTDI_SIO=m
1349 +CONFIG_USB_SERIAL_VISOR=m
1350 +CONFIG_USB_SERIAL_IPAQ=m
1351 +CONFIG_USB_SERIAL_IR=m
1352 +CONFIG_USB_SERIAL_EDGEPORT=m
1353 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
1354 +CONFIG_USB_SERIAL_F81232=m
1355 +CONFIG_USB_SERIAL_GARMIN=m
1356 +CONFIG_USB_SERIAL_IPW=m
1357 +CONFIG_USB_SERIAL_IUU=m
1358 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
1359 +CONFIG_USB_SERIAL_KEYSPAN=m
1360 +CONFIG_USB_SERIAL_KLSI=m
1361 +CONFIG_USB_SERIAL_KOBIL_SCT=m
1362 +CONFIG_USB_SERIAL_MCT_U232=m
1363 +CONFIG_USB_SERIAL_METRO=m
1364 +CONFIG_USB_SERIAL_MOS7720=m
1365 +CONFIG_USB_SERIAL_MOS7840=m
1366 +CONFIG_USB_SERIAL_NAVMAN=m
1367 +CONFIG_USB_SERIAL_PL2303=m
1368 +CONFIG_USB_SERIAL_OTI6858=m
1369 +CONFIG_USB_SERIAL_QCAUX=m
1370 +CONFIG_USB_SERIAL_QUALCOMM=m
1371 +CONFIG_USB_SERIAL_SPCP8X5=m
1372 +CONFIG_USB_SERIAL_SAFE=m
1373 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
1374 +CONFIG_USB_SERIAL_SYMBOL=m
1375 +CONFIG_USB_SERIAL_TI=m
1376 +CONFIG_USB_SERIAL_CYBERJACK=m
1377 +CONFIG_USB_SERIAL_XIRCOM=m
1378 +CONFIG_USB_SERIAL_OPTION=m
1379 +CONFIG_USB_SERIAL_OMNINET=m
1380 +CONFIG_USB_SERIAL_OPTICON=m
1381 +CONFIG_USB_SERIAL_XSENS_MT=m
1382 +CONFIG_USB_SERIAL_WISHBONE=m
1383 +CONFIG_USB_SERIAL_SSU100=m
1384 +CONFIG_USB_SERIAL_QT2=m
1385 +CONFIG_USB_SERIAL_DEBUG=m
1386 +CONFIG_USB_EMI62=m
1387 +CONFIG_USB_EMI26=m
1388 +CONFIG_USB_ADUTUX=m
1389 +CONFIG_USB_SEVSEG=m
1390 +CONFIG_USB_RIO500=m
1391 +CONFIG_USB_LEGOTOWER=m
1392 +CONFIG_USB_LCD=m
1393 +CONFIG_USB_LED=m
1394 +CONFIG_USB_CYPRESS_CY7C63=m
1395 +CONFIG_USB_CYTHERM=m
1396 +CONFIG_USB_IDMOUSE=m
1397 +CONFIG_USB_FTDI_ELAN=m
1398 +CONFIG_USB_APPLEDISPLAY=m
1399 +CONFIG_USB_LD=m
1400 +CONFIG_USB_TRANCEVIBRATOR=m
1401 +CONFIG_USB_IOWARRIOR=m
1402 +CONFIG_USB_TEST=m
1403 +CONFIG_USB_ISIGHTFW=m
1404 +CONFIG_USB_YUREX=m
1405 +CONFIG_USB_ATM=m
1406 +CONFIG_USB_SPEEDTOUCH=m
1407 +CONFIG_USB_CXACRU=m
1408 +CONFIG_USB_UEAGLEATM=m
1409 +CONFIG_USB_XUSBATM=m
1410 +CONFIG_MMC=y
1411 +CONFIG_MMC_BLOCK_MINORS=32
1412 +CONFIG_MMC_SDHCI=y
1413 +CONFIG_MMC_SDHCI_PLTFM=y
1414 +CONFIG_MMC_BCM2835=y
1415 +CONFIG_MMC_BCM2835_DMA=y
1416 +CONFIG_MMC_SPI=m
1417 +CONFIG_LEDS_CLASS=y
1418 +CONFIG_LEDS_GPIO=y
1419 +CONFIG_LEDS_TRIGGER_TIMER=y
1420 +CONFIG_LEDS_TRIGGER_ONESHOT=y
1421 +CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1422 +CONFIG_LEDS_TRIGGER_BACKLIGHT=y
1423 +CONFIG_LEDS_TRIGGER_CPU=y
1424 +CONFIG_LEDS_TRIGGER_GPIO=y
1425 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
1426 +CONFIG_LEDS_TRIGGER_TRANSIENT=m
1427 +CONFIG_LEDS_TRIGGER_CAMERA=m
1428 +CONFIG_RTC_CLASS=y
1429 +# CONFIG_RTC_HCTOSYS is not set
1430 +CONFIG_RTC_DRV_DS1307=m
1431 +CONFIG_RTC_DRV_DS1374=m
1432 +CONFIG_RTC_DRV_DS1672=m
1433 +CONFIG_RTC_DRV_DS3232=m
1434 +CONFIG_RTC_DRV_MAX6900=m
1435 +CONFIG_RTC_DRV_RS5C372=m
1436 +CONFIG_RTC_DRV_ISL1208=m
1437 +CONFIG_RTC_DRV_ISL12022=m
1438 +CONFIG_RTC_DRV_ISL12057=m
1439 +CONFIG_RTC_DRV_X1205=m
1440 +CONFIG_RTC_DRV_PCF2127=m
1441 +CONFIG_RTC_DRV_PCF8523=m
1442 +CONFIG_RTC_DRV_PCF8563=m
1443 +CONFIG_RTC_DRV_PCF8583=m
1444 +CONFIG_RTC_DRV_M41T80=m
1445 +CONFIG_RTC_DRV_BQ32K=m
1446 +CONFIG_RTC_DRV_S35390A=m
1447 +CONFIG_RTC_DRV_FM3130=m
1448 +CONFIG_RTC_DRV_RX8581=m
1449 +CONFIG_RTC_DRV_RX8025=m
1450 +CONFIG_RTC_DRV_EM3027=m
1451 +CONFIG_RTC_DRV_RV3029C2=m
1452 +CONFIG_RTC_DRV_M41T93=m
1453 +CONFIG_RTC_DRV_M41T94=m
1454 +CONFIG_RTC_DRV_DS1305=m
1455 +CONFIG_RTC_DRV_DS1390=m
1456 +CONFIG_RTC_DRV_MAX6902=m
1457 +CONFIG_RTC_DRV_R9701=m
1458 +CONFIG_RTC_DRV_RS5C348=m
1459 +CONFIG_RTC_DRV_DS3234=m
1460 +CONFIG_RTC_DRV_PCF2123=m
1461 +CONFIG_RTC_DRV_RX4581=m
1462 +CONFIG_DMADEVICES=y
1463 +CONFIG_DMA_BCM2708=y
1464 +CONFIG_UIO=m
1465 +CONFIG_UIO_PDRV_GENIRQ=m
1466 +CONFIG_STAGING=y
1467 +CONFIG_PRISM2_USB=m
1468 +CONFIG_R8712U=m
1469 +CONFIG_R8188EU=m
1470 +CONFIG_R8723AU=m
1471 +CONFIG_VT6656=m
1472 +CONFIG_SPEAKUP=m
1473 +CONFIG_SPEAKUP_SYNTH_SOFT=m
1474 +CONFIG_STAGING_MEDIA=y
1475 +CONFIG_LIRC_STAGING=y
1476 +CONFIG_LIRC_IGORPLUGUSB=m
1477 +CONFIG_LIRC_IMON=m
1478 +CONFIG_LIRC_RPI=m
1479 +CONFIG_LIRC_SASEM=m
1480 +CONFIG_LIRC_SERIAL=m
1481 +# CONFIG_IOMMU_SUPPORT is not set
1482 +CONFIG_EXTCON=m
1483 +CONFIG_EXTCON_ARIZONA=m
1484 +CONFIG_EXT4_FS=y
1485 +CONFIG_EXT4_FS_POSIX_ACL=y
1486 +CONFIG_EXT4_FS_SECURITY=y
1487 +CONFIG_REISERFS_FS=m
1488 +CONFIG_REISERFS_FS_XATTR=y
1489 +CONFIG_REISERFS_FS_POSIX_ACL=y
1490 +CONFIG_REISERFS_FS_SECURITY=y
1491 +CONFIG_JFS_FS=m
1492 +CONFIG_JFS_POSIX_ACL=y
1493 +CONFIG_JFS_SECURITY=y
1494 +CONFIG_JFS_STATISTICS=y
1495 +CONFIG_XFS_FS=m
1496 +CONFIG_XFS_QUOTA=y
1497 +CONFIG_XFS_POSIX_ACL=y
1498 +CONFIG_XFS_RT=y
1499 +CONFIG_GFS2_FS=m
1500 +CONFIG_OCFS2_FS=m
1501 +CONFIG_BTRFS_FS=m
1502 +CONFIG_BTRFS_FS_POSIX_ACL=y
1503 +CONFIG_NILFS2_FS=m
1504 +CONFIG_FANOTIFY=y
1505 +CONFIG_QFMT_V1=m
1506 +CONFIG_QFMT_V2=m
1507 +CONFIG_AUTOFS4_FS=y
1508 +CONFIG_FUSE_FS=m
1509 +CONFIG_CUSE=m
1510 +CONFIG_FSCACHE=y
1511 +CONFIG_FSCACHE_STATS=y
1512 +CONFIG_FSCACHE_HISTOGRAM=y
1513 +CONFIG_CACHEFILES=y
1514 +CONFIG_ISO9660_FS=m
1515 +CONFIG_JOLIET=y
1516 +CONFIG_ZISOFS=y
1517 +CONFIG_UDF_FS=m
1518 +CONFIG_MSDOS_FS=y
1519 +CONFIG_VFAT_FS=y
1520 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1521 +CONFIG_NTFS_FS=m
1522 +CONFIG_NTFS_RW=y
1523 +CONFIG_TMPFS=y
1524 +CONFIG_TMPFS_POSIX_ACL=y
1525 +CONFIG_CONFIGFS_FS=y
1526 +CONFIG_ECRYPT_FS=m
1527 +CONFIG_HFS_FS=m
1528 +CONFIG_HFSPLUS_FS=m
1529 +CONFIG_SQUASHFS=m
1530 +CONFIG_SQUASHFS_XATTR=y
1531 +CONFIG_SQUASHFS_LZO=y
1532 +CONFIG_SQUASHFS_XZ=y
1533 +CONFIG_F2FS_FS=y
1534 +CONFIG_NFS_FS=y
1535 +CONFIG_NFS_V3_ACL=y
1536 +CONFIG_NFS_V4=y
1537 +CONFIG_NFS_SWAP=y
1538 +CONFIG_ROOT_NFS=y
1539 +CONFIG_NFS_FSCACHE=y
1540 +CONFIG_NFSD=m
1541 +CONFIG_NFSD_V3_ACL=y
1542 +CONFIG_NFSD_V4=y
1543 +CONFIG_CIFS=m
1544 +CONFIG_CIFS_WEAK_PW_HASH=y
1545 +CONFIG_CIFS_XATTR=y
1546 +CONFIG_CIFS_POSIX=y
1547 +CONFIG_9P_FS=m
1548 +CONFIG_9P_FS_POSIX_ACL=y
1549 +CONFIG_NLS_DEFAULT="utf8"
1550 +CONFIG_NLS_CODEPAGE_437=y
1551 +CONFIG_NLS_CODEPAGE_737=m
1552 +CONFIG_NLS_CODEPAGE_775=m
1553 +CONFIG_NLS_CODEPAGE_850=m
1554 +CONFIG_NLS_CODEPAGE_852=m
1555 +CONFIG_NLS_CODEPAGE_855=m
1556 +CONFIG_NLS_CODEPAGE_857=m
1557 +CONFIG_NLS_CODEPAGE_860=m
1558 +CONFIG_NLS_CODEPAGE_861=m
1559 +CONFIG_NLS_CODEPAGE_862=m
1560 +CONFIG_NLS_CODEPAGE_863=m
1561 +CONFIG_NLS_CODEPAGE_864=m
1562 +CONFIG_NLS_CODEPAGE_865=m
1563 +CONFIG_NLS_CODEPAGE_866=m
1564 +CONFIG_NLS_CODEPAGE_869=m
1565 +CONFIG_NLS_CODEPAGE_936=m
1566 +CONFIG_NLS_CODEPAGE_950=m
1567 +CONFIG_NLS_CODEPAGE_932=m
1568 +CONFIG_NLS_CODEPAGE_949=m
1569 +CONFIG_NLS_CODEPAGE_874=m
1570 +CONFIG_NLS_ISO8859_8=m
1571 +CONFIG_NLS_CODEPAGE_1250=m
1572 +CONFIG_NLS_CODEPAGE_1251=m
1573 +CONFIG_NLS_ASCII=y
1574 +CONFIG_NLS_ISO8859_1=m
1575 +CONFIG_NLS_ISO8859_2=m
1576 +CONFIG_NLS_ISO8859_3=m
1577 +CONFIG_NLS_ISO8859_4=m
1578 +CONFIG_NLS_ISO8859_5=m
1579 +CONFIG_NLS_ISO8859_6=m
1580 +CONFIG_NLS_ISO8859_7=m
1581 +CONFIG_NLS_ISO8859_9=m
1582 +CONFIG_NLS_ISO8859_13=m
1583 +CONFIG_NLS_ISO8859_14=m
1584 +CONFIG_NLS_ISO8859_15=m
1585 +CONFIG_NLS_KOI8_R=m
1586 +CONFIG_NLS_KOI8_U=m
1587 +CONFIG_DLM=m
1588 +CONFIG_PRINTK_TIME=y
1589 +CONFIG_BOOT_PRINTK_DELAY=y
1590 +CONFIG_DEBUG_MEMORY_INIT=y
1591 +CONFIG_DETECT_HUNG_TASK=y
1592 +CONFIG_TIMER_STATS=y
1593 +# CONFIG_DEBUG_PREEMPT is not set
1594 +CONFIG_IRQSOFF_TRACER=y
1595 +CONFIG_SCHED_TRACER=y
1596 +CONFIG_STACK_TRACER=y
1597 +CONFIG_BLK_DEV_IO_TRACE=y
1598 +# CONFIG_KPROBE_EVENT is not set
1599 +CONFIG_FUNCTION_PROFILER=y
1600 +CONFIG_KGDB=y
1601 +CONFIG_KGDB_KDB=y
1602 +CONFIG_KDB_KEYBOARD=y
1603 +CONFIG_CRYPTO_USER=m
1604 +CONFIG_CRYPTO_NULL=m
1605 +CONFIG_CRYPTO_CBC=y
1606 +CONFIG_CRYPTO_CTS=m
1607 +CONFIG_CRYPTO_XTS=m
1608 +CONFIG_CRYPTO_XCBC=m
1609 +CONFIG_CRYPTO_SHA1_ARM_NEON=m
1610 +CONFIG_CRYPTO_SHA512_ARM_NEON=m
1611 +CONFIG_CRYPTO_TGR192=m
1612 +CONFIG_CRYPTO_WP512=m
1613 +CONFIG_CRYPTO_AES_ARM_BS=m
1614 +CONFIG_CRYPTO_CAST5=m
1615 +CONFIG_CRYPTO_DES=y
1616 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1617 +# CONFIG_CRYPTO_HW is not set
1618 +CONFIG_CRC_ITU_T=y
1619 +CONFIG_LIBCRC32C=y
1620 --- /dev/null
1621 +++ b/arch/arm/configs/bcm2709_sdcard_defconfig
1622 @@ -0,0 +1,129 @@
1623 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set
1624 +CONFIG_PHYS_OFFSET=0x0
1625 +CONFIG_LOCALVERSION="-sdcard"
1626 +# CONFIG_LOCALVERSION_AUTO is not set
1627 +# CONFIG_SWAP is not set
1628 +CONFIG_SYSVIPC=y
1629 +CONFIG_POSIX_MQUEUE=y
1630 +CONFIG_FHANDLE=y
1631 +CONFIG_AUDIT=y
1632 +CONFIG_NO_HZ=y
1633 +CONFIG_HIGH_RES_TIMERS=y
1634 +CONFIG_BSD_PROCESS_ACCT=y
1635 +CONFIG_BSD_PROCESS_ACCT_V3=y
1636 +CONFIG_TASKSTATS=y
1637 +CONFIG_TASK_DELAY_ACCT=y
1638 +CONFIG_TASK_XACCT=y
1639 +CONFIG_TASK_IO_ACCOUNTING=y
1640 +CONFIG_IKCONFIG=y
1641 +CONFIG_IKCONFIG_PROC=y
1642 +CONFIG_CGROUP_FREEZER=y
1643 +CONFIG_CGROUP_DEVICE=y
1644 +CONFIG_CGROUP_CPUACCT=y
1645 +CONFIG_RESOURCE_COUNTERS=y
1646 +CONFIG_MEMCG=y
1647 +CONFIG_BLK_CGROUP=y
1648 +CONFIG_NAMESPACES=y
1649 +CONFIG_SCHED_AUTOGROUP=y
1650 +CONFIG_RELAY=y
1651 +CONFIG_BLK_DEV_INITRD=y
1652 +CONFIG_EMBEDDED=y
1653 +# CONFIG_PERF_EVENTS is not set
1654 +# CONFIG_COMPAT_BRK is not set
1655 +CONFIG_PROFILING=y
1656 +CONFIG_JUMP_LABEL=y
1657 +CONFIG_BLK_DEV_BSGLIB=y
1658 +CONFIG_BLK_DEV_THROTTLING=y
1659 +CONFIG_CFQ_GROUP_IOSCHED=y
1660 +CONFIG_ARCH_BCM2709=y
1661 +# CONFIG_CACHE_L2X0 is not set
1662 +CONFIG_SMP=y
1663 +CONFIG_HAVE_ARM_ARCH_TIMER=y
1664 +CONFIG_HOTPLUG_CPU=y
1665 +CONFIG_PREEMPT=y
1666 +CONFIG_AEABI=y
1667 +CONFIG_CMA=y
1668 +CONFIG_UACCESS_WITH_MEMCPY=y
1669 +CONFIG_SECCOMP=y
1670 +CONFIG_ZBOOT_ROM_TEXT=0x0
1671 +CONFIG_ZBOOT_ROM_BSS=0x0
1672 +CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
1673 +CONFIG_CPU_IDLE=y
1674 +CONFIG_VFP=y
1675 +# CONFIG_COREDUMP is not set
1676 +# CONFIG_SUSPEND is not set
1677 +CONFIG_NET=y
1678 +CONFIG_UNIX=y
1679 +CONFIG_CGROUP_NET_CLASSID=y
1680 +# CONFIG_WIRELESS is not set
1681 +CONFIG_DEVTMPFS=y
1682 +CONFIG_DEVTMPFS_MOUNT=y
1683 +CONFIG_DMA_CMA=y
1684 +CONFIG_CMA_SIZE_MBYTES=8
1685 +CONFIG_BLK_DEV_LOOP=y
1686 +CONFIG_BLK_DEV_RAM=y
1687 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1688 +# CONFIG_INPUT_KEYBOARD is not set
1689 +# CONFIG_INPUT_MOUSE is not set
1690 +# CONFIG_SERIO is not set
1691 +# CONFIG_LEGACY_PTYS is not set
1692 +# CONFIG_DEVKMEM is not set
1693 +CONFIG_SERIAL_AMBA_PL011=y
1694 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1695 +CONFIG_TTY_PRINTK=y
1696 +# CONFIG_HW_RANDOM is not set
1697 +CONFIG_BRCM_CHAR_DRIVERS=y
1698 +CONFIG_BCM_VC_CMA=y
1699 +CONFIG_GPIO_SYSFS=y
1700 +# CONFIG_HWMON is not set
1701 +CONFIG_FB=y
1702 +CONFIG_FB_BCM2708=y
1703 +CONFIG_FRAMEBUFFER_CONSOLE=y
1704 +# CONFIG_HID is not set
1705 +# CONFIG_USB_SUPPORT is not set
1706 +CONFIG_MMC=y
1707 +CONFIG_MMC_BLOCK_MINORS=32
1708 +CONFIG_MMC_SDHCI=y
1709 +CONFIG_MMC_SDHCI_PLTFM=y
1710 +CONFIG_MMC_BCM2835=y
1711 +CONFIG_MMC_BCM2835_DMA=y
1712 +CONFIG_DMADEVICES=y
1713 +CONFIG_DMA_BCM2708=y
1714 +# CONFIG_IOMMU_SUPPORT is not set
1715 +CONFIG_EXT4_FS=y
1716 +CONFIG_EXT4_FS_POSIX_ACL=y
1717 +CONFIG_EXT4_FS_SECURITY=y
1718 +CONFIG_FANOTIFY=y
1719 +CONFIG_FSCACHE=y
1720 +CONFIG_FSCACHE_STATS=y
1721 +CONFIG_FSCACHE_HISTOGRAM=y
1722 +CONFIG_CACHEFILES=y
1723 +CONFIG_MSDOS_FS=y
1724 +CONFIG_VFAT_FS=y
1725 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1726 +CONFIG_TMPFS=y
1727 +CONFIG_TMPFS_POSIX_ACL=y
1728 +CONFIG_CONFIGFS_FS=y
1729 +# CONFIG_MISC_FILESYSTEMS is not set
1730 +# CONFIG_NETWORK_FILESYSTEMS is not set
1731 +CONFIG_NLS_DEFAULT="utf8"
1732 +CONFIG_NLS_CODEPAGE_437=y
1733 +CONFIG_NLS_ASCII=y
1734 +CONFIG_PRINTK_TIME=y
1735 +CONFIG_BOOT_PRINTK_DELAY=y
1736 +CONFIG_DEBUG_FS=y
1737 +CONFIG_MAGIC_SYSRQ=y
1738 +CONFIG_DETECT_HUNG_TASK=y
1739 +CONFIG_TIMER_STATS=y
1740 +# CONFIG_DEBUG_PREEMPT is not set
1741 +CONFIG_DEBUG_LL=y
1742 +CONFIG_EARLY_PRINTK=y
1743 +CONFIG_KEYS=y
1744 +CONFIG_CRYPTO_CBC=y
1745 +CONFIG_CRYPTO_AES=y
1746 +CONFIG_CRYPTO_DES=y
1747 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1748 +# CONFIG_CRYPTO_HW is not set
1749 +CONFIG_CRC_ITU_T=y
1750 +CONFIG_LIBCRC32C=y
1751 +CONFIG_AVERAGE=y
1752 --- /dev/null
1753 +++ b/arch/arm/configs/bcm2709_small_defconfig
1754 @@ -0,0 +1,61 @@
1755 +CONFIG_LOCALVERSION="-small"
1756 +# CONFIG_LOCALVERSION_AUTO is not set
1757 +# CONFIG_SWAP is not set
1758 +CONFIG_SYSVIPC=y
1759 +CONFIG_HIGH_RES_TIMERS=y
1760 +CONFIG_LOG_BUF_SHIFT=16
1761 +CONFIG_BLK_DEV_INITRD=y
1762 +CONFIG_INITRAMFS_SOURCE="../target_fs"
1763 +CONFIG_SLAB=y
1764 +# CONFIG_BLK_DEV_BSG is not set
1765 +# CONFIG_IOSCHED_CFQ is not set
1766 +CONFIG_ARCH_BCM2709=y
1767 +# CONFIG_BCM2708_GPIO is not set
1768 +# CONFIG_BCM2708_VCMEM is not set
1769 +CONFIG_ARM_THUMBEE=y
1770 +# CONFIG_SWP_EMULATE is not set
1771 +# CONFIG_CACHE_L2X0 is not set
1772 +CONFIG_ARM_ERRATA_720789=y
1773 +CONFIG_SMP=y
1774 +CONFIG_SCHED_MC=y
1775 +CONFIG_SCHED_SMT=y
1776 +CONFIG_HOTPLUG_CPU=y
1777 +CONFIG_PREEMPT=y
1778 +CONFIG_AEABI=y
1779 +CONFIG_HIGHMEM=y
1780 +CONFIG_HIGHPTE=y
1781 +# CONFIG_COMPACTION is not set
1782 +CONFIG_ZBOOT_ROM_TEXT=0x0
1783 +CONFIG_ZBOOT_ROM_BSS=0x0
1784 +CONFIG_CMDLINE="earlyprintk=ttyAMA0,19200 loglevel=9 console=ttyAMA0,19200"
1785 +CONFIG_AUTO_ZRELADDR=y
1786 +CONFIG_BINFMT_MISC=y
1787 +# CONFIG_SUSPEND is not set
1788 +# CONFIG_UEVENT_HELPER is not set
1789 +# CONFIG_FIRMWARE_IN_KERNEL is not set
1790 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1791 +# CONFIG_INPUT_KEYBOARD is not set
1792 +# CONFIG_INPUT_MOUSE is not set
1793 +# CONFIG_SERIO is not set
1794 +# CONFIG_LEGACY_PTYS is not set
1795 +# CONFIG_DEVKMEM is not set
1796 +CONFIG_SERIAL_AMBA_PL011=y
1797 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1798 +# CONFIG_HW_RANDOM is not set
1799 +# CONFIG_HWMON is not set
1800 +# CONFIG_HID is not set
1801 +# CONFIG_USB_SUPPORT is not set
1802 +# CONFIG_IOMMU_SUPPORT is not set
1803 +CONFIG_AUTOFS4_FS=y
1804 +# CONFIG_MISC_FILESYSTEMS is not set
1805 +CONFIG_PRINTK_TIME=y
1806 +CONFIG_FRAME_WARN=4096
1807 +CONFIG_MAGIC_SYSRQ=y
1808 +CONFIG_DEBUG_KERNEL=y
1809 +CONFIG_RCU_CPU_STALL_TIMEOUT=60
1810 +# CONFIG_FTRACE is not set
1811 +# CONFIG_ARM_UNWIND is not set
1812 +CONFIG_DEBUG_LL=y
1813 +CONFIG_EARLY_PRINTK=y
1814 +CONFIG_CRC16=y
1815 +CONFIG_CRC_ITU_T=y
1816 --- /dev/null
1817 +++ b/arch/arm/configs/bcm2835_sdcard_defconfig
1818 @@ -0,0 +1,176 @@
1819 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set
1820 +CONFIG_LOCALVERSION="-quick"
1821 +# CONFIG_LOCALVERSION_AUTO is not set
1822 +# CONFIG_SWAP is not set
1823 +CONFIG_SYSVIPC=y
1824 +CONFIG_POSIX_MQUEUE=y
1825 +CONFIG_NO_HZ=y
1826 +CONFIG_HIGH_RES_TIMERS=y
1827 +CONFIG_IKCONFIG=y
1828 +CONFIG_IKCONFIG_PROC=y
1829 +CONFIG_KALLSYMS_ALL=y
1830 +CONFIG_EMBEDDED=y
1831 +CONFIG_PERF_EVENTS=y
1832 +# CONFIG_COMPAT_BRK is not set
1833 +CONFIG_SLAB=y
1834 +# CONFIG_BLK_DEV_BSG is not set
1835 +CONFIG_ARCH_BCM2708=y
1836 +# CONFIG_BCM2708_GPIO is not set
1837 +CONFIG_PREEMPT=y
1838 +CONFIG_AEABI=y
1839 +CONFIG_UACCESS_WITH_MEMCPY=y
1840 +CONFIG_ZBOOT_ROM_TEXT=0x0
1841 +CONFIG_ZBOOT_ROM_BSS=0x0
1842 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
1843 +CONFIG_CPU_FREQ=y
1844 +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
1845 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
1846 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
1847 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
1848 +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
1849 +CONFIG_CPU_IDLE=y
1850 +CONFIG_VFP=y
1851 +CONFIG_BINFMT_MISC=y
1852 +CONFIG_NET=y
1853 +CONFIG_PACKET=y
1854 +CONFIG_UNIX=y
1855 +CONFIG_INET=y
1856 +CONFIG_IP_MULTICAST=y
1857 +CONFIG_IP_PNP=y
1858 +CONFIG_IP_PNP_DHCP=y
1859 +CONFIG_IP_PNP_RARP=y
1860 +CONFIG_SYN_COOKIES=y
1861 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1862 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1863 +# CONFIG_INET_XFRM_MODE_BEET is not set
1864 +# CONFIG_INET_LRO is not set
1865 +# CONFIG_INET_DIAG is not set
1866 +# CONFIG_IPV6 is not set
1867 +# CONFIG_WIRELESS is not set
1868 +CONFIG_DEVTMPFS=y
1869 +CONFIG_DEVTMPFS_MOUNT=y
1870 +CONFIG_BLK_DEV_LOOP=y
1871 +CONFIG_BLK_DEV_RAM=y
1872 +CONFIG_SCSI=y
1873 +# CONFIG_SCSI_PROC_FS is not set
1874 +# CONFIG_SCSI_LOWLEVEL is not set
1875 +CONFIG_NETDEVICES=y
1876 +CONFIG_MII=y
1877 +# CONFIG_NET_VENDOR_BROADCOM is not set
1878 +# CONFIG_NET_VENDOR_CIRRUS is not set
1879 +# CONFIG_NET_VENDOR_FARADAY is not set
1880 +# CONFIG_NET_VENDOR_INTEL is not set
1881 +# CONFIG_NET_VENDOR_MARVELL is not set
1882 +# CONFIG_NET_VENDOR_MICREL is not set
1883 +# CONFIG_NET_VENDOR_NATSEMI is not set
1884 +# CONFIG_NET_VENDOR_SEEQ is not set
1885 +# CONFIG_NET_VENDOR_STMICRO is not set
1886 +# CONFIG_NET_VENDOR_WIZNET is not set
1887 +CONFIG_PHYLIB=y
1888 +# CONFIG_WLAN is not set
1889 +# CONFIG_INPUT_MOUSEDEV is not set
1890 +CONFIG_INPUT_EVDEV=y
1891 +# CONFIG_INPUT_KEYBOARD is not set
1892 +# CONFIG_INPUT_MOUSE is not set
1893 +# CONFIG_SERIO is not set
1894 +CONFIG_VT_HW_CONSOLE_BINDING=y
1895 +# CONFIG_LEGACY_PTYS is not set
1896 +# CONFIG_DEVKMEM is not set
1897 +CONFIG_SERIAL_AMBA_PL011=y
1898 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1899 +CONFIG_TTY_PRINTK=y
1900 +CONFIG_RAW_DRIVER=y
1901 +CONFIG_WATCHDOG=y
1902 +CONFIG_REGULATOR=y
1903 +CONFIG_REGULATOR_DEBUG=y
1904 +CONFIG_REGULATOR_FIXED_VOLTAGE=y
1905 +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
1906 +CONFIG_REGULATOR_USERSPACE_CONSUMER=y
1907 +CONFIG_FB=y
1908 +CONFIG_FRAMEBUFFER_CONSOLE=y
1909 +CONFIG_LOGO=y
1910 +# CONFIG_LOGO_LINUX_MONO is not set
1911 +# CONFIG_LOGO_LINUX_VGA16 is not set
1912 +CONFIG_SOUND=y
1913 +CONFIG_SND=y
1914 +CONFIG_MMC=y
1915 +CONFIG_MMC_SDHCI=y
1916 +CONFIG_MMC_SDHCI_PLTFM=y
1917 +CONFIG_MMC_SDHCI_BCM2708=y
1918 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1919 +CONFIG_NEW_LEDS=y
1920 +CONFIG_LEDS_CLASS=y
1921 +CONFIG_LEDS_TRIGGERS=y
1922 +# CONFIG_IOMMU_SUPPORT is not set
1923 +CONFIG_EXT4_FS=y
1924 +CONFIG_EXT4_FS_POSIX_ACL=y
1925 +CONFIG_EXT4_FS_SECURITY=y
1926 +CONFIG_AUTOFS4_FS=y
1927 +CONFIG_FSCACHE=y
1928 +CONFIG_CACHEFILES=y
1929 +CONFIG_MSDOS_FS=y
1930 +CONFIG_VFAT_FS=y
1931 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1932 +CONFIG_TMPFS=y
1933 +CONFIG_TMPFS_POSIX_ACL=y
1934 +CONFIG_CONFIGFS_FS=y
1935 +# CONFIG_MISC_FILESYSTEMS is not set
1936 +CONFIG_NFS_FS=y
1937 +CONFIG_NFS_V3_ACL=y
1938 +CONFIG_NFS_V4=y
1939 +CONFIG_ROOT_NFS=y
1940 +CONFIG_NFS_FSCACHE=y
1941 +CONFIG_NLS_DEFAULT="utf8"
1942 +CONFIG_NLS_CODEPAGE_437=y
1943 +CONFIG_NLS_CODEPAGE_737=y
1944 +CONFIG_NLS_CODEPAGE_775=y
1945 +CONFIG_NLS_CODEPAGE_850=y
1946 +CONFIG_NLS_CODEPAGE_852=y
1947 +CONFIG_NLS_CODEPAGE_855=y
1948 +CONFIG_NLS_CODEPAGE_857=y
1949 +CONFIG_NLS_CODEPAGE_860=y
1950 +CONFIG_NLS_CODEPAGE_861=y
1951 +CONFIG_NLS_CODEPAGE_862=y
1952 +CONFIG_NLS_CODEPAGE_863=y
1953 +CONFIG_NLS_CODEPAGE_864=y
1954 +CONFIG_NLS_CODEPAGE_865=y
1955 +CONFIG_NLS_CODEPAGE_866=y
1956 +CONFIG_NLS_CODEPAGE_869=y
1957 +CONFIG_NLS_CODEPAGE_936=y
1958 +CONFIG_NLS_CODEPAGE_950=y
1959 +CONFIG_NLS_CODEPAGE_932=y
1960 +CONFIG_NLS_CODEPAGE_949=y
1961 +CONFIG_NLS_CODEPAGE_874=y
1962 +CONFIG_NLS_ISO8859_8=y
1963 +CONFIG_NLS_CODEPAGE_1250=y
1964 +CONFIG_NLS_CODEPAGE_1251=y
1965 +CONFIG_NLS_ASCII=y
1966 +CONFIG_NLS_ISO8859_1=y
1967 +CONFIG_NLS_ISO8859_2=y
1968 +CONFIG_NLS_ISO8859_3=y
1969 +CONFIG_NLS_ISO8859_4=y
1970 +CONFIG_NLS_ISO8859_5=y
1971 +CONFIG_NLS_ISO8859_6=y
1972 +CONFIG_NLS_ISO8859_7=y
1973 +CONFIG_NLS_ISO8859_9=y
1974 +CONFIG_NLS_ISO8859_13=y
1975 +CONFIG_NLS_ISO8859_14=y
1976 +CONFIG_NLS_ISO8859_15=y
1977 +CONFIG_NLS_UTF8=y
1978 +CONFIG_PRINTK_TIME=y
1979 +CONFIG_DEBUG_FS=y
1980 +# CONFIG_DEBUG_PREEMPT is not set
1981 +# CONFIG_DEBUG_BUGVERBOSE is not set
1982 +# CONFIG_FTRACE is not set
1983 +CONFIG_KGDB=y
1984 +CONFIG_KGDB_KDB=y
1985 +# CONFIG_ARM_UNWIND is not set
1986 +CONFIG_CRYPTO_CBC=y
1987 +CONFIG_CRYPTO_HMAC=y
1988 +CONFIG_CRYPTO_MD5=y
1989 +CONFIG_CRYPTO_SHA1=y
1990 +CONFIG_CRYPTO_DES=y
1991 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1992 +# CONFIG_CRYPTO_HW is not set
1993 +CONFIG_CRC_ITU_T=y
1994 +CONFIG_LIBCRC32C=y
1995 --- /dev/null
1996 +++ b/arch/arm/configs/bcmrpi_sdcard_defconfig
1997 @@ -0,0 +1,176 @@
1998 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set
1999 +CONFIG_LOCALVERSION="-quick"
2000 +# CONFIG_LOCALVERSION_AUTO is not set
2001 +# CONFIG_SWAP is not set
2002 +CONFIG_SYSVIPC=y
2003 +CONFIG_POSIX_MQUEUE=y
2004 +CONFIG_NO_HZ=y
2005 +CONFIG_HIGH_RES_TIMERS=y
2006 +CONFIG_IKCONFIG=y
2007 +CONFIG_IKCONFIG_PROC=y
2008 +CONFIG_KALLSYMS_ALL=y
2009 +CONFIG_EMBEDDED=y
2010 +CONFIG_PERF_EVENTS=y
2011 +# CONFIG_COMPAT_BRK is not set
2012 +CONFIG_SLAB=y
2013 +# CONFIG_BLK_DEV_BSG is not set
2014 +CONFIG_ARCH_BCM2708=y
2015 +CONFIG_PREEMPT=y
2016 +CONFIG_AEABI=y
2017 +CONFIG_UACCESS_WITH_MEMCPY=y
2018 +CONFIG_ZBOOT_ROM_TEXT=0x0
2019 +CONFIG_ZBOOT_ROM_BSS=0x0
2020 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
2021 +CONFIG_CPU_FREQ=y
2022 +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
2023 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
2024 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
2025 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
2026 +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
2027 +CONFIG_CPU_IDLE=y
2028 +CONFIG_VFP=y
2029 +CONFIG_BINFMT_MISC=y
2030 +CONFIG_NET=y
2031 +CONFIG_PACKET=y
2032 +CONFIG_UNIX=y
2033 +CONFIG_INET=y
2034 +CONFIG_IP_MULTICAST=y
2035 +CONFIG_IP_PNP=y
2036 +CONFIG_IP_PNP_DHCP=y
2037 +CONFIG_IP_PNP_RARP=y
2038 +CONFIG_SYN_COOKIES=y
2039 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
2040 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
2041 +# CONFIG_INET_XFRM_MODE_BEET is not set
2042 +# CONFIG_INET_LRO is not set
2043 +# CONFIG_INET_DIAG is not set
2044 +# CONFIG_IPV6 is not set
2045 +# CONFIG_WIRELESS is not set
2046 +CONFIG_DEVTMPFS=y
2047 +CONFIG_DEVTMPFS_MOUNT=y
2048 +CONFIG_BLK_DEV_LOOP=y
2049 +CONFIG_BLK_DEV_RAM=y
2050 +CONFIG_SCSI=y
2051 +# CONFIG_SCSI_PROC_FS is not set
2052 +# CONFIG_SCSI_LOWLEVEL is not set
2053 +CONFIG_NETDEVICES=y
2054 +CONFIG_MII=y
2055 +# CONFIG_NET_VENDOR_BROADCOM is not set
2056 +# CONFIG_NET_VENDOR_CIRRUS is not set
2057 +# CONFIG_NET_VENDOR_FARADAY is not set
2058 +# CONFIG_NET_VENDOR_INTEL is not set
2059 +# CONFIG_NET_VENDOR_MARVELL is not set
2060 +# CONFIG_NET_VENDOR_MICREL is not set
2061 +# CONFIG_NET_VENDOR_NATSEMI is not set
2062 +# CONFIG_NET_VENDOR_SEEQ is not set
2063 +# CONFIG_NET_VENDOR_STMICRO is not set
2064 +# CONFIG_NET_VENDOR_WIZNET is not set
2065 +CONFIG_PHYLIB=y
2066 +# CONFIG_WLAN is not set
2067 +# CONFIG_INPUT_MOUSEDEV is not set
2068 +CONFIG_INPUT_EVDEV=y
2069 +# CONFIG_INPUT_KEYBOARD is not set
2070 +# CONFIG_INPUT_MOUSE is not set
2071 +# CONFIG_SERIO is not set
2072 +CONFIG_VT_HW_CONSOLE_BINDING=y
2073 +# CONFIG_LEGACY_PTYS is not set
2074 +# CONFIG_DEVKMEM is not set
2075 +CONFIG_SERIAL_AMBA_PL011=y
2076 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
2077 +CONFIG_TTY_PRINTK=y
2078 +CONFIG_RAW_DRIVER=y
2079 +CONFIG_WATCHDOG=y
2080 +CONFIG_REGULATOR=y
2081 +CONFIG_REGULATOR_DEBUG=y
2082 +CONFIG_REGULATOR_FIXED_VOLTAGE=y
2083 +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
2084 +CONFIG_REGULATOR_USERSPACE_CONSUMER=y
2085 +CONFIG_FB=y
2086 +CONFIG_FRAMEBUFFER_CONSOLE=y
2087 +CONFIG_LOGO=y
2088 +# CONFIG_LOGO_LINUX_MONO is not set
2089 +# CONFIG_LOGO_LINUX_VGA16 is not set
2090 +CONFIG_SOUND=y
2091 +CONFIG_SND=y
2092 +CONFIG_MMC=y
2093 +CONFIG_MMC_SDHCI=y
2094 +CONFIG_MMC_SDHCI_PLTFM=y
2095 +CONFIG_MMC_SDHCI_BCM2708=y
2096 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
2097 +CONFIG_NEW_LEDS=y
2098 +CONFIG_LEDS_CLASS=y
2099 +CONFIG_LEDS_TRIGGERS=y
2100 +# CONFIG_IOMMU_SUPPORT is not set
2101 +CONFIG_EXT4_FS=y
2102 +CONFIG_EXT4_FS_POSIX_ACL=y
2103 +CONFIG_EXT4_FS_SECURITY=y
2104 +CONFIG_AUTOFS4_FS=y
2105 +CONFIG_FSCACHE=y
2106 +CONFIG_CACHEFILES=y
2107 +CONFIG_MSDOS_FS=y
2108 +CONFIG_VFAT_FS=y
2109 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
2110 +CONFIG_TMPFS=y
2111 +CONFIG_TMPFS_POSIX_ACL=y
2112 +CONFIG_CONFIGFS_FS=y
2113 +# CONFIG_MISC_FILESYSTEMS is not set
2114 +CONFIG_NFS_FS=y
2115 +CONFIG_NFS_V3_ACL=y
2116 +CONFIG_NFS_V4=y
2117 +CONFIG_ROOT_NFS=y
2118 +CONFIG_NFS_FSCACHE=y
2119 +CONFIG_NLS_DEFAULT="utf8"
2120 +CONFIG_NLS_CODEPAGE_437=y
2121 +CONFIG_NLS_CODEPAGE_737=y
2122 +CONFIG_NLS_CODEPAGE_775=y
2123 +CONFIG_NLS_CODEPAGE_850=y
2124 +CONFIG_NLS_CODEPAGE_852=y
2125 +CONFIG_NLS_CODEPAGE_855=y
2126 +CONFIG_NLS_CODEPAGE_857=y
2127 +CONFIG_NLS_CODEPAGE_860=y
2128 +CONFIG_NLS_CODEPAGE_861=y
2129 +CONFIG_NLS_CODEPAGE_862=y
2130 +CONFIG_NLS_CODEPAGE_863=y
2131 +CONFIG_NLS_CODEPAGE_864=y
2132 +CONFIG_NLS_CODEPAGE_865=y
2133 +CONFIG_NLS_CODEPAGE_866=y
2134 +CONFIG_NLS_CODEPAGE_869=y
2135 +CONFIG_NLS_CODEPAGE_936=y
2136 +CONFIG_NLS_CODEPAGE_950=y
2137 +CONFIG_NLS_CODEPAGE_932=y
2138 +CONFIG_NLS_CODEPAGE_949=y
2139 +CONFIG_NLS_CODEPAGE_874=y
2140 +CONFIG_NLS_ISO8859_8=y
2141 +CONFIG_NLS_CODEPAGE_1250=y
2142 +CONFIG_NLS_CODEPAGE_1251=y
2143 +CONFIG_NLS_ASCII=y
2144 +CONFIG_NLS_ISO8859_1=y
2145 +CONFIG_NLS_ISO8859_2=y
2146 +CONFIG_NLS_ISO8859_3=y
2147 +CONFIG_NLS_ISO8859_4=y
2148 +CONFIG_NLS_ISO8859_5=y
2149 +CONFIG_NLS_ISO8859_6=y
2150 +CONFIG_NLS_ISO8859_7=y
2151 +CONFIG_NLS_ISO8859_9=y
2152 +CONFIG_NLS_ISO8859_13=y
2153 +CONFIG_NLS_ISO8859_14=y
2154 +CONFIG_NLS_ISO8859_15=y
2155 +CONFIG_NLS_UTF8=y
2156 +CONFIG_PRINTK_TIME=y
2157 +CONFIG_DEBUG_FS=y
2158 +CONFIG_DETECT_HUNG_TASK=y
2159 +# CONFIG_DEBUG_PREEMPT is not set
2160 +# CONFIG_DEBUG_BUGVERBOSE is not set
2161 +# CONFIG_FTRACE is not set
2162 +CONFIG_KGDB=y
2163 +CONFIG_KGDB_KDB=y
2164 +# CONFIG_ARM_UNWIND is not set
2165 +CONFIG_CRYPTO_CBC=y
2166 +CONFIG_CRYPTO_HMAC=y
2167 +CONFIG_CRYPTO_MD5=y
2168 +CONFIG_CRYPTO_SHA1=y
2169 +CONFIG_CRYPTO_DES=y
2170 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
2171 +# CONFIG_CRYPTO_HW is not set
2172 +CONFIG_CRC_ITU_T=y
2173 +CONFIG_LIBCRC32C=y
2174 --- /dev/null
2175 +++ b/arch/arm/configs/bcmrpi_small_defconfig
2176 @@ -0,0 +1,103 @@
2177 +CONFIG_LOCALVERSION="-quick"
2178 +# CONFIG_LOCALVERSION_AUTO is not set
2179 +# CONFIG_SWAP is not set
2180 +CONFIG_SYSVIPC=y
2181 +CONFIG_NO_HZ=y
2182 +CONFIG_HIGH_RES_TIMERS=y
2183 +CONFIG_IKCONFIG=y
2184 +CONFIG_IKCONFIG_PROC=y
2185 +CONFIG_KALLSYMS_ALL=y
2186 +CONFIG_PERF_EVENTS=y
2187 +# CONFIG_COMPAT_BRK is not set
2188 +# CONFIG_BLK_DEV_BSG is not set
2189 +CONFIG_ARCH_BCM2836=y
2190 +# CONFIG_BCM2708_GPIO is not set
2191 +# CONFIG_BCM2708_VCMEM is not set
2192 +# CONFIG_CACHE_L2X0 is not set
2193 +CONFIG_SMP=y
2194 +CONFIG_HAVE_ARM_ARCH_TIMER=y
2195 +CONFIG_PREEMPT=y
2196 +CONFIG_AEABI=y
2197 +CONFIG_ZBOOT_ROM_TEXT=0x0
2198 +CONFIG_ZBOOT_ROM_BSS=0x0
2199 +CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
2200 +CONFIG_CPU_IDLE=y
2201 +# CONFIG_SUSPEND is not set
2202 +CONFIG_DEVTMPFS=y
2203 +CONFIG_DEVTMPFS_MOUNT=y
2204 +CONFIG_BLK_DEV_LOOP=y
2205 +CONFIG_BLK_DEV_RAM=y
2206 +# CONFIG_BCM2708_VCHIQ is not set
2207 +# CONFIG_INPUT_MOUSEDEV is not set
2208 +CONFIG_INPUT_EVDEV=y
2209 +# CONFIG_INPUT_KEYBOARD is not set
2210 +# CONFIG_INPUT_MOUSE is not set
2211 +# CONFIG_SERIO is not set
2212 +# CONFIG_LEGACY_PTYS is not set
2213 +# CONFIG_DEVKMEM is not set
2214 +CONFIG_SERIAL_AMBA_PL011=y
2215 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
2216 +CONFIG_RAW_DRIVER=y
2217 +# CONFIG_HID is not set
2218 +CONFIG_DMADEVICES=y
2219 +# CONFIG_IOMMU_SUPPORT is not set
2220 +CONFIG_TMPFS=y
2221 +CONFIG_TMPFS_POSIX_ACL=y
2222 +# CONFIG_MISC_FILESYSTEMS is not set
2223 +CONFIG_NLS=y
2224 +CONFIG_NLS_DEFAULT="utf8"
2225 +CONFIG_NLS_CODEPAGE_437=y
2226 +CONFIG_NLS_CODEPAGE_737=y
2227 +CONFIG_NLS_CODEPAGE_775=y
2228 +CONFIG_NLS_CODEPAGE_850=y
2229 +CONFIG_NLS_CODEPAGE_852=y
2230 +CONFIG_NLS_CODEPAGE_855=y
2231 +CONFIG_NLS_CODEPAGE_857=y
2232 +CONFIG_NLS_CODEPAGE_860=y
2233 +CONFIG_NLS_CODEPAGE_861=y
2234 +CONFIG_NLS_CODEPAGE_862=y
2235 +CONFIG_NLS_CODEPAGE_863=y
2236 +CONFIG_NLS_CODEPAGE_864=y
2237 +CONFIG_NLS_CODEPAGE_865=y
2238 +CONFIG_NLS_CODEPAGE_866=y
2239 +CONFIG_NLS_CODEPAGE_869=y
2240 +CONFIG_NLS_CODEPAGE_936=y
2241 +CONFIG_NLS_CODEPAGE_950=y
2242 +CONFIG_NLS_CODEPAGE_932=y
2243 +CONFIG_NLS_CODEPAGE_949=y
2244 +CONFIG_NLS_CODEPAGE_874=y
2245 +CONFIG_NLS_ISO8859_8=y
2246 +CONFIG_NLS_CODEPAGE_1250=y
2247 +CONFIG_NLS_CODEPAGE_1251=y
2248 +CONFIG_NLS_ASCII=y
2249 +CONFIG_NLS_ISO8859_1=y
2250 +CONFIG_NLS_ISO8859_2=y
2251 +CONFIG_NLS_ISO8859_3=y
2252 +CONFIG_NLS_ISO8859_4=y
2253 +CONFIG_NLS_ISO8859_5=y
2254 +CONFIG_NLS_ISO8859_6=y
2255 +CONFIG_NLS_ISO8859_7=y
2256 +CONFIG_NLS_ISO8859_9=y
2257 +CONFIG_NLS_ISO8859_13=y
2258 +CONFIG_NLS_ISO8859_14=y
2259 +CONFIG_NLS_ISO8859_15=y
2260 +CONFIG_NLS_UTF8=y
2261 +CONFIG_PRINTK_TIME=y
2262 +CONFIG_DEBUG_KERNEL=y
2263 +# CONFIG_DEBUG_PREEMPT is not set
2264 +# CONFIG_FTRACE is not set
2265 +CONFIG_KGDB=y
2266 +CONFIG_KGDB_KDB=y
2267 +# CONFIG_ARM_UNWIND is not set
2268 +CONFIG_DEBUG_LL=y
2269 +CONFIG_EARLY_PRINTK=y
2270 +CONFIG_CRYPTO_CBC=y
2271 +CONFIG_CRYPTO_HMAC=y
2272 +CONFIG_CRYPTO_MD5=y
2273 +CONFIG_CRYPTO_SHA1=y
2274 +CONFIG_CRYPTO_DES=y
2275 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
2276 +# CONFIG_CRYPTO_HW is not set
2277 +CONFIG_CRC16=y
2278 +CONFIG_CRC_ITU_T=y
2279 +CONFIG_LIBCRC32C=y
2280 --- a/arch/arm/kernel/head.S
2281 +++ b/arch/arm/kernel/head.S
2282 @@ -673,6 +673,14 @@ ARM_BE8(rev16 ip, ip)
2283 ldrcc r7, [r4], #4 @ use branch for delay slot
2284 bcc 1b
2285 ret lr
2286 + nop
2287 + nop
2288 + nop
2289 + nop
2290 + nop
2291 + nop
2292 + nop
2293 + nop
2294 #endif
2295 ENDPROC(__fixup_a_pv_table)
2296
2297 --- /dev/null
2298 +++ b/arch/arm/mach-bcm2709/Kconfig
2299 @@ -0,0 +1,49 @@
2300 +menu "Broadcom BCM2709 Implementations"
2301 + depends on ARCH_BCM2709
2302 +
2303 +config MACH_BCM2709
2304 + bool "Broadcom BCM2709 Development Platform"
2305 + help
2306 + Include support for the Broadcom(R) BCM2709 platform.
2307 +
2308 +config BCM2709_DT
2309 + bool "BCM2709 Device Tree support"
2310 + depends on MACH_BCM2709
2311 + default n
2312 + select USE_OF
2313 + select ARCH_REQUIRE_GPIOLIB
2314 + select PINCTRL
2315 + select PINCTRL_BCM2835
2316 + help
2317 + Enable Device Tree support for BCM2709
2318 +
2319 +config BCM2708_GPIO
2320 + bool "BCM2709 gpio support"
2321 + depends on MACH_BCM2709
2322 + select ARCH_REQUIRE_GPIOLIB
2323 + default y
2324 + help
2325 + Include support for the Broadcom(R) BCM2709 gpio.
2326 +
2327 +config BCM2708_VCMEM
2328 + bool "Videocore Memory"
2329 + depends on MACH_BCM2709
2330 + default y
2331 + help
2332 + Helper for videocore memory access and total size allocation.
2333 +
2334 +config BCM2708_NOL2CACHE
2335 + bool "Videocore L2 cache disable"
2336 + depends on MACH_BCM2709
2337 + default y
2338 + help
2339 + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
2340 +
2341 +config BCM2708_SPIDEV
2342 + bool "Bind spidev to SPI0 master"
2343 + depends on MACH_BCM2709
2344 + depends on SPI
2345 + default y
2346 + help
2347 + Binds spidev driver to the SPI0 master
2348 +endmenu
2349 --- /dev/null
2350 +++ b/arch/arm/mach-bcm2709/Makefile
2351 @@ -0,0 +1,7 @@
2352 +#
2353 +# Makefile for the linux kernel.
2354 +#
2355 +
2356 +obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o vcio.o power.o dma.o
2357 +obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o
2358 +obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o
2359 --- /dev/null
2360 +++ b/arch/arm/mach-bcm2709/Makefile.boot
2361 @@ -0,0 +1,3 @@
2362 + zreladdr-y := 0x00008000
2363 +params_phys-y := 0x00000100
2364 +initrd_phys-y := 0x00800000
2365 --- /dev/null
2366 +++ b/arch/arm/mach-bcm2709/armctrl.c
2367 @@ -0,0 +1,357 @@
2368 +/*
2369 + * linux/arch/arm/mach-bcm2708/armctrl.c
2370 + *
2371 + * Copyright (C) 2010 Broadcom
2372 + *
2373 + * This program is free software; you can redistribute it and/or modify
2374 + * it under the terms of the GNU General Public License as published by
2375 + * the Free Software Foundation; either version 2 of the License, or
2376 + * (at your option) any later version.
2377 + *
2378 + * This program is distributed in the hope that it will be useful,
2379 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2380 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2381 + * GNU General Public License for more details.
2382 + *
2383 + * You should have received a copy of the GNU General Public License
2384 + * along with this program; if not, write to the Free Software
2385 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2386 + */
2387 +#include <linux/init.h>
2388 +#include <linux/list.h>
2389 +#include <linux/io.h>
2390 +#include <linux/version.h>
2391 +#include <linux/syscore_ops.h>
2392 +#include <linux/interrupt.h>
2393 +#include <linux/irqdomain.h>
2394 +#include <linux/of.h>
2395 +
2396 +#include <asm/mach/irq.h>
2397 +#include <mach/hardware.h>
2398 +#include "armctrl.h"
2399 +
2400 +/* For support of kernels >= 3.0 assume only one VIC for now*/
2401 +static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
2402 + INTERRUPT_VC_JPEG,
2403 + INTERRUPT_VC_USB,
2404 + INTERRUPT_VC_3D,
2405 + INTERRUPT_VC_DMA2,
2406 + INTERRUPT_VC_DMA3,
2407 + INTERRUPT_VC_I2C,
2408 + INTERRUPT_VC_SPI,
2409 + INTERRUPT_VC_I2SPCM,
2410 + INTERRUPT_VC_SDIO,
2411 + INTERRUPT_VC_UART,
2412 + INTERRUPT_VC_ARASANSDIO
2413 +};
2414 +
2415 +static void armctrl_mask_irq(struct irq_data *d)
2416 +{
2417 + static const unsigned int disables[4] = {
2418 + ARM_IRQ_DIBL1,
2419 + ARM_IRQ_DIBL2,
2420 + ARM_IRQ_DIBL3,
2421 + 0
2422 + };
2423 + int i;
2424 + if (d->irq >= FIQ_START) {
2425 + writel(0, __io_address(ARM_IRQ_FAST));
2426 + } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) {
2427 +#if 1
2428 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ;
2429 + for (i=0; i<4; i++) // i = raw_smp_processor_id(); //
2430 + {
2431 + unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
2432 + writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
2433 + }
2434 +#endif
2435 + } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) {
2436 +#if 0
2437 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0;
2438 + for (i=0; i<4; i++) {
2439 + unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
2440 + writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
2441 + }
2442 +#endif
2443 + } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) {
2444 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
2445 + writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
2446 + } else { printk("%s: %d\n", __func__, d->irq); BUG(); }
2447 +}
2448 +
2449 +static void armctrl_unmask_irq(struct irq_data *d)
2450 +{
2451 + static const unsigned int enables[4] = {
2452 + ARM_IRQ_ENBL1,
2453 + ARM_IRQ_ENBL2,
2454 + ARM_IRQ_ENBL3,
2455 + 0
2456 + };
2457 + int i;
2458 + if (d->irq >= FIQ_START) {
2459 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
2460 + writel(0x80 | data, __io_address(ARM_IRQ_FAST));
2461 + } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) {
2462 +#if 1
2463 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ;
2464 + for (i=0; i<4; i++) // i = raw_smp_processor_id();
2465 + {
2466 + unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
2467 + writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
2468 + }
2469 +#endif
2470 + } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) {
2471 +#if 0
2472 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0;
2473 + for (i=0; i<4; i++) {
2474 + unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
2475 + writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
2476 + }
2477 +#endif
2478 + } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) {
2479 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
2480 + writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
2481 + } else { printk("%s: %d\n", __func__, d->irq); BUG(); }
2482 +}
2483 +
2484 +#ifdef CONFIG_OF
2485 +
2486 +#define NR_IRQS_BANK0 21
2487 +#define NR_BANKS 4
2488 +#define IRQS_PER_BANK 32
2489 +
2490 +/* from drivers/irqchip/irq-bcm2835.c */
2491 +static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
2492 + const u32 *intspec, unsigned int intsize,
2493 + unsigned long *out_hwirq, unsigned int *out_type)
2494 +{
2495 + if (WARN_ON(intsize != 2))
2496 + return -EINVAL;
2497 +
2498 + if (WARN_ON(intspec[0] >= NR_BANKS))
2499 + return -EINVAL;
2500 +
2501 + if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
2502 + return -EINVAL;
2503 +
2504 + if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
2505 + return -EINVAL;
2506 +
2507 + if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5))
2508 + return -EINVAL;
2509 +
2510 + if (intspec[0] == 0)
2511 + *out_hwirq = ARM_IRQ0_BASE + intspec[1];
2512 + else if (intspec[0] == 1)
2513 + *out_hwirq = ARM_IRQ1_BASE + intspec[1];
2514 + else if (intspec[0] == 2)
2515 + *out_hwirq = ARM_IRQ2_BASE + intspec[1];
2516 + else
2517 + *out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1];
2518 +
2519 + /* reverse remap_irqs[] */
2520 + switch (*out_hwirq) {
2521 + case INTERRUPT_VC_JPEG:
2522 + *out_hwirq = INTERRUPT_JPEG;
2523 + break;
2524 + case INTERRUPT_VC_USB:
2525 + *out_hwirq = INTERRUPT_USB;
2526 + break;
2527 + case INTERRUPT_VC_3D:
2528 + *out_hwirq = INTERRUPT_3D;
2529 + break;
2530 + case INTERRUPT_VC_DMA2:
2531 + *out_hwirq = INTERRUPT_DMA2;
2532 + break;
2533 + case INTERRUPT_VC_DMA3:
2534 + *out_hwirq = INTERRUPT_DMA3;
2535 + break;
2536 + case INTERRUPT_VC_I2C:
2537 + *out_hwirq = INTERRUPT_I2C;
2538 + break;
2539 + case INTERRUPT_VC_SPI:
2540 + *out_hwirq = INTERRUPT_SPI;
2541 + break;
2542 + case INTERRUPT_VC_I2SPCM:
2543 + *out_hwirq = INTERRUPT_I2SPCM;
2544 + break;
2545 + case INTERRUPT_VC_SDIO:
2546 + *out_hwirq = INTERRUPT_SDIO;
2547 + break;
2548 + case INTERRUPT_VC_UART:
2549 + *out_hwirq = INTERRUPT_UART;
2550 + break;
2551 + case INTERRUPT_VC_ARASANSDIO:
2552 + *out_hwirq = INTERRUPT_ARASANSDIO;
2553 + break;
2554 + }
2555 +
2556 + *out_type = IRQ_TYPE_NONE;
2557 + return 0;
2558 +}
2559 +
2560 +static struct irq_domain_ops armctrl_ops = {
2561 + .xlate = armctrl_xlate
2562 +};
2563 +
2564 +void __init armctrl_dt_init(void)
2565 +{
2566 + struct device_node *np;
2567 + struct irq_domain *domain;
2568 +
2569 + np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic");
2570 + if (!np)
2571 + return;
2572 +
2573 + domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS,
2574 + IRQ_ARMCTRL_START, 0,
2575 + &armctrl_ops, NULL);
2576 + WARN_ON(!domain);
2577 +}
2578 +#else
2579 +void __init armctrl_dt_init(void) { }
2580 +#endif /* CONFIG_OF */
2581 +
2582 +#if defined(CONFIG_PM)
2583 +
2584 +/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
2585 +
2586 +/* Static defines
2587 + * struct armctrl_device - VIC PM device (< 3.xx)
2588 + * @sysdev: The system device which is registered. (< 3.xx)
2589 + * @irq: The IRQ number for the base of the VIC.
2590 + * @base: The register base for the VIC.
2591 + * @resume_sources: A bitmask of interrupts for resume.
2592 + * @resume_irqs: The IRQs enabled for resume.
2593 + * @int_select: Save for VIC_INT_SELECT.
2594 + * @int_enable: Save for VIC_INT_ENABLE.
2595 + * @soft_int: Save for VIC_INT_SOFT.
2596 + * @protect: Save for VIC_PROTECT.
2597 + */
2598 +struct armctrl_info {
2599 + void __iomem *base;
2600 + int irq;
2601 + u32 resume_sources;
2602 + u32 resume_irqs;
2603 + u32 int_select;
2604 + u32 int_enable;
2605 + u32 soft_int;
2606 + u32 protect;
2607 +} armctrl;
2608 +
2609 +static int armctrl_suspend(void)
2610 +{
2611 + return 0;
2612 +}
2613 +
2614 +static void armctrl_resume(void)
2615 +{
2616 + return;
2617 +}
2618 +
2619 +/**
2620 + * armctrl_pm_register - Register a VIC for later power management control
2621 + * @base: The base address of the VIC.
2622 + * @irq: The base IRQ for the VIC.
2623 + * @resume_sources: bitmask of interrupts allowed for resume sources.
2624 + *
2625 + * For older kernels (< 3.xx) do -
2626 + * Register the VIC with the system device tree so that it can be notified
2627 + * of suspend and resume requests and ensure that the correct actions are
2628 + * taken to re-instate the settings on resume.
2629 + */
2630 +static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
2631 + u32 resume_sources)
2632 +{
2633 + armctrl.base = base;
2634 + armctrl.resume_sources = resume_sources;
2635 + armctrl.irq = irq;
2636 +}
2637 +
2638 +static int armctrl_set_wake(struct irq_data *d, unsigned int on)
2639 +{
2640 + unsigned int off = d->irq & 31;
2641 + u32 bit = 1 << off;
2642 +
2643 + if (!(bit & armctrl.resume_sources))
2644 + return -EINVAL;
2645 +
2646 + if (on)
2647 + armctrl.resume_irqs |= bit;
2648 + else
2649 + armctrl.resume_irqs &= ~bit;
2650 +
2651 + return 0;
2652 +}
2653 +
2654 +#else
2655 +static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
2656 + u32 arg1)
2657 +{
2658 +}
2659 +
2660 +#define armctrl_suspend NULL
2661 +#define armctrl_resume NULL
2662 +#define armctrl_set_wake NULL
2663 +#endif /* CONFIG_PM */
2664 +
2665 +static struct syscore_ops armctrl_syscore_ops = {
2666 + .suspend = armctrl_suspend,
2667 + .resume = armctrl_resume,
2668 +};
2669 +
2670 +/**
2671 + * armctrl_syscore_init - initicall to register VIC pm functions
2672 + *
2673 + * This is called via late_initcall() to register
2674 + * the resources for the VICs due to the early
2675 + * nature of the VIC's registration.
2676 +*/
2677 +static int __init armctrl_syscore_init(void)
2678 +{
2679 + register_syscore_ops(&armctrl_syscore_ops);
2680 + return 0;
2681 +}
2682 +
2683 +late_initcall(armctrl_syscore_init);
2684 +
2685 +static struct irq_chip armctrl_chip = {
2686 + .name = "ARMCTRL",
2687 + .irq_ack = NULL,
2688 + .irq_mask = armctrl_mask_irq,
2689 + .irq_unmask = armctrl_unmask_irq,
2690 + .irq_set_wake = armctrl_set_wake,
2691 +};
2692 +
2693 +/**
2694 + * armctrl_init - initialise a vectored interrupt controller
2695 + * @base: iomem base address
2696 + * @irq_start: starting interrupt number, must be muliple of 32
2697 + * @armctrl_sources: bitmask of interrupt sources to allow
2698 + * @resume_sources: bitmask of interrupt sources to allow for resume
2699 + */
2700 +int __init armctrl_init(void __iomem * base, unsigned int irq_start,
2701 + u32 armctrl_sources, u32 resume_sources)
2702 +{
2703 + unsigned int irq;
2704 +
2705 + for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) {
2706 + unsigned int data = irq;
2707 + if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
2708 + data = remap_irqs[irq - INTERRUPT_JPEG];
2709 + if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) {
2710 + irq_set_percpu_devid(irq);
2711 + irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq);
2712 + set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
2713 + } else {
2714 + irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq);
2715 + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
2716 + }
2717 + irq_set_chip_data(irq, (void *)data);
2718 + }
2719 +
2720 + armctrl_pm_register(base, irq_start, resume_sources);
2721 + init_FIQ(FIQ_START);
2722 + armctrl_dt_init();
2723 + return 0;
2724 +}
2725 --- /dev/null
2726 +++ b/arch/arm/mach-bcm2709/armctrl.h
2727 @@ -0,0 +1,27 @@
2728 +/*
2729 + * linux/arch/arm/mach-bcm2708/armctrl.h
2730 + *
2731 + * Copyright (C) 2010 Broadcom
2732 + *
2733 + * This program is free software; you can redistribute it and/or modify
2734 + * it under the terms of the GNU General Public License as published by
2735 + * the Free Software Foundation; either version 2 of the License, or
2736 + * (at your option) any later version.
2737 + *
2738 + * This program is distributed in the hope that it will be useful,
2739 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2740 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2741 + * GNU General Public License for more details.
2742 + *
2743 + * You should have received a copy of the GNU General Public License
2744 + * along with this program; if not, write to the Free Software
2745 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2746 + */
2747 +
2748 +#ifndef __BCM2708_ARMCTRL_H
2749 +#define __BCM2708_ARMCTRL_H
2750 +
2751 +extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
2752 + u32 armctrl_sources, u32 resume_sources);
2753 +
2754 +#endif
2755 --- /dev/null
2756 +++ b/arch/arm/mach-bcm2709/bcm2708_gpio.c
2757 @@ -0,0 +1,426 @@
2758 +/*
2759 + * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
2760 + *
2761 + * Copyright (C) 2010 Broadcom
2762 + *
2763 + * This program is free software; you can redistribute it and/or modify
2764 + * it under the terms of the GNU General Public License version 2 as
2765 + * published by the Free Software Foundation.
2766 + *
2767 + */
2768 +
2769 +#include <linux/spinlock.h>
2770 +#include <linux/module.h>
2771 +#include <linux/delay.h>
2772 +#include <linux/list.h>
2773 +#include <linux/io.h>
2774 +#include <linux/irq.h>
2775 +#include <linux/interrupt.h>
2776 +#include <linux/slab.h>
2777 +#include <mach/gpio.h>
2778 +#include <linux/gpio.h>
2779 +#include <linux/platform_device.h>
2780 +#include <mach/platform.h>
2781 +#include <linux/pinctrl/consumer.h>
2782 +
2783 +#include <linux/platform_data/bcm2708.h>
2784 +
2785 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
2786 +#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
2787 +#define BCM_GPIO_USE_IRQ 1
2788 +
2789 +#define GPIOFSEL(x) (0x00+(x)*4)
2790 +#define GPIOSET(x) (0x1c+(x)*4)
2791 +#define GPIOCLR(x) (0x28+(x)*4)
2792 +#define GPIOLEV(x) (0x34+(x)*4)
2793 +#define GPIOEDS(x) (0x40+(x)*4)
2794 +#define GPIOREN(x) (0x4c+(x)*4)
2795 +#define GPIOFEN(x) (0x58+(x)*4)
2796 +#define GPIOHEN(x) (0x64+(x)*4)
2797 +#define GPIOLEN(x) (0x70+(x)*4)
2798 +#define GPIOAREN(x) (0x7c+(x)*4)
2799 +#define GPIOAFEN(x) (0x88+(x)*4)
2800 +#define GPIOUD(x) (0x94+(x)*4)
2801 +#define GPIOUDCLK(x) (0x98+(x)*4)
2802 +
2803 +#define GPIO_BANKS 2
2804 +
2805 +enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
2806 + GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
2807 + GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
2808 + GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
2809 +};
2810 +
2811 + /* Each of the two spinlocks protects a different set of hardware
2812 + * regiters and data structurs. This decouples the code of the IRQ from
2813 + * the GPIO code. This also makes the case of a GPIO routine call from
2814 + * the IRQ code simpler.
2815 + */
2816 +static DEFINE_SPINLOCK(lock); /* GPIO registers */
2817 +
2818 +struct bcm2708_gpio {
2819 + struct list_head list;
2820 + void __iomem *base;
2821 + struct gpio_chip gc;
2822 + unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32];
2823 + unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32];
2824 + unsigned long high[(BCM2708_NR_GPIOS + 31) / 32];
2825 + unsigned long low[(BCM2708_NR_GPIOS + 31) / 32];
2826 +};
2827 +
2828 +static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
2829 + int function)
2830 +{
2831 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2832 + unsigned long flags;
2833 + unsigned gpiodir;
2834 + unsigned gpio_bank = offset / 10;
2835 + unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
2836 +
2837 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
2838 + if (offset >= BCM2708_NR_GPIOS)
2839 + return -EINVAL;
2840 +
2841 + spin_lock_irqsave(&lock, flags);
2842 +
2843 + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
2844 + gpiodir &= ~(7 << gpio_field_offset);
2845 + gpiodir |= function << gpio_field_offset;
2846 + writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
2847 + spin_unlock_irqrestore(&lock, flags);
2848 + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
2849 +
2850 + return 0;
2851 +}
2852 +
2853 +static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
2854 +{
2855 + return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
2856 +}
2857 +
2858 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2859 +static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
2860 + int value)
2861 +{
2862 + int ret;
2863 + ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
2864 + if (ret >= 0)
2865 + bcm2708_gpio_set(gc, offset, value);
2866 + return ret;
2867 +}
2868 +
2869 +static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
2870 +{
2871 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2872 + unsigned gpio_bank = offset / 32;
2873 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2874 + unsigned lev;
2875 +
2876 + if (offset >= BCM2708_NR_GPIOS)
2877 + return 0;
2878 + lev = readl(gpio->base + GPIOLEV(gpio_bank));
2879 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
2880 + return 0x1 & (lev >> gpio_field_offset);
2881 +}
2882 +
2883 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2884 +{
2885 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2886 + unsigned gpio_bank = offset / 32;
2887 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2888 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
2889 + if (offset >= BCM2708_NR_GPIOS)
2890 + return;
2891 + if (value)
2892 + writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
2893 + else
2894 + writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
2895 +}
2896 +
2897 +/**********************
2898 + * extension to configure pullups
2899 + */
2900 +int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset,
2901 + bcm2708_gpio_pull_t value)
2902 +{
2903 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2904 + unsigned gpio_bank = offset / 32;
2905 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2906 +
2907 + if (offset >= BCM2708_NR_GPIOS)
2908 + return -EINVAL;
2909 +
2910 + switch (value) {
2911 + case BCM2708_PULL_UP:
2912 + writel(2, gpio->base + GPIOUD(0));
2913 + break;
2914 + case BCM2708_PULL_DOWN:
2915 + writel(1, gpio->base + GPIOUD(0));
2916 + break;
2917 + case BCM2708_PULL_OFF:
2918 + writel(0, gpio->base + GPIOUD(0));
2919 + break;
2920 + }
2921 +
2922 + udelay(5);
2923 + writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
2924 + udelay(5);
2925 + writel(0, gpio->base + GPIOUD(0));
2926 + writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
2927 +
2928 + return 0;
2929 +}
2930 +EXPORT_SYMBOL(bcm2708_gpio_setpull);
2931 +
2932 +/*************************************************************************************************************************
2933 + * bcm2708 GPIO IRQ
2934 + */
2935 +
2936 +#if BCM_GPIO_USE_IRQ
2937 +
2938 +static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
2939 +{
2940 + return gpio_to_irq(gpio);
2941 +}
2942 +
2943 +static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
2944 +{
2945 + unsigned irq = d->irq;
2946 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2947 + unsigned gn = irq_to_gpio(irq);
2948 + unsigned gb = gn / 32;
2949 + unsigned go = gn % 32;
2950 +
2951 + gpio->rising[gb] &= ~(1 << go);
2952 + gpio->falling[gb] &= ~(1 << go);
2953 + gpio->high[gb] &= ~(1 << go);
2954 + gpio->low[gb] &= ~(1 << go);
2955 +
2956 + if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
2957 + return -EINVAL;
2958 +
2959 + if (type & IRQ_TYPE_EDGE_RISING)
2960 + gpio->rising[gb] |= (1 << go);
2961 + if (type & IRQ_TYPE_EDGE_FALLING)
2962 + gpio->falling[gb] |= (1 << go);
2963 + if (type & IRQ_TYPE_LEVEL_HIGH)
2964 + gpio->high[gb] |= (1 << go);
2965 + if (type & IRQ_TYPE_LEVEL_LOW)
2966 + gpio->low[gb] |= (1 << go);
2967 + return 0;
2968 +}
2969 +
2970 +static void bcm2708_gpio_irq_mask(struct irq_data *d)
2971 +{
2972 + unsigned irq = d->irq;
2973 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2974 + unsigned gn = irq_to_gpio(irq);
2975 + unsigned gb = gn / 32;
2976 + unsigned long rising = readl(gpio->base + GPIOREN(gb));
2977 + unsigned long falling = readl(gpio->base + GPIOFEN(gb));
2978 + unsigned long high = readl(gpio->base + GPIOHEN(gb));
2979 + unsigned long low = readl(gpio->base + GPIOLEN(gb));
2980 +
2981 + gn = gn % 32;
2982 +
2983 + writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
2984 + writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
2985 + writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb));
2986 + writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb));
2987 +}
2988 +
2989 +static void bcm2708_gpio_irq_unmask(struct irq_data *d)
2990 +{
2991 + unsigned irq = d->irq;
2992 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2993 + unsigned gn = irq_to_gpio(irq);
2994 + unsigned gb = gn / 32;
2995 + unsigned go = gn % 32;
2996 + unsigned long rising = readl(gpio->base + GPIOREN(gb));
2997 + unsigned long falling = readl(gpio->base + GPIOFEN(gb));
2998 + unsigned long high = readl(gpio->base + GPIOHEN(gb));
2999 + unsigned long low = readl(gpio->base + GPIOLEN(gb));
3000 +
3001 + if (gpio->rising[gb] & (1 << go)) {
3002 + writel(rising | (1 << go), gpio->base + GPIOREN(gb));
3003 + } else {
3004 + writel(rising & ~(1 << go), gpio->base + GPIOREN(gb));
3005 + }
3006 +
3007 + if (gpio->falling[gb] & (1 << go)) {
3008 + writel(falling | (1 << go), gpio->base + GPIOFEN(gb));
3009 + } else {
3010 + writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb));
3011 + }
3012 +
3013 + if (gpio->high[gb] & (1 << go)) {
3014 + writel(high | (1 << go), gpio->base + GPIOHEN(gb));
3015 + } else {
3016 + writel(high & ~(1 << go), gpio->base + GPIOHEN(gb));
3017 + }
3018 +
3019 + if (gpio->low[gb] & (1 << go)) {
3020 + writel(low | (1 << go), gpio->base + GPIOLEN(gb));
3021 + } else {
3022 + writel(low & ~(1 << go), gpio->base + GPIOLEN(gb));
3023 + }
3024 +}
3025 +
3026 +static struct irq_chip bcm2708_irqchip = {
3027 + .name = "GPIO",
3028 + .irq_enable = bcm2708_gpio_irq_unmask,
3029 + .irq_disable = bcm2708_gpio_irq_mask,
3030 + .irq_unmask = bcm2708_gpio_irq_unmask,
3031 + .irq_mask = bcm2708_gpio_irq_mask,
3032 + .irq_set_type = bcm2708_gpio_irq_set_type,
3033 +};
3034 +
3035 +static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
3036 +{
3037 + unsigned long edsr;
3038 + unsigned bank;
3039 + int i;
3040 + unsigned gpio;
3041 + unsigned level_bits;
3042 + struct bcm2708_gpio *gpio_data = dev_id;
3043 +
3044 + for (bank = 0; bank < GPIO_BANKS; bank++) {
3045 + edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
3046 + level_bits = gpio_data->high[bank] | gpio_data->low[bank];
3047 +
3048 + for_each_set_bit(i, &edsr, 32) {
3049 + gpio = i + bank * 32;
3050 + /* ack edge triggered IRQs immediately */
3051 + if (!(level_bits & (1<<i)))
3052 + writel(1<<i,
3053 + __io_address(GPIO_BASE) + GPIOEDS(bank));
3054 + generic_handle_irq(gpio_to_irq(gpio));
3055 + /* ack level triggered IRQ after handling them */
3056 + if (level_bits & (1<<i))
3057 + writel(1<<i,
3058 + __io_address(GPIO_BASE) + GPIOEDS(bank));
3059 + }
3060 + }
3061 + return IRQ_HANDLED;
3062 +}
3063 +
3064 +static struct irqaction bcm2708_gpio_irq = {
3065 + .name = "BCM2708 GPIO catchall handler",
3066 + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
3067 + .handler = bcm2708_gpio_interrupt,
3068 +};
3069 +
3070 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3071 +{
3072 + unsigned irq;
3073 +
3074 + ucb->gc.to_irq = bcm2708_gpio_to_irq;
3075 +
3076 + for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
3077 + irq_set_chip_data(irq, ucb);
3078 + irq_set_chip_and_handler(irq, &bcm2708_irqchip,
3079 + handle_simple_irq);
3080 + set_irq_flags(irq, IRQF_VALID);
3081 + }
3082 +
3083 + bcm2708_gpio_irq.dev_id = ucb;
3084 + setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
3085 +}
3086 +
3087 +#else
3088 +
3089 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3090 +{
3091 +}
3092 +
3093 +#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
3094 +
3095 +static int bcm2708_gpio_probe(struct platform_device *dev)
3096 +{
3097 + struct bcm2708_gpio *ucb;
3098 + struct resource *res;
3099 + int bank;
3100 + int err = 0;
3101 +
3102 + printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
3103 +
3104 + ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
3105 + if (NULL == ucb) {
3106 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
3107 + "mailbox memory\n");
3108 + err = -ENOMEM;
3109 + goto err;
3110 + }
3111 +
3112 + res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3113 +
3114 + platform_set_drvdata(dev, ucb);
3115 + ucb->base = __io_address(GPIO_BASE);
3116 +
3117 + ucb->gc.label = "bcm2708_gpio";
3118 + ucb->gc.base = 0;
3119 + ucb->gc.ngpio = BCM2708_NR_GPIOS;
3120 + ucb->gc.owner = THIS_MODULE;
3121 +
3122 + ucb->gc.direction_input = bcm2708_gpio_dir_in;
3123 + ucb->gc.direction_output = bcm2708_gpio_dir_out;
3124 + ucb->gc.get = bcm2708_gpio_get;
3125 + ucb->gc.set = bcm2708_gpio_set;
3126 + ucb->gc.can_sleep = 0;
3127 +
3128 + for (bank = 0; bank < GPIO_BANKS; bank++) {
3129 + writel(0, ucb->base + GPIOREN(bank));
3130 + writel(0, ucb->base + GPIOFEN(bank));
3131 + writel(0, ucb->base + GPIOHEN(bank));
3132 + writel(0, ucb->base + GPIOLEN(bank));
3133 + writel(0, ucb->base + GPIOAREN(bank));
3134 + writel(0, ucb->base + GPIOAFEN(bank));
3135 + writel(~0, ucb->base + GPIOEDS(bank));
3136 + }
3137 +
3138 + bcm2708_gpio_irq_init(ucb);
3139 +
3140 + err = gpiochip_add(&ucb->gc);
3141 +
3142 +err:
3143 + return err;
3144 +
3145 +}
3146 +
3147 +static int bcm2708_gpio_remove(struct platform_device *dev)
3148 +{
3149 + int err = 0;
3150 + struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
3151 +
3152 + printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
3153 +
3154 + gpiochip_remove(&ucb->gc);
3155 +
3156 + platform_set_drvdata(dev, NULL);
3157 + kfree(ucb);
3158 +
3159 + return err;
3160 +}
3161 +
3162 +static struct platform_driver bcm2708_gpio_driver = {
3163 + .probe = bcm2708_gpio_probe,
3164 + .remove = bcm2708_gpio_remove,
3165 + .driver = {
3166 + .name = "bcm2708_gpio"},
3167 +};
3168 +
3169 +static int __init bcm2708_gpio_init(void)
3170 +{
3171 + return platform_driver_register(&bcm2708_gpio_driver);
3172 +}
3173 +
3174 +static void __exit bcm2708_gpio_exit(void)
3175 +{
3176 + platform_driver_unregister(&bcm2708_gpio_driver);
3177 +}
3178 +
3179 +module_init(bcm2708_gpio_init);
3180 +module_exit(bcm2708_gpio_exit);
3181 +
3182 +MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
3183 +MODULE_LICENSE("GPL");
3184 --- /dev/null
3185 +++ b/arch/arm/mach-bcm2709/bcm2709.c
3186 @@ -0,0 +1,1237 @@
3187 +/*
3188 + * linux/arch/arm/mach-bcm2709/bcm2709.c
3189 + *
3190 + * Copyright (C) 2010 Broadcom
3191 + *
3192 + * This program is free software; you can redistribute it and/or modify
3193 + * it under the terms of the GNU General Public License as published by
3194 + * the Free Software Foundation; either version 2 of the License, or
3195 + * (at your option) any later version.
3196 + *
3197 + * This program is distributed in the hope that it will be useful,
3198 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3199 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3200 + * GNU General Public License for more details.
3201 + *
3202 + * You should have received a copy of the GNU General Public License
3203 + * along with this program; if not, write to the Free Software
3204 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3205 + */
3206 +
3207 +#include <linux/init.h>
3208 +#include <linux/device.h>
3209 +#include <linux/dma-mapping.h>
3210 +#include <linux/serial_8250.h>
3211 +#include <linux/platform_device.h>
3212 +#include <linux/syscore_ops.h>
3213 +#include <linux/interrupt.h>
3214 +#include <linux/amba/bus.h>
3215 +#include <linux/amba/clcd.h>
3216 +#include <linux/clk-provider.h>
3217 +#include <linux/clkdev.h>
3218 +#include <linux/clockchips.h>
3219 +#include <linux/cnt32_to_63.h>
3220 +#include <linux/io.h>
3221 +#include <linux/module.h>
3222 +#include <linux/of_platform.h>
3223 +#include <linux/spi/spi.h>
3224 +#include <linux/gpio/machine.h>
3225 +#include <linux/w1-gpio.h>
3226 +
3227 +#include <linux/version.h>
3228 +#include <linux/clkdev.h>
3229 +#include <asm/system_info.h>
3230 +#include <mach/hardware.h>
3231 +#include <asm/irq.h>
3232 +#include <linux/leds.h>
3233 +#include <asm/mach-types.h>
3234 +#include <asm/cputype.h>
3235 +#include <linux/sched_clock.h>
3236 +
3237 +#include <asm/mach/arch.h>
3238 +#include <asm/mach/flash.h>
3239 +#include <asm/mach/irq.h>
3240 +#include <asm/mach/time.h>
3241 +#include <asm/mach/map.h>
3242 +
3243 +#include <mach/timex.h>
3244 +#include <mach/dma.h>
3245 +#include <mach/vcio.h>
3246 +#include <mach/system.h>
3247 +
3248 +#include <linux/delay.h>
3249 +
3250 +#include "bcm2709.h"
3251 +#include "armctrl.h"
3252 +
3253 +#ifdef CONFIG_BCM_VC_CMA
3254 +#include <linux/broadcom/vc_cma.h>
3255 +#endif
3256 +
3257 +//#define SYSTEM_TIMER
3258 +
3259 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
3260 + * give us IO access only to 64Mbytes of physical memory (26 bits). We could
3261 + * represent this window by setting our dmamasks to 26 bits but, in fact
3262 + * we're not going to use addresses outside this range (they're not in real
3263 + * memory) so we don't bother.
3264 + *
3265 + * In the future we might include code to use this IOMMU to remap other
3266 + * physical addresses onto VideoCore memory then the use of 32-bits would be
3267 + * more legitimate.
3268 + */
3269 +#define DMA_MASK_BITS_COMMON 32
3270 +
3271 +// use GPIO 4 for the one-wire GPIO pin, if enabled
3272 +#define W1_GPIO 4
3273 +// ensure one-wire GPIO pullup is disabled by default
3274 +#define W1_PULLUP -1
3275 +
3276 +/* command line parameters */
3277 +static unsigned boardrev, serial;
3278 +static unsigned uart_clock = UART0_CLOCK;
3279 +static unsigned disk_led_gpio = 16;
3280 +static unsigned disk_led_active_low = 1;
3281 +static unsigned reboot_part = 0;
3282 +static unsigned w1_gpio_pin = W1_GPIO;
3283 +static unsigned w1_gpio_pullup = W1_PULLUP;
3284 +
3285 +static unsigned use_dt = 0;
3286 +
3287 +static void __init bcm2709_init_led(void);
3288 +
3289 +void __init bcm2709_init_irq(void)
3290 +{
3291 + armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
3292 +}
3293 +
3294 +static struct map_desc bcm2709_io_desc[] __initdata = {
3295 + {
3296 + .virtual = IO_ADDRESS(ARMCTRL_BASE),
3297 + .pfn = __phys_to_pfn(ARMCTRL_BASE),
3298 + .length = SZ_4K,
3299 + .type = MT_DEVICE},
3300 + {
3301 + .virtual = IO_ADDRESS(UART0_BASE),
3302 + .pfn = __phys_to_pfn(UART0_BASE),
3303 + .length = SZ_4K,
3304 + .type = MT_DEVICE},
3305 + {
3306 + .virtual = IO_ADDRESS(UART1_BASE),
3307 + .pfn = __phys_to_pfn(UART1_BASE),
3308 + .length = SZ_4K,
3309 + .type = MT_DEVICE},
3310 + {
3311 + .virtual = IO_ADDRESS(DMA_BASE),
3312 + .pfn = __phys_to_pfn(DMA_BASE),
3313 + .length = SZ_4K,
3314 + .type = MT_DEVICE},
3315 + {
3316 + .virtual = IO_ADDRESS(MCORE_BASE),
3317 + .pfn = __phys_to_pfn(MCORE_BASE),
3318 + .length = SZ_4K,
3319 + .type = MT_DEVICE},
3320 + {
3321 + .virtual = IO_ADDRESS(ST_BASE),
3322 + .pfn = __phys_to_pfn(ST_BASE),
3323 + .length = SZ_4K,
3324 + .type = MT_DEVICE},
3325 + {
3326 + .virtual = IO_ADDRESS(USB_BASE),
3327 + .pfn = __phys_to_pfn(USB_BASE),
3328 + .length = SZ_128K,
3329 + .type = MT_DEVICE},
3330 + {
3331 + .virtual = IO_ADDRESS(PM_BASE),
3332 + .pfn = __phys_to_pfn(PM_BASE),
3333 + .length = SZ_4K,
3334 + .type = MT_DEVICE},
3335 + {
3336 + .virtual = IO_ADDRESS(GPIO_BASE),
3337 + .pfn = __phys_to_pfn(GPIO_BASE),
3338 + .length = SZ_4K,
3339 + .type = MT_DEVICE},
3340 + {
3341 + .virtual = IO_ADDRESS(ARM_LOCAL_BASE),
3342 + .pfn = __phys_to_pfn(ARM_LOCAL_BASE),
3343 + .length = SZ_4K,
3344 + .type = MT_DEVICE},
3345 +};
3346 +
3347 +void __init bcm2709_map_io(void)
3348 +{
3349 + iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc));
3350 +}
3351 +
3352 +#ifdef SYSTEM_TIMER
3353 +
3354 +/* The STC is a free running counter that increments at the rate of 1MHz */
3355 +#define STC_FREQ_HZ 1000000
3356 +
3357 +static inline uint32_t timer_read(void)
3358 +{
3359 + /* STC: a free running counter that increments at the rate of 1MHz */
3360 + return readl(__io_address(ST_BASE + 0x04));
3361 +}
3362 +
3363 +static unsigned long bcm2709_read_current_timer(void)
3364 +{
3365 + return timer_read();
3366 +}
3367 +
3368 +static u64 notrace bcm2709_read_sched_clock(void)
3369 +{
3370 + return timer_read();
3371 +}
3372 +
3373 +static cycle_t clksrc_read(struct clocksource *cs)
3374 +{
3375 + return timer_read();
3376 +}
3377 +
3378 +static struct clocksource clocksource_stc = {
3379 + .name = "stc",
3380 + .rating = 300,
3381 + .read = clksrc_read,
3382 + .mask = CLOCKSOURCE_MASK(32),
3383 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
3384 +};
3385 +
3386 +unsigned long frc_clock_ticks32(void)
3387 +{
3388 + return timer_read();
3389 +}
3390 +
3391 +static void __init bcm2709_clocksource_init(void)
3392 +{
3393 + if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
3394 + printk(KERN_ERR "timer: failed to initialize clock "
3395 + "source %s\n", clocksource_stc.name);
3396 + }
3397 +}
3398 +#endif
3399 +
3400 +struct clk __init *bcm2709_clk_register(const char *name, unsigned long fixed_rate)
3401 +{
3402 + struct clk *clk;
3403 +
3404 + clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT,
3405 + fixed_rate);
3406 + if (IS_ERR(clk))
3407 + pr_err("%s not registered\n", name);
3408 +
3409 + return clk;
3410 +}
3411 +
3412 +void __init bcm2709_register_clkdev(struct clk *clk, const char *name)
3413 +{
3414 + int ret;
3415 +
3416 + ret = clk_register_clkdev(clk, NULL, name);
3417 + if (ret)
3418 + pr_err("%s alias not registered\n", name);
3419 +}
3420 +
3421 +void __init bcm2709_init_clocks(void)
3422 +{
3423 + struct clk *clk;
3424 +
3425 + clk = bcm2709_clk_register("uart0_clk", uart_clock);
3426 + bcm2709_register_clkdev(clk, "dev:f1");
3427 +
3428 + clk = bcm2709_clk_register("sdhost_clk", 250000000);
3429 + bcm2709_register_clkdev(clk, "bcm2708_spi.0");
3430 + bcm2709_register_clkdev(clk, "bcm2708_i2c.0");
3431 + bcm2709_register_clkdev(clk, "bcm2708_i2c.1");
3432 +}
3433 +
3434 +#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
3435 +#define UART0_DMA { 15, 14 }
3436 +
3437 +AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
3438 +
3439 +static struct amba_device *amba_devs[] __initdata = {
3440 + &uart0_device,
3441 +};
3442 +
3443 +static struct resource bcm2708_dmaman_resources[] = {
3444 + {
3445 + .start = DMA_BASE,
3446 + .end = DMA_BASE + SZ_4K - 1,
3447 + .flags = IORESOURCE_MEM,
3448 + }
3449 +};
3450 +
3451 +static struct platform_device bcm2708_dmaman_device = {
3452 + .name = BCM_DMAMAN_DRIVER_NAME,
3453 + .id = 0, /* first bcm2708_dma */
3454 + .resource = bcm2708_dmaman_resources,
3455 + .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources),
3456 +};
3457 +
3458 +#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
3459 +static struct w1_gpio_platform_data w1_gpio_pdata = {
3460 + .pin = W1_GPIO,
3461 + .ext_pullup_enable_pin = W1_PULLUP,
3462 + .is_open_drain = 0,
3463 +};
3464 +
3465 +static struct platform_device w1_device = {
3466 + .name = "w1-gpio",
3467 + .id = -1,
3468 + .dev.platform_data = &w1_gpio_pdata,
3469 +};
3470 +#endif
3471 +
3472 +static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3473 +
3474 +static struct platform_device bcm2708_fb_device = {
3475 + .name = "bcm2708_fb",
3476 + .id = -1, /* only one bcm2708_fb */
3477 + .resource = NULL,
3478 + .num_resources = 0,
3479 + .dev = {
3480 + .dma_mask = &fb_dmamask,
3481 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3482 + },
3483 +};
3484 +
3485 +static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
3486 + {
3487 + .mapbase = UART1_BASE + 0x40,
3488 + .irq = IRQ_AUX,
3489 + .uartclk = 125000000,
3490 + .regshift = 2,
3491 + .iotype = UPIO_MEM,
3492 + .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
3493 + .type = PORT_8250,
3494 + },
3495 + {},
3496 +};
3497 +
3498 +static struct platform_device bcm2708_uart1_device = {
3499 + .name = "serial8250",
3500 + .id = PLAT8250_DEV_PLATFORM,
3501 + .dev = {
3502 + .platform_data = bcm2708_uart1_platform_data,
3503 + },
3504 +};
3505 +
3506 +static struct resource bcm2708_usb_resources[] = {
3507 + [0] = {
3508 + .start = USB_BASE,
3509 + .end = USB_BASE + SZ_128K - 1,
3510 + .flags = IORESOURCE_MEM,
3511 + },
3512 + [1] = {
3513 + .start = MPHI_BASE,
3514 + .end = MPHI_BASE + SZ_4K - 1,
3515 + .flags = IORESOURCE_MEM,
3516 + },
3517 + [2] = {
3518 + .start = IRQ_HOSTPORT,
3519 + .end = IRQ_HOSTPORT,
3520 + .flags = IORESOURCE_IRQ,
3521 + },
3522 + [3] = {
3523 + .start = IRQ_USB,
3524 + .end = IRQ_USB,
3525 + .flags = IORESOURCE_IRQ,
3526 + },
3527 +};
3528 +
3529 +
3530 +static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3531 +
3532 +static struct platform_device bcm2708_usb_device = {
3533 + .name = "bcm2708_usb",
3534 + .id = -1, /* only one bcm2708_usb */
3535 + .resource = bcm2708_usb_resources,
3536 + .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
3537 + .dev = {
3538 + .dma_mask = &usb_dmamask,
3539 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3540 + },
3541 +};
3542 +
3543 +static struct resource bcm2708_vcio_resources[] = {
3544 + [0] = { /* mailbox/semaphore/doorbell access */
3545 + .start = MCORE_BASE,
3546 + .end = MCORE_BASE + SZ_4K - 1,
3547 + .flags = IORESOURCE_MEM,
3548 + },
3549 +};
3550 +
3551 +static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3552 +
3553 +static struct platform_device bcm2708_vcio_device = {
3554 + .name = BCM_VCIO_DRIVER_NAME,
3555 + .id = -1, /* only one VideoCore I/O area */
3556 + .resource = bcm2708_vcio_resources,
3557 + .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
3558 + .dev = {
3559 + .dma_mask = &vcio_dmamask,
3560 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3561 + },
3562 +};
3563 +
3564 +#ifdef CONFIG_BCM2708_GPIO
3565 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
3566 +
3567 +static struct resource bcm2708_gpio_resources[] = {
3568 + [0] = { /* general purpose I/O */
3569 + .start = GPIO_BASE,
3570 + .end = GPIO_BASE + SZ_4K - 1,
3571 + .flags = IORESOURCE_MEM,
3572 + },
3573 +};
3574 +
3575 +static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3576 +
3577 +static struct platform_device bcm2708_gpio_device = {
3578 + .name = BCM_GPIO_DRIVER_NAME,
3579 + .id = -1, /* only one VideoCore I/O area */
3580 + .resource = bcm2708_gpio_resources,
3581 + .num_resources = ARRAY_SIZE(bcm2708_gpio_resources),
3582 + .dev = {
3583 + .dma_mask = &gpio_dmamask,
3584 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3585 + },
3586 +};
3587 +#endif
3588 +
3589 +#ifdef SYSTEM_TIMER
3590 +static struct resource bcm2708_systemtimer_resources[] = {
3591 + [0] = { /* system timer access */
3592 + .start = ST_BASE,
3593 + .end = ST_BASE + SZ_4K - 1,
3594 + .flags = IORESOURCE_MEM,
3595 + },
3596 + {
3597 + .start = IRQ_TIMER3,
3598 + .end = IRQ_TIMER3,
3599 + .flags = IORESOURCE_IRQ,
3600 + }
3601 +
3602 +};
3603 +
3604 +static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3605 +
3606 +static struct platform_device bcm2708_systemtimer_device = {
3607 + .name = "bcm2708_systemtimer",
3608 + .id = -1, /* only one VideoCore I/O area */
3609 + .resource = bcm2708_systemtimer_resources,
3610 + .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources),
3611 + .dev = {
3612 + .dma_mask = &systemtimer_dmamask,
3613 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3614 + },
3615 +};
3616 +#endif
3617 +
3618 +#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */
3619 +static struct resource bcm2835_emmc_resources[] = {
3620 + [0] = {
3621 + .start = EMMC_BASE,
3622 + .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */
3623 + /* the memory map actually makes SZ_4K available */
3624 + .flags = IORESOURCE_MEM,
3625 + },
3626 + [1] = {
3627 + .start = IRQ_ARASANSDIO,
3628 + .end = IRQ_ARASANSDIO,
3629 + .flags = IORESOURCE_IRQ,
3630 + },
3631 +};
3632 +
3633 +static u64 bcm2835_emmc_dmamask = 0xffffffffUL;
3634 +
3635 +struct platform_device bcm2835_emmc_device = {
3636 + .name = "mmc-bcm2835",
3637 + .id = 0,
3638 + .num_resources = ARRAY_SIZE(bcm2835_emmc_resources),
3639 + .resource = bcm2835_emmc_resources,
3640 + .dev = {
3641 + .dma_mask = &bcm2835_emmc_dmamask,
3642 + .coherent_dma_mask = 0xffffffffUL},
3643 +};
3644 +#endif /* CONFIG_MMC_BCM2835 */
3645 +
3646 +static struct resource bcm2708_powerman_resources[] = {
3647 + [0] = {
3648 + .start = PM_BASE,
3649 + .end = PM_BASE + SZ_256 - 1,
3650 + .flags = IORESOURCE_MEM,
3651 + },
3652 +};
3653 +
3654 +static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3655 +
3656 +struct platform_device bcm2708_powerman_device = {
3657 + .name = "bcm2708_powerman",
3658 + .id = 0,
3659 + .num_resources = ARRAY_SIZE(bcm2708_powerman_resources),
3660 + .resource = bcm2708_powerman_resources,
3661 + .dev = {
3662 + .dma_mask = &powerman_dmamask,
3663 + .coherent_dma_mask = 0xffffffffUL},
3664 +};
3665 +
3666 +
3667 +static struct platform_device bcm2708_alsa_devices[] = {
3668 + [0] = {
3669 + .name = "bcm2835_AUD0",
3670 + .id = 0, /* first audio device */
3671 + .resource = 0,
3672 + .num_resources = 0,
3673 + },
3674 + [1] = {
3675 + .name = "bcm2835_AUD1",
3676 + .id = 1, /* second audio device */
3677 + .resource = 0,
3678 + .num_resources = 0,
3679 + },
3680 + [2] = {
3681 + .name = "bcm2835_AUD2",
3682 + .id = 2, /* third audio device */
3683 + .resource = 0,
3684 + .num_resources = 0,
3685 + },
3686 + [3] = {
3687 + .name = "bcm2835_AUD3",
3688 + .id = 3, /* forth audio device */
3689 + .resource = 0,
3690 + .num_resources = 0,
3691 + },
3692 + [4] = {
3693 + .name = "bcm2835_AUD4",
3694 + .id = 4, /* fifth audio device */
3695 + .resource = 0,
3696 + .num_resources = 0,
3697 + },
3698 + [5] = {
3699 + .name = "bcm2835_AUD5",
3700 + .id = 5, /* sixth audio device */
3701 + .resource = 0,
3702 + .num_resources = 0,
3703 + },
3704 + [6] = {
3705 + .name = "bcm2835_AUD6",
3706 + .id = 6, /* seventh audio device */
3707 + .resource = 0,
3708 + .num_resources = 0,
3709 + },
3710 + [7] = {
3711 + .name = "bcm2835_AUD7",
3712 + .id = 7, /* eighth audio device */
3713 + .resource = 0,
3714 + .num_resources = 0,
3715 + },
3716 +};
3717 +
3718 +static struct resource bcm2708_spi_resources[] = {
3719 + {
3720 + .start = SPI0_BASE,
3721 + .end = SPI0_BASE + SZ_256 - 1,
3722 + .flags = IORESOURCE_MEM,
3723 + }, {
3724 + .start = IRQ_SPI,
3725 + .end = IRQ_SPI,
3726 + .flags = IORESOURCE_IRQ,
3727 + }
3728 +};
3729 +
3730 +
3731 +static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3732 +static struct platform_device bcm2708_spi_device = {
3733 + .name = "bcm2708_spi",
3734 + .id = 0,
3735 + .num_resources = ARRAY_SIZE(bcm2708_spi_resources),
3736 + .resource = bcm2708_spi_resources,
3737 + .dev = {
3738 + .dma_mask = &bcm2708_spi_dmamask,
3739 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)},
3740 +};
3741 +
3742 +#ifdef CONFIG_BCM2708_SPIDEV
3743 +static struct spi_board_info bcm2708_spi_devices[] = {
3744 +#ifdef CONFIG_SPI_SPIDEV
3745 + {
3746 + .modalias = "spidev",
3747 + .max_speed_hz = 500000,
3748 + .bus_num = 0,
3749 + .chip_select = 0,
3750 + .mode = SPI_MODE_0,
3751 + }, {
3752 + .modalias = "spidev",
3753 + .max_speed_hz = 500000,
3754 + .bus_num = 0,
3755 + .chip_select = 1,
3756 + .mode = SPI_MODE_0,
3757 + }
3758 +#endif
3759 +};
3760 +#endif
3761 +
3762 +static struct resource bcm2708_bsc0_resources[] = {
3763 + {
3764 + .start = BSC0_BASE,
3765 + .end = BSC0_BASE + SZ_256 - 1,
3766 + .flags = IORESOURCE_MEM,
3767 + }, {
3768 + .start = INTERRUPT_I2C,
3769 + .end = INTERRUPT_I2C,
3770 + .flags = IORESOURCE_IRQ,
3771 + }
3772 +};
3773 +
3774 +static struct platform_device bcm2708_bsc0_device = {
3775 + .name = "bcm2708_i2c",
3776 + .id = 0,
3777 + .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources),
3778 + .resource = bcm2708_bsc0_resources,
3779 +};
3780 +
3781 +
3782 +static struct resource bcm2708_bsc1_resources[] = {
3783 + {
3784 + .start = BSC1_BASE,
3785 + .end = BSC1_BASE + SZ_256 - 1,
3786 + .flags = IORESOURCE_MEM,
3787 + }, {
3788 + .start = INTERRUPT_I2C,
3789 + .end = INTERRUPT_I2C,
3790 + .flags = IORESOURCE_IRQ,
3791 + }
3792 +};
3793 +
3794 +static struct platform_device bcm2708_bsc1_device = {
3795 + .name = "bcm2708_i2c",
3796 + .id = 1,
3797 + .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources),
3798 + .resource = bcm2708_bsc1_resources,
3799 +};
3800 +
3801 +static struct platform_device bcm2835_hwmon_device = {
3802 + .name = "bcm2835_hwmon",
3803 +};
3804 +
3805 +static struct platform_device bcm2835_thermal_device = {
3806 + .name = "bcm2835_thermal",
3807 +};
3808 +
3809 +#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE)
3810 +static struct resource bcm2708_i2s_resources[] = {
3811 + {
3812 + .start = I2S_BASE,
3813 + .end = I2S_BASE + 0x20,
3814 + .flags = IORESOURCE_MEM,
3815 + },
3816 + {
3817 + .start = PCM_CLOCK_BASE,
3818 + .end = PCM_CLOCK_BASE + 0x02,
3819 + .flags = IORESOURCE_MEM,
3820 + }
3821 +};
3822 +
3823 +static struct platform_device bcm2708_i2s_device = {
3824 + .name = "bcm2708-i2s",
3825 + .id = 0,
3826 + .num_resources = ARRAY_SIZE(bcm2708_i2s_resources),
3827 + .resource = bcm2708_i2s_resources,
3828 +};
3829 +#endif
3830 +
3831 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE)
3832 +static struct platform_device snd_hifiberry_dac_device = {
3833 + .name = "snd-hifiberry-dac",
3834 + .id = 0,
3835 + .num_resources = 0,
3836 +};
3837 +
3838 +static struct platform_device snd_pcm5102a_codec_device = {
3839 + .name = "pcm5102a-codec",
3840 + .id = -1,
3841 + .num_resources = 0,
3842 +};
3843 +#endif
3844 +
3845 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE)
3846 +static struct platform_device snd_rpi_hifiberry_dacplus_device = {
3847 + .name = "snd-rpi-hifiberry-dacplus",
3848 + .id = 0,
3849 + .num_resources = 0,
3850 +};
3851 +
3852 +static struct i2c_board_info __initdata snd_pcm512x_hbdacplus_i2c_devices[] = {
3853 + {
3854 + I2C_BOARD_INFO("pcm5122", 0x4d)
3855 + },
3856 +};
3857 +#endif
3858 +
3859 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE)
3860 +static struct platform_device snd_hifiberry_digi_device = {
3861 + .name = "snd-hifiberry-digi",
3862 + .id = 0,
3863 + .num_resources = 0,
3864 +};
3865 +
3866 +static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = {
3867 + {
3868 + I2C_BOARD_INFO("wm8804", 0x3b)
3869 + },
3870 +};
3871 +
3872 +#endif
3873 +
3874 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE)
3875 +static struct platform_device snd_hifiberry_amp_device = {
3876 + .name = "snd-hifiberry-amp",
3877 + .id = 0,
3878 + .num_resources = 0,
3879 +};
3880 +
3881 +static struct i2c_board_info __initdata snd_tas5713_i2c_devices[] = {
3882 + {
3883 + I2C_BOARD_INFO("tas5713", 0x1b)
3884 + },
3885 +};
3886 +#endif
3887 +
3888 +#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE)
3889 +static struct platform_device snd_rpi_dac_device = {
3890 + .name = "snd-rpi-dac",
3891 + .id = 0,
3892 + .num_resources = 0,
3893 +};
3894 +
3895 +static struct platform_device snd_pcm1794a_codec_device = {
3896 + .name = "pcm1794a-codec",
3897 + .id = -1,
3898 + .num_resources = 0,
3899 +};
3900 +#endif
3901 +
3902 +
3903 +#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE)
3904 +static struct platform_device snd_rpi_iqaudio_dac_device = {
3905 + .name = "snd-rpi-iqaudio-dac",
3906 + .id = 0,
3907 + .num_resources = 0,
3908 +};
3909 +
3910 +// Use the actual device name rather than generic driver name
3911 +static struct i2c_board_info __initdata snd_pcm512x_i2c_devices[] = {
3912 + {
3913 + I2C_BOARD_INFO("pcm5122", 0x4c)
3914 + },
3915 +};
3916 +#endif
3917 +
3918 +int __init bcm_register_device(struct platform_device *pdev)
3919 +{
3920 + int ret;
3921 +
3922 + ret = platform_device_register(pdev);
3923 + if (ret)
3924 + pr_debug("Unable to register platform device '%s': %d\n",
3925 + pdev->name, ret);
3926 +
3927 + return ret;
3928 +}
3929 +
3930 +/*
3931 + * Use these macros for platform and i2c devices that are present in the
3932 + * Device Tree. This way the devices are only added on non-DT systems.
3933 + */
3934 +#define bcm_register_device_dt(pdev) \
3935 + if (!use_dt) bcm_register_device(pdev)
3936 +
3937 +#define i2c_register_board_info_dt(busnum, info, n) \
3938 + if (!use_dt) i2c_register_board_info(busnum, info, n)
3939 +
3940 +int calc_rsts(int partition)
3941 +{
3942 + return PM_PASSWORD |
3943 + ((partition & (1 << 0)) << 0) |
3944 + ((partition & (1 << 1)) << 1) |
3945 + ((partition & (1 << 2)) << 2) |
3946 + ((partition & (1 << 3)) << 3) |
3947 + ((partition & (1 << 4)) << 4) |
3948 + ((partition & (1 << 5)) << 5);
3949 +}
3950 +
3951 +static void bcm2709_restart(enum reboot_mode mode, const char *cmd)
3952 +{
3953 + extern char bcm2708_reboot_mode;
3954 + uint32_t pm_rstc, pm_wdog;
3955 + uint32_t timeout = 10;
3956 + uint32_t pm_rsts = 0;
3957 +
3958 + if(bcm2708_reboot_mode == 'q')
3959 + {
3960 + // NOOBS < 1.3 booting with reboot=q
3961 + pm_rsts = readl(__io_address(PM_RSTS));
3962 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
3963 + }
3964 + else if(bcm2708_reboot_mode == 'p')
3965 + {
3966 + // NOOBS < 1.3 halting
3967 + pm_rsts = readl(__io_address(PM_RSTS));
3968 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
3969 + }
3970 + else
3971 + {
3972 + pm_rsts = calc_rsts(reboot_part);
3973 + }
3974 +
3975 + writel(pm_rsts, __io_address(PM_RSTS));
3976 +
3977 + /* Setup watchdog for reset */
3978 + pm_rstc = readl(__io_address(PM_RSTC));
3979 +
3980 + pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
3981 + pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
3982 +
3983 + writel(pm_wdog, __io_address(PM_WDOG));
3984 + writel(pm_rstc, __io_address(PM_RSTC));
3985 +}
3986 +
3987 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
3988 +static void bcm2709_power_off(void)
3989 +{
3990 + extern char bcm2708_reboot_mode;
3991 + if(bcm2708_reboot_mode == 'q')
3992 + {
3993 + // NOOBS < v1.3
3994 + bcm2709_restart('p', "");
3995 + }
3996 + else
3997 + {
3998 + /* partition 63 is special code for HALT the bootloader knows not to boot*/
3999 + reboot_part = 63;
4000 + /* continue with normal reset mechanism */
4001 + bcm2709_restart(0, "");
4002 + }
4003 +}
4004 +
4005 +#ifdef CONFIG_OF
4006 +static void __init bcm2709_dt_init(void)
4007 +{
4008 + int ret;
4009 +
4010 + ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
4011 + if (ret) {
4012 + pr_err("of_platform_populate failed: %d\n", ret);
4013 + use_dt = 0;
4014 + }
4015 +}
4016 +#else
4017 +static void __init bcm2709_dt_init(void) { }
4018 +#endif /* CONFIG_OF */
4019 +
4020 +void __init bcm2709_init(void)
4021 +{
4022 + int i;
4023 +
4024 +#if defined(CONFIG_BCM_VC_CMA)
4025 + vc_cma_early_init();
4026 +#endif
4027 + printk("bcm2709.uart_clock = %d\n", uart_clock);
4028 + pm_power_off = bcm2709_power_off;
4029 +
4030 + bcm2709_init_clocks();
4031 + if (use_dt)
4032 + bcm2709_dt_init();
4033 +
4034 + bcm_register_device(&bcm2708_dmaman_device);
4035 + bcm_register_device(&bcm2708_vcio_device);
4036 +#ifdef CONFIG_BCM2708_GPIO
4037 + bcm_register_device_dt(&bcm2708_gpio_device);
4038 +#endif
4039 +#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
4040 + w1_gpio_pdata.pin = w1_gpio_pin;
4041 + w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup;
4042 + bcm_register_device_dt(&w1_device);
4043 +#endif
4044 +#ifdef SYSTEM_TIMER
4045 + bcm_register_device(&bcm2708_systemtimer_device);
4046 +#endif
4047 + bcm_register_device(&bcm2708_fb_device);
4048 + bcm_register_device(&bcm2708_usb_device);
4049 + bcm_register_device(&bcm2708_uart1_device);
4050 + bcm_register_device(&bcm2708_powerman_device);
4051 +
4052 +#ifdef CONFIG_MMC_BCM2835
4053 + bcm_register_device(&bcm2835_emmc_device);
4054 +#endif
4055 + bcm2709_init_led();
4056 + for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++)
4057 + bcm_register_device(&bcm2708_alsa_devices[i]);
4058 +
4059 + bcm_register_device(&bcm2835_hwmon_device);
4060 + bcm_register_device(&bcm2835_thermal_device);
4061 +
4062 + bcm_register_device_dt(&bcm2708_spi_device);
4063 + bcm_register_device_dt(&bcm2708_bsc0_device);
4064 + bcm_register_device_dt(&bcm2708_bsc1_device);
4065 +
4066 +#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE)
4067 + bcm_register_device_dt(&bcm2708_i2s_device);
4068 +#endif
4069 +
4070 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE)
4071 + bcm_register_device_dt(&snd_hifiberry_dac_device);
4072 + bcm_register_device_dt(&snd_pcm5102a_codec_device);
4073 +#endif
4074 +
4075 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE)
4076 + bcm_register_device_dt(&snd_rpi_hifiberry_dacplus_device);
4077 + i2c_register_board_info_dt(1, snd_pcm512x_hbdacplus_i2c_devices, ARRAY_SIZE(snd_pcm512x_hbdacplus_i2c_devices));
4078 +#endif
4079 +
4080 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE)
4081 + bcm_register_device_dt(&snd_hifiberry_digi_device);
4082 + i2c_register_board_info_dt(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices));
4083 +#endif
4084 +
4085 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE)
4086 + bcm_register_device_dt(&snd_hifiberry_amp_device);
4087 + i2c_register_board_info_dt(1, snd_tas5713_i2c_devices, ARRAY_SIZE(snd_tas5713_i2c_devices));
4088 +#endif
4089 +
4090 +#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE)
4091 + bcm_register_device_dt(&snd_rpi_dac_device);
4092 + bcm_register_device_dt(&snd_pcm1794a_codec_device);
4093 +#endif
4094 +
4095 +#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE)
4096 + bcm_register_device_dt(&snd_rpi_iqaudio_dac_device);
4097 + i2c_register_board_info_dt(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices));
4098 +#endif
4099 +
4100 +
4101 + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
4102 + struct amba_device *d = amba_devs[i];
4103 + amba_device_register(d, &iomem_resource);
4104 + }
4105 + system_rev = boardrev;
4106 + system_serial_low = serial;
4107 +
4108 +#ifdef CONFIG_BCM2708_SPIDEV
4109 + if (!use_dt)
4110 + spi_register_board_info(bcm2708_spi_devices,
4111 + ARRAY_SIZE(bcm2708_spi_devices));
4112 +#endif
4113 +}
4114 +
4115 +#ifdef SYSTEM_TIMER
4116 +static void timer_set_mode(enum clock_event_mode mode,
4117 + struct clock_event_device *clk)
4118 +{
4119 + switch (mode) {
4120 + case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
4121 + case CLOCK_EVT_MODE_SHUTDOWN:
4122 + break;
4123 + case CLOCK_EVT_MODE_PERIODIC:
4124 +
4125 + case CLOCK_EVT_MODE_UNUSED:
4126 + case CLOCK_EVT_MODE_RESUME:
4127 +
4128 + default:
4129 + printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
4130 + (int)mode);
4131 + break;
4132 + }
4133 +
4134 +}
4135 +
4136 +static int timer_set_next_event(unsigned long cycles,
4137 + struct clock_event_device *unused)
4138 +{
4139 + unsigned long stc;
4140 + do {
4141 + stc = readl(__io_address(ST_BASE + 0x04));
4142 + /* We could take a FIQ here, which may push ST above STC3 */
4143 + writel(stc + cycles, __io_address(ST_BASE + 0x18));
4144 + } while ((signed long) cycles >= 0 &&
4145 + (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
4146 + >= (signed long) cycles);
4147 + return 0;
4148 +}
4149 +
4150 +static struct clock_event_device timer0_clockevent = {
4151 + .name = "timer0",
4152 + .shift = 32,
4153 + .features = CLOCK_EVT_FEAT_ONESHOT,
4154 + .set_mode = timer_set_mode,
4155 + .set_next_event = timer_set_next_event,
4156 +};
4157 +
4158 +/*
4159 + * IRQ handler for the timer
4160 + */
4161 +static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id)
4162 +{
4163 + struct clock_event_device *evt = &timer0_clockevent;
4164 +
4165 + writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
4166 +
4167 + evt->event_handler(evt);
4168 +
4169 + return IRQ_HANDLED;
4170 +}
4171 +
4172 +static struct irqaction bcm2709_timer_irq = {
4173 + .name = "BCM2709 Timer Tick",
4174 + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
4175 + .handler = bcm2709_timer_interrupt,
4176 +};
4177 +
4178 +/*
4179 + * Set up timer interrupt, and return the current time in seconds.
4180 + */
4181 +
4182 +static struct delay_timer bcm2709_delay_timer = {
4183 + .read_current_timer = bcm2709_read_current_timer,
4184 + .freq = STC_FREQ_HZ,
4185 +};
4186 +
4187 +static void __init bcm2709_timer_init(void)
4188 +{
4189 + /* init high res timer */
4190 + bcm2709_clocksource_init();
4191 +
4192 + /*
4193 + * Make irqs happen for the system timer
4194 + */
4195 + setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
4196 +
4197 + sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ);
4198 +
4199 + timer0_clockevent.mult =
4200 + div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
4201 + timer0_clockevent.max_delta_ns =
4202 + clockevent_delta2ns(0xffffffff, &timer0_clockevent);
4203 + timer0_clockevent.min_delta_ns =
4204 + clockevent_delta2ns(0xf, &timer0_clockevent);
4205 +
4206 + timer0_clockevent.cpumask = cpumask_of(0);
4207 + clockevents_register_device(&timer0_clockevent);
4208 +
4209 + register_current_timer_delay(&bcm2708_delay_timer);
4210 +}
4211 +
4212 +#else
4213 +
4214 +static void __init bcm2709_timer_init(void)
4215 +{
4216 + extern void dc4_arch_timer_init(void);
4217 + // timer control
4218 + writel(0, __io_address(ARM_LOCAL_CONTROL));
4219 + // timer pre_scaler
4220 + writel(0x80000000, __io_address(ARM_LOCAL_PRESCALER)); // 19.2MHz
4221 + //writel(0x06AAAAAB, __io_address(ARM_LOCAL_PRESCALER)); // 1MHz
4222 +
4223 + if (use_dt)
4224 + {
4225 + of_clk_init(NULL);
4226 + clocksource_of_init();
4227 + }
4228 + else
4229 + dc4_arch_timer_init();
4230 +}
4231 +
4232 +#endif
4233 +
4234 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
4235 +#include <linux/leds.h>
4236 +
4237 +static struct gpio_led bcm2709_leds[] = {
4238 + [0] = {
4239 + .gpio = 16,
4240 + .name = "led0",
4241 + .default_trigger = "mmc0",
4242 + .active_low = 1,
4243 + },
4244 +};
4245 +
4246 +static struct gpio_led_platform_data bcm2709_led_pdata = {
4247 + .num_leds = ARRAY_SIZE(bcm2709_leds),
4248 + .leds = bcm2709_leds,
4249 +};
4250 +
4251 +static struct platform_device bcm2709_led_device = {
4252 + .name = "leds-gpio",
4253 + .id = -1,
4254 + .dev = {
4255 + .platform_data = &bcm2709_led_pdata,
4256 + },
4257 +};
4258 +
4259 +static void __init bcm2709_init_led(void)
4260 +{
4261 + bcm2709_leds[0].gpio = disk_led_gpio;
4262 + bcm2709_leds[0].active_low = disk_led_active_low;
4263 + bcm_register_device_dt(&bcm2709_led_device);
4264 +}
4265 +#else
4266 +static inline void bcm2709_init_led(void)
4267 +{
4268 +}
4269 +#endif
4270 +
4271 +void __init bcm2709_init_early(void)
4272 +{
4273 + /*
4274 + * Some devices allocate their coherent buffers from atomic
4275 + * context. Increase size of atomic coherent pool to make sure such
4276 + * the allocations won't fail.
4277 + */
4278 + init_dma_coherent_pool_size(SZ_4M);
4279 +
4280 +#ifdef CONFIG_OF
4281 + if (of_allnodes)
4282 + use_dt = 1;
4283 +#endif
4284 +}
4285 +
4286 +static void __init board_reserve(void)
4287 +{
4288 +#if defined(CONFIG_BCM_VC_CMA)
4289 + vc_cma_reserve();
4290 +#endif
4291 +}
4292 +
4293 +
4294 +#include <linux/smp.h>
4295 +
4296 +#include <mach/hardware.h>
4297 +#include <asm/cacheflush.h>
4298 +#include <asm/smp_plat.h>
4299 +int dc4=0;
4300 +//void dc4_log(unsigned x) { if (dc4) writel((x), __io_address(ST_BASE+10 + raw_smp_processor_id()*4)); }
4301 +void dc4_log_dead(unsigned x) { if (dc4) writel((readl(__io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)) & 0xffff) | ((x)<<16), __io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)); }
4302 +
4303 +static void bcm2835_send_doorbell(const struct cpumask *mask, unsigned int irq)
4304 +{
4305 + int cpu;
4306 + /*
4307 + * Ensure that stores to Normal memory are visible to the
4308 + * other CPUs before issuing the IPI.
4309 + */
4310 + dsb();
4311 +
4312 + /* Convert our logical CPU mask into a physical one. */
4313 + for_each_cpu(cpu, mask)
4314 + {
4315 + /* submit softirq */
4316 + writel(1<<irq, __io_address(ARM_LOCAL_MAILBOX0_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)));
4317 + }
4318 +}
4319 +
4320 +void __init bcm2709_smp_init_cpus(void)
4321 +{
4322 + void secondary_startup(void);
4323 + unsigned int i, ncores;
4324 +
4325 + ncores = 4; // xxx scu_get_core_count(NULL);
4326 + printk("[%s] enter (%x->%x)\n", __FUNCTION__, (unsigned)virt_to_phys((void *)secondary_startup), (unsigned)__io_address(ST_BASE + 0x10));
4327 + printk("[%s] ncores=%d\n", __FUNCTION__, ncores);
4328 +
4329 + for (i = 0; i < ncores; i++) {
4330 + set_cpu_possible(i, true);
4331 + /* enable IRQ (not FIQ) */
4332 + writel(0x1, __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 0x4 * i));
4333 + //writel(0xf, __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 0x4 * i));
4334 + }
4335 + set_smp_cross_call(bcm2835_send_doorbell);
4336 +}
4337 +
4338 +/*
4339 + * for arch/arm/kernel/smp.c:smp_prepare_cpus(unsigned int max_cpus)
4340 + */
4341 +void __init bcm2709_smp_prepare_cpus(unsigned int max_cpus)
4342 +{
4343 + //void __iomem *scu_base;
4344 +
4345 + printk("[%s] enter\n", __FUNCTION__);
4346 + //scu_base = scu_base_addr();
4347 + //scu_enable(scu_base);
4348 +}
4349 +
4350 +/*
4351 + * for linux/arch/arm/kernel/smp.c:secondary_start_kernel(void)
4352 + */
4353 +void __cpuinit bcm2709_secondary_init(unsigned int cpu)
4354 +{
4355 + printk("[%s] enter cpu:%d\n", __FUNCTION__, cpu);
4356 + //gic_secondary_init(0);
4357 +}
4358 +
4359 +/*
4360 + * for linux/arch/arm/kernel/smp.c:__cpu_up(..)
4361 + */
4362 +int __cpuinit bcm2709_boot_secondary(unsigned int cpu, struct task_struct *idle)
4363 +{
4364 + void secondary_startup(void);
4365 + void *mbox_set = __io_address(ARM_LOCAL_MAILBOX3_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
4366 + void *mbox_clr = __io_address(ARM_LOCAL_MAILBOX3_CLR0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
4367 + unsigned secondary_boot = (unsigned)virt_to_phys((void *)secondary_startup);
4368 + int timeout=20;
4369 + unsigned t = -1;
4370 + //printk("[%s] enter cpu:%d (%x->%p) %x\n", __FUNCTION__, cpu, secondary_boot, wake, readl(wake));
4371 +
4372 + dsb();
4373 + BUG_ON(readl(mbox_clr) != 0);
4374 + writel(secondary_boot, mbox_set);
4375 +
4376 + while (--timeout > 0) {
4377 + t = readl(mbox_clr);
4378 + if (t == 0) break;
4379 + cpu_relax();
4380 + }
4381 + if (timeout==0)
4382 + printk("[%s] cpu:%d failed to start (%x)\n", __FUNCTION__, cpu, t);
4383 + else
4384 + printk("[%s] cpu:%d started (%x) %d\n", __FUNCTION__, cpu, t, timeout);
4385 +
4386 + return 0;
4387 +}
4388 +
4389 +
4390 +struct smp_operations bcm2709_smp_ops __initdata = {
4391 + .smp_init_cpus = bcm2709_smp_init_cpus,
4392 + .smp_prepare_cpus = bcm2709_smp_prepare_cpus,
4393 + .smp_secondary_init = bcm2709_secondary_init,
4394 + .smp_boot_secondary = bcm2709_boot_secondary,
4395 +};
4396 +
4397 +static const char * const bcm2709_compat[] = {
4398 + "brcm,bcm2709",
4399 + "brcm,bcm2708", /* Could use bcm2708 in a pinch */
4400 + NULL
4401 +};
4402 +
4403 +MACHINE_START(BCM2709, "BCM2709")
4404 + /* Maintainer: Broadcom Europe Ltd. */
4405 + .smp = smp_ops(bcm2709_smp_ops),
4406 + .map_io = bcm2709_map_io,
4407 + .init_irq = bcm2709_init_irq,
4408 + .init_time = bcm2709_timer_init,
4409 + .init_machine = bcm2709_init,
4410 + .init_early = bcm2709_init_early,
4411 + .reserve = board_reserve,
4412 + .restart = bcm2709_restart,
4413 + .dt_compat = bcm2709_compat,
4414 +MACHINE_END
4415 +
4416 +module_param(boardrev, uint, 0644);
4417 +module_param(serial, uint, 0644);
4418 +module_param(uart_clock, uint, 0644);
4419 +module_param(disk_led_gpio, uint, 0644);
4420 +module_param(disk_led_active_low, uint, 0644);
4421 +module_param(reboot_part, uint, 0644);
4422 +module_param(w1_gpio_pin, uint, 0644);
4423 +module_param(w1_gpio_pullup, uint, 0644);
4424 --- /dev/null
4425 +++ b/arch/arm/mach-bcm2709/bcm2709.h
4426 @@ -0,0 +1,49 @@
4427 +/*
4428 + * linux/arch/arm/mach-bcm2708/bcm2708.h
4429 + *
4430 + * BCM2708 machine support header
4431 + *
4432 + * Copyright (C) 2010 Broadcom
4433 + *
4434 + * This program is free software; you can redistribute it and/or modify
4435 + * it under the terms of the GNU General Public License as published by
4436 + * the Free Software Foundation; either version 2 of the License, or
4437 + * (at your option) any later version.
4438 + *
4439 + * This program is distributed in the hope that it will be useful,
4440 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4441 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4442 + * GNU General Public License for more details.
4443 + *
4444 + * You should have received a copy of the GNU General Public License
4445 + * along with this program; if not, write to the Free Software
4446 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4447 + */
4448 +
4449 +#ifndef __BCM2708_BCM2708_H
4450 +#define __BCM2708_BCM2708_H
4451 +
4452 +#include <linux/amba/bus.h>
4453 +
4454 +extern void __init bcm2708_init(void);
4455 +extern void __init bcm2708_init_irq(void);
4456 +extern void __init bcm2708_map_io(void);
4457 +extern struct sys_timer bcm2708_timer;
4458 +extern unsigned int mmc_status(struct device *dev);
4459 +
4460 +#define AMBA_DEVICE(name, busid, base, plat) \
4461 +static struct amba_device name##_device = { \
4462 + .dev = { \
4463 + .coherent_dma_mask = ~0, \
4464 + .init_name = busid, \
4465 + .platform_data = plat, \
4466 + }, \
4467 + .res = { \
4468 + .start = base##_BASE, \
4469 + .end = (base##_BASE) + SZ_4K - 1,\
4470 + .flags = IORESOURCE_MEM, \
4471 + }, \
4472 + .irq = base##_IRQ, \
4473 +}
4474 +
4475 +#endif
4476 --- /dev/null
4477 +++ b/arch/arm/mach-bcm2709/clock.c
4478 @@ -0,0 +1,61 @@
4479 +/*
4480 + * linux/arch/arm/mach-bcm2708/clock.c
4481 + *
4482 + * Copyright (C) 2010 Broadcom
4483 + *
4484 + * This program is free software; you can redistribute it and/or modify
4485 + * it under the terms of the GNU General Public License as published by
4486 + * the Free Software Foundation; either version 2 of the License, or
4487 + * (at your option) any later version.
4488 + *
4489 + * This program is distributed in the hope that it will be useful,
4490 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4491 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4492 + * GNU General Public License for more details.
4493 + *
4494 + * You should have received a copy of the GNU General Public License
4495 + * along with this program; if not, write to the Free Software
4496 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4497 + */
4498 +#include <linux/module.h>
4499 +#include <linux/kernel.h>
4500 +#include <linux/device.h>
4501 +#include <linux/list.h>
4502 +#include <linux/errno.h>
4503 +#include <linux/err.h>
4504 +#include <linux/string.h>
4505 +#include <linux/clk.h>
4506 +#include <linux/mutex.h>
4507 +
4508 +#include <asm/clkdev.h>
4509 +
4510 +#include "clock.h"
4511 +
4512 +int clk_enable(struct clk *clk)
4513 +{
4514 + return 0;
4515 +}
4516 +EXPORT_SYMBOL(clk_enable);
4517 +
4518 +void clk_disable(struct clk *clk)
4519 +{
4520 +}
4521 +EXPORT_SYMBOL(clk_disable);
4522 +
4523 +unsigned long clk_get_rate(struct clk *clk)
4524 +{
4525 + return clk->rate;
4526 +}
4527 +EXPORT_SYMBOL(clk_get_rate);
4528 +
4529 +long clk_round_rate(struct clk *clk, unsigned long rate)
4530 +{
4531 + return clk->rate;
4532 +}
4533 +EXPORT_SYMBOL(clk_round_rate);
4534 +
4535 +int clk_set_rate(struct clk *clk, unsigned long rate)
4536 +{
4537 + return -EIO;
4538 +}
4539 +EXPORT_SYMBOL(clk_set_rate);
4540 --- /dev/null
4541 +++ b/arch/arm/mach-bcm2709/clock.h
4542 @@ -0,0 +1,24 @@
4543 +/*
4544 + * linux/arch/arm/mach-bcm2708/clock.h
4545 + *
4546 + * Copyright (C) 2010 Broadcom
4547 + *
4548 + * This program is free software; you can redistribute it and/or modify
4549 + * it under the terms of the GNU General Public License as published by
4550 + * the Free Software Foundation; either version 2 of the License, or
4551 + * (at your option) any later version.
4552 + *
4553 + * This program is distributed in the hope that it will be useful,
4554 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4555 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4556 + * GNU General Public License for more details.
4557 + *
4558 + * You should have received a copy of the GNU General Public License
4559 + * along with this program; if not, write to the Free Software
4560 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4561 + */
4562 +struct module;
4563 +
4564 +struct clk {
4565 + unsigned long rate;
4566 +};
4567 --- /dev/null
4568 +++ b/arch/arm/mach-bcm2709/delay.S
4569 @@ -0,0 +1,21 @@
4570 +/*
4571 + * linux/arch/arm/lib/delay.S
4572 + *
4573 + * Copyright (C) 1995, 1996 Russell King
4574 + *
4575 + * This program is free software; you can redistribute it and/or modify
4576 + * it under the terms of the GNU General Public License version 2 as
4577 + * published by the Free Software Foundation.
4578 + */
4579 +#include <linux/linkage.h>
4580 +#include <asm/assembler.h>
4581 +#include <asm/param.h>
4582 +
4583 + .text
4584 +.align 3 @ 8 byte alignment seems to be needed to avoid fetching stalls
4585 +@ Delay routine
4586 +ENTRY(bcm2708_delay)
4587 + subs r0, r0, #1
4588 + bhi bcm2708_delay
4589 + mov pc, lr
4590 +ENDPROC(bcm2708_delay)
4591 --- /dev/null
4592 +++ b/arch/arm/mach-bcm2709/dma.c
4593 @@ -0,0 +1,409 @@
4594 +/*
4595 + * linux/arch/arm/mach-bcm2708/dma.c
4596 + *
4597 + * Copyright (C) 2010 Broadcom
4598 + *
4599 + * This program is free software; you can redistribute it and/or modify
4600 + * it under the terms of the GNU General Public License version 2 as
4601 + * published by the Free Software Foundation.
4602 + */
4603 +
4604 +#include <linux/slab.h>
4605 +#include <linux/device.h>
4606 +#include <linux/platform_device.h>
4607 +#include <linux/module.h>
4608 +#include <linux/scatterlist.h>
4609 +
4610 +#include <mach/dma.h>
4611 +#include <mach/irqs.h>
4612 +
4613 +/*****************************************************************************\
4614 + * *
4615 + * Configuration *
4616 + * *
4617 +\*****************************************************************************/
4618 +
4619 +#define CACHE_LINE_MASK 31
4620 +#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
4621 +#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */
4622 +
4623 +/* valid only for channels 0 - 14, 15 has its own base address */
4624 +#define BCM2708_DMA_CHAN(n) ((n)<<8) /* base address */
4625 +#define BCM2708_DMA_CHANIO(dma_base, n) \
4626 + ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
4627 +
4628 +
4629 +/*****************************************************************************\
4630 + * *
4631 + * DMA Auxilliary Functions *
4632 + * *
4633 +\*****************************************************************************/
4634 +
4635 +/* A DMA buffer on an arbitrary boundary may separate a cache line into a
4636 + section inside the DMA buffer and another section outside it.
4637 + Even if we flush DMA buffers from the cache there is always the chance that
4638 + during a DMA someone will access the part of a cache line that is outside
4639 + the DMA buffer - which will then bring in unwelcome data.
4640 + Without being able to dictate our own buffer pools we must insist that
4641 + DMA buffers consist of a whole number of cache lines.
4642 +*/
4643 +
4644 +extern int
4645 +bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
4646 +{
4647 + int i;
4648 +
4649 + for (i = 0; i < sg_len; i++) {
4650 + if (sg_ptr[i].offset & CACHE_LINE_MASK ||
4651 + sg_ptr[i].length & CACHE_LINE_MASK)
4652 + return 0;
4653 + }
4654 +
4655 + return 1;
4656 +}
4657 +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
4658 +
4659 +extern void
4660 +bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
4661 +{
4662 + dsb(); /* ARM data synchronization (push) operation */
4663 +
4664 + writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
4665 + writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
4666 +}
4667 +
4668 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
4669 +{
4670 + dsb();
4671 +
4672 + /* ugly busy wait only option for now */
4673 + while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
4674 + cpu_relax();
4675 +}
4676 +
4677 +EXPORT_SYMBOL_GPL(bcm_dma_start);
4678 +
4679 +extern bool bcm_dma_is_busy(void __iomem *dma_chan_base)
4680 +{
4681 + dsb();
4682 +
4683 + return readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE;
4684 +}
4685 +EXPORT_SYMBOL_GPL(bcm_dma_is_busy);
4686 +
4687 +/* Complete an ongoing DMA (assuming its results are to be ignored)
4688 + Does nothing if there is no DMA in progress.
4689 + This routine waits for the current AXI transfer to complete before
4690 + terminating the current DMA. If the current transfer is hung on a DREQ used
4691 + by an uncooperative peripheral the AXI transfer may never complete. In this
4692 + case the routine times out and return a non-zero error code.
4693 + Use of this routine doesn't guarantee that the ongoing or aborted DMA
4694 + does not produce an interrupt.
4695 +*/
4696 +extern int
4697 +bcm_dma_abort(void __iomem *dma_chan_base)
4698 +{
4699 + unsigned long int cs;
4700 + int rc = 0;
4701 +
4702 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
4703 +
4704 + if (BCM2708_DMA_ACTIVE & cs) {
4705 + long int timeout = 10000;
4706 +
4707 + /* write 0 to the active bit - pause the DMA */
4708 + writel(0, dma_chan_base + BCM2708_DMA_CS);
4709 +
4710 + /* wait for any current AXI transfer to complete */
4711 + while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
4712 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
4713 +
4714 + if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
4715 + /* we'll un-pause when we set of our next DMA */
4716 + rc = -ETIMEDOUT;
4717 +
4718 + } else if (BCM2708_DMA_ACTIVE & cs) {
4719 + /* terminate the control block chain */
4720 + writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
4721 +
4722 + /* abort the whole DMA */
4723 + writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
4724 + dma_chan_base + BCM2708_DMA_CS);
4725 + }
4726 + }
4727 +
4728 + return rc;
4729 +}
4730 +EXPORT_SYMBOL_GPL(bcm_dma_abort);
4731 +
4732 +
4733 +/***************************************************************************** \
4734 + * *
4735 + * DMA Manager Device Methods *
4736 + * *
4737 +\*****************************************************************************/
4738 +
4739 +struct vc_dmaman {
4740 + void __iomem *dma_base;
4741 + u32 chan_available; /* bitmap of available channels */
4742 + u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
4743 +};
4744 +
4745 +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
4746 + u32 chans_available)
4747 +{
4748 + dmaman->dma_base = dma_base;
4749 + dmaman->chan_available = chans_available;
4750 + dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */
4751 + dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* chan 0 */
4752 + dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe; /* chans 1 to 7 */
4753 + dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00; /* chans 8 to 14 */
4754 +}
4755 +
4756 +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
4757 + unsigned preferred_feature_set)
4758 +{
4759 + u32 chans;
4760 + int feature;
4761 +
4762 + chans = dmaman->chan_available;
4763 + for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
4764 + /* select the subset of available channels with the desired
4765 + feature so long as some of the candidate channels have that
4766 + feature */
4767 + if ((preferred_feature_set & (1 << feature)) &&
4768 + (chans & dmaman->has_feature[feature]))
4769 + chans &= dmaman->has_feature[feature];
4770 +
4771 + if (chans) {
4772 + int chan = 0;
4773 + /* return the ordinal of the first channel in the bitmap */
4774 + while (chans != 0 && (chans & 1) == 0) {
4775 + chans >>= 1;
4776 + chan++;
4777 + }
4778 + /* claim the channel */
4779 + dmaman->chan_available &= ~(1 << chan);
4780 + return chan;
4781 + } else
4782 + return -ENOMEM;
4783 +}
4784 +
4785 +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
4786 +{
4787 + if (chan < 0)
4788 + return -EINVAL;
4789 + else if ((1 << chan) & dmaman->chan_available)
4790 + return -EIDRM;
4791 + else {
4792 + dmaman->chan_available |= (1 << chan);
4793 + return 0;
4794 + }
4795 +}
4796 +
4797 +/*****************************************************************************\
4798 + * *
4799 + * DMA IRQs *
4800 + * *
4801 +\*****************************************************************************/
4802 +
4803 +static unsigned char bcm_dma_irqs[] = {
4804 + IRQ_DMA0,
4805 + IRQ_DMA1,
4806 + IRQ_DMA2,
4807 + IRQ_DMA3,
4808 + IRQ_DMA4,
4809 + IRQ_DMA5,
4810 + IRQ_DMA6,
4811 + IRQ_DMA7,
4812 + IRQ_DMA8,
4813 + IRQ_DMA9,
4814 + IRQ_DMA10,
4815 + IRQ_DMA11,
4816 + IRQ_DMA12
4817 +};
4818 +
4819 +
4820 +/***************************************************************************** \
4821 + * *
4822 + * DMA Manager Monitor *
4823 + * *
4824 +\*****************************************************************************/
4825 +
4826 +static struct device *dmaman_dev; /* we assume there's only one! */
4827 +
4828 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
4829 + void __iomem **out_dma_base, int *out_dma_irq)
4830 +{
4831 + if (!dmaman_dev)
4832 + return -ENODEV;
4833 + else {
4834 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
4835 + int rc;
4836 +
4837 + device_lock(dmaman_dev);
4838 + rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
4839 + if (rc >= 0) {
4840 + *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
4841 + rc);
4842 + *out_dma_irq = bcm_dma_irqs[rc];
4843 + }
4844 + device_unlock(dmaman_dev);
4845 +
4846 + return rc;
4847 + }
4848 +}
4849 +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
4850 +
4851 +extern int bcm_dma_chan_free(int channel)
4852 +{
4853 + if (dmaman_dev) {
4854 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
4855 + int rc;
4856 +
4857 + device_lock(dmaman_dev);
4858 + rc = vc_dmaman_chan_free(dmaman, channel);
4859 + device_unlock(dmaman_dev);
4860 +
4861 + return rc;
4862 + } else
4863 + return -ENODEV;
4864 +}
4865 +EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
4866 +
4867 +static int dev_dmaman_register(const char *dev_name, struct device *dev)
4868 +{
4869 + int rc = dmaman_dev ? -EINVAL : 0;
4870 + dmaman_dev = dev;
4871 + return rc;
4872 +}
4873 +
4874 +static void dev_dmaman_deregister(const char *dev_name, struct device *dev)
4875 +{
4876 + dmaman_dev = NULL;
4877 +}
4878 +
4879 +/*****************************************************************************\
4880 + * *
4881 + * DMA Device *
4882 + * *
4883 +\*****************************************************************************/
4884 +
4885 +static int dmachans = -1; /* module parameter */
4886 +
4887 +static int bcm_dmaman_probe(struct platform_device *pdev)
4888 +{
4889 + int ret = 0;
4890 + struct vc_dmaman *dmaman;
4891 + struct resource *dma_res = NULL;
4892 + void __iomem *dma_base = NULL;
4893 + int have_dma_region = 0;
4894 +
4895 + dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL);
4896 + if (NULL == dmaman) {
4897 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
4898 + "DMA management memory\n");
4899 + ret = -ENOMEM;
4900 + } else {
4901 +
4902 + dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4903 + if (dma_res == NULL) {
4904 + printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
4905 + "resource\n");
4906 + ret = -ENODEV;
4907 + } else if (!request_mem_region(dma_res->start,
4908 + resource_size(dma_res),
4909 + DRIVER_NAME)) {
4910 + dev_err(&pdev->dev, "cannot obtain DMA region\n");
4911 + ret = -EBUSY;
4912 + } else {
4913 + have_dma_region = 1;
4914 + dma_base = ioremap(dma_res->start,
4915 + resource_size(dma_res));
4916 + if (!dma_base) {
4917 + dev_err(&pdev->dev, "cannot map DMA region\n");
4918 + ret = -ENOMEM;
4919 + } else {
4920 + /* use module parameter if one was provided */
4921 + if (dmachans > 0)
4922 + vc_dmaman_init(dmaman, dma_base,
4923 + dmachans);
4924 + else
4925 + vc_dmaman_init(dmaman, dma_base,
4926 + DEFAULT_DMACHAN_BITMAP);
4927 +
4928 + platform_set_drvdata(pdev, dmaman);
4929 + dev_dmaman_register(DRIVER_NAME, &pdev->dev);
4930 +
4931 + printk(KERN_INFO DRIVER_NAME ": DMA manager "
4932 + "at %p\n", dma_base);
4933 + }
4934 + }
4935 + }
4936 + if (ret != 0) {
4937 + if (dma_base)
4938 + iounmap(dma_base);
4939 + if (dma_res && have_dma_region)
4940 + release_mem_region(dma_res->start,
4941 + resource_size(dma_res));
4942 + if (dmaman)
4943 + kfree(dmaman);
4944 + }
4945 + return ret;
4946 +}
4947 +
4948 +static int bcm_dmaman_remove(struct platform_device *pdev)
4949 +{
4950 + struct vc_dmaman *dmaman = platform_get_drvdata(pdev);
4951 +
4952 + platform_set_drvdata(pdev, NULL);
4953 + dev_dmaman_deregister(DRIVER_NAME, &pdev->dev);
4954 + kfree(dmaman);
4955 +
4956 + return 0;
4957 +}
4958 +
4959 +static struct platform_driver bcm_dmaman_driver = {
4960 + .probe = bcm_dmaman_probe,
4961 + .remove = bcm_dmaman_remove,
4962 +
4963 + .driver = {
4964 + .name = DRIVER_NAME,
4965 + .owner = THIS_MODULE,
4966 + },
4967 +};
4968 +
4969 +/*****************************************************************************\
4970 + * *
4971 + * Driver init/exit *
4972 + * *
4973 +\*****************************************************************************/
4974 +
4975 +static int __init bcm_dmaman_drv_init(void)
4976 +{
4977 + int ret;
4978 +
4979 + ret = platform_driver_register(&bcm_dmaman_driver);
4980 + if (ret != 0) {
4981 + printk(KERN_ERR DRIVER_NAME ": failed to register "
4982 + "on platform\n");
4983 + }
4984 +
4985 + return ret;
4986 +}
4987 +
4988 +static void __exit bcm_dmaman_drv_exit(void)
4989 +{
4990 + platform_driver_unregister(&bcm_dmaman_driver);
4991 +}
4992 +
4993 +module_init(bcm_dmaman_drv_init);
4994 +module_exit(bcm_dmaman_drv_exit);
4995 +
4996 +module_param(dmachans, int, 0644);
4997 +
4998 +MODULE_AUTHOR("Gray Girling <grayg@broadcom.com>");
4999 +MODULE_DESCRIPTION("DMA channel manager driver");
5000 +MODULE_LICENSE("GPL");
5001 +
5002 +MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM");
5003 --- /dev/null
5004 +++ b/arch/arm/mach-bcm2709/dmaer.c
5005 @@ -0,0 +1,886 @@
5006 +#include <linux/init.h>
5007 +#include <linux/sched.h>
5008 +#include <linux/module.h>
5009 +#include <linux/types.h>
5010 +#include <linux/kdev_t.h>
5011 +#include <linux/fs.h>
5012 +#include <linux/cdev.h>
5013 +#include <linux/mm.h>
5014 +#include <linux/slab.h>
5015 +#include <linux/pagemap.h>
5016 +#include <linux/device.h>
5017 +#include <linux/jiffies.h>
5018 +#include <linux/timex.h>
5019 +#include <linux/dma-mapping.h>
5020 +
5021 +#include <asm/uaccess.h>
5022 +#include <asm/atomic.h>
5023 +#include <asm/cacheflush.h>
5024 +#include <asm/io.h>
5025 +
5026 +#include <mach/dma.h>
5027 +#include <mach/vc_support.h>
5028 +
5029 +#ifdef ECLIPSE_IGNORE
5030 +
5031 +#define __user
5032 +#define __init
5033 +#define __exit
5034 +#define __iomem
5035 +#define KERN_DEBUG
5036 +#define KERN_ERR
5037 +#define KERN_WARNING
5038 +#define KERN_INFO
5039 +#define _IOWR(a, b, c) b
5040 +#define _IOW(a, b, c) b
5041 +#define _IO(a, b) b
5042 +
5043 +#endif
5044 +
5045 +//#define inline
5046 +
5047 +#define PRINTK(args...) printk(args)
5048 +//#define PRINTK_VERBOSE(args...) printk(args)
5049 +//#define PRINTK(args...)
5050 +#define PRINTK_VERBOSE(args...)
5051 +
5052 +/***** TYPES ****/
5053 +#define PAGES_PER_LIST 500
5054 +struct PageList
5055 +{
5056 + struct page *m_pPages[PAGES_PER_LIST];
5057 + unsigned int m_used;
5058 + struct PageList *m_pNext;
5059 +};
5060 +
5061 +struct VmaPageList
5062 +{
5063 + //each vma has a linked list of pages associated with it
5064 + struct PageList *m_pPageHead;
5065 + struct PageList *m_pPageTail;
5066 + unsigned int m_refCount;
5067 +};
5068 +
5069 +struct DmaControlBlock
5070 +{
5071 + unsigned int m_transferInfo;
5072 + void __user *m_pSourceAddr;
5073 + void __user *m_pDestAddr;
5074 + unsigned int m_xferLen;
5075 + unsigned int m_tdStride;
5076 + struct DmaControlBlock *m_pNext;
5077 + unsigned int m_blank1, m_blank2;
5078 +};
5079 +
5080 +/***** DEFINES ******/
5081 +//magic number defining the module
5082 +#define DMA_MAGIC 0xdd
5083 +
5084 +//do user virtual to physical translation of the CB chain
5085 +#define DMA_PREPARE _IOWR(DMA_MAGIC, 0, struct DmaControlBlock *)
5086 +
5087 +//kick the pre-prepared CB chain
5088 +#define DMA_KICK _IOW(DMA_MAGIC, 1, struct DmaControlBlock *)
5089 +
5090 +//prepare it, kick it, wait for it
5091 +#define DMA_PREPARE_KICK_WAIT _IOWR(DMA_MAGIC, 2, struct DmaControlBlock *)
5092 +
5093 +//prepare it, kick it, don't wait for it
5094 +#define DMA_PREPARE_KICK _IOWR(DMA_MAGIC, 3, struct DmaControlBlock *)
5095 +
5096 +//not currently implemented
5097 +#define DMA_WAIT_ONE _IO(DMA_MAGIC, 4, struct DmaControlBlock *)
5098 +
5099 +//wait on all kicked CB chains
5100 +#define DMA_WAIT_ALL _IO(DMA_MAGIC, 5)
5101 +
5102 +//in order to discover the largest AXI burst that should be programmed into the transfer params
5103 +#define DMA_MAX_BURST _IO(DMA_MAGIC, 6)
5104 +
5105 +//set the address range through which the user address is assumed to already by a physical address
5106 +#define DMA_SET_MIN_PHYS _IOW(DMA_MAGIC, 7, unsigned long)
5107 +#define DMA_SET_MAX_PHYS _IOW(DMA_MAGIC, 8, unsigned long)
5108 +#define DMA_SET_PHYS_OFFSET _IOW(DMA_MAGIC, 9, unsigned long)
5109 +
5110 +//used to define the size for the CMA-based allocation *in pages*, can only be done once once the file is opened
5111 +#define DMA_CMA_SET_SIZE _IOW(DMA_MAGIC, 10, unsigned long)
5112 +
5113 +//used to get the version of the module, to test for a capability
5114 +#define DMA_GET_VERSION _IO(DMA_MAGIC, 99)
5115 +
5116 +#define VERSION_NUMBER 1
5117 +
5118 +#define VIRT_TO_BUS_CACHE_SIZE 8
5119 +
5120 +/***** FILE OPS *****/
5121 +static int Open(struct inode *pInode, struct file *pFile);
5122 +static int Release(struct inode *pInode, struct file *pFile);
5123 +static long Ioctl(struct file *pFile, unsigned int cmd, unsigned long arg);
5124 +static ssize_t Read(struct file *pFile, char __user *pUser, size_t count, loff_t *offp);
5125 +static int Mmap(struct file *pFile, struct vm_area_struct *pVma);
5126 +
5127 +/***** VMA OPS ****/
5128 +static void VmaOpen4k(struct vm_area_struct *pVma);
5129 +static void VmaClose4k(struct vm_area_struct *pVma);
5130 +static int VmaFault4k(struct vm_area_struct *pVma, struct vm_fault *pVmf);
5131 +
5132 +/**** DMA PROTOTYPES */
5133 +static struct DmaControlBlock __user *DmaPrepare(struct DmaControlBlock __user *pUserCB, int *pError);
5134 +static int DmaKick(struct DmaControlBlock __user *pUserCB);
5135 +static void DmaWaitAll(void);
5136 +
5137 +/**** GENERIC ****/
5138 +static int __init dmaer_init(void);
5139 +static void __exit dmaer_exit(void);
5140 +
5141 +/*** OPS ***/
5142 +static struct vm_operations_struct g_vmOps4k = {
5143 + .open = VmaOpen4k,
5144 + .close = VmaClose4k,
5145 + .fault = VmaFault4k,
5146 +};
5147 +
5148 +static struct file_operations g_fOps = {
5149 + .owner = THIS_MODULE,
5150 + .llseek = 0,
5151 + .read = Read,
5152 + .write = 0,
5153 + .unlocked_ioctl = Ioctl,
5154 + .open = Open,
5155 + .release = Release,
5156 + .mmap = Mmap,
5157 +};
5158 +
5159 +/***** GLOBALS ******/
5160 +static dev_t g_majorMinor;
5161 +
5162 +//tracking usage of the two files
5163 +static atomic_t g_oneLock4k = ATOMIC_INIT(1);
5164 +
5165 +//device operations
5166 +static struct cdev g_cDev;
5167 +static int g_trackedPages = 0;
5168 +
5169 +//dma control
5170 +static unsigned int *g_pDmaChanBase;
5171 +static int g_dmaIrq;
5172 +static int g_dmaChan;
5173 +
5174 +//cma allocation
5175 +static int g_cmaHandle;
5176 +
5177 +//user virtual to bus address translation acceleration
5178 +static unsigned long g_virtAddr[VIRT_TO_BUS_CACHE_SIZE];
5179 +static unsigned long g_busAddr[VIRT_TO_BUS_CACHE_SIZE];
5180 +static unsigned long g_cbVirtAddr;
5181 +static unsigned long g_cbBusAddr;
5182 +static int g_cacheInsertAt;
5183 +static int g_cacheHit, g_cacheMiss;
5184 +
5185 +//off by default
5186 +static void __user *g_pMinPhys;
5187 +static void __user *g_pMaxPhys;
5188 +static unsigned long g_physOffset;
5189 +
5190 +/****** CACHE OPERATIONS ********/
5191 +static inline void FlushAddrCache(void)
5192 +{
5193 + int count = 0;
5194 + for (count = 0; count < VIRT_TO_BUS_CACHE_SIZE; count++)
5195 + g_virtAddr[count] = 0xffffffff; //never going to match as we always chop the bottom bits anyway
5196 +
5197 + g_cbVirtAddr = 0xffffffff;
5198 +
5199 + g_cacheInsertAt = 0;
5200 +}
5201 +
5202 +//translate from a user virtual address to a bus address by mapping the page
5203 +//NB this won't lock a page in memory, so to avoid potential paging issues using kernel logical addresses
5204 +static inline void __iomem *UserVirtualToBus(void __user *pUser)
5205 +{
5206 + int mapped;
5207 + struct page *pPage;
5208 + void *phys;
5209 +
5210 + //map it (requiring that the pointer points to something that does not hang off the page boundary)
5211 + mapped = get_user_pages(current, current->mm,
5212 + (unsigned long)pUser, 1,
5213 + 1, 0,
5214 + &pPage,
5215 + 0);
5216 +
5217 + if (mapped <= 0) //error
5218 + return 0;
5219 +
5220 + PRINTK_VERBOSE(KERN_DEBUG "user virtual %p arm phys %p bus %p\n",
5221 + pUser, page_address(pPage), (void __iomem *)__virt_to_bus(page_address(pPage)));
5222 +
5223 + //get the arm physical address
5224 + phys = page_address(pPage) + offset_in_page(pUser);
5225 + page_cache_release(pPage);
5226 +
5227 + //and now the bus address
5228 + return (void __iomem *)__virt_to_bus(phys);
5229 +}
5230 +
5231 +static inline void __iomem *UserVirtualToBusViaCbCache(void __user *pUser)
5232 +{
5233 + unsigned long virtual_page = (unsigned long)pUser & ~4095;
5234 + unsigned long page_offset = (unsigned long)pUser & 4095;
5235 + unsigned long bus_addr;
5236 +
5237 + if (g_cbVirtAddr == virtual_page)
5238 + {
5239 + bus_addr = g_cbBusAddr + page_offset;
5240 + g_cacheHit++;
5241 + return (void __iomem *)bus_addr;
5242 + }
5243 + else
5244 + {
5245 + bus_addr = (unsigned long)UserVirtualToBus(pUser);
5246 +
5247 + if (!bus_addr)
5248 + return 0;
5249 +
5250 + g_cbVirtAddr = virtual_page;
5251 + g_cbBusAddr = bus_addr & ~4095;
5252 + g_cacheMiss++;
5253 +
5254 + return (void __iomem *)bus_addr;
5255 + }
5256 +}
5257 +
5258 +//do the same as above, by query our virt->bus cache
5259 +static inline void __iomem *UserVirtualToBusViaCache(void __user *pUser)
5260 +{
5261 + int count;
5262 + //get the page and its offset
5263 + unsigned long virtual_page = (unsigned long)pUser & ~4095;
5264 + unsigned long page_offset = (unsigned long)pUser & 4095;
5265 + unsigned long bus_addr;
5266 +
5267 + if (pUser >= g_pMinPhys && pUser < g_pMaxPhys)
5268 + {
5269 + PRINTK_VERBOSE(KERN_DEBUG "user->phys passthrough on %p\n", pUser);
5270 + return (void __iomem *)((unsigned long)pUser + g_physOffset);
5271 + }
5272 +
5273 + //check the cache for our entry
5274 + for (count = 0; count < VIRT_TO_BUS_CACHE_SIZE; count++)
5275 + if (g_virtAddr[count] == virtual_page)
5276 + {
5277 + bus_addr = g_busAddr[count] + page_offset;
5278 + g_cacheHit++;
5279 + return (void __iomem *)bus_addr;
5280 + }
5281 +
5282 + //not found, look up manually and then insert its page address
5283 + bus_addr = (unsigned long)UserVirtualToBus(pUser);
5284 +
5285 + if (!bus_addr)
5286 + return 0;
5287 +
5288 + g_virtAddr[g_cacheInsertAt] = virtual_page;
5289 + g_busAddr[g_cacheInsertAt] = bus_addr & ~4095;
5290 +
5291 + //round robin
5292 + g_cacheInsertAt++;
5293 + if (g_cacheInsertAt == VIRT_TO_BUS_CACHE_SIZE)
5294 + g_cacheInsertAt = 0;
5295 +
5296 + g_cacheMiss++;
5297 +
5298 + return (void __iomem *)bus_addr;
5299 +}
5300 +
5301 +/***** FILE OPERATIONS ****/
5302 +static int Open(struct inode *pInode, struct file *pFile)
5303 +{
5304 + PRINTK(KERN_DEBUG "file opening: %d/%d\n", imajor(pInode), iminor(pInode));
5305 +
5306 + //check which device we are
5307 + if (iminor(pInode) == 0) //4k
5308 + {
5309 + //only one at a time
5310 + if (!atomic_dec_and_test(&g_oneLock4k))
5311 + {
5312 + atomic_inc(&g_oneLock4k);
5313 + return -EBUSY;
5314 + }
5315 + }
5316 + else
5317 + return -EINVAL;
5318 +
5319 + //todo there will be trouble if two different processes open the files
5320 +
5321 + //reset after any file is opened
5322 + g_pMinPhys = (void __user *)-1;
5323 + g_pMaxPhys = (void __user *)0;
5324 + g_physOffset = 0;
5325 + g_cmaHandle = 0;
5326 +
5327 + return 0;
5328 +}
5329 +
5330 +static int Release(struct inode *pInode, struct file *pFile)
5331 +{
5332 + PRINTK(KERN_DEBUG "file closing, %d pages tracked\n", g_trackedPages);
5333 + if (g_trackedPages)
5334 + PRINTK(KERN_ERR "we\'re leaking memory!\n");
5335 +
5336 + //wait for any dmas to finish
5337 + DmaWaitAll();
5338 +
5339 + //free this memory on the application closing the file or it crashing (implicitly closing the file)
5340 + if (g_cmaHandle)
5341 + {
5342 + PRINTK(KERN_DEBUG "unlocking vc memory\n");
5343 + if (UnlockVcMemory(g_cmaHandle))
5344 + PRINTK(KERN_ERR "uh-oh, unable to unlock vc memory!\n");
5345 + PRINTK(KERN_DEBUG "releasing vc memory\n");
5346 + if (ReleaseVcMemory(g_cmaHandle))
5347 + PRINTK(KERN_ERR "uh-oh, unable to release vc memory!\n");
5348 + }
5349 +
5350 + if (iminor(pInode) == 0)
5351 + atomic_inc(&g_oneLock4k);
5352 + else
5353 + return -EINVAL;
5354 +
5355 + return 0;
5356 +}
5357 +
5358 +static struct DmaControlBlock __user *DmaPrepare(struct DmaControlBlock __user *pUserCB, int *pError)
5359 +{
5360 + struct DmaControlBlock kernCB;
5361 + struct DmaControlBlock __user *pUNext;
5362 + void __iomem *pSourceBus, __iomem *pDestBus;
5363 +
5364 + //get the control block into kernel memory so we can work on it
5365 + if (copy_from_user(&kernCB, pUserCB, sizeof(struct DmaControlBlock)) != 0)
5366 + {
5367 + PRINTK(KERN_ERR "copy_from_user failed for user cb %p\n", pUserCB);
5368 + *pError = 1;
5369 + return 0;
5370 + }
5371 +
5372 + if (kernCB.m_pSourceAddr == 0 || kernCB.m_pDestAddr == 0)
5373 + {
5374 + PRINTK(KERN_ERR "faulty source (%p) dest (%p) addresses for user cb %p\n",
5375 + kernCB.m_pSourceAddr, kernCB.m_pDestAddr, pUserCB);
5376 + *pError = 1;
5377 + return 0;
5378 + }
5379 +
5380 + pSourceBus = UserVirtualToBusViaCache(kernCB.m_pSourceAddr);
5381 + pDestBus = UserVirtualToBusViaCache(kernCB.m_pDestAddr);
5382 +
5383 + if (!pSourceBus || !pDestBus)
5384 + {
5385 + PRINTK(KERN_ERR "virtual to bus translation failure for source/dest %p/%p->%p/%p\n",
5386 + kernCB.m_pSourceAddr, kernCB.m_pDestAddr,
5387 + pSourceBus, pDestBus);
5388 + *pError = 1;
5389 + return 0;
5390 + }
5391 +
5392 + //update the user structure with the new bus addresses
5393 + kernCB.m_pSourceAddr = pSourceBus;
5394 + kernCB.m_pDestAddr = pDestBus;
5395 +
5396 + PRINTK_VERBOSE(KERN_DEBUG "final source %p dest %p\n", kernCB.m_pSourceAddr, kernCB.m_pDestAddr);
5397 +
5398 + //sort out the bus address for the next block
5399 + pUNext = kernCB.m_pNext;
5400 +
5401 + if (kernCB.m_pNext)
5402 + {
5403 + void __iomem *pNextBus;
5404 + pNextBus = UserVirtualToBusViaCbCache(kernCB.m_pNext);
5405 +
5406 + if (!pNextBus)
5407 + {
5408 + PRINTK(KERN_ERR "virtual to bus translation failure for m_pNext\n");
5409 + *pError = 1;
5410 + return 0;
5411 + }
5412 +
5413 + //update the pointer with the bus address
5414 + kernCB.m_pNext = pNextBus;
5415 + }
5416 +
5417 + //write it back to user space
5418 + if (copy_to_user(pUserCB, &kernCB, sizeof(struct DmaControlBlock)) != 0)
5419 + {
5420 + PRINTK(KERN_ERR "copy_to_user failed for cb %p\n", pUserCB);
5421 + *pError = 1;
5422 + return 0;
5423 + }
5424 +
5425 + __cpuc_flush_dcache_area(pUserCB, 32);
5426 +
5427 + *pError = 0;
5428 + return pUNext;
5429 +}
5430 +
5431 +static int DmaKick(struct DmaControlBlock __user *pUserCB)
5432 +{
5433 + void __iomem *pBusCB;
5434 +
5435 + pBusCB = UserVirtualToBusViaCbCache(pUserCB);
5436 + if (!pBusCB)
5437 + {
5438 + PRINTK(KERN_ERR "virtual to bus translation failure for cb\n");
5439 + return 1;
5440 + }
5441 +
5442 + //flush_cache_all();
5443 +
5444 + bcm_dma_start(g_pDmaChanBase, (dma_addr_t)pBusCB);
5445 +
5446 + return 0;
5447 +}
5448 +
5449 +static void DmaWaitAll(void)
5450 +{
5451 + int counter = 0;
5452 + volatile int inner_count;
5453 + volatile unsigned int cs;
5454 + unsigned long time_before, time_after;
5455 +
5456 + time_before = jiffies;
5457 + //bcm_dma_wait_idle(g_pDmaChanBase);
5458 + dsb();
5459 +
5460 + cs = readl(g_pDmaChanBase);
5461 +
5462 + while ((cs & 1) == 1)
5463 + {
5464 + cs = readl(g_pDmaChanBase);
5465 + counter++;
5466 +
5467 + for (inner_count = 0; inner_count < 32; inner_count++);
5468 +
5469 + asm volatile ("MCR p15,0,r0,c7,c0,4 \n");
5470 + //cpu_do_idle();
5471 + if (counter >= 1000000)
5472 + {
5473 + PRINTK(KERN_WARNING "DMA failed to finish in a timely fashion\n");
5474 + break;
5475 + }
5476 + }
5477 + time_after = jiffies;
5478 + PRINTK_VERBOSE(KERN_DEBUG "done, counter %d, cs %08x", counter, cs);
5479 + PRINTK_VERBOSE(KERN_DEBUG "took %ld jiffies, %d HZ\n", time_after - time_before, HZ);
5480 +}
5481 +
5482 +static long Ioctl(struct file *pFile, unsigned int cmd, unsigned long arg)
5483 +{
5484 + int error = 0;
5485 + PRINTK_VERBOSE(KERN_DEBUG "ioctl cmd %x arg %lx\n", cmd, arg);
5486 +
5487 + switch (cmd)
5488 + {
5489 + case DMA_PREPARE:
5490 + case DMA_PREPARE_KICK:
5491 + case DMA_PREPARE_KICK_WAIT:
5492 + {
5493 + struct DmaControlBlock __user *pUCB = (struct DmaControlBlock *)arg;
5494 + int steps = 0;
5495 + unsigned long start_time = jiffies;
5496 + (void)start_time;
5497 +
5498 + //flush our address cache
5499 + FlushAddrCache();
5500 +
5501 + PRINTK_VERBOSE(KERN_DEBUG "dma prepare\n");
5502 +
5503 + //do virtual to bus translation for each entry
5504 + do
5505 + {
5506 + pUCB = DmaPrepare(pUCB, &error);
5507 + } while (error == 0 && ++steps && pUCB);
5508 + PRINTK_VERBOSE(KERN_DEBUG "prepare done in %d steps, %ld\n", steps, jiffies - start_time);
5509 +
5510 + //carry straight on if we want to kick too
5511 + if (cmd == DMA_PREPARE || error)
5512 + {
5513 + PRINTK_VERBOSE(KERN_DEBUG "falling out\n");
5514 + return error ? -EINVAL : 0;
5515 + }
5516 + }
5517 + case DMA_KICK:
5518 + PRINTK_VERBOSE(KERN_DEBUG "dma begin\n");
5519 +
5520 + if (cmd == DMA_KICK)
5521 + FlushAddrCache();
5522 +
5523 + DmaKick((struct DmaControlBlock __user *)arg);
5524 +
5525 + if (cmd != DMA_PREPARE_KICK_WAIT)
5526 + break;
5527 +/* case DMA_WAIT_ONE:
5528 + //PRINTK(KERN_DEBUG "dma wait one\n");
5529 + break;*/
5530 + case DMA_WAIT_ALL:
5531 + //PRINTK(KERN_DEBUG "dma wait all\n");
5532 + DmaWaitAll();
5533 + break;
5534 + case DMA_MAX_BURST:
5535 + if (g_dmaChan == 0)
5536 + return 10;
5537 + else
5538 + return 5;
5539 + case DMA_SET_MIN_PHYS:
5540 + g_pMinPhys = (void __user *)arg;
5541 + PRINTK(KERN_DEBUG "min/max user/phys bypass set to %p %p\n", g_pMinPhys, g_pMaxPhys);
5542 + break;
5543 + case DMA_SET_MAX_PHYS:
5544 + g_pMaxPhys = (void __user *)arg;
5545 + PRINTK(KERN_DEBUG "min/max user/phys bypass set to %p %p\n", g_pMinPhys, g_pMaxPhys);
5546 + break;
5547 + case DMA_SET_PHYS_OFFSET:
5548 + g_physOffset = arg;
5549 + PRINTK(KERN_DEBUG "user/phys bypass offset set to %ld\n", g_physOffset);
5550 + break;
5551 + case DMA_CMA_SET_SIZE:
5552 + {
5553 + unsigned int pBusAddr;
5554 +
5555 + if (g_cmaHandle)
5556 + {
5557 + PRINTK(KERN_ERR "memory has already been allocated (handle %d)\n", g_cmaHandle);
5558 + return -EINVAL;
5559 + }
5560 +
5561 + PRINTK(KERN_INFO "allocating %ld bytes of VC memory\n", arg * 4096);
5562 +
5563 + //get the memory
5564 + if (AllocateVcMemory(&g_cmaHandle, arg * 4096, 4096, MEM_FLAG_L1_NONALLOCATING | MEM_FLAG_NO_INIT | MEM_FLAG_HINT_PERMALOCK))
5565 + {
5566 + PRINTK(KERN_ERR "failed to allocate %ld bytes of VC memory\n", arg * 4096);
5567 + g_cmaHandle = 0;
5568 + return -EINVAL;
5569 + }
5570 +
5571 + //get an address for it
5572 + PRINTK(KERN_INFO "trying to map VC memory\n");
5573 +
5574 + if (LockVcMemory(&pBusAddr, g_cmaHandle))
5575 + {
5576 + PRINTK(KERN_ERR "failed to map CMA handle %d, releasing memory\n", g_cmaHandle);
5577 + ReleaseVcMemory(g_cmaHandle);
5578 + g_cmaHandle = 0;
5579 + }
5580 +
5581 + PRINTK(KERN_INFO "bus address for CMA memory is %x\n", pBusAddr);
5582 + return pBusAddr;
5583 + }
5584 + case DMA_GET_VERSION:
5585 + PRINTK(KERN_DEBUG "returning version number, %d\n", VERSION_NUMBER);
5586 + return VERSION_NUMBER;
5587 + default:
5588 + PRINTK(KERN_DEBUG "unknown ioctl: %d\n", cmd);
5589 + return -EINVAL;
5590 + }
5591 +
5592 + return 0;
5593 +}
5594 +
5595 +static ssize_t Read(struct file *pFile, char __user *pUser, size_t count, loff_t *offp)
5596 +{
5597 + return -EIO;
5598 +}
5599 +
5600 +static int Mmap(struct file *pFile, struct vm_area_struct *pVma)
5601 +{
5602 + struct PageList *pPages;
5603 + struct VmaPageList *pVmaList;
5604 +
5605 + PRINTK_VERBOSE(KERN_DEBUG "MMAP vma %p, length %ld (%s %d)\n",
5606 + pVma, pVma->vm_end - pVma->vm_start,
5607 + current->comm, current->pid);
5608 + PRINTK_VERBOSE(KERN_DEBUG "MMAP %p %d (tracked %d)\n", pVma, current->pid, g_trackedPages);
5609 +
5610 + //make a new page list
5611 + pPages = (struct PageList *)kmalloc(sizeof(struct PageList), GFP_KERNEL);
5612 + if (!pPages)
5613 + {
5614 + PRINTK(KERN_ERR "couldn\'t allocate a new page list (%s %d)\n",
5615 + current->comm, current->pid);
5616 + return -ENOMEM;
5617 + }
5618 +
5619 + //clear the page list
5620 + pPages->m_used = 0;
5621 + pPages->m_pNext = 0;
5622 +
5623 + //insert our vma and new page list somewhere
5624 + if (!pVma->vm_private_data)
5625 + {
5626 + struct VmaPageList *pList;
5627 +
5628 + PRINTK_VERBOSE(KERN_DEBUG "new vma list, making new one (%s %d)\n",
5629 + current->comm, current->pid);
5630 +
5631 + //make a new vma list
5632 + pList = (struct VmaPageList *)kmalloc(sizeof(struct VmaPageList), GFP_KERNEL);
5633 + if (!pList)
5634 + {
5635 + PRINTK(KERN_ERR "couldn\'t allocate vma page list (%s %d)\n",
5636 + current->comm, current->pid);
5637 + kfree(pPages);
5638 + return -ENOMEM;
5639 + }
5640 +
5641 + //clear this list
5642 + pVma->vm_private_data = (void *)pList;
5643 + pList->m_refCount = 0;
5644 + }
5645 +
5646 + pVmaList = (struct VmaPageList *)pVma->vm_private_data;
5647 +
5648 + //add it to the vma list
5649 + pVmaList->m_pPageHead = pPages;
5650 + pVmaList->m_pPageTail = pPages;
5651 +
5652 + pVma->vm_ops = &g_vmOps4k;
5653 + pVma->vm_flags |= VM_IO;
5654 +
5655 + VmaOpen4k(pVma);
5656 +
5657 + return 0;
5658 +}
5659 +
5660 +/****** VMA OPERATIONS ******/
5661 +
5662 +static void VmaOpen4k(struct vm_area_struct *pVma)
5663 +{
5664 + struct VmaPageList *pVmaList;
5665 +
5666 + PRINTK_VERBOSE(KERN_DEBUG "vma open %p private %p (%s %d), %d live pages\n", pVma, pVma->vm_private_data, current->comm, current->pid, g_trackedPages);
5667 + PRINTK_VERBOSE(KERN_DEBUG "OPEN %p %d %ld pages (tracked pages %d)\n",
5668 + pVma, current->pid, (pVma->vm_end - pVma->vm_start) >> 12,
5669 + g_trackedPages);
5670 +
5671 + pVmaList = (struct VmaPageList *)pVma->vm_private_data;
5672 +
5673 + if (pVmaList)
5674 + {
5675 + pVmaList->m_refCount++;
5676 + PRINTK_VERBOSE(KERN_DEBUG "ref count is now %d\n", pVmaList->m_refCount);
5677 + }
5678 + else
5679 + {
5680 + PRINTK_VERBOSE(KERN_DEBUG "err, open but no vma page list\n");
5681 + }
5682 +}
5683 +
5684 +static void VmaClose4k(struct vm_area_struct *pVma)
5685 +{
5686 + struct VmaPageList *pVmaList;
5687 + int freed = 0;
5688 +
5689 + PRINTK_VERBOSE(KERN_DEBUG "vma close %p private %p (%s %d)\n", pVma, pVma->vm_private_data, current->comm, current->pid);
5690 +
5691 + //wait for any dmas to finish
5692 + DmaWaitAll();
5693 +
5694 + //find our vma in the list
5695 + pVmaList = (struct VmaPageList *)pVma->vm_private_data;
5696 +
5697 + //may be a fork
5698 + if (pVmaList)
5699 + {
5700 + struct PageList *pPages;
5701 +
5702 + pVmaList->m_refCount--;
5703 +
5704 + if (pVmaList->m_refCount == 0)
5705 + {
5706 + PRINTK_VERBOSE(KERN_DEBUG "found vma, freeing pages (%s %d)\n",
5707 + current->comm, current->pid);
5708 +
5709 + pPages = pVmaList->m_pPageHead;
5710 +
5711 + if (!pPages)
5712 + {
5713 + PRINTK(KERN_ERR "no page list (%s %d)!\n",
5714 + current->comm, current->pid);
5715 + return;
5716 + }
5717 +
5718 + while (pPages)
5719 + {
5720 + struct PageList *next;
5721 + int count;
5722 +
5723 + PRINTK_VERBOSE(KERN_DEBUG "page list (%s %d)\n",
5724 + current->comm, current->pid);
5725 +
5726 + next = pPages->m_pNext;
5727 + for (count = 0; count < pPages->m_used; count++)
5728 + {
5729 + PRINTK_VERBOSE(KERN_DEBUG "freeing page %p (%s %d)\n",
5730 + pPages->m_pPages[count],
5731 + current->comm, current->pid);
5732 + __free_pages(pPages->m_pPages[count], 0);
5733 + g_trackedPages--;
5734 + freed++;
5735 + }
5736 +
5737 + PRINTK_VERBOSE(KERN_DEBUG "freeing page list (%s %d)\n",
5738 + current->comm, current->pid);
5739 + kfree(pPages);
5740 + pPages = next;
5741 + }
5742 +
5743 + //remove our vma from the list
5744 + kfree(pVmaList);
5745 + pVma->vm_private_data = 0;
5746 + }
5747 + else
5748 + {
5749 + PRINTK_VERBOSE(KERN_DEBUG "ref count is %d, not closing\n", pVmaList->m_refCount);
5750 + }
5751 + }
5752 + else
5753 + {
5754 + PRINTK_VERBOSE(KERN_ERR "uh-oh, vma %p not found (%s %d)!\n", pVma, current->comm, current->pid);
5755 + PRINTK_VERBOSE(KERN_ERR "CLOSE ERR\n");
5756 + }
5757 +
5758 + PRINTK_VERBOSE(KERN_DEBUG "CLOSE %p %d %d pages (tracked pages %d)",
5759 + pVma, current->pid, freed, g_trackedPages);
5760 +
5761 + PRINTK_VERBOSE(KERN_DEBUG "%d pages open\n", g_trackedPages);
5762 +}
5763 +
5764 +static int VmaFault4k(struct vm_area_struct *pVma, struct vm_fault *pVmf)
5765 +{
5766 + PRINTK_VERBOSE(KERN_DEBUG "vma fault for vma %p private %p at offset %ld (%s %d)\n", pVma, pVma->vm_private_data, pVmf->pgoff,
5767 + current->comm, current->pid);
5768 + PRINTK_VERBOSE(KERN_DEBUG "FAULT\n");
5769 + pVmf->page = alloc_page(GFP_KERNEL);
5770 +
5771 + if (pVmf->page)
5772 + {
5773 + PRINTK_VERBOSE(KERN_DEBUG "alloc page virtual %p\n", page_address(pVmf->page));
5774 + }
5775 +
5776 + if (!pVmf->page)
5777 + {
5778 + PRINTK(KERN_ERR "vma fault oom (%s %d)\n", current->comm, current->pid);
5779 + return VM_FAULT_OOM;
5780 + }
5781 + else
5782 + {
5783 + struct VmaPageList *pVmaList;
5784 +
5785 + get_page(pVmf->page);
5786 + g_trackedPages++;
5787 +
5788 + //find our vma in the list
5789 + pVmaList = (struct VmaPageList *)pVma->vm_private_data;
5790 +
5791 + if (pVmaList)
5792 + {
5793 + PRINTK_VERBOSE(KERN_DEBUG "vma found (%s %d)\n", current->comm, current->pid);
5794 +
5795 + if (pVmaList->m_pPageTail->m_used == PAGES_PER_LIST)
5796 + {
5797 + PRINTK_VERBOSE(KERN_DEBUG "making new page list (%s %d)\n", current->comm, current->pid);
5798 + //making a new page list
5799 + pVmaList->m_pPageTail->m_pNext = (struct PageList *)kmalloc(sizeof(struct PageList), GFP_KERNEL);
5800 + if (!pVmaList->m_pPageTail->m_pNext)
5801 + return -ENOMEM;
5802 +
5803 + //update the tail pointer
5804 + pVmaList->m_pPageTail = pVmaList->m_pPageTail->m_pNext;
5805 + pVmaList->m_pPageTail->m_used = 0;
5806 + pVmaList->m_pPageTail->m_pNext = 0;
5807 + }
5808 +
5809 + PRINTK_VERBOSE(KERN_DEBUG "adding page to list (%s %d)\n", current->comm, current->pid);
5810 +
5811 + pVmaList->m_pPageTail->m_pPages[pVmaList->m_pPageTail->m_used] = pVmf->page;
5812 + pVmaList->m_pPageTail->m_used++;
5813 + }
5814 + else
5815 + PRINTK(KERN_ERR "returned page for vma we don\'t know %p (%s %d)\n", pVma, current->comm, current->pid);
5816 +
5817 + return 0;
5818 + }
5819 +}
5820 +
5821 +/****** GENERIC FUNCTIONS ******/
5822 +static int __init dmaer_init(void)
5823 +{
5824 + int result = alloc_chrdev_region(&g_majorMinor, 0, 1, "dmaer");
5825 + if (result < 0)
5826 + {
5827 + PRINTK(KERN_ERR "unable to get major device number\n");
5828 + return result;
5829 + }
5830 + else
5831 + PRINTK(KERN_DEBUG "major device number %d\n", MAJOR(g_majorMinor));
5832 +
5833 + PRINTK(KERN_DEBUG "vma list size %d, page list size %d, page size %ld\n",
5834 + sizeof(struct VmaPageList), sizeof(struct PageList), PAGE_SIZE);
5835 +
5836 + //get a dma channel to work with
5837 + result = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST, (void **)&g_pDmaChanBase, &g_dmaIrq);
5838 +
5839 + //uncomment to force to channel 0
5840 + //result = 0;
5841 + //g_pDmaChanBase = 0xce808000;
5842 +
5843 + if (result < 0)
5844 + {
5845 + PRINTK(KERN_ERR "failed to allocate dma channel\n");
5846 + cdev_del(&g_cDev);
5847 + unregister_chrdev_region(g_majorMinor, 1);
5848 + }
5849 +
5850 + //reset the channel
5851 + PRINTK(KERN_DEBUG "allocated dma channel %d (%p), initial state %08x\n", result, g_pDmaChanBase, *g_pDmaChanBase);
5852 + *g_pDmaChanBase = 1 << 31;
5853 + PRINTK(KERN_DEBUG "post-reset %08x\n", *g_pDmaChanBase);
5854 +
5855 + g_dmaChan = result;
5856 +
5857 + //clear the cache stats
5858 + g_cacheHit = 0;
5859 + g_cacheMiss = 0;
5860 +
5861 + //register our device - after this we are go go go
5862 + cdev_init(&g_cDev, &g_fOps);
5863 + g_cDev.owner = THIS_MODULE;
5864 + g_cDev.ops = &g_fOps;
5865 +
5866 + result = cdev_add(&g_cDev, g_majorMinor, 1);
5867 + if (result < 0)
5868 + {
5869 + PRINTK(KERN_ERR "failed to add character device\n");
5870 + unregister_chrdev_region(g_majorMinor, 1);
5871 + bcm_dma_chan_free(g_dmaChan);
5872 + return result;
5873 + }
5874 +
5875 + return 0;
5876 +}
5877 +
5878 +static void __exit dmaer_exit(void)
5879 +{
5880 + PRINTK(KERN_INFO "closing dmaer device, cache stats: %d hits %d misses\n", g_cacheHit, g_cacheMiss);
5881 + //unregister the device
5882 + cdev_del(&g_cDev);
5883 + unregister_chrdev_region(g_majorMinor, 1);
5884 + //free the dma channel
5885 + bcm_dma_chan_free(g_dmaChan);
5886 +}
5887 +
5888 +MODULE_LICENSE("Dual BSD/GPL");
5889 +MODULE_AUTHOR("Simon Hall");
5890 +module_init(dmaer_init);
5891 +module_exit(dmaer_exit);
5892 --- /dev/null
5893 +++ b/arch/arm/mach-bcm2709/include/mach/arm_control.h
5894 @@ -0,0 +1,493 @@
5895 +/*
5896 + * linux/arch/arm/mach-bcm2708/arm_control.h
5897 + *
5898 + * Copyright (C) 2010 Broadcom
5899 + *
5900 + * This program is free software; you can redistribute it and/or modify
5901 + * it under the terms of the GNU General Public License as published by
5902 + * the Free Software Foundation; either version 2 of the License, or
5903 + * (at your option) any later version.
5904 + *
5905 + * This program is distributed in the hope that it will be useful,
5906 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5907 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5908 + * GNU General Public License for more details.
5909 + *
5910 + * You should have received a copy of the GNU General Public License
5911 + * along with this program; if not, write to the Free Software
5912 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5913 + */
5914 +
5915 +#ifndef __BCM2708_ARM_CONTROL_H
5916 +#define __BCM2708_ARM_CONTROL_H
5917 +
5918 +/*
5919 + * Definitions and addresses for the ARM CONTROL logic
5920 + * This file is manually generated.
5921 + */
5922 +
5923 +#define ARM_BASE 0x7E00B000
5924 +
5925 +/* Basic configuration */
5926 +#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
5927 +#define ARM_C0_SIZ128M 0x00000000
5928 +#define ARM_C0_SIZ256M 0x00000001
5929 +#define ARM_C0_SIZ512M 0x00000002
5930 +#define ARM_C0_SIZ1G 0x00000003
5931 +#define ARM_C0_BRESP0 0x00000000
5932 +#define ARM_C0_BRESP1 0x00000004
5933 +#define ARM_C0_BRESP2 0x00000008
5934 +#define ARM_C0_BOOTHI 0x00000010
5935 +#define ARM_C0_UNUSED05 0x00000020 /* free */
5936 +#define ARM_C0_FULLPERI 0x00000040
5937 +#define ARM_C0_UNUSED78 0x00000180 /* free */
5938 +#define ARM_C0_JTAGMASK 0x00000E00
5939 +#define ARM_C0_JTAGOFF 0x00000000
5940 +#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
5941 +#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
5942 +#define ARM_C0_APROTMSK 0x0000F000
5943 +#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
5944 +#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
5945 +#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
5946 +#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
5947 +#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
5948 +#define ARM_C0_PRIO_L2 0x0F000000
5949 +#define ARM_C0_PRIO_UC 0xF0000000
5950 +
5951 +#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
5952 +#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
5953 +#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
5954 +
5955 +
5956 +#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
5957 +#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
5958 +#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
5959 +#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
5960 +#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
5961 +#define ARM_C1_PERSON 0x00000100 /* peripherals on */
5962 +#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
5963 +
5964 +#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
5965 +#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
5966 +#define ARM_S_READPEND 0x000003FF /* pending reads counter */
5967 +#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
5968 +
5969 +#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
5970 +#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
5971 +#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
5972 +#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
5973 +#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
5974 +#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
5975 +#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
5976 +
5977 +#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
5978 +#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
5979 +#define ARM_IDVAL 0x364D5241
5980 +
5981 +/* Translation memory */
5982 +#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
5983 +/* 32 locations: 0x100.. 0x17F */
5984 +/* 32 spare means we CAN go to 64 pages.... */
5985 +
5986 +
5987 +/* Interrupts */
5988 +#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
5989 +#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
5990 +#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
5991 +#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
5992 +#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
5993 +#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
5994 +#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
5995 +
5996 +#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
5997 +/* todo: all I1_interrupt sources */
5998 +#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
5999 +/* todo: all I2_interrupt sources */
6000 +
6001 +#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
6002 +#define ARM_IF_INDEX 0x0000007F /* FIQ select */
6003 +#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
6004 +#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
6005 +#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
6006 +#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
6007 +#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
6008 +#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
6009 +#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
6010 +#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
6011 +#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
6012 +
6013 +#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
6014 +#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
6015 +#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
6016 +#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
6017 +#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
6018 +#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
6019 +#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
6020 +#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
6021 +#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
6022 +#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
6023 +#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
6024 +#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
6025 +#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
6026 +
6027 +/* Timer */
6028 +/* For reg. fields see sp804 spec. */
6029 +#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
6030 +#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
6031 +#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
6032 +#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
6033 +#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
6034 +#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
6035 +#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
6036 +#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
6037 +#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
6038 +
6039 +#define TIMER_CTRL_ONESHOT (1 << 0)
6040 +#define TIMER_CTRL_32BIT (1 << 1)
6041 +#define TIMER_CTRL_DIV1 (0 << 2)
6042 +#define TIMER_CTRL_DIV16 (1 << 2)
6043 +#define TIMER_CTRL_DIV256 (2 << 2)
6044 +#define TIMER_CTRL_IE (1 << 5)
6045 +#define TIMER_CTRL_PERIODIC (1 << 6)
6046 +#define TIMER_CTRL_ENABLE (1 << 7)
6047 +#define TIMER_CTRL_DBGHALT (1 << 8)
6048 +#define TIMER_CTRL_ENAFREE (1 << 9)
6049 +#define TIMER_CTRL_FREEDIV_SHIFT 16)
6050 +#define TIMER_CTRL_FREEDIV_MASK 0xff
6051 +
6052 +/* Semaphores, Doorbells, Mailboxes */
6053 +#define ARM_SBM_OWN0 (ARM_BASE+0x800)
6054 +#define ARM_SBM_OWN1 (ARM_BASE+0x900)
6055 +#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
6056 +#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
6057 +
6058 +/* MAILBOXES
6059 + * Register flags are common across all
6060 + * owner registers. See end of this section
6061 + *
6062 + * Semaphores, Doorbells, Mailboxes Owner 0
6063 + *
6064 + */
6065 +
6066 +#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
6067 +#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
6068 +#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
6069 +#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
6070 +#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
6071 +#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
6072 +#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
6073 +#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
6074 +#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
6075 +#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
6076 +#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
6077 +#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
6078 +#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
6079 +/* MAILBOX 0 access in Owner 0 area */
6080 +/* Some addresses should ONLY be used by owner 0 */
6081 +#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
6082 +#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
6083 +#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
6084 +#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
6085 +#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
6086 +#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
6087 +/* MAILBOX 1 access in Owner 0 area */
6088 +/* Owner 0 should only WRITE to this mailbox */
6089 +#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
6090 +/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
6091 +/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
6092 +/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
6093 +#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
6094 +/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
6095 +/* General SEM, BELL, MAIL config/status */
6096 +#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
6097 +#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
6098 +#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
6099 +#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
6100 +
6101 +/* Semaphores, Doorbells, Mailboxes Owner 1 */
6102 +#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
6103 +#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
6104 +#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
6105 +#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
6106 +#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
6107 +#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
6108 +#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
6109 +#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
6110 +#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
6111 +#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
6112 +#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
6113 +#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
6114 +#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
6115 +/* MAILBOX 0 access in Owner 0 area */
6116 +/* Owner 1 should only WRITE to this mailbox */
6117 +#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
6118 +/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
6119 +/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
6120 +/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
6121 +#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
6122 +/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
6123 +/* MAILBOX 1 access in Owner 0 area */
6124 +#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
6125 +#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
6126 +#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
6127 +#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
6128 +#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
6129 +#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
6130 +/* General SEM, BELL, MAIL config/status */
6131 +#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
6132 +#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
6133 +#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
6134 +#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
6135 +
6136 +/* Semaphores, Doorbells, Mailboxes Owner 2 */
6137 +#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
6138 +#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
6139 +#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
6140 +#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
6141 +#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
6142 +#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
6143 +#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
6144 +#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
6145 +#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
6146 +#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
6147 +#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
6148 +#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
6149 +#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
6150 +/* MAILBOX 0 access in Owner 2 area */
6151 +/* Owner 2 should only WRITE to this mailbox */
6152 +#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
6153 +/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
6154 +/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
6155 +/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
6156 +#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
6157 +/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
6158 +/* MAILBOX 1 access in Owner 2 area */
6159 +/* Owner 2 should only WRITE to this mailbox */
6160 +#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
6161 +/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
6162 +/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
6163 +/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
6164 +#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
6165 +/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
6166 +/* General SEM, BELL, MAIL config/status */
6167 +#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
6168 +#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
6169 +#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
6170 +#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
6171 +
6172 +/* Semaphores, Doorbells, Mailboxes Owner 3 */
6173 +#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
6174 +#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
6175 +#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
6176 +#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
6177 +#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
6178 +#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
6179 +#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
6180 +#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
6181 +#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
6182 +#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
6183 +#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
6184 +#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
6185 +#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
6186 +/* MAILBOX 0 access in Owner 3 area */
6187 +/* Owner 3 should only WRITE to this mailbox */
6188 +#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
6189 +/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
6190 +/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
6191 +/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
6192 +#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
6193 +/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
6194 +/* MAILBOX 1 access in Owner 3 area */
6195 +/* Owner 3 should only WRITE to this mailbox */
6196 +#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
6197 +/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
6198 +/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
6199 +/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
6200 +#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
6201 +/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
6202 +/* General SEM, BELL, MAIL config/status */
6203 +#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
6204 +#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
6205 +#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
6206 +#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
6207 +
6208 +
6209 +
6210 +/* Mailbox flags. Valid for all owners */
6211 +
6212 +/* Mailbox status register (...0x98) */
6213 +#define ARM_MS_FULL 0x80000000
6214 +#define ARM_MS_EMPTY 0x40000000
6215 +#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
6216 +
6217 +/* MAILBOX config/status register (...0x9C) */
6218 +/* ANY write to this register clears the error bits! */
6219 +#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
6220 +#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
6221 +#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
6222 +#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
6223 +#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
6224 +#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
6225 +#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
6226 +/* Bit 7 is unused */
6227 +#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
6228 +#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
6229 +#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
6230 +
6231 +/* Semaphore clear/debug register (...0xE0) */
6232 +#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
6233 +#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
6234 +#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
6235 +#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
6236 +#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
6237 +#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
6238 +#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
6239 +#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
6240 +#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
6241 +#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
6242 +#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
6243 +#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
6244 +#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
6245 +#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
6246 +#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
6247 +#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
6248 +
6249 +/* Doorbells clear/debug register (...0xE4) */
6250 +#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
6251 +#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
6252 +#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
6253 +#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
6254 +#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
6255 +#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
6256 +#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
6257 +#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
6258 +
6259 +/* MY IRQS register (...0xF8) */
6260 +#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
6261 +#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
6262 +
6263 +/* ALL IRQS register (...0xF8) */
6264 +#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
6265 +#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
6266 +#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
6267 +#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
6268 +#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
6269 +#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
6270 +#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
6271 +#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
6272 +#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
6273 +#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
6274 +/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
6275 +/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
6276 +/* */
6277 +/* ARM JTAG BASH */
6278 +/* */
6279 +#define AJB_BASE 0x7e2000c0
6280 +
6281 +#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
6282 +#define AJB_BITS0 0x000000
6283 +#define AJB_BITS4 0x000004
6284 +#define AJB_BITS8 0x000008
6285 +#define AJB_BITS12 0x00000C
6286 +#define AJB_BITS16 0x000010
6287 +#define AJB_BITS20 0x000014
6288 +#define AJB_BITS24 0x000018
6289 +#define AJB_BITS28 0x00001C
6290 +#define AJB_BITS32 0x000020
6291 +#define AJB_BITS34 0x000022
6292 +#define AJB_OUT_MS 0x000040
6293 +#define AJB_OUT_LS 0x000000
6294 +#define AJB_INV_CLK 0x000080
6295 +#define AJB_D0_RISE 0x000100
6296 +#define AJB_D0_FALL 0x000000
6297 +#define AJB_D1_RISE 0x000200
6298 +#define AJB_D1_FALL 0x000000
6299 +#define AJB_IN_RISE 0x000400
6300 +#define AJB_IN_FALL 0x000000
6301 +#define AJB_ENABLE 0x000800
6302 +#define AJB_HOLD0 0x000000
6303 +#define AJB_HOLD1 0x001000
6304 +#define AJB_HOLD2 0x002000
6305 +#define AJB_HOLD3 0x003000
6306 +#define AJB_RESETN 0x004000
6307 +#define AJB_CLKSHFT 16
6308 +#define AJB_BUSY 0x80000000
6309 +#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
6310 +#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
6311 +#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
6312 +
6313 +#define ARM_LOCAL_BASE 0x40000000
6314 +#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000)
6315 +#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008)
6316 +#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C)
6317 +#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010)
6318 +#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014)
6319 +#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C)
6320 +#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020)
6321 +#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024)
6322 +#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C)
6323 +#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030)
6324 +#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034)
6325 +#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038)
6326 +
6327 +#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040)
6328 +#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044)
6329 +#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048)
6330 +#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C)
6331 +
6332 +#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050)
6333 +#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054)
6334 +#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058)
6335 +#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C)
6336 +
6337 +#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060)
6338 +#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064)
6339 +#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068)
6340 +#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C)
6341 +
6342 +#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070)
6343 +#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074)
6344 +#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078)
6345 +#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C)
6346 +
6347 +#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080)
6348 +#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084)
6349 +#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088)
6350 +#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C)
6351 +
6352 +#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090)
6353 +#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094)
6354 +#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098)
6355 +#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C)
6356 +
6357 +#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0)
6358 +#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4)
6359 +#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8)
6360 +#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC)
6361 +
6362 +#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0)
6363 +#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4)
6364 +#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8)
6365 +#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC)
6366 +
6367 +#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0)
6368 +#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4)
6369 +#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8)
6370 +#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC)
6371 +
6372 +#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0)
6373 +#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4)
6374 +#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8)
6375 +#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC)
6376 +
6377 +#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0)
6378 +#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4)
6379 +#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8)
6380 +#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC)
6381 +
6382 +#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0)
6383 +#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4)
6384 +#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8)
6385 +#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC)
6386 +
6387 +#endif
6388 --- /dev/null
6389 +++ b/arch/arm/mach-bcm2709/include/mach/arm_power.h
6390 @@ -0,0 +1,62 @@
6391 +/*
6392 + * linux/arch/arm/mach-bcm2708/include/mach/arm_power.h
6393 + *
6394 + * Copyright (C) 2010 Broadcom
6395 + *
6396 + * This program is free software; you can redistribute it and/or modify
6397 + * it under the terms of the GNU General Public License as published by
6398 + * the Free Software Foundation; either version 2 of the License, or
6399 + * (at your option) any later version.
6400 + *
6401 + * This program is distributed in the hope that it will be useful,
6402 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6403 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6404 + * GNU General Public License for more details.
6405 + *
6406 + * You should have received a copy of the GNU General Public License
6407 + * along with this program; if not, write to the Free Software
6408 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6409 + */
6410 +
6411 +#ifndef _ARM_POWER_H
6412 +#define _ARM_POWER_H
6413 +
6414 +/* Use meaningful names on each side */
6415 +#ifdef __VIDEOCORE__
6416 +#define PREFIX(x) ARM_##x
6417 +#else
6418 +#define PREFIX(x) BCM_##x
6419 +#endif
6420 +
6421 +enum {
6422 + PREFIX(POWER_SDCARD_BIT),
6423 + PREFIX(POWER_UART_BIT),
6424 + PREFIX(POWER_MINIUART_BIT),
6425 + PREFIX(POWER_USB_BIT),
6426 + PREFIX(POWER_I2C0_BIT),
6427 + PREFIX(POWER_I2C1_BIT),
6428 + PREFIX(POWER_I2C2_BIT),
6429 + PREFIX(POWER_SPI_BIT),
6430 + PREFIX(POWER_CCP2TX_BIT),
6431 + PREFIX(POWER_DSI_BIT),
6432 +
6433 + PREFIX(POWER_MAX)
6434 +};
6435 +
6436 +enum {
6437 + PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)),
6438 + PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)),
6439 + PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)),
6440 + PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)),
6441 + PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)),
6442 + PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)),
6443 + PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)),
6444 + PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)),
6445 + PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)),
6446 + PREFIX(POWER_DSI) = (1 << PREFIX(POWER_DSI_BIT)),
6447 +
6448 + PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1,
6449 + PREFIX(POWER_NONE) = 0
6450 +};
6451 +
6452 +#endif
6453 --- /dev/null
6454 +++ b/arch/arm/mach-bcm2709/include/mach/barriers.h
6455 @@ -0,0 +1,3 @@
6456 +#define mb() dsb()
6457 +#define rmb() dsb()
6458 +#define wmb() mb()
6459 --- /dev/null
6460 +++ b/arch/arm/mach-bcm2709/include/mach/clkdev.h
6461 @@ -0,0 +1,7 @@
6462 +#ifndef __ASM_MACH_CLKDEV_H
6463 +#define __ASM_MACH_CLKDEV_H
6464 +
6465 +#define __clk_get(clk) ({ 1; })
6466 +#define __clk_put(clk) do { } while (0)
6467 +
6468 +#endif
6469 --- /dev/null
6470 +++ b/arch/arm/mach-bcm2709/include/mach/debug-macro.S
6471 @@ -0,0 +1,22 @@
6472 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
6473 + *
6474 + * Debugging macro include header
6475 + *
6476 + * Copyright (C) 2010 Broadcom
6477 + * Copyright (C) 1994-1999 Russell King
6478 + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
6479 + *
6480 + * This program is free software; you can redistribute it and/or modify
6481 + * it under the terms of the GNU General Public License version 2 as
6482 + * published by the Free Software Foundation.
6483 + *
6484 +*/
6485 +
6486 +#include <mach/platform.h>
6487 +
6488 + .macro addruart, rp, rv, tmp
6489 + ldr \rp, =UART0_BASE
6490 + ldr \rv, =IO_ADDRESS(UART0_BASE)
6491 + .endm
6492 +
6493 +#include <debug/pl01x.S>
6494 --- /dev/null
6495 +++ b/arch/arm/mach-bcm2709/include/mach/dma.h
6496 @@ -0,0 +1,94 @@
6497 +/*
6498 + * linux/arch/arm/mach-bcm2708/include/mach/dma.h
6499 + *
6500 + * Copyright (C) 2010 Broadcom
6501 + *
6502 + * This program is free software; you can redistribute it and/or modify
6503 + * it under the terms of the GNU General Public License version 2 as
6504 + * published by the Free Software Foundation.
6505 + */
6506 +
6507 +
6508 +#ifndef _MACH_BCM2708_DMA_H
6509 +#define _MACH_BCM2708_DMA_H
6510 +
6511 +#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma"
6512 +
6513 +/* DMA CS Control and Status bits */
6514 +#define BCM2708_DMA_ACTIVE (1 << 0)
6515 +#define BCM2708_DMA_INT (1 << 2)
6516 +#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
6517 +#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
6518 +#define BCM2708_DMA_ERR (1 << 8)
6519 +#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
6520 +#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */
6521 +
6522 +/* DMA control block "info" field bits */
6523 +#define BCM2708_DMA_INT_EN (1 << 0)
6524 +#define BCM2708_DMA_TDMODE (1 << 1)
6525 +#define BCM2708_DMA_WAIT_RESP (1 << 3)
6526 +#define BCM2708_DMA_D_INC (1 << 4)
6527 +#define BCM2708_DMA_D_WIDTH (1 << 5)
6528 +#define BCM2708_DMA_D_DREQ (1 << 6)
6529 +#define BCM2708_DMA_S_INC (1 << 8)
6530 +#define BCM2708_DMA_S_WIDTH (1 << 9)
6531 +#define BCM2708_DMA_S_DREQ (1 << 10)
6532 +
6533 +#define BCM2708_DMA_BURST(x) (((x)&0xf) << 12)
6534 +#define BCM2708_DMA_PER_MAP(x) ((x) << 16)
6535 +#define BCM2708_DMA_WAITS(x) (((x)&0x1f) << 21)
6536 +
6537 +#define BCM2708_DMA_DREQ_EMMC 11
6538 +#define BCM2708_DMA_DREQ_SDHOST 13
6539 +
6540 +#define BCM2708_DMA_CS 0x00 /* Control and Status */
6541 +#define BCM2708_DMA_ADDR 0x04
6542 +/* the current control block appears in the following registers - read only */
6543 +#define BCM2708_DMA_INFO 0x08
6544 +#define BCM2708_DMA_SOURCE_AD 0x0c
6545 +#define BCM2708_DMA_DEST_AD 0x10
6546 +#define BCM2708_DMA_NEXTCB 0x1C
6547 +#define BCM2708_DMA_DEBUG 0x20
6548 +
6549 +#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
6550 +#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
6551 +
6552 +#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
6553 +
6554 +struct bcm2708_dma_cb {
6555 + unsigned long info;
6556 + unsigned long src;
6557 + unsigned long dst;
6558 + unsigned long length;
6559 + unsigned long stride;
6560 + unsigned long next;
6561 + unsigned long pad[2];
6562 +};
6563 +struct scatterlist;
6564 +
6565 +extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
6566 +extern void bcm_dma_start(void __iomem *dma_chan_base,
6567 + dma_addr_t control_block);
6568 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base);
6569 +extern bool bcm_dma_is_busy(void __iomem *dma_chan_base);
6570 +extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
6571 +
6572 +/* When listing features we can ask for when allocating DMA channels give
6573 + those with higher priority smaller ordinal numbers */
6574 +#define BCM_DMA_FEATURE_FAST_ORD 0
6575 +#define BCM_DMA_FEATURE_BULK_ORD 1
6576 +#define BCM_DMA_FEATURE_NORMAL_ORD 2
6577 +#define BCM_DMA_FEATURE_LITE_ORD 3
6578 +#define BCM_DMA_FEATURE_FAST (1<<BCM_DMA_FEATURE_FAST_ORD)
6579 +#define BCM_DMA_FEATURE_BULK (1<<BCM_DMA_FEATURE_BULK_ORD)
6580 +#define BCM_DMA_FEATURE_NORMAL (1<<BCM_DMA_FEATURE_NORMAL_ORD)
6581 +#define BCM_DMA_FEATURE_LITE (1<<BCM_DMA_FEATURE_LITE_ORD)
6582 +#define BCM_DMA_FEATURE_COUNT 4
6583 +
6584 +/* return channel no or -ve error */
6585 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
6586 + void __iomem **out_dma_base, int *out_dma_irq);
6587 +extern int bcm_dma_chan_free(int channel);
6588 +
6589 +
6590 +#endif /* _MACH_BCM2708_DMA_H */
6591 --- /dev/null
6592 +++ b/arch/arm/mach-bcm2709/include/mach/entry-macro.S
6593 @@ -0,0 +1,123 @@
6594 +/*
6595 + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
6596 + *
6597 + * Low-level IRQ helper macros for BCM2708 platforms
6598 + *
6599 + * Copyright (C) 2010 Broadcom
6600 + *
6601 + * This program is free software; you can redistribute it and/or modify
6602 + * it under the terms of the GNU General Public License as published by
6603 + * the Free Software Foundation; either version 2 of the License, or
6604 + * (at your option) any later version.
6605 + *
6606 + * This program is distributed in the hope that it will be useful,
6607 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6608 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6609 + * GNU General Public License for more details.
6610 + *
6611 + * You should have received a copy of the GNU General Public License
6612 + * along with this program; if not, write to the Free Software
6613 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6614 + */
6615 +#include <mach/hardware.h>
6616 +#include <mach/irqs.h>
6617 +
6618 + .macro disable_fiq
6619 + .endm
6620 +
6621 + .macro get_irqnr_preamble, base, tmp
6622 + ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
6623 + .endm
6624 +
6625 + .macro arch_ret_to_user, tmp1, tmp2
6626 + .endm
6627 +
6628 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
6629 + /* get core number */
6630 + mrc p15, 0, \tmp, c0, c0, 5
6631 + ubfx \tmp, \tmp, #0, #2
6632 +
6633 + /* get core's local interrupt controller */
6634 + ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
6635 + add \irqstat, \irqstat, \tmp, lsl #2
6636 + ldr \tmp, [\irqstat]
6637 + /* ignore gpu interrupt */
6638 + bic \tmp, #0x100
6639 + /* ignore mailbox interrupts */
6640 + bics \tmp, #0xf0
6641 + beq 1005f
6642 +
6643 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
6644 + @ N.B. CLZ is an ARM5 instruction.
6645 + mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
6646 + sub \irqstat, \tmp, #1
6647 + eor \irqstat, \irqstat, \tmp
6648 + clz \tmp, \irqstat
6649 + sub \irqnr, \tmp
6650 + b 1020f
6651 +1005:
6652 + /* get core number */
6653 + mrc p15, 0, \tmp, c0, c0, 5
6654 + ubfx \tmp, \tmp, #0, #2
6655 +
6656 + cmp \tmp, #1
6657 + beq 1020f
6658 + cmp \tmp, #2
6659 + beq 1020f
6660 + cmp \tmp, #3
6661 + beq 1020f
6662 +
6663 + /* get masked status */
6664 + ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
6665 + mov \irqnr, #(ARM_IRQ0_BASE + 31)
6666 + and \tmp, \irqstat, #0x300 @ save bits 8 and 9
6667 + /* clear bits 8 and 9, and test */
6668 + bics \irqstat, \irqstat, #0x300
6669 + bne 1010f
6670 +
6671 + tst \tmp, #0x100
6672 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
6673 + movne \irqnr, #(ARM_IRQ1_BASE + 31)
6674 + @ Mask out the interrupts also present in PEND0 - see SW-5809
6675 + bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
6676 + bicne \irqstat, #((1<<18) | (1<<19))
6677 + bne 1010f
6678 +
6679 + tst \tmp, #0x200
6680 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
6681 + movne \irqnr, #(ARM_IRQ2_BASE + 31)
6682 + @ Mask out the interrupts also present in PEND0 - see SW-5809
6683 + bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
6684 + bicne \irqstat, #((1<<30))
6685 + beq 1020f
6686 +
6687 +1010:
6688 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
6689 + @ N.B. CLZ is an ARM5 instruction.
6690 + sub \tmp, \irqstat, #1
6691 + eor \irqstat, \irqstat, \tmp
6692 + clz \tmp, \irqstat
6693 + sub \irqnr, \tmp
6694 +
6695 +1020: @ EQ will be set if no irqs pending
6696 +
6697 + .endm
6698 +
6699 + .macro test_for_ipi, irqnr, irqstat, base, tmp
6700 + /* get core number */
6701 + mrc p15, 0, \tmp, c0, c0, 5
6702 + ubfx \tmp, \tmp, #0, #2
6703 + /* get core's mailbox interrupt control */
6704 + ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
6705 + add \irqstat, \irqstat, \tmp, lsl #4
6706 + ldr \tmp, [\irqstat]
6707 + cmp \tmp, #0
6708 + beq 1030f
6709 + clz \tmp, \tmp
6710 + rsb \irqnr, \tmp, #31
6711 + mov \tmp, #1
6712 + lsl \tmp, \irqnr
6713 + str \tmp, [\irqstat] @ clear interrupt source
6714 + dsb
6715 +1030: @ EQ will be set if no irqs pending
6716 + .endm
6717 --- /dev/null
6718 +++ b/arch/arm/mach-bcm2709/include/mach/frc.h
6719 @@ -0,0 +1,38 @@
6720 +/*
6721 + * arch/arm/mach-bcm2708/include/mach/timex.h
6722 + *
6723 + * BCM2708 free running counter (timer)
6724 + *
6725 + * Copyright (C) 2010 Broadcom
6726 + *
6727 + * This program is free software; you can redistribute it and/or modify
6728 + * it under the terms of the GNU General Public License as published by
6729 + * the Free Software Foundation; either version 2 of the License, or
6730 + * (at your option) any later version.
6731 + *
6732 + * This program is distributed in the hope that it will be useful,
6733 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6734 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6735 + * GNU General Public License for more details.
6736 + *
6737 + * You should have received a copy of the GNU General Public License
6738 + * along with this program; if not, write to the Free Software
6739 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6740 + */
6741 +
6742 +#ifndef _MACH_FRC_H
6743 +#define _MACH_FRC_H
6744 +
6745 +#define FRC_TICK_RATE (1000000)
6746 +
6747 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
6748 + (slightly faster than frc_clock_ticks63()
6749 + */
6750 +extern unsigned long frc_clock_ticks32(void);
6751 +
6752 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
6753 + * Note - top bit should be ignored (see cnt32_to_63)
6754 + */
6755 +extern unsigned long long frc_clock_ticks63(void);
6756 +
6757 +#endif
6758 --- /dev/null
6759 +++ b/arch/arm/mach-bcm2709/include/mach/gpio.h
6760 @@ -0,0 +1,17 @@
6761 +/*
6762 + * arch/arm/mach-bcm2708/include/mach/gpio.h
6763 + *
6764 + * This file is licensed under the terms of the GNU General Public
6765 + * License version 2. This program is licensed "as is" without any
6766 + * warranty of any kind, whether express or implied.
6767 + */
6768 +
6769 +#ifndef __ASM_ARCH_GPIO_H
6770 +#define __ASM_ARCH_GPIO_H
6771 +
6772 +#define BCM2708_NR_GPIOS 54 // number of gpio lines
6773 +
6774 +#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
6775 +#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
6776 +
6777 +#endif
6778 --- /dev/null
6779 +++ b/arch/arm/mach-bcm2709/include/mach/hardware.h
6780 @@ -0,0 +1,28 @@
6781 +/*
6782 + * arch/arm/mach-bcm2708/include/mach/hardware.h
6783 + *
6784 + * This file contains the hardware definitions of the BCM2708 devices.
6785 + *
6786 + * Copyright (C) 2010 Broadcom
6787 + *
6788 + * This program is free software; you can redistribute it and/or modify
6789 + * it under the terms of the GNU General Public License as published by
6790 + * the Free Software Foundation; either version 2 of the License, or
6791 + * (at your option) any later version.
6792 + *
6793 + * This program is distributed in the hope that it will be useful,
6794 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6795 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6796 + * GNU General Public License for more details.
6797 + *
6798 + * You should have received a copy of the GNU General Public License
6799 + * along with this program; if not, write to the Free Software
6800 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6801 + */
6802 +#ifndef __ASM_ARCH_HARDWARE_H
6803 +#define __ASM_ARCH_HARDWARE_H
6804 +
6805 +#include <asm/sizes.h>
6806 +#include <mach/platform.h>
6807 +
6808 +#endif
6809 --- /dev/null
6810 +++ b/arch/arm/mach-bcm2709/include/mach/io.h
6811 @@ -0,0 +1,27 @@
6812 +/*
6813 + * arch/arm/mach-bcm2708/include/mach/io.h
6814 + *
6815 + * Copyright (C) 2003 ARM Limited
6816 + *
6817 + * This program is free software; you can redistribute it and/or modify
6818 + * it under the terms of the GNU General Public License as published by
6819 + * the Free Software Foundation; either version 2 of the License, or
6820 + * (at your option) any later version.
6821 + *
6822 + * This program is distributed in the hope that it will be useful,
6823 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6824 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6825 + * GNU General Public License for more details.
6826 + *
6827 + * You should have received a copy of the GNU General Public License
6828 + * along with this program; if not, write to the Free Software
6829 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6830 + */
6831 +#ifndef __ASM_ARM_ARCH_IO_H
6832 +#define __ASM_ARM_ARCH_IO_H
6833 +
6834 +#define IO_SPACE_LIMIT 0xffffffff
6835 +
6836 +#define __io(a) __typesafe_io(a)
6837 +
6838 +#endif
6839 --- /dev/null
6840 +++ b/arch/arm/mach-bcm2709/include/mach/irqs.h
6841 @@ -0,0 +1,225 @@
6842 +/*
6843 + * arch/arm/mach-bcm2708/include/mach/irqs.h
6844 + *
6845 + * Copyright (C) 2010 Broadcom
6846 + * Copyright (C) 2003 ARM Limited
6847 + * Copyright (C) 2000 Deep Blue Solutions Ltd.
6848 + *
6849 + * This program is free software; you can redistribute it and/or modify
6850 + * it under the terms of the GNU General Public License as published by
6851 + * the Free Software Foundation; either version 2 of the License, or
6852 + * (at your option) any later version.
6853 + *
6854 + * This program is distributed in the hope that it will be useful,
6855 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6856 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6857 + * GNU General Public License for more details.
6858 + *
6859 + * You should have received a copy of the GNU General Public License
6860 + * along with this program; if not, write to the Free Software
6861 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6862 + */
6863 +
6864 +#ifndef _BCM2708_IRQS_H_
6865 +#define _BCM2708_IRQS_H_
6866 +
6867 +#include <mach/platform.h>
6868 +
6869 +/*
6870 + * IRQ interrupts definitions are the same as the INT definitions
6871 + * held within platform.h
6872 + */
6873 +#define IRQ_ARMCTRL_START 0
6874 +#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
6875 +#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
6876 +#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
6877 +#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
6878 +#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
6879 +#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
6880 +#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
6881 +#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
6882 +#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
6883 +#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
6884 +#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
6885 +#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
6886 +#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
6887 +#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
6888 +#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
6889 +#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
6890 +#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
6891 +#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
6892 +#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
6893 +#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
6894 +#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
6895 +#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
6896 +#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
6897 +#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
6898 +#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
6899 +#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
6900 +#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
6901 +#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
6902 +#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
6903 +#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
6904 +#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
6905 +#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
6906 +#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
6907 +#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
6908 +#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
6909 +#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
6910 +#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
6911 +#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
6912 +#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
6913 +#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
6914 +#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
6915 +#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
6916 +#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
6917 +#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
6918 +#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
6919 +#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
6920 +#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
6921 +#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
6922 +#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
6923 +#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
6924 +#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
6925 +#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
6926 +#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
6927 +#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
6928 +#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
6929 +#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
6930 +#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
6931 +#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
6932 +#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
6933 +#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
6934 +#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
6935 +#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
6936 +#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
6937 +#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
6938 +
6939 +#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
6940 +#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
6941 +#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
6942 +#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
6943 +#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
6944 +#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
6945 +#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
6946 +#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
6947 +#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
6948 +#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
6949 +
6950 +#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ)
6951 +#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ)
6952 +#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ)
6953 +#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ)
6954 +#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0)
6955 +#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1)
6956 +#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2)
6957 +#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3)
6958 +#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST)
6959 +#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST)
6960 +#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO)
6961 +#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER)
6962 +
6963 +#define FIQ_START HARD_IRQS
6964 +
6965 +/*
6966 + * FIQ interrupts definitions are the same as the INT definitions.
6967 + */
6968 +#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0)
6969 +#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1)
6970 +#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2)
6971 +#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3)
6972 +#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0)
6973 +#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1)
6974 +#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2)
6975 +#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG)
6976 +#define FIQ_ISP (FIQ_START+INTERRUPT_ISP)
6977 +#define FIQ_USB (FIQ_START+INTERRUPT_USB)
6978 +#define FIQ_3D (FIQ_START+INTERRUPT_3D)
6979 +#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER)
6980 +#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0)
6981 +#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1)
6982 +#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2)
6983 +#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3)
6984 +#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0)
6985 +#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1)
6986 +#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2)
6987 +#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3)
6988 +#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4)
6989 +#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5)
6990 +#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6)
6991 +#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7)
6992 +#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8)
6993 +#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9)
6994 +#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10)
6995 +#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11)
6996 +#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12)
6997 +#define FIQ_AUX (FIQ_START+INTERRUPT_AUX)
6998 +#define FIQ_ARM (FIQ_START+INTERRUPT_ARM)
6999 +#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA)
7000 +#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT)
7001 +#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER)
7002 +#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX)
7003 +#define FIQ_SDC (FIQ_START+INTERRUPT_SDC)
7004 +#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0)
7005 +#define FIQ_AVE (FIQ_START+INTERRUPT_AVE)
7006 +#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0)
7007 +#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1)
7008 +#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0)
7009 +#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1)
7010 +#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1)
7011 +#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV)
7012 +#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1)
7013 +#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0)
7014 +#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1)
7015 +#define FIQ_CPR (FIQ_START+INTERRUPT_CPR)
7016 +#define FIQ_SMI (FIQ_START+INTERRUPT_SMI)
7017 +#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0)
7018 +#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1)
7019 +#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2)
7020 +#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3)
7021 +#define FIQ_I2C (FIQ_START+INTERRUPT_I2C)
7022 +#define FIQ_SPI (FIQ_START+INTERRUPT_SPI)
7023 +#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM)
7024 +#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO)
7025 +#define FIQ_UART (FIQ_START+INTERRUPT_UART)
7026 +#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS)
7027 +#define FIQ_VEC (FIQ_START+INTERRUPT_VEC)
7028 +#define FIQ_CPG (FIQ_START+INTERRUPT_CPG)
7029 +#define FIQ_RNG (FIQ_START+INTERRUPT_RNG)
7030 +#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO)
7031 +#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON)
7032 +
7033 +#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER)
7034 +#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX)
7035 +#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0)
7036 +#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1)
7037 +#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED)
7038 +#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED)
7039 +#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0)
7040 +#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1)
7041 +#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1)
7042 +#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2)
7043 +
7044 +#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ)
7045 +#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ)
7046 +#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ)
7047 +#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ)
7048 +#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0)
7049 +#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1)
7050 +#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2)
7051 +#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3)
7052 +#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST)
7053 +#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST)
7054 +#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO)
7055 +#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER)
7056 +
7057 +#define HARD_IRQS (128)
7058 +#define FIQ_IRQS (128)
7059 +#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS)
7060 +#define GPIO_IRQS (32*5)
7061 +#define SPARE_ALLOC_IRQS 32
7062 +#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS)
7063 +#define FREE_IRQS 32
7064 +#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS)
7065 +
7066 +#endif /* _BCM2708_IRQS_H_ */
7067 --- /dev/null
7068 +++ b/arch/arm/mach-bcm2709/include/mach/memory.h
7069 @@ -0,0 +1,57 @@
7070 +/*
7071 + * arch/arm/mach-bcm2708/include/mach/memory.h
7072 + *
7073 + * Copyright (C) 2010 Broadcom
7074 + *
7075 + * This program is free software; you can redistribute it and/or modify
7076 + * it under the terms of the GNU General Public License as published by
7077 + * the Free Software Foundation; either version 2 of the License, or
7078 + * (at your option) any later version.
7079 + *
7080 + * This program is distributed in the hope that it will be useful,
7081 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7082 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7083 + * GNU General Public License for more details.
7084 + *
7085 + * You should have received a copy of the GNU General Public License
7086 + * along with this program; if not, write to the Free Software
7087 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7088 + */
7089 +#ifndef __ASM_ARCH_MEMORY_H
7090 +#define __ASM_ARCH_MEMORY_H
7091 +
7092 +/* Memory overview:
7093 +
7094 + [ARMcore] <--virtual addr-->
7095 + [ARMmmu] <--physical addr-->
7096 + [GERTmap] <--bus add-->
7097 + [VCperiph]
7098 +
7099 +*/
7100 +
7101 +/*
7102 + * Physical DRAM offset.
7103 + */
7104 +#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
7105 +#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
7106 +
7107 +#ifdef CONFIG_BCM2708_NOL2CACHE
7108 + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
7109 +#else
7110 + #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
7111 +#endif
7112 +
7113 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
7114 + * will provide the offset into this area as well as setting the bits that
7115 + * stop the L1 and L2 cache from being used
7116 + *
7117 + * WARNING: this only works because the ARM is given memory at a fixed location
7118 + * (ARMMEM_OFFSET)
7119 + */
7120 +#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
7121 +#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
7122 +#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
7123 +#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
7124 +#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
7125 +
7126 +#endif
7127 --- /dev/null
7128 +++ b/arch/arm/mach-bcm2709/include/mach/platform.h
7129 @@ -0,0 +1,225 @@
7130 +/*
7131 + * arch/arm/mach-bcm2708/include/mach/platform.h
7132 + *
7133 + * Copyright (C) 2010 Broadcom
7134 + *
7135 + * This program is free software; you can redistribute it and/or modify
7136 + * it under the terms of the GNU General Public License as published by
7137 + * the Free Software Foundation; either version 2 of the License, or
7138 + * (at your option) any later version.
7139 + *
7140 + * This program is distributed in the hope that it will be useful,
7141 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7142 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7143 + * GNU General Public License for more details.
7144 + *
7145 + * You should have received a copy of the GNU General Public License
7146 + * along with this program; if not, write to the Free Software
7147 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7148 + */
7149 +
7150 +#ifndef _BCM2708_PLATFORM_H
7151 +#define _BCM2708_PLATFORM_H
7152 +
7153 +
7154 +/* macros to get at IO space when running virtually */
7155 +#define IO_ADDRESS(x) (((x) & 0x00ffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
7156 +
7157 +#define __io_address(n) IOMEM(IO_ADDRESS(n))
7158 +
7159 +
7160 +/*
7161 + * SDRAM
7162 + */
7163 +#define BCM2708_SDRAM_BASE 0x00000000
7164 +
7165 +/*
7166 + * Logic expansion modules
7167 + *
7168 + */
7169 +
7170 +
7171 +/* ------------------------------------------------------------------------
7172 + * BCM2708 ARMCTRL Registers
7173 + * ------------------------------------------------------------------------
7174 + */
7175 +
7176 +#define HW_REGISTER_RW(addr) (addr)
7177 +#define HW_REGISTER_RO(addr) (addr)
7178 +
7179 +#include "arm_control.h"
7180 +#undef ARM_BASE
7181 +
7182 +/*
7183 + * Definitions and addresses for the ARM CONTROL logic
7184 + * This file is manually generated.
7185 + */
7186 +
7187 +#define BCM2708_PERI_BASE 0x3F000000
7188 +#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
7189 +#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
7190 +#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
7191 +#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
7192 +#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
7193 +#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
7194 +#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
7195 +#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
7196 +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
7197 +#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
7198 +#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
7199 +#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
7200 +#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
7201 +#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
7202 +#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
7203 +#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
7204 +#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
7205 +#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
7206 +#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
7207 +#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
7208 +
7209 +#define ARMCTRL_BASE (ARM_BASE + 0x000)
7210 +#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
7211 +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
7212 +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
7213 +
7214 +
7215 +/*
7216 + * Interrupt assignments
7217 + */
7218 +
7219 +#define ARM_IRQ1_BASE 0
7220 +#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
7221 +#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
7222 +#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
7223 +#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
7224 +#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
7225 +#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
7226 +#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
7227 +#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
7228 +#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
7229 +#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
7230 +#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
7231 +#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
7232 +#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
7233 +#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
7234 +#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
7235 +#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
7236 +#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
7237 +#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
7238 +#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
7239 +#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
7240 +#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
7241 +#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
7242 +#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
7243 +#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
7244 +#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
7245 +#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
7246 +#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
7247 +#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
7248 +#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
7249 +#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
7250 +#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
7251 +#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
7252 +
7253 +#define ARM_IRQ2_BASE 32
7254 +#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
7255 +#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
7256 +#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
7257 +#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
7258 +#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
7259 +#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
7260 +#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
7261 +#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
7262 +#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
7263 +#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
7264 +#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
7265 +#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
7266 +#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
7267 +#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
7268 +#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
7269 +#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
7270 +#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
7271 +#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
7272 +#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
7273 +#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
7274 +#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
7275 +#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
7276 +#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
7277 +#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
7278 +#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
7279 +#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
7280 +#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
7281 +#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
7282 +#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
7283 +#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
7284 +#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
7285 +#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
7286 +
7287 +#define ARM_IRQ0_BASE 64
7288 +#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
7289 +#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
7290 +#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
7291 +#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
7292 +#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
7293 +#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
7294 +#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
7295 +#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
7296 +#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
7297 +#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
7298 +#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
7299 +#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
7300 +#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
7301 +#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
7302 +#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
7303 +#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
7304 +#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
7305 +#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
7306 +#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
7307 +#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
7308 +#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
7309 +
7310 +#define ARM_IRQ_LOCAL_BASE 96
7311 +#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0)
7312 +#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1)
7313 +#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2)
7314 +#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3)
7315 +#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4)
7316 +#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5)
7317 +#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6)
7318 +#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7)
7319 +#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8)
7320 +#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9)
7321 +#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10)
7322 +#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11)
7323 +
7324 +/*
7325 + * Watchdog
7326 + */
7327 +#define PM_RSTC (PM_BASE+0x1c)
7328 +#define PM_RSTS (PM_BASE+0x20)
7329 +#define PM_WDOG (PM_BASE+0x24)
7330 +
7331 +#define PM_WDOG_RESET 0000000000
7332 +#define PM_PASSWORD 0x5a000000
7333 +#define PM_WDOG_TIME_SET 0x000fffff
7334 +#define PM_RSTC_WRCFG_CLR 0xffffffcf
7335 +#define PM_RSTC_WRCFG_SET 0x00000030
7336 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
7337 +#define PM_RSTC_RESET 0x00000102
7338 +
7339 +#define PM_RSTS_HADPOR_SET 0x00001000
7340 +#define PM_RSTS_HADSRH_SET 0x00000400
7341 +#define PM_RSTS_HADSRF_SET 0x00000200
7342 +#define PM_RSTS_HADSRQ_SET 0x00000100
7343 +#define PM_RSTS_HADWRH_SET 0x00000040
7344 +#define PM_RSTS_HADWRF_SET 0x00000020
7345 +#define PM_RSTS_HADWRQ_SET 0x00000010
7346 +#define PM_RSTS_HADDRH_SET 0x00000004
7347 +#define PM_RSTS_HADDRF_SET 0x00000002
7348 +#define PM_RSTS_HADDRQ_SET 0x00000001
7349 +
7350 +#define UART0_CLOCK 3000000
7351 +
7352 +#endif
7353 +
7354 +/* END */
7355 --- /dev/null
7356 +++ b/arch/arm/mach-bcm2709/include/mach/power.h
7357 @@ -0,0 +1,26 @@
7358 +/*
7359 + * linux/arch/arm/mach-bcm2708/power.h
7360 + *
7361 + * Copyright (C) 2010 Broadcom
7362 + *
7363 + * This program is free software; you can redistribute it and/or modify
7364 + * it under the terms of the GNU General Public License version 2 as
7365 + * published by the Free Software Foundation.
7366 + *
7367 + * This device provides a shared mechanism for controlling the power to
7368 + * VideoCore subsystems.
7369 + */
7370 +
7371 +#ifndef _MACH_BCM2708_POWER_H
7372 +#define _MACH_BCM2708_POWER_H
7373 +
7374 +#include <linux/types.h>
7375 +#include <mach/arm_power.h>
7376 +
7377 +typedef unsigned int BCM_POWER_HANDLE_T;
7378 +
7379 +extern int bcm_power_open(BCM_POWER_HANDLE_T *handle);
7380 +extern int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request);
7381 +extern int bcm_power_close(BCM_POWER_HANDLE_T handle);
7382 +
7383 +#endif
7384 --- /dev/null
7385 +++ b/arch/arm/mach-bcm2709/include/mach/system.h
7386 @@ -0,0 +1,38 @@
7387 +/*
7388 + * arch/arm/mach-bcm2708/include/mach/system.h
7389 + *
7390 + * Copyright (C) 2010 Broadcom
7391 + * Copyright (C) 2003 ARM Limited
7392 + * Copyright (C) 2000 Deep Blue Solutions Ltd
7393 + *
7394 + * This program is free software; you can redistribute it and/or modify
7395 + * it under the terms of the GNU General Public License as published by
7396 + * the Free Software Foundation; either version 2 of the License, or
7397 + * (at your option) any later version.
7398 + *
7399 + * This program is distributed in the hope that it will be useful,
7400 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7401 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7402 + * GNU General Public License for more details.
7403 + *
7404 + * You should have received a copy of the GNU General Public License
7405 + * along with this program; if not, write to the Free Software
7406 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7407 + */
7408 +#ifndef __ASM_ARCH_SYSTEM_H
7409 +#define __ASM_ARCH_SYSTEM_H
7410 +
7411 +#include <linux/io.h>
7412 +#include <mach/hardware.h>
7413 +#include <mach/platform.h>
7414 +
7415 +static inline void arch_idle(void)
7416 +{
7417 + /*
7418 + * This should do all the clock switching
7419 + * and wait for interrupt tricks
7420 + */
7421 + cpu_do_idle();
7422 +}
7423 +
7424 +#endif
7425 --- /dev/null
7426 +++ b/arch/arm/mach-bcm2709/include/mach/timex.h
7427 @@ -0,0 +1,23 @@
7428 +/*
7429 + * arch/arm/mach-bcm2708/include/mach/timex.h
7430 + *
7431 + * BCM2708 sysem clock frequency
7432 + *
7433 + * Copyright (C) 2010 Broadcom
7434 + *
7435 + * This program is free software; you can redistribute it and/or modify
7436 + * it under the terms of the GNU General Public License as published by
7437 + * the Free Software Foundation; either version 2 of the License, or
7438 + * (at your option) any later version.
7439 + *
7440 + * This program is distributed in the hope that it will be useful,
7441 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7442 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7443 + * GNU General Public License for more details.
7444 + *
7445 + * You should have received a copy of the GNU General Public License
7446 + * along with this program; if not, write to the Free Software
7447 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7448 + */
7449 +
7450 +#define CLOCK_TICK_RATE (1000000)
7451 --- /dev/null
7452 +++ b/arch/arm/mach-bcm2709/include/mach/uncompress.h
7453 @@ -0,0 +1,84 @@
7454 +/*
7455 + * arch/arm/mach-bcn2708/include/mach/uncompress.h
7456 + *
7457 + * Copyright (C) 2010 Broadcom
7458 + * Copyright (C) 2003 ARM Limited
7459 + *
7460 + * This program is free software; you can redistribute it and/or modify
7461 + * it under the terms of the GNU General Public License as published by
7462 + * the Free Software Foundation; either version 2 of the License, or
7463 + * (at your option) any later version.
7464 + *
7465 + * This program is distributed in the hope that it will be useful,
7466 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7467 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7468 + * GNU General Public License for more details.
7469 + *
7470 + * You should have received a copy of the GNU General Public License
7471 + * along with this program; if not, write to the Free Software
7472 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7473 + */
7474 +
7475 +#include <linux/io.h>
7476 +#include <linux/amba/serial.h>
7477 +#include <mach/hardware.h>
7478 +
7479 +#define UART_BAUD 115200
7480 +
7481 +#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
7482 +#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
7483 +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
7484 +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
7485 +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
7486 +#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
7487 +
7488 +/*
7489 + * This does not append a newline
7490 + */
7491 +static inline void putc(int c)
7492 +{
7493 + while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
7494 + barrier();
7495 +
7496 + __raw_writel(c, BCM2708_UART_DR);
7497 +}
7498 +
7499 +static inline void flush(void)
7500 +{
7501 + int fr;
7502 +
7503 + do {
7504 + fr = __raw_readl(BCM2708_UART_FR);
7505 + barrier();
7506 + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
7507 +}
7508 +
7509 +static inline void arch_decomp_setup(void)
7510 +{
7511 + int temp, div, rem, frac;
7512 +
7513 + temp = 16 * UART_BAUD;
7514 + div = UART0_CLOCK / temp;
7515 + rem = UART0_CLOCK % temp;
7516 + temp = (8 * rem) / UART_BAUD;
7517 + frac = (temp >> 1) + (temp & 1);
7518 +
7519 + /* Make sure the UART is disabled before we start */
7520 + __raw_writel(0, BCM2708_UART_CR);
7521 +
7522 + /* Set the baud rate */
7523 + __raw_writel(div, BCM2708_UART_IBRD);
7524 + __raw_writel(frac, BCM2708_UART_FBRD);
7525 +
7526 + /* Set the UART to 8n1, FIFO enabled */
7527 + __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
7528 +
7529 + /* Enable the UART */
7530 + __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
7531 + BCM2708_UART_CR);
7532 +}
7533 +
7534 +/*
7535 + * nothing to do
7536 + */
7537 +#define arch_decomp_wdog()
7538 --- /dev/null
7539 +++ b/arch/arm/mach-bcm2709/include/mach/vc_mem.h
7540 @@ -0,0 +1,35 @@
7541 +/*****************************************************************************
7542 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
7543 +*
7544 +* Unless you and Broadcom execute a separate written software license
7545 +* agreement governing use of this software, this software is licensed to you
7546 +* under the terms of the GNU General Public License version 2, available at
7547 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
7548 +*
7549 +* Notwithstanding the above, under no circumstances may you combine this
7550 +* software in any way with any other Broadcom software provided under a
7551 +* license other than the GPL, without Broadcom's express prior written
7552 +* consent.
7553 +*****************************************************************************/
7554 +
7555 +#if !defined( VC_MEM_H )
7556 +#define VC_MEM_H
7557 +
7558 +#include <linux/ioctl.h>
7559 +
7560 +#define VC_MEM_IOC_MAGIC 'v'
7561 +
7562 +#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
7563 +#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
7564 +#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
7565 +#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
7566 +
7567 +#if defined( __KERNEL__ )
7568 +#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
7569 +
7570 +extern unsigned long mm_vc_mem_phys_addr;
7571 +extern unsigned int mm_vc_mem_size;
7572 +extern int vc_mem_get_current_size( void );
7573 +#endif
7574 +
7575 +#endif /* VC_MEM_H */
7576 --- /dev/null
7577 +++ b/arch/arm/mach-bcm2709/include/mach/vc_support.h
7578 @@ -0,0 +1,69 @@
7579 +#ifndef _VC_SUPPORT_H_
7580 +#define _VC_SUPPORT_H_
7581 +
7582 +/*
7583 + * vc_support.h
7584 + *
7585 + * Created on: 25 Nov 2012
7586 + * Author: Simon
7587 + */
7588 +
7589 +enum {
7590 +/*
7591 + If a MEM_HANDLE_T is discardable, the memory manager may resize it to size
7592 + 0 at any time when it is not locked or retained.
7593 + */
7594 + MEM_FLAG_DISCARDABLE = 1 << 0,
7595 +
7596 + /*
7597 + If a MEM_HANDLE_T is allocating (or normal), its block of memory will be
7598 + accessed in an allocating fashion through the cache.
7599 + */
7600 + MEM_FLAG_NORMAL = 0 << 2,
7601 + MEM_FLAG_ALLOCATING = MEM_FLAG_NORMAL,
7602 +
7603 + /*
7604 + If a MEM_HANDLE_T is direct, its block of memory will be accessed
7605 + directly, bypassing the cache.
7606 + */
7607 + MEM_FLAG_DIRECT = 1 << 2,
7608 +
7609 + /*
7610 + If a MEM_HANDLE_T is coherent, its block of memory will be accessed in a
7611 + non-allocating fashion through the cache.
7612 + */
7613 + MEM_FLAG_COHERENT = 2 << 2,
7614 +
7615 + /*
7616 + If a MEM_HANDLE_T is L1-nonallocating, its block of memory will be accessed by
7617 + the VPU in a fashion which is allocating in L2, but only coherent in L1.
7618 + */
7619 + MEM_FLAG_L1_NONALLOCATING = (MEM_FLAG_DIRECT | MEM_FLAG_COHERENT),
7620 +
7621 + /*
7622 + If a MEM_HANDLE_T is zero'd, its contents are set to 0 rather than
7623 + MEM_HANDLE_INVALID on allocation and resize up.
7624 + */
7625 + MEM_FLAG_ZERO = 1 << 4,
7626 +
7627 + /*
7628 + If a MEM_HANDLE_T is uninitialised, it will not be reset to a defined value
7629 + (either zero, or all 1's) on allocation.
7630 + */
7631 + MEM_FLAG_NO_INIT = 1 << 5,
7632 +
7633 + /*
7634 + Hints.
7635 + */
7636 + MEM_FLAG_HINT_PERMALOCK = 1 << 6, /* Likely to be locked for long periods of time. */
7637 +};
7638 +
7639 +unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags);
7640 +unsigned int ReleaseVcMemory(unsigned int handle);
7641 +unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle);
7642 +unsigned int UnlockVcMemory(unsigned int handle);
7643 +
7644 +unsigned int ExecuteVcCode(unsigned int code,
7645 + unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5);
7646 +
7647 +#endif
7648 --- /dev/null
7649 +++ b/arch/arm/mach-bcm2709/include/mach/vcio.h
7650 @@ -0,0 +1,165 @@
7651 +/*
7652 + * arch/arm/mach-bcm2708/include/mach/vcio.h
7653 + *
7654 + * Copyright (C) 2010 Broadcom
7655 + *
7656 + * This program is free software; you can redistribute it and/or modify
7657 + * it under the terms of the GNU General Public License as published by
7658 + * the Free Software Foundation; either version 2 of the License, or
7659 + * (at your option) any later version.
7660 + *
7661 + * This program is distributed in the hope that it will be useful,
7662 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7663 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7664 + * GNU General Public License for more details.
7665 + *
7666 + * You should have received a copy of the GNU General Public License
7667 + * along with this program; if not, write to the Free Software
7668 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7669 + */
7670 +#ifndef _MACH_BCM2708_VCIO_H
7671 +#define _MACH_BCM2708_VCIO_H
7672 +
7673 +/* Routines to handle I/O via the VideoCore "ARM control" registers
7674 + * (semaphores, doorbells, mailboxes)
7675 + */
7676 +
7677 +#define BCM_VCIO_DRIVER_NAME "bcm2708_vcio"
7678 +
7679 +/* Constants shared with the ARM identifying separate mailbox channels */
7680 +#define MBOX_CHAN_POWER 0 /* for use by the power management interface */
7681 +#define MBOX_CHAN_FB 1 /* for use by the frame buffer */
7682 +#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */
7683 +#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
7684 +#define MBOX_CHAN_COUNT 9
7685 +
7686 +enum {
7687 + VCMSG_PROCESS_REQUEST = 0x00000000
7688 +};
7689 +enum {
7690 + VCMSG_REQUEST_SUCCESSFUL = 0x80000000,
7691 + VCMSG_REQUEST_FAILED = 0x80000001
7692 +};
7693 +/* Mailbox property tags */
7694 +enum {
7695 + VCMSG_PROPERTY_END = 0x00000000,
7696 + VCMSG_GET_FIRMWARE_REVISION = 0x00000001,
7697 + VCMSG_GET_BOARD_MODEL = 0x00010001,
7698 + VCMSG_GET_BOARD_REVISION = 0x00010002,
7699 + VCMSG_GET_BOARD_MAC_ADDRESS = 0x00010003,
7700 + VCMSG_GET_BOARD_SERIAL = 0x00010004,
7701 + VCMSG_GET_ARM_MEMORY = 0x00010005,
7702 + VCMSG_GET_VC_MEMORY = 0x00010006,
7703 + VCMSG_GET_CLOCKS = 0x00010007,
7704 + VCMSG_GET_COMMAND_LINE = 0x00050001,
7705 + VCMSG_GET_DMA_CHANNELS = 0x00060001,
7706 + VCMSG_GET_POWER_STATE = 0x00020001,
7707 + VCMSG_GET_TIMING = 0x00020002,
7708 + VCMSG_SET_POWER_STATE = 0x00028001,
7709 + VCMSG_GET_CLOCK_STATE = 0x00030001,
7710 + VCMSG_SET_CLOCK_STATE = 0x00038001,
7711 + VCMSG_GET_CLOCK_RATE = 0x00030002,
7712 + VCMSG_SET_CLOCK_RATE = 0x00038002,
7713 + VCMSG_GET_VOLTAGE = 0x00030003,
7714 + VCMSG_SET_VOLTAGE = 0x00038003,
7715 + VCMSG_GET_MAX_CLOCK = 0x00030004,
7716 + VCMSG_GET_MAX_VOLTAGE = 0x00030005,
7717 + VCMSG_GET_TEMPERATURE = 0x00030006,
7718 + VCMSG_GET_MIN_CLOCK = 0x00030007,
7719 + VCMSG_GET_MIN_VOLTAGE = 0x00030008,
7720 + VCMSG_GET_TURBO = 0x00030009,
7721 + VCMSG_GET_MAX_TEMPERATURE = 0x0003000a,
7722 + VCMSG_GET_STC = 0x0003000b,
7723 + VCMSG_SET_TURBO = 0x00038009,
7724 + VCMSG_SET_ALLOCATE_MEM = 0x0003000c,
7725 + VCMSG_SET_LOCK_MEM = 0x0003000d,
7726 + VCMSG_SET_UNLOCK_MEM = 0x0003000e,
7727 + VCMSG_SET_RELEASE_MEM = 0x0003000f,
7728 + VCMSG_SET_EXECUTE_CODE = 0x00030010,
7729 + VCMSG_SET_EXECUTE_QPU = 0x00030011,
7730 + VCMSG_SET_ENABLE_QPU = 0x00030012,
7731 + VCMSG_GET_RESOURCE_HANDLE = 0x00030014,
7732 + VCMSG_GET_EDID_BLOCK = 0x00030020,
7733 + VCMSG_GET_CUSTOMER_OTP = 0x00030021,
7734 + VCMSG_SET_CUSTOMER_OTP = 0x00038021,
7735 + VCMSG_SET_ALLOCATE_BUFFER = 0x00040001,
7736 + VCMSG_SET_RELEASE_BUFFER = 0x00048001,
7737 + VCMSG_SET_BLANK_SCREEN = 0x00040002,
7738 + VCMSG_TST_BLANK_SCREEN = 0x00044002,
7739 + VCMSG_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003,
7740 + VCMSG_TST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,
7741 + VCMSG_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003,
7742 + VCMSG_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004,
7743 + VCMSG_TST_VIRTUAL_WIDTH_HEIGHT = 0x00044004,
7744 + VCMSG_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004,
7745 + VCMSG_GET_DEPTH = 0x00040005,
7746 + VCMSG_TST_DEPTH = 0x00044005,
7747 + VCMSG_SET_DEPTH = 0x00048005,
7748 + VCMSG_GET_PIXEL_ORDER = 0x00040006,
7749 + VCMSG_TST_PIXEL_ORDER = 0x00044006,
7750 + VCMSG_SET_PIXEL_ORDER = 0x00048006,
7751 + VCMSG_GET_ALPHA_MODE = 0x00040007,
7752 + VCMSG_TST_ALPHA_MODE = 0x00044007,
7753 + VCMSG_SET_ALPHA_MODE = 0x00048007,
7754 + VCMSG_GET_PITCH = 0x00040008,
7755 + VCMSG_TST_PITCH = 0x00044008,
7756 + VCMSG_SET_PITCH = 0x00048008,
7757 + VCMSG_GET_VIRTUAL_OFFSET = 0x00040009,
7758 + VCMSG_TST_VIRTUAL_OFFSET = 0x00044009,
7759 + VCMSG_SET_VIRTUAL_OFFSET = 0x00048009,
7760 + VCMSG_GET_OVERSCAN = 0x0004000a,
7761 + VCMSG_TST_OVERSCAN = 0x0004400a,
7762 + VCMSG_SET_OVERSCAN = 0x0004800a,
7763 + VCMSG_GET_PALETTE = 0x0004000b,
7764 + VCMSG_TST_PALETTE = 0x0004400b,
7765 + VCMSG_SET_PALETTE = 0x0004800b,
7766 + VCMSG_GET_LAYER = 0x0004000c,
7767 + VCMSG_TST_LAYER = 0x0004400c,
7768 + VCMSG_SET_LAYER = 0x0004800c,
7769 + VCMSG_GET_TRANSFORM = 0x0004000d,
7770 + VCMSG_TST_TRANSFORM = 0x0004400d,
7771 + VCMSG_SET_TRANSFORM = 0x0004800d,
7772 + VCMSG_TST_VSYNC = 0x0004400e,
7773 + VCMSG_SET_VSYNC = 0x0004800e,
7774 + VCMSG_SET_CURSOR_INFO = 0x00008010,
7775 + VCMSG_SET_CURSOR_STATE = 0x00008011,
7776 +};
7777 +
7778 +extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28);
7779 +extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28);
7780 +extern int /*rc*/ bcm_mailbox_property(void *data, int size);
7781 +
7782 +#include <linux/ioctl.h>
7783 +
7784 +/*
7785 + * The major device number. We can't rely on dynamic
7786 + * registration any more, because ioctls need to know
7787 + * it.
7788 + */
7789 +#define MAJOR_NUM 100
7790 +
7791 +/*
7792 + * Set the message of the device driver
7793 + */
7794 +#define IOCTL_MBOX_PROPERTY _IOWR(MAJOR_NUM, 0, char *)
7795 +/*
7796 + * _IOWR means that we're creating an ioctl command
7797 + * number for passing information from a user process
7798 + * to the kernel module and from the kernel module to user process
7799 + *
7800 + * The first arguments, MAJOR_NUM, is the major device
7801 + * number we're using.
7802 + *
7803 + * The second argument is the number of the command
7804 + * (there could be several with different meanings).
7805 + *
7806 + * The third argument is the type we want to get from
7807 + * the process to the kernel.
7808 + */
7809 +
7810 +/*
7811 + * The name of the device file
7812 + */
7813 +#define DEVICE_FILE_NAME "vcio"
7814 +
7815 +#endif
7816 --- /dev/null
7817 +++ b/arch/arm/mach-bcm2709/include/mach/vmalloc.h
7818 @@ -0,0 +1,20 @@
7819 +/*
7820 + * arch/arm/mach-bcm2708/include/mach/vmalloc.h
7821 + *
7822 + * Copyright (C) 2010 Broadcom
7823 + *
7824 + * This program is free software; you can redistribute it and/or modify
7825 + * it under the terms of the GNU General Public License as published by
7826 + * the Free Software Foundation; either version 2 of the License, or
7827 + * (at your option) any later version.
7828 + *
7829 + * This program is distributed in the hope that it will be useful,
7830 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7831 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7832 + * GNU General Public License for more details.
7833 + *
7834 + * You should have received a copy of the GNU General Public License
7835 + * along with this program; if not, write to the Free Software
7836 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7837 + */
7838 +#define VMALLOC_END (0xff000000)
7839 --- /dev/null
7840 +++ b/arch/arm/mach-bcm2709/power.c
7841 @@ -0,0 +1,195 @@
7842 +/*
7843 + * linux/arch/arm/mach-bcm2708/power.c
7844 + *
7845 + * Copyright (C) 2010 Broadcom
7846 + *
7847 + * This program is free software; you can redistribute it and/or modify
7848 + * it under the terms of the GNU General Public License version 2 as
7849 + * published by the Free Software Foundation.
7850 + *
7851 + * This device provides a shared mechanism for controlling the power to
7852 + * VideoCore subsystems.
7853 + */
7854 +
7855 +#include <linux/module.h>
7856 +#include <linux/semaphore.h>
7857 +#include <linux/bug.h>
7858 +#include <mach/power.h>
7859 +#include <mach/vcio.h>
7860 +#include <mach/arm_power.h>
7861 +
7862 +#define DRIVER_NAME "bcm2708_power"
7863 +
7864 +#define BCM_POWER_MAXCLIENTS 4
7865 +#define BCM_POWER_NOCLIENT (1<<31)
7866 +
7867 +/* Some drivers expect there devices to be permanently powered */
7868 +#ifdef CONFIG_USB
7869 +#define BCM_POWER_ALWAYS_ON (BCM_POWER_USB)
7870 +#endif
7871 +
7872 +#if 1
7873 +#define DPRINTK printk
7874 +#else
7875 +#define DPRINTK if (0) printk
7876 +#endif
7877 +
7878 +struct state_struct {
7879 + uint32_t global_request;
7880 + uint32_t client_request[BCM_POWER_MAXCLIENTS];
7881 + struct semaphore client_mutex;
7882 + struct semaphore mutex;
7883 +} g_state;
7884 +
7885 +int bcm_power_open(BCM_POWER_HANDLE_T *handle)
7886 +{
7887 + BCM_POWER_HANDLE_T i;
7888 + int ret = -EBUSY;
7889 +
7890 + down(&g_state.client_mutex);
7891 +
7892 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
7893 + if (g_state.client_request[i] == BCM_POWER_NOCLIENT) {
7894 + g_state.client_request[i] = BCM_POWER_NONE;
7895 + *handle = i;
7896 + ret = 0;
7897 + break;
7898 + }
7899 + }
7900 +
7901 + up(&g_state.client_mutex);
7902 +
7903 + DPRINTK("bcm_power_open() -> %d\n", *handle);
7904 +
7905 + return ret;
7906 +}
7907 +EXPORT_SYMBOL_GPL(bcm_power_open);
7908 +
7909 +int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request)
7910 +{
7911 + int rc = 0;
7912 +
7913 + DPRINTK("bcm_power_request(%d, %x)\n", handle, request);
7914 +
7915 + if ((handle < BCM_POWER_MAXCLIENTS) &&
7916 + (g_state.client_request[handle] != BCM_POWER_NOCLIENT)) {
7917 + if (down_interruptible(&g_state.mutex) != 0) {
7918 + DPRINTK("bcm_power_request -> interrupted\n");
7919 + return -EINTR;
7920 + }
7921 +
7922 + if (request != g_state.client_request[handle]) {
7923 + uint32_t others_request = 0;
7924 + uint32_t global_request;
7925 + BCM_POWER_HANDLE_T i;
7926 +
7927 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
7928 + if (i != handle)
7929 + others_request |=
7930 + g_state.client_request[i];
7931 + }
7932 + others_request &= ~BCM_POWER_NOCLIENT;
7933 +
7934 + global_request = request | others_request;
7935 + if (global_request != g_state.global_request) {
7936 + uint32_t actual;
7937 +
7938 + /* Send a request to VideoCore */
7939 + bcm_mailbox_write(MBOX_CHAN_POWER,
7940 + global_request << 4);
7941 +
7942 + /* Wait for a response during power-up */
7943 + if (global_request & ~g_state.global_request) {
7944 + rc = bcm_mailbox_read(MBOX_CHAN_POWER,
7945 + &actual);
7946 + DPRINTK
7947 + ("bcm_mailbox_read -> %08x, %d\n",
7948 + actual, rc);
7949 + actual >>= 4;
7950 + } else {
7951 + rc = 0;
7952 + actual = global_request;
7953 + }
7954 +
7955 + if (rc == 0) {
7956 + if (actual != global_request) {
7957 + printk(KERN_ERR
7958 + "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n",
7959 + __func__,
7960 + g_state.global_request,
7961 + global_request, actual, request, others_request);
7962 + /* A failure */
7963 + BUG_ON((others_request & actual)
7964 + != others_request);
7965 + request &= actual;
7966 + rc = -EIO;
7967 + }
7968 +
7969 + g_state.global_request = actual;
7970 + g_state.client_request[handle] =
7971 + request;
7972 + }
7973 + }
7974 + }
7975 + up(&g_state.mutex);
7976 + } else {
7977 + rc = -EINVAL;
7978 + }
7979 + DPRINTK("bcm_power_request -> %d\n", rc);
7980 + return rc;
7981 +}
7982 +EXPORT_SYMBOL_GPL(bcm_power_request);
7983 +
7984 +int bcm_power_close(BCM_POWER_HANDLE_T handle)
7985 +{
7986 + int rc;
7987 +
7988 + DPRINTK("bcm_power_close(%d)\n", handle);
7989 +
7990 + rc = bcm_power_request(handle, BCM_POWER_NONE);
7991 + if (rc == 0)
7992 + g_state.client_request[handle] = BCM_POWER_NOCLIENT;
7993 +
7994 + return rc;
7995 +}
7996 +EXPORT_SYMBOL_GPL(bcm_power_close);
7997 +
7998 +static int __init bcm_power_init(void)
7999 +{
8000 +#if defined(BCM_POWER_ALWAYS_ON)
8001 + BCM_POWER_HANDLE_T always_on_handle;
8002 +#endif
8003 + int rc = 0;
8004 + int i;
8005 +
8006 + printk(KERN_INFO "bcm_power: Broadcom power driver\n");
8007 + bcm_mailbox_write(MBOX_CHAN_POWER, 0);
8008 +
8009 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++)
8010 + g_state.client_request[i] = BCM_POWER_NOCLIENT;
8011 +
8012 + sema_init(&g_state.client_mutex, 1);
8013 + sema_init(&g_state.mutex, 1);
8014 +
8015 + g_state.global_request = 0;
8016 +#if defined(BCM_POWER_ALWAYS_ON)
8017 + if (BCM_POWER_ALWAYS_ON) {
8018 + bcm_power_open(&always_on_handle);
8019 + bcm_power_request(always_on_handle, BCM_POWER_ALWAYS_ON);
8020 + }
8021 +#endif
8022 +
8023 + return rc;
8024 +}
8025 +
8026 +static void __exit bcm_power_exit(void)
8027 +{
8028 + bcm_mailbox_write(MBOX_CHAN_POWER, 0);
8029 +}
8030 +
8031 +arch_initcall(bcm_power_init); /* Initialize early */
8032 +module_exit(bcm_power_exit);
8033 +
8034 +MODULE_AUTHOR("Phil Elwell");
8035 +MODULE_DESCRIPTION("Interface to BCM2708 power management");
8036 +MODULE_LICENSE("GPL");
8037 --- /dev/null
8038 +++ b/arch/arm/mach-bcm2709/vc_mem.c
8039 @@ -0,0 +1,431 @@
8040 +/*****************************************************************************
8041 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
8042 +*
8043 +* Unless you and Broadcom execute a separate written software license
8044 +* agreement governing use of this software, this software is licensed to you
8045 +* under the terms of the GNU General Public License version 2, available at
8046 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8047 +*
8048 +* Notwithstanding the above, under no circumstances may you combine this
8049 +* software in any way with any other Broadcom software provided under a
8050 +* license other than the GPL, without Broadcom's express prior written
8051 +* consent.
8052 +*****************************************************************************/
8053 +
8054 +#include <linux/kernel.h>
8055 +#include <linux/module.h>
8056 +#include <linux/fs.h>
8057 +#include <linux/device.h>
8058 +#include <linux/cdev.h>
8059 +#include <linux/mm.h>
8060 +#include <linux/slab.h>
8061 +#include <linux/debugfs.h>
8062 +#include <asm/uaccess.h>
8063 +#include <linux/dma-mapping.h>
8064 +
8065 +#ifdef CONFIG_ARCH_KONA
8066 +#include <chal/chal_ipc.h>
8067 +#elif defined(CONFIG_ARCH_BCM2708) || defined(CONFIG_ARCH_BCM2709)
8068 +#else
8069 +#include <csp/chal_ipc.h>
8070 +#endif
8071 +
8072 +#include "mach/vc_mem.h"
8073 +#include <mach/vcio.h>
8074 +
8075 +#define DRIVER_NAME "vc-mem"
8076 +
8077 +// Device (/dev) related variables
8078 +static dev_t vc_mem_devnum = 0;
8079 +static struct class *vc_mem_class = NULL;
8080 +static struct cdev vc_mem_cdev;
8081 +static int vc_mem_inited = 0;
8082 +
8083 +#ifdef CONFIG_DEBUG_FS
8084 +static struct dentry *vc_mem_debugfs_entry;
8085 +#endif
8086 +
8087 +/*
8088 + * Videocore memory addresses and size
8089 + *
8090 + * Drivers that wish to know the videocore memory addresses and sizes should
8091 + * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
8092 + * headers. This allows the other drivers to not be tied down to a a certain
8093 + * address/size at compile time.
8094 + *
8095 + * In the future, the goal is to have the videocore memory virtual address and
8096 + * size be calculated at boot time rather than at compile time. The decision of
8097 + * where the videocore memory resides and its size would be in the hands of the
8098 + * bootloader (and/or kernel). When that happens, the values of these variables
8099 + * would be calculated and assigned in the init function.
8100 + */
8101 +// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
8102 +unsigned long mm_vc_mem_phys_addr = 0x00000000;
8103 +unsigned int mm_vc_mem_size = 0;
8104 +unsigned int mm_vc_mem_base = 0;
8105 +
8106 +EXPORT_SYMBOL(mm_vc_mem_phys_addr);
8107 +EXPORT_SYMBOL(mm_vc_mem_size);
8108 +EXPORT_SYMBOL(mm_vc_mem_base);
8109 +
8110 +static uint phys_addr = 0;
8111 +static uint mem_size = 0;
8112 +static uint mem_base = 0;
8113 +
8114 +
8115 +/****************************************************************************
8116 +*
8117 +* vc_mem_open
8118 +*
8119 +***************************************************************************/
8120 +
8121 +static int
8122 +vc_mem_open(struct inode *inode, struct file *file)
8123 +{
8124 + (void) inode;
8125 + (void) file;
8126 +
8127 + pr_debug("%s: called file = 0x%p\n", __func__, file);
8128 +
8129 + return 0;
8130 +}
8131 +
8132 +/****************************************************************************
8133 +*
8134 +* vc_mem_release
8135 +*
8136 +***************************************************************************/
8137 +
8138 +static int
8139 +vc_mem_release(struct inode *inode, struct file *file)
8140 +{
8141 + (void) inode;
8142 + (void) file;
8143 +
8144 + pr_debug("%s: called file = 0x%p\n", __func__, file);
8145 +
8146 + return 0;
8147 +}
8148 +
8149 +/****************************************************************************
8150 +*
8151 +* vc_mem_get_size
8152 +*
8153 +***************************************************************************/
8154 +
8155 +static void
8156 +vc_mem_get_size(void)
8157 +{
8158 +}
8159 +
8160 +/****************************************************************************
8161 +*
8162 +* vc_mem_get_base
8163 +*
8164 +***************************************************************************/
8165 +
8166 +static void
8167 +vc_mem_get_base(void)
8168 +{
8169 +}
8170 +
8171 +/****************************************************************************
8172 +*
8173 +* vc_mem_get_current_size
8174 +*
8175 +***************************************************************************/
8176 +
8177 +int
8178 +vc_mem_get_current_size(void)
8179 +{
8180 + return mm_vc_mem_size;
8181 +}
8182 +
8183 +EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
8184 +
8185 +/****************************************************************************
8186 +*
8187 +* vc_mem_ioctl
8188 +*
8189 +***************************************************************************/
8190 +
8191 +static long
8192 +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
8193 +{
8194 + int rc = 0;
8195 +
8196 + (void) cmd;
8197 + (void) arg;
8198 +
8199 + pr_debug("%s: called file = 0x%p\n", __func__, file);
8200 +
8201 + switch (cmd) {
8202 + case VC_MEM_IOC_MEM_PHYS_ADDR:
8203 + {
8204 + pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
8205 + __func__, (void *) mm_vc_mem_phys_addr);
8206 +
8207 + if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
8208 + sizeof (mm_vc_mem_phys_addr)) != 0) {
8209 + rc = -EFAULT;
8210 + }
8211 + break;
8212 + }
8213 + case VC_MEM_IOC_MEM_SIZE:
8214 + {
8215 + // Get the videocore memory size first
8216 + vc_mem_get_size();
8217 +
8218 + pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
8219 + mm_vc_mem_size);
8220 +
8221 + if (copy_to_user((void *) arg, &mm_vc_mem_size,
8222 + sizeof (mm_vc_mem_size)) != 0) {
8223 + rc = -EFAULT;
8224 + }
8225 + break;
8226 + }
8227 + case VC_MEM_IOC_MEM_BASE:
8228 + {
8229 + // Get the videocore memory base
8230 + vc_mem_get_base();
8231 +
8232 + pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
8233 + mm_vc_mem_base);
8234 +
8235 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
8236 + sizeof (mm_vc_mem_base)) != 0) {
8237 + rc = -EFAULT;
8238 + }
8239 + break;
8240 + }
8241 + case VC_MEM_IOC_MEM_LOAD:
8242 + {
8243 + // Get the videocore memory base
8244 + vc_mem_get_base();
8245 +
8246 + pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
8247 + mm_vc_mem_base);
8248 +
8249 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
8250 + sizeof (mm_vc_mem_base)) != 0) {
8251 + rc = -EFAULT;
8252 + }
8253 + break;
8254 + }
8255 + default:
8256 + {
8257 + return -ENOTTY;
8258 + }
8259 + }
8260 + pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
8261 +
8262 + return rc;
8263 +}
8264 +
8265 +/****************************************************************************
8266 +*
8267 +* vc_mem_mmap
8268 +*
8269 +***************************************************************************/
8270 +
8271 +static int
8272 +vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
8273 +{
8274 + int rc = 0;
8275 + unsigned long length = vma->vm_end - vma->vm_start;
8276 + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
8277 +
8278 + pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
8279 + __func__, (long) vma->vm_start, (long) vma->vm_end,
8280 + (long) vma->vm_pgoff);
8281 +
8282 + if (offset + length > mm_vc_mem_size) {
8283 + pr_err("%s: length %ld is too big\n", __func__, length);
8284 + return -EINVAL;
8285 + }
8286 + // Do not cache the memory map
8287 + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
8288 +
8289 + rc = remap_pfn_range(vma, vma->vm_start,
8290 + (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
8291 + vma->vm_pgoff, length, vma->vm_page_prot);
8292 + if (rc != 0) {
8293 + pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
8294 + }
8295 +
8296 + return rc;
8297 +}
8298 +
8299 +/****************************************************************************
8300 +*
8301 +* File Operations for the driver.
8302 +*
8303 +***************************************************************************/
8304 +
8305 +static const struct file_operations vc_mem_fops = {
8306 + .owner = THIS_MODULE,
8307 + .open = vc_mem_open,
8308 + .release = vc_mem_release,
8309 + .unlocked_ioctl = vc_mem_ioctl,
8310 + .mmap = vc_mem_mmap,
8311 +};
8312 +
8313 +#ifdef CONFIG_DEBUG_FS
8314 +static void vc_mem_debugfs_deinit(void)
8315 +{
8316 + debugfs_remove_recursive(vc_mem_debugfs_entry);
8317 + vc_mem_debugfs_entry = NULL;
8318 +}
8319 +
8320 +
8321 +static int vc_mem_debugfs_init(
8322 + struct device *dev)
8323 +{
8324 + vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
8325 + if (!vc_mem_debugfs_entry) {
8326 + dev_warn(dev, "could not create debugfs entry\n");
8327 + return -EFAULT;
8328 + }
8329 +
8330 + if (!debugfs_create_x32("vc_mem_phys_addr",
8331 + 0444,
8332 + vc_mem_debugfs_entry,
8333 + (u32 *)&mm_vc_mem_phys_addr)) {
8334 + dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
8335 + __func__);
8336 + goto fail;
8337 + }
8338 +
8339 + if (!debugfs_create_x32("vc_mem_size",
8340 + 0444,
8341 + vc_mem_debugfs_entry,
8342 + (u32 *)&mm_vc_mem_size)) {
8343 + dev_warn(dev, "%s:could not create vc_mem_size entry\n",
8344 + __func__);
8345 + goto fail;
8346 + }
8347 +
8348 + if (!debugfs_create_x32("vc_mem_base",
8349 + 0444,
8350 + vc_mem_debugfs_entry,
8351 + (u32 *)&mm_vc_mem_base)) {
8352 + dev_warn(dev, "%s:could not create vc_mem_base entry\n",
8353 + __func__);
8354 + goto fail;
8355 + }
8356 +
8357 + return 0;
8358 +
8359 +fail:
8360 + vc_mem_debugfs_deinit();
8361 + return -EFAULT;
8362 +}
8363 +
8364 +#endif /* CONFIG_DEBUG_FS */
8365 +
8366 +
8367 +/****************************************************************************
8368 +*
8369 +* vc_mem_init
8370 +*
8371 +***************************************************************************/
8372 +
8373 +static int __init
8374 +vc_mem_init(void)
8375 +{
8376 + int rc = -EFAULT;
8377 + struct device *dev;
8378 +
8379 + pr_debug("%s: called\n", __func__);
8380 +
8381 + mm_vc_mem_phys_addr = phys_addr;
8382 + mm_vc_mem_size = mem_size;
8383 + mm_vc_mem_base = mem_base;
8384 +
8385 + vc_mem_get_size();
8386 +
8387 + pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
8388 + mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
8389 +
8390 + if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
8391 + pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
8392 + __func__, rc);
8393 + goto out_err;
8394 + }
8395 +
8396 + cdev_init(&vc_mem_cdev, &vc_mem_fops);
8397 + if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
8398 + pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
8399 + goto out_unregister;
8400 + }
8401 +
8402 + vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
8403 + if (IS_ERR(vc_mem_class)) {
8404 + rc = PTR_ERR(vc_mem_class);
8405 + pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
8406 + goto out_cdev_del;
8407 + }
8408 +
8409 + dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
8410 + DRIVER_NAME);
8411 + if (IS_ERR(dev)) {
8412 + rc = PTR_ERR(dev);
8413 + pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
8414 + goto out_class_destroy;
8415 + }
8416 +
8417 +#ifdef CONFIG_DEBUG_FS
8418 + /* don't fail if the debug entries cannot be created */
8419 + vc_mem_debugfs_init(dev);
8420 +#endif
8421 +
8422 + vc_mem_inited = 1;
8423 + return 0;
8424 +
8425 + device_destroy(vc_mem_class, vc_mem_devnum);
8426 +
8427 + out_class_destroy:
8428 + class_destroy(vc_mem_class);
8429 + vc_mem_class = NULL;
8430 +
8431 + out_cdev_del:
8432 + cdev_del(&vc_mem_cdev);
8433 +
8434 + out_unregister:
8435 + unregister_chrdev_region(vc_mem_devnum, 1);
8436 +
8437 + out_err:
8438 + return -1;
8439 +}
8440 +
8441 +/****************************************************************************
8442 +*
8443 +* vc_mem_exit
8444 +*
8445 +***************************************************************************/
8446 +
8447 +static void __exit
8448 +vc_mem_exit(void)
8449 +{
8450 + pr_debug("%s: called\n", __func__);
8451 +
8452 + if (vc_mem_inited) {
8453 +#if CONFIG_DEBUG_FS
8454 + vc_mem_debugfs_deinit();
8455 +#endif
8456 + device_destroy(vc_mem_class, vc_mem_devnum);
8457 + class_destroy(vc_mem_class);
8458 + cdev_del(&vc_mem_cdev);
8459 + unregister_chrdev_region(vc_mem_devnum, 1);
8460 + }
8461 +}
8462 +
8463 +module_init(vc_mem_init);
8464 +module_exit(vc_mem_exit);
8465 +MODULE_LICENSE("GPL");
8466 +MODULE_AUTHOR("Broadcom Corporation");
8467 +
8468 +module_param(phys_addr, uint, 0644);
8469 +module_param(mem_size, uint, 0644);
8470 +module_param(mem_base, uint, 0644);
8471 --- /dev/null
8472 +++ b/arch/arm/mach-bcm2709/vc_support.c
8473 @@ -0,0 +1,318 @@
8474 +/*
8475 + * vc_support.c
8476 + *
8477 + * Created on: 25 Nov 2012
8478 + * Author: Simon
8479 + */
8480 +
8481 +#include <linux/module.h>
8482 +#include <mach/vcio.h>
8483 +
8484 +#ifdef ECLIPSE_IGNORE
8485 +
8486 +#define __user
8487 +#define __init
8488 +#define __exit
8489 +#define __iomem
8490 +#define KERN_DEBUG
8491 +#define KERN_ERR
8492 +#define KERN_WARNING
8493 +#define KERN_INFO
8494 +#define _IOWR(a, b, c) b
8495 +#define _IOW(a, b, c) b
8496 +#define _IO(a, b) b
8497 +
8498 +#endif
8499 +
8500 +/****** VC MAILBOX FUNCTIONALITY ******/
8501 +unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags)
8502 +{
8503 + struct vc_msg
8504 + {
8505 + unsigned int m_msgSize;
8506 + unsigned int m_response;
8507 +
8508 + struct vc_tag
8509 + {
8510 + unsigned int m_tagId;
8511 + unsigned int m_sendBufferSize;
8512 + union {
8513 + unsigned int m_sendDataSize;
8514 + unsigned int m_recvDataSize;
8515 + };
8516 +
8517 + struct args
8518 + {
8519 + union {
8520 + unsigned int m_size;
8521 + unsigned int m_handle;
8522 + };
8523 + unsigned int m_alignment;
8524 + unsigned int m_flags;
8525 + } m_args;
8526 + } m_tag;
8527 +
8528 + unsigned int m_endTag;
8529 + } msg;
8530 + int s;
8531 +
8532 + msg.m_msgSize = sizeof(msg);
8533 + msg.m_response = 0;
8534 + msg.m_endTag = 0;
8535 +
8536 + //fill in the tag for the allocation command
8537 + msg.m_tag.m_tagId = 0x3000c;
8538 + msg.m_tag.m_sendBufferSize = 12;
8539 + msg.m_tag.m_sendDataSize = 12;
8540 +
8541 + //fill in our args
8542 + msg.m_tag.m_args.m_size = size;
8543 + msg.m_tag.m_args.m_alignment = alignment;
8544 + msg.m_tag.m_args.m_flags = flags;
8545 +
8546 + //run the command
8547 + s = bcm_mailbox_property(&msg, sizeof(msg));
8548 +
8549 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
8550 + {
8551 + *pHandle = msg.m_tag.m_args.m_handle;
8552 + return 0;
8553 + }
8554 + else
8555 + {
8556 + printk(KERN_ERR "failed to allocate vc memory: s=%d response=%08x recv data size=%08x\n",
8557 + s, msg.m_response, msg.m_tag.m_recvDataSize);
8558 + return 1;
8559 + }
8560 +}
8561 +
8562 +unsigned int ReleaseVcMemory(unsigned int handle)
8563 +{
8564 + struct vc_msg
8565 + {
8566 + unsigned int m_msgSize;
8567 + unsigned int m_response;
8568 +
8569 + struct vc_tag
8570 + {
8571 + unsigned int m_tagId;
8572 + unsigned int m_sendBufferSize;
8573 + union {
8574 + unsigned int m_sendDataSize;
8575 + unsigned int m_recvDataSize;
8576 + };
8577 +
8578 + struct args
8579 + {
8580 + union {
8581 + unsigned int m_handle;
8582 + unsigned int m_error;
8583 + };
8584 + } m_args;
8585 + } m_tag;
8586 +
8587 + unsigned int m_endTag;
8588 + } msg;
8589 + int s;
8590 +
8591 + msg.m_msgSize = sizeof(msg);
8592 + msg.m_response = 0;
8593 + msg.m_endTag = 0;
8594 +
8595 + //fill in the tag for the release command
8596 + msg.m_tag.m_tagId = 0x3000f;
8597 + msg.m_tag.m_sendBufferSize = 4;
8598 + msg.m_tag.m_sendDataSize = 4;
8599 +
8600 + //pass across the handle
8601 + msg.m_tag.m_args.m_handle = handle;
8602 +
8603 + s = bcm_mailbox_property(&msg, sizeof(msg));
8604 +
8605 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
8606 + return 0;
8607 + else
8608 + {
8609 + printk(KERN_ERR "failed to release vc memory: s=%d response=%08x recv data size=%08x error=%08x\n",
8610 + s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
8611 + return 1;
8612 + }
8613 +}
8614 +
8615 +unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle)
8616 +{
8617 + struct vc_msg
8618 + {
8619 + unsigned int m_msgSize;
8620 + unsigned int m_response;
8621 +
8622 + struct vc_tag
8623 + {
8624 + unsigned int m_tagId;
8625 + unsigned int m_sendBufferSize;
8626 + union {
8627 + unsigned int m_sendDataSize;
8628 + unsigned int m_recvDataSize;
8629 + };
8630 +
8631 + struct args
8632 + {
8633 + union {
8634 + unsigned int m_handle;
8635 + unsigned int m_busAddress;
8636 + };
8637 + } m_args;
8638 + } m_tag;
8639 +
8640 + unsigned int m_endTag;
8641 + } msg;
8642 + int s;
8643 +
8644 + msg.m_msgSize = sizeof(msg);
8645 + msg.m_response = 0;
8646 + msg.m_endTag = 0;
8647 +
8648 + //fill in the tag for the lock command
8649 + msg.m_tag.m_tagId = 0x3000d;
8650 + msg.m_tag.m_sendBufferSize = 4;
8651 + msg.m_tag.m_sendDataSize = 4;
8652 +
8653 + //pass across the handle
8654 + msg.m_tag.m_args.m_handle = handle;
8655 +
8656 + s = bcm_mailbox_property(&msg, sizeof(msg));
8657 +
8658 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
8659 + {
8660 + //pick out the bus address
8661 + *pBusAddress = msg.m_tag.m_args.m_busAddress;
8662 + return 0;
8663 + }
8664 + else
8665 + {
8666 + printk(KERN_ERR "failed to lock vc memory: s=%d response=%08x recv data size=%08x\n",
8667 + s, msg.m_response, msg.m_tag.m_recvDataSize);
8668 + return 1;
8669 + }
8670 +}
8671 +
8672 +unsigned int UnlockVcMemory(unsigned int handle)
8673 +{
8674 + struct vc_msg
8675 + {
8676 + unsigned int m_msgSize;
8677 + unsigned int m_response;
8678 +
8679 + struct vc_tag
8680 + {
8681 + unsigned int m_tagId;
8682 + unsigned int m_sendBufferSize;
8683 + union {
8684 + unsigned int m_sendDataSize;
8685 + unsigned int m_recvDataSize;
8686 + };
8687 +
8688 + struct args
8689 + {
8690 + union {
8691 + unsigned int m_handle;
8692 + unsigned int m_error;
8693 + };
8694 + } m_args;
8695 + } m_tag;
8696 +
8697 + unsigned int m_endTag;
8698 + } msg;
8699 + int s;
8700 +
8701 + msg.m_msgSize = sizeof(msg);
8702 + msg.m_response = 0;
8703 + msg.m_endTag = 0;
8704 +
8705 + //fill in the tag for the unlock command
8706 + msg.m_tag.m_tagId = 0x3000e;
8707 + msg.m_tag.m_sendBufferSize = 4;
8708 + msg.m_tag.m_sendDataSize = 4;
8709 +
8710 + //pass across the handle
8711 + msg.m_tag.m_args.m_handle = handle;
8712 +
8713 + s = bcm_mailbox_property(&msg, sizeof(msg));
8714 +
8715 + //check the error code too
8716 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
8717 + return 0;
8718 + else
8719 + {
8720 + printk(KERN_ERR "failed to unlock vc memory: s=%d response=%08x recv data size=%08x error%08x\n",
8721 + s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
8722 + return 1;
8723 + }
8724 +}
8725 +
8726 +unsigned int ExecuteVcCode(unsigned int code,
8727 + unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5)
8728 +{
8729 + struct vc_msg
8730 + {
8731 + unsigned int m_msgSize;
8732 + unsigned int m_response;
8733 +
8734 + struct vc_tag
8735 + {
8736 + unsigned int m_tagId;
8737 + unsigned int m_sendBufferSize;
8738 + union {
8739 + unsigned int m_sendDataSize;
8740 + unsigned int m_recvDataSize;
8741 + };
8742 +
8743 + struct args
8744 + {
8745 + union {
8746 + unsigned int m_pCode;
8747 + unsigned int m_return;
8748 + };
8749 + unsigned int m_r0;
8750 + unsigned int m_r1;
8751 + unsigned int m_r2;
8752 + unsigned int m_r3;
8753 + unsigned int m_r4;
8754 + unsigned int m_r5;
8755 + } m_args;
8756 + } m_tag;
8757 +
8758 + unsigned int m_endTag;
8759 + } msg;
8760 + int s;
8761 +
8762 + msg.m_msgSize = sizeof(msg);
8763 + msg.m_response = 0;
8764 + msg.m_endTag = 0;
8765 +
8766 + //fill in the tag for the unlock command
8767 + msg.m_tag.m_tagId = 0x30010;
8768 + msg.m_tag.m_sendBufferSize = 28;
8769 + msg.m_tag.m_sendDataSize = 28;
8770 +
8771 + //pass across the handle
8772 + msg.m_tag.m_args.m_pCode = code;
8773 + msg.m_tag.m_args.m_r0 = r0;
8774 + msg.m_tag.m_args.m_r1 = r1;
8775 + msg.m_tag.m_args.m_r2 = r2;
8776 + msg.m_tag.m_args.m_r3 = r3;
8777 + msg.m_tag.m_args.m_r4 = r4;
8778 + msg.m_tag.m_args.m_r5 = r5;
8779 +
8780 + s = bcm_mailbox_property(&msg, sizeof(msg));
8781 +
8782 + //check the error code too
8783 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
8784 + return msg.m_tag.m_args.m_return;
8785 + else
8786 + {
8787 + printk(KERN_ERR "failed to execute: s=%d response=%08x recv data size=%08x\n",
8788 + s, msg.m_response, msg.m_tag.m_recvDataSize);
8789 + return 1;
8790 + }
8791 +}
8792 --- /dev/null
8793 +++ b/arch/arm/mach-bcm2709/vcio.c
8794 @@ -0,0 +1,474 @@
8795 +/*
8796 + * linux/arch/arm/mach-bcm2708/vcio.c
8797 + *
8798 + * Copyright (C) 2010 Broadcom
8799 + *
8800 + * This program is free software; you can redistribute it and/or modify
8801 + * it under the terms of the GNU General Public License version 2 as
8802 + * published by the Free Software Foundation.
8803 + *
8804 + * This device provides a shared mechanism for writing to the mailboxes,
8805 + * semaphores, doorbells etc. that are shared between the ARM and the
8806 + * VideoCore processor
8807 + */
8808 +
8809 +#if defined(CONFIG_SERIAL_BCM_MBOX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
8810 +#define SUPPORT_SYSRQ
8811 +#endif
8812 +
8813 +#include <linux/module.h>
8814 +#include <linux/console.h>
8815 +#include <linux/serial_core.h>
8816 +#include <linux/serial.h>
8817 +#include <linux/errno.h>
8818 +#include <linux/device.h>
8819 +#include <linux/init.h>
8820 +#include <linux/mm.h>
8821 +#include <linux/dma-mapping.h>
8822 +#include <linux/platform_device.h>
8823 +#include <linux/sysrq.h>
8824 +#include <linux/delay.h>
8825 +#include <linux/slab.h>
8826 +#include <linux/interrupt.h>
8827 +#include <linux/irq.h>
8828 +
8829 +#include <linux/io.h>
8830 +
8831 +#include <mach/vcio.h>
8832 +#include <mach/platform.h>
8833 +
8834 +#include <asm/uaccess.h>
8835 +
8836 +
8837 +#define DRIVER_NAME BCM_VCIO_DRIVER_NAME
8838 +
8839 +/* ----------------------------------------------------------------------
8840 + * Mailbox
8841 + * -------------------------------------------------------------------- */
8842 +
8843 +/* offsets from a mail box base address */
8844 +#define MAIL_WRT 0x00 /* write - and next 4 words */
8845 +#define MAIL_RD 0x00 /* read - and next 4 words */
8846 +#define MAIL_POL 0x10 /* read without popping the fifo */
8847 +#define MAIL_SND 0x14 /* sender ID (bottom two bits) */
8848 +#define MAIL_STA 0x18 /* status */
8849 +#define MAIL_CNF 0x1C /* configuration */
8850 +
8851 +#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf))
8852 +#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf))
8853 +#define MBOX_CHAN(msg) ((msg) & 0xf)
8854 +#define MBOX_DATA28(msg) ((msg) & ~0xf)
8855 +#define MBOX_DATA28_LSB(msg) (((uint32_t)msg) >> 4)
8856 +
8857 +#define MBOX_MAGIC 0xd0d0c0de
8858 +
8859 +struct vc_mailbox {
8860 + struct device *dev; /* parent device */
8861 + void __iomem *status;
8862 + void __iomem *config;
8863 + void __iomem *read;
8864 + void __iomem *write;
8865 + uint32_t msg[MBOX_CHAN_COUNT];
8866 + struct semaphore sema[MBOX_CHAN_COUNT];
8867 + uint32_t magic;
8868 +};
8869 +
8870 +static void mbox_init(struct vc_mailbox *mbox_out, struct device *dev,
8871 + uint32_t addr_mbox)
8872 +{
8873 + int i;
8874 +
8875 + mbox_out->dev = dev;
8876 + mbox_out->status = __io_address(addr_mbox + MAIL_STA);
8877 + mbox_out->config = __io_address(addr_mbox + MAIL_CNF);
8878 + mbox_out->read = __io_address(addr_mbox + MAIL_RD);
8879 + /* Write to the other mailbox */
8880 + mbox_out->write =
8881 + __io_address((addr_mbox ^ ARM_0_MAIL0_WRT ^ ARM_0_MAIL1_WRT) +
8882 + MAIL_WRT);
8883 +
8884 + for (i = 0; i < MBOX_CHAN_COUNT; i++) {
8885 + mbox_out->msg[i] = 0;
8886 + sema_init(&mbox_out->sema[i], 0);
8887 + }
8888 +
8889 + /* Enable the interrupt on data reception */
8890 + writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->config);
8891 +
8892 + mbox_out->magic = MBOX_MAGIC;
8893 +}
8894 +
8895 +static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28)
8896 +{
8897 + int rc;
8898 +
8899 + if (mbox->magic != MBOX_MAGIC)
8900 + rc = -EINVAL;
8901 + else {
8902 + /* wait for the mailbox FIFO to have some space in it */
8903 + while (0 != (readl(mbox->status) & ARM_MS_FULL))
8904 + cpu_relax();
8905 +
8906 + writel(MBOX_MSG(chan, data28), mbox->write);
8907 + rc = 0;
8908 + }
8909 + return rc;
8910 +}
8911 +
8912 +static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28)
8913 +{
8914 + int rc;
8915 +
8916 + if (mbox->magic != MBOX_MAGIC)
8917 + rc = -EINVAL;
8918 + else {
8919 + down(&mbox->sema[chan]);
8920 + *data28 = MBOX_DATA28(mbox->msg[chan]);
8921 + mbox->msg[chan] = 0;
8922 + rc = 0;
8923 + }
8924 + return rc;
8925 +}
8926 +
8927 +static irqreturn_t mbox_irq(int irq, void *dev_id)
8928 +{
8929 + /* wait for the mailbox FIFO to have some data in it */
8930 + struct vc_mailbox *mbox = (struct vc_mailbox *) dev_id;
8931 + int status = readl(mbox->status);
8932 + int ret = IRQ_NONE;
8933 +
8934 + while (!(status & ARM_MS_EMPTY)) {
8935 + uint32_t msg = readl(mbox->read);
8936 + int chan = MBOX_CHAN(msg);
8937 + if (chan < MBOX_CHAN_COUNT) {
8938 + if (mbox->msg[chan]) {
8939 + /* Overflow */
8940 + printk(KERN_ERR DRIVER_NAME
8941 + ": mbox chan %d overflow - drop %08x\n",
8942 + chan, msg);
8943 + } else {
8944 + mbox->msg[chan] = (msg | 0xf);
8945 + up(&mbox->sema[chan]);
8946 + }
8947 + } else {
8948 + printk(KERN_ERR DRIVER_NAME
8949 + ": invalid channel selector (msg %08x)\n", msg);
8950 + }
8951 + ret = IRQ_HANDLED;
8952 + status = readl(mbox->status);
8953 + }
8954 + return ret;
8955 +}
8956 +
8957 +static struct irqaction mbox_irqaction = {
8958 + .name = "ARM Mailbox IRQ",
8959 + .flags = IRQF_DISABLED | IRQF_IRQPOLL,
8960 + .handler = mbox_irq,
8961 +};
8962 +
8963 +/* ----------------------------------------------------------------------
8964 + * Mailbox Methods
8965 + * -------------------------------------------------------------------- */
8966 +
8967 +static struct device *mbox_dev; /* we assume there's only one! */
8968 +
8969 +static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28)
8970 +{
8971 + int rc;
8972 +
8973 + struct vc_mailbox *mailbox = dev_get_drvdata(dev);
8974 + device_lock(dev);
8975 + rc = mbox_write(mailbox, chan, data28);
8976 + device_unlock(dev);
8977 +
8978 + return rc;
8979 +}
8980 +
8981 +static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28)
8982 +{
8983 + int rc;
8984 +
8985 + struct vc_mailbox *mailbox = dev_get_drvdata(dev);
8986 + device_lock(dev);
8987 + rc = mbox_read(mailbox, chan, data28);
8988 + device_unlock(dev);
8989 +
8990 + return rc;
8991 +}
8992 +
8993 +extern int bcm_mailbox_write(unsigned chan, uint32_t data28)
8994 +{
8995 + if (mbox_dev)
8996 + return dev_mbox_write(mbox_dev, chan, data28);
8997 + else
8998 + return -ENODEV;
8999 +}
9000 +EXPORT_SYMBOL_GPL(bcm_mailbox_write);
9001 +
9002 +extern int bcm_mailbox_read(unsigned chan, uint32_t *data28)
9003 +{
9004 + if (mbox_dev)
9005 + return dev_mbox_read(mbox_dev, chan, data28);
9006 + else
9007 + return -ENODEV;
9008 +}
9009 +EXPORT_SYMBOL_GPL(bcm_mailbox_read);
9010 +
9011 +static void dev_mbox_register(const char *dev_name, struct device *dev)
9012 +{
9013 + mbox_dev = dev;
9014 +}
9015 +
9016 +static int mbox_copy_from_user(void *dst, const void *src, int size)
9017 +{
9018 + if ( (uint32_t)src < TASK_SIZE)
9019 + {
9020 + return copy_from_user(dst, src, size);
9021 + }
9022 + else
9023 + {
9024 + memcpy( dst, src, size );
9025 + return 0;
9026 + }
9027 +}
9028 +
9029 +static int mbox_copy_to_user(void *dst, const void *src, int size)
9030 +{
9031 + if ( (uint32_t)dst < TASK_SIZE)
9032 + {
9033 + return copy_to_user(dst, src, size);
9034 + }
9035 + else
9036 + {
9037 + memcpy( dst, src, size );
9038 + return 0;
9039 + }
9040 +}
9041 +
9042 +static DEFINE_MUTEX(mailbox_lock);
9043 +extern int bcm_mailbox_property(void *data, int size)
9044 +{
9045 + uint32_t success;
9046 + dma_addr_t mem_bus; /* the memory address accessed from videocore */
9047 + void *mem_kern; /* the memory address accessed from driver */
9048 + int s = 0;
9049 +
9050 + mutex_lock(&mailbox_lock);
9051 + /* allocate some memory for the messages communicating with GPU */
9052 + mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, GFP_ATOMIC);
9053 + if (mem_kern) {
9054 + /* create the message */
9055 + mbox_copy_from_user(mem_kern, data, size);
9056 +
9057 + /* send the message */
9058 + wmb();
9059 + s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus);
9060 + if (s == 0) {
9061 + s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success);
9062 + }
9063 + if (s == 0) {
9064 + /* copy the response */
9065 + rmb();
9066 + mbox_copy_to_user(data, mem_kern, size);
9067 + }
9068 + dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus);
9069 + } else {
9070 + s = -ENOMEM;
9071 + }
9072 + if (s != 0)
9073 + printk(KERN_ERR DRIVER_NAME ": %s failed (%d)\n", __func__, s);
9074 +
9075 + mutex_unlock(&mailbox_lock);
9076 + return s;
9077 +}
9078 +EXPORT_SYMBOL_GPL(bcm_mailbox_property);
9079 +
9080 +/* ----------------------------------------------------------------------
9081 + * Platform Device for Mailbox
9082 + * -------------------------------------------------------------------- */
9083 +
9084 +/*
9085 + * Is the device open right now? Used to prevent
9086 + * concurent access into the same device
9087 + */
9088 +static int Device_Open = 0;
9089 +
9090 +/*
9091 + * This is called whenever a process attempts to open the device file
9092 + */
9093 +static int device_open(struct inode *inode, struct file *file)
9094 +{
9095 + /*
9096 + * We don't want to talk to two processes at the same time
9097 + */
9098 + if (Device_Open)
9099 + return -EBUSY;
9100 +
9101 + Device_Open++;
9102 + /*
9103 + * Initialize the message
9104 + */
9105 + try_module_get(THIS_MODULE);
9106 + return 0;
9107 +}
9108 +
9109 +static int device_release(struct inode *inode, struct file *file)
9110 +{
9111 + /*
9112 + * We're now ready for our next caller
9113 + */
9114 + Device_Open--;
9115 +
9116 + module_put(THIS_MODULE);
9117 + return 0;
9118 +}
9119 +
9120 +/*
9121 + * This function is called whenever a process tries to do an ioctl on our
9122 + * device file. We get two extra parameters (additional to the inode and file
9123 + * structures, which all device functions get): the number of the ioctl called
9124 + * and the parameter given to the ioctl function.
9125 + *
9126 + * If the ioctl is write or read/write (meaning output is returned to the
9127 + * calling process), the ioctl call returns the output of this function.
9128 + *
9129 + */
9130 +static long device_ioctl(struct file *file, /* see include/linux/fs.h */
9131 + unsigned int ioctl_num, /* number and param for ioctl */
9132 + unsigned long ioctl_param)
9133 +{
9134 + unsigned size;
9135 + /*
9136 + * Switch according to the ioctl called
9137 + */
9138 + switch (ioctl_num) {
9139 + case IOCTL_MBOX_PROPERTY:
9140 + /*
9141 + * Receive a pointer to a message (in user space) and set that
9142 + * to be the device's message. Get the parameter given to
9143 + * ioctl by the process.
9144 + */
9145 + mbox_copy_from_user(&size, (void *)ioctl_param, sizeof size);
9146 + return bcm_mailbox_property((void *)ioctl_param, size);
9147 + break;
9148 + default:
9149 + printk(KERN_ERR DRIVER_NAME "unknown ioctl: %d\n", ioctl_num);
9150 + return -EINVAL;
9151 + }
9152 +
9153 + return 0;
9154 +}
9155 +
9156 +/* Module Declarations */
9157 +
9158 +/*
9159 + * This structure will hold the functions to be called
9160 + * when a process does something to the device we
9161 + * created. Since a pointer to this structure is kept in
9162 + * the devices table, it can't be local to
9163 + * init_module. NULL is for unimplemented functios.
9164 + */
9165 +struct file_operations fops = {
9166 + .unlocked_ioctl = device_ioctl,
9167 + .open = device_open,
9168 + .release = device_release, /* a.k.a. close */
9169 +};
9170 +
9171 +static int bcm_vcio_probe(struct platform_device *pdev)
9172 +{
9173 + int ret = 0;
9174 + struct vc_mailbox *mailbox;
9175 +
9176 + mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL);
9177 + if (NULL == mailbox) {
9178 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
9179 + "mailbox memory\n");
9180 + ret = -ENOMEM;
9181 + } else {
9182 + struct resource *res;
9183 +
9184 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9185 + if (res == NULL) {
9186 + printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
9187 + "resource\n");
9188 + ret = -ENODEV;
9189 + kfree(mailbox);
9190 + } else {
9191 + /* should be based on the registers from res really */
9192 + mbox_init(mailbox, &pdev->dev, ARM_0_MAIL0_RD);
9193 +
9194 + platform_set_drvdata(pdev, mailbox);
9195 + dev_mbox_register(DRIVER_NAME, &pdev->dev);
9196 +
9197 + mbox_irqaction.dev_id = mailbox;
9198 + setup_irq(IRQ_ARM_MAILBOX, &mbox_irqaction);
9199 + printk(KERN_INFO DRIVER_NAME ": mailbox at %p\n",
9200 + __io_address(ARM_0_MAIL0_RD));
9201 + }
9202 + }
9203 +
9204 + if (ret == 0) {
9205 + /*
9206 + * Register the character device
9207 + */
9208 + ret = register_chrdev(MAJOR_NUM, DEVICE_FILE_NAME, &fops);
9209 +
9210 + /*
9211 + * Negative values signify an error
9212 + */
9213 + if (ret < 0) {
9214 + printk(KERN_ERR DRIVER_NAME
9215 + "Failed registering the character device %d\n", ret);
9216 + return ret;
9217 + }
9218 + }
9219 + return ret;
9220 +}
9221 +
9222 +static int bcm_vcio_remove(struct platform_device *pdev)
9223 +{
9224 + struct vc_mailbox *mailbox = platform_get_drvdata(pdev);
9225 +
9226 + platform_set_drvdata(pdev, NULL);
9227 + kfree(mailbox);
9228 +
9229 + return 0;
9230 +}
9231 +
9232 +static struct platform_driver bcm_mbox_driver = {
9233 + .probe = bcm_vcio_probe,
9234 + .remove = bcm_vcio_remove,
9235 +
9236 + .driver = {
9237 + .name = DRIVER_NAME,
9238 + .owner = THIS_MODULE,
9239 + },
9240 +};
9241 +
9242 +static int __init bcm_mbox_init(void)
9243 +{
9244 + int ret;
9245 +
9246 + printk(KERN_INFO "mailbox: Broadcom VideoCore Mailbox driver\n");
9247 +
9248 + ret = platform_driver_register(&bcm_mbox_driver);
9249 + if (ret != 0) {
9250 + printk(KERN_ERR DRIVER_NAME ": failed to register "
9251 + "on platform\n");
9252 + }
9253 +
9254 + return ret;
9255 +}
9256 +
9257 +static void __exit bcm_mbox_exit(void)
9258 +{
9259 + platform_driver_unregister(&bcm_mbox_driver);
9260 +}
9261 +
9262 +arch_initcall(bcm_mbox_init); /* Initialize early */
9263 +module_exit(bcm_mbox_exit);
9264 +
9265 +MODULE_AUTHOR("Gray Girling");
9266 +MODULE_DESCRIPTION("ARM I/O to VideoCore processor");
9267 +MODULE_LICENSE("GPL");
9268 +MODULE_ALIAS("platform:bcm-mbox");
9269 --- a/arch/arm/mm/proc-v7.S
9270 +++ b/arch/arm/mm/proc-v7.S
9271 @@ -441,6 +441,7 @@ __v7_setup:
9272 orr r0, r0, r6 @ set them
9273 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
9274 ret lr @ return to head.S:__ret
9275 + .space 256
9276 ENDPROC(__v7_setup)
9277
9278 .align 2
9279 --- a/arch/arm/tools/mach-types
9280 +++ b/arch/arm/tools/mach-types
9281 @@ -523,6 +523,7 @@ prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB
9282 paz00 MACH_PAZ00 PAZ00 3128
9283 acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129
9284 bcm2708 MACH_BCM2708 BCM2708 3138
9285 +bcm2709 MACH_BCM2709 BCM2709 3139
9286 ag5evm MACH_AG5EVM AG5EVM 3189
9287 ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
9288 wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
9289 --- a/drivers/char/hw_random/Kconfig
9290 +++ b/drivers/char/hw_random/Kconfig
9291 @@ -322,7 +322,7 @@ config HW_RANDOM_TPM
9292
9293 config HW_RANDOM_BCM2708
9294 tristate "BCM2708 generic true random number generator support"
9295 - depends on HW_RANDOM && ARCH_BCM2708
9296 + depends on HW_RANDOM && (ARCH_BCM2708 || ARCH_BCM2709)
9297 ---help---
9298 This driver provides the kernel-side support for the BCM2708 hardware.
9299
9300 --- a/drivers/clocksource/arm_arch_timer.c
9301 +++ b/drivers/clocksource/arm_arch_timer.c
9302 @@ -795,3 +795,39 @@ static void __init arch_timer_mem_init(s
9303 }
9304 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
9305 arch_timer_mem_init);
9306 +
9307 +int __init dc4_arch_timer_init(void)
9308 +{
9309 + if (arch_timers_present & ARCH_CP15_TIMER) {
9310 + pr_warn("arch_timer: multiple nodes in dt, skipping\n");
9311 + return -1;
9312 + }
9313 +
9314 + arch_timers_present |= ARCH_CP15_TIMER;
9315 +
9316 + /* Try to determine the frequency from the device tree or CNTFRQ */
9317 + arch_timer_rate = 19200000;
9318 +
9319 + arch_timer_ppi[PHYS_SECURE_PPI] = IRQ_ARM_LOCAL_CNTPSIRQ;
9320 + arch_timer_ppi[PHYS_NONSECURE_PPI] = IRQ_ARM_LOCAL_CNTPNSIRQ;
9321 + arch_timer_ppi[VIRT_PPI] = IRQ_ARM_LOCAL_CNTVIRQ;
9322 + arch_timer_ppi[HYP_PPI] = IRQ_ARM_LOCAL_CNTHPIRQ;
9323 +
9324 + /*
9325 + * If HYP mode is available, we know that the physical timer
9326 + * has been configured to be accessible from PL1. Use it, so
9327 + * that a guest can use the virtual timer instead.
9328 + *
9329 + * If no interrupt provided for virtual timer, we'll have to
9330 + * stick to the physical timer. It'd better be accessible...
9331 + */
9332 + if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
9333 + arch_timer_use_virtual = false;
9334 + }
9335 +
9336 + arch_timer_c3stop = 0;
9337 +
9338 + arch_timer_register();
9339 + arch_timer_common_init();
9340 + return 0;
9341 +}
9342 --- a/drivers/dma/Kconfig
9343 +++ b/drivers/dma/Kconfig
9344 @@ -332,7 +332,7 @@ config DMA_BCM2835
9345
9346 config DMA_BCM2708
9347 tristate "BCM2708 DMA engine support"
9348 - depends on MACH_BCM2708
9349 + depends on MACH_BCM2708 || MACH_BCM2709
9350 select DMA_ENGINE
9351 select DMA_VIRTUAL_CHANNELS
9352
9353 --- a/drivers/i2c/busses/Kconfig
9354 +++ b/drivers/i2c/busses/Kconfig
9355 @@ -362,7 +362,7 @@ config I2C_AXXIA
9356
9357 config I2C_BCM2835
9358 tristate "Broadcom BCM2835 I2C controller"
9359 - depends on ARCH_BCM2835 || ARCH_BCM2708
9360 + depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709
9361 help
9362 If you say yes to this option, support will be included for the
9363 BCM2835 I2C controller.
9364 @@ -374,7 +374,7 @@ config I2C_BCM2835
9365
9366 config I2C_BCM2708
9367 tristate "BCM2708 BSC"
9368 - depends on MACH_BCM2708
9369 + depends on MACH_BCM2708 || MACH_BCM2709
9370 help
9371 Enabling this option will add BSC (Broadcom Serial Controller)
9372 support for the BCM2708. BSC is a Broadcom proprietary bus compatible
9373 --- a/drivers/media/platform/bcm2835/Kconfig
9374 +++ b/drivers/media/platform/bcm2835/Kconfig
9375 @@ -2,7 +2,7 @@
9376
9377 config VIDEO_BCM2835
9378 bool "Broadcom BCM2835 camera interface driver"
9379 - depends on VIDEO_V4L2 && ARCH_BCM2708
9380 + depends on VIDEO_V4L2 && (ARCH_BCM2708 || ARCH_BCM2709)
9381 ---help---
9382 Say Y here to enable camera host interface devices for
9383 Broadcom BCM2835 SoC. This operates over the VCHIQ interface
9384 --- a/drivers/misc/vc04_services/Kconfig
9385 +++ b/drivers/misc/vc04_services/Kconfig
9386 @@ -1,6 +1,6 @@
9387 config BCM2708_VCHIQ
9388 tristate "Videocore VCHIQ"
9389 - depends on MACH_BCM2708
9390 + depends on MACH_BCM2708 || MACH_BCM2709
9391 default y
9392 help
9393 Kernel to VideoCore communication interface for the
9394 --- a/drivers/misc/vc04_services/Makefile
9395 +++ b/drivers/misc/vc04_services/Makefile
9396 @@ -1,5 +1,3 @@
9397 -ifeq ($(CONFIG_MACH_BCM2708),y)
9398 -
9399 obj-$(CONFIG_BCM2708_VCHIQ) += vchiq.o
9400
9401 vchiq-objs := \
9402 @@ -14,4 +12,3 @@ vchiq-objs := \
9403
9404 ccflags-y += -DVCOS_VERIFY_BKPTS=1 -Idrivers/misc/vc04_services -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000
9405
9406 -endif
9407 --- a/drivers/mmc/host/Kconfig
9408 +++ b/drivers/mmc/host/Kconfig
9409 @@ -304,7 +304,7 @@ config MMC_SDHCI_ST
9410
9411 config MMC_BCM2835
9412 tristate "MMC support on BCM2835"
9413 - depends on MACH_BCM2708
9414 + depends on (MACH_BCM2708 || MACH_BCM2709)
9415 help
9416 This selects the MMC Interface on BCM2835.
9417
9418 --- a/drivers/spi/Kconfig
9419 +++ b/drivers/spi/Kconfig
9420 @@ -77,7 +77,7 @@ config SPI_ATMEL
9421
9422 config SPI_BCM2835
9423 tristate "BCM2835 SPI controller"
9424 - depends on ARCH_BCM2835 || ARCH_BCM2708 || COMPILE_TEST
9425 + depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 || COMPILE_TEST
9426 help
9427 This selects a driver for the Broadcom BCM2835 SPI master.
9428
9429 @@ -88,7 +88,7 @@ config SPI_BCM2835
9430
9431 config SPI_BCM2708
9432 tristate "BCM2708 SPI controller driver (SPI0)"
9433 - depends on MACH_BCM2708
9434 + depends on MACH_BCM2708 || MACH_BCM2709
9435 help
9436 This selects a driver for the Broadcom BCM2708 SPI master (SPI0). This
9437 driver is not compatible with the "Universal SPI Master" or the SPI slave
9438 --- a/drivers/watchdog/Kconfig
9439 +++ b/drivers/watchdog/Kconfig
9440 @@ -454,7 +454,7 @@ config RETU_WATCHDOG
9441
9442 config BCM2708_WDT
9443 tristate "BCM2708 Watchdog"
9444 - depends on ARCH_BCM2708
9445 + depends on ARCH_BCM2708 || ARCH_BCM2709
9446 help
9447 Enables BCM2708 watchdog support.
9448
9449 --- a/sound/arm/Kconfig
9450 +++ b/sound/arm/Kconfig
9451 @@ -41,7 +41,7 @@ config SND_PXA2XX_AC97
9452
9453 config SND_BCM2835
9454 tristate "BCM2835 ALSA driver"
9455 - depends on ARCH_BCM2708 && BCM2708_VCHIQ && SND
9456 + depends on (ARCH_BCM2708 || ARCH_BCM2709) && BCM2708_VCHIQ && SND
9457 select SND_PCM
9458 help
9459 Say Y or M if you want to support BCM2835 Alsa pcm card driver
9460 --- a/sound/soc/bcm/Kconfig
9461 +++ b/sound/soc/bcm/Kconfig
9462 @@ -10,7 +10,7 @@ config SND_BCM2835_SOC_I2S
9463
9464 config SND_BCM2708_SOC_I2S
9465 tristate "SoC Audio support for the Broadcom BCM2708 I2S module"
9466 - depends on MACH_BCM2708
9467 + depends on MACH_BCM2708 || MACH_BCM2709
9468 select REGMAP_MMIO
9469 select SND_SOC_DMAENGINE_PCM
9470 select SND_SOC_GENERIC_DMAENGINE_PCM
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