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merge another batch of code from michael buesch's wireless-dev tree, fix up extpci...
[openwrt/svn-archive/archive.git] / target / linux / brcm47xx-2.6 / patches / 100-board_support.patch
1 diff -urN linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
2 --- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2007-01-25 23:34:01.000000000 +0100
4 @@ -0,0 +1,232 @@
5 +/*
6 + * CFE environment varialble access
7 + *
8 + * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
9 + *
10 + * This program is free software; you can redistribute it and/or modify it
11 + * under the terms of the GNU General Public License as published by the
12 + * Free Software Foundation; either version 2 of the License, or (at your
13 + * option) any later version.
14 + *
15 + * Copyright 2001-2003, Broadcom Corporation
16 + *
17 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
19 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
20 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
21 + */
22 +
23 +#include <linux/init.h>
24 +#include <linux/module.h>
25 +#include <linux/kernel.h>
26 +#include <linux/string.h>
27 +#include <asm/io.h>
28 +#include <asm/uaccess.h>
29 +
30 +#define NVRAM_SIZE (0x1ff0)
31 +static char _nvdata[NVRAM_SIZE] __initdata;
32 +static char _valuestr[256] __initdata;
33 +
34 +/*
35 + * TLV types. These codes are used in the "type-length-value"
36 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
37 + *
38 + * The layout of the flash/nvram is as follows:
39 + *
40 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
41 + *
42 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
43 + * The "length" field marks the length of the data section, not
44 + * including the type and length fields.
45 + *
46 + * Environment variables are stored as follows:
47 + *
48 + * <type_env> <length> <flags> <name> = <value>
49 + *
50 + * If bit 0 (low bit) is set, the length is an 8-bit value.
51 + * If bit 0 (low bit) is clear, the length is a 16-bit value
52 + *
53 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
54 + * indicates the size of the length field.
55 + *
56 + * Flags are from the constants below:
57 + *
58 + */
59 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
60 +#define ENV_LENGTH_8BITS 0x01
61 +
62 +#define ENV_TYPE_USER 0x80
63 +
64 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
65 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
66 +
67 +/*
68 + * The actual TLV types we support
69 + */
70 +
71 +#define ENV_TLV_TYPE_END 0x00
72 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
73 +
74 +/*
75 + * Environment variable flags
76 + */
77 +
78 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
79 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
80 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
81 +
82 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
83 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
84 +
85 +
86 +/* *********************************************************************
87 + * _nvram_read(buffer,offset,length)
88 + *
89 + * Read data from the NVRAM device
90 + *
91 + * Input parameters:
92 + * buffer - destination buffer
93 + * offset - offset of data to read
94 + * length - number of bytes to read
95 + *
96 + * Return value:
97 + * number of bytes read, or <0 if error occured
98 + ********************************************************************* */
99 +static int
100 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
101 +{
102 + int i;
103 + if (offset > NVRAM_SIZE)
104 + return -1;
105 +
106 + for ( i = 0; i < length; i++) {
107 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
108 + }
109 + return length;
110 +}
111 +
112 +
113 +static char*
114 +_strnchr(const char *dest,int c,size_t cnt)
115 +{
116 + while (*dest && (cnt > 0)) {
117 + if (*dest == c) return (char *) dest;
118 + dest++;
119 + cnt--;
120 + }
121 + return NULL;
122 +}
123 +
124 +
125 +
126 +/*
127 + * Core support API: Externally visible.
128 + */
129 +
130 +/*
131 + * Get the value of an NVRAM variable
132 + * @param name name of variable to get
133 + * @return value of variable or NULL if undefined
134 + */
135 +
136 +char*
137 +cfe_env_get(unsigned char *nv_buf, char* name)
138 +{
139 + int size;
140 + unsigned char *buffer;
141 + unsigned char *ptr;
142 + unsigned char *envval;
143 + unsigned int reclen;
144 + unsigned int rectype;
145 + int offset;
146 + int flg;
147 +
148 + size = NVRAM_SIZE;
149 + buffer = &_nvdata[0];
150 +
151 + ptr = buffer;
152 + offset = 0;
153 +
154 + /* Read the record type and length */
155 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
156 + goto error;
157 + }
158 +
159 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
160 +
161 + /* Adjust pointer for TLV type */
162 + rectype = *(ptr);
163 + offset++;
164 + size--;
165 +
166 + /*
167 + * Read the length. It can be either 1 or 2 bytes
168 + * depending on the code
169 + */
170 + if (rectype & ENV_LENGTH_8BITS) {
171 + /* Read the record type and length - 8 bits */
172 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
173 + goto error;
174 + }
175 + reclen = *(ptr);
176 + size--;
177 + offset++;
178 + }
179 + else {
180 + /* Read the record type and length - 16 bits, MSB first */
181 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
182 + goto error;
183 + }
184 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
185 + size -= 2;
186 + offset += 2;
187 + }
188 +
189 + if (reclen > size)
190 + break; /* should not happen, bad NVRAM */
191 +
192 + switch (rectype) {
193 + case ENV_TLV_TYPE_ENV:
194 + /* Read the TLV data */
195 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
196 + goto error;
197 + flg = *ptr++;
198 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
199 + if (envval) {
200 + *envval++ = '\0';
201 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
202 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
203 +#if 0
204 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
205 +#endif
206 + if(!strcmp(ptr, name)){
207 + return _valuestr;
208 + }
209 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
210 + return _valuestr;
211 + }
212 + break;
213 +
214 + default:
215 + /* Unknown TLV type, skip it. */
216 + break;
217 + }
218 +
219 + /*
220 + * Advance to next TLV
221 + */
222 +
223 + size -= (int)reclen;
224 + offset += reclen;
225 +
226 + /* Read the next record type */
227 + ptr = buffer;
228 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
229 + goto error;
230 + }
231 +
232 +error:
233 + return NULL;
234 +
235 +}
236 +
237 diff -urN linux.old/arch/mips/bcm947xx/include/nvram.h linux.dev/arch/mips/bcm947xx/include/nvram.h
238 --- linux.old/arch/mips/bcm947xx/include/nvram.h 1970-01-01 01:00:00.000000000 +0100
239 +++ linux.dev/arch/mips/bcm947xx/include/nvram.h 2007-01-25 23:34:01.000000000 +0100
240 @@ -0,0 +1,37 @@
241 +/*
242 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
243 + *
244 + * This program is free software; you can redistribute it and/or modify it
245 + * under the terms of the GNU General Public License as published by the
246 + * Free Software Foundation; either version 2 of the License, or (at your
247 + * option) any later version.
248 + */
249 +
250 +#ifndef __NVRAM_H
251 +#define __NVRAM_H
252 +
253 +struct nvram_header {
254 + u32 magic;
255 + u32 len;
256 + u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
257 + u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
258 + u32 config_ncdl; /* ncdl values for memc */
259 +};
260 +
261 +struct nvram_tuple {
262 + char *name;
263 + char *value;
264 + struct nvram_tuple *next;
265 +};
266 +
267 +#define NVRAM_HEADER 0x48534C46 /* 'FLSH' */
268 +#define NVRAM_VERSION 1
269 +#define NVRAM_HEADER_SIZE 20
270 +#define NVRAM_SPACE 0x8000
271 +
272 +#define NVRAM_MAX_VALUE_LEN 255
273 +#define NVRAM_MAX_PARAM_LEN 64
274 +
275 +char *nvram_get(const char *name);
276 +
277 +#endif
278 diff -urN linux.old/arch/mips/bcm947xx/irq.c linux.dev/arch/mips/bcm947xx/irq.c
279 --- linux.old/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100
280 +++ linux.dev/arch/mips/bcm947xx/irq.c 2007-01-25 23:34:01.000000000 +0100
281 @@ -0,0 +1,63 @@
282 +/*
283 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
284 + *
285 + * This program is free software; you can redistribute it and/or modify it
286 + * under the terms of the GNU General Public License as published by the
287 + * Free Software Foundation; either version 2 of the License, or (at your
288 + * option) any later version.
289 + *
290 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
291 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
292 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
293 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
294 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
295 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
296 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
297 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
298 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
299 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
300 + *
301 + * You should have received a copy of the GNU General Public License along
302 + * with this program; if not, write to the Free Software Foundation, Inc.,
303 + * 675 Mass Ave, Cambridge, MA 02139, USA.
304 + */
305 +
306 +#include <linux/errno.h>
307 +#include <linux/init.h>
308 +#include <linux/interrupt.h>
309 +#include <linux/irq.h>
310 +#include <linux/module.h>
311 +#include <linux/smp.h>
312 +#include <linux/types.h>
313 +
314 +#include <asm/cpu.h>
315 +#include <asm/io.h>
316 +#include <asm/irq.h>
317 +#include <asm/irq_cpu.h>
318 +
319 +void plat_irq_dispatch(void)
320 +{
321 + u32 cause;
322 +
323 + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
324 +
325 + clear_c0_status(cause);
326 +
327 + if (cause & CAUSEF_IP7)
328 + do_IRQ(7);
329 + if (cause & CAUSEF_IP2)
330 + do_IRQ(2);
331 + if (cause & CAUSEF_IP3)
332 + do_IRQ(3);
333 + if (cause & CAUSEF_IP4)
334 + do_IRQ(4);
335 + if (cause & CAUSEF_IP5)
336 + do_IRQ(5);
337 + if (cause & CAUSEF_IP6)
338 + do_IRQ(6);
339 +}
340 +
341 +void __init arch_init_irq(void)
342 +{
343 + mips_cpu_irq_init(0);
344 +}
345 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
346 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
347 +++ linux.dev/arch/mips/bcm947xx/Makefile 2007-01-26 01:38:18.000000000 +0100
348 @@ -0,0 +1,7 @@
349 +#
350 +# Makefile for the BCM47xx specific kernel interface routines
351 +# under Linux.
352 +#
353 +
354 +obj-y := irq.o prom.o setup.o time.o
355 +obj-y += nvram.o cfe_env.o
356 diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
357 --- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
358 +++ linux.dev/arch/mips/bcm947xx/nvram.c 2007-01-26 01:14:42.000000000 +0100
359 @@ -0,0 +1,131 @@
360 +/*
361 + * BCM947xx nvram variable access
362 + *
363 + * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
364 + *
365 + * This program is free software; you can redistribute it and/or modify it
366 + * under the terms of the GNU General Public License as published by the
367 + * Free Software Foundation; either version 2 of the License, or (at your
368 + * option) any later version.
369 + *
370 + *
371 + * Copyright 2005, Broadcom Corporation
372 + *
373 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
374 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
375 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
376 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
377 + *
378 + */
379 +
380 +#include <linux/init.h>
381 +#include <linux/module.h>
382 +#include <linux/ssb/ssb.h>
383 +#include <linux/kernel.h>
384 +#include <linux/string.h>
385 +#include <linux/interrupt.h>
386 +#include <linux/spinlock.h>
387 +#include <linux/slab.h>
388 +#include <asm/byteorder.h>
389 +#include <asm/bootinfo.h>
390 +#include <asm/addrspace.h>
391 +#include <asm/io.h>
392 +#include <asm/uaccess.h>
393 +
394 +#include <nvram.h>
395 +
396 +#define MB * 1048576
397 +extern struct ssb_bus ssb;
398 +
399 +static char nvram_buf[NVRAM_SPACE];
400 +static int cfe_env;
401 +extern char *cfe_env_get(char *nv_buf, const char *name);
402 +
403 +/* Probe for NVRAM header */
404 +static void __init early_nvram_init(void)
405 +{
406 + struct ssb_mipscore *mcore = &ssb.mipscore;
407 + struct nvram_header *header;
408 + int i;
409 + u32 base, lim, off;
410 + u32 *src, *dst;
411 +
412 + base = mcore->flash_window;
413 + lim = mcore->flash_window_size;
414 + cfe_env = 0;
415 +
416 +
417 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
418 + if (lim >= 8 MB) {
419 + src = (u32 *) KSEG1ADDR(base + 8 MB - 0x2000);
420 + dst = (u32 *) nvram_buf;
421 +
422 + if ((*src & 0xff00ff) == 0x000001) {
423 + printk("early_nvram_init: WGT634U NVRAM found.\n");
424 +
425 + for (i = 0; i < 0x1ff0; i++) {
426 + if (*src == 0xFFFFFFFF)
427 + break;
428 + *dst++ = *src++;
429 + }
430 + cfe_env = 1;
431 + return;
432 + }
433 + }
434 +
435 + off = 0x20000;
436 + while (off <= lim) {
437 + /* Windowed flash access */
438 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
439 + if (header->magic == NVRAM_HEADER)
440 + goto found;
441 + off <<= 1;
442 + }
443 +
444 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
445 + header = (struct nvram_header *) KSEG1ADDR(base + 4096);
446 + if (header->magic == NVRAM_HEADER)
447 + goto found;
448 +
449 + header = (struct nvram_header *) KSEG1ADDR(base + 1024);
450 + if (header->magic == NVRAM_HEADER)
451 + goto found;
452 +
453 + return;
454 +
455 +found:
456 + src = (u32 *) header;
457 + dst = (u32 *) nvram_buf;
458 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
459 + *dst++ = *src++;
460 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
461 + *dst++ = le32_to_cpu(*src++);
462 +}
463 +
464 +char *nvram_get(const char *name)
465 +{
466 + char *var, *value, *end, *eq;
467 +
468 + if (!name)
469 + return NULL;
470 +
471 + if (!nvram_buf[0])
472 + early_nvram_init();
473 +
474 + if (cfe_env)
475 + return cfe_env_get(nvram_buf, name);
476 +
477 + /* Look for name=value and return value */
478 + var = &nvram_buf[sizeof(struct nvram_header)];
479 + end = nvram_buf + sizeof(nvram_buf) - 2;
480 + end[0] = end[1] = '\0';
481 + for (; *var; var = value + strlen(value) + 1) {
482 + if (!(eq = strchr(var, '=')))
483 + break;
484 + value = eq + 1;
485 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
486 + return value;
487 + }
488 +
489 + return NULL;
490 +}
491 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
492 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
493 +++ linux.dev/arch/mips/bcm947xx/prom.c 2007-01-26 20:20:38.000000000 +0100
494 @@ -0,0 +1,61 @@
495 +/*
496 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
497 + *
498 + * This program is free software; you can redistribute it and/or modify it
499 + * under the terms of the GNU General Public License as published by the
500 + * Free Software Foundation; either version 2 of the License, or (at your
501 + * option) any later version.
502 + *
503 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
504 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
505 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
506 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
507 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
508 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
509 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
510 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
511 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
512 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
513 + *
514 + * You should have received a copy of the GNU General Public License along
515 + * with this program; if not, write to the Free Software Foundation, Inc.,
516 + * 675 Mass Ave, Cambridge, MA 02139, USA.
517 + */
518 +
519 +#include <linux/init.h>
520 +#include <linux/mm.h>
521 +#include <linux/sched.h>
522 +#include <linux/bootmem.h>
523 +
524 +#include <asm/addrspace.h>
525 +#include <asm/bootinfo.h>
526 +#include <asm/pmon.h>
527 +
528 +const char *get_system_type(void)
529 +{
530 + return "Broadcom BCM47xx";
531 +}
532 +
533 +void __init prom_init(void)
534 +{
535 + unsigned long mem;
536 +
537 + mips_machgroup = MACH_GROUP_BRCM;
538 + mips_machtype = MACH_BCM47XX;
539 +
540 + cfe_setup(fw_arg0, fw_arg1, fw_arg2, fw_arg3);
541 +
542 + /* Figure out memory size by finding aliases */
543 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
544 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
545 + *(unsigned long *)(prom_init))
546 + break;
547 + }
548 +
549 + add_memory_region(0, mem, BOOT_MEM_RAM);
550 +}
551 +
552 +unsigned long __init prom_free_prom_memory(void)
553 +{
554 + return 0;
555 +}
556 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
557 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
558 +++ linux.dev/arch/mips/bcm947xx/setup.c 2007-01-26 20:20:38.000000000 +0100
559 @@ -0,0 +1,162 @@
560 +/*
561 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
562 + * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
563 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
564 + * Copyright (C) 2006 Michael Buesch
565 + *
566 + * This program is free software; you can redistribute it and/or modify it
567 + * under the terms of the GNU General Public License as published by the
568 + * Free Software Foundation; either version 2 of the License, or (at your
569 + * option) any later version.
570 + *
571 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
572 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
573 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
574 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
575 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
576 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
577 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
578 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
579 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
580 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
581 + *
582 + * You should have received a copy of the GNU General Public License along
583 + * with this program; if not, write to the Free Software Foundation, Inc.,
584 + * 675 Mass Ave, Cambridge, MA 02139, USA.
585 + */
586 +
587 +#include <linux/init.h>
588 +#include <linux/types.h>
589 +#include <linux/tty.h>
590 +#include <linux/serial.h>
591 +#include <linux/serial_core.h>
592 +#include <linux/serial_reg.h>
593 +#include <asm/bootinfo.h>
594 +#include <asm/time.h>
595 +#include <asm/reboot.h>
596 +#include <asm/cfe.h>
597 +#include <linux/pm.h>
598 +#include <linux/ssb/ssb.h>
599 +
600 +#include <nvram.h>
601 +
602 +extern void bcm47xx_pci_init(void);
603 +extern void bcm47xx_time_init(void);
604 +
605 +struct ssb_bus ssb;
606 +
607 +static void bcm47xx_machine_restart(char *command)
608 +{
609 + printk(KERN_ALERT "Please stand by while rebooting the system...\n");
610 + local_irq_disable();
611 + /* CFE has a reboot callback, but that does not work.
612 + * Oopses with: Reserved instruction in kernel code.
613 + */
614 +
615 + /* Set the watchdog timer to reset immediately */
616 +//TODO sb_watchdog(sbh, 1);
617 + while (1)
618 + cpu_relax();
619 +}
620 +
621 +static void bcm47xx_machine_halt(void)
622 +{
623 + /* Disable interrupts and watchdog and spin forever */
624 + local_irq_disable();
625 +//TODO sb_watchdog(sbh, 0);
626 + while (1)
627 + cpu_relax();
628 +}
629 +
630 +static void e_aton(char *str, char *dest)
631 +{
632 + int i = 0;
633 +
634 + if (str == NULL) {
635 + memset(dest, 0, 6);
636 + return;
637 + }
638 +
639 + for (;;) {
640 + dest[i++] = (char) simple_strtoul(str, NULL, 16);
641 + str += 2;
642 + if (!*str++ || i == 6)
643 + break;
644 + }
645 +}
646 +
647 +static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
648 +{
649 + // TODO
650 +}
651 +
652 +static void bcm47xx_fill_sprom_nvram(struct ssb_sprom *sprom)
653 +{
654 + char *s;
655 +
656 + memset(sprom, 0, sizeof(struct ssb_sprom));
657 +
658 + sprom->revision = 3;
659 + if ((s = nvram_get("et0macaddr")))
660 + e_aton(s, sprom->r1.et0mac);
661 + if ((s = nvram_get("et1macaddr")))
662 + e_aton(s, sprom->r1.et1mac);
663 + if ((s = nvram_get("et0phyaddr")))
664 + sprom->r1.et0phyaddr = simple_strtoul(s, NULL, 10);
665 + if ((s = nvram_get("et1phyaddr")))
666 + sprom->r1.et1phyaddr = simple_strtoul(s, NULL, 10);
667 +}
668 +
669 +void __init plat_mem_setup(void)
670 +{
671 + int i, err;
672 + char *s;
673 + struct ssb_mipscore *mcore;
674 +
675 + err = ssb_bus_ssbbus_register(&ssb, SSB_ENUM_BASE, bcm47xx_fill_sprom);
676 + if (err) {
677 + const char *msg = "Failed to initialize SSB bus (err %d)\n";
678 + cfe_printk(msg, err); /* Make sure the message gets out of the box. */
679 + panic(msg, err);
680 + }
681 + mcore = &ssb.mipscore;
682 +
683 + /* FIXME: the nvram init depends on the ssb being fully initializes,
684 + * can't use the fill_sprom callback yet! */
685 + bcm47xx_fill_sprom_nvram(&ssb.sprom);
686 +
687 + s = nvram_get("kernel_args");
688 + if (s && !strncmp(s, "console=ttyS1", 13)) {
689 + struct ssb_serial_port port;
690 +
691 + cfe_printk("Swapping serial ports!\n");
692 + /* swap serial ports */
693 + memcpy(&port, &mcore->serial_ports[0], sizeof(port));
694 + memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], sizeof(port));
695 + memcpy(&mcore->serial_ports[1], &port, sizeof(port));
696 + }
697 +
698 + for (i = 0; i < mcore->nr_serial_ports; i++) {
699 + struct ssb_serial_port *port = &(mcore->serial_ports[i]);
700 + struct uart_port s;
701 +
702 + memset(&s, 0, sizeof(s));
703 + s.line = i;
704 + s.membase = port->regs;
705 + s.irq = port->irq + 2;//FIXME?
706 + s.uartclk = port->baud_base;
707 + s.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
708 + s.iotype = SERIAL_IO_MEM;
709 + s.regshift = port->reg_shift;
710 +
711 + early_serial_setup(&s);
712 + }
713 + cfe_printk("Serial init done.\n");
714 +
715 + _machine_restart = bcm47xx_machine_restart;
716 + _machine_halt = bcm47xx_machine_halt;
717 + pm_power_off = bcm47xx_machine_halt;
718 +
719 + board_time_init = bcm47xx_time_init;//FIXME move into ssb
720 +}
721 +
722 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
723 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
724 +++ linux.dev/arch/mips/bcm947xx/time.c 2007-01-26 16:26:48.000000000 +0100
725 @@ -0,0 +1,62 @@
726 +/*
727 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
728 + *
729 + * This program is free software; you can redistribute it and/or modify it
730 + * under the terms of the GNU General Public License as published by the
731 + * Free Software Foundation; either version 2 of the License, or (at your
732 + * option) any later version.
733 + *
734 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
735 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
736 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
737 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
738 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
739 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
740 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
741 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
742 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
743 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
744 + *
745 + * You should have received a copy of the GNU General Public License along
746 + * with this program; if not, write to the Free Software Foundation, Inc.,
747 + * 675 Mass Ave, Cambridge, MA 02139, USA.
748 + */
749 +
750 +#include <linux/init.h>
751 +#include <linux/kernel.h>
752 +#include <linux/sched.h>
753 +#include <linux/serial_reg.h>
754 +#include <linux/interrupt.h>
755 +#include <linux/ssb/ssb.h>
756 +#include <asm/addrspace.h>
757 +#include <asm/io.h>
758 +#include <asm/time.h>
759 +
760 +extern struct ssb_bus ssb;
761 +
762 +void __init
763 +bcm47xx_time_init(void)
764 +{
765 + unsigned long hz;
766 +
767 + /*
768 + * Use deterministic values for initial counter interrupt
769 + * so that calibrate delay avoids encountering a counter wrap.
770 + */
771 + write_c0_count(0);
772 + write_c0_compare(0xffff);
773 +
774 +// hz = ssb_clockspeed(&ssb);
775 +// if (!hz)
776 + hz = 100000000;
777 +
778 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
779 + mips_hpt_frequency = hz;
780 +}
781 +
782 +void __init
783 +plat_timer_setup(struct irqaction *irq)
784 +{
785 + /* Enable the timer interrupt */
786 + setup_irq(7, irq);
787 +}
788 diff -urN linux.old/arch/mips/cfe/cfe.c linux.dev/arch/mips/cfe/cfe.c
789 --- linux.old/arch/mips/cfe/cfe.c 1970-01-01 01:00:00.000000000 +0100
790 +++ linux.dev/arch/mips/cfe/cfe.c 2007-01-25 23:34:01.000000000 +0100
791 @@ -0,0 +1,533 @@
792 +/*
793 + * Broadcom Common Firmware Environment (CFE) support
794 + *
795 + * Copyright 2000, 2001, 2002
796 + * Broadcom Corporation. All rights reserved.
797 + *
798 + * Copyright (C) 2006 Michael Buesch
799 + *
800 + * Original Authors: Mitch Lichtenberg, Chris Demetriou
801 + *
802 + * This software is furnished under license and may be used and copied only
803 + * in accordance with the following terms and conditions. Subject to these
804 + * conditions, you may download, copy, install, use, modify and distribute
805 + * modified or unmodified copies of this software in source and/or binary
806 + * form. No title or ownership is transferred hereby.
807 + *
808 + * 1) Any source code used, modified or distributed must reproduce and
809 + * retain this copyright notice and list of conditions as they appear in
810 + * the source file.
811 + *
812 + * 2) No right is granted to use any trade name, trademark, or logo of
813 + * Broadcom Corporation. The "Broadcom Corporation" name may not be
814 + * used to endorse or promote products derived from this software
815 + * without the prior written permission of Broadcom Corporation.
816 + *
817 + * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
818 + * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
819 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
820 + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
821 + * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
822 + * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
823 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
824 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
825 + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
826 + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
827 + * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
828 + */
829 +
830 +#include <linux/init.h>
831 +#include <linux/string.h>
832 +#include <linux/errno.h>
833 +#include <linux/spinlock.h>
834 +#include <asm/cfe.h>
835 +
836 +#include "cfe_private.h"
837 +
838 +
839 +static cfe_uint_t cfe_handle;
840 +static int (*cfe_trampoline)(long handle, long iocb);
841 +
842 +
843 +#include <linux/kernel.h>
844 +
845 +void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1,
846 + unsigned long fwarg2, unsigned long fwarg3)
847 +{
848 + if (fwarg3 == 0x80300000) {
849 + /* WRT54G workaround */
850 + fwarg3 = CFE_EPTSEAL;
851 + fwarg2 = 0xBFC00500;
852 + }
853 + if (fwarg3 != CFE_EPTSEAL) {
854 + /* We are not booted from CFE */
855 + return;
856 + }
857 + if (fwarg1 == 0) {
858 + /* We are on the boot CPU */
859 + cfe_handle = (cfe_uint_t)fwarg0;
860 + cfe_trampoline = CFE_TO_PTR(fwarg2);
861 + }
862 +}
863 +
864 +int cfe_vprintk(const char *fmt, va_list args)
865 +{
866 + static char buffer[1024];
867 + static DEFINE_SPINLOCK(lock);
868 + static const char pfx[] = "CFE-console: ";
869 + static const size_t pfx_len = sizeof(pfx) - 1;
870 + unsigned long flags;
871 + int len, cnt, pos;
872 + int handle;
873 + int res;
874 +
875 + if (!cfe_present())
876 + return -ENODEV;
877 +
878 + spin_lock_irqsave(&lock, flags);
879 + handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
880 + if (CFE_ISERR(handle)) {
881 + len = -EIO;
882 + goto out;
883 + }
884 + strcpy(buffer, pfx);
885 + len = vscnprintf(buffer + pfx_len,
886 + sizeof(buffer) - pfx_len - 2,
887 + fmt, args);
888 + len += pfx_len;
889 + /* The CFE console requires CR-LF line-ends.
890 + * Add a CR, if we only terminate lines with a LF.
891 + * This does only fix CR-LF at the end of the string.
892 + * So for multiple lines, use multiple cfe_vprintk calls.
893 + */
894 + if (len > 1 &&
895 + buffer[len - 1] == '\n' && buffer[len - 2] != '\r') {
896 + buffer[len - 1] = '\r';
897 + buffer[len] = '\n';
898 + len += 1;
899 + }
900 + cnt = len;
901 + pos = 0;
902 + while (cnt > 0) {
903 + res = cfe_write(handle, buffer + pos, len - pos);
904 + if (CFE_ISERR(res)) {
905 + len = -EIO;
906 + goto out;
907 + }
908 + cnt -= res;
909 + pos += res;
910 + }
911 +out:
912 + spin_unlock_irqrestore(&lock, flags);
913 +
914 + return len;
915 +}
916 +
917 +int cfe_printk(const char *fmt, ...)
918 +{
919 + va_list args;
920 + int res;
921 +
922 + va_start(args, fmt);
923 + res = cfe_vprintk(fmt, args);
924 + va_end(args);
925 +
926 + return res;
927 +}
928 +
929 +static int cfe_iocb_dispatch(struct cfe_iocb *iocb)
930 +{
931 + if (!cfe_present())
932 + return CFE_ERR_UNSUPPORTED;
933 + return cfe_trampoline((long)cfe_handle, (long)iocb);
934 +}
935 +
936 +int cfe_present(void)
937 +{
938 + return (cfe_trampoline != NULL);
939 +}
940 +
941 +int cfe_close(int handle)
942 +{
943 + struct cfe_iocb iocb;
944 + int err;
945 +
946 + memset(&iocb, 0, sizeof(iocb));
947 + iocb.fcode = CFE_CMD_DEV_CLOSE;
948 + iocb.handle = handle;
949 +
950 + err = cfe_iocb_dispatch(&iocb);
951 +
952 + return (CFE_ISERR(err)) ? err : iocb.status;
953 +}
954 +
955 +int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1)
956 +{
957 + struct cfe_iocb iocb;
958 + int err;
959 +
960 + memset(&iocb, 0, sizeof(iocb));
961 + iocb.fcode = CFE_CMD_FW_CPUCTL;
962 + iocb.psize = sizeof(struct cfe_iocb_cpuctl);
963 + iocb.cpuctl.number = cpu;
964 + iocb.cpuctl.command = CFE_CPU_CMD_START;
965 + iocb.cpuctl.gp = gp;
966 + iocb.cpuctl.sp = sp;
967 + iocb.cpuctl.a1 = a1;
968 + iocb.cpuctl.start_addr = (long)fn;
969 +
970 + err = cfe_iocb_dispatch(&iocb);
971 +
972 + return (CFE_ISERR(err)) ? err : iocb.status;
973 +}
974 +
975 +int cfe_cpu_stop(int cpu)
976 +{
977 + struct cfe_iocb iocb;
978 + int err;
979 +
980 + memset(&iocb, 0, sizeof(iocb));
981 + iocb.fcode = CFE_CMD_FW_CPUCTL;
982 + iocb.psize = sizeof(struct cfe_iocb_cpuctl);
983 + iocb.cpuctl.number = cpu;
984 + iocb.cpuctl.command = CFE_CPU_CMD_STOP;
985 +
986 + err = cfe_iocb_dispatch(&iocb);
987 +
988 + return (CFE_ISERR(err)) ? err : iocb.status;
989 +}
990 +
991 +int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen)
992 +{
993 + struct cfe_iocb iocb;
994 + int err;
995 +
996 + memset(&iocb, 0, sizeof(iocb));
997 + iocb.fcode = CFE_CMD_ENV_ENUM;
998 + iocb.psize = sizeof(struct cfe_iocb_envbuf);
999 + iocb.envbuf.index = idx;
1000 + iocb.envbuf.name = PTR_TO_CFE(name);
1001 + iocb.envbuf.name_len = namelen;
1002 + iocb.envbuf.val = PTR_TO_CFE(val);
1003 + iocb.envbuf.val_len = vallen;
1004 +
1005 + err = cfe_iocb_dispatch(&iocb);
1006 +
1007 + return (CFE_ISERR(err)) ? err : iocb.status;
1008 +}
1009 +
1010 +int cfe_enumdev(int idx, char *name, int namelen)
1011 +{
1012 + struct cfe_iocb iocb;
1013 + int err;
1014 +
1015 + memset(&iocb, 0, sizeof(iocb));
1016 +
1017 + iocb.fcode = CFE_CMD_DEV_ENUM;
1018 + iocb.psize = sizeof(struct cfe_iocb_envbuf);
1019 + iocb.envbuf.index = idx;
1020 + iocb.envbuf.name = PTR_TO_CFE(name);
1021 + iocb.envbuf.name_len = namelen;
1022 +
1023 + err = cfe_iocb_dispatch(&iocb);
1024 +
1025 + return (CFE_ISERR(err)) ? err : iocb.status;
1026 +}
1027 +
1028 +int cfe_enummem(int idx, int flags, u64 *start, u64 *length,
1029 + u64 *type)
1030 +{
1031 + struct cfe_iocb iocb;
1032 + int err;
1033 +
1034 + memset(&iocb, 0, sizeof(iocb));
1035 +
1036 + iocb.fcode = CFE_CMD_FW_MEMENUM;
1037 + iocb.flags = flags;
1038 + iocb.psize = sizeof(struct cfe_iocb_meminfo);
1039 + iocb.meminfo.index = idx;
1040 +
1041 + err = cfe_iocb_dispatch(&iocb);
1042 + if (CFE_ISERR(err))
1043 + return err;
1044 + if (!CFE_ISERR(iocb.status)) {
1045 + *start = iocb.meminfo.addr;
1046 + *length = iocb.meminfo.size;
1047 + *type = iocb.meminfo.type;
1048 + }
1049 +
1050 + return iocb.status;
1051 +}
1052 +
1053 +int cfe_exit(int warm, int status)
1054 +{
1055 + struct cfe_iocb iocb;
1056 + int err;
1057 +
1058 +printk("CFE REBOOT\n");
1059 + memset(&iocb, 0, sizeof(iocb));
1060 + iocb.fcode = CFE_CMD_FW_RESTART;
1061 + if (warm)
1062 + iocb.flags = CFE_FLG_WARMSTART;
1063 + iocb.psize = sizeof(struct cfe_iocb_exitstat);
1064 + iocb.exitstat.status = status;
1065 +
1066 +printk("CALL\n");
1067 + err = cfe_iocb_dispatch(&iocb);
1068 +printk("DONE\n");
1069 +
1070 + return (CFE_ISERR(err)) ? err : iocb.status;
1071 +}
1072 +
1073 +int cfe_flushcache(int flags)
1074 +{
1075 + struct cfe_iocb iocb;
1076 + int err;
1077 +
1078 + memset(&iocb, 0, sizeof(iocb));
1079 + iocb.fcode = CFE_CMD_FW_FLUSHCACHE;
1080 + iocb.flags = flags;
1081 +
1082 + err = cfe_iocb_dispatch(&iocb);
1083 +
1084 + return (CFE_ISERR(err)) ? err : iocb.status;
1085 +}
1086 +
1087 +int cfe_getdevinfo(char *name)
1088 +{
1089 + struct cfe_iocb iocb;
1090 + int err;
1091 +
1092 + memset(&iocb, 0, sizeof(iocb));
1093 + iocb.fcode = CFE_CMD_DEV_GETINFO;
1094 + iocb.psize = sizeof(struct cfe_iocb_buf);
1095 + iocb.buffer.ptr = PTR_TO_CFE(name);
1096 + iocb.buffer.length = strlen(name);
1097 +
1098 + err = cfe_iocb_dispatch(&iocb);
1099 + if (CFE_ISERR(err))
1100 + return err;
1101 + if (CFE_ISERR(iocb.status))
1102 + return iocb.status;
1103 +
1104 + return iocb.buffer.devflags;
1105 +}
1106 +
1107 +int cfe_getenv(char *name, char *dest, int destlen)
1108 +{
1109 + struct cfe_iocb iocb;
1110 + int err;
1111 +
1112 + dest[0] = '\0';
1113 + memset(&iocb, 0, sizeof(iocb));
1114 + iocb.fcode = CFE_CMD_ENV_GET;
1115 + iocb.psize = sizeof(struct cfe_iocb_envbuf);
1116 + iocb.envbuf.name = PTR_TO_CFE(name);
1117 + iocb.envbuf.name_len = strlen(name);
1118 + iocb.envbuf.val = PTR_TO_CFE(dest);
1119 + iocb.envbuf.val_len = destlen;
1120 +
1121 + err = cfe_iocb_dispatch(&iocb);
1122 +
1123 + return (CFE_ISERR(err)) ? err : iocb.status;
1124 +}
1125 +
1126 +int cfe_getfwinfo(struct cfe_fwinfo *info)
1127 +{
1128 + struct cfe_iocb iocb;
1129 + int err;
1130 +
1131 + memset(&iocb, 0, sizeof(iocb));
1132 + iocb.fcode = CFE_CMD_FW_GETINFO;
1133 + iocb.psize = sizeof(struct cfe_iocb_fwinfo);
1134 +
1135 + err = cfe_iocb_dispatch(&iocb);
1136 + if (CFE_ISERR(err))
1137 + return err;
1138 + if (CFE_ISERR(iocb.status))
1139 + return err;
1140 +
1141 + info->version = iocb.fwinfo.version;
1142 + info->totalmem = iocb.fwinfo.totalmem;
1143 + info->flags = iocb.fwinfo.flags;
1144 + info->boardid = iocb.fwinfo.boardid;
1145 + info->bootarea_va = iocb.fwinfo.bootarea_va;
1146 + info->bootarea_pa = iocb.fwinfo.bootarea_pa;
1147 + info->bootarea_size = iocb.fwinfo.bootarea_size;
1148 +
1149 + return iocb.status;
1150 +}
1151 +
1152 +int cfe_getstdhandle(int handletype)
1153 +{
1154 + struct cfe_iocb iocb;
1155 + int err;
1156 +
1157 + memset(&iocb, 0, sizeof(iocb));
1158 + iocb.fcode = CFE_CMD_DEV_GETHANDLE;
1159 + iocb.flags = handletype;
1160 +
1161 + err = cfe_iocb_dispatch(&iocb);
1162 + if (CFE_ISERR(err))
1163 + return err;
1164 + if (CFE_ISERR(iocb.status))
1165 + return iocb.status;
1166 +
1167 + return iocb.handle;
1168 +}
1169 +
1170 +int cfe_getticks(s64 *ticks)
1171 +{
1172 + struct cfe_iocb iocb;
1173 + int err;
1174 +
1175 + memset(&iocb, 0, sizeof(iocb));
1176 + iocb.fcode = CFE_CMD_FW_GETTIME;
1177 + iocb.psize = sizeof(struct cfe_iocb_time);
1178 +
1179 + err = cfe_iocb_dispatch(&iocb);
1180 + if (CFE_ISERR(err))
1181 + return err;
1182 + if (!CFE_ISERR(iocb.status))
1183 + *ticks = iocb.time.ticks;
1184 +
1185 + return iocb.status;
1186 +}
1187 +
1188 +int cfe_inpstat(int handle)
1189 +{
1190 + struct cfe_iocb iocb;
1191 + int err;
1192 +
1193 + memset(&iocb, 0, sizeof(iocb));
1194 + iocb.fcode = CFE_CMD_DEV_INPSTAT;
1195 + iocb.handle = handle;
1196 + iocb.psize = sizeof(struct cfe_iocb_inpstat);
1197 +
1198 + err = cfe_iocb_dispatch(&iocb);
1199 + if (CFE_ISERR(err))
1200 + return err;
1201 + if (CFE_ISERR(iocb.status))
1202 + return iocb.status;
1203 +
1204 + return iocb.inpstat.status;
1205 +}
1206 +
1207 +int cfe_ioctl(int handle, unsigned int ioctlnum,
1208 + unsigned char *buffer, int length,
1209 + int *retlen, u64 offset)
1210 +{
1211 + struct cfe_iocb iocb;
1212 + int err;
1213 +
1214 + memset(&iocb, 0, sizeof(iocb));
1215 + iocb.fcode = CFE_CMD_DEV_IOCTL;
1216 + iocb.handle = handle;
1217 + iocb.psize = sizeof(struct cfe_iocb_buf);
1218 + iocb.buffer.offset = offset;
1219 + iocb.buffer.ioctlcmd = ioctlnum;
1220 + iocb.buffer.ptr = PTR_TO_CFE(buffer);
1221 + iocb.buffer.length = length;
1222 +
1223 + err = cfe_iocb_dispatch(&iocb);
1224 + if (CFE_ISERR(err))
1225 + return err;
1226 + if (CFE_ISERR(iocb.status))
1227 + return iocb.status;
1228 + if (retlen)
1229 + *retlen = iocb.buffer.retlen;
1230 +
1231 + return iocb.status;
1232 +}
1233 +
1234 +int cfe_open(char *name)
1235 +{
1236 + struct cfe_iocb iocb;
1237 + int err;
1238 +
1239 + memset(&iocb, 0, sizeof(iocb));
1240 + iocb.fcode = CFE_CMD_DEV_OPEN;
1241 + iocb.psize = sizeof(struct cfe_iocb_buf);
1242 + iocb.buffer.ptr = PTR_TO_CFE(name);
1243 + iocb.buffer.length = strlen(name);
1244 +
1245 + err = cfe_iocb_dispatch(&iocb);
1246 + if (CFE_ISERR(err))
1247 + return err;
1248 + if (CFE_ISERR(iocb.status))
1249 + return iocb.status;
1250 +
1251 + return iocb.handle;
1252 +}
1253 +
1254 +int cfe_read(int handle, unsigned char *buffer, int length)
1255 +{
1256 + return cfe_readblk(handle, 0, buffer, length);
1257 +}
1258 +
1259 +int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length)
1260 +{
1261 + struct cfe_iocb iocb;
1262 + int err;
1263 +
1264 + memset(&iocb, 0, sizeof(iocb));
1265 + iocb.fcode = CFE_CMD_DEV_READ;
1266 + iocb.handle = handle;
1267 + iocb.psize = sizeof(struct cfe_iocb_buf);
1268 + iocb.buffer.offset = offset;
1269 + iocb.buffer.ptr = PTR_TO_CFE(buffer);
1270 + iocb.buffer.length = length;
1271 +
1272 + err = cfe_iocb_dispatch(&iocb);
1273 + if (CFE_ISERR(err))
1274 + return err;
1275 + if (CFE_ISERR(iocb.status))
1276 + return iocb.status;
1277 +
1278 + return iocb.buffer.retlen;
1279 +}
1280 +
1281 +int cfe_setenv(char *name, char *val)
1282 +{
1283 + struct cfe_iocb iocb;
1284 + int err;
1285 +
1286 + memset(&iocb, 0, sizeof(iocb));
1287 + iocb.fcode = CFE_CMD_ENV_SET;
1288 + iocb.psize = sizeof(struct cfe_iocb_envbuf);
1289 + iocb.envbuf.name = PTR_TO_CFE(name);
1290 + iocb.envbuf.name_len = strlen(name);
1291 + iocb.envbuf.val = PTR_TO_CFE(val);
1292 + iocb.envbuf.val_len = strlen(val);
1293 +
1294 + err = cfe_iocb_dispatch(&iocb);
1295 +
1296 + return (CFE_ISERR(err)) ? err : iocb.status;
1297 +}
1298 +
1299 +int cfe_write(int handle, unsigned char *buffer, int length)
1300 +{
1301 + return cfe_writeblk(handle, 0, buffer, length);
1302 +}
1303 +
1304 +int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length)
1305 +{
1306 + struct cfe_iocb iocb;
1307 + int err;
1308 +
1309 + memset(&iocb, 0, sizeof(iocb));
1310 + iocb.fcode = CFE_CMD_DEV_WRITE;
1311 + iocb.handle = handle;
1312 + iocb.psize = sizeof(struct cfe_iocb_buf);
1313 + iocb.buffer.offset = offset;
1314 + iocb.buffer.ptr = PTR_TO_CFE(buffer);
1315 + iocb.buffer.length = length;
1316 +
1317 + err = cfe_iocb_dispatch(&iocb);
1318 + if (CFE_ISERR(err))
1319 + return err;
1320 + if (CFE_ISERR(iocb.status))
1321 + return iocb.status;
1322 +
1323 + return iocb.buffer.retlen;
1324 +}
1325 diff -urN linux.old/arch/mips/cfe/cfe_private.h linux.dev/arch/mips/cfe/cfe_private.h
1326 --- linux.old/arch/mips/cfe/cfe_private.h 1970-01-01 01:00:00.000000000 +0100
1327 +++ linux.dev/arch/mips/cfe/cfe_private.h 2007-01-25 23:34:01.000000000 +0100
1328 @@ -0,0 +1,176 @@
1329 +/*
1330 + * Broadcom Common Firmware Environment (CFE) support
1331 + *
1332 + * Copyright 2000, 2001, 2002
1333 + * Broadcom Corporation. All rights reserved.
1334 + *
1335 + * Copyright (C) 2006 Michael Buesch
1336 + *
1337 + * Original Authors: Mitch Lichtenberg, Chris Demetriou
1338 + *
1339 + * This software is furnished under license and may be used and copied only
1340 + * in accordance with the following terms and conditions. Subject to these
1341 + * conditions, you may download, copy, install, use, modify and distribute
1342 + * modified or unmodified copies of this software in source and/or binary
1343 + * form. No title or ownership is transferred hereby.
1344 + *
1345 + * 1) Any source code used, modified or distributed must reproduce and
1346 + * retain this copyright notice and list of conditions as they appear in
1347 + * the source file.
1348 + *
1349 + * 2) No right is granted to use any trade name, trademark, or logo of
1350 + * Broadcom Corporation. The "Broadcom Corporation" name may not be
1351 + * used to endorse or promote products derived from this software
1352 + * without the prior written permission of Broadcom Corporation.
1353 + *
1354 + * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
1355 + * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
1356 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
1357 + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
1358 + * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
1359 + * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1360 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1361 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
1362 + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
1363 + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
1364 + * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1365 + */
1366 +
1367 +#ifndef LINUX_CFE_PRIVATE_H_
1368 +#define LINUX_CFE_PRIVATE_H_
1369 +
1370 +#ifndef __ASSEMBLY__
1371 +
1372 +/* Seal indicating CFE's presence, passed to the kernel. */
1373 +#define CFE_EPTSEAL 0x43464531
1374 +
1375 +#define CFE_CMD_FW_GETINFO 0
1376 +#define CFE_CMD_FW_RESTART 1
1377 +#define CFE_CMD_FW_BOOT 2
1378 +#define CFE_CMD_FW_CPUCTL 3
1379 +#define CFE_CMD_FW_GETTIME 4
1380 +#define CFE_CMD_FW_MEMENUM 5
1381 +#define CFE_CMD_FW_FLUSHCACHE 6
1382 +
1383 +#define CFE_CMD_DEV_GETHANDLE 9
1384 +#define CFE_CMD_DEV_ENUM 10
1385 +#define CFE_CMD_DEV_OPEN 11
1386 +#define CFE_CMD_DEV_INPSTAT 12
1387 +#define CFE_CMD_DEV_READ 13
1388 +#define CFE_CMD_DEV_WRITE 14
1389 +#define CFE_CMD_DEV_IOCTL 15
1390 +#define CFE_CMD_DEV_CLOSE 16
1391 +#define CFE_CMD_DEV_GETINFO 17
1392 +
1393 +#define CFE_CMD_ENV_ENUM 20
1394 +#define CFE_CMD_ENV_GET 22
1395 +#define CFE_CMD_ENV_SET 23
1396 +#define CFE_CMD_ENV_DEL 24
1397 +
1398 +#define CFE_CMD_MAX 32
1399 +
1400 +#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */
1401 +
1402 +typedef u64 cfe_uint_t;
1403 +typedef s64 cfe_int_t;
1404 +typedef s64 cfe_ptr_t;
1405 +
1406 +/* Cast a pointer from native to CFE-API pointer and back */
1407 +#define CFE_TO_PTR(p) ((void *)(unsigned long)(p))
1408 +#define PTR_TO_CFE(p) ((cfe_ptr_t)(unsigned long)(p))
1409 +
1410 +struct cfe_iocb_buf {
1411 + cfe_uint_t offset; /* offset on device (bytes) */
1412 + cfe_ptr_t ptr; /* pointer to a buffer */
1413 + cfe_uint_t length; /* length of this buffer */
1414 + cfe_uint_t retlen; /* returned length (for read ops) */
1415 + union {
1416 + cfe_uint_t ioctlcmd; /* IOCTL command (used only for IOCTLs) */
1417 + cfe_uint_t devflags; /* Returned device info flags */
1418 + };
1419 +};
1420 +
1421 +struct cfe_iocb_inpstat {
1422 + cfe_uint_t status; /* 1 means input available */
1423 +};
1424 +
1425 +struct cfe_iocb_envbuf {
1426 + cfe_int_t index; /* 0-based enumeration index */
1427 + cfe_ptr_t name; /* name string buffer */
1428 + cfe_int_t name_len; /* size of name buffer */
1429 + cfe_ptr_t val; /* value string buffer */
1430 + cfe_int_t val_len; /* size of value string buffer */
1431 +};
1432 +
1433 +struct cfe_iocb_cpuctl {
1434 + cfe_uint_t number; /* cpu number to control */
1435 + cfe_uint_t command; /* command to issue to CPU */
1436 + cfe_uint_t start_addr; /* CPU start address */
1437 + cfe_uint_t gp; /* starting GP value */
1438 + cfe_uint_t sp; /* starting SP value */
1439 + cfe_uint_t a1; /* starting A1 value */
1440 +};
1441 +
1442 +struct cfe_iocb_time {
1443 + cfe_int_t ticks; /* current time in ticks */
1444 +};
1445 +
1446 +struct cfe_iocb_exitstat {
1447 + cfe_int_t status;
1448 +};
1449 +
1450 +struct cfe_iocb_meminfo {
1451 + cfe_int_t index; /* 0-based enumeration index */
1452 + cfe_int_t type; /* type of memory block */
1453 + cfe_uint_t addr; /* physical start address */
1454 + cfe_uint_t size; /* block size */
1455 +};
1456 +
1457 +struct cfe_iocb_fwinfo {
1458 + cfe_int_t version; /* major, minor, eco version */
1459 + cfe_int_t totalmem; /* total installed mem */
1460 + cfe_int_t flags; /* various flags */
1461 + cfe_int_t boardid; /* board ID */
1462 + cfe_int_t bootarea_va; /* VA of boot area */
1463 + cfe_int_t bootarea_pa; /* PA of boot area */
1464 + cfe_int_t bootarea_size; /* size of boot area */
1465 + cfe_int_t reserved1;
1466 + cfe_int_t reserved2;
1467 + cfe_int_t reserved3;
1468 +};
1469 +
1470 +/* CFE I/O Control Block */
1471 +struct cfe_iocb {
1472 + cfe_uint_t fcode; /* IOCB function code */
1473 + cfe_int_t status; /* return status */
1474 + cfe_int_t handle; /* file/device handle */
1475 + cfe_uint_t flags; /* flags for this IOCB */
1476 + cfe_uint_t psize; /* size of parameter list */
1477 + union {
1478 + struct cfe_iocb_buf buffer; /* buffer parameters */
1479 + struct cfe_iocb_inpstat inpstat; /* input status parameters */
1480 + struct cfe_iocb_envbuf envbuf; /* environment function parameters */
1481 + struct cfe_iocb_cpuctl cpuctl; /* CPU control parameters */
1482 + struct cfe_iocb_time time; /* timer parameters */
1483 + struct cfe_iocb_meminfo meminfo; /* memory arena info parameters */
1484 + struct cfe_iocb_fwinfo fwinfo; /* firmware information */
1485 + struct cfe_iocb_exitstat exitstat; /* Exit Status */
1486 + };
1487 +};
1488 +
1489 +
1490 +#include <linux/init.h>
1491 +
1492 +void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1,
1493 + unsigned long fwarg2, unsigned long fwarg3);
1494 +
1495 +#else /* __ASSEMBLY__ */
1496 +
1497 + .macro cfe_early_init
1498 +#ifdef CONFIG_CFE
1499 + jal cfe_setup
1500 +#endif
1501 + .endm
1502 +
1503 +#endif /* __ASSEMBLY__ */
1504 +#endif /* LINUX_CFE_PRIVATE_H_ */
1505 diff -urN linux.old/arch/mips/cfe/Makefile linux.dev/arch/mips/cfe/Makefile
1506 --- linux.old/arch/mips/cfe/Makefile 1970-01-01 01:00:00.000000000 +0100
1507 +++ linux.dev/arch/mips/cfe/Makefile 2007-01-25 23:34:01.000000000 +0100
1508 @@ -0,0 +1,5 @@
1509 +#
1510 +# Makefile for the Broadcom Common Firmware Environment support
1511 +#
1512 +
1513 +obj-y += cfe.o
1514 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
1515 --- linux.old/arch/mips/Kconfig 2007-01-26 00:51:33.000000000 +0100
1516 +++ linux.dev/arch/mips/Kconfig 2007-01-26 00:51:18.000000000 +0100
1517 @@ -4,6 +4,10 @@
1518 # Horrible source of confusion. Die, die, die ...
1519 select EMBEDDED
1520
1521 +config CFE
1522 + bool
1523 + # Common Firmware Environment
1524 +
1525 mainmenu "Linux/MIPS Kernel Configuration"
1526
1527 menu "Machine selection"
1528 @@ -222,6 +226,24 @@
1529 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
1530 Olivetti M700-10 workstations.
1531
1532 +config BCM947XX
1533 + bool "Support for BCM947xx based boards"
1534 + select DMA_NONCOHERENT
1535 + select HW_HAS_PCI
1536 + select IRQ_CPU
1537 + select SYS_HAS_CPU_MIPS32_R1
1538 + select SYS_SUPPORTS_32BIT_KERNEL
1539 + select SYS_SUPPORTS_LITTLE_ENDIAN
1540 + select SSB
1541 + select SSB_SERIAL
1542 + select SSB_DRIVER_PCICORE
1543 + select SSB_PCICORE_HOSTMODE
1544 + select SSB_DRIVER_MIPS
1545 + select SSB_DRIVER_EXTIF
1546 + select CFE
1547 + help
1548 + Support for BCM947xx based boards
1549 +
1550 config LASAT
1551 bool "LASAT Networks platforms"
1552 select DMA_NONCOHERENT
1553 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
1554 --- linux.old/arch/mips/kernel/cpu-probe.c 2007-01-26 00:51:33.000000000 +0100
1555 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2007-01-25 23:34:01.000000000 +0100
1556 @@ -723,6 +723,28 @@
1557 }
1558
1559
1560 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
1561 +{
1562 + decode_config1(c);
1563 + switch (c->processor_id & 0xff00) {
1564 + case PRID_IMP_BCM3302:
1565 + c->cputype = CPU_BCM3302;
1566 + c->isa_level = MIPS_CPU_ISA_M32R1;
1567 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1568 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
1569 + break;
1570 + case PRID_IMP_BCM4710:
1571 + c->cputype = CPU_BCM4710;
1572 + c->isa_level = MIPS_CPU_ISA_M32R1;
1573 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1574 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
1575 + break;
1576 + default:
1577 + c->cputype = CPU_UNKNOWN;
1578 + break;
1579 + }
1580 +}
1581 +
1582 __init void cpu_probe(void)
1583 {
1584 struct cpuinfo_mips *c = &current_cpu_data;
1585 @@ -745,6 +767,9 @@
1586 case PRID_COMP_SIBYTE:
1587 cpu_probe_sibyte(c);
1588 break;
1589 + case PRID_COMP_BROADCOM:
1590 + cpu_probe_broadcom(c);
1591 + break;
1592 case PRID_COMP_SANDCRAFT:
1593 cpu_probe_sandcraft(c);
1594 break;
1595 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
1596 --- linux.old/arch/mips/kernel/proc.c 2007-01-26 00:51:33.000000000 +0100
1597 +++ linux.dev/arch/mips/kernel/proc.c 2007-01-25 23:34:01.000000000 +0100
1598 @@ -83,6 +83,8 @@
1599 [CPU_VR4181] = "NEC VR4181",
1600 [CPU_VR4181A] = "NEC VR4181A",
1601 [CPU_SR71000] = "Sandcraft SR71000",
1602 + [CPU_BCM3302] = "Broadcom BCM3302",
1603 + [CPU_BCM4710] = "Broadcom BCM4710",
1604 [CPU_PR4450] = "Philips PR4450",
1605 };
1606
1607 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
1608 --- linux.old/arch/mips/Makefile 2007-01-26 00:51:33.000000000 +0100
1609 +++ linux.dev/arch/mips/Makefile 2007-01-25 23:34:01.000000000 +0100
1610 @@ -571,6 +571,18 @@
1611 load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
1612
1613 #
1614 +# Broadcom BCM47XX boards
1615 +#
1616 +core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/
1617 +cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include -Iinclude/asm-mips/mach-bcm947xx
1618 +load-$(CONFIG_BCM947XX) := 0xffffffff80001000
1619 +
1620 +#
1621 +# Common Firmware Environment
1622 +#
1623 +core-$(CONFIG_CFE) += arch/mips/cfe/
1624 +
1625 +#
1626 # SNI RM200 PCI
1627 #
1628 core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/
1629 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
1630 --- linux.old/arch/mips/mm/tlbex.c 2007-01-26 00:51:33.000000000 +0100
1631 +++ linux.dev/arch/mips/mm/tlbex.c 2007-01-25 23:34:01.000000000 +0100
1632 @@ -880,6 +880,8 @@
1633 case CPU_4KSC:
1634 case CPU_20KC:
1635 case CPU_25KF:
1636 + case CPU_BCM3302:
1637 + case CPU_BCM4710:
1638 tlbw(p);
1639 break;
1640
1641 diff -urN linux.old/drivers/Kconfig linux.dev/drivers/Kconfig
1642 --- linux.old/drivers/Kconfig 2007-01-26 00:51:33.000000000 +0100
1643 +++ linux.dev/drivers/Kconfig 2007-01-25 23:34:01.000000000 +0100
1644 @@ -56,6 +56,8 @@
1645
1646 source "drivers/hwmon/Kconfig"
1647
1648 +source "drivers/ssb/Kconfig"
1649 +
1650 source "drivers/mfd/Kconfig"
1651
1652 source "drivers/media/Kconfig"
1653 diff -urN linux.old/drivers/Makefile linux.dev/drivers/Makefile
1654 --- linux.old/drivers/Makefile 2007-01-26 00:51:33.000000000 +0100
1655 +++ linux.dev/drivers/Makefile 2007-01-25 23:34:01.000000000 +0100
1656 @@ -77,3 +77,4 @@
1657 obj-$(CONFIG_SUPERH) += sh/
1658 obj-$(CONFIG_GENERIC_TIME) += clocksource/
1659 obj-$(CONFIG_DMA_ENGINE) += dma/
1660 +obj-$(CONFIG_SSB) += ssb/
1661 diff -urN linux.old/drivers/ssb/core.c linux.dev/drivers/ssb/core.c
1662 --- linux.old/drivers/ssb/core.c 1970-01-01 01:00:00.000000000 +0100
1663 +++ linux.dev/drivers/ssb/core.c 2007-01-26 00:44:13.000000000 +0100
1664 @@ -0,0 +1,805 @@
1665 +/*
1666 + * Sonics Silicon Backplane
1667 + * Subsystem core
1668 + *
1669 + * Copyright 2005, Broadcom Corporation
1670 + * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1671 + *
1672 + * Licensed under the GNU/GPL. See COPYING for details.
1673 + */
1674 +
1675 +#include "ssb_private.h"
1676 +
1677 +#include <linux/delay.h>
1678 +#include <linux/ssb/ssb.h>
1679 +#include <linux/ssb/ssb_regs.h>
1680 +
1681 +#ifdef CONFIG_SSB_PCIHOST
1682 +# include <linux/pci.h>
1683 +#endif
1684 +
1685 +#ifdef CONFIG_SSB_PCMCIAHOST
1686 +# include <pcmcia/cs_types.h>
1687 +# include <pcmcia/cs.h>
1688 +# include <pcmcia/cistpl.h>
1689 +# include <pcmcia/ds.h>
1690 +#endif
1691 +
1692 +
1693 +MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
1694 +MODULE_LICENSE("GPL");
1695 +
1696 +
1697 +static LIST_HEAD(attach_queue);
1698 +static LIST_HEAD(buses);
1699 +static int nr_buses;
1700 +static DEFINE_MUTEX(buses_mutex);
1701 +
1702 +#define ssb_buses_lock() do { \
1703 + if (!is_early_boot()) \
1704 + mutex_lock(&buses_mutex); \
1705 + } while (0)
1706 +
1707 +#define ssb_buses_unlock() do { \
1708 + if (!is_early_boot()) \
1709 + mutex_unlock(&buses_mutex); \
1710 + } while (0)
1711 +
1712 +
1713 +static struct ssb_device * ssb_device_get(struct ssb_device *dev)
1714 +{
1715 + if (dev)
1716 + get_device(&dev->dev);
1717 + return dev;
1718 +}
1719 +
1720 +static void ssb_device_put(struct ssb_device *dev)
1721 +{
1722 + if (dev)
1723 + put_device(&dev->dev);
1724 +}
1725 +
1726 +static void ssb_bus_resume(struct ssb_bus *bus)
1727 +{
1728 +printk("SSB BUS RESUME\n");
1729 + ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1730 + ssb_chipco_resume(&bus->chipco);
1731 +}
1732 +
1733 +static int ssb_device_resume(struct device *dev)
1734 +{
1735 + struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
1736 + struct ssb_driver *ssb_drv;
1737 + struct ssb_bus *bus;
1738 + int err = 0;
1739 +
1740 +printk("SSB DEV RESUME\n");
1741 + bus = ssb_dev->bus;
1742 + if (bus->suspend_cnt == bus->nr_devices)
1743 + ssb_bus_resume(bus);
1744 + bus->suspend_cnt--;
1745 + if (dev->driver) {
1746 + ssb_drv = drv_to_ssb_drv(dev->driver);
1747 + if (ssb_drv && ssb_drv->resume)
1748 + err = ssb_drv->resume(ssb_dev);
1749 + if (err)
1750 + goto out;
1751 + }
1752 +out:
1753 + return err;
1754 +}
1755 +
1756 +static void ssb_bus_suspend(struct ssb_bus *bus, pm_message_t state)
1757 +{
1758 +printk("SSB BUS SUSPEND\n");
1759 +// ssb_chipco_suspend(&bus->chipco, state);
1760 +// ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1761 +}
1762 +
1763 +static int ssb_device_suspend(struct device *dev, pm_message_t state)
1764 +{
1765 + struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
1766 + struct ssb_driver *ssb_drv;
1767 + struct ssb_bus *bus;
1768 + int err = 0;
1769 +
1770 +printk("SSB DEV SUSPEND\n");
1771 + if (dev->driver) {
1772 + ssb_drv = drv_to_ssb_drv(dev->driver);
1773 + if (ssb_drv && ssb_drv->suspend)
1774 + err = ssb_drv->suspend(ssb_dev, state);
1775 + if (err)
1776 + goto out;
1777 + }
1778 +
1779 + bus = ssb_dev->bus;
1780 + bus->suspend_cnt++;
1781 + if (bus->suspend_cnt == bus->nr_devices) {
1782 + /* All devices suspended. Shutdown the bus. */
1783 + ssb_bus_suspend(bus, state);
1784 + }
1785 +
1786 +out:
1787 + return err;
1788 +}
1789 +
1790 +static void ssb_device_shutdown(struct device *dev)
1791 +{
1792 + struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
1793 + struct ssb_driver *ssb_drv;
1794 +
1795 + if (!dev->driver)
1796 + return;
1797 + ssb_drv = drv_to_ssb_drv(dev->driver);
1798 + if (ssb_drv && ssb_drv->shutdown)
1799 + ssb_drv->shutdown(ssb_dev);
1800 +}
1801 +
1802 +static int ssb_device_remove(struct device *dev)
1803 +{
1804 + struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
1805 + struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
1806 +
1807 + if (ssb_drv && ssb_drv->remove)
1808 + ssb_drv->remove(ssb_dev);
1809 + ssb_device_put(ssb_dev);
1810 +
1811 + return 0;
1812 +}
1813 +
1814 +static int ssb_device_probe(struct device *dev)
1815 +{
1816 + struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
1817 + struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
1818 + int err = 0;
1819 +
1820 + ssb_device_get(ssb_dev);
1821 + if (ssb_drv && ssb_drv->probe)
1822 + err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
1823 + if (err)
1824 + ssb_device_put(ssb_dev);
1825 +
1826 + return err;
1827 +}
1828 +
1829 +static int ssb_match_devid(const struct ssb_device_id *tabid,
1830 + const struct ssb_device_id *devid)
1831 +{
1832 + if ((tabid->vendor != devid->vendor) &&
1833 + tabid->vendor != SSB_ANY_VENDOR)
1834 + return 0;
1835 + if ((tabid->coreid != devid->coreid) &&
1836 + tabid->coreid != SSB_ANY_ID)
1837 + return 0;
1838 + if ((tabid->revision != devid->revision) &&
1839 + tabid->revision != SSB_ANY_REV)
1840 + return 0;
1841 + return 1;
1842 +}
1843 +
1844 +static int ssb_bus_match(struct device *dev, struct device_driver *drv)
1845 +{
1846 + struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
1847 + struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
1848 + const struct ssb_device_id *id;
1849 +
1850 + for (id = ssb_drv->id_table;
1851 + id->vendor || id->coreid || id->revision;
1852 + id++) {
1853 + if (ssb_match_devid(id, &ssb_dev->id))
1854 + return 1; /* found */
1855 + }
1856 +
1857 + return 0;
1858 +}
1859 +
1860 +struct bus_type ssb_bustype = {
1861 + .name = NULL, /* Intentionally NULL to indicate early boot */
1862 + .match = ssb_bus_match,
1863 + .probe = ssb_device_probe,
1864 + .remove = ssb_device_remove,
1865 + .shutdown = ssb_device_shutdown,
1866 + .suspend = ssb_device_suspend,
1867 + .resume = ssb_device_resume,
1868 +};
1869 +
1870 +#define is_early_boot() (ssb_bustype.name == NULL)
1871 +
1872 +void ssb_bus_unregister(struct ssb_bus *bus)
1873 +{
1874 + struct ssb_device *dev;
1875 + int i;
1876 +
1877 + ssb_buses_lock();
1878 + for (i = bus->nr_devices - 1; i >= 0; i--) {
1879 + dev = &(bus->devices[i]);
1880 + device_unregister(&dev->dev);
1881 + }
1882 + list_del(&bus->list);
1883 + ssb_buses_unlock();
1884 +
1885 + ssb_iounmap(bus);
1886 +}
1887 +EXPORT_SYMBOL(ssb_bus_unregister);
1888 +
1889 +static void ssb_release_dev(struct device *dev)
1890 +{
1891 + /* Nothing, devices are allocated together with struct ssb_bus. */
1892 +}
1893 +
1894 +/* Needs ssb_buses_lock() */
1895 +static int ssb_attach_queued_buses(void)
1896 +{
1897 + struct ssb_bus *bus, *n;
1898 + struct ssb_device *dev;
1899 + int i, err;
1900 +
1901 + list_for_each_entry_safe(bus, n, &attach_queue, list) {
1902 + for (i = 0; i < bus->nr_devices; i++) {
1903 + dev = &(bus->devices[i]);
1904 +
1905 + dev->dev.release = ssb_release_dev;
1906 + err = device_register(&dev->dev);
1907 + if (err) {
1908 + ssb_printk(KERN_ERR PFX
1909 + "Could not register %s\n",
1910 + dev->dev.bus_id);
1911 + }
1912 + }
1913 + list_move_tail(&bus->list, &buses);
1914 + }
1915 + return 0;
1916 +}
1917 +
1918 +static void ssb_get_boardtype(struct ssb_bus *bus)
1919 +{//FIXME for pcmcia?
1920 + if (bus->bustype != SSB_BUSTYPE_PCI) {
1921 + /* Must set board_vendor, board_type and board_rev
1922 + * before calling ssb_bus_*_register() */
1923 + assert(bus->board_vendor && bus->board_type);
1924 + return;
1925 + }
1926 + ssb_pci_get_boardtype(bus);
1927 +}
1928 +
1929 +static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
1930 +{
1931 + struct ssb_bus *bus = dev->bus;
1932 +
1933 + offset += dev->core_index * SSB_CORE_SIZE;
1934 + return readw(bus->mmio + offset);
1935 +}
1936 +
1937 +static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
1938 +{
1939 + struct ssb_bus *bus = dev->bus;
1940 +
1941 + offset += dev->core_index * SSB_CORE_SIZE;
1942 + return readl(bus->mmio + offset);
1943 +}
1944 +
1945 +static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
1946 +{
1947 + struct ssb_bus *bus = dev->bus;
1948 +
1949 + offset += dev->core_index * SSB_CORE_SIZE;
1950 + writew(value, bus->mmio + offset);
1951 +}
1952 +
1953 +static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
1954 +{
1955 + struct ssb_bus *bus = dev->bus;
1956 +
1957 + offset += dev->core_index * SSB_CORE_SIZE;
1958 + writel(value, bus->mmio + offset);
1959 +}
1960 +
1961 +static const struct ssb_bus_ops ssb_ssb_ops = {
1962 + .read16 = ssb_ssb_read16,
1963 + .read32 = ssb_ssb_read32,
1964 + .write16 = ssb_ssb_write16,
1965 + .write32 = ssb_ssb_write32,
1966 +};
1967 +
1968 +static int ssb_bus_register(struct ssb_bus *bus,
1969 + unsigned long baseaddr)
1970 +{
1971 + int err;
1972 +
1973 + ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on ");
1974 + switch (bus->bustype) {
1975 + case SSB_BUSTYPE_SSB:
1976 + ssb_printk("address 0x%08lX\n", baseaddr);
1977 + break;
1978 + case SSB_BUSTYPE_PCI:
1979 +#ifdef CONFIG_SSB_PCIHOST
1980 + ssb_printk("PCI device %s\n", bus->host_pci->dev.bus_id);
1981 +#endif
1982 + break;
1983 + case SSB_BUSTYPE_PCMCIA:
1984 +#ifdef CONFIG_SSB_PCMCIAHOST
1985 + ssb_printk("PCMCIA device %s\n", bus->host_pcmcia->devname);
1986 +#endif
1987 + break;
1988 + }
1989 +
1990 + spin_lock_init(&bus->bar_lock);
1991 + INIT_LIST_HEAD(&bus->list);
1992 +
1993 + ssb_get_boardtype(bus);
1994 + /* Powerup the bus */
1995 + err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1996 + if (err)
1997 + goto out;
1998 + ssb_buses_lock();
1999 + bus->busnumber = nr_buses;
2000 + /* Scan for devices (cores) */
2001 + err = ssb_bus_scan(bus, baseaddr);
2002 + if (err)
2003 + goto err_disable_xtal;
2004 +
2005 + /* Init PCI-host device (if any) */
2006 + err = ssb_pci_init(bus);
2007 + if (err)
2008 + goto err_unmap;
2009 + /* Init PCMCIA-host device (if any) */
2010 + err = ssb_pcmcia_init(bus);
2011 + if (err)
2012 + goto err_unmap;
2013 +
2014 + /* Initialize basic system devices (if available) */
2015 + ssb_chipcommon_init(&bus->chipco);
2016 + ssb_mipscore_init(&bus->mipscore);
2017 + ssb_pcicore_init(&bus->pcicore);
2018 +
2019 + /* Queue it for attach */
2020 + list_add_tail(&bus->list, &attach_queue);
2021 + if (!is_early_boot()) {
2022 + /* This is not early boot, so we must attach the bus now */
2023 + err = ssb_attach_queued_buses();
2024 + if (err)
2025 + goto err_dequeue;
2026 + }
2027 + nr_buses++;
2028 + ssb_buses_unlock();
2029 +
2030 +out:
2031 + return err;
2032 +
2033 +err_dequeue:
2034 + list_del(&bus->list);
2035 +err_unmap:
2036 + ssb_iounmap(bus);
2037 +err_disable_xtal:
2038 + ssb_buses_unlock();
2039 + ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
2040 + goto out;
2041 +}
2042 +
2043 +#ifdef CONFIG_SSB_PCIHOST
2044 +int ssb_bus_pcibus_register(struct ssb_bus *bus,
2045 + struct pci_dev *host_pci)
2046 +{
2047 + int err;
2048 +
2049 + bus->bustype = SSB_BUSTYPE_PCI;
2050 + bus->host_pci = host_pci;
2051 + bus->ops = &ssb_pci_ops;
2052 +
2053 + err = ssb_bus_register(bus, 0);
2054 +
2055 + return err;
2056 +}
2057 +EXPORT_SYMBOL(ssb_bus_pcibus_register);
2058 +#endif /* CONFIG_SSB_PCIHOST */
2059 +
2060 +#ifdef CONFIG_SSB_PCMCIAHOST
2061 +int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
2062 + struct pcmcia_device *pcmcia_dev,
2063 + unsigned long baseaddr,
2064 + void (*fill_sprom)(struct ssb_sprom *sprom))
2065 +{
2066 + int err;
2067 +
2068 + bus->bustype = SSB_BUSTYPE_PCMCIA;
2069 + bus->host_pcmcia = pcmcia_dev;
2070 + bus->ops = &ssb_pcmcia_ops;
2071 + fill_sprom(&bus->sprom);
2072 +
2073 + err = ssb_bus_register(bus, baseaddr);
2074 +
2075 + return err;
2076 +}
2077 +EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
2078 +#endif /* CONFIG_SSB_PCMCIAHOST */
2079 +
2080 +int ssb_bus_ssbbus_register(struct ssb_bus *bus,
2081 + unsigned long baseaddr,
2082 + void (*fill_sprom)(struct ssb_sprom *sprom))
2083 +{
2084 + int err;
2085 +
2086 + bus->bustype = SSB_BUSTYPE_SSB;
2087 + bus->ops = &ssb_ssb_ops;
2088 + fill_sprom(&bus->sprom);
2089 + err = ssb_bus_register(bus, baseaddr);
2090 +
2091 + return err;
2092 +}
2093 +
2094 +int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
2095 +{
2096 + drv->drv.name = drv->name;
2097 + drv->drv.bus = &ssb_bustype;
2098 + drv->drv.owner = owner;
2099 +
2100 + return driver_register(&drv->drv);
2101 +}
2102 +EXPORT_SYMBOL(__ssb_driver_register);
2103 +
2104 +void ssb_driver_unregister(struct ssb_driver *drv)
2105 +{
2106 + driver_unregister(&drv->drv);
2107 +}
2108 +EXPORT_SYMBOL(ssb_driver_unregister);
2109 +
2110 +void ssb_set_devtypedata(struct ssb_device *dev, void *data)
2111 +{
2112 + struct ssb_bus *bus = dev->bus;
2113 + struct ssb_device *ent;
2114 + int i;
2115 +
2116 + for (i = 0; i < bus->nr_devices; i++) {
2117 + ent = &(bus->devices[i]);
2118 + if (ent->id.vendor != dev->id.vendor)
2119 + continue;
2120 + if (ent->id.coreid != dev->id.coreid)
2121 + continue;
2122 +
2123 + ent->devtypedata = data;
2124 + }
2125 +}
2126 +EXPORT_SYMBOL(ssb_set_devtypedata);
2127 +
2128 +static u32 clkfactor_f6_resolve(u32 v)
2129 +{
2130 + /* map the magic values */
2131 + switch (v) {
2132 + case SSB_CHIPCO_CLK_F6_2:
2133 + return 2;
2134 + case SSB_CHIPCO_CLK_F6_3:
2135 + return 3;
2136 + case SSB_CHIPCO_CLK_F6_4:
2137 + return 4;
2138 + case SSB_CHIPCO_CLK_F6_5:
2139 + return 5;
2140 + case SSB_CHIPCO_CLK_F6_6:
2141 + return 6;
2142 + case SSB_CHIPCO_CLK_F6_7:
2143 + return 7;
2144 + }
2145 + return 0;
2146 +}
2147 +
2148 +/* Calculate the speed the backplane would run at a given set of clockcontrol values */
2149 +u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
2150 +{
2151 + u32 n1, n2, clock, m1, m2, m3, mc;
2152 +
2153 + n1 = (n & SSB_CHIPCO_CLK_N1);
2154 + n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
2155 +
2156 + switch (plltype) {
2157 + case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
2158 + if (m & SSB_CHIPCO_CLK_T6_MMASK)
2159 + return SSB_CHIPCO_CLK_T6_M0;
2160 + return SSB_CHIPCO_CLK_T6_M1;
2161 + case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
2162 + case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
2163 + case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
2164 + case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
2165 + n1 = clkfactor_f6_resolve(n1);
2166 + n2 += SSB_CHIPCO_CLK_F5_BIAS;
2167 + break;
2168 + case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
2169 + n1 += SSB_CHIPCO_CLK_T2_BIAS;
2170 + n2 += SSB_CHIPCO_CLK_T2_BIAS;
2171 + assert((n1 >= 2) && (n1 <= 7));
2172 + assert((n2 >= 5) && (n2 <= 23));
2173 + break;
2174 + case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
2175 + return 100000000;
2176 + default:
2177 + assert(0);
2178 + }
2179 +
2180 + switch (plltype) {
2181 + case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
2182 + case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
2183 + clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
2184 + break;
2185 + default:
2186 + clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
2187 + }
2188 + if (!clock)
2189 + return 0;
2190 +
2191 + m1 = (m & SSB_CHIPCO_CLK_M1);
2192 + m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
2193 + m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
2194 + mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
2195 +
2196 + switch (plltype) {
2197 + case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
2198 + case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
2199 + case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
2200 + case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
2201 + m1 = clkfactor_f6_resolve(m1);
2202 + if ((plltype == SSB_PLLTYPE_1) ||
2203 + (plltype == SSB_PLLTYPE_3))
2204 + m2 += SSB_CHIPCO_CLK_F5_BIAS;
2205 + else
2206 + m2 = clkfactor_f6_resolve(m2);
2207 + m3 = clkfactor_f6_resolve(m3);
2208 +
2209 + switch (mc) {
2210 + case SSB_CHIPCO_CLK_MC_BYPASS:
2211 + return clock;
2212 + case SSB_CHIPCO_CLK_MC_M1:
2213 + return (clock / m1);
2214 + case SSB_CHIPCO_CLK_MC_M1M2:
2215 + return (clock / (m1 * m2));
2216 + case SSB_CHIPCO_CLK_MC_M1M2M3:
2217 + return (clock / (m1 * m2 * m3));
2218 + case SSB_CHIPCO_CLK_MC_M1M3:
2219 + return (clock / (m1 * m3));
2220 + }
2221 + return 0;
2222 + case SSB_PLLTYPE_2:
2223 + m1 += SSB_CHIPCO_CLK_T2_BIAS;
2224 + m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
2225 + m3 += SSB_CHIPCO_CLK_T2_BIAS;
2226 + assert((m1 >= 2) && (m1 <= 7));
2227 + assert((m2 >= 3) && (m2 <= 10));
2228 + assert((m3 >= 2) && (m3 <= 7));
2229 +
2230 + if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
2231 + clock /= m1;
2232 + if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
2233 + clock /= m2;
2234 + if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
2235 + clock /= m3;
2236 + return clock;
2237 + default:
2238 + assert(0);
2239 + }
2240 + return 0;
2241 +}
2242 +
2243 +/* Get the current speed the backplane is running at */
2244 +u32 ssb_clockspeed(struct ssb_bus *bus)
2245 +{
2246 + u32 rate;
2247 + u32 plltype;
2248 + u32 clkctl_n, clkctl_m;
2249 +
2250 + //TODO if EXTIF: PLLTYPE == 1, read n from clockcontrol_n, m from clockcontrol_sb
2251 +
2252 + if (bus->chipco.dev) {
2253 + ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
2254 + &clkctl_n, &clkctl_m);
2255 + } else
2256 + return 0;
2257 +
2258 + if (bus->chip_id == 0x5365) {
2259 + rate = 100000000;
2260 + } else {
2261 + rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
2262 + if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
2263 + rate /= 2;
2264 + }
2265 +
2266 + return rate;
2267 +}
2268 +EXPORT_SYMBOL(ssb_clockspeed);
2269 +
2270 +int ssb_device_is_enabled(struct ssb_device *dev)
2271 +{
2272 + u32 val;
2273 +
2274 + val = ssb_read32(dev, SSB_TMSLOW);
2275 + val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT;
2276 +
2277 + return (val == SSB_TMSLOW_CLOCK);
2278 +}
2279 +EXPORT_SYMBOL(ssb_device_is_enabled);
2280 +
2281 +void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
2282 +{
2283 + u32 val;
2284 +
2285 + ssb_device_disable(dev, core_specific_flags);
2286 + ssb_write32(dev, SSB_TMSLOW,
2287 + SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
2288 + SSB_TMSLOW_FGC | core_specific_flags);
2289 + /* flush */
2290 + ssb_read32(dev, SSB_TMSLOW);
2291 + udelay(1);
2292 +
2293 + /* Clear SERR if set. This is a hw bug workaround. */
2294 + if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
2295 + ssb_write32(dev, SSB_TMSHIGH, 0);
2296 +
2297 + val = ssb_read32(dev, SSB_IMSTATE);
2298 + if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
2299 + val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
2300 + ssb_write32(dev, SSB_IMSTATE, val);
2301 + }
2302 +
2303 + ssb_write32(dev, SSB_TMSLOW,
2304 + SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
2305 + core_specific_flags);
2306 + /* flush */
2307 + ssb_read32(dev, SSB_TMSLOW);
2308 + udelay(1);
2309 +
2310 + ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
2311 + core_specific_flags);
2312 + /* flush */
2313 + ssb_read32(dev, SSB_TMSLOW);
2314 + udelay(1);
2315 +}
2316 +EXPORT_SYMBOL(ssb_device_enable);
2317 +
2318 +static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
2319 + int timeout, int set)
2320 +{
2321 + int i;
2322 + u32 val;
2323 +
2324 + for (i = 0; i < timeout; i++) {
2325 + val = ssb_read32(dev, reg);
2326 + if (set) {
2327 + if (val & bitmask)
2328 + return 0;
2329 + } else {
2330 + if (!(val & bitmask))
2331 + return 0;
2332 + }
2333 + udelay(10);
2334 + }
2335 + printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
2336 + "register %04X to %s.\n",
2337 + bitmask, reg, (set ? "set" : "clear"));
2338 +
2339 + return -ETIMEDOUT;
2340 +}
2341 +
2342 +void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
2343 +{
2344 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
2345 + return;
2346 +
2347 + ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT | SSB_TMSLOW_CLOCK);
2348 + ssb_wait_bit(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT, 1000, 1);
2349 + ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
2350 + ssb_write32(dev, SSB_TMSLOW,
2351 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
2352 + SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET |
2353 + core_specific_flags);
2354 + /* flush */
2355 + ssb_read32(dev, SSB_TMSLOW);
2356 + udelay(1);
2357 +
2358 + ssb_write32(dev, SSB_TMSLOW,
2359 + SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET |
2360 + core_specific_flags);
2361 + /* flush */
2362 + ssb_read32(dev, SSB_TMSLOW);
2363 + udelay(1);
2364 +}
2365 +EXPORT_SYMBOL(ssb_device_disable);
2366 +
2367 +u32 ssb_dma_translation(struct ssb_device *dev)
2368 +{
2369 + switch(dev->bus->bustype) {
2370 + case SSB_BUSTYPE_SSB:
2371 + return 0;
2372 + case SSB_BUSTYPE_PCI:
2373 + case SSB_BUSTYPE_PCMCIA:
2374 + return SSB_PCI_DMA;
2375 + }
2376 + return 0;
2377 +}
2378 +EXPORT_SYMBOL(ssb_dma_translation);
2379 +
2380 +int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask)
2381 +{
2382 + struct device *dev = &ssb_dev->dev;
2383 +
2384 +#ifdef CONFIG_SSB_PCIHOST
2385 + if (ssb_dev->bus->bustype == SSB_BUSTYPE_PCI &&
2386 + !dma_supported(dev, mask))
2387 + return -EIO;
2388 +#endif
2389 + dev->coherent_dma_mask = mask;
2390 + dev->dma_mask = &dev->coherent_dma_mask;
2391 +
2392 + return 0;
2393 +}
2394 +EXPORT_SYMBOL(ssb_dma_set_mask);
2395 +
2396 +u32 ssb_admatch_base(u32 adm)
2397 +{
2398 + u32 base = 0;
2399 +
2400 + switch (adm & SSB_ADM_TYPE) {
2401 + case SSB_ADM_TYPE0:
2402 + base = (adm & SSB_ADM_BASE0);
2403 + break;
2404 + case SSB_ADM_TYPE1:
2405 + assert(!(adm & SSB_ADM_NEG)); /* unsupported */
2406 + base = (adm & SSB_ADM_BASE1);
2407 + break;
2408 + case SSB_ADM_TYPE2:
2409 + assert(!(adm & SSB_ADM_NEG)); /* unsupported */
2410 + base = (adm & SSB_ADM_BASE2);
2411 + break;
2412 + default:
2413 + assert(0);
2414 + }
2415 +
2416 + return base;
2417 +}
2418 +EXPORT_SYMBOL(ssb_admatch_base);
2419 +
2420 +u32 ssb_admatch_size(u32 adm)
2421 +{
2422 + u32 size = 0;
2423 +
2424 + switch (adm & SSB_ADM_TYPE) {
2425 + case SSB_ADM_TYPE0:
2426 + size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
2427 + break;
2428 + case SSB_ADM_TYPE1:
2429 + assert(!(adm & SSB_ADM_NEG)); /* unsupported */
2430 + size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
2431 + break;
2432 + case SSB_ADM_TYPE2:
2433 + assert(!(adm & SSB_ADM_NEG)); /* unsupported */
2434 + size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
2435 + break;
2436 + default:
2437 + assert(0);
2438 + }
2439 + size = (1 << (size + 1));
2440 +
2441 + return size;
2442 +}
2443 +EXPORT_SYMBOL(ssb_admatch_size);
2444 +
2445 +static int __init ssb_modinit(void)
2446 +{
2447 + int err;
2448 +
2449 + ssb_bustype.name = "ssb";
2450 + err = bus_register(&ssb_bustype);
2451 + if (err)
2452 + return err;
2453 +
2454 + /* Maybe we already registered some buses at early boot.
2455 + * Check for this and attach them
2456 + */
2457 + ssb_buses_lock();
2458 + err = ssb_attach_queued_buses();
2459 + ssb_buses_unlock();
2460 +
2461 + return err;
2462 +}
2463 +subsys_initcall(ssb_modinit);
2464 +
2465 +static void __exit ssb_modexit(void)
2466 +{
2467 + bus_unregister(&ssb_bustype);
2468 +}
2469 +module_exit(ssb_modexit)
2470 diff -urN linux.old/drivers/ssb/driver_chipcommon/chipcommon.c linux.dev/drivers/ssb/driver_chipcommon/chipcommon.c
2471 --- linux.old/drivers/ssb/driver_chipcommon/chipcommon.c 1970-01-01 01:00:00.000000000 +0100
2472 +++ linux.dev/drivers/ssb/driver_chipcommon/chipcommon.c 2007-01-26 00:44:13.000000000 +0100
2473 @@ -0,0 +1,403 @@
2474 +/*
2475 + * Sonics Silicon Backplane
2476 + * Broadcom ChipCommon core driver
2477 + *
2478 + * Copyright 2005, Broadcom Corporation
2479 + * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
2480 + *
2481 + * Licensed under the GNU/GPL. See COPYING for details.
2482 + */
2483 +
2484 +#include <linux/ssb/ssb.h>
2485 +#include <linux/ssb/ssb_regs.h>
2486 +#include <linux/pci.h>
2487 +
2488 +#include "../ssb_private.h"
2489 +
2490 +
2491 +/* Clock sources */
2492 +enum {
2493 + /* PCI clock */
2494 + SSB_CHIPCO_CLKSRC_PCI,
2495 + /* Crystal slow clock oscillator */
2496 + SSB_CHIPCO_CLKSRC_XTALOS,
2497 + /* Low power oscillator */
2498 + SSB_CHIPCO_CLKSRC_LOPWROS,
2499 +};
2500 +
2501 +
2502 +static inline u32 chipco_read32(struct ssb_chipcommon *cc,
2503 + u16 offset)
2504 +{
2505 + return ssb_read32(cc->dev, offset);
2506 +}
2507 +
2508 +static inline void chipco_write32(struct ssb_chipcommon *cc,
2509 + u16 offset,
2510 + u32 value)
2511 +{
2512 + ssb_write32(cc->dev, offset, value);
2513 +}
2514 +
2515 +void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
2516 + enum ssb_clkmode mode)
2517 +{
2518 + struct ssb_device *ccdev = cc->dev;
2519 + struct ssb_bus *bus;
2520 + u32 tmp;
2521 +
2522 + if (!ccdev)
2523 + return;
2524 + bus = ccdev->bus;
2525 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
2526 + if (ccdev->id.revision < 6)
2527 + return;
2528 + /* chipcommon cores rev10 are a whole new ball game */
2529 + if (ccdev->id.revision >= 10)
2530 + return;
2531 + if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
2532 + return;
2533 +
2534 + switch (mode) {
2535 + case SSB_CLKMODE_SLOW:
2536 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
2537 + tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
2538 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
2539 + break;
2540 + case SSB_CLKMODE_FAST:
2541 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
2542 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
2543 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
2544 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
2545 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
2546 + break;
2547 + case SSB_CLKMODE_DYNAMIC:
2548 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
2549 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
2550 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
2551 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
2552 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
2553 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
2554 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
2555 +
2556 + /* for dynamic control, we have to release our xtal_pu "force on" */
2557 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
2558 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
2559 + break;
2560 + default:
2561 + assert(0);
2562 + }
2563 +}
2564 +EXPORT_SYMBOL(ssb_chipco_set_clockmode);
2565 +
2566 +/* Get the Slow Clock Source */
2567 +static int chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
2568 +{
2569 + struct ssb_bus *bus = cc->dev->bus;
2570 + u32 tmp = 0;
2571 +
2572 + if (cc->dev->id.revision < 6) {
2573 + if (bus->bustype == SSB_BUSTYPE_SSB /*TODO ||
2574 + bus->bustype == SSB_BUSTYPE_PCMCIA*/)
2575 + return SSB_CHIPCO_CLKSRC_XTALOS;
2576 + if (bus->bustype == SSB_BUSTYPE_PCI) {
2577 + pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
2578 + if (tmp & 0x10)
2579 + return SSB_CHIPCO_CLKSRC_PCI;
2580 + return SSB_CHIPCO_CLKSRC_XTALOS;
2581 + }
2582 + }
2583 + if (cc->dev->id.revision < 10) {
2584 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
2585 + tmp &= 0x7;
2586 + if (tmp == 0)
2587 + return SSB_CHIPCO_CLKSRC_LOPWROS;
2588 + if (tmp == 1)
2589 + return SSB_CHIPCO_CLKSRC_XTALOS;
2590 + if (tmp == 2)
2591 + return SSB_CHIPCO_CLKSRC_PCI;
2592 + }
2593 +
2594 + return SSB_CHIPCO_CLKSRC_XTALOS;
2595 +}
2596 +
2597 +/* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
2598 +static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
2599 +{
2600 + int limit;
2601 + int clocksrc;
2602 + int divisor;
2603 + u32 tmp;
2604 +
2605 + clocksrc = chipco_pctl_get_slowclksrc(cc);
2606 + if (cc->dev->id.revision < 6) {
2607 + switch (clocksrc) {
2608 + case SSB_CHIPCO_CLKSRC_PCI:
2609 + divisor = 64;
2610 + break;
2611 + case SSB_CHIPCO_CLKSRC_XTALOS:
2612 + divisor = 32;
2613 + break;
2614 + default:
2615 + assert(0);
2616 + divisor = 1;
2617 + }
2618 + } else if (cc->dev->id.revision < 10) {
2619 + switch (clocksrc) {
2620 + case SSB_CHIPCO_CLKSRC_LOPWROS:
2621 + divisor = 1;
2622 + break;
2623 + case SSB_CHIPCO_CLKSRC_XTALOS:
2624 + case SSB_CHIPCO_CLKSRC_PCI:
2625 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
2626 + divisor = (tmp >> 16) + 1;
2627 + divisor *= 4;
2628 + break;
2629 + default:
2630 + assert(0);
2631 + divisor = 1;
2632 + }
2633 + } else {
2634 + tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
2635 + divisor = (tmp >> 16) + 1;
2636 + divisor *= 4;
2637 + }
2638 +
2639 + switch (clocksrc) {
2640 + case SSB_CHIPCO_CLKSRC_LOPWROS:
2641 + if (get_max)
2642 + limit = 43000;
2643 + else
2644 + limit = 25000;
2645 + break;
2646 + case SSB_CHIPCO_CLKSRC_XTALOS:
2647 + if (get_max)
2648 + limit = 20200000;
2649 + else
2650 + limit = 19800000;
2651 + break;
2652 + case SSB_CHIPCO_CLKSRC_PCI:
2653 + if (get_max)
2654 + limit = 34000000;
2655 + else
2656 + limit = 25000000;
2657 + break;
2658 + default:
2659 + assert(0);
2660 + limit = 0;
2661 + }
2662 + limit /= divisor;
2663 +
2664 + return limit;
2665 +}
2666 +
2667 +static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
2668 +{
2669 + struct ssb_bus *bus = cc->dev->bus;
2670 +
2671 + if (bus->chip_id == 0x4321) {
2672 + if (bus->chip_rev == 0)
2673 + chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
2674 + else if (bus->chip_rev == 1)
2675 + chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
2676 + }
2677 +
2678 + if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
2679 + return;
2680 +
2681 + if (cc->dev->id.revision >= 10) {
2682 + /* Set Idle Power clock rate to 1Mhz */
2683 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
2684 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
2685 + 0x0000FFFF) | 0x00040000);
2686 + } else {
2687 + int maxfreq;
2688 +
2689 + maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
2690 + chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
2691 + (maxfreq * 150 + 999999) / 1000000);
2692 + chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
2693 + (maxfreq * 15 + 999999) / 1000000);
2694 + }
2695 +}
2696 +
2697 +static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
2698 +{
2699 + struct ssb_bus *bus = cc->dev->bus;
2700 + int minfreq;
2701 + unsigned int tmp;
2702 + u32 pll_on_delay;
2703 +
2704 + if (bus->bustype != SSB_BUSTYPE_PCI)
2705 + return;
2706 + if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
2707 + return;
2708 +
2709 + minfreq = chipco_pctl_clockfreqlimit(cc, 0);
2710 + pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
2711 + tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
2712 + assert((tmp & ~0xFFFF) == 0);
2713 +
2714 + cc->fast_pwrup_delay = tmp;
2715 +}
2716 +
2717 +void ssb_chipcommon_init(struct ssb_chipcommon *cc)
2718 +{
2719 + if (!cc->dev)
2720 + return; /* We don't have a ChipCommon */
2721 + ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
2722 + chipco_powercontrol_init(cc);
2723 + calc_fast_powerup_delay(cc);
2724 +}
2725 +
2726 +void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state)
2727 +{
2728 + if (!cc->dev)
2729 + return;
2730 + ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
2731 +}
2732 +
2733 +void ssb_chipco_resume(struct ssb_chipcommon *cc)
2734 +{
2735 + if (!cc->dev)
2736 + return;
2737 + ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
2738 + chipco_powercontrol_init(cc);
2739 +}
2740 +
2741 +void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
2742 + u32 *plltype, u32 *n, u32 *m)
2743 +{
2744 + *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
2745 + *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
2746 + switch (*plltype) {
2747 + case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
2748 + *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
2749 + break;
2750 + case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
2751 + if (cc->dev->bus->chip_id != 0x5365) {
2752 + *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
2753 + break;
2754 + }
2755 + /* Fallthough */
2756 + default:
2757 + *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
2758 + }
2759 +}
2760 +
2761 +void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
2762 + unsigned long ns)
2763 +{
2764 + struct ssb_device *dev = cc->dev;
2765 + struct ssb_bus *bus = dev->bus;
2766 + u32 tmp;
2767 +
2768 + /* set register for external IO to control LED. */
2769 + chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
2770 + tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
2771 + tmp |= ceildiv(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */
2772 + tmp |= ceildiv(240, ns); /* Waitcount-0 = 240ns */
2773 + chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
2774 +
2775 + /* Set timing for the flash */
2776 + tmp = ceildiv(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */
2777 + tmp |= ceildiv(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */
2778 + tmp |= ceildiv(120, ns); /* Waitcount-0 = 120nS */
2779 + if ((bus->chip_id == 0x5365) ||
2780 + (dev->id.revision < 9))
2781 + chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
2782 + if ((bus->chip_id == 0x5365) ||
2783 + (dev->id.revision < 9) ||
2784 + ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
2785 + chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
2786 +
2787 + if (bus->chip_id == 0x5350) {
2788 + /* Enable EXTIF */
2789 + tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
2790 + tmp |= ceildiv(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */
2791 + tmp |= ceildiv(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
2792 + tmp |= ceildiv(120, ns); /* Waitcount-0 = 120ns */
2793 + chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
2794 + }
2795 +}
2796 +
2797 +
2798 +#ifdef CONFIG_SSB_SERIAL
2799 +int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
2800 + struct ssb_serial_port *ports)
2801 +{
2802 + struct ssb_bus *bus = cc->dev->bus;
2803 + int nr_ports = 0;
2804 + u32 plltype;
2805 + unsigned int irq;
2806 + u32 baud_base, div;
2807 + u32 i, n;
2808 +
2809 + plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
2810 + irq = ssb_mips_irq(cc->dev);
2811 +
2812 + if (plltype == SSB_PLLTYPE_1) {
2813 + /* PLL clock */
2814 + baud_base = ssb_calc_clock_rate(plltype,
2815 + chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
2816 + chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
2817 + div = 1;
2818 + } else {
2819 + if (cc->dev->id.revision >= 11) {
2820 + /* Fixed ALP clock */
2821 + baud_base = 20000000;
2822 + div = 1;
2823 + /* Set the override bit so we don't divide it */
2824 + chipco_write32(cc, SSB_CHIPCO_CORECTL,
2825 + SSB_CHIPCO_CORECTL_UARTCLK0);
2826 + } else if (cc->dev->id.revision >= 3) {
2827 + /* Internal backplane clock */
2828 + baud_base = ssb_clockspeed(bus);
2829 + div = 2; /* Minimum divisor */
2830 + chipco_write32(cc, SSB_CHIPCO_CLKDIV,
2831 + (chipco_read32(cc, SSB_CHIPCO_CLKDIV)
2832 + & ~SSB_CHIPCO_CLKDIV_UART) | div);
2833 + } else {
2834 + /* Fixed internal backplane clock */
2835 + baud_base = 88000000;
2836 + div = 48;
2837 + }
2838 +
2839 + /* Clock source depends on strapping if UartClkOverride is unset */
2840 + if ((cc->dev->id.revision > 0) &&
2841 + !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
2842 + if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
2843 + SSB_CHIPCO_CAP_UARTCLK_INT) {
2844 + /* Internal divided backplane clock */
2845 + baud_base /= div;
2846 + } else {
2847 + /* Assume external clock of 1.8432 MHz */
2848 + baud_base = 1843200;
2849 + }
2850 + }
2851 + }
2852 +
2853 + /* Determine the registers of the UARTs */
2854 + n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
2855 + for (i = 0; i < n; i++) {
2856 + void __iomem *cc_mmio;
2857 + void __iomem *uart_regs;
2858 +
2859 + cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
2860 + uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
2861 + /* Offset changed at after rev 0 */
2862 + if (cc->dev->id.revision == 0)
2863 + uart_regs += (i * 8);
2864 + else
2865 + uart_regs += (i * 256);
2866 +
2867 + nr_ports++;
2868 + ports[i].regs = uart_regs;
2869 + ports[i].irq = irq;
2870 + ports[i].baud_base = baud_base;
2871 + ports[i].reg_shift = 0;
2872 + }
2873 +
2874 + return nr_ports;
2875 +}
2876 +#endif /* CONFIG_SSB_SERIAL */
2877 diff -urN linux.old/drivers/ssb/driver_mips/mips.c linux.dev/drivers/ssb/driver_mips/mips.c
2878 --- linux.old/drivers/ssb/driver_mips/mips.c 1970-01-01 01:00:00.000000000 +0100
2879 +++ linux.dev/drivers/ssb/driver_mips/mips.c 2007-01-26 00:44:13.000000000 +0100
2880 @@ -0,0 +1,258 @@
2881 +/*
2882 + * Sonics Silicon Backplane
2883 + * Broadcom MIPS core driver
2884 + *
2885 + * Copyright 2005, Broadcom Corporation
2886 + * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
2887 + *
2888 + * Licensed under the GNU/GPL. See COPYING for details.
2889 + */
2890 +
2891 +#include <linux/ssb/ssb.h>
2892 +
2893 +#include <linux/serial.h>
2894 +#include <linux/serial_core.h>
2895 +#include <linux/serial_reg.h>
2896 +#include <asm/time.h>
2897 +
2898 +#include "../ssb_private.h"
2899 +
2900 +
2901 +static inline u32 mips_read32(struct ssb_mipscore *mcore,
2902 + u16 offset)
2903 +{
2904 + return ssb_read32(mcore->dev, offset);
2905 +}
2906 +
2907 +static inline void mips_write32(struct ssb_mipscore *mcore,
2908 + u16 offset,
2909 + u32 value)
2910 +{
2911 + ssb_write32(mcore->dev, offset, value);
2912 +}
2913 +
2914 +static const u32 ipsflag_irq_mask[] = {
2915 + 0,
2916 + SSB_IPSFLAG_IRQ1,
2917 + SSB_IPSFLAG_IRQ2,
2918 + SSB_IPSFLAG_IRQ3,
2919 + SSB_IPSFLAG_IRQ4,
2920 +};
2921 +
2922 +static const u32 ipsflag_irq_shift[] = {
2923 + 0,
2924 + SSB_IPSFLAG_IRQ1_SHIFT,
2925 + SSB_IPSFLAG_IRQ2_SHIFT,
2926 + SSB_IPSFLAG_IRQ3_SHIFT,
2927 + SSB_IPSFLAG_IRQ4_SHIFT,
2928 +};
2929 +
2930 +static inline u32 ssb_irqflag(struct ssb_device *dev)
2931 +{
2932 + return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
2933 +}
2934 +
2935 +/* Get the MIPS IRQ assignment for a specified device.
2936 + * If unassigned, 0 is returned.
2937 + */
2938 +unsigned int ssb_mips_irq(struct ssb_device *dev)
2939 +{
2940 + struct ssb_bus *bus = dev->bus;
2941 + u32 irqflag;
2942 + u32 ipsflag;
2943 + u32 tmp;
2944 + unsigned int irq;
2945 +
2946 + irqflag = ssb_irqflag(dev);
2947 + ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
2948 + for (irq = 1; irq <= 4; irq++) {
2949 + tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
2950 + if (tmp == irqflag)
2951 + break;
2952 + }
2953 + if (irq == 5)
2954 + irq = 0;
2955 +
2956 + return irq;
2957 +}
2958 +
2959 +static void clear_irq(struct ssb_bus *bus, unsigned int irq)
2960 +{
2961 + struct ssb_device *dev = bus->mipscore.dev;
2962 +
2963 + /* Clear the IRQ in the MIPScore backplane registers */
2964 + if (irq == 0) {
2965 + ssb_write32(dev, SSB_INTVEC, 0);
2966 + } else {
2967 + ssb_write32(dev, SSB_IPSFLAG,
2968 + ssb_read32(dev, SSB_IPSFLAG) |
2969 + ipsflag_irq_mask[irq]);
2970 + }
2971 +}
2972 +
2973 +static void set_irq(struct ssb_device *dev, unsigned int irq)
2974 +{
2975 + unsigned int oldirq = ssb_mips_irq(dev);
2976 + struct ssb_bus *bus = dev->bus;
2977 + struct ssb_device *mdev = bus->mipscore.dev;
2978 + u32 irqflag = ssb_irqflag(dev);
2979 +
2980 + dev->irq = irq + 2;
2981 +
2982 + ssb_dprintk(KERN_INFO PFX
2983 + "set_irq: core 0x%04x, irq %d => %d\n",
2984 + dev->id.coreid, oldirq, irq);
2985 + /* clear the old irq */
2986 + if (oldirq == 0)
2987 + ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
2988 + else
2989 + clear_irq(bus, oldirq);
2990 +
2991 + /* assign the new one */
2992 + if (irq == 0)
2993 + ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
2994 +
2995 + irqflag <<= ipsflag_irq_shift[irq];
2996 + irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
2997 + ssb_write32(mdev, SSB_IPSFLAG, irqflag);
2998 +}
2999 +
3000 +/* XXX: leave here or move into separate extif driver? */
3001 +static int ssb_extif_serial_init(struct ssb_device *dev, struct ssb_serial_ports *ports)
3002 +{
3003 +
3004 +}
3005 +
3006 +
3007 +static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
3008 +{
3009 + struct ssb_bus *bus = mcore->dev->bus;
3010 +
3011 + //TODO if (EXTIF available
3012 +#if 0
3013 + extifregs_t *eir = (extifregs_t *) regs;
3014 + sbconfig_t *sb;
3015 +
3016 + /* Determine external UART register base */
3017 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
3018 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
3019 +
3020 + /* Determine IRQ */
3021 + irq = sb_irq(sbh);
3022 +
3023 + /* Disable GPIO interrupt initially */
3024 + W_REG(&eir->gpiointpolarity, 0);
3025 + W_REG(&eir->gpiointmask, 0);
3026 +
3027 + /* Search for external UARTs */
3028 + n = 2;
3029 + for (i = 0; i < 2; i++) {
3030 + regs = (void *) REG_MAP(base + (i * 8), 8);
3031 + if (BCMINIT(serial_exists)(regs)) {
3032 + /* Set GPIO 1 to be the external UART IRQ */
3033 + W_REG(&eir->gpiointmask, 2);
3034 + if (add)
3035 + add(regs, irq, 13500000, 0);
3036 + }
3037 + }
3038 +
3039 + /* Add internal UART if enabled */
3040 + if (R_REG(&eir->corecontrol) & CC_UE)
3041 + if (add)
3042 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
3043 +
3044 +#endif
3045 + if (bus->extif.dev)
3046 + mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
3047 + else if (bus->chipco.dev)
3048 + mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
3049 + else
3050 + mcore->nr_serial_ports = 0;
3051 +}
3052 +
3053 +static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
3054 +{
3055 + struct ssb_bus *bus = mcore->dev->bus;
3056 +
3057 + if (bus->chipco.dev) {
3058 + mcore->flash_window = 0x1c000000;
3059 + mcore->flash_window_size = 0x800000;
3060 + } else {
3061 + mcore->flash_window = 0x1fc00000;
3062 + mcore->flash_window_size = 0x400000;
3063 + }
3064 +}
3065 +
3066 +
3067 +static void ssb_cpu_clock(struct ssb_mipscore *mcore)
3068 +{
3069 +}
3070 +
3071 +void ssb_mipscore_init(struct ssb_mipscore *mcore)
3072 +{
3073 + struct ssb_bus *bus = mcore->dev->bus;
3074 + struct ssb_device *dev;
3075 + unsigned long hz, ns;
3076 + unsigned int irq, i;
3077 +
3078 + if (!mcore->dev)
3079 + return; /* We don't have a MIPS core */
3080 +
3081 + ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
3082 +
3083 + hz = ssb_clockspeed(bus);
3084 + if (!hz)
3085 + hz = 100000000;
3086 + ns = 1000000000 / hz;
3087 +
3088 +//TODO
3089 +#if 0
3090 + if (have EXTIF) {
3091 + /* Initialize extif so we can get to the LEDs and external UART */
3092 + W_REG(&eir->prog_config, CF_EN);
3093 +
3094 + /* Set timing for the flash */
3095 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
3096 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
3097 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
3098 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
3099 +
3100 + /* Set programmable interface timing for external uart */
3101 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
3102 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
3103 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
3104 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
3105 + W_REG(&eir->prog_waitcount, tmp);
3106 + }
3107 + else... chipcommon
3108 +#endif
3109 + if (bus->chipco.dev)
3110 + ssb_chipco_timing_init(&bus->chipco, ns);
3111 +
3112 + /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
3113 + for (irq = 2, i = 0; i < bus->nr_devices; i++) {
3114 + dev = &(bus->devices[i]);
3115 + dev->irq = ssb_mips_irq(dev) + 2;
3116 + switch(dev->id.coreid) {
3117 + case SSB_DEV_USB11_HOST:
3118 + /* shouldn't need a separate irq line for non-4710, most of them have a proper
3119 + * external usb controller on the pci */
3120 + if ((bus->chip_id == 0x4710) && (irq <= 4)) {
3121 + set_irq(dev, irq++);
3122 + break;
3123 + }
3124 + case SSB_DEV_PCI:
3125 + case SSB_DEV_ETHERNET:
3126 + case SSB_DEV_80211:
3127 + case SSB_DEV_USB20_HOST:
3128 + /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
3129 + if (irq <= 4) {
3130 + set_irq(dev, irq++);
3131 + break;
3132 + }
3133 + }
3134 + }
3135 +
3136 + ssb_mips_serial_init(mcore);
3137 + ssb_mips_flash_detect(mcore);
3138 +}
3139 diff -urN linux.old/drivers/ssb/driver_pci/pcicore.c linux.dev/drivers/ssb/driver_pci/pcicore.c
3140 --- linux.old/drivers/ssb/driver_pci/pcicore.c 1970-01-01 01:00:00.000000000 +0100
3141 +++ linux.dev/drivers/ssb/driver_pci/pcicore.c 2007-01-26 20:19:19.000000000 +0100
3142 @@ -0,0 +1,549 @@
3143 +/*
3144 + * Sonics Silicon Backplane
3145 + * Broadcom PCI-core driver
3146 + *
3147 + * Copyright 2005, Broadcom Corporation
3148 + * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
3149 + *
3150 + * Licensed under the GNU/GPL. See COPYING for details.
3151 + */
3152 +
3153 +#include <linux/ssb/ssb.h>
3154 +#include <linux/pci.h>
3155 +#include <linux/delay.h>
3156 +
3157 +#include "../ssb_private.h"
3158 +
3159 +static inline
3160 +u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
3161 +{
3162 + return ssb_read32(pc->dev, offset);
3163 +}
3164 +
3165 +static inline
3166 +void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
3167 +{
3168 + ssb_write32(pc->dev, offset, value);
3169 +}
3170 +
3171 +/**************************************************
3172 + * Code for hostmode operation.
3173 + **************************************************/
3174 +
3175 +#ifdef CONFIG_SSB_PCICORE_HOSTMODE
3176 +
3177 +#include <asm/paccess.h>
3178 +/* Read the bus and catch bus exceptions. This is MIPS specific. */
3179 +#define mips_busprobe(val, addr) get_dbe((val), (addr))
3180 +
3181 +/* Assume one-hot slot wiring */
3182 +#define SSB_PCI_SLOT_MAX 16
3183 +
3184 +/* Global lock is OK, as we won't have more than one extpci anyway. */
3185 +static DEFINE_SPINLOCK(cfgspace_lock);
3186 +/* Core to access the external PCI config space. Can only have one. */
3187 +static struct ssb_pcicore *extpci_core;
3188 +
3189 +u32 pci_iobase = 0x100;
3190 +u32 pci_membase = SSB_PCI_DMA;
3191 +
3192 +int pcibios_plat_dev_init(struct pci_dev *d)
3193 +{
3194 + struct resource *res;
3195 + int pos, size;
3196 + u32 *base;
3197 +
3198 + printk("PCI: Fixing up device %s\n", pci_name(d));
3199 +
3200 + /* Fix up resource bases */
3201 + for (pos = 0; pos < 6; pos++) {
3202 + res = &d->resource[pos];
3203 + base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
3204 + if (res->end) {
3205 + size = res->end - res->start + 1;
3206 + if (*base & (size - 1))
3207 + *base = (*base + size) & ~(size - 1);
3208 + res->start = *base;
3209 + res->end = res->start + size - 1;
3210 + *base += size;
3211 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
3212 + }
3213 + /* Fix up PCI bridge BAR0 only */
3214 + if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
3215 + break;
3216 + }
3217 + /* Fix up interrupt lines */
3218 + d->irq = ssb_mips_irq(extpci_core->dev) + 2;
3219 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
3220 +
3221 + return 0;
3222 +}
3223 +
3224 +static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
3225 +{
3226 + if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
3227 + return;
3228 +
3229 + printk("PCI: fixing up bridge\n");
3230 +
3231 + /* Enable PCI bridge bus mastering and memory space */
3232 + pci_set_master(dev);
3233 + pcibios_enable_device(dev, ~0);
3234 +
3235 + /* Enable PCI bridge BAR1 prefetch and burst */
3236 + pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
3237 +}
3238 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
3239 +
3240 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
3241 +{
3242 + return ssb_mips_irq(extpci_core->dev) + 2;
3243 +}
3244 +
3245 +static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
3246 + unsigned int bus, unsigned int dev,
3247 + unsigned int func, unsigned int off)
3248 +{
3249 + u32 addr = 0;
3250 + u32 tmp;
3251 +
3252 + if (unlikely(pc->cardbusmode && dev > 1))
3253 + goto out;
3254 + if (bus == 0) {//FIXME busnumber ok?
3255 + /* Type 0 transaction */
3256 + if (unlikely(dev >= SSB_PCI_SLOT_MAX))
3257 + goto out;
3258 + /* Slide the window */
3259 + tmp = SSB_PCICORE_SBTOPCI_CFG0;
3260 + tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
3261 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
3262 + /* Calculate the address */
3263 + addr = SSB_PCI_CFG;
3264 + addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
3265 + addr |= (func << 8);
3266 + addr |= (off & ~3);
3267 + } else {
3268 + /* Type 1 transaction */
3269 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
3270 + SSB_PCICORE_SBTOPCI_CFG1);
3271 + /* Calculate the address */
3272 + addr = SSB_PCI_CFG;
3273 + addr |= (bus << 16);
3274 + addr |= (dev << 11);
3275 + addr |= (func << 8);
3276 + addr |= (off & ~3);
3277 + }
3278 +out:
3279 + return addr;
3280 +}
3281 +
3282 +static int ssb_extpci_read_config(struct ssb_pcicore *pc,
3283 + unsigned int bus, unsigned int dev,
3284 + unsigned int func, unsigned int off,
3285 + void *buf, int len)
3286 +{
3287 + int err = -EINVAL;
3288 + u32 addr, val;
3289 + void __iomem *mmio;
3290 +
3291 + assert(pc->hostmode);
3292 + if (unlikely(len != 1 && len != 2 && len != 4))
3293 + goto out;
3294 + addr = get_cfgspace_addr(pc, bus, dev, func, off);
3295 + if (unlikely(!addr))
3296 + goto out;
3297 + err = -ENOMEM;
3298 + mmio = ioremap_nocache(addr, len);
3299 + if (!mmio)
3300 + goto out;
3301 +
3302 + if (mips_busprobe(val, (u32 *) mmio)) {
3303 + val = 0xffffffff;
3304 + goto unmap;
3305 + }
3306 +
3307 + val = readl(mmio);
3308 + val >>= (8 * (off & 3));
3309 +
3310 + switch (len) {
3311 + case 1:
3312 + *((u8 *)buf) = (u8)val;
3313 + break;
3314 + case 2:
3315 + *((u16 *)buf) = (u16)val;
3316 + break;
3317 + case 4:
3318 + *((u32 *)buf) = (u32)val;
3319 + break;
3320 + }
3321 + err = 0;
3322 +unmap:
3323 + iounmap(mmio);
3324 +out:
3325 + return err;
3326 +}
3327 +
3328 +static int ssb_extpci_write_config(struct ssb_pcicore *pc,
3329 + unsigned int bus, unsigned int dev,
3330 + unsigned int func, unsigned int off,
3331 + const void *buf, int len)
3332 +{
3333 + int err = -EINVAL;
3334 + u32 addr, val = 0;
3335 + void __iomem *mmio;
3336 +
3337 + assert(pc->hostmode);
3338 + if (unlikely(len != 1 && len != 2 && len != 4))
3339 + goto out;
3340 + addr = get_cfgspace_addr(pc, bus, dev, func, off);
3341 + if (unlikely(!addr))
3342 + goto out;
3343 + err = -ENOMEM;
3344 + mmio = ioremap_nocache(addr, len);
3345 + if (!mmio)
3346 + goto out;
3347 +
3348 + if (mips_busprobe(val, (u32 *) mmio)) {
3349 + val = 0xffffffff;
3350 + goto unmap;
3351 + }
3352 +
3353 + switch (len) {
3354 + case 1:
3355 + val = readl(mmio);
3356 + val &= ~(0xFF << (8 * (off & 3)));
3357 + val |= *((const u8 *)buf) << (8 * (off & 3));
3358 + break;
3359 + case 2:
3360 + val = readl(mmio);
3361 + val &= ~(0xFFFF << (8 * (off & 3)));
3362 + val |= *((const u16 *)buf) << (8 * (off & 3));
3363 + break;
3364 + case 4:
3365 + val = *((const u32 *)buf);
3366 + break;
3367 + }
3368 + writel(*((const u32 *)buf), mmio);
3369 +
3370 + err = 0;
3371 +unmap:
3372 + iounmap(mmio);
3373 +out:
3374 + return err;
3375 +}
3376 +
3377 +static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
3378 + int reg, int size, u32 *val)
3379 +{
3380 + unsigned long flags;
3381 + int err;
3382 +
3383 + spin_lock_irqsave(&cfgspace_lock, flags);
3384 + err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
3385 + PCI_FUNC(devfn), reg, val, size);
3386 + spin_unlock_irqrestore(&cfgspace_lock, flags);
3387 +
3388 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
3389 +}
3390 +
3391 +static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
3392 + int reg, int size, u32 val)
3393 +{
3394 + unsigned long flags;
3395 + int err;
3396 +
3397 + spin_lock_irqsave(&cfgspace_lock, flags);
3398 + err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
3399 + PCI_FUNC(devfn), reg, &val, size);
3400 + spin_unlock_irqrestore(&cfgspace_lock, flags);
3401 +
3402 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
3403 +}
3404 +
3405 +static struct pci_ops ssb_pcicore_pciops = {
3406 + .read = ssb_pcicore_read_config,
3407 + .write = ssb_pcicore_write_config,
3408 +};
3409 +
3410 +static struct resource ssb_pcicore_mem_resource = {
3411 + .name = "SSB PCIcore external memory",
3412 + .start = SSB_PCI_DMA,
3413 + .end = (u32)SSB_PCI_DMA + (u32)SSB_PCI_DMA_SZ - 1,
3414 + .flags = IORESOURCE_MEM,
3415 +};
3416 +
3417 +static struct resource ssb_pcicore_io_resource = {
3418 + .name = "SSB PCIcore external I/O",
3419 + .start = 0x100,
3420 + .end = 0x7FF,
3421 + .flags = IORESOURCE_IO,
3422 +};
3423 +
3424 +static struct pci_controller ssb_pcicore_controller = {
3425 + .pci_ops = &ssb_pcicore_pciops,
3426 + .io_resource = &ssb_pcicore_io_resource,
3427 + .mem_resource = &ssb_pcicore_mem_resource,
3428 + .mem_offset = 0x24000000,
3429 +};
3430 +
3431 +static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
3432 +{
3433 + u32 val;
3434 +
3435 + assert(!extpci_core);
3436 + extpci_core = pc;
3437 +
3438 + ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
3439 + /* Reset devices on the external PCI bus */
3440 + val = SSB_PCICORE_CTL_RST_OE;
3441 + val |= SSB_PCICORE_CTL_CLK_OE;
3442 + pcicore_write32(pc, SSB_PCICORE_CTL, val);
3443 + val |= SSB_PCICORE_CTL_CLK; /* Clock on */
3444 + pcicore_write32(pc, SSB_PCICORE_CTL, val);
3445 + udelay(150);
3446 + val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
3447 + pcicore_write32(pc, SSB_PCICORE_CTL, val);
3448 + udelay(1);
3449 +
3450 + //TODO cardbus mode
3451 +
3452 + /* 64MB I/O window */
3453 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
3454 + SSB_PCICORE_SBTOPCI_IO);
3455 + /* 64MB config space */
3456 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
3457 + SSB_PCICORE_SBTOPCI_CFG0);
3458 + /* 1GB memory window */
3459 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
3460 + SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
3461 +
3462 + /* Enable PCI bridge BAR0 prefetch and burst */
3463 + val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
3464 + ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 4);
3465 +
3466 + /* Enable PCI interrupts */
3467 + pcicore_write32(pc, SSB_PCICORE_IMASK,
3468 + SSB_PCICORE_IMASK_INTA);
3469 +
3470 + /* Ok, ready to run, register it to the system.
3471 + * The following needs change, if we want to port hostmode
3472 + * to non-MIPS platform. */
3473 + set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
3474 + register_pci_controller(&ssb_pcicore_controller);
3475 +}
3476 +
3477 +static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
3478 +{
3479 + struct ssb_bus *bus = pc->dev->bus;
3480 + u16 chipid_top;
3481 + u32 tmp;
3482 +
3483 + chipid_top = (bus->chip_id & 0xFF00);
3484 + if (chipid_top != 0x4700 &&
3485 + chipid_top != 0x5300)
3486 + return 0;
3487 +
3488 + if (bus->sprom.r1.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
3489 + return 0;
3490 +
3491 + /* The 200-pin BCM4712 package does not bond out PCI. Even when
3492 + * PCI is bonded out, some boards may leave the pins floating. */
3493 + if (bus->chip_id == 0x4712) {
3494 + if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
3495 + return 0;
3496 + if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
3497 + return 0;
3498 + }
3499 + if (bus->chip_id == 0x5350)
3500 + return 0;
3501 +
3502 + return !mips_busprobe(tmp, (u32 *) (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
3503 +}
3504 +#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
3505 +
3506 +
3507 +/**************************************************
3508 + * Generic and Clientmode operation code.
3509 + **************************************************/
3510 +
3511 +static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
3512 +{
3513 + /* Disable PCI interrupts. */
3514 + ssb_write32(pc->dev, SSB_INTVEC, 0);
3515 +}
3516 +
3517 +void ssb_pcicore_init(struct ssb_pcicore *pc)
3518 +{
3519 + struct ssb_device *dev = pc->dev;
3520 + struct ssb_bus *bus;
3521 +
3522 + if (!dev)
3523 + return;
3524 + bus = dev->bus;
3525 + if (!ssb_device_is_enabled(dev))
3526 + ssb_device_enable(dev, 0);
3527 +
3528 +#ifdef CONFIG_SSB_PCICORE_HOSTMODE
3529 + pc->hostmode = pcicore_is_in_hostmode(pc);
3530 + if (pc->hostmode)
3531 + ssb_pcicore_init_hostmode(pc);
3532 +#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
3533 + if (!pc->hostmode)
3534 + ssb_pcicore_init_clientmode(pc);
3535 +}
3536 +
3537 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
3538 +{
3539 + pcicore_write32(pc, 0x130, address);
3540 + return pcicore_read32(pc, 0x134);
3541 +}
3542 +
3543 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
3544 +{
3545 + pcicore_write32(pc, 0x130, address);
3546 + pcicore_write32(pc, 0x134, data);
3547 +}
3548 +
3549 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
3550 + u8 address, u16 data)
3551 +{
3552 + const u16 mdio_control = 0x128;
3553 + const u16 mdio_data = 0x12C;
3554 + u32 v;
3555 + int i;
3556 +
3557 + v = 0x80; /* Enable Preamble Sequence */
3558 + v |= 0x2; /* MDIO Clock Divisor */
3559 + pcicore_write32(pc, mdio_control, v);
3560 +
3561 + v = (1 << 30); /* Start of Transaction */
3562 + v |= (1 << 28); /* Write Transaction */
3563 + v |= (1 << 17); /* Turnaround */
3564 + v |= (u32)device << 22;
3565 + v |= (u32)address << 18;
3566 + v |= data;
3567 + pcicore_write32(pc, mdio_data, v);
3568 + udelay(10);
3569 + for (i = 0; i < 10; i++) {
3570 + v = pcicore_read32(pc, mdio_control);
3571 + if (v & 0x100 /* Trans complete */)
3572 + break;
3573 + msleep(1);
3574 + }
3575 + pcicore_write32(pc, mdio_control, 0);
3576 +}
3577 +
3578 +static void ssb_broadcast_value(struct ssb_device *dev,
3579 + u32 address, u32 data)
3580 +{
3581 + /* This is used for both, PCI and ChipCommon core, so be careful. */
3582 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
3583 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
3584 +
3585 + ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
3586 + ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
3587 + ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
3588 + ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
3589 +}
3590 +
3591 +static void ssb_commit_settings(struct ssb_bus *bus)
3592 +{
3593 + struct ssb_device *dev;
3594 +
3595 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
3596 + assert(dev);
3597 + /* This forces an update of the cached registers. */
3598 + ssb_broadcast_value(dev, 0xFD8, 0);
3599 +}
3600 +
3601 +int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
3602 + struct ssb_device *dev)
3603 +{
3604 + struct ssb_device *pdev = pc->dev;
3605 + struct ssb_bus *bus;
3606 + int err = 0;
3607 + u32 tmp;
3608 +
3609 + might_sleep();
3610 +
3611 + if (!pdev)
3612 + goto out;
3613 + bus = pdev->bus;
3614 +
3615 + /* Enable interrupts for this device. */
3616 + if (bus->host_pci &&
3617 + ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
3618 + u32 coremask;
3619 +
3620 + /* Calculate the "coremask" for the device. */
3621 + coremask = (1 << dev->core_index);
3622 +
3623 + err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
3624 + if (err)
3625 + goto out;
3626 + tmp |= coremask << 8;
3627 + err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
3628 + if (err)
3629 + goto out;
3630 + } else {
3631 + u32 intvec;
3632 +
3633 + intvec = ssb_read32(pdev, SSB_INTVEC);
3634 + tmp = ssb_read32(dev, SSB_TPSFLAG);
3635 + tmp &= SSB_TPSFLAG_BPFLAG;
3636 + intvec |= tmp;
3637 + ssb_write32(pdev, SSB_INTVEC, intvec);
3638 + }
3639 +
3640 + /* Setup PCIcore operation. */
3641 + if (pc->setup_done)
3642 + goto out;
3643 + if (pdev->id.coreid == SSB_DEV_PCI) {
3644 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
3645 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
3646 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
3647 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
3648 +
3649 + if (pdev->id.revision < 5) {
3650 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
3651 + tmp &= ~SSB_IMCFGLO_SERTO;
3652 + tmp |= 2;
3653 + tmp &= ~SSB_IMCFGLO_REQTO;
3654 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
3655 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
3656 + ssb_commit_settings(bus);
3657 + } else if (pdev->id.revision >= 11) {
3658 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
3659 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
3660 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
3661 + }
3662 + } else {
3663 + assert(pdev->id.coreid == SSB_DEV_PCIE);
3664 + //TODO: Better make defines for all these magic PCIE values.
3665 + if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
3666 + /* TLP Workaround register. */
3667 + tmp = ssb_pcie_read(pc, 0x4);
3668 + tmp |= 0x8;
3669 + ssb_pcie_write(pc, 0x4, tmp);
3670 + }
3671 + if (pdev->id.revision == 0) {
3672 + const u8 serdes_rx_device = 0x1F;
3673 +
3674 + ssb_pcie_mdio_write(pc, serdes_rx_device,
3675 + 2 /* Timer */, 0x8128);
3676 + ssb_pcie_mdio_write(pc, serdes_rx_device,
3677 + 6 /* CDR */, 0x0100);
3678 + ssb_pcie_mdio_write(pc, serdes_rx_device,
3679 + 7 /* CDR BW */, 0x1466);
3680 + } else if (pdev->id.revision == 1) {
3681 + /* DLLP Link Control register. */
3682 + tmp = ssb_pcie_read(pc, 0x100);
3683 + tmp |= 0x40;
3684 + ssb_pcie_write(pc, 0x100, tmp);
3685 + }
3686 + }
3687 + pc->setup_done = 1;
3688 +out:
3689 + return err;
3690 +}
3691 +EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);
3692 diff -urN linux.old/drivers/ssb/Kconfig linux.dev/drivers/ssb/Kconfig
3693 --- linux.old/drivers/ssb/Kconfig 1970-01-01 01:00:00.000000000 +0100
3694 +++ linux.dev/drivers/ssb/Kconfig 2007-01-26 00:44:13.000000000 +0100
3695 @@ -0,0 +1,93 @@
3696 +menu "Sonics Silicon Backplane"
3697 +
3698 +config SSB
3699 + tristate "Sonics Silicon Backplane support"
3700 + depends on EXPERIMENTAL
3701 + help
3702 + Support for the Sonics Silicon Backplane bus
3703 +
3704 + The module will be called ssb
3705 +
3706 + If unsure, say M
3707 +
3708 +config SSB_PCIHOST
3709 + bool "Support for SSB on PCI-bus host"
3710 + depends on SSB && PCI
3711 + default y
3712 + help
3713 + Support for a Sonics Silicon Backplane on top
3714 + of a PCI device.
3715 +
3716 + If unsure, say Y
3717 +
3718 +config SSB_PCMCIAHOST
3719 + bool "Support for SSB on PCMCIA-bus host"
3720 + depends on SSB && PCMCIA
3721 + help
3722 + Support for a Sonics Silicon Backplane on top
3723 + of a PCMCIA device.
3724 +
3725 + If unsure, say N
3726 +
3727 +config SSB_SILENT
3728 + bool "No SSB kernel messages"
3729 + depends on SSB
3730 + help
3731 + This option turns off all Sonics Silicon Backplane printks.
3732 + Note that you won't be able to identify problems, once
3733 + messages are turned off.
3734 + This might only be desired for production kernels on
3735 + embedded devices to reduce the kernel size.
3736 +
3737 + Say N
3738 +
3739 +config SSB_DEBUG
3740 + bool "SSB debugging"
3741 + depends on SSB && !SSB_SILENT
3742 + help
3743 + This turns on additional runtime checks and debugging
3744 + messages. Turn this on for SSB troubleshooting.
3745 +
3746 + If unsure, say N
3747 +
3748 +config SSB_SERIAL
3749 + bool
3750 + depends on SSB
3751 + # ChipCommon and ExtIf serial support routines.
3752 +
3753 +config SSB_DRIVER_PCICORE
3754 + bool "SSB PCI core driver"
3755 + depends on SSB && SSB_PCIHOST
3756 + default y
3757 + help
3758 + Driver for the Sonics Silicon Backplane attached
3759 + Broadcom PCI core.
3760 +
3761 + If unsure, say Y
3762 +
3763 +config SSB_PCICORE_HOSTMODE
3764 + bool "Hostmode support for SSB PCI core"
3765 + depends on SSB_DRIVER_PCICORE && SSB_DRIVER_MIPS
3766 + help
3767 + PCIcore hostmode operation (external PCI bus).
3768 +
3769 +config SSB_DRIVER_MIPS
3770 + bool "SSB Broadcom MIPS core driver"
3771 + depends on SSB && MIPS
3772 + select SSB_SERIAL
3773 + help
3774 + Driver for the Sonics Silicon Backplane attached
3775 + Broadcom MIPS core.
3776 +
3777 + If unsure, say N
3778 +
3779 +config SSB_DRIVER_EXTIF
3780 + bool "SSB Broadcom EXTIF core driver"
3781 + depends on SSB_DRIVER_MIPS
3782 + help
3783 + Driver for the Sonics Silicon Backplane attached
3784 + Broadcom EXTIF core.
3785 +
3786 + If unsure, say N
3787 +
3788 +endmenu
3789 diff -urN linux.old/drivers/ssb/Makefile linux.dev/drivers/ssb/Makefile
3790 --- linux.old/drivers/ssb/Makefile 1970-01-01 01:00:00.000000000 +0100
3791 +++ linux.dev/drivers/ssb/Makefile 2007-01-26 00:44:13.000000000 +0100
3792 @@ -0,0 +1,14 @@
3793 +ssb-driver-chipcommon-y := driver_chipcommon/chipcommon.o
3794 +ssb-driver-mips-$(CONFIG_SSB_DRIVER_MIPS) := driver_mips/mips.o
3795 +ssb-driver-pci-$(CONFIG_SSB_DRIVER_PCICORE) := driver_pci/pcicore.o
3796 +
3797 +ssb-$(CONFIG_SSB_PCIHOST) += pci.o
3798 +ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.o
3799 +
3800 +obj-$(CONFIG_SSB) += ssb.o
3801 +
3802 +ssb-objs := core.o scan.o \
3803 + $(ssb-y) $(ssb-m) \
3804 + $(ssb-driver-chipcommon-y) \
3805 + $(ssb-driver-mips-y) \
3806 + $(ssb-driver-pci-y)
3807 diff -urN linux.old/drivers/ssb/pci.c linux.dev/drivers/ssb/pci.c
3808 --- linux.old/drivers/ssb/pci.c 1970-01-01 01:00:00.000000000 +0100
3809 +++ linux.dev/drivers/ssb/pci.c 2007-01-26 00:44:13.000000000 +0100
3810 @@ -0,0 +1,480 @@
3811 +/*
3812 + * Sonics Silicon Backplane PCI-Hostbus related functions.
3813 + *
3814 + * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
3815 + * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
3816 + * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
3817 + * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
3818 + * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
3819 + *
3820 + * Derived from the Broadcom 4400 device driver.
3821 + * Copyright (C) 2002 David S. Miller (davem@redhat.com)
3822 + * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
3823 + * Copyright (C) 2006 Broadcom Corporation.
3824 + *
3825 + * Licensed under the GNU/GPL. See COPYING for details.
3826 + */
3827 +
3828 +#include <linux/ssb/ssb.h>
3829 +#include <linux/ssb/ssb_regs.h>
3830 +#include <linux/pci.h>
3831 +#include <linux/delay.h>
3832 +
3833 +#include "ssb_private.h"
3834 +
3835 +
3836 +int ssb_pci_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
3837 +{
3838 + int err;
3839 + int attempts = 0;
3840 + u32 cur_core;
3841 +
3842 + while (1) {
3843 + err = pci_write_config_dword(bus->host_pci, SSB_BAR0_WIN,
3844 + (coreidx * SSB_CORE_SIZE)
3845 + + SSB_ENUM_BASE);
3846 + if (err)
3847 + goto error;
3848 + err = pci_read_config_dword(bus->host_pci, SSB_BAR0_WIN,
3849 + &cur_core);
3850 + if (err)
3851 + goto error;
3852 + cur_core = (cur_core - SSB_ENUM_BASE)
3853 + / SSB_CORE_SIZE;
3854 + if (cur_core == coreidx)
3855 + break;
3856 +
3857 + if (attempts++ > SSB_BAR0_MAX_RETRIES)
3858 + goto error;
3859 + udelay(10);
3860 + }
3861 + return 0;
3862 +error:
3863 + ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
3864 + return -ENODEV;
3865 +}
3866 +
3867 +int ssb_pci_switch_core(struct ssb_bus *bus,
3868 + struct ssb_device *dev)
3869 +{
3870 + int err;
3871 + unsigned long flags;
3872 +
3873 + ssb_dprintk(KERN_INFO PFX
3874 + "Switching to %s core, index %d\n",
3875 + ssb_core_name(dev->id.coreid),
3876 + dev->core_index);
3877 +
3878 + spin_lock_irqsave(&bus->bar_lock, flags);
3879 + err = ssb_pci_switch_coreidx(bus, dev->core_index);
3880 + if (!err)
3881 + bus->mapped_device = dev;
3882 + spin_unlock_irqrestore(&bus->bar_lock, flags);
3883 +
3884 + return err;
3885 +}
3886 +
3887 +int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on)
3888 +{
3889 + int err;
3890 + u32 in, out, outenable;
3891 + u16 pci_status;
3892 +
3893 + if (bus->bustype != SSB_BUSTYPE_PCI)
3894 + return 0;
3895 +
3896 + err = pci_read_config_dword(bus->host_pci, SSB_GPIO_IN, &in);
3897 + if (err)
3898 + goto err_pci;
3899 + err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &out);
3900 + if (err)
3901 + goto err_pci;
3902 + err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, &outenable);
3903 + if (err)
3904 + goto err_pci;
3905 +
3906 + outenable |= what;
3907 +
3908 + if (turn_on) {
3909 + /* Avoid glitching the clock if GPRS is already using it.
3910 + * We can't actually read the state of the PLLPD so we infer it
3911 + * by the value of XTAL_PU which *is* readable via gpioin.
3912 + */
3913 + if (!(in & SSB_GPIO_XTAL)) {
3914 + if (what & SSB_GPIO_XTAL) {
3915 + /* Turn the crystal on */
3916 + out |= SSB_GPIO_XTAL;
3917 + if (what & SSB_GPIO_PLL)
3918 + out |= SSB_GPIO_PLL;
3919 + err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
3920 + if (err)
3921 + goto err_pci;
3922 + err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE,
3923 + outenable);
3924 + if (err)
3925 + goto err_pci;
3926 + msleep(1);
3927 + }
3928 + if (what & SSB_GPIO_PLL) {
3929 + /* Turn the PLL on */
3930 + out &= ~SSB_GPIO_PLL;
3931 + err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
3932 + if (err)
3933 + goto err_pci;
3934 + msleep(2);
3935 + }
3936 + }
3937 +
3938 + err = pci_read_config_word(bus->host_pci, PCI_STATUS, &pci_status);
3939 + if (err)
3940 + goto err_pci;
3941 + pci_status &= ~PCI_STATUS_SIG_TARGET_ABORT;
3942 + err = pci_write_config_word(bus->host_pci, PCI_STATUS, pci_status);
3943 + if (err)
3944 + goto err_pci;
3945 + } else {
3946 + if (what & SSB_GPIO_XTAL) {
3947 + /* Turn the crystal off */
3948 + out &= ~SSB_GPIO_XTAL;
3949 + }
3950 + if (what & SSB_GPIO_PLL) {
3951 + /* Turn the PLL off */
3952 + out |= SSB_GPIO_PLL;
3953 + }
3954 + err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
3955 + if (err)
3956 + goto err_pci;
3957 + err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, outenable);
3958 + if (err)
3959 + goto err_pci;
3960 + }
3961 +
3962 +out:
3963 + return err;
3964 +
3965 +err_pci:
3966 + printk(KERN_ERR PFX "Error: ssb_pci_xtal() could not access PCI config space!\n");
3967 + err = -EBUSY;
3968 + goto out;
3969 +}
3970 +
3971 +#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
3972 +#define SPEX(_outvar, _offset, _mask, _shift) \
3973 + out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
3974 +
3975 +static inline u8 ssb_crc8(u8 crc, u8 data)
3976 +{
3977 + /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */
3978 + static const u8 t[] = {
3979 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
3980 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
3981 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
3982 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
3983 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
3984 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
3985 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
3986 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
3987 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
3988 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
3989 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
3990 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
3991 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
3992 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
3993 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
3994 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
3995 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
3996 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
3997 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
3998 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
3999 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
4000 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
4001 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
4002 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
4003 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
4004 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
4005 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
4006 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
4007 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
4008 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
4009 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
4010 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
4011 + };
4012 + return t[crc ^ data];
4013 +}
4014 +
4015 +static u8 ssb_sprom_crc(const u16 *sprom)
4016 +{
4017 + int word;
4018 + u8 crc = 0xFF;
4019 +
4020 + for (word = 0; word < SSB_SPROMSIZE_WORDS - 1; word++) {
4021 + crc = ssb_crc8(crc, sprom[word] & 0x00FF);
4022 + crc = ssb_crc8(crc, (sprom[word] & 0xFF00) >> 8);
4023 + }
4024 + crc = ssb_crc8(crc, sprom[SPOFF(SSB_SPROM_REVISION)] & 0x00FF);
4025 + crc ^= 0xFF;
4026 +
4027 + return crc;
4028 +}
4029 +
4030 +static int sprom_check_crc(const u16 *sprom)
4031 +{
4032 + u8 crc;
4033 + u8 expected_crc;
4034 + u16 tmp;
4035 +
4036 + crc = ssb_sprom_crc(sprom);
4037 + tmp = sprom[SPOFF(SSB_SPROM_REVISION)] & SSB_SPROM_REVISION_CRC;
4038 + expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
4039 + if (crc != expected_crc)
4040 + return -EPROTO;
4041 +
4042 + return 0;
4043 +}
4044 +
4045 +static void sprom_do_read(struct ssb_bus *bus, u16 *sprom)
4046 +{
4047 + int i;
4048 +
4049 + for (i = 0; i < SSB_SPROMSIZE_WORDS; i++)
4050 + sprom[i] = readw(bus->mmio + SSB_SPROM_BASE + (i * 2));
4051 +}
4052 +
4053 +static void sprom_extract_r1(struct ssb_sprom_r1 *out, const u16 *in)
4054 +{
4055 + int i;
4056 + u16 v;
4057 +
4058 + SPEX(pci_spid, SSB_SPROM1_SPID, 0xFFFF, 0);
4059 + SPEX(pci_svid, SSB_SPROM1_SVID, 0xFFFF, 0);
4060 + SPEX(pci_pid, SSB_SPROM1_PID, 0xFFFF, 0);
4061 + for (i = 0; i < 3; i++) {
4062 + v = in[SPOFF(SSB_SPROM1_IL0MAC) + i];
4063 + *(((u16 *)out->il0mac) + i) = cpu_to_be16(v);
4064 + }
4065 + for (i = 0; i < 3; i++) {
4066 + v = in[SPOFF(SSB_SPROM1_ET0MAC) + i];
4067 + *(((u16 *)out->et0mac) + i) = cpu_to_be16(v);
4068 + }
4069 + for (i = 0; i < 3; i++) {
4070 + v = in[SPOFF(SSB_SPROM1_ET1MAC) + i];
4071 + *(((u16 *)out->et1mac) + i) = cpu_to_be16(v);
4072 + }
4073 + SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
4074 + SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
4075 + SSB_SPROM1_ETHPHY_ET1A_SHIFT);
4076 + SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
4077 + SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
4078 + SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
4079 + SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
4080 + SSB_SPROM1_BINF_CCODE_SHIFT);
4081 + SPEX(antenna_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
4082 + SSB_SPROM1_BINF_ANTA_SHIFT);
4083 + SPEX(antenna_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
4084 + SSB_SPROM1_BINF_ANTBG_SHIFT);
4085 + SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
4086 + SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
4087 + SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
4088 + SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
4089 + SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
4090 + SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
4091 + SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
4092 + SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
4093 + SSB_SPROM1_GPIOA_P1_SHIFT);
4094 + SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
4095 + SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
4096 + SSB_SPROM1_GPIOB_P3_SHIFT);
4097 + SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A, 0);
4098 + SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG,
4099 + SSB_SPROM1_MAXPWR_BG_SHIFT);
4100 + SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A, 0);
4101 + SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG,
4102 + SSB_SPROM1_ITSSI_BG_SHIFT);
4103 + SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
4104 + SPEX(antenna_gain_a, SSB_SPROM1_AGAIN, SSB_SPROM1_AGAIN_A, 0);
4105 + SPEX(antenna_gain_bg, SSB_SPROM1_AGAIN, SSB_SPROM1_AGAIN_BG,
4106 + SSB_SPROM1_AGAIN_BG_SHIFT);
4107 + for (i = 0; i < 4; i++) {
4108 + v = in[SPOFF(SSB_SPROM1_OEM) + i];
4109 + *(((u16 *)out->oem) + i) = cpu_to_le16(v);
4110 + }
4111 +}
4112 +
4113 +static void sprom_extract_r2(struct ssb_sprom_r2 *out, const u16 *in)
4114 +{
4115 + int i;
4116 + u16 v;
4117 +
4118 + SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
4119 + SPEX(maxpwr_a_hi, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
4120 + SPEX(maxpwr_a_lo, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
4121 + SSB_SPROM2_MAXP_A_LO_SHIFT);
4122 + SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
4123 + SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
4124 + SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
4125 + SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
4126 + SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
4127 + SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
4128 + SPEX(ofdm_pwr_off, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
4129 + for (i = 0; i < 4; i++) {
4130 + v = in[SPOFF(SSB_SPROM2_CCODE) + i];
4131 + *(((u16 *)out->country_str) + i) = cpu_to_le16(v);
4132 + }
4133 +}
4134 +
4135 +static void sprom_extract_r3(struct ssb_sprom_r3 *out, const u16 *in)
4136 +{
4137 + out->ofdmapo = (in[SPOFF(SSB_SPROM3_OFDMAPO) + 0] & 0xFF00) >> 8;
4138 + out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 0] & 0x00FF) << 8;
4139 + out->ofdmapo <<= 16;
4140 + out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 1] & 0xFF00) >> 8;
4141 + out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 1] & 0x00FF) << 8;
4142 +
4143 + out->ofdmalpo = (in[SPOFF(SSB_SPROM3_OFDMALPO) + 0] & 0xFF00) >> 8;
4144 + out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 0] & 0x00FF) << 8;
4145 + out->ofdmalpo <<= 16;
4146 + out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 1] & 0xFF00) >> 8;
4147 + out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 1] & 0x00FF) << 8;
4148 +
4149 + out->ofdmahpo = (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 0] & 0xFF00) >> 8;
4150 + out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 0] & 0x00FF) << 8;
4151 + out->ofdmahpo <<= 16;
4152 + out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 1] & 0xFF00) >> 8;
4153 + out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 1] & 0x00FF) << 8;
4154 +
4155 + SPEX(gpioldc_on_cnt, SSB_SPROM3_GPIOLDC, SSB_SPROM3_GPIOLDC_ON,
4156 + SSB_SPROM3_GPIOLDC_ON_SHIFT);
4157 + SPEX(gpioldc_off_cnt, SSB_SPROM3_GPIOLDC, SSB_SPROM3_GPIOLDC_OFF,
4158 + SSB_SPROM3_GPIOLDC_OFF_SHIFT);
4159 + SPEX(cckpo_1M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_1M, 0);
4160 + SPEX(cckpo_2M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_2M,
4161 + SSB_SPROM3_CCKPO_2M_SHIFT);
4162 + SPEX(cckpo_55M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_55M,
4163 + SSB_SPROM3_CCKPO_55M_SHIFT);
4164 + SPEX(cckpo_11M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_11M,
4165 + SSB_SPROM3_CCKPO_11M_SHIFT);
4166 +
4167 + out->ofdmgpo = (in[SPOFF(SSB_SPROM3_OFDMGPO) + 0] & 0xFF00) >> 8;
4168 + out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 0] & 0x00FF) << 8;
4169 + out->ofdmgpo <<= 16;
4170 + out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 1] & 0xFF00) >> 8;
4171 + out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 1] & 0x00FF) << 8;
4172 +}
4173 +
4174 +static int sprom_extract(struct ssb_sprom *out, const u16 *in)
4175 +{
4176 + memset(out, 0, sizeof(*out));
4177 +
4178 + SPEX(revision, SSB_SPROM_REVISION, SSB_SPROM_REVISION_REV, 0);
4179 + SPEX(crc, SSB_SPROM_REVISION, SSB_SPROM_REVISION_CRC,
4180 + SSB_SPROM_REVISION_CRC_SHIFT);
4181 +
4182 + if (out->revision == 0)
4183 + goto unsupported;
4184 + if (out->revision >= 1 && out->revision <= 3)
4185 + sprom_extract_r1(&out->r1, in);
4186 + if (out->revision >= 2 && out->revision <= 3)
4187 + sprom_extract_r2(&out->r2, in);
4188 + if (out->revision == 3)
4189 + sprom_extract_r3(&out->r3, in);
4190 + if (out->revision >= 4)
4191 + goto unsupported;
4192 +
4193 + return 0;
4194 +unsupported:
4195 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM revision %d "
4196 + "detected. Will extract v1\n", out->revision);
4197 + sprom_extract_r1(&out->r1, in);
4198 + return 0;
4199 +}
4200 +
4201 +int ssb_pci_sprom_get(struct ssb_bus *bus)
4202 +{
4203 + int err = -ENOMEM;
4204 + u16 *buf;
4205 +
4206 + assert(bus->bustype == SSB_BUSTYPE_PCI);
4207 +
4208 + buf = kcalloc(SSB_SPROMSIZE_WORDS, sizeof(u16), GFP_KERNEL);
4209 + if (!buf)
4210 + goto out;
4211 + sprom_do_read(bus, buf);
4212 + err = sprom_check_crc(buf);
4213 + if (err) {
4214 + ssb_printk(KERN_WARNING PFX
4215 + "WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
4216 + }
4217 + err = sprom_extract(&bus->sprom, buf);
4218 +
4219 + kfree(buf);
4220 +out:
4221 + return err;
4222 +}
4223 +
4224 +void ssb_pci_get_boardtype(struct ssb_bus *bus)
4225 +{
4226 + pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
4227 + &bus->board_vendor);
4228 + pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
4229 + &bus->board_type);
4230 + pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
4231 + &bus->board_rev);
4232 +}
4233 +
4234 +static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
4235 +{
4236 + struct ssb_bus *bus = dev->bus;
4237 +
4238 + if (unlikely(bus->mapped_device != dev)) {
4239 + if (unlikely(ssb_pci_switch_core(bus, dev)))
4240 + return 0xFFFF;
4241 + }
4242 + return readw(bus->mmio + offset);
4243 +}
4244 +
4245 +static u32 ssb_pci_read32(struct ssb_device *dev, u16 offset)
4246 +{
4247 + struct ssb_bus *bus = dev->bus;
4248 +
4249 + if (unlikely(bus->mapped_device != dev)) {
4250 + if (unlikely(ssb_pci_switch_core(bus, dev)))
4251 + return 0xFFFFFFFF;
4252 + }
4253 + return readl(bus->mmio + offset);
4254 +}
4255 +
4256 +static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
4257 +{
4258 + struct ssb_bus *bus = dev->bus;
4259 +
4260 + if (unlikely(bus->mapped_device != dev)) {
4261 + if (unlikely(ssb_pci_switch_core(bus, dev)))
4262 + return;
4263 + }
4264 + writew(value, bus->mmio + offset);
4265 +}
4266 +
4267 +static void ssb_pci_write32(struct ssb_device *dev, u16 offset, u32 value)
4268 +{
4269 + struct ssb_bus *bus = dev->bus;
4270 +
4271 + if (unlikely(bus->mapped_device != dev)) {
4272 + if (unlikely(ssb_pci_switch_core(bus, dev)))
4273 + return;
4274 + }
4275 + writel(value, bus->mmio + offset);
4276 +}
4277 +
4278 +const struct ssb_bus_ops ssb_pci_ops = {
4279 + .read16 = ssb_pci_read16,
4280 + .read32 = ssb_pci_read32,
4281 + .write16 = ssb_pci_write16,
4282 + .write32 = ssb_pci_write32,
4283 +};
4284 +
4285 +int ssb_pci_init(struct ssb_bus *bus)
4286 +{
4287 + if (bus->bustype != SSB_BUSTYPE_PCI)
4288 + return 0;
4289 + return ssb_pci_sprom_get(bus);
4290 +}
4291 diff -urN linux.old/drivers/ssb/pcmcia.c linux.dev/drivers/ssb/pcmcia.c
4292 --- linux.old/drivers/ssb/pcmcia.c 1970-01-01 01:00:00.000000000 +0100
4293 +++ linux.dev/drivers/ssb/pcmcia.c 2007-01-26 00:44:13.000000000 +0100
4294 @@ -0,0 +1,256 @@
4295 +/*
4296 + * Sonics Silicon Backplane
4297 + * PCMCIA-Hostbus related functions
4298 + *
4299 + * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
4300 + * Copyright 2007 Michael Buesch <mb@bu3sch.de>
4301 + *
4302 + * Licensed under the GNU/GPL. See COPYING for details.
4303 + */
4304 +
4305 +#include <linux/ssb/ssb.h>
4306 +#include <linux/delay.h>
4307 +
4308 +#include <pcmcia/cs_types.h>
4309 +#include <pcmcia/cs.h>
4310 +#include <pcmcia/cistpl.h>
4311 +#include <pcmcia/ciscode.h>
4312 +#include <pcmcia/ds.h>
4313 +#include <pcmcia/cisreg.h>
4314 +
4315 +#include "ssb_private.h"
4316 +
4317 +
4318 +int ssb_pcmcia_switch_coreidx(struct ssb_bus *bus,
4319 + u8 coreidx)
4320 +{
4321 + struct pcmcia_device *pdev = bus->host_pcmcia;
4322 + int err;
4323 + int attempts = 0;
4324 + u32 cur_core;
4325 + conf_reg_t reg;
4326 + u32 addr;
4327 + u32 read_addr;
4328 +
4329 + addr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE;
4330 + while (1) {
4331 + reg.Action = CS_WRITE;
4332 + reg.Offset = 0x2E;
4333 + reg.Value = (addr & 0x0000F000) >> 12;
4334 + err = pcmcia_access_configuration_register(pdev, &reg);
4335 + if (err != CS_SUCCESS)
4336 + goto error;
4337 + reg.Offset = 0x30;
4338 + reg.Value = (addr & 0x00FF0000) >> 16;
4339 + err = pcmcia_access_configuration_register(pdev, &reg);
4340 + if (err != CS_SUCCESS)
4341 + goto error;
4342 + reg.Offset = 0x32;
4343 + reg.Value = (addr & 0xFF000000) >> 24;
4344 + err = pcmcia_access_configuration_register(pdev, &reg);
4345 + if (err != CS_SUCCESS)
4346 + goto error;
4347 +
4348 + read_addr = 0;
4349 +
4350 + reg.Action = CS_READ;
4351 + reg.Offset = 0x2E;
4352 + err = pcmcia_access_configuration_register(pdev, &reg);
4353 + if (err != CS_SUCCESS)
4354 + goto error;
4355 + read_addr |= (reg.Value & 0xF) << 12;
4356 + reg.Offset = 0x30;
4357 + err = pcmcia_access_configuration_register(pdev, &reg);
4358 + if (err != CS_SUCCESS)
4359 + goto error;
4360 + read_addr |= reg.Value << 16;
4361 + reg.Offset = 0x32;
4362 + err = pcmcia_access_configuration_register(pdev, &reg);
4363 + if (err != CS_SUCCESS)
4364 + goto error;
4365 + read_addr |= reg.Value << 24;
4366 +
4367 + cur_core = (read_addr - SSB_ENUM_BASE) / SSB_CORE_SIZE;
4368 + if (cur_core == coreidx)
4369 + break;
4370 +
4371 + if (attempts++ > SSB_BAR0_MAX_RETRIES)
4372 + goto error;
4373 + udelay(10);
4374 + }
4375 +
4376 + return 0;
4377 +error:
4378 + ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
4379 + return -ENODEV;
4380 +}
4381 +
4382 +int ssb_pcmcia_switch_core(struct ssb_bus *bus,
4383 + struct ssb_device *dev)
4384 +{
4385 + int err;
4386 + unsigned long flags;
4387 +
4388 + ssb_dprintk(KERN_INFO PFX
4389 + "Switching to %s core, index %d\n",
4390 + ssb_core_name(dev->id.coreid),
4391 + dev->core_index);
4392 +
4393 + spin_lock_irqsave(&bus->bar_lock, flags);
4394 + err = ssb_pcmcia_switch_coreidx(bus, dev->core_index);
4395 + if (!err)
4396 + bus->mapped_device = dev;
4397 + spin_unlock_irqrestore(&bus->bar_lock, flags);
4398 +
4399 + return err;
4400 +}
4401 +
4402 +int ssb_pcmcia_switch_segment(struct ssb_bus *bus, u8 seg)
4403 +{
4404 + int attempts = 0;
4405 + unsigned long flags;
4406 + conf_reg_t reg;
4407 + int res, err = 0;
4408 +
4409 + assert(seg == 0 || seg == 1);
4410 + reg.Offset = 0x34;
4411 + reg.Function = 0;
4412 + spin_lock_irqsave(&bus->bar_lock, flags);
4413 + while (1) {
4414 + reg.Action = CS_WRITE;
4415 + reg.Value = seg;
4416 + res = pcmcia_access_configuration_register(bus->host_pcmcia, &reg);
4417 + if (unlikely(res != CS_SUCCESS))
4418 + goto error;
4419 + reg.Value = 0xFF;
4420 + reg.Action = CS_READ;
4421 + res = pcmcia_access_configuration_register(bus->host_pcmcia, &reg);
4422 + if (unlikely(res != CS_SUCCESS))
4423 + goto error;
4424 +
4425 + if (reg.Value == seg)
4426 + break;
4427 +
4428 + if (unlikely(attempts++ > SSB_BAR0_MAX_RETRIES))
4429 + goto error;
4430 + udelay(10);
4431 + }
4432 + bus->mapped_pcmcia_seg = seg;
4433 +out_unlock:
4434 + spin_unlock_irqrestore(&bus->bar_lock, flags);
4435 + return err;
4436 +error:
4437 + ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n");
4438 + err = -ENODEV;
4439 + goto out_unlock;
4440 +}
4441 +
4442 +static inline int do_select_core(struct ssb_bus *bus,
4443 + struct ssb_device *dev,
4444 + u16 *offset)
4445 +{
4446 + int err;
4447 + u8 need_seg = (*offset >= 0x800) ? 1 : 0;
4448 +
4449 + if (unlikely(dev != bus->mapped_device)) {
4450 + err = ssb_pcmcia_switch_core(bus, dev);
4451 + if (unlikely(err))
4452 + return err;
4453 + }
4454 + if (unlikely(need_seg != bus->mapped_pcmcia_seg)) {
4455 + err = ssb_pcmcia_switch_segment(bus, need_seg);
4456 + if (unlikely(err))
4457 + return err;
4458 + }
4459 + if (need_seg == 1)
4460 + *offset -= 0x800;
4461 +
4462 + return 0;
4463 +}
4464 +
4465 +static u16 ssb_pcmcia_read16(struct ssb_device *dev, u16 offset)
4466 +{
4467 + struct ssb_bus *bus = dev->bus;
4468 + u16 x;
4469 +
4470 + if (unlikely(do_select_core(bus, dev, &offset)))
4471 + return 0xFFFF;
4472 + x = readw(bus->mmio + offset);
4473 +//printk("R16 0x%04X, 0x%04X\n", offset, x);
4474 + return x;
4475 +}
4476 +
4477 +static u32 ssb_pcmcia_read32(struct ssb_device *dev, u16 offset)
4478 +{
4479 + struct ssb_bus *bus = dev->bus;
4480 + u32 x;
4481 +
4482 + if (unlikely(do_select_core(bus, dev, &offset)))
4483 + return 0xFFFFFFFF;
4484 + x = readl(bus->mmio + offset);
4485 +//printk("R32 0x%04X, 0x%08X\n", offset, x);
4486 + return x;
4487 +}
4488 +
4489 +static void ssb_pcmcia_write16(struct ssb_device *dev, u16 offset, u16 value)
4490 +{
4491 + struct ssb_bus *bus = dev->bus;
4492 +
4493 + if (unlikely(do_select_core(bus, dev, &offset)))
4494 + return;
4495 +//printk("W16 0x%04X, 0x%04X\n", offset, value);
4496 + writew(value, bus->mmio + offset);
4497 +}
4498 +
4499 +static void ssb_pcmcia_write32(struct ssb_device *dev, u16 offset, u32 value)
4500 +{
4501 + struct ssb_bus *bus = dev->bus;
4502 +
4503 + if (unlikely(do_select_core(bus, dev, &offset)))
4504 + return;
4505 +//printk("W32 0x%04X, 0x%08X\n", offset, value);
4506 + readw(bus->mmio + offset);
4507 + writew(value >> 16, bus->mmio + offset + 2);
4508 + readw(bus->mmio + offset);
4509 + writew(value, bus->mmio + offset);
4510 +}
4511 +
4512 +const struct ssb_bus_ops ssb_pcmcia_ops = {
4513 + .read16 = ssb_pcmcia_read16,
4514 + .read32 = ssb_pcmcia_read32,
4515 + .write16 = ssb_pcmcia_write16,
4516 + .write32 = ssb_pcmcia_write32,
4517 +};
4518 +
4519 +int ssb_pcmcia_init(struct ssb_bus *bus)
4520 +{
4521 + conf_reg_t reg;
4522 + int err;
4523 +
4524 + if (bus->bustype != SSB_BUSTYPE_PCMCIA)
4525 + return 0;
4526 +
4527 + /* Switch segment to a known state and sync
4528 + * bus->mapped_pcmcia_seg with hardware state. */
4529 + ssb_pcmcia_switch_segment(bus, 0);
4530 +
4531 + /* Init IRQ routing */
4532 + reg.Action = CS_READ;
4533 + reg.Function = 0;
4534 + if (bus->chip_id == 0x4306)
4535 + reg.Offset = 0x00;
4536 + else
4537 + reg.Offset = 0x80;
4538 + err = pcmcia_access_configuration_register(bus->host_pcmcia, &reg);
4539 + if (err != CS_SUCCESS)
4540 + goto error;
4541 + reg.Action = CS_WRITE;
4542 + reg.Value |= 0x04 | 0x01;
4543 + err = pcmcia_access_configuration_register(bus->host_pcmcia, &reg);
4544 + if (err != CS_SUCCESS)
4545 + goto error;
4546 +
4547 + return 0;
4548 +error:
4549 + return -ENODEV;
4550 +}
4551 diff -urN linux.old/drivers/ssb/scan.c linux.dev/drivers/ssb/scan.c
4552 --- linux.old/drivers/ssb/scan.c 1970-01-01 01:00:00.000000000 +0100
4553 +++ linux.dev/drivers/ssb/scan.c 2007-01-26 00:44:13.000000000 +0100
4554 @@ -0,0 +1,373 @@
4555 +/*
4556 + * Sonics Silicon Backplane
4557 + * Bus scanning
4558 + *
4559 + * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
4560 + * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
4561 + * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
4562 + * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
4563 + * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
4564 + * Copyright (C) 2006 Broadcom Corporation.
4565 + *
4566 + * Licensed under the GNU/GPL. See COPYING for details.
4567 + */
4568 +
4569 +#include <linux/ssb/ssb.h>
4570 +#include <linux/ssb/ssb_regs.h>
4571 +#include <linux/pci.h>
4572 +#include <asm/io.h>
4573 +
4574 +#include "ssb_private.h"
4575 +
4576 +
4577 +const char * ssb_core_name(u16 coreid)
4578 +{
4579 + switch (coreid) {
4580 + case SSB_DEV_CHIPCOMMON:
4581 + return "ChipCommon";
4582 + case SSB_DEV_ILINE20:
4583 + return "ILine 20";
4584 + case SSB_DEV_SDRAM:
4585 + return "SDRAM";
4586 + case SSB_DEV_PCI:
4587 + return "PCI";
4588 + case SSB_DEV_MIPS:
4589 + return "MIPS";
4590 + case SSB_DEV_ETHERNET:
4591 + return "Fast Ethernet";
4592 + case SSB_DEV_V90:
4593 + return "V90";
4594 + case SSB_DEV_USB11_HOSTDEV:
4595 + return "USB 1.1 Hostdev";
4596 + case SSB_DEV_ADSL:
4597 + return "ADSL";
4598 + case SSB_DEV_ILINE100:
4599 + return "ILine 100";
4600 + case SSB_DEV_IPSEC:
4601 + return "IPSEC";
4602 + case SSB_DEV_PCMCIA:
4603 + return "PCMCIA";
4604 + case SSB_DEV_INTERNAL_MEM:
4605 + return "Internal Memory";
4606 + case SSB_DEV_MEMC_SDRAM:
4607 + return "MEMC SDRAM";
4608 + case SSB_DEV_EXTIF:
4609 + return "EXTIF";
4610 + case SSB_DEV_80211:
4611 + return "IEEE 802.11";
4612 + case SSB_DEV_MIPS_3302:
4613 + return "MIPS 3302";
4614 + case SSB_DEV_USB11_HOST:
4615 + return "USB 1.1 Host";
4616 + case SSB_DEV_USB11_DEV:
4617 + return "USB 1.1 Device";
4618 + case SSB_DEV_USB20_HOST:
4619 + return "USB 2.0 Host";
4620 + case SSB_DEV_USB20_DEV:
4621 + return "USB 2.0 Device";
4622 + case SSB_DEV_SDIO_HOST:
4623 + return "SDIO Host";
4624 + case SSB_DEV_ROBOSWITCH:
4625 + return "Roboswitch";
4626 + case SSB_DEV_PARA_ATA:
4627 + return "PATA";
4628 + case SSB_DEV_SATA_XORDMA:
4629 + return "SATA XOR-DMA";
4630 + case SSB_DEV_ETHERNET_GBIT:
4631 + return "GBit Ethernet";
4632 + case SSB_DEV_PCIE:
4633 + return "PCI-E";
4634 + case SSB_DEV_MIMO_PHY:
4635 + return "MIMO PHY";
4636 + case SSB_DEV_SRAM_CTRLR:
4637 + return "SRAM Controller";
4638 + case SSB_DEV_MINI_MACPHY:
4639 + return "Mini MACPHY";
4640 + case SSB_DEV_ARM_1176:
4641 + return "ARM 1176";
4642 + case SSB_DEV_ARM_7TDMI:
4643 + return "ARM 7TDMI";
4644 + }
4645 + return "UNKNOWN";
4646 +}
4647 +
4648 +static u16 pcidev_to_chipid(struct pci_dev *pci_dev)
4649 +{
4650 + u16 chipid_fallback = 0;
4651 +
4652 + switch (pci_dev->device) {
4653 + case 0x4301:
4654 + chipid_fallback = 0x4301;
4655 + break;
4656 + case 0x4305 ... 0x4307:
4657 + chipid_fallback = 0x4307;
4658 + break;
4659 + case 0x4403:
4660 + chipid_fallback = 0x4402;
4661 + break;
4662 + case 0x4610 ... 0x4615:
4663 + chipid_fallback = 0x4610;
4664 + break;
4665 + case 0x4710 ... 0x4715:
4666 + chipid_fallback = 0x4710;
4667 + break;
4668 + case 0x4320 ... 0x4325:
4669 + chipid_fallback = 0x4309;
4670 + break;
4671 + case PCI_DEVICE_ID_BCM4401:
4672 + case PCI_DEVICE_ID_BCM4401B0:
4673 + case PCI_DEVICE_ID_BCM4401B1:
4674 + chipid_fallback = 0x4401;
4675 + break;
4676 + default:
4677 + ssb_printk(KERN_ERR PFX
4678 + "PCI-ID not in fallback list\n");
4679 + }
4680 +
4681 + return chipid_fallback;
4682 +}
4683 +
4684 +static u8 chipid_to_nrcores(u16 chipid)
4685 +{
4686 + switch (chipid) {
4687 + case 0x5365:
4688 + return 7;
4689 + case 0x4306:
4690 + return 6;
4691 + case 0x4310:
4692 + return 8;
4693 + case 0x4307:
4694 + case 0x4301:
4695 + return 5;
4696 + case 0x4401:
4697 + case 0x4402:
4698 + return 3;
4699 + case 0x4710:
4700 + case 0x4610:
4701 + case 0x4704:
4702 + return 9;
4703 + default:
4704 + ssb_printk(KERN_ERR PFX
4705 + "CHIPID not in nrcores fallback list\n");
4706 + }
4707 +
4708 + return 1;
4709 +}
4710 +
4711 +static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
4712 + u16 offset)
4713 +{
4714 + switch (bus->bustype) {
4715 + case SSB_BUSTYPE_SSB:
4716 + offset += current_coreidx * SSB_CORE_SIZE;
4717 + break;
4718 + case SSB_BUSTYPE_PCI:
4719 + break;
4720 + case SSB_BUSTYPE_PCMCIA:
4721 + if (offset >= 0x800) {
4722 + ssb_pcmcia_switch_segment(bus, 1);
4723 + offset -= 0x800;
4724 + } else
4725 + ssb_pcmcia_switch_segment(bus, 0);
4726 + break;
4727 + }
4728 + return readl(bus->mmio + offset);
4729 +}
4730 +
4731 +static int scan_switchcore(struct ssb_bus *bus, u8 coreidx)
4732 +{
4733 + switch (bus->bustype) {
4734 + case SSB_BUSTYPE_SSB:
4735 + break;
4736 + case SSB_BUSTYPE_PCI:
4737 + return ssb_pci_switch_coreidx(bus, coreidx);
4738 + case SSB_BUSTYPE_PCMCIA:
4739 + return ssb_pcmcia_switch_coreidx(bus, coreidx);
4740 + }
4741 + return 0;
4742 +}
4743 +
4744 +void ssb_iounmap(struct ssb_bus *bus)
4745 +{
4746 + switch (bus->bustype) {
4747 + case SSB_BUSTYPE_SSB:
4748 + case SSB_BUSTYPE_PCMCIA:
4749 + iounmap(bus->mmio);
4750 + break;
4751 + case SSB_BUSTYPE_PCI:
4752 + pci_iounmap(bus->host_pci, bus->mmio);
4753 + break;
4754 + }
4755 + bus->mmio = NULL;
4756 + bus->mapped_device = NULL;
4757 +}
4758 +
4759 +static void __iomem * ssb_ioremap(struct ssb_bus *bus,
4760 + unsigned long baseaddr)
4761 +{
4762 + void __iomem *mmio = NULL;
4763 +
4764 + switch (bus->bustype) {
4765 + case SSB_BUSTYPE_SSB:
4766 + /* Only map the first core for now. */
4767 + /* fallthrough... */
4768 + case SSB_BUSTYPE_PCMCIA:
4769 + mmio = ioremap(baseaddr, SSB_CORE_SIZE);
4770 + break;
4771 + case SSB_BUSTYPE_PCI:
4772 + mmio = pci_iomap(bus->host_pci, 0, ~0UL);
4773 + break;
4774 + }
4775 +
4776 + return mmio;
4777 +}
4778 +
4779 +int ssb_bus_scan(struct ssb_bus *bus,
4780 + unsigned long baseaddr)
4781 +{
4782 + int err = -ENOMEM;
4783 + void __iomem *mmio;
4784 + u32 idhi, cc, rev, tmp;
4785 + int i;
4786 + struct ssb_device *dev;
4787 +
4788 + mmio = ssb_ioremap(bus, baseaddr);
4789 + if (!mmio)
4790 + goto out;
4791 + bus->mmio = mmio;
4792 +
4793 + err = scan_switchcore(bus, 0); /* Switch to first core */
4794 + if (err)
4795 + goto err_unmap;
4796 +
4797 + idhi = scan_read32(bus, 0, SSB_IDHIGH);
4798 + cc = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
4799 + rev = (idhi & SSB_IDHIGH_RCLO);
4800 + rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
4801 +
4802 + bus->nr_devices = 0;
4803 + if (cc == SSB_DEV_CHIPCOMMON) {
4804 + tmp = scan_read32(bus, 0, SSB_CHIPCO_CHIPID);
4805 +
4806 + bus->chip_id = (tmp & SSB_CHIPCO_IDMASK);
4807 + bus->chip_rev = (tmp & SSB_CHIPCO_REVMASK) >>
4808 + SSB_CHIPCO_REVSHIFT;
4809 + bus->chip_package = (tmp & SSB_CHIPCO_PACKMASK) >>
4810 + SSB_CHIPCO_PACKSHIFT;
4811 + if (rev >= 4) {
4812 + bus->nr_devices = (tmp & SSB_CHIPCO_NRCORESMASK) >>
4813 + SSB_CHIPCO_NRCORESSHIFT;
4814 + }
4815 + tmp = scan_read32(bus, 0, SSB_CHIPCO_CAP);
4816 + bus->chipco.capabilities = tmp;
4817 + } else {
4818 + if (bus->bustype == SSB_BUSTYPE_PCI) {
4819 + bus->chip_id = pcidev_to_chipid(bus->host_pci);
4820 + pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
4821 + &bus->chip_rev);
4822 + bus->chip_package = 0;
4823 + } else {
4824 + bus->chip_id = 0x4710;
4825 + bus->chip_rev = 0;
4826 + bus->chip_package = 0;
4827 + }
4828 + }
4829 + if (!bus->nr_devices)
4830 + bus->nr_devices = chipid_to_nrcores(bus->chip_id);
4831 + if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
4832 + ssb_printk(KERN_ERR PFX
4833 + "More than %d ssb cores found (%d)\n",
4834 + SSB_MAX_NR_CORES, bus->nr_devices);
4835 + goto err_unmap;
4836 + }
4837 + if (bus->bustype == SSB_BUSTYPE_SSB) {
4838 + /* Now that we know the number of cores,
4839 + * remap the whole IO space for all cores.
4840 + */
4841 + err = -ENOMEM;
4842 + iounmap(mmio);
4843 + mmio = ioremap(baseaddr, SSB_CORE_SIZE * bus->nr_devices);
4844 + if (!mmio)
4845 + goto out;
4846 + bus->mmio = mmio;
4847 + }
4848 +
4849 + /* Fetch basic information about each core/device */
4850 + for (i = 0; i < bus->nr_devices; i++) {
4851 + err = scan_switchcore(bus, i);
4852 + if (err)
4853 + goto err_unmap;
4854 + dev = &(bus->devices[i]);
4855 +
4856 + idhi = scan_read32(bus, i, SSB_IDHIGH);
4857 + dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
4858 + dev->id.revision = (idhi & SSB_IDHIGH_RCLO);
4859 + dev->id.revision |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
4860 + dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT;
4861 + dev->core_index = i;
4862 + dev->bus = bus;
4863 + if ((dev->bus->bustype == SSB_BUSTYPE_PCI) && (bus->host_pci))
4864 + dev->irq = bus->host_pci->irq;
4865 +
4866 + ssb_dprintk(KERN_INFO PFX
4867 + "Core %d found: %s "
4868 + "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
4869 + i, ssb_core_name(dev->id.coreid),
4870 + dev->id.coreid, dev->id.revision, dev->id.vendor);
4871 +
4872 + dev->dev.bus = &ssb_bustype;
4873 + snprintf(dev->dev.bus_id, sizeof(dev->dev.bus_id),
4874 + "ssb%02x:%02x", bus->busnumber, i);
4875 +
4876 + switch (dev->id.coreid) {
4877 + case SSB_DEV_EXTIF:
4878 +#ifdef CONFIG_SSB_DRIVER_EXTIF
4879 + if (bus->extif.dev) {
4880 + ssb_printk(KERN_WARNING PFX
4881 + "WARNING: Multiple EXTIFs found\n");
4882 + break;
4883 + }
4884 + bus->extif.dev = dev;
4885 +#endif /* CONFIG_SSB_DRIVER_EXTIF */
4886 + break;
4887 + case SSB_DEV_CHIPCOMMON:
4888 + if (bus->chipco.dev) {
4889 + ssb_printk(KERN_WARNING PFX
4890 + "WARNING: Multiple ChipCommon found\n");
4891 + break;
4892 + }
4893 + bus->chipco.dev = dev;
4894 + break;
4895 + case SSB_DEV_MIPS:
4896 + case SSB_DEV_MIPS_3302:
4897 +#ifdef CONFIG_SSB_DRIVER_MIPS
4898 + if (bus->mipscore.dev) {
4899 + ssb_printk(KERN_WARNING PFX
4900 + "WARNING: Multiple MIPS cores found\n");
4901 + break;
4902 + }
4903 + bus->mipscore.dev = dev;
4904 +#endif /* CONFIG_SSB_DRIVER_MIPS */
4905 + break;
4906 + case SSB_DEV_PCI:
4907 + case SSB_DEV_PCIE:
4908 +#ifdef CONFIG_SSB_DRIVER_PCICORE
4909 + if (bus->pcicore.dev) {
4910 + ssb_printk(KERN_WARNING PFX
4911 + "WARNING: Multiple PCI(E) cores found\n");
4912 + break;
4913 + }
4914 + bus->pcicore.dev = dev;
4915 +#endif /* CONFIG_SSB_DRIVER_PCICORE */
4916 + break;
4917 + default:
4918 + break;
4919 + }
4920 + }
4921 + err = 0;
4922 +out:
4923 + return err;
4924 +err_unmap:
4925 + ssb_iounmap(bus);
4926 + goto out;
4927 +}
4928 diff -urN linux.old/drivers/ssb/ssb_private.h linux.dev/drivers/ssb/ssb_private.h
4929 --- linux.old/drivers/ssb/ssb_private.h 1970-01-01 01:00:00.000000000 +0100
4930 +++ linux.dev/drivers/ssb/ssb_private.h 2007-01-26 00:44:13.000000000 +0100
4931 @@ -0,0 +1,143 @@
4932 +#ifndef LINUX_SSB_PRIVATE_H_
4933 +#define LINUX_SSB_PRIVATE_H_
4934 +
4935 +#include <linux/ssb/ssb.h>
4936 +#include <linux/types.h>
4937 +#include <asm/io.h>
4938 +
4939 +
4940 +#define PFX "ssb: "
4941 +
4942 +#ifdef CONFIG_SSB_SILENT
4943 +# define ssb_printk(fmt, x...) do { /* nothing */ } while (0)
4944 +#else
4945 +# define ssb_printk printk
4946 +#endif /* CONFIG_SSB_SILENT */
4947 +
4948 +/* dprintk: Debugging printk; vanishes for non-debug compilation */
4949 +#ifdef CONFIG_SSB_DEBUG
4950 +# define ssb_dprintk(fmt, x...) ssb_printk(fmt ,##x)
4951 +#else
4952 +# define ssb_dprintk(fmt, x...) do { /* nothing */ } while (0)
4953 +#endif
4954 +
4955 +/* printkl: Rate limited printk */
4956 +#define ssb_printkl(fmt, x...) do { \
4957 + if (printk_ratelimit()) \
4958 + ssb_printk(fmt ,##x); \
4959 + } while (0)
4960 +
4961 +/* dprintkl: Rate limited debugging printk */
4962 +#ifdef CONFIG_SSB_DEBUG
4963 +# define ssb_dprintkl ssb_printkl
4964 +#else
4965 +# define ssb_dprintkl(fmt, x...) do { /* nothing */ } while (0)
4966 +#endif
4967 +
4968 +#define assert(cond) do { \
4969 + if (unlikely(!(cond))) { \
4970 + ssb_dprintk(KERN_ERR PFX "BUG: Assertion failed (%s) " \
4971 + "at: %s:%d:%s()\n", \
4972 + #cond, __FILE__, __LINE__, __func__); \
4973 + } \
4974 + } while (0)
4975 +
4976 +
4977 +/* pci.c */
4978 +#ifdef CONFIG_SSB_PCIHOST
4979 +extern int ssb_pci_switch_core(struct ssb_bus *bus,
4980 + struct ssb_device *dev);
4981 +extern int ssb_pci_switch_coreidx(struct ssb_bus *bus,
4982 + u8 coreidx);
4983 +extern int ssb_pci_xtal(struct ssb_bus *bus, u32 what,
4984 + int turn_on);
4985 +extern int ssb_pci_sprom_get(struct ssb_bus *bus);
4986 +extern void ssb_pci_get_boardtype(struct ssb_bus *bus);
4987 +extern int ssb_pci_init(struct ssb_bus *bus);
4988 +extern const struct ssb_bus_ops ssb_pci_ops;
4989 +
4990 +#else /* CONFIG_SSB_PCIHOST */
4991 +
4992 +static inline int ssb_pci_switch_core(struct ssb_bus *bus,
4993 + struct ssb_device *dev)
4994 +{
4995 + return 0;
4996 +}
4997 +static inline int ssb_pci_switch_coreidx(struct ssb_bus *bus,
4998 + u8 coreidx)
4999 +{
5000 + return 0;
5001 +}
5002 +static inline int ssb_pci_xtal(struct ssb_bus *bus, u32 what,
5003 + int turn_on)
5004 +{
5005 + return 0;
5006 +}
5007 +static inline int ssb_pci_sprom_get(struct ssb_bus *bus)
5008 +{
5009 + return 0;
5010 +}
5011 +static inline void ssb_pci_get_boardtype(struct ssb_bus *bus)
5012 +{
5013 +}
5014 +static inline int ssb_pci_init(struct ssb_bus *bus)
5015 +{
5016 + return 0;
5017 +}
5018 +#endif /* CONFIG_SSB_PCIHOST */
5019 +
5020 +
5021 +/* pcmcia.c */
5022 +#ifdef CONFIG_SSB_PCMCIAHOST
5023 +extern int ssb_pcmcia_switch_core(struct ssb_bus *bus,
5024 + struct ssb_device *dev);
5025 +extern int ssb_pcmcia_switch_coreidx(struct ssb_bus *bus,
5026 + u8 coreidx);
5027 +extern int ssb_pcmcia_switch_segment(struct ssb_bus *bus,
5028 + u8 seg);
5029 +extern int ssb_pcmcia_init(struct ssb_bus *bus);
5030 +extern const struct ssb_bus_ops ssb_pcmcia_ops;
5031 +#else /* CONFIG_SSB_PCMCIAHOST */
5032 +static inline int ssb_pcmcia_switch_core(struct ssb_bus *bus,
5033 + struct ssb_device *dev)
5034 +{
5035 + return 0;
5036 +}
5037 +static inline int ssb_pcmcia_switch_coreidx(struct ssb_bus *bus,
5038 + u8 coreidx)
5039 +{
5040 + return 0;
5041 +}
5042 +static inline int ssb_pcmcia_switch_segment(struct ssb_bus *bus,
5043 + u8 seg)
5044 +{
5045 + return 0;
5046 +}
5047 +static inline int ssb_pcmcia_init(struct ssb_bus *bus)
5048 +{
5049 + return 0;
5050 +}
5051 +#endif /* CONFIG_SSB_PCMCIAHOST */
5052 +
5053 +
5054 +/* scan.c */
5055 +extern const char * ssb_core_name(u16 coreid);
5056 +extern int ssb_bus_scan(struct ssb_bus *bus,
5057 + unsigned long baseaddr);
5058 +extern void ssb_iounmap(struct ssb_bus *ssb);
5059 +
5060 +
5061 +/* core.c */
5062 +extern struct bus_type ssb_bustype;
5063 +extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
5064 +
5065 +
5066 +/* Ceiling division helper. Divides x by y. */
5067 +static inline
5068 +unsigned long ceildiv(unsigned long x, unsigned long y)
5069 +{
5070 + return ((x + (y - 1)) / y);
5071 +}
5072 +
5073 +
5074 +#endif /* LINUX_SSB_PRIVATE_H_ */
5075 diff -urN linux.old/include/asm-mips/asm-offsets.h linux.dev/include/asm-mips/asm-offsets.h
5076 --- linux.old/include/asm-mips/asm-offsets.h 1970-01-01 01:00:00.000000000 +0100
5077 +++ linux.dev/include/asm-mips/asm-offsets.h 2007-01-25 23:34:01.000000000 +0100
5078 @@ -0,0 +1,214 @@
5079 +#ifndef __ASM_OFFSETS_H__
5080 +#define __ASM_OFFSETS_H__
5081 +/*
5082 + * DO NOT MODIFY.
5083 + *
5084 + * This file was generated by Kbuild
5085 + *
5086 + */
5087 +
5088 +/* MIPS pt_regs offsets. */
5089 +#define PT_R0 24
5090 +#define PT_R1 28
5091 +#define PT_R2 32
5092 +#define PT_R3 36
5093 +#define PT_R4 40
5094 +#define PT_R5 44
5095 +#define PT_R6 48
5096 +#define PT_R7 52
5097 +#define PT_R8 56
5098 +#define PT_R9 60
5099 +#define PT_R10 64
5100 +#define PT_R11 68
5101 +#define PT_R12 72
5102 +#define PT_R13 76
5103 +#define PT_R14 80
5104 +#define PT_R15 84
5105 +#define PT_R16 88
5106 +#define PT_R17 92
5107 +#define PT_R18 96
5108 +#define PT_R19 100
5109 +#define PT_R20 104
5110 +#define PT_R21 108
5111 +#define PT_R22 112
5112 +#define PT_R23 116
5113 +#define PT_R24 120
5114 +#define PT_R25 124
5115 +#define PT_R26 128
5116 +#define PT_R27 132
5117 +#define PT_R28 136
5118 +#define PT_R29 140
5119 +#define PT_R30 144
5120 +#define PT_R31 148
5121 +#define PT_LO 160
5122 +#define PT_HI 156
5123 +#define PT_EPC 172
5124 +#define PT_BVADDR 164
5125 +#define PT_STATUS 152
5126 +#define PT_CAUSE 168
5127 +#define PT_SIZE 176
5128 +
5129 +/* MIPS task_struct offsets. */
5130 +#define TASK_STATE 0
5131 +#define TASK_THREAD_INFO 4
5132 +#define TASK_FLAGS 12
5133 +#define TASK_MM 132
5134 +#define TASK_PID 168
5135 +#define TASK_STRUCT_SIZE 1048
5136 +
5137 +/* MIPS thread_info offsets. */
5138 +#define TI_TASK 0
5139 +#define TI_EXEC_DOMAIN 4
5140 +#define TI_FLAGS 8
5141 +#define TI_TP_VALUE 12
5142 +#define TI_CPU 16
5143 +#define TI_PRE_COUNT 20
5144 +#define TI_ADDR_LIMIT 24
5145 +#define TI_RESTART_BLOCK 28
5146 +#define TI_REGS 48
5147 +#define _THREAD_SIZE_ORDER 0x1
5148 +#define _THREAD_SIZE 0x2000
5149 +#define _THREAD_MASK 0x1fff
5150 +
5151 +/* MIPS specific thread_struct offsets. */
5152 +#define THREAD_REG16 432
5153 +#define THREAD_REG17 436
5154 +#define THREAD_REG18 440
5155 +#define THREAD_REG19 444
5156 +#define THREAD_REG20 448
5157 +#define THREAD_REG21 452
5158 +#define THREAD_REG22 456
5159 +#define THREAD_REG23 460
5160 +#define THREAD_REG29 464
5161 +#define THREAD_REG30 468
5162 +#define THREAD_REG31 472
5163 +#define THREAD_STATUS 476
5164 +#define THREAD_FPU 480
5165 +#define THREAD_BVADDR 772
5166 +#define THREAD_BUADDR 776
5167 +#define THREAD_ECODE 780
5168 +#define THREAD_TRAPNO 784
5169 +#define THREAD_MFLAGS 788
5170 +#define THREAD_TRAMP 792
5171 +#define THREAD_OLDCTX 796
5172 +
5173 +#define THREAD_FPR0 480
5174 +#define THREAD_FPR1 488
5175 +#define THREAD_FPR2 496
5176 +#define THREAD_FPR3 504
5177 +#define THREAD_FPR4 512
5178 +#define THREAD_FPR5 520
5179 +#define THREAD_FPR6 528
5180 +#define THREAD_FPR7 536
5181 +#define THREAD_FPR8 544
5182 +#define THREAD_FPR9 552
5183 +#define THREAD_FPR10 560
5184 +#define THREAD_FPR11 568
5185 +#define THREAD_FPR12 576
5186 +#define THREAD_FPR13 584
5187 +#define THREAD_FPR14 592
5188 +#define THREAD_FPR15 600
5189 +#define THREAD_FPR16 608
5190 +#define THREAD_FPR17 616
5191 +#define THREAD_FPR18 624
5192 +#define THREAD_FPR19 632
5193 +#define THREAD_FPR20 640
5194 +#define THREAD_FPR21 648
5195 +#define THREAD_FPR22 656
5196 +#define THREAD_FPR23 664
5197 +#define THREAD_FPR24 672
5198 +#define THREAD_FPR25 680
5199 +#define THREAD_FPR26 688
5200 +#define THREAD_FPR27 696
5201 +#define THREAD_FPR28 704
5202 +#define THREAD_FPR29 712
5203 +#define THREAD_FPR30 720
5204 +#define THREAD_FPR31 728
5205 +#define THREAD_FCR31 736
5206 +
5207 +/* Linux sigcontext offsets. */
5208 +#define SC_REGS 16
5209 +#define SC_FPREGS 272
5210 +#define SC_MDHI 552
5211 +#define SC_MDLO 560
5212 +#define SC_PC 8
5213 +#define SC_STATUS 4
5214 +#define SC_FPC_CSR 532
5215 +#define SC_FPC_EIR 536
5216 +#define SC_HI1 568
5217 +#define SC_LO1 572
5218 +#define SC_HI2 576
5219 +#define SC_LO2 580
5220 +#define SC_HI3 584
5221 +#define SC_LO3 588
5222 +
5223 +/* Linux signal numbers. */
5224 +#define _SIGHUP 0x1
5225 +#define _SIGINT 0x2
5226 +#define _SIGQUIT 0x3
5227 +#define _SIGILL 0x4
5228 +#define _SIGTRAP 0x5
5229 +#define _SIGIOT 0x6
5230 +#define _SIGABRT 0x6
5231 +#define _SIGEMT 0x7
5232 +#define _SIGFPE 0x8
5233 +#define _SIGKILL 0x9
5234 +#define _SIGBUS 0xa
5235 +#define _SIGSEGV 0xb
5236 +#define _SIGSYS 0xc
5237 +#define _SIGPIPE 0xd
5238 +#define _SIGALRM 0xe
5239 +#define _SIGTERM 0xf
5240 +#define _SIGUSR1 0x10
5241 +#define _SIGUSR2 0x11
5242 +#define _SIGCHLD 0x12
5243 +#define _SIGPWR 0x13
5244 +#define _SIGWINCH 0x14
5245 +#define _SIGURG 0x15
5246 +#define _SIGIO 0x16
5247 +#define _SIGSTOP 0x17
5248 +#define _SIGTSTP 0x18
5249 +#define _SIGCONT 0x19
5250 +#define _SIGTTIN 0x1a
5251 +#define _SIGTTOU 0x1b
5252 +#define _SIGVTALRM 0x1c
5253 +#define _SIGPROF 0x1d
5254 +#define _SIGXCPU 0x1e
5255 +#define _SIGXFSZ 0x1f
5256 +
5257 +/* Linux irq_cpustat_t offsets. */
5258 +#define IC_SOFTIRQ_PENDING 0
5259 +#define IC_IRQ_CPUSTAT_T 32
5260 +
5261 +/* Size of struct page */
5262 +#define STRUCT_PAGE_SIZE 32
5263 +
5264 +/* Linux mm_struct offsets. */
5265 +#define MM_USERS 40
5266 +#define MM_PGD 36
5267 +#define MM_CONTEXT 348
5268 +
5269 +#define _PAGE_SIZE 0x1000
5270 +#define _PAGE_SHIFT 0xc
5271 +
5272 +#define _PGD_T_SIZE 0x4
5273 +#define _PMD_T_SIZE 0x4
5274 +#define _PTE_T_SIZE 0x4
5275 +
5276 +#define _PGD_T_LOG2 $2
5277 +#define _PMD_T_LOG2 $2
5278 +#define _PTE_T_LOG2 $2
5279 +
5280 +#define _PMD_SHIFT 0x16
5281 +#define _PGDIR_SHIFT 0x16
5282 +
5283 +#define _PGD_ORDER 0x0
5284 +#define _PMD_ORDER 0x1
5285 +#define _PTE_ORDER 0x0
5286 +
5287 +#define _PTRS_PER_PGD 0x400
5288 +#define _PTRS_PER_PMD 0x1
5289 +#define _PTRS_PER_PTE 0x400
5290 +
5291 +
5292 +#endif
5293 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
5294 --- linux.old/include/asm-mips/bootinfo.h 2007-01-26 00:51:33.000000000 +0100
5295 +++ linux.dev/include/asm-mips/bootinfo.h 2007-01-25 23:34:01.000000000 +0100
5296 @@ -212,6 +212,12 @@
5297 #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */
5298 #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
5299
5300 +/*
5301 + * Valid machtype for group Broadcom
5302 + */
5303 +#define MACH_GROUP_BRCM 23 /* Broadcom */
5304 +#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
5305 +
5306 #define CL_SIZE COMMAND_LINE_SIZE
5307
5308 const char *get_system_type(void);
5309 diff -urN linux.old/include/asm-mips/cfe.h linux.dev/include/asm-mips/cfe.h
5310 --- linux.old/include/asm-mips/cfe.h 1970-01-01 01:00:00.000000000 +0100
5311 +++ linux.dev/include/asm-mips/cfe.h 2007-01-25 23:34:01.000000000 +0100
5312 @@ -0,0 +1,189 @@
5313 +/*
5314 + * Broadcom Common Firmware Environment (CFE) support
5315 + *
5316 + * Copyright 2000, 2001, 2002
5317 + * Broadcom Corporation. All rights reserved.
5318 + *
5319 + * Copyright (C) 2006 Michael Buesch
5320 + *
5321 + * Original Authors: Mitch Lichtenberg, Chris Demetriou
5322 + *
5323 + * This software is furnished under license and may be used and copied only
5324 + * in accordance with the following terms and conditions. Subject to these
5325 + * conditions, you may download, copy, install, use, modify and distribute
5326 + * modified or unmodified copies of this software in source and/or binary
5327 + * form. No title or ownership is transferred hereby.
5328 + *
5329 + * 1) Any source code used, modified or distributed must reproduce and
5330 + * retain this copyright notice and list of conditions as they appear in
5331 + * the source file.
5332 + *
5333 + * 2) No right is granted to use any trade name, trademark, or logo of
5334 + * Broadcom Corporation. The "Broadcom Corporation" name may not be
5335 + * used to endorse or promote products derived from this software
5336 + * without the prior written permission of Broadcom Corporation.
5337 + *
5338 + * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
5339 + * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
5340 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
5341 + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
5342 + * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
5343 + * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
5344 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
5345 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
5346 + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
5347 + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
5348 + * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5349 + */
5350 +
5351 +#ifndef LINUX_CFE_API_H_
5352 +#define LINUX_CFE_API_H_
5353 +
5354 +#include <linux/types.h>
5355 +
5356 +
5357 +#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */
5358 +#define CFE_MI_AVAILABLE 1 /* memory is available */
5359 +
5360 +#define CFE_FLG_WARMSTART 0x00000001
5361 +#define CFE_FLG_FULL_ARENA 0x00000001
5362 +#define CFE_FLG_ENV_PERMANENT 0x00000001
5363 +
5364 +#define CFE_CPU_CMD_START 1
5365 +#define CFE_CPU_CMD_STOP 0
5366 +
5367 +#define CFE_STDHANDLE_CONSOLE 0
5368 +
5369 +#define CFE_DEV_NETWORK 1
5370 +#define CFE_DEV_DISK 2
5371 +#define CFE_DEV_FLASH 3
5372 +#define CFE_DEV_SERIAL 4
5373 +#define CFE_DEV_CPU 5
5374 +#define CFE_DEV_NVRAM 6
5375 +#define CFE_DEV_CLOCK 7
5376 +#define CFE_DEV_OTHER 8
5377 +#define CFE_DEV_MASK 0x0F
5378 +
5379 +#define CFE_CACHE_FLUSH_D 1
5380 +#define CFE_CACHE_INVAL_I 2
5381 +#define CFE_CACHE_INVAL_D 4
5382 +#define CFE_CACHE_INVAL_L2 8
5383 +
5384 +#define CFE_FWI_64BIT 0x00000001
5385 +#define CFE_FWI_32BIT 0x00000002
5386 +#define CFE_FWI_RELOC 0x00000004
5387 +#define CFE_FWI_UNCACHED 0x00000008
5388 +#define CFE_FWI_MULTICPU 0x00000010
5389 +#define CFE_FWI_FUNCSIM 0x00000020
5390 +#define CFE_FWI_RTLSIM 0x00000040
5391 +
5392 +struct cfe_fwinfo {
5393 + s64 version; /* major, minor, eco version */
5394 + s64 totalmem; /* total installed mem */
5395 + s64 flags; /* various flags */
5396 + s64 boardid; /* board ID */
5397 + s64 bootarea_va; /* VA of boot area */
5398 + s64 bootarea_pa; /* PA of boot area */
5399 + s64 bootarea_size; /* size of boot area */
5400 +};
5401 +
5402 +
5403 +/* The public CFE API */
5404 +
5405 +int cfe_present(void); /* Check if we booted from CFE. Returns bool */
5406 +
5407 +int cfe_getticks(s64 *ticks);
5408 +int cfe_close(int handle);
5409 +int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1);
5410 +int cfe_cpu_stop(int cpu);
5411 +int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen);
5412 +int cfe_enumdev(int idx, char *name, int namelen);
5413 +int cfe_enummem(int idx, int flags, u64 *start, u64 *length,
5414 + u64 *type);
5415 +int cfe_exit(int warm, int status);
5416 +int cfe_flushcache(int flags);
5417 +int cfe_getdevinfo(char *name);
5418 +int cfe_getenv(char *name, char *dest, int destlen);
5419 +int cfe_getfwinfo(struct cfe_fwinfo *info);
5420 +int cfe_getstdhandle(int handletype);
5421 +int cfe_inpstat(int handle);
5422 +int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
5423 + int length, int *retlen, u64 offset);
5424 +int cfe_open(char *name);
5425 +int cfe_read(int handle, unsigned char *buffer, int length);
5426 +int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length);
5427 +int cfe_setenv(char *name, char *val);
5428 +int cfe_write(int handle, unsigned char *buffer, int length);
5429 +int cfe_writeblk(int handle, s64 offset, unsigned char *buffer,
5430 + int length);
5431 +
5432 +
5433 +/* High level API */
5434 +
5435 +/* Print some information to CFE's console (most likely serial line) */
5436 +int cfe_printk(const char *fmt, ...) __attribute__((format(printf, 1, 2)));
5437 +int cfe_vprintk(const char *fmt, va_list args);
5438 +
5439 +
5440 +
5441 +/* Error codes returned by the low API functions */
5442 +
5443 +#define CFE_ISERR(errcode) (errcode < 0)
5444 +
5445 +#define CFE_OK 0
5446 +#define CFE_ERR -1 /* generic error */
5447 +#define CFE_ERR_INV_COMMAND -2
5448 +#define CFE_ERR_EOF -3
5449 +#define CFE_ERR_IOERR -4
5450 +#define CFE_ERR_NOMEM -5
5451 +#define CFE_ERR_DEVNOTFOUND -6
5452 +#define CFE_ERR_DEVOPEN -7
5453 +#define CFE_ERR_INV_PARAM -8
5454 +#define CFE_ERR_ENVNOTFOUND -9
5455 +#define CFE_ERR_ENVREADONLY -10
5456 +
5457 +#define CFE_ERR_NOTELF -11
5458 +#define CFE_ERR_NOT32BIT -12
5459 +#define CFE_ERR_WRONGENDIAN -13
5460 +#define CFE_ERR_BADELFVERS -14
5461 +#define CFE_ERR_NOTMIPS -15
5462 +#define CFE_ERR_BADELFFMT -16
5463 +#define CFE_ERR_BADADDR -17
5464 +
5465 +#define CFE_ERR_FILENOTFOUND -18
5466 +#define CFE_ERR_UNSUPPORTED -19
5467 +
5468 +#define CFE_ERR_HOSTUNKNOWN -20
5469 +
5470 +#define CFE_ERR_TIMEOUT -21
5471 +
5472 +#define CFE_ERR_PROTOCOLERR -22
5473 +
5474 +#define CFE_ERR_NETDOWN -23
5475 +#define CFE_ERR_NONAMESERVER -24
5476 +
5477 +#define CFE_ERR_NOHANDLES -25
5478 +#define CFE_ERR_ALREADYBOUND -26
5479 +
5480 +#define CFE_ERR_CANNOTSET -27
5481 +#define CFE_ERR_NOMORE -28
5482 +#define CFE_ERR_BADFILESYS -29
5483 +#define CFE_ERR_FSNOTAVAIL -30
5484 +
5485 +#define CFE_ERR_INVBOOTBLOCK -31
5486 +#define CFE_ERR_WRONGDEVTYPE -32
5487 +#define CFE_ERR_BBCHECKSUM -33
5488 +#define CFE_ERR_BOOTPROGCHKSUM -34
5489 +
5490 +#define CFE_ERR_LDRNOTAVAIL -35
5491 +
5492 +#define CFE_ERR_NOTREADY -36
5493 +
5494 +#define CFE_ERR_GETMEM -37
5495 +#define CFE_ERR_SETMEM -38
5496 +
5497 +#define CFE_ERR_NOTCONN -39
5498 +#define CFE_ERR_ADDRINUSE -40
5499 +
5500 +
5501 +#endif /* LINUX_CFE_API_H_ */
5502 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
5503 --- linux.old/include/asm-mips/cpu.h 2007-01-26 00:51:33.000000000 +0100
5504 +++ linux.dev/include/asm-mips/cpu.h 2007-01-25 23:34:01.000000000 +0100
5505 @@ -104,6 +104,13 @@
5506 #define PRID_IMP_SR71000 0x0400
5507
5508 /*
5509 + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
5510 + */
5511 +
5512 +#define PRID_IMP_BCM4710 0x4000
5513 +#define PRID_IMP_BCM3302 0x9000
5514 +
5515 +/*
5516 * Definitions for 7:0 on legacy processors
5517 */
5518
5519 @@ -200,7 +207,9 @@
5520 #define CPU_SB1A 62
5521 #define CPU_74K 63
5522 #define CPU_R14000 64
5523 -#define CPU_LAST 64
5524 +#define CPU_BCM3302 65
5525 +#define CPU_BCM4710 66
5526 +#define CPU_LAST 66
5527
5528 /*
5529 * ISA Level encodings
5530 diff -urN linux.old/include/asm-mips/mach-bcm947xx/kernel-entry-init.h linux.dev/include/asm-mips/mach-bcm947xx/kernel-entry-init.h
5531 --- linux.old/include/asm-mips/mach-bcm947xx/kernel-entry-init.h 1970-01-01 01:00:00.000000000 +0100
5532 +++ linux.dev/include/asm-mips/mach-bcm947xx/kernel-entry-init.h 2007-01-25 23:34:01.000000000 +0100
5533 @@ -0,0 +1,26 @@
5534 +/*
5535 + * This file is subject to the terms and conditions of the GNU General Public
5536 + * License. See the file "COPYING" in the main directory of this archive
5537 + * for more details.
5538 + *
5539 + * Copyright (C) 2005 Embedded Alley Solutions, Inc
5540 + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
5541 + * Copyright (C) 2006 Michael Buesch
5542 + */
5543 +#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H
5544 +#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H
5545 +
5546 +/* Intentionally empty macro, used in head.S. Override in
5547 + * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
5548 + */
5549 + .macro kernel_entry_setup
5550 + .endm
5551 +
5552 +/*
5553 + * Do SMP slave processor setup necessary before we can savely execute C code.
5554 + */
5555 + .macro smp_slave_setup
5556 + .endm
5557 +
5558 +
5559 +#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */
5560 diff -urN linux.old/include/linux/pci_ids.h linux.dev/include/linux/pci_ids.h
5561 --- linux.old/include/linux/pci_ids.h 2007-01-26 00:51:33.000000000 +0100
5562 +++ linux.dev/include/linux/pci_ids.h 2007-01-25 23:34:01.000000000 +0100
5563 @@ -1950,6 +1950,7 @@
5564 #define PCI_DEVICE_ID_TIGON3_5906M 0x1713
5565 #define PCI_DEVICE_ID_BCM4401 0x4401
5566 #define PCI_DEVICE_ID_BCM4401B0 0x4402
5567 +#define PCI_DEVICE_ID_BCM4713 0x4713
5568
5569 #define PCI_VENDOR_ID_TOPIC 0x151f
5570 #define PCI_DEVICE_ID_TOPIC_TP560 0x0000
5571 diff -urN linux.old/include/linux/ssb/ssb_driver_chipcommon.h linux.dev/include/linux/ssb/ssb_driver_chipcommon.h
5572 --- linux.old/include/linux/ssb/ssb_driver_chipcommon.h 1970-01-01 01:00:00.000000000 +0100
5573 +++ linux.dev/include/linux/ssb/ssb_driver_chipcommon.h 2007-01-26 00:49:32.000000000 +0100
5574 @@ -0,0 +1,387 @@
5575 +#ifndef LINUX_SSB_CHIPCO_H_
5576 +#define LINUX_SSB_CHIPCO_H_
5577 +
5578 +/* SonicsSiliconBackplane CHIPCOMMON core hardware definitions
5579 + *
5580 + * The chipcommon core provides chip identification, SB control,
5581 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
5582 + * gpio interface, extbus, and support for serial and parallel flashes.
5583 + *
5584 + * Copyright 2005, Broadcom Corporation
5585 + * Copyright 2006, Michael Buesch <mb@bu3sch.de>
5586 + *
5587 + * Licensed under the GPL version 2. See COPYING for details.
5588 + */
5589 +#ifdef __KERNEL__
5590 +
5591 +/** ChipCommon core registers. **/
5592 +
5593 +#define SSB_CHIPCO_CHIPID 0x0000
5594 +#define SSB_CHIPCO_IDMASK 0x0000FFFF
5595 +#define SSB_CHIPCO_REVMASK 0x000F0000
5596 +#define SSB_CHIPCO_REVSHIFT 16
5597 +#define SSB_CHIPCO_PACKMASK 0x00F00000
5598 +#define SSB_CHIPCO_PACKSHIFT 20
5599 +#define SSB_CHIPCO_NRCORESMASK 0x0F000000
5600 +#define SSB_CHIPCO_NRCORESSHIFT 24
5601 +#define SSB_CHIPCO_CAP 0x0004 /* Capabilities */
5602 +#define SSB_CHIPCO_CAP_NRUART 0x00000003 /* # of UARTs */
5603 +#define SSB_CHIPCO_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
5604 +#define SSB_CHIPCO_CAP_UARTCLK 0x00000018 /* UART clock select */
5605 +#define SSB_CHIPCO_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
5606 +#define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
5607 +#define SSB_CHIPCO_CAP_EXTBUS 0x000000C0 /* External buses present */
5608 +#define SSB_CHIPCO_CAP_FLASHT 0x00000700 /* Flash Type */
5609 +#define SSB_CHIPCO_FLASHT_NONE 0x00000000 /* No flash */
5610 +#define SSB_CHIPCO_FLASHT_STSER 0x00000100 /* ST serial flash */
5611 +#define SSB_CHIPCO_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
5612 +#define SSB_CHIPCO_FLASHT_PARA 0x00000700 /* Parallel flash */
5613 +#define SSB_CHIPCO_CAP_PLLT 0x00038000 /* PLL Type */
5614 +#define SSB_PLLTYPE_NONE 0x00000000
5615 +#define SSB_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */
5616 +#define SSB_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */
5617 +#define SSB_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
5618 +#define SSB_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */
5619 +#define SSB_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */
5620 +#define SSB_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
5621 +#define SSB_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
5622 +#define SSB_CHIPCO_CAP_PCTL 0x00040000 /* Power Control */
5623 +#define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */
5624 +#define SSB_CHIPCO_CAP_OTPS_SHIFT 19
5625 +#define SSB_CHIPCO_CAP_OTPS_BASE 5
5626 +#define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */
5627 +#define SSB_CHIPCO_CAP_BROM 0x00800000 /* Internal boot ROM active */
5628 +#define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
5629 +#define SSB_CHIPCO_CORECTL 0x0008
5630 +#define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
5631 +#define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
5632 +#define SSB_CHIPCO_BIST 0x000C
5633 +#define SSB_CHIPCO_OTPS 0x0010 /* OTP status */
5634 +#define SSB_CHIPCO_OTPS_PROGFAIL 0x80000000
5635 +#define SSB_CHIPCO_OTPS_PROTECT 0x00000007
5636 +#define SSB_CHIPCO_OTPS_HW_PROTECT 0x00000001
5637 +#define SSB_CHIPCO_OTPS_SW_PROTECT 0x00000002
5638 +#define SSB_CHIPCO_OTPS_CID_PROTECT 0x00000004
5639 +#define SSB_CHIPCO_OTPC 0x0014 /* OTP control */
5640 +#define SSB_CHIPCO_OTPC_RECWAIT 0xFF000000
5641 +#define SSB_CHIPCO_OTPC_PROGWAIT 0x00FFFF00
5642 +#define SSB_CHIPCO_OTPC_PRW_SHIFT 8
5643 +#define SSB_CHIPCO_OTPC_MAXFAIL 0x00000038
5644 +#define SSB_CHIPCO_OTPC_VSEL 0x00000006
5645 +#define SSB_CHIPCO_OTPC_SELVL 0x00000001
5646 +#define SSB_CHIPCO_OTPP 0x0018 /* OTP prog */
5647 +#define SSB_CHIPCO_OTPP_COL 0x000000FF
5648 +#define SSB_CHIPCO_OTPP_ROW 0x0000FF00
5649 +#define SSB_CHIPCO_OTPP_ROW_SHIFT 8
5650 +#define SSB_CHIPCO_OTPP_READERR 0x10000000
5651 +#define SSB_CHIPCO_OTPP_VALUE 0x20000000
5652 +#define SSB_CHIPCO_OTPP_READ 0x40000000
5653 +#define SSB_CHIPCO_OTPP_START 0x80000000
5654 +#define SSB_CHIPCO_OTPP_BUSY 0x80000000
5655 +#define SSB_CHIPCO_IRQSTAT 0x0020
5656 +#define SSB_CHIPCO_IRQMASK 0x0024
5657 +#define SSB_CHIPCO_IRQ_GPIO 0x00000001 /* gpio intr */
5658 +#define SSB_CHIPCO_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
5659 +#define SSB_CHIPCO_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
5660 +#define SSB_CHIPCO_CHIPCTL 0x0028 /* Rev >= 11 only */
5661 +#define SSB_CHIPCO_CHIPSTAT 0x002C /* Rev >= 11 only */
5662 +#define SSB_CHIPCO_JCMD 0x0030 /* Rev >= 10 only */
5663 +#define SSB_CHIPCO_JCMD_START 0x80000000
5664 +#define SSB_CHIPCO_JCMD_BUSY 0x80000000
5665 +#define SSB_CHIPCO_JCMD_PAUSE 0x40000000
5666 +#define SSB_CHIPCO_JCMD0_ACC_MASK 0x0000F000
5667 +#define SSB_CHIPCO_JCMD0_ACC_IRDR 0x00000000
5668 +#define SSB_CHIPCO_JCMD0_ACC_DR 0x00001000
5669 +#define SSB_CHIPCO_JCMD0_ACC_IR 0x00002000
5670 +#define SSB_CHIPCO_JCMD0_ACC_RESET 0x00003000
5671 +#define SSB_CHIPCO_JCMD0_ACC_IRPDR 0x00004000
5672 +#define SSB_CHIPCO_JCMD0_ACC_PDR 0x00005000
5673 +#define SSB_CHIPCO_JCMD0_IRW_MASK 0x00000F00
5674 +#define SSB_CHIPCO_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
5675 +#define SSB_CHIPCO_JCMD_ACC_IRDR 0x00000000
5676 +#define SSB_CHIPCO_JCMD_ACC_DR 0x00010000
5677 +#define SSB_CHIPCO_JCMD_ACC_IR 0x00020000
5678 +#define SSB_CHIPCO_JCMD_ACC_RESET 0x00030000
5679 +#define SSB_CHIPCO_JCMD_ACC_IRPDR 0x00040000
5680 +#define SSB_CHIPCO_JCMD_ACC_PDR 0x00050000
5681 +#define SSB_CHIPCO_JCMD_IRW_MASK 0x00001F00
5682 +#define SSB_CHIPCO_JCMD_IRW_SHIFT 8
5683 +#define SSB_CHIPCO_JCMD_DRW_MASK 0x0000003F
5684 +#define SSB_CHIPCO_JIR 0x0034 /* Rev >= 10 only */
5685 +#define SSB_CHIPCO_JDR 0x0038 /* Rev >= 10 only */
5686 +#define SSB_CHIPCO_JCTL 0x003C /* Rev >= 10 only */
5687 +#define SSB_CHIPCO_JCTL_FORCE_CLK 4 /* Force clock */
5688 +#define SSB_CHIPCO_JCTL_EXT_EN 2 /* Enable external targets */
5689 +#define SSB_CHIPCO_JCTL_EN 1 /* Enable Jtag master */
5690 +#define SSB_CHIPCO_FLASHCTL 0x0040
5691 +#define SSB_CHIPCO_FLASHCTL_START 0x80000000
5692 +#define SSB_CHIPCO_FLASHCTL_BUSY SSB_CHIPCO_FLASHCTL_START
5693 +#define SSB_CHIPCO_FLASHADDR 0x0044
5694 +#define SSB_CHIPCO_FLASHDATA 0x0048
5695 +#define SSB_CHIPCO_BCAST_ADDR 0x0050
5696 +#define SSB_CHIPCO_BCAST_DATA 0x0054
5697 +#define SSB_CHIPCO_GPIOIN 0x0060
5698 +#define SSB_CHIPCO_GPIOOUT 0x0064
5699 +#define SSB_CHIPCO_GPIOOUTEN 0x0068
5700 +#define SSB_CHIPCO_GPIOCTL 0x006C
5701 +#define SSB_CHIPCO_GPIOPOL 0x0070
5702 +#define SSB_CHIPCO_GPIOIRQ 0x0074
5703 +#define SSB_CHIPCO_WATCHDOG 0x0080
5704 +#define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
5705 +#define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
5706 +#define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
5707 +#define SSB_CHIPCO_CLOCK_N 0x0090
5708 +#define SSB_CHIPCO_CLOCK_SB 0x0094
5709 +#define SSB_CHIPCO_CLOCK_PCI 0x0098
5710 +#define SSB_CHIPCO_CLOCK_M2 0x009C
5711 +#define SSB_CHIPCO_CLOCK_MIPS 0x00A0
5712 +#define SSB_CHIPCO_CLKDIV 0x00A4 /* Rev >= 3 only */
5713 +#define SSB_CHIPCO_CLKDIV_SFLASH 0x0F000000
5714 +#define SSB_CHIPCO_CLKDIV_SFLASH_SHIFT 24
5715 +#define SSB_CHIPCO_CLKDIV_OTP 0x000F0000
5716 +#define SSB_CHIPCO_CLKDIV_OTP_SHIFT 16
5717 +#define SSB_CHIPCO_CLKDIV_JTAG 0x00000F00
5718 +#define SSB_CHIPCO_CLKDIV_JTAG_SHIFT 8
5719 +#define SSB_CHIPCO_CLKDIV_UART 0x000000FF
5720 +#define SSB_CHIPCO_PLLONDELAY 0x00B0 /* Rev >= 4 only */
5721 +#define SSB_CHIPCO_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
5722 +#define SSB_CHIPCO_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
5723 +#define SSB_CHIPCO_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */
5724 +#define SSB_CHIPCO_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */
5725 +#define SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
5726 +#define SSB_CHIPCO_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */
5727 +#define SSB_CHIPCO_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
5728 +#define SSB_CHIPCO_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
5729 +#define SSB_CHIPCO_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
5730 +#define SSB_CHIPCO_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
5731 +#define SSB_CHIPCO_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
5732 +#define SSB_CHIPCO_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
5733 +#define SSB_CHIPCO_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
5734 +#define SSB_CHIPCO_SLOWCLKCTL_CLKDIV_SHIFT 16
5735 +#define SSB_CHIPCO_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
5736 +#define SSB_CHIPCO_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
5737 +#define SSB_CHIPCO_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
5738 +#define SSB_CHIPCO_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */
5739 +#define SSB_CHIPCO_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
5740 +#define SSB_CHIPCO_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
5741 +#define SSB_CHIPCO_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
5742 +#define SSB_CHIPCO_SYSCLKCTL_CLKDIV_SHIFT 16
5743 +#define SSB_CHIPCO_CLKSTSTR 0x00C4 /* Rev >= 3 only */
5744 +#define SSB_CHIPCO_PCMCIA_CFG 0x0100
5745 +#define SSB_CHIPCO_PCMCIA_MEMWAIT 0x0104
5746 +#define SSB_CHIPCO_PCMCIA_ATTRWAIT 0x0108
5747 +#define SSB_CHIPCO_PCMCIA_IOWAIT 0x010C
5748 +#define SSB_CHIPCO_IDE_CFG 0x0110
5749 +#define SSB_CHIPCO_IDE_MEMWAIT 0x0114
5750 +#define SSB_CHIPCO_IDE_ATTRWAIT 0x0118
5751 +#define SSB_CHIPCO_IDE_IOWAIT 0x011C
5752 +#define SSB_CHIPCO_PROG_CFG 0x0120
5753 +#define SSB_CHIPCO_PROG_WAITCNT 0x0124
5754 +#define SSB_CHIPCO_FLASH_CFG 0x0128
5755 +#define SSB_CHIPCO_FLASH_WAITCNT 0x012C
5756 +#define SSB_CHIPCO_UART0_DATA 0x0300
5757 +#define SSB_CHIPCO_UART0_IMR 0x0304
5758 +#define SSB_CHIPCO_UART0_FCR 0x0308
5759 +#define SSB_CHIPCO_UART0_LCR 0x030C
5760 +#define SSB_CHIPCO_UART0_MCR 0x0310
5761 +#define SSB_CHIPCO_UART0_LSR 0x0314
5762 +#define SSB_CHIPCO_UART0_MSR 0x0318
5763 +#define SSB_CHIPCO_UART0_SCRATCH 0x031C
5764 +#define SSB_CHIPCO_UART1_DATA 0x0400
5765 +#define SSB_CHIPCO_UART1_IMR 0x0404
5766 +#define SSB_CHIPCO_UART1_FCR 0x0408
5767 +#define SSB_CHIPCO_UART1_LCR 0x040C
5768 +#define SSB_CHIPCO_UART1_MCR 0x0410
5769 +#define SSB_CHIPCO_UART1_LSR 0x0414
5770 +#define SSB_CHIPCO_UART1_MSR 0x0418
5771 +#define SSB_CHIPCO_UART1_SCRATCH 0x041C
5772 +
5773 +
5774 +
5775 +/** Clockcontrol masks and values **/
5776 +
5777 +/* SSB_CHIPCO_CLOCK_N */
5778 +#define SSB_CHIPCO_CLK_N1 0x0000003F /* n1 control */
5779 +#define SSB_CHIPCO_CLK_N2 0x00003F00 /* n2 control */
5780 +#define SSB_CHIPCO_CLK_N2_SHIFT 8
5781 +#define SSB_CHIPCO_CLK_PLLC 0x000F0000 /* pll control */
5782 +#define SSB_CHIPCO_CLK_PLLC_SHIFT 16
5783 +
5784 +/* SSB_CHIPCO_CLOCK_SB/PCI/UART */
5785 +#define SSB_CHIPCO_CLK_M1 0x0000003F /* m1 control */
5786 +#define SSB_CHIPCO_CLK_M2 0x00003F00 /* m2 control */
5787 +#define SSB_CHIPCO_CLK_M2_SHIFT 8
5788 +#define SSB_CHIPCO_CLK_M3 0x003F0000 /* m3 control */
5789 +#define SSB_CHIPCO_CLK_M3_SHIFT 16
5790 +#define SSB_CHIPCO_CLK_MC 0x1F000000 /* mux control */
5791 +#define SSB_CHIPCO_CLK_MC_SHIFT 24
5792 +
5793 +/* N3M Clock control magic field values */
5794 +#define SSB_CHIPCO_CLK_F6_2 0x02 /* A factor of 2 in */
5795 +#define SSB_CHIPCO_CLK_F6_3 0x03 /* 6-bit fields like */
5796 +#define SSB_CHIPCO_CLK_F6_4 0x05 /* N1, M1 or M3 */
5797 +#define SSB_CHIPCO_CLK_F6_5 0x09
5798 +#define SSB_CHIPCO_CLK_F6_6 0x11
5799 +#define SSB_CHIPCO_CLK_F6_7 0x21
5800 +
5801 +#define SSB_CHIPCO_CLK_F5_BIAS 5 /* 5-bit fields get this added */
5802 +
5803 +#define SSB_CHIPCO_CLK_MC_BYPASS 0x08
5804 +#define SSB_CHIPCO_CLK_MC_M1 0x04
5805 +#define SSB_CHIPCO_CLK_MC_M1M2 0x02
5806 +#define SSB_CHIPCO_CLK_MC_M1M2M3 0x01
5807 +#define SSB_CHIPCO_CLK_MC_M1M3 0x11
5808 +
5809 +/* Type 2 Clock control magic field values */
5810 +#define SSB_CHIPCO_CLK_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
5811 +#define SSB_CHIPCO_CLK_T2M2_BIAS 3 /* m2 bias */
5812 +
5813 +#define SSB_CHIPCO_CLK_T2MC_M1BYP 1
5814 +#define SSB_CHIPCO_CLK_T2MC_M2BYP 2
5815 +#define SSB_CHIPCO_CLK_T2MC_M3BYP 4
5816 +
5817 +/* Type 6 Clock control magic field values */
5818 +#define SSB_CHIPCO_CLK_T6_MMASK 1 /* bits of interest in m */
5819 +#define SSB_CHIPCO_CLK_T6_M0 120000000 /* sb clock for m = 0 */
5820 +#define SSB_CHIPCO_CLK_T6_M1 100000000 /* sb clock for m = 1 */
5821 +#define SSB_CHIPCO_CLK_SB2MIPS_T6(sb) (2 * (sb))
5822 +
5823 +/* Common clock base */
5824 +#define SSB_CHIPCO_CLK_BASE1 24000000 /* Half the clock freq */
5825 +#define SSB_CHIPCO_CLK_BASE2 12500000 /* Alternate crystal on some PLL's */
5826 +
5827 +/* Clock control values for 200Mhz in 5350 */
5828 +#define SSB_CHIPCO_CLK_5350_N 0x0311
5829 +#define SSB_CHIPCO_CLK_5350_M 0x04020009
5830 +
5831 +
5832 +/** Bits in the config registers **/
5833 +
5834 +#define SSB_CHIPCO_CFG_EN 0x0001 /* Enable */
5835 +#define SSB_CHIPCO_CFG_EXTM 0x000E /* Extif Mode */
5836 +#define SSB_CHIPCO_CFG_EXTM_ASYNC 0x0002 /* Async/Parallel flash */
5837 +#define SSB_CHIPCO_CFG_EXTM_SYNC 0x0004 /* Synchronous */
5838 +#define SSB_CHIPCO_CFG_EXTM_PCMCIA 0x0008 /* PCMCIA */
5839 +#define SSB_CHIPCO_CFG_EXTM_IDE 0x000A /* IDE */
5840 +#define SSB_CHIPCO_CFG_DS16 0x0010 /* Data size, 0=8bit, 1=16bit */
5841 +#define SSB_CHIPCO_CFG_CLKDIV 0x0060 /* Sync: Clock divisor */
5842 +#define SSB_CHIPCO_CFG_CLKEN 0x0080 /* Sync: Clock enable */
5843 +#define SSB_CHIPCO_CFG_BSTRO 0x0100 /* Sync: Size/Bytestrobe */
5844 +
5845 +
5846 +/** Flash-specific control/status values */
5847 +
5848 +/* flashcontrol opcodes for ST flashes */
5849 +#define SSB_CHIPCO_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
5850 +#define SSB_CHIPCO_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
5851 +#define SSB_CHIPCO_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
5852 +#define SSB_CHIPCO_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
5853 +#define SSB_CHIPCO_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
5854 +#define SSB_CHIPCO_FLASHCTL_ST_PP 0x0302 /* Page Program */
5855 +#define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
5856 +#define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
5857 +#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
5858 +#define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */
5859 +
5860 +/* Status register bits for ST flashes */
5861 +#define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
5862 +#define SSB_CHIPCO_FLASHSTA_ST_WEL 0x02 /* Write Enable Latch */
5863 +#define SSB_CHIPCO_FLASHSTA_ST_BP 0x1C /* Block Protect */
5864 +#define SSB_CHIPCO_FLASHSTA_ST_BP_SHIFT 2
5865 +#define SSB_CHIPCO_FLASHSTA_ST_SRWD 0x80 /* Status Register Write Disable */
5866 +
5867 +/* flashcontrol opcodes for Atmel flashes */
5868 +#define SSB_CHIPCO_FLASHCTL_AT_READ 0x07E8
5869 +#define SSB_CHIPCO_FLASHCTL_AT_PAGE_READ 0x07D2
5870 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_READ /* FIXME */
5871 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_READ /* FIXME */
5872 +#define SSB_CHIPCO_FLASHCTL_AT_STATUS 0x01D7
5873 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE 0x0384
5874 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRITE 0x0387
5875 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_ERASE_PRGM 0x0283 /* Erase program */
5876 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_ERASE_PRGM 0x0286 /* Erase program */
5877 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM 0x0288
5878 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_PROGRAM 0x0289
5879 +#define SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE 0x0281
5880 +#define SSB_CHIPCO_FLASHCTL_AT_BLOCK_ERASE 0x0250
5881 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRER_PRGM 0x0382 /* Write erase program */
5882 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRER_PRGM 0x0385 /* Write erase program */
5883 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD 0x0253
5884 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_LOAD 0x0255
5885 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_COMPARE 0x0260
5886 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_COMPARE 0x0261
5887 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
5888 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
5889 +
5890 +/* Status register bits for Atmel flashes */
5891 +#define SSB_CHIPCO_FLASHSTA_AT_READY 0x80
5892 +#define SSB_CHIPCO_FLASHSTA_AT_MISMATCH 0x40
5893 +#define SSB_CHIPCO_FLASHSTA_AT_ID 0x38
5894 +#define SSB_CHIPCO_FLASHSTA_AT_ID_SHIFT 3
5895 +
5896 +
5897 +/** OTP **/
5898 +
5899 +/* OTP regions */
5900 +#define SSB_CHIPCO_OTP_HW_REGION SSB_CHIPCO_OTPS_HW_PROTECT
5901 +#define SSB_CHIPCO_OTP_SW_REGION SSB_CHIPCO_OTPS_SW_PROTECT
5902 +#define SSB_CHIPCO_OTP_CID_REGION SSB_CHIPCO_OTPS_CID_PROTECT
5903 +
5904 +/* OTP regions (Byte offsets from otp size) */
5905 +#define SSB_CHIPCO_OTP_SWLIM_OFF (-8)
5906 +#define SSB_CHIPCO_OTP_CIDBASE_OFF 0
5907 +#define SSB_CHIPCO_OTP_CIDLIM_OFF 8
5908 +
5909 +/* Predefined OTP words (Word offset from otp size) */
5910 +#define SSB_CHIPCO_OTP_BOUNDARY_OFF (-4)
5911 +#define SSB_CHIPCO_OTP_HWSIGN_OFF (-3)
5912 +#define SSB_CHIPCO_OTP_SWSIGN_OFF (-2)
5913 +#define SSB_CHIPCO_OTP_CIDSIGN_OFF (-1)
5914 +
5915 +#define SSB_CHIPCO_OTP_CID_OFF 0
5916 +#define SSB_CHIPCO_OTP_PKG_OFF 1
5917 +#define SSB_CHIPCO_OTP_FID_OFF 2
5918 +#define SSB_CHIPCO_OTP_RSV_OFF 3
5919 +#define SSB_CHIPCO_OTP_LIM_OFF 4
5920 +
5921 +#define SSB_CHIPCO_OTP_SIGNATURE 0x578A
5922 +#define SSB_CHIPCO_OTP_MAGIC 0x4E56
5923 +
5924 +
5925 +struct ssb_device;
5926 +struct ssb_serial_port;
5927 +
5928 +struct ssb_chipcommon {
5929 + struct ssb_device *dev;
5930 + u32 capabilities;
5931 + /* Fast Powerup Delay constant */
5932 + u16 fast_pwrup_delay;
5933 +};
5934 +
5935 +extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
5936 +
5937 +#include <linux/pm.h>
5938 +extern void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state);
5939 +extern void ssb_chipco_resume(struct ssb_chipcommon *cc);
5940 +
5941 +extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
5942 + u32 *plltype, u32 *n, u32 *m);
5943 +extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
5944 + unsigned long ns_per_cycle);
5945 +
5946 +enum ssb_clkmode {
5947 + SSB_CLKMODE_SLOW,
5948 + SSB_CLKMODE_FAST,
5949 + SSB_CLKMODE_DYNAMIC,
5950 +};
5951 +
5952 +extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
5953 + enum ssb_clkmode mode);
5954 +
5955 +#ifdef CONFIG_SSB_SERIAL
5956 +extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
5957 + struct ssb_serial_port *ports);
5958 +#endif /* CONFIG_SSB_SERIAL */
5959 +
5960 +#endif /* __KERNEL__ */
5961 +#endif /* LINUX_SSB_CHIPCO_H_ */
5962 diff -urN linux.old/include/linux/ssb/ssb_driver_extif.h linux.dev/include/linux/ssb/ssb_driver_extif.h
5963 --- linux.old/include/linux/ssb/ssb_driver_extif.h 1970-01-01 01:00:00.000000000 +0100
5964 +++ linux.dev/include/linux/ssb/ssb_driver_extif.h 2007-01-26 00:49:32.000000000 +0100
5965 @@ -0,0 +1,163 @@
5966 +/*
5967 + * Hardware-specific External Interface I/O core definitions
5968 + * for the BCM47xx family of SiliconBackplane-based chips.
5969 + *
5970 + * The External Interface core supports a total of three external chip selects
5971 + * supporting external interfaces. One of the external chip selects is
5972 + * used for Flash, one is used for PCMCIA, and the other may be
5973 + * programmed to support either a synchronous interface or an
5974 + * asynchronous interface. The asynchronous interface can be used to
5975 + * support external devices such as UARTs and the BCM2019 Bluetooth
5976 + * baseband processor.
5977 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
5978 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
5979 + *
5980 + * Copyright 2005, Broadcom Corporation
5981 + * Copyright 2006, Michael Buesch
5982 + *
5983 + * Licensed under the GPL version 2. See COPYING for details.
5984 + */
5985 +#ifndef LINUX_SSB_EXTIFCORE_H_
5986 +#define LINUX_SSB_EXTIFCORE_H_
5987 +
5988 +#ifdef __KERNEL__
5989 +
5990 +struct ssb_extif {
5991 + struct ssb_device *dev;
5992 +};
5993 +
5994 +/* external interface address space */
5995 +#define SSB_EXTIF_PCMCIA_MEMBASE(x) (x)
5996 +#define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
5997 +#define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
5998 +#define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
5999 +#define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
6000 +
6001 +#define SSB_EXTIF_NR_GPIOOUT 5
6002 +/* GPIO NOTE:
6003 + * The multiple instances of output and output enable registers
6004 + * are present to allow driver software for multiple cores to control
6005 + * gpio outputs without needing to share a single register pair.
6006 + * Use the following helper macro to get a register offset value.
6007 + */
6008 +#define SSB_EXTIF_GPIO_OUT(index) ({ \
6009 + BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT); \
6010 + SSB_EXTIF_GPIO_OUT_BASE + ((index) * 8); \
6011 + })
6012 +#define SSB_EXTIF_GPIO_OUTEN(index) ({ \
6013 + BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT); \
6014 + SSB_EXTIF_GPIO_OUTEN_BASE + ((index) * 8); \
6015 + })
6016 +
6017 +/** EXTIF core registers **/
6018 +
6019 +#define SSB_EXTIF_CTL 0x0000
6020 +#define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */
6021 +#define SSB_EXTIF_EXTSTAT 0x0004
6022 +#define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */
6023 +#define SSB_EXTIF_EXTSTAT_EIRQPIN (1 << 1) /* External interrupt pin (ro) */
6024 +#define SSB_EXTIF_EXTSTAT_GPIOIRQPIN (1 << 2) /* GPIO interrupt pin (ro) */
6025 +#define SSB_EXTIF_PCMCIA_CFG 0x0010
6026 +#define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014
6027 +#define SSB_EXTIF_PCMCIA_ATTRWAIT 0x0018
6028 +#define SSB_EXTIF_PCMCIA_IOWAIT 0x001C
6029 +#define SSB_EXTIF_PROG_CFG 0x0020
6030 +#define SSB_EXTIF_PROG_WAITCNT 0x0024
6031 +#define SSB_EXTIF_FLASH_CFG 0x0028
6032 +#define SSB_EXTIF_FLASH_WAITCNT 0x002C
6033 +#define SSB_EXTIF_WATCHDOG 0x0040
6034 +#define SSB_EXTIF_CLOCK_N 0x0044
6035 +#define SSB_EXTIF_CLOCK_SB 0x0048
6036 +#define SSB_EXTIF_CLOCK_PCI 0x004C
6037 +#define SSB_EXTIF_CLOCK_MII 0x0050
6038 +#define SSB_EXTIF_GPIO_IN 0x0060
6039 +#define SSB_EXTIF_GPIO_OUT_BASE 0x0064
6040 +#define SSB_EXTIF_GPIO_OUTEN_BASE 0x0068
6041 +#define SSB_EXTIF_EJTAG_OUTEN 0x0090
6042 +#define SSB_EXTIF_GPIO_INTPOL 0x0094
6043 +#define SSB_EXTIF_GPIO_INTMASK 0x0098
6044 +#define SSB_EXTIF_UART_DATA 0x0300
6045 +#define SSB_EXTIF_UART_TIMER 0x0310
6046 +#define SSB_EXTIF_UART_FCR 0x0320
6047 +#define SSB_EXTIF_UART_LCR 0x0330
6048 +#define SSB_EXTIF_UART_MCR 0x0340
6049 +#define SSB_EXTIF_UART_LSR 0x0350
6050 +#define SSB_EXTIF_UART_MSR 0x0360
6051 +#define SSB_EXTIF_UART_SCRATCH 0x0370
6052 +
6053 +
6054 +
6055 +
6056 +/* pcmcia/prog/flash_config */
6057 +#define SSB_EXTCFG_EN (1 << 0) /* enable */
6058 +#define SSB_EXTCFG_MODE 0xE /* mode */
6059 +#define SSB_EXTCFG_MODE_SHIFT 1
6060 +#define SSB_EXTCFG_MODE_FLASH 0x0 /* flash/asynchronous mode */
6061 +#define SSB_EXTCFG_MODE_SYNC 0x2 /* synchronous mode */
6062 +#define SSB_EXTCFG_MODE_PCMCIA 0x4 /* pcmcia mode */
6063 +#define SSB_EXTCFG_DS16 (1 << 4) /* destsize: 0=8bit, 1=16bit */
6064 +#define SSB_EXTCFG_BSWAP (1 << 5) /* byteswap */
6065 +#define SSB_EXTCFG_CLKDIV 0xC0 /* clock divider */
6066 +#define SSB_EXTCFG_CLKDIV_SHIFT 6
6067 +#define SSB_EXTCFG_CLKDIV_2 0x0 /* backplane/2 */
6068 +#define SSB_EXTCFG_CLKDIV_3 0x40 /* backplane/3 */
6069 +#define SSB_EXTCFG_CLKDIV_4 0x80 /* backplane/4 */
6070 +#define SSB_EXTCFG_CLKEN (1 << 8) /* clock enable */
6071 +#define SSB_EXTCFG_STROBE (1 << 9) /* size/bytestrobe (synch only) */
6072 +
6073 +/* pcmcia_memwait */
6074 +#define SSB_PCMCIA_MEMW_0 0x0000003F /* waitcount0 */
6075 +#define SSB_PCMCIA_MEMW_1 0x00001F00 /* waitcount1 */
6076 +#define SSB_PCMCIA_MEMW_1_SHIFT 8
6077 +#define SSB_PCMCIA_MEMW_2 0x001F0000 /* waitcount2 */
6078 +#define SSB_PCMCIA_MEMW_2_SHIFT 16
6079 +#define SSB_PCMCIA_MEMW_3 0x1F000000 /* waitcount3 */
6080 +#define SSB_PCMCIA_MEMW_3_SHIFT 24
6081 +
6082 +/* pcmcia_attrwait */
6083 +#define SSB_PCMCIA_ATTW_0 0x0000003F /* waitcount0 */
6084 +#define SSB_PCMCIA_ATTW_1 0x00001F00 /* waitcount1 */
6085 +#define SSB_PCMCIA_ATTW_1_SHIFT 8
6086 +#define SSB_PCMCIA_ATTW_2 0x001F0000 /* waitcount2 */
6087 +#define SSB_PCMCIA_ATTW_2_SHIFT 16
6088 +#define SSB_PCMCIA_ATTW_3 0x1F000000 /* waitcount3 */
6089 +#define SSB_PCMCIA_ATTW_3_SHIFT 24
6090 +
6091 +/* pcmcia_iowait */
6092 +#define SSB_PCMCIA_IOW_0 0x0000003F /* waitcount0 */
6093 +#define SSB_PCMCIA_IOW_1 0x00001F00 /* waitcount1 */
6094 +#define SSB_PCMCIA_IOW_1_SHIFT 8
6095 +#define SSB_PCMCIA_IOW_2 0x001F0000 /* waitcount2 */
6096 +#define SSB_PCMCIA_IOW_2_SHIFT 16
6097 +#define SSB_PCMCIA_IOW_3 0x1F000000 /* waitcount3 */
6098 +#define SSB_PCMCIA_IOW_3_SHIFT 24
6099 +
6100 +/* prog_waitcount */
6101 +#define SSB_PROG_WCNT_0 0x0000001F /* waitcount0 */
6102 +#define SSB_PROG_WCNT_1 0x00001F00 /* waitcount1 */
6103 +#define SSB_PROG_WCNT_1_SHIFT 8
6104 +#define SSB_PROG_WCNT_2 0x001F0000 /* waitcount2 */
6105 +#define SSB_PROG_WCNT_2_SHIFT 16
6106 +#define SSB_PROG_WCNT_3 0x1F000000 /* waitcount3 */
6107 +#define SSB_PROG_WCNT_3_SHIFT 24
6108 +
6109 +#define SSB_PROG_W0 0x0000000C
6110 +#define SSB_PROG_W1 0x00000A00
6111 +#define SSB_PROG_W2 0x00020000
6112 +#define SSB_PROG_W3 0x01000000
6113 +
6114 +/* flash_waitcount */
6115 +#define SSB_FLASH_WCNT_0 0x0000001F /* waitcount0 */
6116 +#define SSB_FLASH_WCNT_1 0x00001F00 /* waitcount1 */
6117 +#define SSB_FLASH_WCNT_1_SHIFT 8
6118 +#define SSB_FLASH_WCNT_2 0x001F0000 /* waitcount2 */
6119 +#define SSB_FLASH_WCNT_2_SHIFT 16
6120 +#define SSB_FLASH_WCNT_3 0x1F000000 /* waitcount3 */
6121 +#define SSB_FLASH_WCNT_3_SHIFT 24
6122 +
6123 +/* watchdog */
6124 +#define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
6125 +
6126 +
6127 +#endif /* __KERNEL__ */
6128 +#endif /* LINUX_SSB_EXTIFCORE_H_ */
6129 diff -urN linux.old/include/linux/ssb/ssb_driver_mips.h linux.dev/include/linux/ssb/ssb_driver_mips.h
6130 --- linux.old/include/linux/ssb/ssb_driver_mips.h 1970-01-01 01:00:00.000000000 +0100
6131 +++ linux.dev/include/linux/ssb/ssb_driver_mips.h 2007-01-26 00:49:32.000000000 +0100
6132 @@ -0,0 +1,47 @@
6133 +#ifndef LINUX_SSB_MIPSCORE_H_
6134 +#define LINUX_SSB_MIPSCORE_H_
6135 +
6136 +#ifdef __KERNEL__
6137 +
6138 +#ifdef CONFIG_SSB_DRIVER_MIPS
6139 +
6140 +struct ssb_device;
6141 +
6142 +struct ssb_serial_port {
6143 + void *regs;
6144 + unsigned long clockspeed;
6145 + unsigned int irq;
6146 + unsigned int baud_base;
6147 + unsigned int reg_shift;
6148 +};
6149 +
6150 +
6151 +struct ssb_mipscore {
6152 + struct ssb_device *dev;
6153 +
6154 + int nr_serial_ports;
6155 + struct ssb_serial_port serial_ports[4];
6156 +
6157 + u32 flash_window;
6158 + u32 flash_window_size;
6159 +};
6160 +
6161 +extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
6162 +
6163 +extern unsigned int ssb_mips_irq(struct ssb_device *dev);
6164 +
6165 +
6166 +#else /* CONFIG_SSB_DRIVER_MIPS */
6167 +
6168 +struct ssb_mipscore {
6169 +};
6170 +
6171 +static inline
6172 +void ssb_mipscore_init(struct ssb_mipscore *mcore)
6173 +{
6174 +}
6175 +
6176 +#endif /* CONFIG_SSB_DRIVER_MIPS */
6177 +
6178 +#endif /* __KERNEL__ */
6179 +#endif /* LINUX_SSB_MIPSCORE_H_ */
6180 diff -urN linux.old/include/linux/ssb/ssb_driver_pci.h linux.dev/include/linux/ssb/ssb_driver_pci.h
6181 --- linux.old/include/linux/ssb/ssb_driver_pci.h 1970-01-01 01:00:00.000000000 +0100
6182 +++ linux.dev/include/linux/ssb/ssb_driver_pci.h 2007-01-26 00:49:32.000000000 +0100
6183 @@ -0,0 +1,108 @@
6184 +#ifndef LINUX_SSB_PCICORE_H_
6185 +#define LINUX_SSB_PCICORE_H_
6186 +#ifdef __KERNEL__
6187 +
6188 +#ifdef CONFIG_SSB_DRIVER_PCICORE
6189 +
6190 +/* PCI core registers. */
6191 +#define SSB_PCICORE_CTL 0x0000 /* PCI Control */
6192 +#define SSB_PCICORE_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
6193 +#define SSB_PCICORE_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
6194 +#define SSB_PCICORE_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
6195 +#define SSB_PCICORE_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
6196 +#define SSB_PCICORE_ARBCTL 0x0010 /* PCI Arbiter Control */
6197 +#define SSB_PCICORE_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */
6198 +#define SSB_PCICORE_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */
6199 +#define SSB_PCICORE_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */
6200 +#define SSB_PCICORE_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */
6201 +#define SSB_PCICORE_ARBCTL_PARKID_4710 0x00000002 /* 4710 */
6202 +#define SSB_PCICORE_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */
6203 +#define SSB_PCICORE_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */
6204 +#define SSB_PCICORE_ISTAT 0x0020 /* Interrupt status */
6205 +#define SSB_PCICORE_ISTAT_INTA 0x00000001 /* PCI INTA# */
6206 +#define SSB_PCICORE_ISTAT_INTB 0x00000002 /* PCI INTB# */
6207 +#define SSB_PCICORE_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */
6208 +#define SSB_PCICORE_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */
6209 +#define SSB_PCICORE_ISTAT_PME 0x00000010 /* PCI PME# */
6210 +#define SSB_PCICORE_IMASK 0x0024 /* Interrupt mask */
6211 +#define SSB_PCICORE_IMASK_INTA 0x00000001 /* PCI INTA# */
6212 +#define SSB_PCICORE_IMASK_INTB 0x00000002 /* PCI INTB# */
6213 +#define SSB_PCICORE_IMASK_SERR 0x00000004 /* PCI SERR# */
6214 +#define SSB_PCICORE_IMASK_PERR 0x00000008 /* PCI PERR# */
6215 +#define SSB_PCICORE_IMASK_PME 0x00000010 /* PCI PME# */
6216 +#define SSB_PCICORE_MBOX 0x0028 /* Backplane to PCI Mailbox */
6217 +#define SSB_PCICORE_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */
6218 +#define SSB_PCICORE_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */
6219 +#define SSB_PCICORE_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */
6220 +#define SSB_PCICORE_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */
6221 +#define SSB_PCICORE_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */
6222 +#define SSB_PCICORE_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */
6223 +#define SSB_PCICORE_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */
6224 +#define SSB_PCICORE_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */
6225 +#define SSB_PCICORE_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */
6226 +#define SSB_PCICORE_BCAST_ADDR_MASK 0x000000FF
6227 +#define SSB_PCICORE_BCAST_DATA 0x0054 /* Backplane Broadcast Data */
6228 +#define SSB_PCICORE_GPIO_IN 0x0060 /* rev >= 2 only */
6229 +#define SSB_PCICORE_GPIO_OUT 0x0064 /* rev >= 2 only */
6230 +#define SSB_PCICORE_GPIO_ENABLE 0x0068 /* rev >= 2 only */
6231 +#define SSB_PCICORE_GPIO_CTL 0x006C /* rev >= 2 only */
6232 +#define SSB_PCICORE_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */
6233 +#define SSB_PCICORE_SBTOPCI0_MASK 0xFC000000
6234 +#define SSB_PCICORE_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */
6235 +#define SSB_PCICORE_SBTOPCI1_MASK 0xFC000000
6236 +#define SSB_PCICORE_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
6237 +#define SSB_PCICORE_SBTOPCI2_MASK 0xC0000000
6238 +
6239 +/* SBtoPCIx */
6240 +#define SSB_PCICORE_SBTOPCI_MEM 0x00000000
6241 +#define SSB_PCICORE_SBTOPCI_IO 0x00000001
6242 +#define SSB_PCICORE_SBTOPCI_CFG0 0x00000002
6243 +#define SSB_PCICORE_SBTOPCI_CFG1 0x00000003
6244 +#define SSB_PCICORE_SBTOPCI_PREF 0x00000004 /* Prefetch enable */
6245 +#define SSB_PCICORE_SBTOPCI_BURST 0x00000008 /* Burst enable */
6246 +#define SSB_PCICORE_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */
6247 +#define SSB_PCICORE_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */
6248 +#define SSB_PCICORE_SBTOPCI_RC_READ 0x00000000 /* Memory read */
6249 +#define SSB_PCICORE_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
6250 +#define SSB_PCICORE_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
6251 +
6252 +
6253 +/* PCIcore specific boardflags */
6254 +#define SSB_PCICORE_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
6255 +
6256 +
6257 +struct ssb_pcicore {
6258 + struct ssb_device *dev;
6259 + u8 setup_done:1;
6260 + u8 hostmode:1;
6261 + u8 cardbusmode:1;
6262 +};
6263 +
6264 +extern void ssb_pcicore_init(struct ssb_pcicore *pc);
6265 +
6266 +/* Enable IRQ routing for a specific device */
6267 +extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
6268 + struct ssb_device *dev);
6269 +
6270 +
6271 +#else /* CONFIG_SSB_DRIVER_PCICORE */
6272 +
6273 +
6274 +struct ssb_pcicore {
6275 +};
6276 +
6277 +static inline
6278 +void ssb_pcicore_init(struct ssb_pcicore *pc)
6279 +{
6280 +}
6281 +
6282 +static inline
6283 +int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
6284 + struct ssb_device *dev)
6285 +{
6286 + return 0;
6287 +}
6288 +
6289 +#endif /* CONFIG_SSB_DRIVER_PCICORE */
6290 +#endif /* __KERNEL__ */
6291 +#endif /* LINUX_SSB_PCICORE_H_ */
6292 diff -urN linux.old/include/linux/ssb/ssb.h linux.dev/include/linux/ssb/ssb.h
6293 --- linux.old/include/linux/ssb/ssb.h 1970-01-01 01:00:00.000000000 +0100
6294 +++ linux.dev/include/linux/ssb/ssb.h 2007-01-26 00:49:32.000000000 +0100
6295 @@ -0,0 +1,358 @@
6296 +#ifndef LINUX_SSB_H_
6297 +#define LINUX_SSB_H_
6298 +#ifdef __KERNEL__
6299 +
6300 +#include <linux/device.h>
6301 +#include <linux/list.h>
6302 +#include <linux/types.h>
6303 +#include <linux/spinlock.h>
6304 +
6305 +#include <linux/ssb/ssb_regs.h>
6306 +
6307 +
6308 +struct pcmcia_device;
6309 +struct ssb_bus;
6310 +struct ssb_driver;
6311 +
6312 +
6313 +struct ssb_sprom_r1 {
6314 + u16 pci_spid; /* Subsystem Product ID for PCI */
6315 + u16 pci_svid; /* Subsystem Vendor ID for PCI */
6316 + u16 pci_pid; /* Product ID for PCI */
6317 + u8 il0mac[6]; /* MAC address for 802.11b/g */
6318 + u8 et0mac[6]; /* MAC address for Ethernet */
6319 + u8 et1mac[6]; /* MAC address for 802.11a */
6320 + u8 et0phyaddr:5; /* MII address for enet0 */
6321 + u8 et1phyaddr:5; /* MII address for enet1 */
6322 + u8 et0mdcport:1; /* MDIO for enet0 */
6323 + u8 et1mdcport:1; /* MDIO for enet1 */
6324 + u8 board_rev; /* Board revision */
6325 + u8 country_code:4; /* Country Code */
6326 + u8 antenna_a:2; /* Antenna 0/1 available for A-PHY */
6327 + u8 antenna_bg:2; /* Antenna 0/1 available for B-PHY and G-PHY */
6328 + u16 pa0b0;
6329 + u16 pa0b1;
6330 + u16 pa0b2;
6331 + u16 pa1b0;
6332 + u16 pa1b1;
6333 + u16 pa1b2;
6334 + u8 gpio0; /* GPIO pin 0 */
6335 + u8 gpio1; /* GPIO pin 1 */
6336 + u8 gpio2; /* GPIO pin 2 */
6337 + u8 gpio3; /* GPIO pin 3 */
6338 + u16 maxpwr_a; /* A-PHY Power Amplifier Max Power (in dBm Q5.2) */
6339 + u16 maxpwr_bg; /* B/G-PHY Power Amplifier Max Power (in dBm Q5.2) */
6340 + u8 itssi_a; /* Idle TSSI Target for A-PHY */
6341 + u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
6342 + u16 boardflags_lo; /* Boardflags (low 16 bits) */
6343 + u8 antenna_gain_a; /* A-PHY Antenna gain (in dBm Q5.2) */
6344 + u8 antenna_gain_bg; /* B/G-PHY Antenna gain (in dBm Q5.2) */
6345 + u8 oem[8]; /* OEM string (rev 1 only) */
6346 +};
6347 +
6348 +struct ssb_sprom_r2 {
6349 + u16 boardflags_hi; /* Boardflags (high 16 bits) */
6350 + u8 maxpwr_a_lo; /* A-PHY Max Power Low */
6351 + u8 maxpwr_a_hi; /* A-PHY Max Power High */
6352 + u16 pa1lob0; /* A-PHY PA Low Settings */
6353 + u16 pa1lob1; /* A-PHY PA Low Settings */
6354 + u16 pa1lob2; /* A-PHY PA Low Settings */
6355 + u16 pa1hib0; /* A-PHY PA High Settings */
6356 + u16 pa1hib1; /* A-PHY PA High Settings */
6357 + u16 pa1hib2; /* A-PHY PA High Settings */
6358 + u8 ofdm_pwr_off; /* OFDM Power Offset from CCK Level */
6359 + u8 country_str[2]; /* Two char Country Code */
6360 +};
6361 +
6362 +struct ssb_sprom_r3 {
6363 + u32 ofdmapo; /* A-PHY OFDM Mid Power Offset */
6364 + u32 ofdmalpo; /* A-PHY OFDM Low Power Offset */
6365 + u32 ofdmahpo; /* A-PHY OFDM High Power Offset */
6366 + u8 gpioldc_on_cnt; /* GPIO LED Powersave Duty Cycle ON count */
6367 + u8 gpioldc_off_cnt; /* GPIO LED Powersave Duty Cycle OFF count */
6368 + u8 cckpo_1M:4; /* CCK Power Offset for Rate 1M */
6369 + u8 cckpo_2M:4; /* CCK Power Offset for Rate 2M */
6370 + u8 cckpo_55M:4; /* CCK Power Offset for Rate 5.5M */
6371 + u8 cckpo_11M:4; /* CCK Power Offset for Rate 11M */
6372 + u32 ofdmgpo; /* G-PHY OFDM Power Offset */
6373 +};
6374 +
6375 +struct ssb_sprom_r4 {
6376 + /* TODO */
6377 +};
6378 +
6379 +struct ssb_sprom {
6380 + u8 revision;
6381 + u8 crc;
6382 + /* The valid r# fields are selected by the "revision".
6383 + * Revision 3 and lower inherit from lower revisions.
6384 + */
6385 + union {
6386 + struct {
6387 + struct ssb_sprom_r1 r1;
6388 + struct ssb_sprom_r2 r2;
6389 + struct ssb_sprom_r3 r3;
6390 + };
6391 + struct ssb_sprom_r4 r4;
6392 + };
6393 +};
6394 +
6395 +
6396 +/* Core-ID values. */
6397 +#define SSB_DEV_CHIPCOMMON 0x800
6398 +#define SSB_DEV_ILINE20 0x801
6399 +#define SSB_DEV_SDRAM 0x803
6400 +#define SSB_DEV_PCI 0x804
6401 +#define SSB_DEV_MIPS 0x805
6402 +#define SSB_DEV_ETHERNET 0x806
6403 +#define SSB_DEV_V90 0x807
6404 +#define SSB_DEV_USB11_HOSTDEV 0x808
6405 +#define SSB_DEV_ADSL 0x809
6406 +#define SSB_DEV_ILINE100 0x80A
6407 +#define SSB_DEV_IPSEC 0x80B
6408 +#define SSB_DEV_PCMCIA 0x80D
6409 +#define SSB_DEV_INTERNAL_MEM 0x80E
6410 +#define SSB_DEV_MEMC_SDRAM 0x80F
6411 +#define SSB_DEV_EXTIF 0x811
6412 +#define SSB_DEV_80211 0x812
6413 +#define SSB_DEV_MIPS_3302 0x816
6414 +#define SSB_DEV_USB11_HOST 0x817
6415 +#define SSB_DEV_USB11_DEV 0x818
6416 +#define SSB_DEV_USB20_HOST 0x819
6417 +#define SSB_DEV_USB20_DEV 0x81A
6418 +#define SSB_DEV_SDIO_HOST 0x81B
6419 +#define SSB_DEV_ROBOSWITCH 0x81C
6420 +#define SSB_DEV_PARA_ATA 0x81D
6421 +#define SSB_DEV_SATA_XORDMA 0x81E
6422 +#define SSB_DEV_ETHERNET_GBIT 0x81F
6423 +#define SSB_DEV_PCIE 0x820
6424 +#define SSB_DEV_MIMO_PHY 0x821
6425 +#define SSB_DEV_SRAM_CTRLR 0x822
6426 +#define SSB_DEV_MINI_MACPHY 0x823
6427 +#define SSB_DEV_ARM_1176 0x824
6428 +#define SSB_DEV_ARM_7TDMI 0x825
6429 +
6430 +/* Vendor-ID values */
6431 +#define SSB_VENDOR_BROADCOM 0x4243
6432 +
6433 +struct ssb_device_id {
6434 + u16 vendor;
6435 + u16 coreid;
6436 + u8 revision;
6437 +};
6438 +#define SSB_DEVICE(_vendor, _coreid, _revision) \
6439 + { .vendor = _vendor, .coreid = _coreid, .revision = _revision, }
6440 +#define SSB_DEVTABLE_END \
6441 + { 0, },
6442 +
6443 +#define SSB_ANY_VENDOR 0xFFFF
6444 +#define SSB_ANY_ID 0xFFFF
6445 +#define SSB_ANY_REV 0xFF
6446 +
6447 +
6448 +struct ssb_device {
6449 + struct device dev;
6450 + struct ssb_bus *bus;
6451 + struct ssb_device_id id;
6452 +
6453 + u8 core_index;
6454 + unsigned int irq;
6455 + void *drvdata; /* Per-device data */
6456 + void *devtypedata; /* Per-devicetype (eg 802.11) data */
6457 +};
6458 +#define dev_to_ssb_dev(_dev) container_of(_dev, struct ssb_device, dev)
6459 +
6460 +/* Device specific user data */
6461 +static inline
6462 +void ssb_set_drvdata(struct ssb_device *dev, void *data)
6463 +{
6464 + dev->drvdata = data;
6465 +}
6466 +static inline
6467 +void * ssb_get_drvdata(struct ssb_device *dev)
6468 +{
6469 + return dev->drvdata;
6470 +}
6471 +
6472 +/* Devicetype specific user data. This is per device-type (not per device) */
6473 +void ssb_set_devtypedata(struct ssb_device *dev, void *data);
6474 +static inline
6475 +void * ssb_get_devtypedata(struct ssb_device *dev)
6476 +{
6477 + return dev->devtypedata;
6478 +}
6479 +
6480 +struct ssb_bus_ops {
6481 + u16 (*read16)(struct ssb_device *dev, u16 offset);
6482 + u32 (*read32)(struct ssb_device *dev, u16 offset);
6483 + void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
6484 + void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
6485 +};
6486 +
6487 +
6488 +struct ssb_driver {
6489 + const char *name;
6490 + const struct ssb_device_id *id_table;
6491 +
6492 + int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id);
6493 + void (*remove)(struct ssb_device *dev);
6494 + int (*suspend)(struct ssb_device *dev, pm_message_t state);
6495 + int (*resume)(struct ssb_device *dev);
6496 + void (*shutdown)(struct ssb_device *dev);
6497 +
6498 + struct device_driver drv;
6499 +};
6500 +#define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
6501 +
6502 +extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
6503 +static inline int ssb_driver_register(struct ssb_driver *drv)
6504 +{
6505 + return __ssb_driver_register(drv, THIS_MODULE);
6506 +}
6507 +extern void ssb_driver_unregister(struct ssb_driver *drv);
6508 +
6509 +
6510 +
6511 +
6512 +enum ssb_bustype {
6513 + SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */
6514 + SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */
6515 + SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */
6516 + //TODO SSB_BUSTYPE_JTAG,
6517 +};
6518 +
6519 +/* board_vendor */
6520 +#define SSB_BOARDVENDOR_BCM 0x14E4 /* Broadcom */
6521 +#define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */
6522 +#define SSB_BOARDVENDOR_HP 0x0E11 /* HP */
6523 +/* board_type */
6524 +#define SSB_BOARD_BCM94306MP 0x0418
6525 +#define SSB_BOARD_BCM4309G 0x0421
6526 +#define SSB_BOARD_BCM4306CB 0x0417
6527 +#define SSB_BOARD_BCM4309MP 0x040C
6528 +#define SSB_BOARD_MP4318 0x044A
6529 +#define SSB_BOARD_BU4306 0x0416
6530 +#define SSB_BOARD_BU4309 0x040A
6531 +/* chip_package */
6532 +#define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */
6533 +#define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */
6534 +#define SSB_CHIPPACK_BCM4712L 0 /* Large 340pin 4712 */
6535 +
6536 +#include <linux/ssb/ssb_driver_chipcommon.h>
6537 +#include <linux/ssb/ssb_driver_mips.h>
6538 +#include <linux/ssb/ssb_driver_extif.h>
6539 +#include <linux/ssb/ssb_driver_pci.h>
6540 +
6541 +struct ssb_bus {
6542 + /* The MMIO area. */
6543 + void __iomem *mmio;
6544 +
6545 + const struct ssb_bus_ops *ops;
6546 +
6547 + /* The core in the basic address register window. (PCI bus only) */
6548 + struct ssb_device *mapped_device;
6549 + /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
6550 + u8 mapped_pcmcia_seg;
6551 + /* Lock for core and segment switching. */
6552 + spinlock_t bar_lock;
6553 +
6554 + /* The bus this backplane is running on. */
6555 + enum ssb_bustype bustype;
6556 + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
6557 + struct pci_dev *host_pci;
6558 + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
6559 + struct pcmcia_device *host_pcmcia;
6560 +
6561 + /* ID information about the PCB. */
6562 + u16 board_vendor;
6563 + u16 board_type;
6564 + u16 board_rev;
6565 + /* ID information about the Chip. */
6566 + u16 chip_id;
6567 + u16 chip_rev;
6568 + u8 chip_package;
6569 +
6570 + /* Contents of the SPROM.
6571 + * If there is no sprom (not on PCI-bus), this is emulated. */
6572 + struct ssb_sprom sprom;
6573 +
6574 + /* List of devices (cores) on the backplane. */
6575 + struct ssb_device devices[SSB_MAX_NR_CORES];
6576 + u8 nr_devices;
6577 +
6578 + /* Reference count. Number of suspended devices. */
6579 + u8 suspend_cnt;
6580 +
6581 + /* Software ID number for this bus. */
6582 + int busnumber;
6583 +
6584 + /* The ChipCommon device (if available). */
6585 + struct ssb_chipcommon chipco;
6586 + /* The PCI-core device (if available). */
6587 + struct ssb_pcicore pcicore;
6588 + /* The MIPS-core device (if available). */
6589 + struct ssb_mipscore mipscore;
6590 + /* The EXTif-core device (if available). */
6591 + struct ssb_extif extif;
6592 +
6593 + /* Internal. */
6594 + struct list_head list;
6595 +};
6596 +
6597 +extern int ssb_bus_ssbbus_register(struct ssb_bus *bus,
6598 + unsigned long baseaddr,
6599 + void (*fill_sprom)(struct ssb_sprom *sprom));
6600 +#ifdef CONFIG_SSB_PCIHOST
6601 +extern int ssb_bus_pcibus_register(struct ssb_bus *bus,
6602 + struct pci_dev *host_pci);
6603 +#endif /* CONFIG_SSB_PCIHOST */
6604 +#ifdef CONFIG_SSB_PCMCIAHOST
6605 +extern int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
6606 + struct pcmcia_device *pcmcia_dev,
6607 + unsigned long baseaddr,
6608 + void (*fill_sprom)(struct ssb_sprom *sprom));
6609 +#endif /* CONFIG_SSB_PCMCIAHOST */
6610 +
6611 +extern void ssb_bus_unregister(struct ssb_bus *bus);
6612 +
6613 +extern u32 ssb_clockspeed(struct ssb_bus *bus);
6614 +
6615 +int ssb_device_is_enabled(struct ssb_device *dev);
6616 +void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags);
6617 +void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags);
6618 +
6619 +
6620 +static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
6621 +{
6622 + return dev->bus->ops->read16(dev, offset);
6623 +}
6624 +static inline u32 ssb_read32(struct ssb_device *dev, u16 offset)
6625 +{
6626 + return dev->bus->ops->read32(dev, offset);
6627 +}
6628 +static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
6629 +{
6630 + dev->bus->ops->write16(dev, offset, value);
6631 +}
6632 +static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
6633 +{
6634 + dev->bus->ops->write32(dev, offset, value);
6635 +}
6636 +
6637 +
6638 +/* Translation (routing) bits that need to be ORed to DMA
6639 + * addresses before they are given to a device. */
6640 +extern u32 ssb_dma_translation(struct ssb_device *dev);
6641 +#define SSB_DMA_TRANSLATION_MASK 0xC0000000
6642 +#define SSB_DMA_TRANSLATION_SHIFT 30
6643 +
6644 +extern int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask);
6645 +
6646 +
6647 +/* Various helper functions */
6648 +extern u32 ssb_admatch_base(u32 adm);
6649 +extern u32 ssb_admatch_size(u32 adm);
6650 +
6651 +
6652 +#endif /* __KERNEL__ */
6653 +#endif /* LINUX_SSB_H_ */
6654 diff -urN linux.old/include/linux/ssb/ssb_regs.h linux.dev/include/linux/ssb/ssb_regs.h
6655 --- linux.old/include/linux/ssb/ssb_regs.h 1970-01-01 01:00:00.000000000 +0100
6656 +++ linux.dev/include/linux/ssb/ssb_regs.h 2007-01-26 00:49:32.000000000 +0100
6657 @@ -0,0 +1,293 @@
6658 +#ifndef LINUX_SSB_REGS_H_
6659 +#define LINUX_SSB_REGS_H_
6660 +#ifdef __KERNEL__
6661 +
6662 +
6663 +/* SiliconBackplane Address Map.
6664 + * All regions may not exist on all chips.
6665 + */
6666 +#define SSB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
6667 +#define SSB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
6668 +#define SSB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
6669 +#define SSB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6670 +#define SSB_ENUM_BASE 0x18000000 /* Enumeration space base */
6671 +#define SSB_ENUM_LIMIT 0x18010000 /* Enumeration space limit */
6672 +
6673 +#define SSB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
6674 +#define SSB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
6675 +
6676 +#define SSB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
6677 +#define SSB_FLASH1 0x1fc00000 /* Flash Region 1 */
6678 +#define SSB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
6679 +
6680 +#define SSB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
6681 +#define SSB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
6682 +#define SSB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
6683 +#define SSB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
6684 +#define SSB_EUART (SB_EXTIF_BASE + 0x00800000)
6685 +#define SSB_LED (SB_EXTIF_BASE + 0x00900000)
6686 +
6687 +
6688 +/* Enumeration space constants */
6689 +#define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */
6690 +#define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
6691 +
6692 +
6693 +/* mips address */
6694 +#define SSB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6695 +
6696 +
6697 +/* SSB PCI config space registers. */
6698 +#define SSB_PMCSR 0x44
6699 +#define SSB_PE 0x100
6700 +#define SSB_BAR0_WIN 0x80 /* Backplane address space 0 */
6701 +#define SSB_BAR1_WIN 0x84 /* Backplane address space 1 */
6702 +#define SSB_SPROMCTL 0x88 /* SPROM control */
6703 +#define SSB_SPROMCTL_WE 0x10 /* SPROM write enable */
6704 +#define SSB_BAR1_CONTROL 0x8c /* Address space 1 burst control */
6705 +#define SSB_PCI_IRQS 0x90 /* PCI interrupts */
6706 +#define SSB_PCI_IRQMASK 0x94 /* PCI IRQ control and mask (pcirev >= 6 only) */
6707 +#define SSB_BACKPLANE_IRQS 0x98 /* Backplane Interrupts */
6708 +#define SSB_GPIO_IN 0xB0 /* GPIO Input (pcirev >= 3 only) */
6709 +#define SSB_GPIO_OUT 0xB4 /* GPIO Output (pcirev >= 3 only) */
6710 +#define SSB_GPIO_OUT_ENABLE 0xB8 /* GPIO Output Enable/Disable (pcirev >= 3 only) */
6711 +#define SSB_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
6712 +#define SSB_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
6713 +#define SSB_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
6714 +#define SSB_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
6715 +
6716 +
6717 +#define SSB_BAR0_MAX_RETRIES 50
6718 +
6719 +/* Silicon backplane configuration register definitions */
6720 +#define SSB_IPSFLAG 0x0F08
6721 +#define SSB_IPSFLAG_IRQ1 0x0000003F /* which sbflags get routed to mips interrupt 1 */
6722 +#define SSB_IPSFLAG_IRQ1_SHIFT 0
6723 +#define SSB_IPSFLAG_IRQ2 0x00003F00 /* which sbflags get routed to mips interrupt 2 */
6724 +#define SSB_IPSFLAG_IRQ2_SHIFT 8
6725 +#define SSB_IPSFLAG_IRQ3 0x003F0000 /* which sbflags get routed to mips interrupt 3 */
6726 +#define SSB_IPSFLAG_IRQ3_SHIFT 16
6727 +#define SSB_IPSFLAG_IRQ4 0x3F000000 /* which sbflags get routed to mips interrupt 4 */
6728 +#define SSB_IPSFLAG_IRQ4_SHIFT 24
6729 +#define SSB_TPSFLAG 0x0F18
6730 +#define SSB_TPSFLAG_BPFLAG 0x0000003F /* Backplane flag # */
6731 +#define SSB_TPSFLAG_ALWAYSIRQ 0x00000040 /* IRQ is always sent on the Backplane */
6732 +#define SSB_TMERRLOGA 0x0F48
6733 +#define SSB_TMERRLOG 0x0F50
6734 +#define SSB_ADMATCH3 0x0F60
6735 +#define SSB_ADMATCH2 0x0F68
6736 +#define SSB_ADMATCH1 0x0F70
6737 +#define SSB_IMSTATE 0x0F90 /* SB Initiator Agent State */
6738 +#define SSB_IMSTATE_PC 0x0000000f /* Pipe Count */
6739 +#define SSB_IMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */
6740 +#define SSB_IMSTATE_AP_BOTH 0x00000000 /* Use both timeslices and token */
6741 +#define SSB_IMSTATE_AP_TS 0x00000010 /* Use timeslices only */
6742 +#define SSB_IMSTATE_AP_TK 0x00000020 /* Use token only */
6743 +#define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
6744 +#define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
6745 +#define SSB_IMSTATE_TO 0x00040000 /* Timeout */
6746 +#define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
6747 +#define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
6748 +#define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
6749 +#define SSB_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */
6750 +#define SSB_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */
6751 +#define SSB_INTVEC_USB 0x00000010 /* Enable interrupts for usb */
6752 +#define SSB_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */
6753 +#define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
6754 +#define SSB_TMSLOW 0x0F98 /* SB Target State Low */
6755 +#define SSB_TMSLOW_RESET 0x00000001 /* Reset */
6756 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject */
6757 +#define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
6758 +#define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
6759 +#define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */
6760 +#define SSB_TMSLOW_BE 0x80000000 /* BIST Enable */
6761 +#define SSB_TMSHIGH 0x0F9C /* SB Target State High */
6762 +#define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
6763 +#define SSB_TMSHIGH_INT 0x00000002 /* Interrupt */
6764 +#define SSB_TMSHIGH_BUSY 0x00000004 /* Busy */
6765 +#define SSB_TMSHIGH_TO 0x00000020 /* Timeout. Backplane rev >= 2.3 only */
6766 +#define SSB_TMSHIGH_COREFL 0x1FFF0000 /* Core specific flags */
6767 +#define SSB_TMSHIGH_COREFL_SHIFT 16
6768 +#define SSB_TMSHIGH_DMA64 0x10000000 /* 64bit DMA supported */
6769 +#define SSB_TMSHIGH_GCR 0x20000000 /* Gated Clock Request */
6770 +#define SSB_TMSHIGH_BISTF 0x40000000 /* BIST Failed */
6771 +#define SSB_TMSHIGH_BISTD 0x80000000 /* BIST Done */
6772 +#define SSB_BWA0 0x0FA0
6773 +#define SSB_IMCFGLO 0x0FA8
6774 +#define SSB_IMCFGLO_SERTO 0x00000007 /* Service timeout */
6775 +#define SSB_IMCFGLO_REQTO 0x00000070 /* Request timeout */
6776 +#define SSB_IMCFGLO_REQTO_SHIFT 4
6777 +#define SSB_IMCFGLO_CONNID 0x00FF0000 /* Connection ID */
6778 +#define SSB_IMCFGLO_CONNID_SHIFT 16
6779 +#define SSB_IMCFGHI 0x0FAC
6780 +#define SSB_ADMATCH0 0x0FB0
6781 +#define SSB_TMCFGLO 0x0FB8
6782 +#define SSB_TMCFGHI 0x0FBC
6783 +#define SSB_BCONFIG 0x0FC0
6784 +#define SSB_BSTATE 0x0FC8
6785 +#define SSB_ACTCFG 0x0FD8
6786 +#define SSB_FLAGST 0x0FE8
6787 +#define SSB_IDLOW 0x0FF8
6788 +#define SSB_IDLOW_CFGSP 0x00000003 /* Config Space */
6789 +#define SSB_IDLOW_ADDRNGE 0x00000038 /* Address Ranges supported */
6790 +#define SSB_IDLOW_ADDRNGE_SHIFT 3
6791 +#define SSB_IDLOW_SYNC 0x00000040
6792 +#define SSB_IDLOW_INITIATOR 0x00000080
6793 +#define SSB_IDLOW_MIBL 0x00000F00 /* Minimum Backplane latency */
6794 +#define SSB_IDLOW_MIBL_SHIFT 8
6795 +#define SSB_IDLOW_MABL 0x0000F000 /* Maximum Backplane latency */
6796 +#define SSB_IDLOW_MABL_SHIFT 12
6797 +#define SSB_IDLOW_TIF 0x00010000 /* This Initiator is first */
6798 +#define SSB_IDLOW_CCW 0x000C0000 /* Cycle counter width */
6799 +#define SSB_IDLOW_CCW_SHIFT 18
6800 +#define SSB_IDLOW_TPT 0x00F00000 /* Target ports */
6801 +#define SSB_IDLOW_TPT_SHIFT 20
6802 +#define SSB_IDLOW_INITP 0x0F000000 /* Initiator ports */
6803 +#define SSB_IDLOW_INITP_SHIFT 24
6804 +#define SSB_IDLOW_SSBREV 0xF0000000 /* Sonics Backplane Revision code */
6805 +#define SSB_IDLOW_SSBREV_22 0x00000000 /* <= 2.2 */
6806 +#define SSB_IDLOW_SSBREV_23 0x10000000 /* 2.3 */
6807 +#define SSB_IDHIGH 0x0FFC /* SB Identification High */
6808 +#define SSB_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */
6809 +#define SSB_IDHIGH_CC 0x00008FF0 /* Core Code */
6810 +#define SSB_IDHIGH_CC_SHIFT 4
6811 +#define SSB_IDHIGH_RCHI 0x00007000 /* Revision Code (high part) */
6812 +#define SSB_IDHIGH_RCHI_SHIFT 8 /* yes, shift 8 is right */
6813 +#define SSB_IDHIGH_VC 0xFFFF0000 /* Vendor Code */
6814 +#define SSB_IDHIGH_VC_SHIFT 16
6815 +
6816 +/* SPROM shadow area. If not otherwise noted, fields are
6817 + * two bytes wide. Note that the SPROM can _only_ be read
6818 + * in two-byte quantinies.
6819 + */
6820 +#define SSB_SPROMSIZE_WORDS 64
6821 +#define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
6822 +#define SSB_SPROM_BASE 0x1000
6823 +#define SSB_SPROM_REVISION 0x107E
6824 +#define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
6825 +#define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
6826 +#define SSB_SPROM_REVISION_CRC_SHIFT 8
6827 +/* SPROM Revision 1 */
6828 +#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
6829 +#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
6830 +#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
6831 +#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
6832 +#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
6833 +#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
6834 +#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
6835 +#define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
6836 +#define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
6837 +#define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
6838 +#define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
6839 +#define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
6840 +#define SSB_SPROM1_BINF 0x105C /* Board info */
6841 +#define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
6842 +#define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
6843 +#define SSB_SPROM1_BINF_CCODE_SHIFT 8
6844 +#define SSB_SPROM1_BINF_ANTA 0x3000 /* Available A-PHY antennas */
6845 +#define SSB_SPROM1_BINF_ANTA_SHIFT 12
6846 +#define SSB_SPROM1_BINF_ANTBG 0xC000 /* Available B-PHY antennas */
6847 +#define SSB_SPROM1_BINF_ANTBG_SHIFT 14
6848 +#define SSB_SPROM1_PA0B0 0x105E
6849 +#define SSB_SPROM1_PA0B1 0x1060
6850 +#define SSB_SPROM1_PA0B2 0x1062
6851 +#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
6852 +#define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
6853 +#define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
6854 +#define SSB_SPROM1_GPIOA_P1_SHIFT 8
6855 +#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
6856 +#define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
6857 +#define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
6858 +#define SSB_SPROM1_GPIOB_P3_SHIFT 8
6859 +#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
6860 +#define SSB_SPROM1_MAXPWR_A 0x00FF /* A-PHY (in dBm Q5.2) */
6861 +#define SSB_SPROM1_MAXPWR_BG 0xFF00 /* B-PHY and G-PHY (in dBm Q5.2) */
6862 +#define SSB_SPROM1_MAXPWR_BG_SHIFT 8
6863 +#define SSB_SPROM1_PA1B0 0x106A
6864 +#define SSB_SPROM1_PA1B1 0x106C
6865 +#define SSB_SPROM1_PA1B2 0x106E
6866 +#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
6867 +#define SSB_SPROM1_ITSSI_A 0x00FF /* A-PHY */
6868 +#define SSB_SPROM1_ITSSI_BG 0xFF00 /* B-PHY and G-PHY */
6869 +#define SSB_SPROM1_ITSSI_BG_SHIFT 8
6870 +#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
6871 +#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
6872 +#define SSB_SPROM1_AGAIN_A 0x00FF /* A-PHY */
6873 +#define SSB_SPROM1_AGAIN_BG 0xFF00 /* B-PHY and G-PHY */
6874 +#define SSB_SPROM1_AGAIN_BG_SHIFT 8
6875 +#define SSB_SPROM1_OEM 0x1076 /* 8 bytes OEM string (rev 1 only) */
6876 +/* SPROM Revision 2 (inherits from rev 1) */
6877 +#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
6878 +#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
6879 +#define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
6880 +#define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
6881 +#define SSB_SPROM2_MAXP_A_LO_SHIFT 8
6882 +#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
6883 +#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
6884 +#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
6885 +#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
6886 +#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
6887 +#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
6888 +#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
6889 +#define SSB_SPROM2_OPO_VALUE 0x00FF
6890 +#define SSB_SPROM2_OPO_UNUSED 0xFF00
6891 +#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
6892 +/* SPROM Revision 3 (inherits from rev 2) */
6893 +#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
6894 +#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
6895 +#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
6896 +#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
6897 +#define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
6898 +#define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
6899 +#define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
6900 +#define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
6901 +#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
6902 +#define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
6903 +#define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
6904 +#define SSB_SPROM3_CCKPO_2M_SHIFT 4
6905 +#define SSB_SPROM3_CCKPO_55M 0x0F00 /* 5.5M Rate PO */
6906 +#define SSB_SPROM3_CCKPO_55M_SHIFT 8
6907 +#define SSB_SPROM3_CCKPO_11M 0xF000 /* 11M Rate PO */
6908 +#define SSB_SPROM3_CCKPO_11M_SHIFT 12
6909 +#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
6910 +
6911 +/* Values for SSB_SPROM1_BINF_CCODE */
6912 +enum {
6913 + SSB_SPROM1CCODE_WORLD = 0,
6914 + SSB_SPROM1CCODE_THAILAND,
6915 + SSB_SPROM1CCODE_ISRAEL,
6916 + SSB_SPROM1CCODE_JORDAN,
6917 + SSB_SPROM1CCODE_CHINA,
6918 + SSB_SPROM1CCODE_JAPAN,
6919 + SSB_SPROM1CCODE_USA_CANADA_ANZ,
6920 + SSB_SPROM1CCODE_EUROPE,
6921 + SSB_SPROM1CCODE_USA_LOW,
6922 + SSB_SPROM1CCODE_JAPAN_HIGH,
6923 + SSB_SPROM1CCODE_ALL,
6924 + SSB_SPROM1CCODE_NONE,
6925 +};
6926 +
6927 +/* Address-Match values and masks (SSB_ADMATCH?) */
6928 +#define SSB_ADM_TYPE 0x00000003 /* Address type */
6929 +#define SSB_ADM_TYPE0 0
6930 +#define SSB_ADM_TYPE1 1
6931 +#define SSB_ADM_TYPE2 2
6932 +#define SSB_ADM_AD64 0x00000004
6933 +#define SSB_ADM_SZ0 0x000000F8 /* Type0 size */
6934 +#define SSB_ADM_SZ0_SHIFT 3
6935 +#define SSB_ADM_SZ1 0x000001F8 /* Type1 size */
6936 +#define SSB_ADM_SZ1_SHIFT 3
6937 +#define SSB_ADM_SZ2 0x000001F8 /* Type2 size */
6938 +#define SSB_ADM_SZ2_SHIFT 3
6939 +#define SSB_ADM_EN 0x00000400 /* Enable */
6940 +#define SSB_ADM_NEG 0x00000800 /* Negative decode */
6941 +#define SSB_ADM_BASE0 0xFFFFFF00 /* Type0 base address */
6942 +#define SSB_ADM_BASE0_SHIFT 8
6943 +#define SSB_ADM_BASE1 0xFFFFF000 /* Type1 base address for the core */
6944 +#define SSB_ADM_BASE1_SHIFT 12
6945 +#define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */
6946 +#define SSB_ADM_BASE2_SHIFT 16
6947 +
6948 +
6949 +#endif /* __KERNEL__ */
6950 +#endif /* LINUX_SSB_REGS_H_ */
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