ec595342c0e68cc5d323ccf8d532793af3817c09
[openwrt/svn-archive/archive.git] / target / linux / brcm47xx / patches-3.10 / 090-MIPS-BCM47XX-fix-clock-detection-for-BCM5354-with-20.patch
1 commit 0388a0410d590a6c239c1cfaa7d49bffd4ed1101
2 Author: Hauke Mehrtens <hauke@hauke-m.de>
3 Date: Wed Sep 18 13:32:59 2013 +0200
4
5 MIPS: BCM47XX: Fix clock detection for BCM5354 with 200MHz clock
6
7 Some BCM5354 SoCs are running at 200MHz, but it is not possible to read
8 the clock from a register like it is done on some other SoC in ssb and
9 bcma. These devices should have a clkfreq nvram configuration value set
10 to 200, read it and set the clock to the correct value.
11
12 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
13 Cc: linux-mips@linux-mips.org
14 Patchwork: https://patchwork.linux-mips.org/patch/5842/
15 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
16
17 --- a/arch/mips/bcm47xx/time.c
18 +++ b/arch/mips/bcm47xx/time.c
19 @@ -27,10 +27,14 @@
20 #include <linux/ssb/ssb.h>
21 #include <asm/time.h>
22 #include <bcm47xx.h>
23 +#include <bcm47xx_nvram.h>
24
25 void __init plat_time_init(void)
26 {
27 unsigned long hz = 0;
28 + u16 chip_id = 0;
29 + char buf[10];
30 + int len;
31
32 /*
33 * Use deterministic values for initial counter interrupt
34 @@ -43,15 +47,23 @@ void __init plat_time_init(void)
35 #ifdef CONFIG_BCM47XX_SSB
36 case BCM47XX_BUS_TYPE_SSB:
37 hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
38 + chip_id = bcm47xx_bus.ssb.chip_id;
39 break;
40 #endif
41 #ifdef CONFIG_BCM47XX_BCMA
42 case BCM47XX_BUS_TYPE_BCMA:
43 hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
44 + chip_id = bcm47xx_bus.bcma.bus.chipinfo.id;
45 break;
46 #endif
47 }
48
49 + if (chip_id == 0x5354) {
50 + len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf));
51 + if (len >= 0 && !strncmp(buf, "200", 4))
52 + hz = 100000000;
53 + }
54 +
55 if (!hz)
56 hz = 100000000;
57