brcm47xx: add support for pcie host controller on bcma based SoCs.
[openwrt/svn-archive/archive.git] / target / linux / brcm47xx / patches-3.2 / 0043-bcma-add-extra-sprom-check.patch
1 From 1cd3d0de72e42161fe0df355c5429459265aeef0 Mon Sep 17 00:00:00 2001
2 From: Hauke Mehrtens <hauke@hauke-m.de>
3 Date: Sat, 14 Jan 2012 16:11:17 +0100
4 Subject: [PATCH 30/32] bcma: add extra sprom check
5
6 This check is needed on the BCM43224 device as it says in the
7 capabilities it has an sprom but is extra check says it has not.
8
9 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
10 ---
11 drivers/bcma/sprom.c | 8 ++++++++
12 include/linux/bcma/bcma_driver_chipcommon.h | 16 ++++++++++++++++
13 2 files changed, 24 insertions(+), 0 deletions(-)
14
15 --- a/drivers/bcma/sprom.c
16 +++ b/drivers/bcma/sprom.c
17 @@ -210,6 +210,7 @@ int bcma_sprom_get(struct bcma_bus *bus)
18 {
19 u16 offset;
20 u16 *sprom;
21 + u32 sromctrl;
22 int err = 0;
23
24 if (!bus->drv_cc.core)
25 @@ -220,6 +221,13 @@ int bcma_sprom_get(struct bcma_bus *bus)
26 return -ENOENT;
27 }
28
29 + if (bus->drv_cc.core->id.rev >= 32) {
30 + sromctrl = bcma_read32(bus->drv_cc.core, BCMA_CC_SROM_CONTROL);
31 + if (!(sromctrl & BCMA_CC_SROM_CONTROL_PRESENT))
32 + random_ether_addr(bus->sprom.il0mac);
33 + return -ENOENT;
34 + }
35 +
36 sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
37 GFP_KERNEL);
38 if (!sprom)
39 --- a/include/linux/bcma/bcma_driver_chipcommon.h
40 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
41 @@ -239,6 +239,22 @@
42 #define BCMA_CC_FLASH_CFG 0x0128
43 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
44 #define BCMA_CC_FLASH_WAITCNT 0x012C
45 +#define BCMA_CC_SROM_CONTROL 0x0190
46 +#define BCMA_CC_SROM_CONTROL_START 0x80000000
47 +#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
48 +#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
49 +#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
50 +#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
51 +#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
52 +#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
53 +#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
54 +#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
55 +#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
56 +#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
57 +#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
58 +#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
59 +#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
60 +#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
61 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
62 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
63 #define BCMA_CC_UART0_DATA 0x0300