target/linux/brcm47xx/patches-3.3/700-ssb-gigabit-ethernet-driver.patch

   1 --- a/drivers/net/ethernet/broadcom/tg3.c
   2 +++ b/drivers/net/ethernet/broadcom/tg3.c
   3 @@ -44,6 +44,7 @@
   4  #include <linux/prefetch.h>
   5  #include <linux/dma-mapping.h>
   6  #include <linux/firmware.h>
   7 +#include <linux/ssb/ssb_driver_gige.h>
   8
   9  #include <net/checksum.h>
  10  #include <net/ip.h>
  11 @@ -249,6 +250,7 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_t
  12         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
  13         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
  14         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
  15 +       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
  16         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
  17         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
  18         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
  19 @@ -530,7 +532,8 @@ static void _tw32_flush(struct tg3 *tp,
  20  static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  21  {
  22         tp->write32_mbox(tp, off, val);
  23 -       if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
  24 +       if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
  25 +           (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)))
  26                 tp->read32_mbox(tp, off);
  27  }
  28
  29 @@ -540,7 +543,7 @@ static void tg3_write32_tx_mbox(struct t
  30         writel(val, mbox);
  31         if (tg3_flag(tp, TXD_MBOX_HWBUG))
  32                 writel(val, mbox);
  33 -       if (tg3_flag(tp, MBOX_WRITE_REORDER))
  34 +       if (tg3_flag(tp, MBOX_WRITE_REORDER) || tg3_flag(tp, FLUSH_POSTED_WRITES))
  35                 readl(mbox);
  36  }
  37
  38 @@ -943,7 +946,7 @@ static void tg3_switch_clocks(struct tg3
  39
  40  #define PHY_BUSY_LOOPS 5000
  41
  42 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  43 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
  44  {
  45         u32 frame_val;
  46         unsigned int loops;
  47 @@ -957,7 +960,7 @@ static int tg3_readphy(struct tg3 *tp, i
  48
  49         *val = 0x0;
  50
  51 -       frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  52 +       frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  53                       MI_COM_PHY_ADDR_MASK);
  54         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  55                       MI_COM_REG_ADDR_MASK);
  56 @@ -992,7 +995,12 @@ static int tg3_readphy(struct tg3 *tp, i
  57         return ret;
  58  }
  59
  60 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  61 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  62 +{
  63 +       return __tg3_readphy(tp, tp->phy_addr, reg, val);
  64 +}
  65 +
  66 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
  67  {
  68         u32 frame_val;
  69         unsigned int loops;
  70 @@ -1008,7 +1016,7 @@ static int tg3_writephy(struct tg3 *tp,
  71                 udelay(80);
  72         }
  73
  74 -       frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  75 +       frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  76                       MI_COM_PHY_ADDR_MASK);
  77         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  78                       MI_COM_REG_ADDR_MASK);
  79 @@ -1041,6 +1049,11 @@ static int tg3_writephy(struct tg3 *tp,
  80         return ret;
  81  }
  82
  83 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  84 +{
  85 +       return __tg3_writephy(tp, tp->phy_addr, reg, val);
  86 +}
  87 +
  88  static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
  89  {
  90         int err;
  91 @@ -1603,6 +1616,11 @@ static int tg3_poll_fw(struct tg3 *tp)
  92         int i;
  93         u32 val;
  94
  95 +       if (tg3_flag(tp, IS_SSB_CORE)) {
  96 +               /* We don't use firmware. */
  97 +               return 0;
  98 +       }
  99 +
 100         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 101                 /* Wait up to 20ms for init done. */
 102                 for (i = 0; i < 200; i++) {
 103 @@ -3024,9 +3042,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
 104                 return -ENODEV;
 105         }
 106
 107 -       /* Clear firmware's nvram arbitration. */
 108 -       if (tg3_flag(tp, NVRAM))
 109 -               tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
 110 +       if (!tg3_flag(tp, IS_SSB_CORE)) {
 111 +               /* Clear firmware's nvram arbitration. */
 112 +               if (tg3_flag(tp, NVRAM))
 113 +                       tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
 114 +       }
 115 +
 116         return 0;
 117  }
 118
 119 @@ -3089,6 +3110,11 @@ static int tg3_load_5701_a0_firmware_fix
 120         const __be32 *fw_data;
 121         int err, i;
 122
 123 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 124 +               /* We don't use firmware. */
 125 +               return 0;
 126 +       }
 127 +
 128         fw_data = (void *)tp->fw->data;
 129
 130         /* Firmware blob starts with version numbers, followed by
 131 @@ -3145,6 +3171,11 @@ static int tg3_load_tso_firmware(struct
 132         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
 133         int err, i;
 134
 135 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 136 +               /* We don't use firmware. */
 137 +               return 0;
 138 +       }
 139 +
 140         if (tg3_flag(tp, HW_TSO_1) ||
 141             tg3_flag(tp, HW_TSO_2) ||
 142             tg3_flag(tp, HW_TSO_3))
 143 @@ -3491,8 +3522,11 @@ static int tg3_power_down_prepare(struct
 144         tg3_frob_aux_power(tp, true);
 145
 146         /* Workaround for unstable PLL clock */
 147 -       if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
 148 -           (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
 149 +       if ((tp->phy_id & TG3_PHY_ID_MASK) != TG3_PHY_ID_BCM5750_2 &&
 150 +           (tp->phy_id & TG3_PHY_ID_MASK) != TG3_PHY_ID_BCM5750_3 &&
 151 +                               /* !!! FIXME !!! */
 152 +           ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
 153 +           (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
 154                 u32 val = tr32(0x7d00);
 155
 156                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
 157 @@ -4006,6 +4040,14 @@ relink:
 158         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
 159                 tg3_phy_copper_begin(tp);
 160
 161 +               if (tg3_flag(tp, ROBOSWITCH)) {
 162 +                       current_link_up = 1;
 163 +                       current_speed = SPEED_1000; /* FIXME */
 164 +                       current_duplex = DUPLEX_FULL;
 165 +                       tp->link_config.active_speed = current_speed;
 166 +                       tp->link_config.active_duplex = current_duplex;
 167 +               }
 168 +
 169                 tg3_readphy(tp, MII_BMSR, &bmsr);
 170                 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
 171                     (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
 172 @@ -7819,6 +7861,14 @@ static int tg3_chip_reset(struct tg3 *tp
 173                 tw32(0x5000, 0x400);
 174         }
 175
 176 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 177 +               /* BCM4785: In order to avoid repercussions from using potentially
 178 +                * defective internal ROM, stop the Rx RISC CPU, which is not
 179 +                * required. */
 180 +               tg3_stop_fw(tp);
 181 +               tg3_halt_cpu(tp, RX_CPU_BASE);
 182 +       }
 183 +
 184         tw32(GRC_MODE, tp->grc_mode);
 185
 186         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
 187 @@ -9233,6 +9283,11 @@ static void tg3_timer(unsigned long __op
 188             tg3_flag(tp, 57765_CLASS))
 189                 tg3_chk_missed_msi(tp);
 190
 191 +       if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
 192 +               /* BCM4785: Flush posted writes from GbE to host memory. */
 193 +               tr32(HOSTCC_MODE);
 194 +       }
 195 +
 196         if (!tg3_flag(tp, TAGGED_STATUS)) {
 197                 /* All of this garbage is because when using non-tagged
 198                  * IRQ status the mailbox/status_block protocol the chip
 199 @@ -10945,6 +11000,11 @@ static int tg3_test_nvram(struct tg3 *tp
 200         if (tg3_flag(tp, NO_NVRAM))
 201                 return 0;
 202
 203 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 204 +               /* We don't have NVRAM. */
 205 +               return 0;
 206 +       }
 207 +
 208         if (tg3_nvram_read(tp, 0, &magic) != 0)
 209                 return -EIO;
 210
 211 @@ -11902,11 +11962,11 @@ static int tg3_ioctl(struct net_device *
 212                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
 213                         break;                  /* We have no PHY */
 214
 215 -               if (!netif_running(dev))
 216 +               if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
 217                         return -EAGAIN;
 218
 219                 spin_lock_bh(&tp->lock);
 220 -               err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
 221 +               err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
 222                 spin_unlock_bh(&tp->lock);
 223
 224                 data->val_out = mii_regval;
 225 @@ -11918,11 +11978,11 @@ static int tg3_ioctl(struct net_device *
 226                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
 227                         break;                  /* We have no PHY */
 228
 229 -               if (!netif_running(dev))
 230 +               if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
 231                         return -EAGAIN;
 232
 233                 spin_lock_bh(&tp->lock);
 234 -               err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
 235 +               err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
 236                 spin_unlock_bh(&tp->lock);
 237
 238                 return err;
 239 @@ -12656,6 +12716,13 @@ static void __devinit tg3_get_5720_nvram
 240  /* Chips other than 5700/5701 use the NVRAM for fetching info. */
 241  static void __devinit tg3_nvram_init(struct tg3 *tp)
 242  {
 243 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 244 +               /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
 245 +               tg3_flag_clear(tp, NVRAM);
 246 +               tg3_flag_clear(tp, NVRAM_BUFFERED);
 247 +               return;
 248 +       }
 249 +
 250         tw32_f(GRC_EEPROM_ADDR,
 251              (EEPROM_ADDR_FSM_RESET |
 252               (EEPROM_DEFAULT_CLOCK_PERIOD <<
 253 @@ -12922,6 +12989,9 @@ static int tg3_nvram_write_block(struct
 254  {
 255         int ret;
 256
 257 +       if (tg3_flag(tp, IS_SSB_CORE))
 258 +               return -ENODEV;
 259 +
 260         if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
 261                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
 262                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
 263 @@ -14368,6 +14438,11 @@ static int __devinit tg3_get_invariants(
 264                 }
 265         }
 266
 267 +       if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
 268 +               tp->write32_tx_mbox = tg3_write_flush_reg32;
 269 +               tp->write32_rx_mbox = tg3_write_flush_reg32;
 270 +       }
 271 +
 272         /* Get eeprom hw config before calling tg3_set_power_state().
 273          * In particular, the TG3_FLAG_IS_NIC flag must be
 274          * determined before calling tg3_set_power_state() so that
 275 @@ -14784,6 +14859,10 @@ static int __devinit tg3_get_device_addr
 276         }
 277
 278         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
 279 +               if (tg3_flag(tp, IS_SSB_CORE))
 280 +                       ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
 281 +       }
 282 +       if (!is_valid_ether_addr(&dev->dev_addr[0])) {
 283  #ifdef CONFIG_SPARC
 284                 if (!tg3_get_default_macaddr_sparc(tp))
 285                         return 0;
 286 @@ -15282,6 +15361,8 @@ static char * __devinit tg3_phy_string(s
 287         case TG3_PHY_ID_BCM5704:        return "5704";
 288         case TG3_PHY_ID_BCM5705:        return "5705";
 289         case TG3_PHY_ID_BCM5750:        return "5750";
 290 +       case TG3_PHY_ID_BCM5750_2:      return "5750-2";
 291 +       case TG3_PHY_ID_BCM5750_3:      return "5750-3";
 292         case TG3_PHY_ID_BCM5752:        return "5752";
 293         case TG3_PHY_ID_BCM5714:        return "5714";
 294         case TG3_PHY_ID_BCM5780:        return "5780";
 295 @@ -15492,6 +15573,13 @@ static int __devinit tg3_init_one(struct
 296                 tp->msg_enable = tg3_debug;
 297         else
 298                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
 299 +       if (pdev_is_ssb_gige_core(pdev)) {
 300 +               tg3_flag_set(tp, IS_SSB_CORE);
 301 +               if (ssb_gige_must_flush_posted_writes(pdev))
 302 +                       tg3_flag_set(tp, FLUSH_POSTED_WRITES);
 303 +               if (ssb_gige_have_roboswitch(pdev))
 304 +                       tg3_flag_set(tp, ROBOSWITCH);
 305 +       }
 306
 307         /* The word/byte swap controls here control register access byte
 308          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
 309 --- a/drivers/net/ethernet/broadcom/tg3.h
 310 +++ b/drivers/net/ethernet/broadcom/tg3.h
 311 @@ -2940,6 +2940,9 @@ enum TG3_FLAGS {
 312         TG3_FLAG_57765_PLUS,
 313         TG3_FLAG_57765_CLASS,
 314         TG3_FLAG_5717_PLUS,
 315 +       TG3_FLAG_IS_SSB_CORE,
 316 +       TG3_FLAG_FLUSH_POSTED_WRITES,
 317 +       TG3_FLAG_ROBOSWITCH,
 318
 319         /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
 320         TG3_FLAG_NUMBER_OF_FLAGS,       /* Last entry in enum TG3_FLAGS */
 321 @@ -3089,6 +3092,8 @@ struct tg3 {
 322  #define TG3_PHY_ID_BCM5704             0x60008190
 323  #define TG3_PHY_ID_BCM5705             0x600081a0
 324  #define TG3_PHY_ID_BCM5750             0x60008180
 325 +#define TG3_PHY_ID_BCM5750_2           0xbc050cd0
 326 +#define TG3_PHY_ID_BCM5750_3           0xbc050f80
 327  #define TG3_PHY_ID_BCM5752             0x60008100
 328  #define TG3_PHY_ID_BCM5714             0x60008340
 329  #define TG3_PHY_ID_BCM5780             0x60008350
 330 @@ -3126,7 +3131,8 @@ struct tg3 {
 331          (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
 332          (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
 333          (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
 334 -        (X) == TG3_PHY_ID_BCM8002)
 335 +        (X) == TG3_PHY_ID_BCM8002 || (X) == TG3_PHY_ID_BCM5750_2 || \
 336 +        (X) == TG3_PHY_ID_BCM5750_3)
 337
 338         u32                             phy_flags;
 339  #define TG3_PHYFLG_IS_LOW_POWER                0x00000001
 340 --- a/include/linux/ssb/ssb_driver_gige.h
 341 +++ b/include/linux/ssb/ssb_driver_gige.h
 342 @@ -97,21 +97,12 @@ static inline bool ssb_gige_must_flush_p
 343         return 0;
 344  }
 345
 346 -#ifdef CONFIG_BCM47XX
 347 -#include <asm/mach-bcm47xx/nvram.h>
 348 -/* Get the device MAC address */
 349 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
 350 -{
 351 -       char buf[20];
 352 -       if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
 353 -               return;
 354 -       nvram_parse_macaddr(buf, macaddr);
 355 -}
 356 -#else
 357  static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
 358  {
 359 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
 360 +
 361 +       memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
 362  }
 363 -#endif
 364
 365  extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
 366                                           struct pci_dev *pdev);
 367 @@ -175,6 +166,9 @@ static inline bool ssb_gige_must_flush_p
 368  {
 369         return 0;
 370  }
 371 +static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
 372 +{
 373 +}
 374
 375  #endif /* CONFIG_SSB_DRIVER_GIGE */
 376  #endif /* LINUX_SSB_DRIVER_GIGE_H_ */
 377 --- a/include/linux/pci_ids.h
 378 +++ b/include/linux/pci_ids.h
 379 @@ -2120,6 +2120,7 @@
 380  #define PCI_DEVICE_ID_TIGON3_5754M     0x1672
 381  #define PCI_DEVICE_ID_TIGON3_5755M     0x1673
 382  #define PCI_DEVICE_ID_TIGON3_5756      0x1674
 383 +#define PCI_DEVICE_ID_TIGON3_5750      0x1676
 384  #define PCI_DEVICE_ID_TIGON3_5751      0x1677
 385  #define PCI_DEVICE_ID_TIGON3_5715      0x1678
 386  #define PCI_DEVICE_ID_TIGON3_5715S     0x1679