target/linux/brcm63xx-2.6/files/arch/mips/bcm963xx/include/6338_map_part.h

   1 /*
   2 <:copyright-gpl
   3  Copyright 2004 Broadcom Corp. All Rights Reserved.
   4
   5  This program is free software; you can distribute it and/or modify it
   6  under the terms of the GNU General Public License (Version 2) as
   7  published by the Free Software Foundation.
   8
   9  This program is distributed in the hope it will be useful, but WITHOUT
  10  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  for more details.
  13
  14  You should have received a copy of the GNU General Public License along
  15  with this program; if not, write to the Free Software Foundation, Inc.,
  16  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17 :>
  18 */
  19
  20 #ifndef __BCM6338_MAP_H
  21 #define __BCM6338_MAP_H
  22
  23 #include "bcmtypes.h"
  24
  25 #define PERF_BASE           0xfffe0000
  26 #define TIMR_BASE           0xfffe0200
  27 #define UART_BASE           0xfffe0300
  28 #define GPIO_BASE           0xfffe0400
  29 #define SPI_BASE            0xfffe0c00
  30
  31 typedef struct PerfControl {
  32   uint32        RevID;
  33   uint16        testControl;
  34   uint16        blkEnables;
  35 #define EMAC_CLK_EN     0x0010
  36 #define USBS_CLK_EN     0x0010
  37 #define SAR_CLK_EN      0x0020
  38
  39 #define SPI_CLK_EN      0x0200
  40
  41   uint32        pll_control;
  42 #define SOFT_RESET 0x00000001
  43
  44   uint32        IrqMask;
  45   uint32        IrqStatus;
  46
  47   uint32        ExtIrqCfg;
  48 #define EI_SENSE_SHFT   0
  49 #define EI_STATUS_SHFT  5
  50 #define EI_CLEAR_SHFT   10
  51 #define EI_MASK_SHFT    15
  52 #define EI_INSENS_SHFT  20
  53 #define EI_LEVEL_SHFT   25
  54
  55   uint32        unused[4];      /* (18) */
  56   uint32        BlockSoftReset; /* (28) */
  57 #define BSR_SPI             0x00000001
  58 #define BSR_EMAC            0x00000004
  59 #define BSR_USBH            0x00000008
  60 #define BSR_USBS            0x00000010
  61 #define BSR_ADSL            0x00000020
  62 #define BSR_DMAMEM          0x00000040
  63 #define BSR_SAR             0x00000080
  64 #define BSR_ACLC            0x00000100
  65 #define BSR_ADSL_MIPS_PLL   0x00000400
  66 #define BSR_ALL_BLOCKS      \
  67     (BSR_SPI | BSR_EMAC | BSR_USBH | BSR_USBS | BSR_ADSL | BSR_DMAMEM | \
  68      BSR_SAR | BSR_ACLC | BSR_ADSL_MIPS_PLL)
  69 } PerfControl;
  70
  71 #define PERF ((volatile PerfControl * const) PERF_BASE)
  72
  73
  74 typedef struct Timer {
  75   uint16        unused0;
  76   byte          TimerMask;
  77 #define TIMER0EN        0x01
  78 #define TIMER1EN        0x02
  79 #define TIMER2EN        0x04
  80   byte          TimerInts;
  81 #define TIMER0          0x01
  82 #define TIMER1          0x02
  83 #define TIMER2          0x04
  84 #define WATCHDOG        0x08
  85   uint32        TimerCtl0;
  86   uint32        TimerCtl1;
  87   uint32        TimerCtl2;
  88 #define TIMERENABLE     0x80000000
  89 #define RSTCNTCLR       0x40000000
  90   uint32        TimerCnt0;
  91   uint32        TimerCnt1;
  92   uint32        TimerCnt2;
  93   uint32        WatchDogDefCount;
  94
  95   /* Write 0xff00 0x00ff to Start timer
  96    * Write 0xee00 0x00ee to Stop and re-load default count
  97    * Read from this register returns current watch dog count
  98    */
  99   uint32        WatchDogCtl;
 100
 101   /* Number of 40-MHz ticks for WD Reset pulse to last */
 102   uint32        WDResetCount;
 103 } Timer;
 104
 105 #define TIMER ((volatile Timer * const) TIMR_BASE)
 106 typedef struct UartChannel {
 107   byte          unused0;
 108   byte          control;
 109 #define BRGEN           0x80    /* Control register bit defs */
 110 #define TXEN            0x40
 111 #define RXEN            0x20
 112 #define LOOPBK          0x10
 113 #define TXPARITYEN      0x08
 114 #define TXPARITYEVEN    0x04
 115 #define RXPARITYEN      0x02
 116 #define RXPARITYEVEN    0x01
 117
 118   byte          config;
 119 #define XMITBREAK       0x40
 120 #define BITS5SYM        0x00
 121 #define BITS6SYM        0x10
 122 #define BITS7SYM        0x20
 123 #define BITS8SYM        0x30
 124 #define ONESTOP         0x07
 125 #define TWOSTOP         0x0f
 126   /* 4-LSBS represent STOP bits/char
 127    * in 1/8 bit-time intervals.  Zero
 128    * represents 1/8 stop bit interval.
 129    * Fifteen represents 2 stop bits.
 130    */
 131   byte          fifoctl;
 132 #define RSTTXFIFOS      0x80
 133 #define RSTRXFIFOS      0x40
 134   /* 5-bit TimeoutCnt is in low bits of this register.
 135    *  This count represents the number of characters
 136    *  idle times before setting receive Irq when below threshold
 137    */
 138   uint32        baudword;
 139   /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
 140    */
 141
 142   byte          txf_levl;       /* Read-only fifo depth */
 143   byte          rxf_levl;       /* Read-only fifo depth */
 144   byte          fifocfg;        /* Upper 4-bits are TxThresh, Lower are
 145                                  *      RxThreshold.  Irq can be asserted
 146                                  *      when rx fifo> thresh, txfifo<thresh
 147                                  */
 148   byte          prog_out;       /* Set value of DTR (Bit0), RTS (Bit1)
 149                                  *  if these bits are also enabled to GPIO_o
 150                                  */
 151 #define DTREN   0x01
 152 #define RTSEN   0x02
 153
 154   byte          unused1;
 155   byte          DeltaIPEdgeNoSense;     /* Low 4-bits, set corr bit to 1 to
 156                                          * detect irq on rising AND falling
 157                                          * edges for corresponding GPIO_i
 158                                          * if enabled (edge insensitive)
 159                                          */
 160   byte          DeltaIPConfig_Mask;     /* Upper 4 bits: 1 for posedge sense
 161                                          *      0 for negedge sense if
 162                                          *      not configured for edge
 163                                          *      insensitive (see above)
 164                                          * Lower 4 bits: Mask to enable change
 165                                          *  detection IRQ for corresponding
 166                                          *  GPIO_i
 167                                          */
 168   byte          DeltaIP_SyncIP;         /* Upper 4 bits show which bits
 169                                          *  have changed (may set IRQ).
 170                                          *  read automatically clears bit
 171                                          * Lower 4 bits are actual status
 172                                          */
 173
 174   uint16        intMask;                                /* Same Bit defs for Mask and status */
 175   uint16        intStatus;
 176 #define DELTAIP         0x0001
 177 #define TXUNDERR        0x0002
 178 #define TXOVFERR        0x0004
 179 #define TXFIFOTHOLD     0x0008
 180 #define TXREADLATCH     0x0010
 181 #define TXFIFOEMT       0x0020
 182 #define RXUNDERR        0x0040
 183 #define RXOVFERR        0x0080
 184 #define RXTIMEOUT       0x0100
 185 #define RXFIFOFULL      0x0200
 186 #define RXFIFOTHOLD     0x0400
 187 #define RXFIFONE        0x0800
 188 #define RXFRAMERR       0x1000
 189 #define RXPARERR        0x2000
 190 #define RXBRK           0x4000
 191
 192   uint16        unused2;
 193   uint16        Data;                   /* Write to TX, Read from RX */
 194                                         /* bits 11:8 are BRK,PAR,FRM errors */
 195
 196   uint32                unused3;
 197   uint32                unused4;
 198 } Uart;
 199
 200 #define UART ((volatile Uart * const) UART_BASE)
 201
 202 typedef struct GpioControl {
 203   uint32        unused0;
 204   uint32        GPIODir;      /* bits 7:0 */
 205   uint32        unused1;
 206   uint32        GPIOio;       /* bits 7:0 */
 207   uint32        LEDCtrl;
 208 #define         LED3_STROBE             0x08000000
 209 #define         LED2_STROBE             0x04000000
 210 #define         LED1_STROBE             0x02000000
 211 #define         LED0_STROBE             0x01000000
 212 #define         LED_TEST                0x00010000
 213 #define         LED3_DISABLE_LINK_ACT   0x00008000
 214 #define         LED2_DISABLE_LINK_ACT   0x00004000
 215 #define         LED1_DISABLE_LINK_ACT   0x00002000
 216 #define         LED0_DISABLE_LINK_ACT   0x00001000
 217 #define         LED_INTERVAL_SET_MASK   0x00000f00
 218 #define         LED_INTERVAL_SET_320MS  0x00000500
 219 #define         LED_INTERVAL_SET_160MS  0x00000400
 220 #define         LED_INTERVAL_SET_80MS   0x00000300
 221 #define         LED_INTERVAL_SET_40MS   0x00000200
 222 #define         LED_INTERVAL_SET_20MS   0x00000100
 223 #define         LED3_ON                 0x00000080
 224 #define         LED2_ON                 0x00000040
 225 #define         LED1_ON                 0x00000020
 226 #define         LED0_ON                 0x00000010
 227 #define         LED3_ENABLE             0x00000008
 228 #define         LED2_ENABLE             0x00000004
 229 #define         LED1_ENABLE             0x00000002
 230 #define         LED0_ENABLE             0x00000001
 231   uint32        SpiSlaveCfg;
 232 #define         SPI_SLAVE_RESET         0x00010000
 233 #define         SPI_RESTRICT            0x00000400
 234 #define         SPI_DELAY_DISABLE       0x00000200
 235 #define         SPI_PROBE_MUX_SEL_MASK  0x000001e0
 236 #define         SPI_SER_ADDR_CFG_MASK   0x0000000c
 237 #define         SPI_MODE                0x00000001
 238   uint32        vRegConfig;
 239 } GpioControl;
 240
 241 #define GPIO ((volatile GpioControl * const) GPIO_BASE)
 242
 243 /* Number to mask conversion macro used for GPIODir and GPIOio */
 244 #define GPIO_NUM_MAX_BITS_MASK          0x0f
 245 #define GPIO_NUM_TO_MASK(X)             (1 << ((X) & GPIO_NUM_MAX_BITS_MASK))
 246
 247 /*
 248 ** Spi Controller
 249 */
 250
 251 typedef struct SpiControl {
 252   uint16        spiCmd;                 /* (0x0): SPI command */
 253 #define SPI_CMD_START_IMMEDIATE         3
 254
 255 #define SPI_CMD_COMMAND_SHIFT           0
 256 #define SPI_CMD_DEVICE_ID_SHIFT         4
 257 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
 258
 259   byte          spiIntStatus;           /* (0x2): SPI interrupt status */
 260   byte          spiMaskIntStatus;       /* (0x3): SPI masked interrupt status */
 261
 262   byte          spiIntMask;             /* (0x4): SPI interrupt mask */
 263 #define SPI_INTR_CMD_DONE               0x01
 264 #define SPI_INTR_CLEAR_ALL              0x1f
 265
 266   byte          spiStatus;              /* (0x5): SPI status */
 267
 268   byte          spiClkCfg;              /* (0x6): SPI clock configuration */
 269
 270   byte          spiFillByte;            /* (0x7): SPI fill byte */
 271
 272   byte          unused0;
 273   byte          spiMsgTail;             /* (0x9): msgtail */
 274   byte          unused1;
 275   byte          spiRxTail;              /* (0xB): rxtail */
 276
 277   uint32        unused2[13];            /* (0x0c - 0x3c) reserved */
 278
 279   byte          spiMsgCtl;              /* (0x40) control byte */
 280 #define HALF_DUPLEX_W                   1
 281 #define HALF_DUPLEX_R                   2
 282 #define SPI_MSG_TYPE_SHIFT              6
 283 #define SPI_BYTE_CNT_SHIFT              0
 284   byte          spiMsgData[63];         /* (0x41 - 0x7f) msg data */
 285   byte          spiRxDataFifo[64];      /* (0x80 - 0xbf) rx data */
 286   byte          unused3[64];            /* (0xc0 - 0xff) reserved */
 287 } SpiControl;
 288
 289 #define SPI ((volatile SpiControl * const) SPI_BASE)
 290
 291 /*
 292 ** External Bus Interface
 293 */
 294 typedef struct EbiChipSelect {
 295   uint32        base;                   /* base address in upper 24 bits */
 296 #define EBI_SIZE_8K         0
 297 #define EBI_SIZE_16K        1
 298 #define EBI_SIZE_32K        2
 299 #define EBI_SIZE_64K        3
 300 #define EBI_SIZE_128K       4
 301 #define EBI_SIZE_256K       5
 302 #define EBI_SIZE_512K       6
 303 #define EBI_SIZE_1M         7
 304 #define EBI_SIZE_2M         8
 305 #define EBI_SIZE_4M         9
 306 #define EBI_SIZE_8M         10
 307 #define EBI_SIZE_16M        11
 308 #define EBI_SIZE_32M        12
 309 #define EBI_SIZE_64M        13
 310 #define EBI_SIZE_128M       14
 311 #define EBI_SIZE_256M       15
 312   uint32        config;
 313 #define EBI_ENABLE          0x00000001      /* .. enable this range */
 314 #define EBI_WAIT_STATES     0x0000000e      /* .. mask for wait states */
 315 #define EBI_WTST_SHIFT      1               /* .. for shifting wait states */
 316 #define EBI_WORD_WIDE       0x00000010      /* .. 16-bit peripheral, else 8 */
 317 #define EBI_WREN            0x00000020      /* enable posted writes */
 318 #define EBI_POLARITY        0x00000040      /* .. set to invert something,
 319                                         **    don't know what yet */
 320 #define EBI_TS_TA_MODE      0x00000080      /* .. use TS/TA mode */
 321 #define EBI_TS_SEL          0x00000100      /* .. drive tsize, not bs_b */
 322 #define EBI_FIFO            0x00000200      /* .. use fifo */
 323 #define EBI_RE              0x00000400      /* .. Reverse Endian */
 324 } EbiChipSelect;
 325
 326 typedef struct MpiRegisters {
 327   EbiChipSelect cs[1];                  /* size chip select configuration */
 328 } MpiRegisters;
 329
 330 #define MPI ((volatile MpiRegisters * const) MPI_BASE)
 331
 332
 333 #endif
 334